1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10 #ifndef MPI3MR_H_INCLUDED 11 #define MPI3MR_H_INCLUDED 12 13 #include <linux/blkdev.h> 14 #include <linux/blk-mq.h> 15 #include <linux/blk-mq-pci.h> 16 #include <linux/delay.h> 17 #include <linux/dmapool.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/miscdevice.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/aer.h> 27 #include <linux/poll.h> 28 #include <linux/sched.h> 29 #include <linux/slab.h> 30 #include <linux/types.h> 31 #include <linux/uaccess.h> 32 #include <linux/utsname.h> 33 #include <linux/workqueue.h> 34 #include <linux/unaligned.h> 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_dbg.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 #include <scsi/scsi_tcq.h> 41 #include <uapi/scsi/scsi_bsg_mpi3mr.h> 42 #include <scsi/scsi_transport_sas.h> 43 44 #include "mpi/mpi30_transport.h" 45 #include "mpi/mpi30_cnfg.h" 46 #include "mpi/mpi30_image.h" 47 #include "mpi/mpi30_init.h" 48 #include "mpi/mpi30_ioc.h" 49 #include "mpi/mpi30_sas.h" 50 #include "mpi/mpi30_pci.h" 51 #include "mpi/mpi30_tool.h" 52 #include "mpi3mr_debug.h" 53 54 /* Global list and lock for storing multiple adapters managed by the driver */ 55 extern spinlock_t mrioc_list_lock; 56 extern struct list_head mrioc_list; 57 extern int prot_mask; 58 extern atomic64_t event_counter; 59 60 #define MPI3MR_DRIVER_VERSION "8.12.0.0.50" 61 #define MPI3MR_DRIVER_RELDATE "05-Sept-2024" 62 63 #define MPI3MR_DRIVER_NAME "mpi3mr" 64 #define MPI3MR_DRIVER_LICENSE "GPL" 65 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 66 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 67 68 #define MPI3MR_NAME_LENGTH 64 69 #define IOCNAME "%s: " 70 71 #define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024) 72 73 /* Definitions for internal SGL and Chain SGL buffers */ 74 #define MPI3MR_PAGE_SIZE_4K 4096 75 #define MPI3MR_DEFAULT_SGL_ENTRIES 256 76 #define MPI3MR_MAX_SGL_ENTRIES 2048 77 78 /* Definitions for MAX values for shost */ 79 #define MPI3MR_MAX_CMDS_LUN 128 80 #define MPI3MR_MAX_CDB_LENGTH 32 81 82 /* Admin queue management definitions */ 83 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 84 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 85 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128 86 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 87 88 /* Operational queue management definitions */ 89 #define MPI3MR_OP_REQ_Q_QD 512 90 #define MPI3MR_OP_REP_Q_QD 1024 91 #define MPI3MR_OP_REP_Q_QD4K 4096 92 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 93 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096 94 #define MPI3MR_MAX_SEG_LIST_SIZE 4096 95 96 /* Reserved Host Tag definitions */ 97 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 98 #define MPI3MR_HOSTTAG_INITCMDS 1 99 #define MPI3MR_HOSTTAG_BSG_CMDS 2 100 #define MPI3MR_HOSTTAG_PEL_ABORT 3 101 #define MPI3MR_HOSTTAG_PEL_WAIT 4 102 #define MPI3MR_HOSTTAG_BLK_TMS 5 103 #define MPI3MR_HOSTTAG_CFG_CMDS 6 104 #define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7 105 106 #define MPI3MR_NUM_DEVRMCMD 16 107 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1) 108 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 109 MPI3MR_NUM_DEVRMCMD - 1) 110 111 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 112 #define MPI3MR_NUM_EVTACKCMD 4 113 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 114 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 115 MPI3MR_NUM_EVTACKCMD - 1) 116 117 /* Reduced resource count definition for crash kernel */ 118 #define MPI3MR_HOST_IOS_KDUMP 128 119 120 /* command/controller interaction timeout definitions in seconds */ 121 #define MPI3MR_INTADMCMD_TIMEOUT 60 122 #define MPI3MR_PORTENABLE_TIMEOUT 300 123 #define MPI3MR_PORTENABLE_POLL_INTERVAL 5 124 #define MPI3MR_ABORTTM_TIMEOUT 60 125 #define MPI3MR_RESETTM_TIMEOUT 60 126 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 127 #define MPI3MR_TSUPDATE_INTERVAL 900 128 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 129 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 130 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 131 #define MPI3MR_RESET_ACK_TIMEOUT 30 132 #define MPI3MR_MUR_TIMEOUT 120 133 #define MPI3MR_RESET_TIMEOUT 510 134 135 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 136 137 #define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */ 138 139 #define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10 140 141 #define MPI3MR_SCMD_TIMEOUT (60 * HZ) 142 #define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 143 144 /* Internal admin command state definitions*/ 145 #define MPI3MR_CMD_NOTUSED 0x8000 146 #define MPI3MR_CMD_COMPLETE 0x0001 147 #define MPI3MR_CMD_PENDING 0x0002 148 #define MPI3MR_CMD_REPLY_VALID 0x0004 149 #define MPI3MR_CMD_RESET 0x0008 150 151 /* Definitions for Event replies and sense buffer allocated per controller */ 152 #define MPI3MR_NUM_EVT_REPLIES 64 153 #define MPI3MR_SENSE_BUF_SZ 256 154 #define MPI3MR_SENSEBUF_FACTOR 3 155 #define MPI3MR_CHAINBUF_FACTOR 3 156 #define MPI3MR_CHAINBUFDIX_FACTOR 2 157 158 /* Invalid target device handle */ 159 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 160 161 /* Controller Reset related definitions */ 162 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 163 #define MPI3MR_MAX_RESET_RETRY_COUNT 3 164 165 /* ResponseCode definitions */ 166 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 167 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 168 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 169 170 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 171 #define MPI3MR_DEFAULT_PGSZEXP (12) 172 173 /* Command retry count definitions */ 174 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 175 #define MPI3MR_PEL_RETRY_COUNT 3 176 177 /* Default target device queue depth */ 178 #define MPI3MR_DEFAULT_SDEV_QD 32 179 180 /* Definitions for Threaded IRQ poll*/ 181 #define MPI3MR_IRQ_POLL_SLEEP 20 182 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 183 184 /* Definitions for the controller security status*/ 185 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 186 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 187 188 #define MPI3MR_INVALID_DEVICE 0x00 189 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 190 #define MPI3MR_HARD_SECURE_DEVICE 0x08 191 #define MPI3MR_TAMPERED_DEVICE 0x0C 192 193 #define MPI3MR_DEFAULT_HDB_MAX_SZ (4 * 1024 * 1024) 194 #define MPI3MR_DEFAULT_HDB_DEC_SZ (1 * 1024 * 1024) 195 #define MPI3MR_DEFAULT_HDB_MIN_SZ (2 * 1024 * 1024) 196 #define MPI3MR_MAX_NUM_HDB 2 197 198 #define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0 199 #define MPI3MR_HDB_TRIGGER_TYPE_FAULT 1 200 #define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2 201 #define MPI3MR_HDB_TRIGGER_TYPE_GLOBAL 3 202 #define MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET 4 203 #define MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED 5 204 205 #define MPI3MR_HDB_REFRESH_TYPE_RESERVED 0 206 #define MPI3MR_HDB_REFRESH_TYPE_CURRENT 1 207 #define MPI3MR_HDB_REFRESH_TYPE_DEFAULT 2 208 #define MPI3MR_HDB_HDB_REFRESH_TYPE_PERSISTENT 3 209 210 #define MPI3MR_DEFAULT_HDB_SZ (4 * 1024 * 1024) 211 #define MPI3MR_MAX_NUM_HDB 2 212 213 #define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_INDEX 0 214 #define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_DATA 1 215 216 #define MPI3MR_THRESHOLD_REPLY_COUNT 100 217 218 /* SGE Flag definition */ 219 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 220 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 221 MPI3_SGE_FLAGS_END_OF_LIST) 222 223 /* MSI Index from Reply Queue Index */ 224 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 225 226 /* 227 * Maximum data transfer size definitions for management 228 * application commands 229 */ 230 #define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 231 #define MPI3MR_MAX_APP_XFER_SEGMENTS 512 232 /* 233 * 2048 sectors are for data buffers and additional 512 sectors for 234 * other buffers 235 */ 236 #define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 237 238 #define MPI3MR_WRITE_SAME_MAX_LEN_256_BLKS 256 239 #define MPI3MR_WRITE_SAME_MAX_LEN_2048_BLKS 2048 240 241 #define MPI3MR_DRIVER_EVENT_PROCESS_TRIGGER (0xFFFD) 242 243 /** 244 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 245 * Encapsulated commands. 246 * 247 * @base_addr: Physical address 248 * @length: SGE length 249 * @rsvd: Reserved 250 * @rsvd1: Reserved 251 * @sub_type: sgl sub type 252 * @type: sgl type 253 */ 254 struct mpi3mr_nvme_pt_sge { 255 __le64 base_addr; 256 __le32 length; 257 u16 rsvd; 258 u8 rsvd1; 259 u8 sub_type:4; 260 u8 type:4; 261 }; 262 263 /** 264 * struct mpi3mr_buf_map - local structure to 265 * track kernel and user buffers associated with an BSG 266 * structure. 267 * 268 * @bsg_buf: BSG buffer virtual address 269 * @bsg_buf_len: BSG buffer length 270 * @kern_buf: Kernel buffer virtual address 271 * @kern_buf_len: Kernel buffer length 272 * @kern_buf_dma: Kernel buffer DMA address 273 * @data_dir: Data direction. 274 */ 275 struct mpi3mr_buf_map { 276 void *bsg_buf; 277 u32 bsg_buf_len; 278 void *kern_buf; 279 u32 kern_buf_len; 280 dma_addr_t kern_buf_dma; 281 u8 data_dir; 282 u16 num_dma_desc; 283 struct dma_memory_desc *dma_desc; 284 }; 285 286 /* IOC State definitions */ 287 enum mpi3mr_iocstate { 288 MRIOC_STATE_READY = 1, 289 MRIOC_STATE_RESET, 290 MRIOC_STATE_FAULT, 291 MRIOC_STATE_BECOMING_READY, 292 MRIOC_STATE_RESET_REQUESTED, 293 MRIOC_STATE_UNRECOVERABLE, 294 }; 295 296 /* Reset reason code definitions*/ 297 enum mpi3mr_reset_reason { 298 MPI3MR_RESET_FROM_BRINGUP = 1, 299 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 300 MPI3MR_RESET_FROM_APP = 3, 301 MPI3MR_RESET_FROM_EH_HOS = 4, 302 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 303 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 304 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 305 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 306 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 307 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 308 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 309 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 310 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 311 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 312 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 313 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 314 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 315 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 316 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 317 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 318 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 319 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 320 MPI3MR_RESET_FROM_SYSFS = 23, 321 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 322 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25, 323 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT = 26, 324 MPI3MR_RESET_FROM_FIRMWARE = 27, 325 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29, 326 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30, 327 MPI3MR_RESET_FROM_TRIGGER = 31, 328 }; 329 330 #define MPI3MR_RESET_REASON_OSTYPE_LINUX 1 331 #define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28 332 #define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20 333 334 /* Queue type definitions */ 335 enum queue_type { 336 MPI3MR_DEFAULT_QUEUE = 0, 337 MPI3MR_POLL_QUEUE, 338 }; 339 340 /** 341 * struct mpi3mr_compimg_ver - replica of component image 342 * version defined in mpi30_image.h in host endianness 343 * 344 */ 345 struct mpi3mr_compimg_ver { 346 u16 build_num; 347 u16 cust_id; 348 u8 ph_minor; 349 u8 ph_major; 350 u8 gen_minor; 351 u8 gen_major; 352 }; 353 354 /** 355 * struct mpi3mr_ioc_facs - replica of component image version 356 * defined in mpi30_ioc.h in host endianness 357 * 358 */ 359 struct mpi3mr_ioc_facts { 360 u32 ioc_capabilities; 361 struct mpi3mr_compimg_ver fw_ver; 362 u32 mpi_version; 363 u32 diag_trace_sz; 364 u32 diag_fw_sz; 365 u32 diag_drvr_sz; 366 u16 max_reqs; 367 u16 product_id; 368 u16 op_req_sz; 369 u16 reply_sz; 370 u16 exceptions; 371 u16 max_perids; 372 u16 max_pds; 373 u16 max_sasexpanders; 374 u32 max_data_length; 375 u16 max_sasinitiators; 376 u16 max_enclosures; 377 u16 max_pcie_switches; 378 u16 max_nvme; 379 u16 max_vds; 380 u16 max_hpds; 381 u16 max_advhpds; 382 u16 max_raid_pds; 383 u16 min_devhandle; 384 u16 max_devhandle; 385 u16 max_op_req_q; 386 u16 max_op_reply_q; 387 u16 shutdown_timeout; 388 u8 ioc_num; 389 u8 who_init; 390 u16 max_msix_vectors; 391 u8 personality; 392 u8 dma_mask; 393 u8 protocol_flags; 394 u8 sge_mod_mask; 395 u8 sge_mod_value; 396 u8 sge_mod_shift; 397 u8 max_dev_per_tg; 398 u16 max_io_throttle_group; 399 u16 io_throttle_data_length; 400 u16 io_throttle_low; 401 u16 io_throttle_high; 402 403 }; 404 405 /** 406 * struct segments - memory descriptor structure to store 407 * virtual and dma addresses for operational queue segments. 408 * 409 * @segment: virtual address 410 * @segment_dma: dma address 411 */ 412 struct segments { 413 void *segment; 414 dma_addr_t segment_dma; 415 }; 416 417 /** 418 * struct op_req_qinfo - Operational Request Queue Information 419 * 420 * @ci: consumer index 421 * @pi: producer index 422 * @num_request: Maximum number of entries in the queue 423 * @qid: Queue Id starting from 1 424 * @reply_qid: Associated reply queue Id 425 * @num_segments: Number of discontiguous memory segments 426 * @segment_qd: Depth of each segments 427 * @q_lock: Concurrent queue access lock 428 * @q_segments: Segment descriptor pointer 429 * @q_segment_list: Segment list base virtual address 430 * @q_segment_list_dma: Segment list base DMA address 431 */ 432 struct op_req_qinfo { 433 u16 ci; 434 u16 pi; 435 u16 num_requests; 436 u16 qid; 437 u16 reply_qid; 438 u16 num_segments; 439 u16 segment_qd; 440 spinlock_t q_lock; 441 struct segments *q_segments; 442 void *q_segment_list; 443 dma_addr_t q_segment_list_dma; 444 }; 445 446 /** 447 * struct op_reply_qinfo - Operational Reply Queue Information 448 * 449 * @ci: consumer index 450 * @qid: Queue Id starting from 1 451 * @num_replies: Maximum number of entries in the queue 452 * @num_segments: Number of discontiguous memory segments 453 * @segment_qd: Depth of each segments 454 * @q_segments: Segment descriptor pointer 455 * @q_segment_list: Segment list base virtual address 456 * @q_segment_list_dma: Segment list base DMA address 457 * @ephase: Expected phased identifier for the reply queue 458 * @pend_ios: Number of IOs pending in HW for this queue 459 * @enable_irq_poll: Flag to indicate polling is enabled 460 * @in_use: Queue is handled by poll/ISR 461 * @qtype: Type of queue (types defined in enum queue_type) 462 */ 463 struct op_reply_qinfo { 464 u16 ci; 465 u16 qid; 466 u16 num_replies; 467 u16 num_segments; 468 u16 segment_qd; 469 struct segments *q_segments; 470 void *q_segment_list; 471 dma_addr_t q_segment_list_dma; 472 u8 ephase; 473 atomic_t pend_ios; 474 bool enable_irq_poll; 475 atomic_t in_use; 476 enum queue_type qtype; 477 }; 478 479 /** 480 * struct mpi3mr_intr_info - Interrupt cookie information 481 * 482 * @mrioc: Adapter instance reference 483 * @os_irq: irq number 484 * @msix_index: MSIx index 485 * @op_reply_q: Associated operational reply queue 486 * @name: Dev name for the irq claiming device 487 */ 488 struct mpi3mr_intr_info { 489 struct mpi3mr_ioc *mrioc; 490 int os_irq; 491 u16 msix_index; 492 struct op_reply_qinfo *op_reply_q; 493 char name[MPI3MR_NAME_LENGTH]; 494 }; 495 496 /** 497 * struct mpi3mr_throttle_group_info - Throttle group info 498 * 499 * @io_divert: Flag indicates io divert is on or off for the TG 500 * @need_qd_reduction: Flag to indicate QD reduction is needed 501 * @qd_reduction: Queue Depth reduction in units of 10% 502 * @fw_qd: QueueDepth value reported by the firmware 503 * @modified_qd: Modified QueueDepth value due to throttling 504 * @id: Throttle Group ID. 505 * @high: High limit to turn on throttling in 512 byte blocks 506 * @low: Low limit to turn off throttling in 512 byte blocks 507 * @pend_large_data_sz: Counter to track pending large data 508 */ 509 struct mpi3mr_throttle_group_info { 510 u8 io_divert; 511 u8 need_qd_reduction; 512 u8 qd_reduction; 513 u16 fw_qd; 514 u16 modified_qd; 515 u16 id; 516 u32 high; 517 u32 low; 518 atomic_t pend_large_data_sz; 519 }; 520 521 /* HBA port flags */ 522 #define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01 523 #define MPI3MR_HBA_PORT_FLAG_NEW 0x02 524 525 /* IOCTL data transfer sge*/ 526 #define MPI3MR_NUM_IOCTL_SGE 256 527 #define MPI3MR_IOCTL_SGE_SIZE (8 * 1024) 528 529 /** 530 * struct mpi3mr_hba_port - HBA's port information 531 * @port_id: Port number 532 * @flags: HBA port flags 533 */ 534 struct mpi3mr_hba_port { 535 struct list_head list; 536 u8 port_id; 537 u8 flags; 538 }; 539 540 /** 541 * struct mpi3mr_sas_port - Internal SAS port information 542 * @port_list: List of ports belonging to a SAS node 543 * @num_phys: Number of phys associated with port 544 * @marked_responding: used while refresing the sas ports 545 * @lowest_phy: lowest phy ID of current sas port, valid for controller port 546 * @phy_mask: phy_mask of current sas port, valid for controller port 547 * @hba_port: HBA port entry 548 * @remote_identify: Attached device identification 549 * @rphy: SAS transport layer rphy object 550 * @port: SAS transport layer port object 551 * @phy_list: mpi3mr_sas_phy objects belonging to this port 552 */ 553 struct mpi3mr_sas_port { 554 struct list_head port_list; 555 u8 num_phys; 556 u8 marked_responding; 557 int lowest_phy; 558 u64 phy_mask; 559 struct mpi3mr_hba_port *hba_port; 560 struct sas_identify remote_identify; 561 struct sas_rphy *rphy; 562 struct sas_port *port; 563 struct list_head phy_list; 564 }; 565 566 /** 567 * struct mpi3mr_sas_phy - Internal SAS Phy information 568 * @port_siblings: List of phys belonging to a port 569 * @identify: Phy identification 570 * @remote_identify: Attached device identification 571 * @phy: SAS transport layer Phy object 572 * @phy_id: Unique phy id within a port 573 * @handle: Firmware device handle for this phy 574 * @attached_handle: Firmware device handle for attached device 575 * @phy_belongs_to_port: Flag to indicate phy belongs to port 576 @hba_port: HBA port entry 577 */ 578 struct mpi3mr_sas_phy { 579 struct list_head port_siblings; 580 struct sas_identify identify; 581 struct sas_identify remote_identify; 582 struct sas_phy *phy; 583 u8 phy_id; 584 u16 handle; 585 u16 attached_handle; 586 u8 phy_belongs_to_port; 587 struct mpi3mr_hba_port *hba_port; 588 }; 589 590 /** 591 * struct mpi3mr_sas_node - SAS host/expander information 592 * @list: List of sas nodes in a controller 593 * @parent_dev: Parent device class 594 * @num_phys: Number phys belonging to sas_node 595 * @sas_address: SAS address of sas_node 596 * @handle: Firmware device handle for this sas_host/expander 597 * @sas_address_parent: SAS address of parent expander or host 598 * @enclosure_handle: Firmware handle of enclosure of this node 599 * @device_info: Capabilities of this sas_host/expander 600 * @non_responding: used to refresh the expander devices during reset 601 * @host_node: Flag to indicate this is a host_node 602 * @hba_port: HBA port entry 603 * @phy: A list of phys that make up this sas_host/expander 604 * @sas_port_list: List of internal ports of this node 605 * @rphy: sas_rphy object of this expander node 606 */ 607 struct mpi3mr_sas_node { 608 struct list_head list; 609 struct device *parent_dev; 610 u8 num_phys; 611 u64 sas_address; 612 u16 handle; 613 u64 sas_address_parent; 614 u16 enclosure_handle; 615 u64 enclosure_logical_id; 616 u8 non_responding; 617 u8 host_node; 618 struct mpi3mr_hba_port *hba_port; 619 struct mpi3mr_sas_phy *phy; 620 struct list_head sas_port_list; 621 struct sas_rphy *rphy; 622 }; 623 624 /** 625 * struct mpi3mr_enclosure_node - enclosure information 626 * @list: List of enclosures 627 * @pg0: Enclosure page 0; 628 */ 629 struct mpi3mr_enclosure_node { 630 struct list_head list; 631 struct mpi3_enclosure_page0 pg0; 632 }; 633 634 /** 635 * struct tgt_dev_sas_sata - SAS/SATA device specific 636 * information cached from firmware given data 637 * 638 * @sas_address: World wide unique SAS address 639 * @sas_address_parent: Sas address of parent expander or host 640 * @dev_info: Device information bits 641 * @phy_id: Phy identifier provided in device page 0 642 * @attached_phy_id: Attached phy identifier provided in device page 0 643 * @sas_transport_attached: Is this device exposed to transport 644 * @pend_sas_rphy_add: Flag to check device is in process of add 645 * @hba_port: HBA port entry 646 * @rphy: SAS transport layer rphy object 647 */ 648 struct tgt_dev_sas_sata { 649 u64 sas_address; 650 u64 sas_address_parent; 651 u16 dev_info; 652 u8 phy_id; 653 u8 attached_phy_id; 654 u8 sas_transport_attached; 655 u8 pend_sas_rphy_add; 656 struct mpi3mr_hba_port *hba_port; 657 struct sas_rphy *rphy; 658 }; 659 660 /** 661 * struct tgt_dev_pcie - PCIe device specific information cached 662 * from firmware given data 663 * 664 * @mdts: Maximum data transfer size 665 * @capb: Device capabilities 666 * @pgsz: Device page size 667 * @abort_to: Timeout for abort TM 668 * @reset_to: Timeout for Target/LUN reset TM 669 * @dev_info: Device information bits 670 */ 671 struct tgt_dev_pcie { 672 u32 mdts; 673 u16 capb; 674 u8 pgsz; 675 u8 abort_to; 676 u8 reset_to; 677 u16 dev_info; 678 }; 679 680 /** 681 * struct tgt_dev_vd - virtual device specific information 682 * cached from firmware given data 683 * 684 * @state: State of the VD 685 * @tg_qd_reduction: Queue Depth reduction in units of 10% 686 * @tg_id: VDs throttle group ID 687 * @high: High limit to turn on throttling in 512 byte blocks 688 * @low: Low limit to turn off throttling in 512 byte blocks 689 * @tg: Pointer to throttle group info 690 */ 691 struct tgt_dev_vd { 692 u8 state; 693 u8 tg_qd_reduction; 694 u16 tg_id; 695 u32 tg_high; 696 u32 tg_low; 697 struct mpi3mr_throttle_group_info *tg; 698 }; 699 700 701 /** 702 * union _form_spec_inf - union of device specific information 703 */ 704 union _form_spec_inf { 705 struct tgt_dev_sas_sata sas_sata_inf; 706 struct tgt_dev_pcie pcie_inf; 707 struct tgt_dev_vd vd_inf; 708 }; 709 710 enum mpi3mr_dev_state { 711 MPI3MR_DEV_CREATED = 1, 712 MPI3MR_DEV_REMOVE_HS_STARTED = 2, 713 MPI3MR_DEV_DELETED = 3, 714 }; 715 716 /** 717 * struct mpi3mr_tgt_dev - target device data structure 718 * 719 * @list: List pointer 720 * @starget: Scsi_target pointer 721 * @dev_handle: FW device handle 722 * @parent_handle: FW parent device handle 723 * @slot: Slot number 724 * @encl_handle: FW enclosure handle 725 * @perst_id: FW assigned Persistent ID 726 * @devpg0_flag: Device Page0 flag 727 * @dev_type: SAS/SATA/PCIE device type 728 * @is_hidden: Should be exposed to upper layers or not 729 * @host_exposed: Already exposed to host or not 730 * @io_unit_port: IO Unit port ID 731 * @non_stl: Is this device not to be attached with SAS TL 732 * @io_throttle_enabled: I/O throttling needed or not 733 * @wslen: Write same max length 734 * @q_depth: Device specific Queue Depth 735 * @wwid: World wide ID 736 * @enclosure_logical_id: Enclosure logical identifier 737 * @dev_spec: Device type specific information 738 * @ref_count: Reference count 739 * @state: device state 740 */ 741 struct mpi3mr_tgt_dev { 742 struct list_head list; 743 struct scsi_target *starget; 744 u16 dev_handle; 745 u16 parent_handle; 746 u16 slot; 747 u16 encl_handle; 748 u16 perst_id; 749 u16 devpg0_flag; 750 u8 dev_type; 751 u8 is_hidden; 752 u8 host_exposed; 753 u8 io_unit_port; 754 u8 non_stl; 755 u8 io_throttle_enabled; 756 u16 wslen; 757 u16 q_depth; 758 u64 wwid; 759 u64 enclosure_logical_id; 760 union _form_spec_inf dev_spec; 761 struct kref ref_count; 762 enum mpi3mr_dev_state state; 763 }; 764 765 /** 766 * mpi3mr_tgtdev_get - k reference incrementor 767 * @s: Target device reference 768 * 769 * Increment target device reference count. 770 */ 771 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 772 { 773 kref_get(&s->ref_count); 774 } 775 776 /** 777 * mpi3mr_free_tgtdev - target device memory dealloctor 778 * @r: k reference pointer of the target device 779 * 780 * Free target device memory when no reference. 781 */ 782 static inline void mpi3mr_free_tgtdev(struct kref *r) 783 { 784 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 785 } 786 787 /** 788 * mpi3mr_tgtdev_put - k reference decrementor 789 * @s: Target device reference 790 * 791 * Decrement target device reference count. 792 */ 793 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 794 { 795 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 796 } 797 798 799 /** 800 * struct mpi3mr_stgt_priv_data - SCSI target private structure 801 * 802 * @starget: Scsi_target pointer 803 * @dev_handle: FW device handle 804 * @perst_id: FW assigned Persistent ID 805 * @num_luns: Number of Logical Units 806 * @block_io: I/O blocked to the device or not 807 * @dev_removed: Device removed in the Firmware 808 * @dev_removedelay: Device is waiting to be removed in FW 809 * @dev_type: Device type 810 * @dev_nvme_dif: Device is NVMe DIF enabled 811 * @wslen: Write same max length 812 * @io_throttle_enabled: I/O throttling needed or not 813 * @io_divert: Flag indicates io divert is on or off for the dev 814 * @throttle_group: Pointer to throttle group info 815 * @tgt_dev: Internal target device pointer 816 * @pend_count: Counter to track pending I/Os during error 817 * handling 818 */ 819 struct mpi3mr_stgt_priv_data { 820 struct scsi_target *starget; 821 u16 dev_handle; 822 u16 perst_id; 823 u32 num_luns; 824 atomic_t block_io; 825 u8 dev_removed; 826 u8 dev_removedelay; 827 u8 dev_type; 828 u8 dev_nvme_dif; 829 u16 wslen; 830 u8 io_throttle_enabled; 831 u8 io_divert; 832 struct mpi3mr_throttle_group_info *throttle_group; 833 struct mpi3mr_tgt_dev *tgt_dev; 834 u32 pend_count; 835 }; 836 837 /** 838 * struct mpi3mr_stgt_priv_data - SCSI device private structure 839 * 840 * @tgt_priv_data: Scsi_target private data pointer 841 * @lun_id: LUN ID of the device 842 * @ncq_prio_enable: NCQ priority enable for SATA device 843 * @pend_count: Counter to track pending I/Os during error 844 * handling 845 * @wslen: Write same max length 846 */ 847 struct mpi3mr_sdev_priv_data { 848 struct mpi3mr_stgt_priv_data *tgt_priv_data; 849 u32 lun_id; 850 u8 ncq_prio_enable; 851 u32 pend_count; 852 u16 wslen; 853 }; 854 855 /** 856 * struct mpi3mr_drv_cmd - Internal command tracker 857 * 858 * @mutex: Command mutex 859 * @done: Completeor for wakeup 860 * @reply: Firmware reply for internal commands 861 * @sensebuf: Sensebuf for SCSI IO commands 862 * @iou_rc: IO Unit control reason code 863 * @state: Command State 864 * @dev_handle: Firmware handle for device specific commands 865 * @ioc_status: IOC status from the firmware 866 * @ioc_loginfo:IOC log info from the firmware 867 * @is_waiting: Is the command issued in block mode 868 * @is_sense: Is Sense data present 869 * @retry_count: Retry count for retriable commands 870 * @host_tag: Host tag used by the command 871 * @callback: Callback for non blocking commands 872 */ 873 struct mpi3mr_drv_cmd { 874 struct mutex mutex; 875 struct completion done; 876 void *reply; 877 u8 *sensebuf; 878 u8 iou_rc; 879 u16 state; 880 u16 dev_handle; 881 u16 ioc_status; 882 u32 ioc_loginfo; 883 u8 is_waiting; 884 u8 is_sense; 885 u8 retry_count; 886 u16 host_tag; 887 888 void (*callback)(struct mpi3mr_ioc *mrioc, 889 struct mpi3mr_drv_cmd *drv_cmd); 890 }; 891 892 /** 893 * union mpi3mr_trigger_data - Trigger data information 894 * @fault: Fault code 895 * @global: Global trigger data 896 * @element: element trigger data 897 */ 898 union mpi3mr_trigger_data { 899 u16 fault; 900 u64 global; 901 union mpi3_driver2_trigger_element element; 902 }; 903 904 /** 905 * struct trigger_event_data - store trigger related 906 * information. 907 * 908 * @trace_hdb: Trace diag buffer descriptor reference 909 * @fw_hdb: FW diag buffer descriptor reference 910 * @trigger_type: Trigger type 911 * @trigger_specific_data: Trigger specific data 912 * @snapdump: Snapdump enable or disable flag 913 */ 914 struct trigger_event_data { 915 struct diag_buffer_desc *trace_hdb; 916 struct diag_buffer_desc *fw_hdb; 917 u8 trigger_type; 918 union mpi3mr_trigger_data trigger_specific_data; 919 bool snapdump; 920 }; 921 922 /** 923 * struct diag_buffer_desc - memory descriptor structure to 924 * store virtual, dma addresses, size, buffer status for host 925 * diagnostic buffers. 926 * 927 * @type: Buffer type 928 * @trigger_data: Trigger data 929 * @trigger_type: Trigger type 930 * @status: Buffer status 931 * @size: Buffer size 932 * @addr: Virtual address 933 * @dma_addr: Buffer DMA address 934 */ 935 struct diag_buffer_desc { 936 u8 type; 937 union mpi3mr_trigger_data trigger_data; 938 u8 trigger_type; 939 u8 status; 940 u32 size; 941 void *addr; 942 dma_addr_t dma_addr; 943 }; 944 945 /** 946 * struct dma_memory_desc - memory descriptor structure to store 947 * virtual address, dma address and size for any generic dma 948 * memory allocations in the driver. 949 * 950 * @size: buffer size 951 * @addr: virtual address 952 * @dma_addr: dma address 953 */ 954 struct dma_memory_desc { 955 u32 size; 956 void *addr; 957 dma_addr_t dma_addr; 958 }; 959 960 961 /** 962 * struct chain_element - memory descriptor structure to store 963 * virtual and dma addresses for chain elements. 964 * 965 * @addr: virtual address 966 * @dma_addr: dma address 967 */ 968 struct chain_element { 969 void *addr; 970 dma_addr_t dma_addr; 971 }; 972 973 /** 974 * struct scmd_priv - SCSI command private data 975 * 976 * @host_tag: Host tag specific to operational queue 977 * @in_lld_scope: Command in LLD scope or not 978 * @meta_sg_valid: DIX command with meta data SGL or not 979 * @scmd: SCSI Command pointer 980 * @req_q_idx: Operational request queue index 981 * @chain_idx: Chain frame index 982 * @meta_chain_idx: Chain frame index of meta data SGL 983 * @mpi3mr_scsiio_req: MPI SCSI IO request 984 */ 985 struct scmd_priv { 986 u16 host_tag; 987 u8 in_lld_scope; 988 u8 meta_sg_valid; 989 struct scsi_cmnd *scmd; 990 u16 req_q_idx; 991 int chain_idx; 992 int meta_chain_idx; 993 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 994 }; 995 996 /** 997 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 998 * private data 999 * 1000 * @list: List pointer 1001 * @pdev: PCI device pointer 1002 * @shost: Scsi_Host pointer 1003 * @id: Controller ID 1004 * @cpu_count: Number of online CPUs 1005 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 1006 * @name: Controller ASCII name 1007 * @driver_name: Driver ASCII name 1008 * @sysif_regs: System interface registers virtual address 1009 * @sysif_regs_phys: System interface registers physical address 1010 * @bars: PCI BARS 1011 * @dma_mask: DMA mask 1012 * @msix_count: Number of MSIX vectors used 1013 * @intr_enabled: Is interrupts enabled 1014 * @num_admin_req: Number of admin requests 1015 * @admin_req_q_sz: Admin request queue size 1016 * @admin_req_pi: Admin request queue producer index 1017 * @admin_req_ci: Admin request queue consumer index 1018 * @admin_req_base: Admin request queue base virtual address 1019 * @admin_req_dma: Admin request queue base dma address 1020 * @admin_req_lock: Admin queue access lock 1021 * @num_admin_replies: Number of admin replies 1022 * @admin_reply_q_sz: Admin reply queue size 1023 * @admin_reply_ci: Admin reply queue consumer index 1024 * @admin_reply_ephase:Admin reply queue expected phase 1025 * @admin_reply_base: Admin reply queue base virtual address 1026 * @admin_reply_dma: Admin reply queue base dma address 1027 * @admin_reply_q_in_use: Queue is handled by poll/ISR 1028 * @ready_timeout: Controller ready timeout 1029 * @intr_info: Interrupt cookie pointer 1030 * @intr_info_count: Number of interrupt cookies 1031 * @is_intr_info_set: Flag to indicate intr info is setup 1032 * @num_queues: Number of operational queues 1033 * @num_op_req_q: Number of operational request queues 1034 * @req_qinfo: Operational request queue info pointer 1035 * @num_op_reply_q: Number of operational reply queues 1036 * @op_reply_qinfo: Operational reply queue info pointer 1037 * @init_cmds: Command tracker for initialization commands 1038 * @cfg_cmds: Command tracker for configuration requests 1039 * @facts: Cached IOC facts data 1040 * @op_reply_desc_sz: Operational reply descriptor size 1041 * @num_reply_bufs: Number of reply buffers allocated 1042 * @reply_buf_pool: Reply buffer pool 1043 * @reply_buf: Reply buffer base virtual address 1044 * @reply_buf_dma: Reply buffer DMA address 1045 * @reply_buf_dma_max_address: Reply DMA address max limit 1046 * @reply_free_qsz: Reply free queue size 1047 * @reply_free_q_pool: Reply free queue pool 1048 * @reply_free_q: Reply free queue base virtual address 1049 * @reply_free_q_dma: Reply free queue base DMA address 1050 * @reply_free_queue_lock: Reply free queue lock 1051 * @reply_free_queue_host_index: Reply free queue host index 1052 * @num_sense_bufs: Number of sense buffers 1053 * @sense_buf_pool: Sense buffer pool 1054 * @sense_buf: Sense buffer base virtual address 1055 * @sense_buf_dma: Sense buffer base DMA address 1056 * @sense_buf_q_sz: Sense buffer queue size 1057 * @sense_buf_q_pool: Sense buffer queue pool 1058 * @sense_buf_q: Sense buffer queue virtual address 1059 * @sense_buf_q_dma: Sense buffer queue DMA address 1060 * @sbq_lock: Sense buffer queue lock 1061 * @sbq_host_index: Sense buffer queuehost index 1062 * @event_masks: Event mask bitmap 1063 * @fwevt_worker_thread: Firmware event worker thread 1064 * @fwevt_lock: Firmware event lock 1065 * @fwevt_list: Firmware event list 1066 * @watchdog_work_q_name: Fault watchdog worker thread name 1067 * @watchdog_work_q: Fault watchdog worker thread 1068 * @watchdog_work: Fault watchdog work 1069 * @watchdog_lock: Fault watchdog lock 1070 * @is_driver_loading: Is driver still loading 1071 * @scan_started: Async scan started 1072 * @scan_failed: Asycn scan failed 1073 * @stop_drv_processing: Stop all command processing 1074 * @device_refresh_on: Don't process the events until devices are refreshed 1075 * @max_host_ios: Maximum host I/O count 1076 * @max_sgl_entries: Max SGL entries per I/O 1077 * @chain_buf_count: Chain buffer count 1078 * @chain_buf_pool: Chain buffer pool 1079 * @chain_sgl_list: Chain SGL list 1080 * @chain_bitmap: Chain buffer allocator bitmap 1081 * @chain_buf_lock: Chain buffer list lock 1082 * @bsg_cmds: Command tracker for BSG command 1083 * @host_tm_cmds: Command tracker for task management commands 1084 * @dev_rmhs_cmds: Command tracker for device removal commands 1085 * @evtack_cmds: Command tracker for event ack commands 1086 * @devrem_bitmap: Device removal bitmap 1087 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap 1088 * @removepend_bitmap: Remove pending bitmap 1089 * @delayed_rmhs_list: Delayed device removal list 1090 * @evtack_cmds_bitmap: Event Ack bitmap 1091 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 1092 * @ts_update_counter: Timestamp update counter 1093 * @ts_update_interval: Timestamp update interval 1094 * @reset_in_progress: Reset in progress flag 1095 * @unrecoverable: Controller unrecoverable flag 1096 * @prev_reset_result: Result of previous reset 1097 * @reset_mutex: Controller reset mutex 1098 * @reset_waitq: Controller reset wait queue 1099 * @prepare_for_reset: Prepare for reset event received 1100 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 1101 * @prp_list_virt: NVMe encapsulated PRP list virtual base 1102 * @prp_list_dma: NVMe encapsulated PRP list DMA 1103 * @prp_sz: NVME encapsulated PRP list size 1104 * @diagsave_timeout: Diagnostic information save timeout 1105 * @logging_level: Controller debug logging level 1106 * @flush_io_count: I/O count to flush after reset 1107 * @current_event: Firmware event currently in process 1108 * @driver_info: Driver, Kernel, OS information to firmware 1109 * @change_count: Topology change count 1110 * @pel_enabled: Persistent Event Log(PEL) enabled or not 1111 * @pel_abort_requested: PEL abort is requested or not 1112 * @pel_class: PEL Class identifier 1113 * @pel_locale: PEL Locale identifier 1114 * @pel_cmds: Command tracker for PEL wait command 1115 * @pel_abort_cmd: Command tracker for PEL abort command 1116 * @pel_newest_seqnum: Newest PEL sequenece number 1117 * @pel_seqnum_virt: PEL sequence number virtual address 1118 * @pel_seqnum_dma: PEL sequence number DMA address 1119 * @pel_seqnum_sz: PEL sequenece number size 1120 * @op_reply_q_offset: Operational reply queue offset with MSIx 1121 * @default_qcount: Total Default queues 1122 * @active_poll_qcount: Currently active poll queue count 1123 * @requested_poll_qcount: User requested poll queue count 1124 * @bsg_dev: BSG device structure 1125 * @bsg_queue: Request queue for BSG device 1126 * @stop_bsgs: Stop BSG request flag 1127 * @logdata_buf: Circular buffer to store log data entries 1128 * @logdata_buf_idx: Index of entry in buffer to store 1129 * @logdata_entry_sz: log data entry size 1130 * @pend_large_data_sz: Counter to track pending large data 1131 * @io_throttle_data_length: I/O size to track in 512b blocks 1132 * @io_throttle_high: I/O size to start throttle in 512b blocks 1133 * @io_throttle_low: I/O size to stop throttle in 512b blocks 1134 * @num_io_throttle_group: Maximum number of throttle groups 1135 * @throttle_groups: Pointer to throttle group info structures 1136 * @cfg_page: Default memory for configuration pages 1137 * @cfg_page_dma: Configuration page DMA address 1138 * @cfg_page_sz: Default configuration page memory size 1139 * @sas_transport_enabled: SAS transport enabled or not 1140 * @scsi_device_channel: Channel ID for SCSI devices 1141 * @transport_cmds: Command tracker for SAS transport commands 1142 * @sas_hba: SAS node for the controller 1143 * @sas_expander_list: SAS node list of expanders 1144 * @sas_node_lock: Lock to protect SAS node list 1145 * @hba_port_table_list: List of HBA Ports 1146 * @enclosure_list: List of Enclosure objects 1147 * @diag_buffers: Host diagnostic buffers 1148 * @driver_pg2: Driver page 2 pointer 1149 * @reply_trigger_present: Reply trigger present flag 1150 * @event_trigger_present: Event trigger present flag 1151 * @scsisense_trigger_present: Scsi sense trigger present flag 1152 * @ioctl_dma_pool: DMA pool for IOCTL data buffers 1153 * @ioctl_sge: DMA buffer descriptors for IOCTL data 1154 * @ioctl_chain_sge: DMA buffer descriptor for IOCTL chain 1155 * @ioctl_resp_sge: DMA buffer descriptor for Mgmt cmd response 1156 * @ioctl_sges_allocated: Flag for IOCTL SGEs allocated or not 1157 * @trace_release_trigger_active: Trace trigger active flag 1158 * @fw_release_trigger_active: Fw release trigger active flag 1159 * @snapdump_trigger_active: Snapdump trigger active flag 1160 * @pci_err_recovery: PCI error recovery in progress 1161 * @block_on_pci_err: Block IO during PCI error recovery 1162 */ 1163 struct mpi3mr_ioc { 1164 struct list_head list; 1165 struct pci_dev *pdev; 1166 struct Scsi_Host *shost; 1167 u8 id; 1168 int cpu_count; 1169 bool enable_segqueue; 1170 u32 irqpoll_sleep; 1171 1172 char name[MPI3MR_NAME_LENGTH]; 1173 char driver_name[MPI3MR_NAME_LENGTH]; 1174 1175 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 1176 resource_size_t sysif_regs_phys; 1177 int bars; 1178 u64 dma_mask; 1179 1180 u16 msix_count; 1181 u8 intr_enabled; 1182 1183 u16 num_admin_req; 1184 u32 admin_req_q_sz; 1185 u16 admin_req_pi; 1186 u16 admin_req_ci; 1187 void *admin_req_base; 1188 dma_addr_t admin_req_dma; 1189 spinlock_t admin_req_lock; 1190 1191 u16 num_admin_replies; 1192 u32 admin_reply_q_sz; 1193 u16 admin_reply_ci; 1194 u8 admin_reply_ephase; 1195 void *admin_reply_base; 1196 dma_addr_t admin_reply_dma; 1197 atomic_t admin_reply_q_in_use; 1198 1199 u32 ready_timeout; 1200 1201 struct mpi3mr_intr_info *intr_info; 1202 u16 intr_info_count; 1203 bool is_intr_info_set; 1204 1205 u16 num_queues; 1206 u16 num_op_req_q; 1207 struct op_req_qinfo *req_qinfo; 1208 1209 u16 num_op_reply_q; 1210 struct op_reply_qinfo *op_reply_qinfo; 1211 1212 struct mpi3mr_drv_cmd init_cmds; 1213 struct mpi3mr_drv_cmd cfg_cmds; 1214 struct mpi3mr_ioc_facts facts; 1215 u16 op_reply_desc_sz; 1216 1217 u32 num_reply_bufs; 1218 struct dma_pool *reply_buf_pool; 1219 u8 *reply_buf; 1220 dma_addr_t reply_buf_dma; 1221 dma_addr_t reply_buf_dma_max_address; 1222 1223 u16 reply_free_qsz; 1224 u16 reply_sz; 1225 struct dma_pool *reply_free_q_pool; 1226 __le64 *reply_free_q; 1227 dma_addr_t reply_free_q_dma; 1228 spinlock_t reply_free_queue_lock; 1229 u32 reply_free_queue_host_index; 1230 1231 u32 num_sense_bufs; 1232 struct dma_pool *sense_buf_pool; 1233 u8 *sense_buf; 1234 dma_addr_t sense_buf_dma; 1235 1236 u16 sense_buf_q_sz; 1237 struct dma_pool *sense_buf_q_pool; 1238 __le64 *sense_buf_q; 1239 dma_addr_t sense_buf_q_dma; 1240 spinlock_t sbq_lock; 1241 u32 sbq_host_index; 1242 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 1243 1244 struct workqueue_struct *fwevt_worker_thread; 1245 spinlock_t fwevt_lock; 1246 struct list_head fwevt_list; 1247 1248 char watchdog_work_q_name[50]; 1249 struct workqueue_struct *watchdog_work_q; 1250 struct delayed_work watchdog_work; 1251 spinlock_t watchdog_lock; 1252 1253 u8 is_driver_loading; 1254 u8 scan_started; 1255 u16 scan_failed; 1256 u8 stop_drv_processing; 1257 u8 device_refresh_on; 1258 1259 u16 max_host_ios; 1260 spinlock_t tgtdev_lock; 1261 struct list_head tgtdev_list; 1262 u16 max_sgl_entries; 1263 1264 u32 chain_buf_count; 1265 struct dma_pool *chain_buf_pool; 1266 struct chain_element *chain_sgl_list; 1267 unsigned long *chain_bitmap; 1268 spinlock_t chain_buf_lock; 1269 1270 struct mpi3mr_drv_cmd bsg_cmds; 1271 struct mpi3mr_drv_cmd host_tm_cmds; 1272 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 1273 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 1274 unsigned long *devrem_bitmap; 1275 u16 dev_handle_bitmap_bits; 1276 unsigned long *removepend_bitmap; 1277 struct list_head delayed_rmhs_list; 1278 unsigned long *evtack_cmds_bitmap; 1279 struct list_head delayed_evtack_cmds_list; 1280 1281 u16 ts_update_counter; 1282 u16 ts_update_interval; 1283 u8 reset_in_progress; 1284 u8 unrecoverable; 1285 int prev_reset_result; 1286 struct mutex reset_mutex; 1287 wait_queue_head_t reset_waitq; 1288 1289 u8 prepare_for_reset; 1290 u16 prepare_for_reset_timeout_counter; 1291 1292 void *prp_list_virt; 1293 dma_addr_t prp_list_dma; 1294 u32 prp_sz; 1295 1296 u16 diagsave_timeout; 1297 int logging_level; 1298 u16 flush_io_count; 1299 1300 struct mpi3mr_fwevt *current_event; 1301 struct mpi3_driver_info_layout driver_info; 1302 u16 change_count; 1303 1304 u8 pel_enabled; 1305 u8 pel_abort_requested; 1306 u8 pel_class; 1307 u16 pel_locale; 1308 struct mpi3mr_drv_cmd pel_cmds; 1309 struct mpi3mr_drv_cmd pel_abort_cmd; 1310 1311 u32 pel_newest_seqnum; 1312 void *pel_seqnum_virt; 1313 dma_addr_t pel_seqnum_dma; 1314 u32 pel_seqnum_sz; 1315 1316 u16 op_reply_q_offset; 1317 u16 default_qcount; 1318 u16 active_poll_qcount; 1319 u16 requested_poll_qcount; 1320 1321 struct device bsg_dev; 1322 struct request_queue *bsg_queue; 1323 u8 stop_bsgs; 1324 u8 *logdata_buf; 1325 u16 logdata_buf_idx; 1326 u16 logdata_entry_sz; 1327 1328 atomic_t pend_large_data_sz; 1329 u32 io_throttle_data_length; 1330 u32 io_throttle_high; 1331 u32 io_throttle_low; 1332 u16 num_io_throttle_group; 1333 struct mpi3mr_throttle_group_info *throttle_groups; 1334 1335 void *cfg_page; 1336 dma_addr_t cfg_page_dma; 1337 u16 cfg_page_sz; 1338 1339 u8 sas_transport_enabled; 1340 u8 scsi_device_channel; 1341 struct mpi3mr_drv_cmd transport_cmds; 1342 struct mpi3mr_sas_node sas_hba; 1343 struct list_head sas_expander_list; 1344 spinlock_t sas_node_lock; 1345 struct list_head hba_port_table_list; 1346 struct list_head enclosure_list; 1347 1348 struct dma_pool *ioctl_dma_pool; 1349 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE]; 1350 struct dma_memory_desc ioctl_chain_sge; 1351 struct dma_memory_desc ioctl_resp_sge; 1352 bool ioctl_sges_allocated; 1353 bool reply_trigger_present; 1354 bool event_trigger_present; 1355 bool scsisense_trigger_present; 1356 struct diag_buffer_desc diag_buffers[MPI3MR_MAX_NUM_HDB]; 1357 struct mpi3_driver_page2 *driver_pg2; 1358 spinlock_t trigger_lock; 1359 bool snapdump_trigger_active; 1360 bool trace_release_trigger_active; 1361 bool fw_release_trigger_active; 1362 bool pci_err_recovery; 1363 bool block_on_pci_err; 1364 }; 1365 1366 /** 1367 * struct mpi3mr_fwevt - Firmware event structure. 1368 * 1369 * @list: list head 1370 * @work: Work structure 1371 * @mrioc: Adapter instance reference 1372 * @event_id: MPI3 firmware event ID 1373 * @send_ack: Event acknowledgment required or not 1374 * @process_evt: Bottomhalf processing required or not 1375 * @evt_ctx: Event context to send in Ack 1376 * @event_data_size: size of the event data in bytes 1377 * @pending_at_sml: waiting for device add/remove API to complete 1378 * @discard: discard this event 1379 * @ref_count: kref count 1380 * @event_data: Actual MPI3 event data 1381 */ 1382 struct mpi3mr_fwevt { 1383 struct list_head list; 1384 struct work_struct work; 1385 struct mpi3mr_ioc *mrioc; 1386 u16 event_id; 1387 bool send_ack; 1388 bool process_evt; 1389 u32 evt_ctx; 1390 u16 event_data_size; 1391 bool pending_at_sml; 1392 bool discard; 1393 struct kref ref_count; 1394 char event_data[] __aligned(4); 1395 }; 1396 1397 1398 /** 1399 * struct delayed_dev_rmhs_node - Delayed device removal node 1400 * 1401 * @list: list head 1402 * @handle: Device handle 1403 * @iou_rc: IO Unit Control Reason Code 1404 */ 1405 struct delayed_dev_rmhs_node { 1406 struct list_head list; 1407 u16 handle; 1408 u8 iou_rc; 1409 }; 1410 1411 /** 1412 * struct delayed_evt_ack_node - Delayed event ack node 1413 * @list: list head 1414 * @event: MPI3 event ID 1415 * @event_ctx: event context 1416 */ 1417 struct delayed_evt_ack_node { 1418 struct list_head list; 1419 u8 event; 1420 u32 event_ctx; 1421 }; 1422 1423 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1424 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1425 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1426 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1427 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1428 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1429 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1430 u16 admin_req_sz, u8 ignore_reset); 1431 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1432 struct op_req_qinfo *opreqq, u8 *req); 1433 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1434 dma_addr_t dma_addr); 1435 void mpi3mr_build_zero_len_sge(void *paddr); 1436 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1437 dma_addr_t phys_addr); 1438 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1439 dma_addr_t phys_addr); 1440 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1441 u64 sense_buf_dma); 1442 1443 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1444 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1445 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1446 struct mpi3_event_notification_reply *event_reply); 1447 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1448 struct mpi3_default_reply_descriptor *reply_desc, 1449 u64 *reply_dma, u16 qidx); 1450 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1451 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1452 1453 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1454 u16 reset_reason, u8 snapdump); 1455 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1456 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1457 1458 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1459 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1460 u32 event_ctx); 1461 1462 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1463 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1464 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1465 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1466 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1467 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1468 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1469 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1470 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1471 struct op_reply_qinfo *op_reply_q); 1472 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1473 void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1474 void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1475 int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1476 u16 handle, uint lun, u16 htag, ulong timeout, 1477 struct mpi3mr_drv_cmd *drv_cmd, 1478 u8 *resp_code, struct scsi_cmnd *scmd); 1479 struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1480 struct mpi3mr_ioc *mrioc, u16 handle); 1481 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1482 struct mpi3mr_drv_cmd *drv_cmd); 1483 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1484 struct mpi3mr_drv_cmd *drv_cmd); 1485 void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1486 u16 event_data_size); 1487 struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle( 1488 struct mpi3mr_ioc *mrioc, u16 handle); 1489 extern const struct attribute_group *mpi3mr_host_groups[]; 1490 extern const struct attribute_group *mpi3mr_dev_groups[]; 1491 1492 extern struct sas_function_template mpi3mr_transport_functions; 1493 extern struct scsi_transport_template *mpi3mr_transport_template; 1494 1495 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1496 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec); 1497 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1498 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 1499 u32 form_spec); 1500 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1501 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 1502 u32 form_spec); 1503 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1504 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 1505 u32 form_spec); 1506 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1507 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 1508 u32 form_spec); 1509 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1510 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 1511 u32 form_spec); 1512 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 1513 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz); 1514 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1515 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1516 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1517 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1518 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 1519 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz); 1520 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc, 1521 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_type); 1522 1523 u8 mpi3mr_is_expander_device(u16 device_info); 1524 int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle); 1525 void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address, 1526 struct mpi3mr_hba_port *hba_port); 1527 struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc 1528 *mrioc, u16 handle); 1529 struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc, 1530 u8 port_id); 1531 void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc); 1532 void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc); 1533 void mpi3mr_update_links(struct mpi3mr_ioc *mrioc, 1534 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate, 1535 struct mpi3mr_hba_port *hba_port); 1536 void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc, 1537 struct mpi3mr_tgt_dev *tgtdev); 1538 int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc, 1539 struct mpi3mr_tgt_dev *tgtdev); 1540 void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc, 1541 struct mpi3mr_tgt_dev *tgtdev); 1542 struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy( 1543 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy); 1544 void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc, 1545 bool device_add); 1546 void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc); 1547 void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc); 1548 void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc); 1549 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc); 1550 void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc); 1551 void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc); 1552 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc); 1553 void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc, 1554 struct mpi3mr_sas_node *sas_expander); 1555 void mpi3mr_alloc_diag_bufs(struct mpi3mr_ioc *mrioc); 1556 int mpi3mr_post_diag_bufs(struct mpi3mr_ioc *mrioc); 1557 int mpi3mr_issue_diag_buf_release(struct mpi3mr_ioc *mrioc, 1558 struct diag_buffer_desc *diag_buffer); 1559 void mpi3mr_release_diag_bufs(struct mpi3mr_ioc *mrioc, u8 skip_rel_action); 1560 void mpi3mr_set_trigger_data_in_hdb(struct diag_buffer_desc *hdb, 1561 u8 type, union mpi3mr_trigger_data *trigger_data, bool force); 1562 int mpi3mr_refresh_trigger(struct mpi3mr_ioc *mrioc, u8 page_type); 1563 struct diag_buffer_desc *mpi3mr_diag_buffer_for_type(struct mpi3mr_ioc *mrioc, 1564 u8 buf_type); 1565 int mpi3mr_issue_diag_buf_post(struct mpi3mr_ioc *mrioc, 1566 struct diag_buffer_desc *diag_buffer); 1567 void mpi3mr_set_trigger_data_in_all_hdb(struct mpi3mr_ioc *mrioc, 1568 u8 type, union mpi3mr_trigger_data *trigger_data, bool force); 1569 void mpi3mr_reply_trigger(struct mpi3mr_ioc *mrioc, u16 iocstatus, 1570 u32 iocloginfo); 1571 void mpi3mr_hdb_trigger_data_event(struct mpi3mr_ioc *mrioc, 1572 struct trigger_event_data *event_data); 1573 void mpi3mr_scsisense_trigger(struct mpi3mr_ioc *mrioc, u8 senseky, u8 asc, 1574 u8 ascq); 1575 void mpi3mr_event_trigger(struct mpi3mr_ioc *mrioc, u8 event); 1576 void mpi3mr_global_trigger(struct mpi3mr_ioc *mrioc, u64 trigger_data); 1577 void mpi3mr_hdbstatuschg_evt_th(struct mpi3mr_ioc *mrioc, 1578 struct mpi3_event_notification_reply *event_reply); 1579 #endif /*MPI3MR_H_INCLUDED*/ 1580