1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2016-2023 Broadcom Inc. All rights reserved. 4 */ 5 #ifndef MPI30_IOC_H 6 #define MPI30_IOC_H 1 7 struct mpi3_ioc_init_request { 8 __le16 host_tag; 9 u8 ioc_use_only02; 10 u8 function; 11 __le16 ioc_use_only04; 12 u8 ioc_use_only06; 13 u8 msg_flags; 14 __le16 change_count; 15 __le16 reserved0a; 16 union mpi3_version_union mpi_version; 17 __le64 time_stamp; 18 u8 reserved18; 19 u8 who_init; 20 __le16 reserved1a; 21 __le16 reply_free_queue_depth; 22 __le16 reserved1e; 23 __le64 reply_free_queue_address; 24 __le32 reserved28; 25 __le16 sense_buffer_free_queue_depth; 26 __le16 sense_buffer_length; 27 __le64 sense_buffer_free_queue_address; 28 __le64 driver_information_address; 29 }; 30 #define MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED (0x08) 31 #define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0x04) 32 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03) 33 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00) 34 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01) 35 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02) 36 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03) 37 #define MPI3_WHOINIT_NOT_INITIALIZED (0x00) 38 #define MPI3_WHOINIT_ROM_BIOS (0x02) 39 #define MPI3_WHOINIT_HOST_DRIVER (0x03) 40 #define MPI3_WHOINIT_MANUFACTURER (0x04) 41 42 struct mpi3_ioc_facts_request { 43 __le16 host_tag; 44 u8 ioc_use_only02; 45 u8 function; 46 __le16 ioc_use_only04; 47 u8 ioc_use_only06; 48 u8 msg_flags; 49 __le16 change_count; 50 __le16 reserved0a; 51 __le32 reserved0c; 52 union mpi3_sge_union sgl; 53 }; 54 55 struct mpi3_ioc_facts_data { 56 __le16 ioc_facts_data_length; 57 __le16 reserved02; 58 union mpi3_version_union mpi_version; 59 struct mpi3_comp_image_version fw_version; 60 __le32 ioc_capabilities; 61 u8 ioc_number; 62 u8 who_init; 63 __le16 max_msix_vectors; 64 __le16 max_outstanding_requests; 65 __le16 product_id; 66 __le16 ioc_request_frame_size; 67 __le16 reply_frame_size; 68 __le16 ioc_exceptions; 69 __le16 max_persistent_id; 70 u8 sge_modifier_mask; 71 u8 sge_modifier_value; 72 u8 sge_modifier_shift; 73 u8 protocol_flags; 74 __le16 max_sas_initiators; 75 __le16 max_data_length; 76 __le16 max_sas_expanders; 77 __le16 max_enclosures; 78 __le16 min_dev_handle; 79 __le16 max_dev_handle; 80 __le16 max_pcie_switches; 81 __le16 max_nvme; 82 __le16 reserved38; 83 __le16 max_vds; 84 __le16 max_host_pds; 85 __le16 max_adv_host_pds; 86 __le16 max_raid_pds; 87 __le16 max_posted_cmd_buffers; 88 __le32 flags; 89 __le16 max_operational_request_queues; 90 __le16 max_operational_reply_queues; 91 __le16 shutdown_timeout; 92 __le16 reserved4e; 93 __le32 diag_trace_size; 94 __le32 diag_fw_size; 95 __le32 diag_driver_size; 96 u8 max_host_pd_ns_count; 97 u8 max_adv_host_pd_ns_count; 98 u8 max_raidpd_ns_count; 99 u8 max_devices_per_throttle_group; 100 __le16 io_throttle_data_length; 101 __le16 max_io_throttle_group; 102 __le16 io_throttle_low; 103 __le16 io_throttle_high; 104 __le32 diag_fdl_size; 105 __le32 diag_tty_size; 106 }; 107 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000) 108 #define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000) 109 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x80000000) 110 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600) 111 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000) 112 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200) 113 #define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_SUPPORTED (0x00000100) 114 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED (0x00000080) 115 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_SUPPORTED (0x00000040) 116 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_SUPPORTED (0x00000020) 117 #define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_SUPPORTED (0x00000010) 118 #define MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED (0x00000008) 119 #define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED (0x00000002) 120 #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001) 121 #define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000) 122 #define MPI3_IOCFACTS_PID_TYPE_SHIFT (12) 123 #define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00) 124 #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8) 125 #define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff) 126 #define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0) 127 #define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0x2000) 128 #define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000) 129 #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800) 130 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700) 131 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000) 132 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100) 133 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200) 134 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0x0300) 135 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0400) 136 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0500) 137 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0x0600) 138 #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080) 139 #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040) 140 #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020) 141 #define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010) 142 #define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008) 143 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001) 144 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000) 145 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001) 146 #define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010) 147 #define MPI3_IOCFACTS_PROTOCOL_SATA (0x0008) 148 #define MPI3_IOCFACTS_PROTOCOL_NVME (0x0004) 149 #define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 150 #define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 151 #define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED (0x0000) 152 #define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000) 153 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000ff00) 154 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8) 155 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030) 156 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000) 157 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010) 158 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020) 159 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000f) 160 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000) 161 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002) 162 #define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000) 163 #define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000) 164 #define MPI3_IOCFACTS_DIAGFDLSIZE_NOT_SUPPORTED (0x00000000) 165 #define MPI3_IOCFACTS_DIAGTTYSIZE_NOT_SUPPORTED (0x00000000) 166 struct mpi3_mgmt_passthrough_request { 167 __le16 host_tag; 168 u8 ioc_use_only02; 169 u8 function; 170 __le16 ioc_use_only04; 171 u8 ioc_use_only06; 172 u8 msg_flags; 173 __le16 change_count; 174 __le16 reserved0a; 175 __le32 reserved0c[5]; 176 union mpi3_sge_union command_sgl; 177 union mpi3_sge_union response_sgl; 178 }; 179 180 struct mpi3_create_request_queue_request { 181 __le16 host_tag; 182 u8 ioc_use_only02; 183 u8 function; 184 __le16 ioc_use_only04; 185 u8 ioc_use_only06; 186 u8 msg_flags; 187 __le16 change_count; 188 u8 flags; 189 u8 burst; 190 __le16 size; 191 __le16 queue_id; 192 __le16 reply_queue_id; 193 __le16 reserved12; 194 __le32 reserved14; 195 __le64 base_address; 196 }; 197 198 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 199 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 200 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 201 #define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2) 202 struct mpi3_delete_request_queue_request { 203 __le16 host_tag; 204 u8 ioc_use_only02; 205 u8 function; 206 __le16 ioc_use_only04; 207 u8 ioc_use_only06; 208 u8 msg_flags; 209 __le16 change_count; 210 __le16 queue_id; 211 }; 212 213 struct mpi3_create_reply_queue_request { 214 __le16 host_tag; 215 u8 ioc_use_only02; 216 u8 function; 217 __le16 ioc_use_only04; 218 u8 ioc_use_only06; 219 u8 msg_flags; 220 __le16 change_count; 221 u8 flags; 222 u8 reserved0b; 223 __le16 size; 224 __le16 queue_id; 225 __le16 msix_index; 226 __le16 reserved12; 227 __le32 reserved14; 228 __le64 base_address; 229 }; 230 231 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 232 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 233 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 234 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0x02) 235 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01) 236 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00) 237 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01) 238 #define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2) 239 struct mpi3_delete_reply_queue_request { 240 __le16 host_tag; 241 u8 ioc_use_only02; 242 u8 function; 243 __le16 ioc_use_only04; 244 u8 ioc_use_only06; 245 u8 msg_flags; 246 __le16 change_count; 247 __le16 queue_id; 248 }; 249 250 struct mpi3_port_enable_request { 251 __le16 host_tag; 252 u8 ioc_use_only02; 253 u8 function; 254 __le16 ioc_use_only04; 255 u8 ioc_use_only06; 256 u8 msg_flags; 257 __le16 change_count; 258 __le16 reserved0a; 259 }; 260 261 #define MPI3_EVENT_LOG_DATA (0x01) 262 #define MPI3_EVENT_CHANGE (0x02) 263 #define MPI3_EVENT_GPIO_INTERRUPT (0x04) 264 #define MPI3_EVENT_CABLE_MGMT (0x06) 265 #define MPI3_EVENT_DEVICE_ADDED (0x07) 266 #define MPI3_EVENT_DEVICE_INFO_CHANGED (0x08) 267 #define MPI3_EVENT_PREPARE_FOR_RESET (0x09) 268 #define MPI3_EVENT_COMP_IMAGE_ACT_START (0x0a) 269 #define MPI3_EVENT_ENCL_DEVICE_ADDED (0x0b) 270 #define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x0c) 271 #define MPI3_EVENT_DEVICE_STATUS_CHANGE (0x0d) 272 #define MPI3_EVENT_ENERGY_PACK_CHANGE (0x0e) 273 #define MPI3_EVENT_SAS_DISCOVERY (0x11) 274 #define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0x12) 275 #define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0x13) 276 #define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x14) 277 #define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0x15) 278 #define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x16) 279 #define MPI3_EVENT_SAS_PHY_COUNTER (0x18) 280 #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19) 281 #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20) 282 #define MPI3_EVENT_PCIE_ENUMERATION (0x22) 283 #define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0x23) 284 #define MPI3_EVENT_HARD_RESET_RECEIVED (0x40) 285 #define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0x50) 286 #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60) 287 #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f) 288 #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4) 289 struct mpi3_event_notification_request { 290 __le16 host_tag; 291 u8 ioc_use_only02; 292 u8 function; 293 __le16 ioc_use_only04; 294 u8 ioc_use_only06; 295 u8 msg_flags; 296 __le16 change_count; 297 __le16 reserved0a; 298 __le16 sas_broadcast_primitive_masks; 299 __le16 sas_notify_primitive_masks; 300 __le32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 301 }; 302 303 struct mpi3_event_notification_reply { 304 __le16 host_tag; 305 u8 ioc_use_only02; 306 u8 function; 307 __le16 ioc_use_only04; 308 u8 ioc_use_only06; 309 u8 msg_flags; 310 __le16 ioc_use_only08; 311 __le16 ioc_status; 312 __le32 ioc_log_info; 313 u8 event_data_length; 314 u8 event; 315 __le16 ioc_change_count; 316 __le32 event_context; 317 __le32 event_data[1]; 318 }; 319 320 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01) 321 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01) 322 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00) 323 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02) 324 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00) 325 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02) 326 struct mpi3_event_data_gpio_interrupt { 327 u8 gpio_num; 328 u8 reserved01[3]; 329 }; 330 struct mpi3_event_data_cable_management { 331 __le32 active_cable_power_requirement; 332 u8 status; 333 u8 receptacle_id; 334 __le16 reserved06; 335 }; 336 337 #define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0xffffffff) 338 #define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0x00) 339 #define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0x01) 340 #define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0x02) 341 struct mpi3_event_ack_request { 342 __le16 host_tag; 343 u8 ioc_use_only02; 344 u8 function; 345 __le16 ioc_use_only04; 346 u8 ioc_use_only06; 347 u8 msg_flags; 348 __le16 change_count; 349 __le16 reserved0a; 350 u8 event; 351 u8 reserved0d[3]; 352 __le32 event_context; 353 }; 354 355 struct mpi3_event_data_prepare_for_reset { 356 u8 reason_code; 357 u8 reserved01; 358 __le16 reserved02; 359 }; 360 361 #define MPI3_EVENT_PREPARE_RESET_RC_START (0x01) 362 #define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0x02) 363 struct mpi3_event_data_comp_image_activation { 364 __le32 reserved00; 365 }; 366 367 struct mpi3_event_data_device_status_change { 368 __le16 task_tag; 369 u8 reason_code; 370 u8 io_unit_port; 371 __le16 parent_dev_handle; 372 __le16 dev_handle; 373 __le64 wwid; 374 u8 lun[8]; 375 }; 376 377 #define MPI3_EVENT_DEV_STAT_RC_MOVED (0x01) 378 #define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0x02) 379 #define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0x03) 380 #define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0x04) 381 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0x20) 382 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0x21) 383 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0x22) 384 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0x23) 385 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0x24) 386 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0x25) 387 #define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x30) 388 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0x40) 389 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0x41) 390 #define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0x50) 391 struct mpi3_event_data_energy_pack_change { 392 __le32 reserved00; 393 __le16 shutdown_timeout; 394 __le16 reserved06; 395 }; 396 397 struct mpi3_event_data_sas_discovery { 398 u8 flags; 399 u8 reason_code; 400 u8 io_unit_port; 401 u8 reserved03; 402 __le32 discovery_status; 403 }; 404 405 #define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0x02) 406 #define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0x01) 407 #define MPI3_EVENT_SAS_DISC_RC_STARTED (0x01) 408 #define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0x02) 409 #define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0x80000000) 410 #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000) 411 #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000) 412 #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000) 413 #define MPI3_SAS_DISC_STATUS_INVALID_CEI (0x00010000) 414 #define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0x00008000) 415 #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000) 416 #define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0x00002000) 417 #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000) 418 #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800) 419 #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400) 420 #define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0x00000200) 421 #define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0x00000100) 422 #define MPI3_SAS_DISC_STATUS_TABLE_LINK (0x00000080) 423 #define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0x00000040) 424 #define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0x00000020) 425 #define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0x00000010) 426 #define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0x00000008) 427 #define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0x00000004) 428 #define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0x00000002) 429 #define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0x00000001) 430 struct mpi3_event_data_sas_broadcast_primitive { 431 u8 phy_num; 432 u8 io_unit_port; 433 u8 port_width; 434 u8 primitive; 435 }; 436 437 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0x01) 438 #define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0x02) 439 #define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0x03) 440 #define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 441 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0x05) 442 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0x06) 443 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0x07) 444 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0x08) 445 struct mpi3_event_data_sas_notify_primitive { 446 u8 phy_num; 447 u8 io_unit_port; 448 u8 reserved02; 449 u8 primitive; 450 }; 451 452 #define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0x01) 453 #define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0x02) 454 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0x03) 455 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0x04) 456 #ifndef MPI3_EVENT_SAS_TOPO_PHY_COUNT 457 #define MPI3_EVENT_SAS_TOPO_PHY_COUNT (1) 458 #endif 459 struct mpi3_event_sas_topo_phy_entry { 460 __le16 attached_dev_handle; 461 u8 link_rate; 462 u8 status; 463 }; 464 465 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xf0) 466 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 467 #define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0x0f) 468 #define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 469 #define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 470 #define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 471 #define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 472 #define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 473 #define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 474 #define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 475 #define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 476 #define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0a) 477 #define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0b) 478 #define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0c) 479 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0xc0) 480 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6) 481 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0x00) 482 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40) 483 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80) 484 #define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0f) 485 #define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02) 486 #define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03) 487 #define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04) 488 #define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0x05) 489 #define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0x06) 490 struct mpi3_event_data_sas_topology_change_list { 491 __le16 enclosure_handle; 492 __le16 expander_dev_handle; 493 u8 num_phys; 494 u8 reserved05[3]; 495 u8 num_entries; 496 u8 start_phy_num; 497 u8 exp_status; 498 u8 io_unit_port; 499 struct mpi3_event_sas_topo_phy_entry phy_entry[MPI3_EVENT_SAS_TOPO_PHY_COUNT]; 500 }; 501 502 #define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 503 #define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 504 #define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 505 #define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 506 struct mpi3_event_data_sas_phy_counter { 507 __le64 time_stamp; 508 __le32 reserved08; 509 u8 phy_event_code; 510 u8 phy_num; 511 __le16 reserved0e; 512 __le32 phy_event_info; 513 u8 counter_type; 514 u8 threshold_window; 515 u8 time_units; 516 u8 reserved17; 517 __le32 event_threshold; 518 __le16 threshold_flags; 519 __le16 reserved1e; 520 }; 521 522 struct mpi3_event_data_sas_device_disc_err { 523 __le16 dev_handle; 524 u8 reason_code; 525 u8 io_unit_port; 526 __le32 reserved04; 527 __le64 sas_address; 528 }; 529 530 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0x01) 531 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0x02) 532 struct mpi3_event_data_pcie_enumeration { 533 u8 flags; 534 u8 reason_code; 535 u8 io_unit_port; 536 u8 reserved03; 537 __le32 enumeration_status; 538 }; 539 540 #define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0x02) 541 #define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0x01) 542 #define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0x01) 543 #define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) 544 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0x80000000) 545 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) 546 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) 547 #define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) 548 #ifndef MPI3_EVENT_PCIE_TOPO_PORT_COUNT 549 #define MPI3_EVENT_PCIE_TOPO_PORT_COUNT (1) 550 #endif 551 struct mpi3_event_pcie_topo_port_entry { 552 __le16 attached_dev_handle; 553 u8 port_status; 554 u8 reserved03; 555 u8 current_port_info; 556 u8 reserved05; 557 u8 previous_port_info; 558 u8 reserved07; 559 }; 560 561 #define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) 562 #define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) 563 #define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) 564 #define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) 565 #define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06) 566 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xf0) 567 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) 568 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10) 569 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20) 570 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30) 571 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40) 572 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50) 573 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0f) 574 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 575 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) 576 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) 577 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) 578 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) 579 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) 580 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0x06) 581 struct mpi3_event_data_pcie_topology_change_list { 582 __le16 enclosure_handle; 583 __le16 switch_dev_handle; 584 u8 num_ports; 585 u8 reserved05[3]; 586 u8 num_entries; 587 u8 start_port_num; 588 u8 switch_status; 589 u8 io_unit_port; 590 __le32 reserved0c; 591 struct mpi3_event_pcie_topo_port_entry port_entry[MPI3_EVENT_PCIE_TOPO_PORT_COUNT]; 592 }; 593 594 #define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) 595 #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) 596 #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) 597 #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) 598 struct mpi3_event_data_pcie_error_threshold { 599 __le64 timestamp; 600 u8 reason_code; 601 u8 port; 602 __le16 switch_dev_handle; 603 u8 error; 604 u8 action; 605 __le16 threshold_count; 606 __le16 attached_dev_handle; 607 __le16 reserved12; 608 __le32 reserved14; 609 }; 610 611 #define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0x00) 612 #define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0x01) 613 struct mpi3_event_data_sas_init_dev_status_change { 614 u8 reason_code; 615 u8 io_unit_port; 616 __le16 dev_handle; 617 __le32 reserved04; 618 __le64 sas_address; 619 }; 620 621 #define MPI3_EVENT_SAS_INIT_RC_ADDED (0x01) 622 #define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 623 struct mpi3_event_data_sas_init_table_overflow { 624 __le16 max_init; 625 __le16 current_init; 626 __le32 reserved04; 627 __le64 sas_address; 628 }; 629 630 struct mpi3_event_data_hard_reset_received { 631 u8 reserved00; 632 u8 io_unit_port; 633 __le16 reserved02; 634 }; 635 636 struct mpi3_event_data_diag_buffer_status_change { 637 u8 type; 638 u8 reason_code; 639 __le16 reserved02; 640 __le32 reserved04; 641 }; 642 643 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01) 644 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02) 645 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03) 646 #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) 647 #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) 648 #define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) 649 #define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040) 650 #define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020) 651 #define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010) 652 #define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008) 653 #define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004) 654 #define MPI3_PEL_LOCALE_FLAGS_PD (0x0002) 655 #define MPI3_PEL_LOCALE_FLAGS_VD (0x0001) 656 #define MPI3_PEL_CLASS_DEBUG (0x00) 657 #define MPI3_PEL_CLASS_PROGRESS (0x01) 658 #define MPI3_PEL_CLASS_INFORMATIONAL (0x02) 659 #define MPI3_PEL_CLASS_WARNING (0x03) 660 #define MPI3_PEL_CLASS_CRITICAL (0x04) 661 #define MPI3_PEL_CLASS_FATAL (0x05) 662 #define MPI3_PEL_CLASS_FAULT (0x06) 663 #define MPI3_PEL_CLEARTYPE_CLEAR (0x00) 664 #define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00) 665 #define MPI3_PEL_ACTION_GET_SEQNUM (0x01) 666 #define MPI3_PEL_ACTION_MARK_CLEAR (0x02) 667 #define MPI3_PEL_ACTION_GET_LOG (0x03) 668 #define MPI3_PEL_ACTION_GET_COUNT (0x04) 669 #define MPI3_PEL_ACTION_WAIT (0x05) 670 #define MPI3_PEL_ACTION_ABORT (0x06) 671 #define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0x07) 672 #define MPI3_PEL_ACTION_ACKNOWLEDGE (0x08) 673 #define MPI3_PEL_STATUS_SUCCESS (0x00) 674 #define MPI3_PEL_STATUS_NOT_FOUND (0x01) 675 #define MPI3_PEL_STATUS_ABORTED (0x02) 676 #define MPI3_PEL_STATUS_NOT_READY (0x03) 677 struct mpi3_pel_seq { 678 __le32 newest; 679 __le32 oldest; 680 __le32 clear; 681 __le32 shutdown; 682 __le32 boot; 683 __le32 last_acknowledged; 684 }; 685 686 struct mpi3_pel_entry { 687 __le64 time_stamp; 688 __le32 sequence_number; 689 __le16 log_code; 690 __le16 arg_type; 691 __le16 locale; 692 u8 class; 693 u8 flags; 694 u8 ext_num; 695 u8 num_exts; 696 u8 arg_data_size; 697 u8 fixed_format_strings_size; 698 __le32 reserved18[2]; 699 __le32 pel_info[24]; 700 }; 701 702 #define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0x02) 703 #define MPI3_PEL_FLAGS_ACK_NEEDED (0x01) 704 struct mpi3_pel_list { 705 __le32 log_count; 706 __le32 reserved04; 707 struct mpi3_pel_entry entry[1]; 708 }; 709 710 struct mpi3_pel_arg_map { 711 u8 arg_type; 712 u8 length; 713 __le16 start_location; 714 }; 715 716 #define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0x00) 717 #define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0x01) 718 #define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0x02) 719 #define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0x03) 720 struct mpi3_pel_print_string { 721 __le16 log_code; 722 __le16 string_length; 723 u8 num_arg_map; 724 u8 reserved05[3]; 725 struct mpi3_pel_arg_map arg_map[1]; 726 }; 727 728 struct mpi3_pel_print_string_list { 729 __le32 num_print_strings; 730 __le32 residual_bytes_remain; 731 __le32 reserved08[2]; 732 struct mpi3_pel_print_string print_string[1]; 733 }; 734 735 #ifndef MPI3_PEL_ACTION_SPECIFIC_MAX 736 #define MPI3_PEL_ACTION_SPECIFIC_MAX (1) 737 #endif 738 struct mpi3_pel_request { 739 __le16 host_tag; 740 u8 ioc_use_only02; 741 u8 function; 742 __le16 ioc_use_only04; 743 u8 ioc_use_only06; 744 u8 msg_flags; 745 __le16 change_count; 746 u8 action; 747 u8 reserved0b; 748 __le32 action_specific[MPI3_PEL_ACTION_SPECIFIC_MAX]; 749 }; 750 751 struct mpi3_pel_req_action_get_sequence_numbers { 752 __le16 host_tag; 753 u8 ioc_use_only02; 754 u8 function; 755 __le16 ioc_use_only04; 756 u8 ioc_use_only06; 757 u8 msg_flags; 758 __le16 change_count; 759 u8 action; 760 u8 reserved0b; 761 __le32 reserved0c[5]; 762 union mpi3_sge_union sgl; 763 }; 764 765 struct mpi3_pel_req_action_clear_log_marker { 766 __le16 host_tag; 767 u8 ioc_use_only02; 768 u8 function; 769 __le16 ioc_use_only04; 770 u8 ioc_use_only06; 771 u8 msg_flags; 772 __le16 change_count; 773 u8 action; 774 u8 reserved0b; 775 u8 clear_type; 776 u8 reserved0d[3]; 777 }; 778 779 struct mpi3_pel_req_action_get_log { 780 __le16 host_tag; 781 u8 ioc_use_only02; 782 u8 function; 783 __le16 ioc_use_only04; 784 u8 ioc_use_only06; 785 u8 msg_flags; 786 __le16 change_count; 787 u8 action; 788 u8 reserved0b; 789 __le32 starting_sequence_number; 790 __le16 locale; 791 u8 class; 792 u8 reserved13; 793 __le32 reserved14[3]; 794 union mpi3_sge_union sgl; 795 }; 796 797 struct mpi3_pel_req_action_get_count { 798 __le16 host_tag; 799 u8 ioc_use_only02; 800 u8 function; 801 __le16 ioc_use_only04; 802 u8 ioc_use_only06; 803 u8 msg_flags; 804 __le16 change_count; 805 u8 action; 806 u8 reserved0b; 807 __le32 starting_sequence_number; 808 __le16 locale; 809 u8 class; 810 u8 reserved13; 811 __le32 reserved14[3]; 812 union mpi3_sge_union sgl; 813 }; 814 815 struct mpi3_pel_req_action_wait { 816 __le16 host_tag; 817 u8 ioc_use_only02; 818 u8 function; 819 __le16 ioc_use_only04; 820 u8 ioc_use_only06; 821 u8 msg_flags; 822 __le16 change_count; 823 u8 action; 824 u8 reserved0b; 825 __le32 starting_sequence_number; 826 __le16 locale; 827 u8 class; 828 u8 reserved13; 829 __le16 wait_time; 830 __le16 reserved16; 831 __le32 reserved18[2]; 832 }; 833 834 struct mpi3_pel_req_action_abort { 835 __le16 host_tag; 836 u8 ioc_use_only02; 837 u8 function; 838 __le16 ioc_use_only04; 839 u8 ioc_use_only06; 840 u8 msg_flags; 841 __le16 change_count; 842 u8 action; 843 u8 reserved0b; 844 __le32 reserved0c; 845 __le16 abort_host_tag; 846 __le16 reserved12; 847 __le32 reserved14; 848 }; 849 850 struct mpi3_pel_req_action_get_print_strings { 851 __le16 host_tag; 852 u8 ioc_use_only02; 853 u8 function; 854 __le16 ioc_use_only04; 855 u8 ioc_use_only06; 856 u8 msg_flags; 857 __le16 change_count; 858 u8 action; 859 u8 reserved0b; 860 __le32 reserved0c; 861 __le16 start_log_code; 862 __le16 reserved12; 863 __le32 reserved14[3]; 864 union mpi3_sge_union sgl; 865 }; 866 867 struct mpi3_pel_req_action_acknowledge { 868 __le16 host_tag; 869 u8 ioc_use_only02; 870 u8 function; 871 __le16 ioc_use_only04; 872 u8 ioc_use_only06; 873 u8 msg_flags; 874 __le16 change_count; 875 u8 action; 876 u8 reserved0b; 877 __le32 sequence_number; 878 __le32 reserved10; 879 }; 880 881 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03) 882 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00) 883 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01) 884 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02) 885 struct mpi3_pel_reply { 886 __le16 host_tag; 887 u8 ioc_use_only02; 888 u8 function; 889 __le16 ioc_use_only04; 890 u8 ioc_use_only06; 891 u8 msg_flags; 892 __le16 ioc_use_only08; 893 __le16 ioc_status; 894 __le32 ioc_log_info; 895 u8 action; 896 u8 reserved11; 897 __le16 reserved12; 898 __le16 pe_log_status; 899 __le16 reserved16; 900 __le32 transfer_length; 901 }; 902 903 struct mpi3_ci_download_request { 904 __le16 host_tag; 905 u8 ioc_use_only02; 906 u8 function; 907 __le16 ioc_use_only04; 908 u8 ioc_use_only06; 909 u8 msg_flags; 910 __le16 change_count; 911 u8 action; 912 u8 reserved0b; 913 __le32 signature1; 914 __le32 total_image_size; 915 __le32 image_offset; 916 __le32 segment_size; 917 __le32 reserved1c; 918 union mpi3_sge_union sgl; 919 }; 920 921 #define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0x80) 922 #define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40) 923 #define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20) 924 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03) 925 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00) 926 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01) 927 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02) 928 #define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0x01) 929 #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02) 930 #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03) 931 #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04) 932 #define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0x05) 933 struct mpi3_ci_download_reply { 934 __le16 host_tag; 935 u8 ioc_use_only02; 936 u8 function; 937 __le16 ioc_use_only04; 938 u8 ioc_use_only06; 939 u8 msg_flags; 940 __le16 ioc_use_only08; 941 __le16 ioc_status; 942 __le32 ioc_log_info; 943 u8 flags; 944 u8 cache_dirty; 945 u8 pending_count; 946 u8 reserved13; 947 }; 948 949 #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80) 950 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_FAILURE (0x40) 951 #define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20) 952 #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10) 953 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e) 954 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00) 955 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02) 956 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04) 957 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0x06) 958 #define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0x01) 959 struct mpi3_ci_upload_request { 960 __le16 host_tag; 961 u8 ioc_use_only02; 962 u8 function; 963 __le16 ioc_use_only04; 964 u8 ioc_use_only06; 965 u8 msg_flags; 966 __le16 change_count; 967 __le16 reserved0a; 968 __le32 signature1; 969 __le32 reserved10; 970 __le32 image_offset; 971 __le32 segment_size; 972 __le32 reserved1c; 973 union mpi3_sge_union sgl; 974 }; 975 976 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01) 977 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00) 978 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01) 979 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02) 980 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00) 981 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02) 982 #define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01) 983 #define MPI3_CTRL_OP_LOOKUP_MAPPING (0x02) 984 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0x04) 985 #define MPI3_CTRL_OP_GET_TIMESTAMP (0x05) 986 #define MPI3_CTRL_OP_GET_IOC_CHANGE_COUNT (0x06) 987 #define MPI3_CTRL_OP_CHANGE_PROFILE (0x07) 988 #define MPI3_CTRL_OP_REMOVE_DEVICE (0x10) 989 #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11) 990 #define MPI3_CTRL_OP_HIDDEN_ACK (0x12) 991 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0x13) 992 #define MPI3_CTRL_OP_SEND_SAS_PRIMITIVE (0x20) 993 #define MPI3_CTRL_OP_SAS_PHY_CONTROL (0x21) 994 #define MPI3_CTRL_OP_READ_INTERNAL_BUS (0x23) 995 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0x24) 996 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0x30) 997 #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00) 998 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00) 999 #define MPI3_CTRL_OP_CHANGE_PROFILE_PARAM8_PROFILE_ID_INDEX (0x00) 1000 #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00) 1001 #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00) 1002 #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00) 1003 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0x00) 1004 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PHY_INDEX (0x00) 1005 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PRIMSEQ_INDEX (0x01) 1006 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM32_PRIMITIVE_INDEX (0x00) 1007 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0x00) 1008 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0x01) 1009 #define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) 1010 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) 1011 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0x00) 1012 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0x00) 1013 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0x01) 1014 #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 1015 #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 1016 #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 1017 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0x04) 1018 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0) 1019 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0) 1020 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0) 1021 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0) 1022 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0) 1023 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0) 1024 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0) 1025 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1) 1026 #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0) 1027 #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0) 1028 #define MPI3_CTRL_GET_IOC_CHANGE_COUNT_VALUE16_CHANGECOUNT_INDEX (0) 1029 #define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0) 1030 #define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01) 1031 #define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03) 1032 #define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06) 1033 #define MPI3_CTRL_ACTION_NOP (0x00) 1034 #define MPI3_CTRL_ACTION_LINK_RESET (0x01) 1035 #define MPI3_CTRL_ACTION_HARD_RESET (0x02) 1036 #define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0x05) 1037 struct mpi3_iounit_control_request { 1038 __le16 host_tag; 1039 u8 ioc_use_only02; 1040 u8 function; 1041 __le16 ioc_use_only04; 1042 u8 ioc_use_only06; 1043 u8 msg_flags; 1044 __le16 change_count; 1045 u8 reserved0a; 1046 u8 operation; 1047 __le32 reserved0c; 1048 __le64 param64[2]; 1049 __le32 param32[4]; 1050 __le16 param16[4]; 1051 u8 param8[8]; 1052 }; 1053 1054 struct mpi3_iounit_control_reply { 1055 __le16 host_tag; 1056 u8 ioc_use_only02; 1057 u8 function; 1058 __le16 ioc_use_only04; 1059 u8 ioc_use_only06; 1060 u8 msg_flags; 1061 __le16 ioc_use_only08; 1062 __le16 ioc_status; 1063 __le32 ioc_log_info; 1064 __le64 value64[2]; 1065 __le32 value32[4]; 1066 __le16 value16[4]; 1067 u8 value8[8]; 1068 }; 1069 #endif 1070