1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2016-2023 Broadcom Inc. All rights reserved. 4 */ 5 #ifndef MPI30_IOC_H 6 #define MPI30_IOC_H 1 7 struct mpi3_ioc_init_request { 8 __le16 host_tag; 9 u8 ioc_use_only02; 10 u8 function; 11 __le16 ioc_use_only04; 12 u8 ioc_use_only06; 13 u8 msg_flags; 14 __le16 change_count; 15 __le16 reserved0a; 16 union mpi3_version_union mpi_version; 17 __le64 time_stamp; 18 u8 reserved18; 19 u8 who_init; 20 __le16 reserved1a; 21 __le16 reply_free_queue_depth; 22 __le16 reserved1e; 23 __le64 reply_free_queue_address; 24 __le32 reserved28; 25 __le16 sense_buffer_free_queue_depth; 26 __le16 sense_buffer_length; 27 __le64 sense_buffer_free_queue_address; 28 __le64 driver_information_address; 29 }; 30 31 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03) 32 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00) 33 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01) 34 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02) 35 #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03) 36 #define MPI3_WHOINIT_NOT_INITIALIZED (0x00) 37 #define MPI3_WHOINIT_ROM_BIOS (0x02) 38 #define MPI3_WHOINIT_HOST_DRIVER (0x03) 39 #define MPI3_WHOINIT_MANUFACTURER (0x04) 40 41 struct mpi3_ioc_facts_request { 42 __le16 host_tag; 43 u8 ioc_use_only02; 44 u8 function; 45 __le16 ioc_use_only04; 46 u8 ioc_use_only06; 47 u8 msg_flags; 48 __le16 change_count; 49 __le16 reserved0a; 50 __le32 reserved0c; 51 union mpi3_sge_union sgl; 52 }; 53 54 struct mpi3_ioc_facts_data { 55 __le16 ioc_facts_data_length; 56 __le16 reserved02; 57 union mpi3_version_union mpi_version; 58 struct mpi3_comp_image_version fw_version; 59 __le32 ioc_capabilities; 60 u8 ioc_number; 61 u8 who_init; 62 __le16 max_msix_vectors; 63 __le16 max_outstanding_requests; 64 __le16 product_id; 65 __le16 ioc_request_frame_size; 66 __le16 reply_frame_size; 67 __le16 ioc_exceptions; 68 __le16 max_persistent_id; 69 u8 sge_modifier_mask; 70 u8 sge_modifier_value; 71 u8 sge_modifier_shift; 72 u8 protocol_flags; 73 __le16 max_sas_initiators; 74 __le16 max_data_length; 75 __le16 max_sas_expanders; 76 __le16 max_enclosures; 77 __le16 min_dev_handle; 78 __le16 max_dev_handle; 79 __le16 max_pcie_switches; 80 __le16 max_nvme; 81 __le16 reserved38; 82 __le16 max_vds; 83 __le16 max_host_pds; 84 __le16 max_adv_host_pds; 85 __le16 max_raid_pds; 86 __le16 max_posted_cmd_buffers; 87 __le32 flags; 88 __le16 max_operational_request_queues; 89 __le16 max_operational_reply_queues; 90 __le16 shutdown_timeout; 91 __le16 reserved4e; 92 __le32 diag_trace_size; 93 __le32 diag_fw_size; 94 __le32 diag_driver_size; 95 u8 max_host_pd_ns_count; 96 u8 max_adv_host_pd_ns_count; 97 u8 max_raidpd_ns_count; 98 u8 max_devices_per_throttle_group; 99 __le16 io_throttle_data_length; 100 __le16 max_io_throttle_group; 101 __le16 io_throttle_low; 102 __le16 io_throttle_high; 103 }; 104 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000) 105 #define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000) 106 #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x80000000) 107 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600) 108 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000) 109 #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200) 110 #define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_CAPABLE (0x00000100) 111 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_ENABLED (0x00000080) 112 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_ENABLED (0x00000040) 113 #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_ENABLED (0x00000020) 114 #define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_ENABLED (0x00000010) 115 #define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE (0x00000008) 116 #define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED (0x00000002) 117 #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001) 118 #define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000) 119 #define MPI3_IOCFACTS_PID_TYPE_SHIFT (12) 120 #define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00) 121 #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8) 122 #define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff) 123 #define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0) 124 #define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0x2000) 125 #define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000) 126 #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800) 127 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700) 128 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000) 129 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100) 130 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200) 131 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0x0300) 132 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0400) 133 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0500) 134 #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0x0600) 135 #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080) 136 #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040) 137 #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020) 138 #define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010) 139 #define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008) 140 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001) 141 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000) 142 #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001) 143 #define MPI3_IOCFACTS_PROTOCOL_SAS (0x0010) 144 #define MPI3_IOCFACTS_PROTOCOL_SATA (0x0008) 145 #define MPI3_IOCFACTS_PROTOCOL_NVME (0x0004) 146 #define MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 147 #define MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 148 #define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED (0x0000) 149 #define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000) 150 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000ff00) 151 #define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8) 152 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030) 153 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000) 154 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010) 155 #define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020) 156 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000f) 157 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000) 158 #define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002) 159 #define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000) 160 #define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000) 161 struct mpi3_mgmt_passthrough_request { 162 __le16 host_tag; 163 u8 ioc_use_only02; 164 u8 function; 165 __le16 ioc_use_only04; 166 u8 ioc_use_only06; 167 u8 msg_flags; 168 __le16 change_count; 169 __le16 reserved0a; 170 __le32 reserved0c[5]; 171 union mpi3_sge_union command_sgl; 172 union mpi3_sge_union response_sgl; 173 }; 174 175 struct mpi3_create_request_queue_request { 176 __le16 host_tag; 177 u8 ioc_use_only02; 178 u8 function; 179 __le16 ioc_use_only04; 180 u8 ioc_use_only06; 181 u8 msg_flags; 182 __le16 change_count; 183 u8 flags; 184 u8 burst; 185 __le16 size; 186 __le16 queue_id; 187 __le16 reply_queue_id; 188 __le16 reserved12; 189 __le32 reserved14; 190 __le64 base_address; 191 }; 192 193 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 194 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 195 #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 196 #define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2) 197 struct mpi3_delete_request_queue_request { 198 __le16 host_tag; 199 u8 ioc_use_only02; 200 u8 function; 201 __le16 ioc_use_only04; 202 u8 ioc_use_only06; 203 u8 msg_flags; 204 __le16 change_count; 205 __le16 queue_id; 206 }; 207 208 struct mpi3_create_reply_queue_request { 209 __le16 host_tag; 210 u8 ioc_use_only02; 211 u8 function; 212 __le16 ioc_use_only04; 213 u8 ioc_use_only06; 214 u8 msg_flags; 215 __le16 change_count; 216 u8 flags; 217 u8 reserved0b; 218 __le16 size; 219 __le16 queue_id; 220 __le16 msix_index; 221 __le16 reserved12; 222 __le32 reserved14; 223 __le64 base_address; 224 }; 225 226 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80) 227 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) 228 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) 229 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0x02) 230 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01) 231 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00) 232 #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01) 233 #define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2) 234 struct mpi3_delete_reply_queue_request { 235 __le16 host_tag; 236 u8 ioc_use_only02; 237 u8 function; 238 __le16 ioc_use_only04; 239 u8 ioc_use_only06; 240 u8 msg_flags; 241 __le16 change_count; 242 __le16 queue_id; 243 }; 244 245 struct mpi3_port_enable_request { 246 __le16 host_tag; 247 u8 ioc_use_only02; 248 u8 function; 249 __le16 ioc_use_only04; 250 u8 ioc_use_only06; 251 u8 msg_flags; 252 __le16 change_count; 253 __le16 reserved0a; 254 }; 255 256 #define MPI3_EVENT_LOG_DATA (0x01) 257 #define MPI3_EVENT_CHANGE (0x02) 258 #define MPI3_EVENT_GPIO_INTERRUPT (0x04) 259 #define MPI3_EVENT_CABLE_MGMT (0x06) 260 #define MPI3_EVENT_DEVICE_ADDED (0x07) 261 #define MPI3_EVENT_DEVICE_INFO_CHANGED (0x08) 262 #define MPI3_EVENT_PREPARE_FOR_RESET (0x09) 263 #define MPI3_EVENT_COMP_IMAGE_ACT_START (0x0a) 264 #define MPI3_EVENT_ENCL_DEVICE_ADDED (0x0b) 265 #define MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x0c) 266 #define MPI3_EVENT_DEVICE_STATUS_CHANGE (0x0d) 267 #define MPI3_EVENT_ENERGY_PACK_CHANGE (0x0e) 268 #define MPI3_EVENT_SAS_DISCOVERY (0x11) 269 #define MPI3_EVENT_SAS_BROADCAST_PRIMITIVE (0x12) 270 #define MPI3_EVENT_SAS_NOTIFY_PRIMITIVE (0x13) 271 #define MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x14) 272 #define MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW (0x15) 273 #define MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x16) 274 #define MPI3_EVENT_SAS_PHY_COUNTER (0x18) 275 #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19) 276 #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20) 277 #define MPI3_EVENT_PCIE_ENUMERATION (0x22) 278 #define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0x23) 279 #define MPI3_EVENT_HARD_RESET_RECEIVED (0x40) 280 #define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0x50) 281 #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60) 282 #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f) 283 #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4) 284 struct mpi3_event_notification_request { 285 __le16 host_tag; 286 u8 ioc_use_only02; 287 u8 function; 288 __le16 ioc_use_only04; 289 u8 ioc_use_only06; 290 u8 msg_flags; 291 __le16 change_count; 292 __le16 reserved0a; 293 __le16 sas_broadcast_primitive_masks; 294 __le16 sas_notify_primitive_masks; 295 __le32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 296 }; 297 298 struct mpi3_event_notification_reply { 299 __le16 host_tag; 300 u8 ioc_use_only02; 301 u8 function; 302 __le16 ioc_use_only04; 303 u8 ioc_use_only06; 304 u8 msg_flags; 305 __le16 ioc_use_only08; 306 __le16 ioc_status; 307 __le32 ioc_log_info; 308 u8 event_data_length; 309 u8 event; 310 __le16 ioc_change_count; 311 __le32 event_context; 312 __le32 event_data[1]; 313 }; 314 315 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01) 316 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01) 317 #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00) 318 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02) 319 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00) 320 #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02) 321 struct mpi3_event_data_gpio_interrupt { 322 u8 gpio_num; 323 u8 reserved01[3]; 324 }; 325 struct mpi3_event_data_cable_management { 326 __le32 active_cable_power_requirement; 327 u8 status; 328 u8 receptacle_id; 329 __le16 reserved06; 330 }; 331 332 #define MPI3_EVENT_CABLE_MGMT_ACT_CABLE_PWR_INVALID (0xffffffff) 333 #define MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER (0x00) 334 #define MPI3_EVENT_CABLE_MGMT_STATUS_PRESENT (0x01) 335 #define MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED (0x02) 336 struct mpi3_event_ack_request { 337 __le16 host_tag; 338 u8 ioc_use_only02; 339 u8 function; 340 __le16 ioc_use_only04; 341 u8 ioc_use_only06; 342 u8 msg_flags; 343 __le16 change_count; 344 __le16 reserved0a; 345 u8 event; 346 u8 reserved0d[3]; 347 __le32 event_context; 348 }; 349 350 struct mpi3_event_data_prepare_for_reset { 351 u8 reason_code; 352 u8 reserved01; 353 __le16 reserved02; 354 }; 355 356 #define MPI3_EVENT_PREPARE_RESET_RC_START (0x01) 357 #define MPI3_EVENT_PREPARE_RESET_RC_ABORT (0x02) 358 struct mpi3_event_data_comp_image_activation { 359 __le32 reserved00; 360 }; 361 362 struct mpi3_event_data_device_status_change { 363 __le16 task_tag; 364 u8 reason_code; 365 u8 io_unit_port; 366 __le16 parent_dev_handle; 367 __le16 dev_handle; 368 __le64 wwid; 369 u8 lun[8]; 370 }; 371 372 #define MPI3_EVENT_DEV_STAT_RC_MOVED (0x01) 373 #define MPI3_EVENT_DEV_STAT_RC_HIDDEN (0x02) 374 #define MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN (0x03) 375 #define MPI3_EVENT_DEV_STAT_RC_ASYNC_NOTIFICATION (0x04) 376 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT (0x20) 377 #define MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP (0x21) 378 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_STRT (0x22) 379 #define MPI3_EVENT_DEV_STAT_RC_INT_TASK_ABORT_CMP (0x23) 380 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT (0x24) 381 #define MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP (0x25) 382 #define MPI3_EVENT_DEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x30) 383 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_STRT (0x40) 384 #define MPI3_EVENT_DEV_STAT_RC_EXPANDER_REDUCED_FUNC_CMP (0x41) 385 #define MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING (0x50) 386 struct mpi3_event_data_energy_pack_change { 387 __le32 reserved00; 388 __le16 shutdown_timeout; 389 __le16 reserved06; 390 }; 391 392 struct mpi3_event_data_sas_discovery { 393 u8 flags; 394 u8 reason_code; 395 u8 io_unit_port; 396 u8 reserved03; 397 __le32 discovery_status; 398 }; 399 400 #define MPI3_EVENT_SAS_DISC_FLAGS_DEVICE_CHANGE (0x02) 401 #define MPI3_EVENT_SAS_DISC_FLAGS_IN_PROGRESS (0x01) 402 #define MPI3_EVENT_SAS_DISC_RC_STARTED (0x01) 403 #define MPI3_EVENT_SAS_DISC_RC_COMPLETED (0x02) 404 #define MPI3_SAS_DISC_STATUS_MAX_ENCLOSURES_EXCEED (0x80000000) 405 #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000) 406 #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000) 407 #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000) 408 #define MPI3_SAS_DISC_STATUS_INVALID_CEI (0x00010000) 409 #define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0x00008000) 410 #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000) 411 #define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0x00002000) 412 #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000) 413 #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800) 414 #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400) 415 #define MPI3_SAS_DISC_STATUS_TABLE_TO_SUBTRACTIVE_LINK (0x00000200) 416 #define MPI3_SAS_DISC_STATUS_UNSUPPORTED_DEVICE (0x00000100) 417 #define MPI3_SAS_DISC_STATUS_TABLE_LINK (0x00000080) 418 #define MPI3_SAS_DISC_STATUS_SUBTRACTIVE_LINK (0x00000040) 419 #define MPI3_SAS_DISC_STATUS_SMP_CRC_ERROR (0x00000020) 420 #define MPI3_SAS_DISC_STATUS_SMP_FUNCTION_FAILED (0x00000010) 421 #define MPI3_SAS_DISC_STATUS_SMP_TIMEOUT (0x00000008) 422 #define MPI3_SAS_DISC_STATUS_MULTIPLE_PORTS (0x00000004) 423 #define MPI3_SAS_DISC_STATUS_INVALID_SAS_ADDRESS (0x00000002) 424 #define MPI3_SAS_DISC_STATUS_LOOP_DETECTED (0x00000001) 425 struct mpi3_event_data_sas_broadcast_primitive { 426 u8 phy_num; 427 u8 io_unit_port; 428 u8 port_width; 429 u8 primitive; 430 }; 431 432 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE (0x01) 433 #define MPI3_EVENT_BROADCAST_PRIMITIVE_SES (0x02) 434 #define MPI3_EVENT_BROADCAST_PRIMITIVE_EXPANDER (0x03) 435 #define MPI3_EVENT_BROADCAST_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 436 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED3 (0x05) 437 #define MPI3_EVENT_BROADCAST_PRIMITIVE_RESERVED4 (0x06) 438 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE0_RESERVED (0x07) 439 #define MPI3_EVENT_BROADCAST_PRIMITIVE_CHANGE1_RESERVED (0x08) 440 struct mpi3_event_data_sas_notify_primitive { 441 u8 phy_num; 442 u8 io_unit_port; 443 u8 reserved02; 444 u8 primitive; 445 }; 446 447 #define MPI3_EVENT_NOTIFY_PRIMITIVE_ENABLE_SPINUP (0x01) 448 #define MPI3_EVENT_NOTIFY_PRIMITIVE_POWER_LOSS_EXPECTED (0x02) 449 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED1 (0x03) 450 #define MPI3_EVENT_NOTIFY_PRIMITIVE_RESERVED2 (0x04) 451 #ifndef MPI3_EVENT_SAS_TOPO_PHY_COUNT 452 #define MPI3_EVENT_SAS_TOPO_PHY_COUNT (1) 453 #endif 454 struct mpi3_event_sas_topo_phy_entry { 455 __le16 attached_dev_handle; 456 u8 link_rate; 457 u8 status; 458 }; 459 460 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xf0) 461 #define MPI3_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 462 #define MPI3_EVENT_SAS_TOPO_LR_PREV_MASK (0x0f) 463 #define MPI3_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 464 #define MPI3_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 465 #define MPI3_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 466 #define MPI3_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 467 #define MPI3_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 468 #define MPI3_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 469 #define MPI3_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 470 #define MPI3_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 471 #define MPI3_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0a) 472 #define MPI3_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0b) 473 #define MPI3_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0c) 474 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_MASK (0xc0) 475 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_SHIFT (6) 476 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_ACCESSIBLE (0x00) 477 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40) 478 #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80) 479 #define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0f) 480 #define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02) 481 #define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03) 482 #define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04) 483 #define MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING (0x05) 484 #define MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING (0x06) 485 struct mpi3_event_data_sas_topology_change_list { 486 __le16 enclosure_handle; 487 __le16 expander_dev_handle; 488 u8 num_phys; 489 u8 reserved05[3]; 490 u8 num_entries; 491 u8 start_phy_num; 492 u8 exp_status; 493 u8 io_unit_port; 494 struct mpi3_event_sas_topo_phy_entry phy_entry[MPI3_EVENT_SAS_TOPO_PHY_COUNT]; 495 }; 496 497 #define MPI3_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 498 #define MPI3_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 499 #define MPI3_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 500 #define MPI3_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 501 struct mpi3_event_data_sas_phy_counter { 502 __le64 time_stamp; 503 __le32 reserved08; 504 u8 phy_event_code; 505 u8 phy_num; 506 __le16 reserved0e; 507 __le32 phy_event_info; 508 u8 counter_type; 509 u8 threshold_window; 510 u8 time_units; 511 u8 reserved17; 512 __le32 event_threshold; 513 __le16 threshold_flags; 514 __le16 reserved1e; 515 }; 516 517 struct mpi3_event_data_sas_device_disc_err { 518 __le16 dev_handle; 519 u8 reason_code; 520 u8 io_unit_port; 521 __le32 reserved04; 522 __le64 sas_address; 523 }; 524 525 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_FAILED (0x01) 526 #define MPI3_EVENT_SAS_DISC_ERR_RC_SMP_TIMEOUT (0x02) 527 struct mpi3_event_data_pcie_enumeration { 528 u8 flags; 529 u8 reason_code; 530 u8 io_unit_port; 531 u8 reserved03; 532 __le32 enumeration_status; 533 }; 534 535 #define MPI3_EVENT_PCIE_ENUM_FLAGS_DEVICE_CHANGE (0x02) 536 #define MPI3_EVENT_PCIE_ENUM_FLAGS_IN_PROGRESS (0x01) 537 #define MPI3_EVENT_PCIE_ENUM_RC_STARTED (0x01) 538 #define MPI3_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) 539 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCH_DEPTH_EXCEED (0x80000000) 540 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) 541 #define MPI3_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) 542 #define MPI3_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) 543 #ifndef MPI3_EVENT_PCIE_TOPO_PORT_COUNT 544 #define MPI3_EVENT_PCIE_TOPO_PORT_COUNT (1) 545 #endif 546 struct mpi3_event_pcie_topo_port_entry { 547 __le16 attached_dev_handle; 548 u8 port_status; 549 u8 reserved03; 550 u8 current_port_info; 551 u8 reserved05; 552 u8 previous_port_info; 553 u8 reserved07; 554 }; 555 556 #define MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) 557 #define MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) 558 #define MPI3_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) 559 #define MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) 560 #define MPI3_EVENT_PCIE_TOPO_PS_RESPONDING (0x06) 561 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xf0) 562 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) 563 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10) 564 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20) 565 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_4 (0x30) 566 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_8 (0x40) 567 #define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50) 568 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0f) 569 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 570 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) 571 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) 572 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) 573 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) 574 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) 575 #define MPI3_EVENT_PCIE_TOPO_PI_RATE_32_0 (0x06) 576 struct mpi3_event_data_pcie_topology_change_list { 577 __le16 enclosure_handle; 578 __le16 switch_dev_handle; 579 u8 num_ports; 580 u8 reserved05[3]; 581 u8 num_entries; 582 u8 start_port_num; 583 u8 switch_status; 584 u8 io_unit_port; 585 __le32 reserved0c; 586 struct mpi3_event_pcie_topo_port_entry port_entry[MPI3_EVENT_PCIE_TOPO_PORT_COUNT]; 587 }; 588 589 #define MPI3_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) 590 #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) 591 #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) 592 #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) 593 struct mpi3_event_data_pcie_error_threshold { 594 __le64 timestamp; 595 u8 reason_code; 596 u8 port; 597 __le16 switch_dev_handle; 598 u8 error; 599 u8 action; 600 __le16 threshold_count; 601 __le16 attached_dev_handle; 602 __le16 reserved12; 603 }; 604 605 #define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0x00) 606 #define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0x01) 607 struct mpi3_event_data_sas_init_dev_status_change { 608 u8 reason_code; 609 u8 io_unit_port; 610 __le16 dev_handle; 611 __le32 reserved04; 612 __le64 sas_address; 613 }; 614 615 #define MPI3_EVENT_SAS_INIT_RC_ADDED (0x01) 616 #define MPI3_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 617 struct mpi3_event_data_sas_init_table_overflow { 618 __le16 max_init; 619 __le16 current_init; 620 __le32 reserved04; 621 __le64 sas_address; 622 }; 623 624 struct mpi3_event_data_hard_reset_received { 625 u8 reserved00; 626 u8 io_unit_port; 627 __le16 reserved02; 628 }; 629 630 struct mpi3_event_data_diag_buffer_status_change { 631 u8 type; 632 u8 reason_code; 633 __le16 reserved02; 634 __le32 reserved04; 635 }; 636 637 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01) 638 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02) 639 #define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03) 640 #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) 641 #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) 642 #define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) 643 #define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040) 644 #define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020) 645 #define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010) 646 #define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008) 647 #define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004) 648 #define MPI3_PEL_LOCALE_FLAGS_PD (0x0002) 649 #define MPI3_PEL_LOCALE_FLAGS_VD (0x0001) 650 #define MPI3_PEL_CLASS_DEBUG (0x00) 651 #define MPI3_PEL_CLASS_PROGRESS (0x01) 652 #define MPI3_PEL_CLASS_INFORMATIONAL (0x02) 653 #define MPI3_PEL_CLASS_WARNING (0x03) 654 #define MPI3_PEL_CLASS_CRITICAL (0x04) 655 #define MPI3_PEL_CLASS_FATAL (0x05) 656 #define MPI3_PEL_CLASS_FAULT (0x06) 657 #define MPI3_PEL_CLEARTYPE_CLEAR (0x00) 658 #define MPI3_PEL_WAITTIME_INFINITE_WAIT (0x00) 659 #define MPI3_PEL_ACTION_GET_SEQNUM (0x01) 660 #define MPI3_PEL_ACTION_MARK_CLEAR (0x02) 661 #define MPI3_PEL_ACTION_GET_LOG (0x03) 662 #define MPI3_PEL_ACTION_GET_COUNT (0x04) 663 #define MPI3_PEL_ACTION_WAIT (0x05) 664 #define MPI3_PEL_ACTION_ABORT (0x06) 665 #define MPI3_PEL_ACTION_GET_PRINT_STRINGS (0x07) 666 #define MPI3_PEL_ACTION_ACKNOWLEDGE (0x08) 667 #define MPI3_PEL_STATUS_SUCCESS (0x00) 668 #define MPI3_PEL_STATUS_NOT_FOUND (0x01) 669 #define MPI3_PEL_STATUS_ABORTED (0x02) 670 #define MPI3_PEL_STATUS_NOT_READY (0x03) 671 struct mpi3_pel_seq { 672 __le32 newest; 673 __le32 oldest; 674 __le32 clear; 675 __le32 shutdown; 676 __le32 boot; 677 __le32 last_acknowledged; 678 }; 679 680 struct mpi3_pel_entry { 681 __le64 time_stamp; 682 __le32 sequence_number; 683 __le16 log_code; 684 __le16 arg_type; 685 __le16 locale; 686 u8 class; 687 u8 flags; 688 u8 ext_num; 689 u8 num_exts; 690 u8 arg_data_size; 691 u8 fixed_format_strings_size; 692 __le32 reserved18[2]; 693 __le32 pel_info[24]; 694 }; 695 696 #define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0x02) 697 #define MPI3_PEL_FLAGS_ACK_NEEDED (0x01) 698 struct mpi3_pel_list { 699 __le32 log_count; 700 __le32 reserved04; 701 struct mpi3_pel_entry entry[1]; 702 }; 703 704 struct mpi3_pel_arg_map { 705 u8 arg_type; 706 u8 length; 707 __le16 start_location; 708 }; 709 710 #define MPI3_PEL_ARG_MAP_ARG_TYPE_APPEND_STRING (0x00) 711 #define MPI3_PEL_ARG_MAP_ARG_TYPE_INTEGER (0x01) 712 #define MPI3_PEL_ARG_MAP_ARG_TYPE_STRING (0x02) 713 #define MPI3_PEL_ARG_MAP_ARG_TYPE_BIT_FIELD (0x03) 714 struct mpi3_pel_print_string { 715 __le16 log_code; 716 __le16 string_length; 717 u8 num_arg_map; 718 u8 reserved05[3]; 719 struct mpi3_pel_arg_map arg_map[1]; 720 }; 721 722 struct mpi3_pel_print_string_list { 723 __le32 num_print_strings; 724 __le32 residual_bytes_remain; 725 __le32 reserved08[2]; 726 struct mpi3_pel_print_string print_string[1]; 727 }; 728 729 #ifndef MPI3_PEL_ACTION_SPECIFIC_MAX 730 #define MPI3_PEL_ACTION_SPECIFIC_MAX (1) 731 #endif 732 struct mpi3_pel_request { 733 __le16 host_tag; 734 u8 ioc_use_only02; 735 u8 function; 736 __le16 ioc_use_only04; 737 u8 ioc_use_only06; 738 u8 msg_flags; 739 __le16 change_count; 740 u8 action; 741 u8 reserved0b; 742 __le32 action_specific[MPI3_PEL_ACTION_SPECIFIC_MAX]; 743 }; 744 745 struct mpi3_pel_req_action_get_sequence_numbers { 746 __le16 host_tag; 747 u8 ioc_use_only02; 748 u8 function; 749 __le16 ioc_use_only04; 750 u8 ioc_use_only06; 751 u8 msg_flags; 752 __le16 change_count; 753 u8 action; 754 u8 reserved0b; 755 __le32 reserved0c[5]; 756 union mpi3_sge_union sgl; 757 }; 758 759 struct mpi3_pel_req_action_clear_log_marker { 760 __le16 host_tag; 761 u8 ioc_use_only02; 762 u8 function; 763 __le16 ioc_use_only04; 764 u8 ioc_use_only06; 765 u8 msg_flags; 766 __le16 change_count; 767 u8 action; 768 u8 reserved0b; 769 u8 clear_type; 770 u8 reserved0d[3]; 771 }; 772 773 struct mpi3_pel_req_action_get_log { 774 __le16 host_tag; 775 u8 ioc_use_only02; 776 u8 function; 777 __le16 ioc_use_only04; 778 u8 ioc_use_only06; 779 u8 msg_flags; 780 __le16 change_count; 781 u8 action; 782 u8 reserved0b; 783 __le32 starting_sequence_number; 784 __le16 locale; 785 u8 class; 786 u8 reserved13; 787 __le32 reserved14[3]; 788 union mpi3_sge_union sgl; 789 }; 790 791 struct mpi3_pel_req_action_get_count { 792 __le16 host_tag; 793 u8 ioc_use_only02; 794 u8 function; 795 __le16 ioc_use_only04; 796 u8 ioc_use_only06; 797 u8 msg_flags; 798 __le16 change_count; 799 u8 action; 800 u8 reserved0b; 801 __le32 starting_sequence_number; 802 __le16 locale; 803 u8 class; 804 u8 reserved13; 805 __le32 reserved14[3]; 806 union mpi3_sge_union sgl; 807 }; 808 809 struct mpi3_pel_req_action_wait { 810 __le16 host_tag; 811 u8 ioc_use_only02; 812 u8 function; 813 __le16 ioc_use_only04; 814 u8 ioc_use_only06; 815 u8 msg_flags; 816 __le16 change_count; 817 u8 action; 818 u8 reserved0b; 819 __le32 starting_sequence_number; 820 __le16 locale; 821 u8 class; 822 u8 reserved13; 823 __le16 wait_time; 824 __le16 reserved16; 825 __le32 reserved18[2]; 826 }; 827 828 struct mpi3_pel_req_action_abort { 829 __le16 host_tag; 830 u8 ioc_use_only02; 831 u8 function; 832 __le16 ioc_use_only04; 833 u8 ioc_use_only06; 834 u8 msg_flags; 835 __le16 change_count; 836 u8 action; 837 u8 reserved0b; 838 __le32 reserved0c; 839 __le16 abort_host_tag; 840 __le16 reserved12; 841 __le32 reserved14; 842 }; 843 844 struct mpi3_pel_req_action_get_print_strings { 845 __le16 host_tag; 846 u8 ioc_use_only02; 847 u8 function; 848 __le16 ioc_use_only04; 849 u8 ioc_use_only06; 850 u8 msg_flags; 851 __le16 change_count; 852 u8 action; 853 u8 reserved0b; 854 __le32 reserved0c; 855 __le16 start_log_code; 856 __le16 reserved12; 857 __le32 reserved14[3]; 858 union mpi3_sge_union sgl; 859 }; 860 861 struct mpi3_pel_req_action_acknowledge { 862 __le16 host_tag; 863 u8 ioc_use_only02; 864 u8 function; 865 __le16 ioc_use_only04; 866 u8 ioc_use_only06; 867 u8 msg_flags; 868 __le16 change_count; 869 u8 action; 870 u8 reserved0b; 871 __le32 sequence_number; 872 __le32 reserved10; 873 }; 874 875 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03) 876 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00) 877 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01) 878 #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02) 879 struct mpi3_pel_reply { 880 __le16 host_tag; 881 u8 ioc_use_only02; 882 u8 function; 883 __le16 ioc_use_only04; 884 u8 ioc_use_only06; 885 u8 msg_flags; 886 __le16 ioc_use_only08; 887 __le16 ioc_status; 888 __le32 ioc_log_info; 889 u8 action; 890 u8 reserved11; 891 __le16 reserved12; 892 __le16 pe_log_status; 893 __le16 reserved16; 894 __le32 transfer_length; 895 }; 896 897 struct mpi3_ci_download_request { 898 __le16 host_tag; 899 u8 ioc_use_only02; 900 u8 function; 901 __le16 ioc_use_only04; 902 u8 ioc_use_only06; 903 u8 msg_flags; 904 __le16 change_count; 905 u8 action; 906 u8 reserved0b; 907 __le32 signature1; 908 __le32 total_image_size; 909 __le32 image_offset; 910 __le32 segment_size; 911 __le32 reserved1c; 912 union mpi3_sge_union sgl; 913 }; 914 915 #define MPI3_CI_DOWNLOAD_MSGFLAGS_LAST_SEGMENT (0x80) 916 #define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40) 917 #define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20) 918 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03) 919 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00) 920 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01) 921 #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02) 922 #define MPI3_CI_DOWNLOAD_ACTION_DOWNLOAD (0x01) 923 #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02) 924 #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03) 925 #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04) 926 #define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0x05) 927 struct mpi3_ci_download_reply { 928 __le16 host_tag; 929 u8 ioc_use_only02; 930 u8 function; 931 __le16 ioc_use_only04; 932 u8 ioc_use_only06; 933 u8 msg_flags; 934 __le16 ioc_use_only08; 935 __le16 ioc_status; 936 __le32 ioc_log_info; 937 u8 flags; 938 u8 cache_dirty; 939 u8 pending_count; 940 u8 reserved13; 941 }; 942 943 #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80) 944 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_FAILURE (0x40) 945 #define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20) 946 #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10) 947 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e) 948 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00) 949 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02) 950 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04) 951 #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_OFFLINE_PENDING (0x06) 952 #define MPI3_CI_DOWNLOAD_FLAGS_COMPATIBLE (0x01) 953 struct mpi3_ci_upload_request { 954 __le16 host_tag; 955 u8 ioc_use_only02; 956 u8 function; 957 __le16 ioc_use_only04; 958 u8 ioc_use_only06; 959 u8 msg_flags; 960 __le16 change_count; 961 __le16 reserved0a; 962 __le32 signature1; 963 __le32 reserved10; 964 __le32 image_offset; 965 __le32 segment_size; 966 __le32 reserved1c; 967 union mpi3_sge_union sgl; 968 }; 969 970 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01) 971 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00) 972 #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01) 973 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02) 974 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00) 975 #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02) 976 #define MPI3_CTRL_OP_FORCE_FULL_DISCOVERY (0x01) 977 #define MPI3_CTRL_OP_LOOKUP_MAPPING (0x02) 978 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP (0x04) 979 #define MPI3_CTRL_OP_GET_TIMESTAMP (0x05) 980 #define MPI3_CTRL_OP_GET_IOC_CHANGE_COUNT (0x06) 981 #define MPI3_CTRL_OP_CHANGE_PROFILE (0x07) 982 #define MPI3_CTRL_OP_REMOVE_DEVICE (0x10) 983 #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11) 984 #define MPI3_CTRL_OP_HIDDEN_ACK (0x12) 985 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0x13) 986 #define MPI3_CTRL_OP_SEND_SAS_PRIMITIVE (0x20) 987 #define MPI3_CTRL_OP_SAS_PHY_CONTROL (0x21) 988 #define MPI3_CTRL_OP_READ_INTERNAL_BUS (0x23) 989 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0x24) 990 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0x30) 991 #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00) 992 #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00) 993 #define MPI3_CTRL_OP_CHANGE_PROFILE_PARAM8_PROFILE_ID_INDEX (0x00) 994 #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00) 995 #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00) 996 #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00) 997 #define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0x00) 998 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PHY_INDEX (0x00) 999 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM8_PRIMSEQ_INDEX (0x01) 1000 #define MPI3_CTRL_OP_SEND_SAS_PRIM_PARAM32_PRIMITIVE_INDEX (0x00) 1001 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0x00) 1002 #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0x01) 1003 #define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) 1004 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00) 1005 #define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0x00) 1006 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0x00) 1007 #define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0x01) 1008 #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) 1009 #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) 1010 #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) 1011 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTENT_ID (0x04) 1012 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM16_DEVH_INDEX (0) 1013 #define MPI3_CTRL_LOOKUP_METHOD_WWIDADDR_PARAM64_WWID_INDEX (0) 1014 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM16_SLOTNUM_INDEX (0) 1015 #define MPI3_CTRL_LOOKUP_METHOD_ENCLSLOT_PARAM64_ENCLOSURELID_INDEX (0) 1016 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM16_DEVH_INDEX (0) 1017 #define MPI3_CTRL_LOOKUP_METHOD_SASDEVNAME_PARAM64_DEVNAME_INDEX (0) 1018 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_DEVH_INDEX (0) 1019 #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1) 1020 #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0) 1021 #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0) 1022 #define MPI3_CTRL_GET_IOC_CHANGE_COUNT_VALUE16_CHANGECOUNT_INDEX (0) 1023 #define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0) 1024 #define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01) 1025 #define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03) 1026 #define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06) 1027 #define MPI3_CTRL_ACTION_NOP (0x00) 1028 #define MPI3_CTRL_ACTION_LINK_RESET (0x01) 1029 #define MPI3_CTRL_ACTION_HARD_RESET (0x02) 1030 #define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0x05) 1031 struct mpi3_iounit_control_request { 1032 __le16 host_tag; 1033 u8 ioc_use_only02; 1034 u8 function; 1035 __le16 ioc_use_only04; 1036 u8 ioc_use_only06; 1037 u8 msg_flags; 1038 __le16 change_count; 1039 u8 reserved0a; 1040 u8 operation; 1041 __le32 reserved0c; 1042 __le64 param64[2]; 1043 __le32 param32[4]; 1044 __le16 param16[4]; 1045 u8 param8[8]; 1046 }; 1047 1048 struct mpi3_iounit_control_reply { 1049 __le16 host_tag; 1050 u8 ioc_use_only02; 1051 u8 function; 1052 __le16 ioc_use_only04; 1053 u8 ioc_use_only06; 1054 u8 msg_flags; 1055 __le16 ioc_use_only08; 1056 __le16 ioc_status; 1057 __le32 ioc_log_info; 1058 __le64 value64[2]; 1059 __le32 value32[4]; 1060 __le16 value16[4]; 1061 u8 value8[8]; 1062 }; 1063 #endif 1064