1 /* 2 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware) 3 * bus adaptor found on Power Macintosh computers. 4 * We assume the MESH is connected to a DBDMA (descriptor-based DMA) 5 * controller. 6 * 7 * Paul Mackerras, August 1996. 8 * Copyright (C) 1996 Paul Mackerras. 9 * 10 * Apr. 21 2002 - BenH Rework bus reset code for new error handler 11 * Add delay after initial bus reset 12 * Add module parameters 13 * 14 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting 15 * issues 16 * To do: 17 * - handle aborts correctly 18 * - retry arbitration if lost (unless higher levels do this for us) 19 * - power down the chip when no device is detected 20 */ 21 #include <linux/module.h> 22 #include <linux/kernel.h> 23 #include <linux/delay.h> 24 #include <linux/types.h> 25 #include <linux/string.h> 26 #include <linux/slab.h> 27 #include <linux/blkdev.h> 28 #include <linux/proc_fs.h> 29 #include <linux/stat.h> 30 #include <linux/interrupt.h> 31 #include <linux/reboot.h> 32 #include <linux/spinlock.h> 33 #include <asm/dbdma.h> 34 #include <asm/io.h> 35 #include <asm/pgtable.h> 36 #include <asm/prom.h> 37 #include <asm/system.h> 38 #include <asm/irq.h> 39 #include <asm/hydra.h> 40 #include <asm/processor.h> 41 #include <asm/machdep.h> 42 #include <asm/pmac_feature.h> 43 #include <asm/pci-bridge.h> 44 #include <asm/macio.h> 45 46 #include <scsi/scsi.h> 47 #include <scsi/scsi_cmnd.h> 48 #include <scsi/scsi_device.h> 49 #include <scsi/scsi_host.h> 50 51 #include "mesh.h" 52 53 #if 1 54 #undef KERN_DEBUG 55 #define KERN_DEBUG KERN_WARNING 56 #endif 57 58 MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)"); 59 MODULE_DESCRIPTION("PowerMac MESH SCSI driver"); 60 MODULE_LICENSE("GPL"); 61 62 static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE; 63 static int sync_targets = 0xff; 64 static int resel_targets = 0xff; 65 static int debug_targets = 0; /* print debug for these targets */ 66 static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS; 67 68 module_param(sync_rate, int, 0); 69 MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)"); 70 module_param(sync_targets, int, 0); 71 MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous"); 72 module_param(resel_targets, int, 0); 73 MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect"); 74 module_param(debug_targets, int, 0644); 75 MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets"); 76 module_param(init_reset_delay, int, 0); 77 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)"); 78 79 static int mesh_sync_period = 100; 80 static int mesh_sync_offset = 0; 81 static unsigned char use_active_neg = 0; /* bit mask for SEQ_ACTIVE_NEG if used */ 82 83 #define ALLOW_SYNC(tgt) ((sync_targets >> (tgt)) & 1) 84 #define ALLOW_RESEL(tgt) ((resel_targets >> (tgt)) & 1) 85 #define ALLOW_DEBUG(tgt) ((debug_targets >> (tgt)) & 1) 86 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id)) 87 88 #undef MESH_DBG 89 #define N_DBG_LOG 50 90 #define N_DBG_SLOG 20 91 #define NUM_DBG_EVENTS 13 92 #undef DBG_USE_TB /* bombs on 601 */ 93 94 struct dbglog { 95 char *fmt; 96 u32 tb; 97 u8 phase; 98 u8 bs0; 99 u8 bs1; 100 u8 tgt; 101 int d; 102 }; 103 104 enum mesh_phase { 105 idle, 106 arbitrating, 107 selecting, 108 commanding, 109 dataing, 110 statusing, 111 busfreeing, 112 disconnecting, 113 reselecting, 114 sleeping 115 }; 116 117 enum msg_phase { 118 msg_none, 119 msg_out, 120 msg_out_xxx, 121 msg_out_last, 122 msg_in, 123 msg_in_bad, 124 }; 125 126 enum sdtr_phase { 127 do_sdtr, 128 sdtr_sent, 129 sdtr_done 130 }; 131 132 struct mesh_target { 133 enum sdtr_phase sdtr_state; 134 int sync_params; 135 int data_goes_out; /* guess as to data direction */ 136 struct scsi_cmnd *current_req; 137 u32 saved_ptr; 138 #ifdef MESH_DBG 139 int log_ix; 140 int n_log; 141 struct dbglog log[N_DBG_LOG]; 142 #endif 143 }; 144 145 struct mesh_state { 146 volatile struct mesh_regs __iomem *mesh; 147 int meshintr; 148 volatile struct dbdma_regs __iomem *dma; 149 int dmaintr; 150 struct Scsi_Host *host; 151 struct mesh_state *next; 152 struct scsi_cmnd *request_q; 153 struct scsi_cmnd *request_qtail; 154 enum mesh_phase phase; /* what we're currently trying to do */ 155 enum msg_phase msgphase; 156 int conn_tgt; /* target we're connected to */ 157 struct scsi_cmnd *current_req; /* req we're currently working on */ 158 int data_ptr; 159 int dma_started; 160 int dma_count; 161 int stat; 162 int aborting; 163 int expect_reply; 164 int n_msgin; 165 u8 msgin[16]; 166 int n_msgout; 167 int last_n_msgout; 168 u8 msgout[16]; 169 struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */ 170 dma_addr_t dma_cmd_bus; 171 void *dma_cmd_space; 172 int dma_cmd_size; 173 int clk_freq; 174 struct mesh_target tgts[8]; 175 struct macio_dev *mdev; 176 struct pci_dev* pdev; 177 #ifdef MESH_DBG 178 int log_ix; 179 int n_log; 180 struct dbglog log[N_DBG_SLOG]; 181 #endif 182 }; 183 184 /* 185 * Driver is too messy, we need a few prototypes... 186 */ 187 static void mesh_done(struct mesh_state *ms, int start_next); 188 static void mesh_interrupt(struct mesh_state *ms); 189 static void cmd_complete(struct mesh_state *ms); 190 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd); 191 static void halt_dma(struct mesh_state *ms); 192 static void phase_mismatch(struct mesh_state *ms); 193 194 195 /* 196 * Some debugging & logging routines 197 */ 198 199 #ifdef MESH_DBG 200 201 static inline u32 readtb(void) 202 { 203 u32 tb; 204 205 #ifdef DBG_USE_TB 206 /* Beware: if you enable this, it will crash on 601s. */ 207 asm ("mftb %0" : "=r" (tb) : ); 208 #else 209 tb = 0; 210 #endif 211 return tb; 212 } 213 214 static void dlog(struct mesh_state *ms, char *fmt, int a) 215 { 216 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 217 struct dbglog *tlp, *slp; 218 219 tlp = &tp->log[tp->log_ix]; 220 slp = &ms->log[ms->log_ix]; 221 tlp->fmt = fmt; 222 tlp->tb = readtb(); 223 tlp->phase = (ms->msgphase << 4) + ms->phase; 224 tlp->bs0 = ms->mesh->bus_status0; 225 tlp->bs1 = ms->mesh->bus_status1; 226 tlp->tgt = ms->conn_tgt; 227 tlp->d = a; 228 *slp = *tlp; 229 if (++tp->log_ix >= N_DBG_LOG) 230 tp->log_ix = 0; 231 if (tp->n_log < N_DBG_LOG) 232 ++tp->n_log; 233 if (++ms->log_ix >= N_DBG_SLOG) 234 ms->log_ix = 0; 235 if (ms->n_log < N_DBG_SLOG) 236 ++ms->n_log; 237 } 238 239 static void dumplog(struct mesh_state *ms, int t) 240 { 241 struct mesh_target *tp = &ms->tgts[t]; 242 struct dbglog *lp; 243 int i; 244 245 if (tp->n_log == 0) 246 return; 247 i = tp->log_ix - tp->n_log; 248 if (i < 0) 249 i += N_DBG_LOG; 250 tp->n_log = 0; 251 do { 252 lp = &tp->log[i]; 253 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ", 254 t, lp->bs1, lp->bs0, lp->phase); 255 #ifdef DBG_USE_TB 256 printk("tb=%10u ", lp->tb); 257 #endif 258 printk(lp->fmt, lp->d); 259 printk("\n"); 260 if (++i >= N_DBG_LOG) 261 i = 0; 262 } while (i != tp->log_ix); 263 } 264 265 static void dumpslog(struct mesh_state *ms) 266 { 267 struct dbglog *lp; 268 int i; 269 270 if (ms->n_log == 0) 271 return; 272 i = ms->log_ix - ms->n_log; 273 if (i < 0) 274 i += N_DBG_SLOG; 275 ms->n_log = 0; 276 do { 277 lp = &ms->log[i]; 278 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ", 279 lp->bs1, lp->bs0, lp->phase, lp->tgt); 280 #ifdef DBG_USE_TB 281 printk("tb=%10u ", lp->tb); 282 #endif 283 printk(lp->fmt, lp->d); 284 printk("\n"); 285 if (++i >= N_DBG_SLOG) 286 i = 0; 287 } while (i != ms->log_ix); 288 } 289 290 #else 291 292 static inline void dlog(struct mesh_state *ms, char *fmt, int a) 293 {} 294 static inline void dumplog(struct mesh_state *ms, int tgt) 295 {} 296 static inline void dumpslog(struct mesh_state *ms) 297 {} 298 299 #endif /* MESH_DBG */ 300 301 #define MKWORD(a, b, c, d) (((a) << 24) + ((b) << 16) + ((c) << 8) + (d)) 302 303 static void 304 mesh_dump_regs(struct mesh_state *ms) 305 { 306 volatile struct mesh_regs __iomem *mr = ms->mesh; 307 volatile struct dbdma_regs __iomem *md = ms->dma; 308 int t; 309 struct mesh_target *tp; 310 311 printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n", 312 ms, mr, md); 313 printk(KERN_DEBUG " ct=%4x seq=%2x bs=%4x fc=%2x " 314 "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n", 315 (mr->count_hi << 8) + mr->count_lo, mr->sequence, 316 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count, 317 mr->exception, mr->error, mr->intr_mask, mr->interrupt, 318 mr->sync_params); 319 while(in_8(&mr->fifo_count)) 320 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo)); 321 printk(KERN_DEBUG " dma stat=%x cmdptr=%x\n", 322 in_le32(&md->status), in_le32(&md->cmdptr)); 323 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n", 324 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr); 325 printk(KERN_DEBUG " dma_st=%d dma_ct=%d n_msgout=%d\n", 326 ms->dma_started, ms->dma_count, ms->n_msgout); 327 for (t = 0; t < 8; ++t) { 328 tp = &ms->tgts[t]; 329 if (tp->current_req == NULL) 330 continue; 331 printk(KERN_DEBUG " target %d: req=%p goes_out=%d saved_ptr=%d\n", 332 t, tp->current_req, tp->data_goes_out, tp->saved_ptr); 333 } 334 } 335 336 337 /* 338 * Flush write buffers on the bus path to the mesh 339 */ 340 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr) 341 { 342 (void)in_8(&mr->mesh_id); 343 } 344 345 346 /* 347 * Complete a SCSI command 348 */ 349 static void mesh_completed(struct mesh_state *ms, struct scsi_cmnd *cmd) 350 { 351 (*cmd->scsi_done)(cmd); 352 } 353 354 355 /* Called with meshinterrupt disabled, initialize the chipset 356 * and eventually do the initial bus reset. The lock must not be 357 * held since we can schedule. 358 */ 359 static void mesh_init(struct mesh_state *ms) 360 { 361 volatile struct mesh_regs __iomem *mr = ms->mesh; 362 volatile struct dbdma_regs __iomem *md = ms->dma; 363 364 mesh_flush_io(mr); 365 udelay(100); 366 367 /* Reset controller */ 368 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ 369 out_8(&mr->exception, 0xff); /* clear all exception bits */ 370 out_8(&mr->error, 0xff); /* clear all error bits */ 371 out_8(&mr->sequence, SEQ_RESETMESH); 372 mesh_flush_io(mr); 373 udelay(10); 374 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 375 out_8(&mr->source_id, ms->host->this_id); 376 out_8(&mr->sel_timeout, 25); /* 250ms */ 377 out_8(&mr->sync_params, ASYNC_PARAMS); 378 379 if (init_reset_delay) { 380 printk(KERN_INFO "mesh: performing initial bus reset...\n"); 381 382 /* Reset bus */ 383 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ 384 mesh_flush_io(mr); 385 udelay(30); /* leave it on for >= 25us */ 386 out_8(&mr->bus_status1, 0); /* negate RST */ 387 mesh_flush_io(mr); 388 389 /* Wait for bus to come back */ 390 msleep(init_reset_delay); 391 } 392 393 /* Reconfigure controller */ 394 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */ 395 out_8(&mr->sequence, SEQ_FLUSHFIFO); 396 mesh_flush_io(mr); 397 udelay(1); 398 out_8(&mr->sync_params, ASYNC_PARAMS); 399 out_8(&mr->sequence, SEQ_ENBRESEL); 400 401 ms->phase = idle; 402 ms->msgphase = msg_none; 403 } 404 405 406 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd) 407 { 408 volatile struct mesh_regs __iomem *mr = ms->mesh; 409 int t, id; 410 411 id = cmd->device->id; 412 ms->current_req = cmd; 413 ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE; 414 ms->tgts[id].current_req = cmd; 415 416 #if 1 417 if (DEBUG_TARGET(cmd)) { 418 int i; 419 printk(KERN_DEBUG "mesh_start: %p ser=%lu tgt=%d cmd=", 420 cmd, cmd->serial_number, id); 421 for (i = 0; i < cmd->cmd_len; ++i) 422 printk(" %x", cmd->cmnd[i]); 423 printk(" use_sg=%d buffer=%p bufflen=%u\n", 424 scsi_sg_count(cmd), scsi_sglist(cmd), scsi_bufflen(cmd)); 425 } 426 #endif 427 if (ms->dma_started) 428 panic("mesh: double DMA start !\n"); 429 430 ms->phase = arbitrating; 431 ms->msgphase = msg_none; 432 ms->data_ptr = 0; 433 ms->dma_started = 0; 434 ms->n_msgout = 0; 435 ms->last_n_msgout = 0; 436 ms->expect_reply = 0; 437 ms->conn_tgt = id; 438 ms->tgts[id].saved_ptr = 0; 439 ms->stat = DID_OK; 440 ms->aborting = 0; 441 #ifdef MESH_DBG 442 ms->tgts[id].n_log = 0; 443 dlog(ms, "start cmd=%x", (int) cmd); 444 #endif 445 446 /* Off we go */ 447 dlog(ms, "about to arb, intr/exc/err/fc=%.8x", 448 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); 449 out_8(&mr->interrupt, INT_CMDDONE); 450 out_8(&mr->sequence, SEQ_ENBRESEL); 451 mesh_flush_io(mr); 452 udelay(1); 453 454 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { 455 /* 456 * Some other device has the bus or is arbitrating for it - 457 * probably a target which is about to reselect us. 458 */ 459 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x", 460 MKWORD(mr->interrupt, mr->exception, 461 mr->error, mr->fifo_count)); 462 for (t = 100; t > 0; --t) { 463 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0) 464 break; 465 if (in_8(&mr->interrupt) != 0) { 466 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x", 467 MKWORD(mr->interrupt, mr->exception, 468 mr->error, mr->fifo_count)); 469 mesh_interrupt(ms); 470 if (ms->phase != arbitrating) 471 return; 472 } 473 udelay(1); 474 } 475 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { 476 /* XXX should try again in a little while */ 477 ms->stat = DID_BUS_BUSY; 478 ms->phase = idle; 479 mesh_done(ms, 0); 480 return; 481 } 482 } 483 484 /* 485 * Apparently the mesh has a bug where it will assert both its 486 * own bit and the target's bit on the bus during arbitration. 487 */ 488 out_8(&mr->dest_id, mr->source_id); 489 490 /* 491 * There appears to be a race with reselection sometimes, 492 * where a target reselects us just as we issue the 493 * arbitrate command. It seems that then the arbitrate 494 * command just hangs waiting for the bus to be free 495 * without giving us a reselection exception. 496 * The only way I have found to get it to respond correctly 497 * is this: disable reselection before issuing the arbitrate 498 * command, then after issuing it, if it looks like a target 499 * is trying to reselect us, reset the mesh and then enable 500 * reselection. 501 */ 502 out_8(&mr->sequence, SEQ_DISRESEL); 503 if (in_8(&mr->interrupt) != 0) { 504 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x", 505 MKWORD(mr->interrupt, mr->exception, 506 mr->error, mr->fifo_count)); 507 mesh_interrupt(ms); 508 if (ms->phase != arbitrating) 509 return; 510 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x", 511 MKWORD(mr->interrupt, mr->exception, 512 mr->error, mr->fifo_count)); 513 } 514 515 out_8(&mr->sequence, SEQ_ARBITRATE); 516 517 for (t = 230; t > 0; --t) { 518 if (in_8(&mr->interrupt) != 0) 519 break; 520 udelay(1); 521 } 522 dlog(ms, "after arb, intr/exc/err/fc=%.8x", 523 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); 524 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) 525 && (in_8(&mr->bus_status0) & BS0_IO)) { 526 /* looks like a reselection - try resetting the mesh */ 527 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x", 528 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); 529 out_8(&mr->sequence, SEQ_RESETMESH); 530 mesh_flush_io(mr); 531 udelay(10); 532 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 533 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 534 out_8(&mr->sequence, SEQ_ENBRESEL); 535 mesh_flush_io(mr); 536 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t) 537 udelay(1); 538 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x", 539 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); 540 #ifndef MESH_MULTIPLE_HOSTS 541 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) 542 && (in_8(&mr->bus_status0) & BS0_IO)) { 543 printk(KERN_ERR "mesh: controller not responding" 544 " to reselection!\n"); 545 /* 546 * If this is a target reselecting us, and the 547 * mesh isn't responding, the higher levels of 548 * the scsi code will eventually time out and 549 * reset the bus. 550 */ 551 } 552 #endif 553 } 554 } 555 556 /* 557 * Start the next command for a MESH. 558 * Should be called with interrupts disabled. 559 */ 560 static void mesh_start(struct mesh_state *ms) 561 { 562 struct scsi_cmnd *cmd, *prev, *next; 563 564 if (ms->phase != idle || ms->current_req != NULL) { 565 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)", 566 ms->phase, ms); 567 return; 568 } 569 570 while (ms->phase == idle) { 571 prev = NULL; 572 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) { 573 if (cmd == NULL) 574 return; 575 if (ms->tgts[cmd->device->id].current_req == NULL) 576 break; 577 prev = cmd; 578 } 579 next = (struct scsi_cmnd *) cmd->host_scribble; 580 if (prev == NULL) 581 ms->request_q = next; 582 else 583 prev->host_scribble = (void *) next; 584 if (next == NULL) 585 ms->request_qtail = prev; 586 587 mesh_start_cmd(ms, cmd); 588 } 589 } 590 591 static void mesh_done(struct mesh_state *ms, int start_next) 592 { 593 struct scsi_cmnd *cmd; 594 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 595 596 cmd = ms->current_req; 597 ms->current_req = NULL; 598 tp->current_req = NULL; 599 if (cmd) { 600 cmd->result = (ms->stat << 16) + cmd->SCp.Status; 601 if (ms->stat == DID_OK) 602 cmd->result += (cmd->SCp.Message << 8); 603 if (DEBUG_TARGET(cmd)) { 604 printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n", 605 cmd->result, ms->data_ptr, scsi_bufflen(cmd)); 606 #if 0 607 /* needs to use sg? */ 608 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3) 609 && cmd->request_buffer != 0) { 610 unsigned char *b = cmd->request_buffer; 611 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n", 612 b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]); 613 } 614 #endif 615 } 616 cmd->SCp.this_residual -= ms->data_ptr; 617 mesh_completed(ms, cmd); 618 } 619 if (start_next) { 620 out_8(&ms->mesh->sequence, SEQ_ENBRESEL); 621 mesh_flush_io(ms->mesh); 622 udelay(1); 623 ms->phase = idle; 624 mesh_start(ms); 625 } 626 } 627 628 static inline void add_sdtr_msg(struct mesh_state *ms) 629 { 630 int i = ms->n_msgout; 631 632 ms->msgout[i] = EXTENDED_MESSAGE; 633 ms->msgout[i+1] = 3; 634 ms->msgout[i+2] = EXTENDED_SDTR; 635 ms->msgout[i+3] = mesh_sync_period/4; 636 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0); 637 ms->n_msgout = i + 5; 638 } 639 640 static void set_sdtr(struct mesh_state *ms, int period, int offset) 641 { 642 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 643 volatile struct mesh_regs __iomem *mr = ms->mesh; 644 int v, tr; 645 646 tp->sdtr_state = sdtr_done; 647 if (offset == 0) { 648 /* asynchronous */ 649 if (SYNC_OFF(tp->sync_params)) 650 printk(KERN_INFO "mesh: target %d now asynchronous\n", 651 ms->conn_tgt); 652 tp->sync_params = ASYNC_PARAMS; 653 out_8(&mr->sync_params, ASYNC_PARAMS); 654 return; 655 } 656 /* 657 * We need to compute ceil(clk_freq * period / 500e6) - 2 658 * without incurring overflow. 659 */ 660 v = (ms->clk_freq / 5000) * period; 661 if (v <= 250000) { 662 /* special case: sync_period == 5 * clk_period */ 663 v = 0; 664 /* units of tr are 100kB/s */ 665 tr = (ms->clk_freq + 250000) / 500000; 666 } else { 667 /* sync_period == (v + 2) * 2 * clk_period */ 668 v = (v + 99999) / 100000 - 2; 669 if (v > 15) 670 v = 15; /* oops */ 671 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000; 672 } 673 if (offset > 15) 674 offset = 15; /* can't happen */ 675 tp->sync_params = SYNC_PARAMS(offset, v); 676 out_8(&mr->sync_params, tp->sync_params); 677 printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n", 678 ms->conn_tgt, tr/10, tr%10); 679 } 680 681 static void start_phase(struct mesh_state *ms) 682 { 683 int i, seq, nb; 684 volatile struct mesh_regs __iomem *mr = ms->mesh; 685 volatile struct dbdma_regs __iomem *md = ms->dma; 686 struct scsi_cmnd *cmd = ms->current_req; 687 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 688 689 dlog(ms, "start_phase nmo/exc/fc/seq = %.8x", 690 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence)); 691 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 692 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0); 693 switch (ms->msgphase) { 694 case msg_none: 695 break; 696 697 case msg_in: 698 out_8(&mr->count_hi, 0); 699 out_8(&mr->count_lo, 1); 700 out_8(&mr->sequence, SEQ_MSGIN + seq); 701 ms->n_msgin = 0; 702 return; 703 704 case msg_out: 705 /* 706 * To make sure ATN drops before we assert ACK for 707 * the last byte of the message, we have to do the 708 * last byte specially. 709 */ 710 if (ms->n_msgout <= 0) { 711 printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n", 712 ms->n_msgout); 713 mesh_dump_regs(ms); 714 ms->msgphase = msg_none; 715 break; 716 } 717 if (ALLOW_DEBUG(ms->conn_tgt)) { 718 printk(KERN_DEBUG "mesh: sending %d msg bytes:", 719 ms->n_msgout); 720 for (i = 0; i < ms->n_msgout; ++i) 721 printk(" %x", ms->msgout[i]); 722 printk("\n"); 723 } 724 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0], 725 ms->msgout[1], ms->msgout[2])); 726 out_8(&mr->count_hi, 0); 727 out_8(&mr->sequence, SEQ_FLUSHFIFO); 728 mesh_flush_io(mr); 729 udelay(1); 730 /* 731 * If ATN is not already asserted, we assert it, then 732 * issue a SEQ_MSGOUT to get the mesh to drop ACK. 733 */ 734 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) { 735 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0); 736 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */ 737 mesh_flush_io(mr); 738 udelay(1); 739 out_8(&mr->count_lo, 1); 740 out_8(&mr->sequence, SEQ_MSGOUT + seq); 741 out_8(&mr->bus_status0, 0); /* release explicit ATN */ 742 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0); 743 } 744 if (ms->n_msgout == 1) { 745 /* 746 * We can't issue the SEQ_MSGOUT without ATN 747 * until the target has asserted REQ. The logic 748 * in cmd_complete handles both situations: 749 * REQ already asserted or not. 750 */ 751 cmd_complete(ms); 752 } else { 753 out_8(&mr->count_lo, ms->n_msgout - 1); 754 out_8(&mr->sequence, SEQ_MSGOUT + seq); 755 for (i = 0; i < ms->n_msgout - 1; ++i) 756 out_8(&mr->fifo, ms->msgout[i]); 757 } 758 return; 759 760 default: 761 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n", 762 ms->msgphase); 763 } 764 765 switch (ms->phase) { 766 case selecting: 767 out_8(&mr->dest_id, ms->conn_tgt); 768 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN); 769 break; 770 case commanding: 771 out_8(&mr->sync_params, tp->sync_params); 772 out_8(&mr->count_hi, 0); 773 if (cmd) { 774 out_8(&mr->count_lo, cmd->cmd_len); 775 out_8(&mr->sequence, SEQ_COMMAND + seq); 776 for (i = 0; i < cmd->cmd_len; ++i) 777 out_8(&mr->fifo, cmd->cmnd[i]); 778 } else { 779 out_8(&mr->count_lo, 6); 780 out_8(&mr->sequence, SEQ_COMMAND + seq); 781 for (i = 0; i < 6; ++i) 782 out_8(&mr->fifo, 0); 783 } 784 break; 785 case dataing: 786 /* transfer data, if any */ 787 if (!ms->dma_started) { 788 set_dma_cmds(ms, cmd); 789 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds)); 790 out_le32(&md->control, (RUN << 16) | RUN); 791 ms->dma_started = 1; 792 } 793 nb = ms->dma_count; 794 if (nb > 0xfff0) 795 nb = 0xfff0; 796 ms->dma_count -= nb; 797 ms->data_ptr += nb; 798 out_8(&mr->count_lo, nb); 799 out_8(&mr->count_hi, nb >> 8); 800 out_8(&mr->sequence, (tp->data_goes_out? 801 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq); 802 break; 803 case statusing: 804 out_8(&mr->count_hi, 0); 805 out_8(&mr->count_lo, 1); 806 out_8(&mr->sequence, SEQ_STATUS + seq); 807 break; 808 case busfreeing: 809 case disconnecting: 810 out_8(&mr->sequence, SEQ_ENBRESEL); 811 mesh_flush_io(mr); 812 udelay(1); 813 dlog(ms, "enbresel intr/exc/err/fc=%.8x", 814 MKWORD(mr->interrupt, mr->exception, mr->error, 815 mr->fifo_count)); 816 out_8(&mr->sequence, SEQ_BUSFREE); 817 break; 818 default: 819 printk(KERN_ERR "mesh: start_phase called with phase=%d\n", 820 ms->phase); 821 dumpslog(ms); 822 } 823 824 } 825 826 static inline void get_msgin(struct mesh_state *ms) 827 { 828 volatile struct mesh_regs __iomem *mr = ms->mesh; 829 int i, n; 830 831 n = mr->fifo_count; 832 if (n != 0) { 833 i = ms->n_msgin; 834 ms->n_msgin = i + n; 835 for (; n > 0; --n) 836 ms->msgin[i++] = in_8(&mr->fifo); 837 } 838 } 839 840 static inline int msgin_length(struct mesh_state *ms) 841 { 842 int b, n; 843 844 n = 1; 845 if (ms->n_msgin > 0) { 846 b = ms->msgin[0]; 847 if (b == 1) { 848 /* extended message */ 849 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2; 850 } else if (0x20 <= b && b <= 0x2f) { 851 /* 2-byte message */ 852 n = 2; 853 } 854 } 855 return n; 856 } 857 858 static void reselected(struct mesh_state *ms) 859 { 860 volatile struct mesh_regs __iomem *mr = ms->mesh; 861 struct scsi_cmnd *cmd; 862 struct mesh_target *tp; 863 int b, t, prev; 864 865 switch (ms->phase) { 866 case idle: 867 break; 868 case arbitrating: 869 if ((cmd = ms->current_req) != NULL) { 870 /* put the command back on the queue */ 871 cmd->host_scribble = (void *) ms->request_q; 872 if (ms->request_q == NULL) 873 ms->request_qtail = cmd; 874 ms->request_q = cmd; 875 tp = &ms->tgts[cmd->device->id]; 876 tp->current_req = NULL; 877 } 878 break; 879 case busfreeing: 880 ms->phase = reselecting; 881 mesh_done(ms, 0); 882 break; 883 case disconnecting: 884 break; 885 default: 886 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n", 887 ms->msgphase, ms->phase, ms->conn_tgt); 888 dumplog(ms, ms->conn_tgt); 889 dumpslog(ms); 890 } 891 892 if (ms->dma_started) { 893 printk(KERN_ERR "mesh: reselected with DMA started !\n"); 894 halt_dma(ms); 895 } 896 ms->current_req = NULL; 897 ms->phase = dataing; 898 ms->msgphase = msg_in; 899 ms->n_msgout = 0; 900 ms->last_n_msgout = 0; 901 prev = ms->conn_tgt; 902 903 /* 904 * We seem to get abortive reselections sometimes. 905 */ 906 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) { 907 static int mesh_aborted_resels; 908 mesh_aborted_resels++; 909 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 910 mesh_flush_io(mr); 911 udelay(1); 912 out_8(&mr->sequence, SEQ_ENBRESEL); 913 mesh_flush_io(mr); 914 udelay(5); 915 dlog(ms, "extra resel err/exc/fc = %.6x", 916 MKWORD(0, mr->error, mr->exception, mr->fifo_count)); 917 } 918 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 919 mesh_flush_io(mr); 920 udelay(1); 921 out_8(&mr->sequence, SEQ_ENBRESEL); 922 mesh_flush_io(mr); 923 udelay(1); 924 out_8(&mr->sync_params, ASYNC_PARAMS); 925 926 /* 927 * Find out who reselected us. 928 */ 929 if (in_8(&mr->fifo_count) == 0) { 930 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n"); 931 ms->conn_tgt = ms->host->this_id; 932 goto bogus; 933 } 934 /* get the last byte in the fifo */ 935 do { 936 b = in_8(&mr->fifo); 937 dlog(ms, "reseldata %x", b); 938 } while (in_8(&mr->fifo_count)); 939 for (t = 0; t < 8; ++t) 940 if ((b & (1 << t)) != 0 && t != ms->host->this_id) 941 break; 942 if (b != (1 << t) + (1 << ms->host->this_id)) { 943 printk(KERN_ERR "mesh: bad reselection data %x\n", b); 944 ms->conn_tgt = ms->host->this_id; 945 goto bogus; 946 } 947 948 949 /* 950 * Set up to continue with that target's transfer. 951 */ 952 ms->conn_tgt = t; 953 tp = &ms->tgts[t]; 954 out_8(&mr->sync_params, tp->sync_params); 955 if (ALLOW_DEBUG(t)) { 956 printk(KERN_DEBUG "mesh: reselected by target %d\n", t); 957 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n", 958 tp->saved_ptr, tp->data_goes_out, tp->current_req); 959 } 960 ms->current_req = tp->current_req; 961 if (tp->current_req == NULL) { 962 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t); 963 goto bogus; 964 } 965 ms->data_ptr = tp->saved_ptr; 966 dlog(ms, "resel prev tgt=%d", prev); 967 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception)); 968 start_phase(ms); 969 return; 970 971 bogus: 972 dumplog(ms, ms->conn_tgt); 973 dumpslog(ms); 974 ms->data_ptr = 0; 975 ms->aborting = 1; 976 start_phase(ms); 977 } 978 979 static void do_abort(struct mesh_state *ms) 980 { 981 ms->msgout[0] = ABORT; 982 ms->n_msgout = 1; 983 ms->aborting = 1; 984 ms->stat = DID_ABORT; 985 dlog(ms, "abort", 0); 986 } 987 988 static void handle_reset(struct mesh_state *ms) 989 { 990 int tgt; 991 struct mesh_target *tp; 992 struct scsi_cmnd *cmd; 993 volatile struct mesh_regs __iomem *mr = ms->mesh; 994 995 for (tgt = 0; tgt < 8; ++tgt) { 996 tp = &ms->tgts[tgt]; 997 if ((cmd = tp->current_req) != NULL) { 998 cmd->result = DID_RESET << 16; 999 tp->current_req = NULL; 1000 mesh_completed(ms, cmd); 1001 } 1002 ms->tgts[tgt].sdtr_state = do_sdtr; 1003 ms->tgts[tgt].sync_params = ASYNC_PARAMS; 1004 } 1005 ms->current_req = NULL; 1006 while ((cmd = ms->request_q) != NULL) { 1007 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble; 1008 cmd->result = DID_RESET << 16; 1009 mesh_completed(ms, cmd); 1010 } 1011 ms->phase = idle; 1012 ms->msgphase = msg_none; 1013 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 1014 out_8(&mr->sequence, SEQ_FLUSHFIFO); 1015 mesh_flush_io(mr); 1016 udelay(1); 1017 out_8(&mr->sync_params, ASYNC_PARAMS); 1018 out_8(&mr->sequence, SEQ_ENBRESEL); 1019 } 1020 1021 static irqreturn_t do_mesh_interrupt(int irq, void *dev_id) 1022 { 1023 unsigned long flags; 1024 struct mesh_state *ms = dev_id; 1025 struct Scsi_Host *dev = ms->host; 1026 1027 spin_lock_irqsave(dev->host_lock, flags); 1028 mesh_interrupt(ms); 1029 spin_unlock_irqrestore(dev->host_lock, flags); 1030 return IRQ_HANDLED; 1031 } 1032 1033 static void handle_error(struct mesh_state *ms) 1034 { 1035 int err, exc, count; 1036 volatile struct mesh_regs __iomem *mr = ms->mesh; 1037 1038 err = in_8(&mr->error); 1039 exc = in_8(&mr->exception); 1040 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 1041 dlog(ms, "error err/exc/fc/cl=%.8x", 1042 MKWORD(err, exc, mr->fifo_count, mr->count_lo)); 1043 if (err & ERR_SCSIRESET) { 1044 /* SCSI bus was reset */ 1045 printk(KERN_INFO "mesh: SCSI bus reset detected: " 1046 "waiting for end..."); 1047 while ((in_8(&mr->bus_status1) & BS1_RST) != 0) 1048 udelay(1); 1049 printk("done\n"); 1050 handle_reset(ms); 1051 /* request_q is empty, no point in mesh_start() */ 1052 return; 1053 } 1054 if (err & ERR_UNEXPDISC) { 1055 /* Unexpected disconnect */ 1056 if (exc & EXC_RESELECTED) { 1057 reselected(ms); 1058 return; 1059 } 1060 if (!ms->aborting) { 1061 printk(KERN_WARNING "mesh: target %d aborted\n", 1062 ms->conn_tgt); 1063 dumplog(ms, ms->conn_tgt); 1064 dumpslog(ms); 1065 } 1066 out_8(&mr->interrupt, INT_CMDDONE); 1067 ms->stat = DID_ABORT; 1068 mesh_done(ms, 1); 1069 return; 1070 } 1071 if (err & ERR_PARITY) { 1072 if (ms->msgphase == msg_in) { 1073 printk(KERN_ERR "mesh: msg parity error, target %d\n", 1074 ms->conn_tgt); 1075 ms->msgout[0] = MSG_PARITY_ERROR; 1076 ms->n_msgout = 1; 1077 ms->msgphase = msg_in_bad; 1078 cmd_complete(ms); 1079 return; 1080 } 1081 if (ms->stat == DID_OK) { 1082 printk(KERN_ERR "mesh: parity error, target %d\n", 1083 ms->conn_tgt); 1084 ms->stat = DID_PARITY; 1085 } 1086 count = (mr->count_hi << 8) + mr->count_lo; 1087 if (count == 0) { 1088 cmd_complete(ms); 1089 } else { 1090 /* reissue the data transfer command */ 1091 out_8(&mr->sequence, mr->sequence); 1092 } 1093 return; 1094 } 1095 if (err & ERR_SEQERR) { 1096 if (exc & EXC_RESELECTED) { 1097 /* This can happen if we issue a command to 1098 get the bus just after the target reselects us. */ 1099 static int mesh_resel_seqerr; 1100 mesh_resel_seqerr++; 1101 reselected(ms); 1102 return; 1103 } 1104 if (exc == EXC_PHASEMM) { 1105 static int mesh_phasemm_seqerr; 1106 mesh_phasemm_seqerr++; 1107 phase_mismatch(ms); 1108 return; 1109 } 1110 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n", 1111 err, exc); 1112 } else { 1113 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc); 1114 } 1115 mesh_dump_regs(ms); 1116 dumplog(ms, ms->conn_tgt); 1117 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) { 1118 /* try to do what the target wants */ 1119 do_abort(ms); 1120 phase_mismatch(ms); 1121 return; 1122 } 1123 ms->stat = DID_ERROR; 1124 mesh_done(ms, 1); 1125 } 1126 1127 static void handle_exception(struct mesh_state *ms) 1128 { 1129 int exc; 1130 volatile struct mesh_regs __iomem *mr = ms->mesh; 1131 1132 exc = in_8(&mr->exception); 1133 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE); 1134 if (exc & EXC_RESELECTED) { 1135 static int mesh_resel_exc; 1136 mesh_resel_exc++; 1137 reselected(ms); 1138 } else if (exc == EXC_ARBLOST) { 1139 printk(KERN_DEBUG "mesh: lost arbitration\n"); 1140 ms->stat = DID_BUS_BUSY; 1141 mesh_done(ms, 1); 1142 } else if (exc == EXC_SELTO) { 1143 /* selection timed out */ 1144 ms->stat = DID_BAD_TARGET; 1145 mesh_done(ms, 1); 1146 } else if (exc == EXC_PHASEMM) { 1147 /* target wants to do something different: 1148 find out what it wants and do it. */ 1149 phase_mismatch(ms); 1150 } else { 1151 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc); 1152 mesh_dump_regs(ms); 1153 dumplog(ms, ms->conn_tgt); 1154 do_abort(ms); 1155 phase_mismatch(ms); 1156 } 1157 } 1158 1159 static void handle_msgin(struct mesh_state *ms) 1160 { 1161 int i, code; 1162 struct scsi_cmnd *cmd = ms->current_req; 1163 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 1164 1165 if (ms->n_msgin == 0) 1166 return; 1167 code = ms->msgin[0]; 1168 if (ALLOW_DEBUG(ms->conn_tgt)) { 1169 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin); 1170 for (i = 0; i < ms->n_msgin; ++i) 1171 printk(" %x", ms->msgin[i]); 1172 printk("\n"); 1173 } 1174 dlog(ms, "msgin msg=%.8x", 1175 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2])); 1176 1177 ms->expect_reply = 0; 1178 ms->n_msgout = 0; 1179 if (ms->n_msgin < msgin_length(ms)) 1180 goto reject; 1181 if (cmd) 1182 cmd->SCp.Message = code; 1183 switch (code) { 1184 case COMMAND_COMPLETE: 1185 break; 1186 case EXTENDED_MESSAGE: 1187 switch (ms->msgin[2]) { 1188 case EXTENDED_MODIFY_DATA_POINTER: 1189 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6] 1190 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8); 1191 break; 1192 case EXTENDED_SDTR: 1193 if (tp->sdtr_state != sdtr_sent) { 1194 /* reply with an SDTR */ 1195 add_sdtr_msg(ms); 1196 /* limit period to at least his value, 1197 offset to no more than his */ 1198 if (ms->msgout[3] < ms->msgin[3]) 1199 ms->msgout[3] = ms->msgin[3]; 1200 if (ms->msgout[4] > ms->msgin[4]) 1201 ms->msgout[4] = ms->msgin[4]; 1202 set_sdtr(ms, ms->msgout[3], ms->msgout[4]); 1203 ms->msgphase = msg_out; 1204 } else { 1205 set_sdtr(ms, ms->msgin[3], ms->msgin[4]); 1206 } 1207 break; 1208 default: 1209 goto reject; 1210 } 1211 break; 1212 case SAVE_POINTERS: 1213 tp->saved_ptr = ms->data_ptr; 1214 break; 1215 case RESTORE_POINTERS: 1216 ms->data_ptr = tp->saved_ptr; 1217 break; 1218 case DISCONNECT: 1219 ms->phase = disconnecting; 1220 break; 1221 case ABORT: 1222 break; 1223 case MESSAGE_REJECT: 1224 if (tp->sdtr_state == sdtr_sent) 1225 set_sdtr(ms, 0, 0); 1226 break; 1227 case NOP: 1228 break; 1229 default: 1230 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) { 1231 if (cmd == NULL) { 1232 do_abort(ms); 1233 ms->msgphase = msg_out; 1234 } else if (code != cmd->device->lun + IDENTIFY_BASE) { 1235 printk(KERN_WARNING "mesh: lun mismatch " 1236 "(%d != %d) on reselection from " 1237 "target %d\n", code - IDENTIFY_BASE, 1238 cmd->device->lun, ms->conn_tgt); 1239 } 1240 break; 1241 } 1242 goto reject; 1243 } 1244 return; 1245 1246 reject: 1247 printk(KERN_WARNING "mesh: rejecting message from target %d:", 1248 ms->conn_tgt); 1249 for (i = 0; i < ms->n_msgin; ++i) 1250 printk(" %x", ms->msgin[i]); 1251 printk("\n"); 1252 ms->msgout[0] = MESSAGE_REJECT; 1253 ms->n_msgout = 1; 1254 ms->msgphase = msg_out; 1255 } 1256 1257 /* 1258 * Set up DMA commands for transferring data. 1259 */ 1260 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd) 1261 { 1262 int i, dma_cmd, total, off, dtot; 1263 struct scatterlist *scl; 1264 struct dbdma_cmd *dcmds; 1265 1266 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out? 1267 OUTPUT_MORE: INPUT_MORE; 1268 dcmds = ms->dma_cmds; 1269 dtot = 0; 1270 if (cmd) { 1271 int nseg; 1272 1273 cmd->SCp.this_residual = scsi_bufflen(cmd); 1274 1275 nseg = scsi_dma_map(cmd); 1276 BUG_ON(nseg < 0); 1277 1278 if (nseg) { 1279 total = 0; 1280 off = ms->data_ptr; 1281 1282 scsi_for_each_sg(cmd, scl, nseg, i) { 1283 u32 dma_addr = sg_dma_address(scl); 1284 u32 dma_len = sg_dma_len(scl); 1285 1286 total += scl->length; 1287 if (off >= dma_len) { 1288 off -= dma_len; 1289 continue; 1290 } 1291 if (dma_len > 0xffff) 1292 panic("mesh: scatterlist element >= 64k"); 1293 st_le16(&dcmds->req_count, dma_len - off); 1294 st_le16(&dcmds->command, dma_cmd); 1295 st_le32(&dcmds->phy_addr, dma_addr + off); 1296 dcmds->xfer_status = 0; 1297 ++dcmds; 1298 dtot += dma_len - off; 1299 off = 0; 1300 } 1301 } 1302 } 1303 if (dtot == 0) { 1304 /* Either the target has overrun our buffer, 1305 or the caller didn't provide a buffer. */ 1306 static char mesh_extra_buf[64]; 1307 1308 dtot = sizeof(mesh_extra_buf); 1309 st_le16(&dcmds->req_count, dtot); 1310 st_le32(&dcmds->phy_addr, virt_to_phys(mesh_extra_buf)); 1311 dcmds->xfer_status = 0; 1312 ++dcmds; 1313 } 1314 dma_cmd += OUTPUT_LAST - OUTPUT_MORE; 1315 st_le16(&dcmds[-1].command, dma_cmd); 1316 memset(dcmds, 0, sizeof(*dcmds)); 1317 st_le16(&dcmds->command, DBDMA_STOP); 1318 ms->dma_count = dtot; 1319 } 1320 1321 static void halt_dma(struct mesh_state *ms) 1322 { 1323 volatile struct dbdma_regs __iomem *md = ms->dma; 1324 volatile struct mesh_regs __iomem *mr = ms->mesh; 1325 struct scsi_cmnd *cmd = ms->current_req; 1326 int t, nb; 1327 1328 if (!ms->tgts[ms->conn_tgt].data_goes_out) { 1329 /* wait a little while until the fifo drains */ 1330 t = 50; 1331 while (t > 0 && in_8(&mr->fifo_count) != 0 1332 && (in_le32(&md->status) & ACTIVE) != 0) { 1333 --t; 1334 udelay(1); 1335 } 1336 } 1337 out_le32(&md->control, RUN << 16); /* turn off RUN bit */ 1338 nb = (mr->count_hi << 8) + mr->count_lo; 1339 dlog(ms, "halt_dma fc/count=%.6x", 1340 MKWORD(0, mr->fifo_count, 0, nb)); 1341 if (ms->tgts[ms->conn_tgt].data_goes_out) 1342 nb += mr->fifo_count; 1343 /* nb is the number of bytes not yet transferred 1344 to/from the target. */ 1345 ms->data_ptr -= nb; 1346 dlog(ms, "data_ptr %x", ms->data_ptr); 1347 if (ms->data_ptr < 0) { 1348 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n", 1349 ms->data_ptr, nb, ms); 1350 ms->data_ptr = 0; 1351 #ifdef MESH_DBG 1352 dumplog(ms, ms->conn_tgt); 1353 dumpslog(ms); 1354 #endif /* MESH_DBG */ 1355 } else if (cmd && scsi_bufflen(cmd) && 1356 ms->data_ptr > scsi_bufflen(cmd)) { 1357 printk(KERN_DEBUG "mesh: target %d overrun, " 1358 "data_ptr=%x total=%x goes_out=%d\n", 1359 ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd), 1360 ms->tgts[ms->conn_tgt].data_goes_out); 1361 } 1362 scsi_dma_unmap(cmd); 1363 ms->dma_started = 0; 1364 } 1365 1366 static void phase_mismatch(struct mesh_state *ms) 1367 { 1368 volatile struct mesh_regs __iomem *mr = ms->mesh; 1369 int phase; 1370 1371 dlog(ms, "phasemm ch/cl/seq/fc=%.8x", 1372 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count)); 1373 phase = in_8(&mr->bus_status0) & BS0_PHASE; 1374 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) { 1375 /* output the last byte of the message, without ATN */ 1376 out_8(&mr->count_lo, 1); 1377 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); 1378 mesh_flush_io(mr); 1379 udelay(1); 1380 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); 1381 ms->msgphase = msg_out_last; 1382 return; 1383 } 1384 1385 if (ms->msgphase == msg_in) { 1386 get_msgin(ms); 1387 if (ms->n_msgin) 1388 handle_msgin(ms); 1389 } 1390 1391 if (ms->dma_started) 1392 halt_dma(ms); 1393 if (mr->fifo_count) { 1394 out_8(&mr->sequence, SEQ_FLUSHFIFO); 1395 mesh_flush_io(mr); 1396 udelay(1); 1397 } 1398 1399 ms->msgphase = msg_none; 1400 switch (phase) { 1401 case BP_DATAIN: 1402 ms->tgts[ms->conn_tgt].data_goes_out = 0; 1403 ms->phase = dataing; 1404 break; 1405 case BP_DATAOUT: 1406 ms->tgts[ms->conn_tgt].data_goes_out = 1; 1407 ms->phase = dataing; 1408 break; 1409 case BP_COMMAND: 1410 ms->phase = commanding; 1411 break; 1412 case BP_STATUS: 1413 ms->phase = statusing; 1414 break; 1415 case BP_MSGIN: 1416 ms->msgphase = msg_in; 1417 ms->n_msgin = 0; 1418 break; 1419 case BP_MSGOUT: 1420 ms->msgphase = msg_out; 1421 if (ms->n_msgout == 0) { 1422 if (ms->aborting) { 1423 do_abort(ms); 1424 } else { 1425 if (ms->last_n_msgout == 0) { 1426 printk(KERN_DEBUG 1427 "mesh: no msg to repeat\n"); 1428 ms->msgout[0] = NOP; 1429 ms->last_n_msgout = 1; 1430 } 1431 ms->n_msgout = ms->last_n_msgout; 1432 } 1433 } 1434 break; 1435 default: 1436 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase); 1437 ms->stat = DID_ERROR; 1438 mesh_done(ms, 1); 1439 return; 1440 } 1441 1442 start_phase(ms); 1443 } 1444 1445 static void cmd_complete(struct mesh_state *ms) 1446 { 1447 volatile struct mesh_regs __iomem *mr = ms->mesh; 1448 struct scsi_cmnd *cmd = ms->current_req; 1449 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; 1450 int seq, n, t; 1451 1452 dlog(ms, "cmd_complete fc=%x", mr->fifo_count); 1453 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0); 1454 switch (ms->msgphase) { 1455 case msg_out_xxx: 1456 /* huh? we expected a phase mismatch */ 1457 ms->n_msgin = 0; 1458 ms->msgphase = msg_in; 1459 /* fall through */ 1460 1461 case msg_in: 1462 /* should have some message bytes in fifo */ 1463 get_msgin(ms); 1464 n = msgin_length(ms); 1465 if (ms->n_msgin < n) { 1466 out_8(&mr->count_lo, n - ms->n_msgin); 1467 out_8(&mr->sequence, SEQ_MSGIN + seq); 1468 } else { 1469 ms->msgphase = msg_none; 1470 handle_msgin(ms); 1471 start_phase(ms); 1472 } 1473 break; 1474 1475 case msg_in_bad: 1476 out_8(&mr->sequence, SEQ_FLUSHFIFO); 1477 mesh_flush_io(mr); 1478 udelay(1); 1479 out_8(&mr->count_lo, 1); 1480 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg); 1481 break; 1482 1483 case msg_out: 1484 /* 1485 * To get the right timing on ATN wrt ACK, we have 1486 * to get the MESH to drop ACK, wait until REQ gets 1487 * asserted, then drop ATN. To do this we first 1488 * issue a SEQ_MSGOUT with ATN and wait for REQ, 1489 * then change the command to a SEQ_MSGOUT w/o ATN. 1490 * If we don't see REQ in a reasonable time, we 1491 * change the command to SEQ_MSGIN with ATN, 1492 * wait for the phase mismatch interrupt, then 1493 * issue the SEQ_MSGOUT without ATN. 1494 */ 1495 out_8(&mr->count_lo, 1); 1496 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN); 1497 t = 30; /* wait up to 30us */ 1498 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0) 1499 udelay(1); 1500 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x", 1501 MKWORD(mr->error, mr->exception, 1502 mr->fifo_count, mr->count_lo)); 1503 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) { 1504 /* whoops, target didn't do what we expected */ 1505 ms->last_n_msgout = ms->n_msgout; 1506 ms->n_msgout = 0; 1507 if (in_8(&mr->interrupt) & INT_ERROR) { 1508 printk(KERN_ERR "mesh: error %x in msg_out\n", 1509 in_8(&mr->error)); 1510 handle_error(ms); 1511 return; 1512 } 1513 if (in_8(&mr->exception) != EXC_PHASEMM) 1514 printk(KERN_ERR "mesh: exc %x in msg_out\n", 1515 in_8(&mr->exception)); 1516 else 1517 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n", 1518 in_8(&mr->bus_status0)); 1519 handle_exception(ms); 1520 return; 1521 } 1522 if (in_8(&mr->bus_status0) & BS0_REQ) { 1523 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); 1524 mesh_flush_io(mr); 1525 udelay(1); 1526 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); 1527 ms->msgphase = msg_out_last; 1528 } else { 1529 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN); 1530 ms->msgphase = msg_out_xxx; 1531 } 1532 break; 1533 1534 case msg_out_last: 1535 ms->last_n_msgout = ms->n_msgout; 1536 ms->n_msgout = 0; 1537 ms->msgphase = ms->expect_reply? msg_in: msg_none; 1538 start_phase(ms); 1539 break; 1540 1541 case msg_none: 1542 switch (ms->phase) { 1543 case idle: 1544 printk(KERN_ERR "mesh: interrupt in idle phase?\n"); 1545 dumpslog(ms); 1546 return; 1547 case selecting: 1548 dlog(ms, "Selecting phase at command completion",0); 1549 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt), 1550 (cmd? cmd->device->lun: 0)); 1551 ms->n_msgout = 1; 1552 ms->expect_reply = 0; 1553 if (ms->aborting) { 1554 ms->msgout[0] = ABORT; 1555 ms->n_msgout++; 1556 } else if (tp->sdtr_state == do_sdtr) { 1557 /* add SDTR message */ 1558 add_sdtr_msg(ms); 1559 ms->expect_reply = 1; 1560 tp->sdtr_state = sdtr_sent; 1561 } 1562 ms->msgphase = msg_out; 1563 /* 1564 * We need to wait for REQ before dropping ATN. 1565 * We wait for at most 30us, then fall back to 1566 * a scheme where we issue a SEQ_COMMAND with ATN, 1567 * which will give us a phase mismatch interrupt 1568 * when REQ does come, and then we send the message. 1569 */ 1570 t = 230; /* wait up to 230us */ 1571 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) { 1572 if (--t < 0) { 1573 dlog(ms, "impatient for req", ms->n_msgout); 1574 ms->msgphase = msg_none; 1575 break; 1576 } 1577 udelay(1); 1578 } 1579 break; 1580 case dataing: 1581 if (ms->dma_count != 0) { 1582 start_phase(ms); 1583 return; 1584 } 1585 /* 1586 * We can get a phase mismatch here if the target 1587 * changes to the status phase, even though we have 1588 * had a command complete interrupt. Then, if we 1589 * issue the SEQ_STATUS command, we'll get a sequence 1590 * error interrupt. Which isn't so bad except that 1591 * occasionally the mesh actually executes the 1592 * SEQ_STATUS *as well as* giving us the sequence 1593 * error and phase mismatch exception. 1594 */ 1595 out_8(&mr->sequence, 0); 1596 out_8(&mr->interrupt, 1597 INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 1598 halt_dma(ms); 1599 break; 1600 case statusing: 1601 if (cmd) { 1602 cmd->SCp.Status = mr->fifo; 1603 if (DEBUG_TARGET(cmd)) 1604 printk(KERN_DEBUG "mesh: status is %x\n", 1605 cmd->SCp.Status); 1606 } 1607 ms->msgphase = msg_in; 1608 break; 1609 case busfreeing: 1610 mesh_done(ms, 1); 1611 return; 1612 case disconnecting: 1613 ms->current_req = NULL; 1614 ms->phase = idle; 1615 mesh_start(ms); 1616 return; 1617 default: 1618 break; 1619 } 1620 ++ms->phase; 1621 start_phase(ms); 1622 break; 1623 } 1624 } 1625 1626 1627 /* 1628 * Called by midlayer with host locked to queue a new 1629 * request 1630 */ 1631 static int mesh_queue(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *)) 1632 { 1633 struct mesh_state *ms; 1634 1635 cmd->scsi_done = done; 1636 cmd->host_scribble = NULL; 1637 1638 ms = (struct mesh_state *) cmd->device->host->hostdata; 1639 1640 if (ms->request_q == NULL) 1641 ms->request_q = cmd; 1642 else 1643 ms->request_qtail->host_scribble = (void *) cmd; 1644 ms->request_qtail = cmd; 1645 1646 if (ms->phase == idle) 1647 mesh_start(ms); 1648 1649 return 0; 1650 } 1651 1652 /* 1653 * Called to handle interrupts, either call by the interrupt 1654 * handler (do_mesh_interrupt) or by other functions in 1655 * exceptional circumstances 1656 */ 1657 static void mesh_interrupt(struct mesh_state *ms) 1658 { 1659 volatile struct mesh_regs __iomem *mr = ms->mesh; 1660 int intr; 1661 1662 #if 0 1663 if (ALLOW_DEBUG(ms->conn_tgt)) 1664 printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x " 1665 "phase=%d msgphase=%d\n", mr->bus_status0, 1666 mr->interrupt, mr->exception, mr->error, 1667 ms->phase, ms->msgphase); 1668 #endif 1669 while ((intr = in_8(&mr->interrupt)) != 0) { 1670 dlog(ms, "interrupt intr/err/exc/seq=%.8x", 1671 MKWORD(intr, mr->error, mr->exception, mr->sequence)); 1672 if (intr & INT_ERROR) { 1673 handle_error(ms); 1674 } else if (intr & INT_EXCEPTION) { 1675 handle_exception(ms); 1676 } else if (intr & INT_CMDDONE) { 1677 out_8(&mr->interrupt, INT_CMDDONE); 1678 cmd_complete(ms); 1679 } 1680 } 1681 } 1682 1683 /* Todo: here we can at least try to remove the command from the 1684 * queue if it isn't connected yet, and for pending command, assert 1685 * ATN until the bus gets freed. 1686 */ 1687 static int mesh_abort(struct scsi_cmnd *cmd) 1688 { 1689 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata; 1690 1691 printk(KERN_DEBUG "mesh_abort(%p)\n", cmd); 1692 mesh_dump_regs(ms); 1693 dumplog(ms, cmd->device->id); 1694 dumpslog(ms); 1695 return FAILED; 1696 } 1697 1698 /* 1699 * Called by the midlayer with the lock held to reset the 1700 * SCSI host and bus. 1701 * The midlayer will wait for devices to come back, we don't need 1702 * to do that ourselves 1703 */ 1704 static int mesh_host_reset(struct scsi_cmnd *cmd) 1705 { 1706 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata; 1707 volatile struct mesh_regs __iomem *mr = ms->mesh; 1708 volatile struct dbdma_regs __iomem *md = ms->dma; 1709 unsigned long flags; 1710 1711 printk(KERN_DEBUG "mesh_host_reset\n"); 1712 1713 spin_lock_irqsave(ms->host->host_lock, flags); 1714 1715 /* Reset the controller & dbdma channel */ 1716 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ 1717 out_8(&mr->exception, 0xff); /* clear all exception bits */ 1718 out_8(&mr->error, 0xff); /* clear all error bits */ 1719 out_8(&mr->sequence, SEQ_RESETMESH); 1720 mesh_flush_io(mr); 1721 udelay(1); 1722 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 1723 out_8(&mr->source_id, ms->host->this_id); 1724 out_8(&mr->sel_timeout, 25); /* 250ms */ 1725 out_8(&mr->sync_params, ASYNC_PARAMS); 1726 1727 /* Reset the bus */ 1728 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ 1729 mesh_flush_io(mr); 1730 udelay(30); /* leave it on for >= 25us */ 1731 out_8(&mr->bus_status1, 0); /* negate RST */ 1732 1733 /* Complete pending commands */ 1734 handle_reset(ms); 1735 1736 spin_unlock_irqrestore(ms->host->host_lock, flags); 1737 return SUCCESS; 1738 } 1739 1740 static void set_mesh_power(struct mesh_state *ms, int state) 1741 { 1742 if (!machine_is(powermac)) 1743 return; 1744 if (state) { 1745 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1); 1746 msleep(200); 1747 } else { 1748 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0); 1749 msleep(10); 1750 } 1751 } 1752 1753 1754 #ifdef CONFIG_PM 1755 static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg) 1756 { 1757 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); 1758 unsigned long flags; 1759 1760 switch (mesg.event) { 1761 case PM_EVENT_SUSPEND: 1762 case PM_EVENT_HIBERNATE: 1763 case PM_EVENT_FREEZE: 1764 break; 1765 default: 1766 return 0; 1767 } 1768 if (ms->phase == sleeping) 1769 return 0; 1770 1771 scsi_block_requests(ms->host); 1772 spin_lock_irqsave(ms->host->host_lock, flags); 1773 while(ms->phase != idle) { 1774 spin_unlock_irqrestore(ms->host->host_lock, flags); 1775 msleep(10); 1776 spin_lock_irqsave(ms->host->host_lock, flags); 1777 } 1778 ms->phase = sleeping; 1779 spin_unlock_irqrestore(ms->host->host_lock, flags); 1780 disable_irq(ms->meshintr); 1781 set_mesh_power(ms, 0); 1782 1783 return 0; 1784 } 1785 1786 static int mesh_resume(struct macio_dev *mdev) 1787 { 1788 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); 1789 unsigned long flags; 1790 1791 if (ms->phase != sleeping) 1792 return 0; 1793 1794 set_mesh_power(ms, 1); 1795 mesh_init(ms); 1796 spin_lock_irqsave(ms->host->host_lock, flags); 1797 mesh_start(ms); 1798 spin_unlock_irqrestore(ms->host->host_lock, flags); 1799 enable_irq(ms->meshintr); 1800 scsi_unblock_requests(ms->host); 1801 1802 return 0; 1803 } 1804 1805 #endif /* CONFIG_PM */ 1806 1807 /* 1808 * If we leave drives set for synchronous transfers (especially 1809 * CDROMs), and reboot to MacOS, it gets confused, poor thing. 1810 * So, on reboot we reset the SCSI bus. 1811 */ 1812 static int mesh_shutdown(struct macio_dev *mdev) 1813 { 1814 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); 1815 volatile struct mesh_regs __iomem *mr; 1816 unsigned long flags; 1817 1818 printk(KERN_INFO "resetting MESH scsi bus(es)\n"); 1819 spin_lock_irqsave(ms->host->host_lock, flags); 1820 mr = ms->mesh; 1821 out_8(&mr->intr_mask, 0); 1822 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); 1823 out_8(&mr->bus_status1, BS1_RST); 1824 mesh_flush_io(mr); 1825 udelay(30); 1826 out_8(&mr->bus_status1, 0); 1827 spin_unlock_irqrestore(ms->host->host_lock, flags); 1828 1829 return 0; 1830 } 1831 1832 static struct scsi_host_template mesh_template = { 1833 .proc_name = "mesh", 1834 .name = "MESH", 1835 .queuecommand = mesh_queue, 1836 .eh_abort_handler = mesh_abort, 1837 .eh_host_reset_handler = mesh_host_reset, 1838 .can_queue = 20, 1839 .this_id = 7, 1840 .sg_tablesize = SG_ALL, 1841 .cmd_per_lun = 2, 1842 .use_clustering = DISABLE_CLUSTERING, 1843 }; 1844 1845 static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match) 1846 { 1847 struct device_node *mesh = macio_get_of_node(mdev); 1848 struct pci_dev* pdev = macio_get_pci_dev(mdev); 1849 int tgt, minper; 1850 const int *cfp; 1851 struct mesh_state *ms; 1852 struct Scsi_Host *mesh_host; 1853 void *dma_cmd_space; 1854 dma_addr_t dma_cmd_bus; 1855 1856 switch (mdev->bus->chip->type) { 1857 case macio_heathrow: 1858 case macio_gatwick: 1859 case macio_paddington: 1860 use_active_neg = 0; 1861 break; 1862 default: 1863 use_active_neg = SEQ_ACTIVE_NEG; 1864 } 1865 1866 if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) { 1867 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs" 1868 " (got %d,%d)\n", macio_resource_count(mdev), 1869 macio_irq_count(mdev)); 1870 return -ENODEV; 1871 } 1872 1873 if (macio_request_resources(mdev, "mesh") != 0) { 1874 printk(KERN_ERR "mesh: unable to request memory resources"); 1875 return -EBUSY; 1876 } 1877 mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state)); 1878 if (mesh_host == NULL) { 1879 printk(KERN_ERR "mesh: couldn't register host"); 1880 goto out_release; 1881 } 1882 1883 /* Old junk for root discovery, that will die ultimately */ 1884 #if !defined(MODULE) 1885 note_scsi_host(mesh, mesh_host); 1886 #endif 1887 1888 mesh_host->base = macio_resource_start(mdev, 0); 1889 mesh_host->irq = macio_irq(mdev, 0); 1890 ms = (struct mesh_state *) mesh_host->hostdata; 1891 macio_set_drvdata(mdev, ms); 1892 ms->host = mesh_host; 1893 ms->mdev = mdev; 1894 ms->pdev = pdev; 1895 1896 ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000); 1897 if (ms->mesh == NULL) { 1898 printk(KERN_ERR "mesh: can't map registers\n"); 1899 goto out_free; 1900 } 1901 ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000); 1902 if (ms->dma == NULL) { 1903 printk(KERN_ERR "mesh: can't map registers\n"); 1904 iounmap(ms->mesh); 1905 goto out_free; 1906 } 1907 1908 ms->meshintr = macio_irq(mdev, 0); 1909 ms->dmaintr = macio_irq(mdev, 1); 1910 1911 /* Space for dma command list: +1 for stop command, 1912 * +1 to allow for aligning. 1913 */ 1914 ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd); 1915 1916 /* We use the PCI APIs for now until the generic one gets fixed 1917 * enough or until we get some macio-specific versions 1918 */ 1919 dma_cmd_space = pci_alloc_consistent(macio_get_pci_dev(mdev), 1920 ms->dma_cmd_size, 1921 &dma_cmd_bus); 1922 if (dma_cmd_space == NULL) { 1923 printk(KERN_ERR "mesh: can't allocate DMA table\n"); 1924 goto out_unmap; 1925 } 1926 memset(dma_cmd_space, 0, ms->dma_cmd_size); 1927 1928 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space); 1929 ms->dma_cmd_space = dma_cmd_space; 1930 ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds) 1931 - (unsigned long)dma_cmd_space; 1932 ms->current_req = NULL; 1933 for (tgt = 0; tgt < 8; ++tgt) { 1934 ms->tgts[tgt].sdtr_state = do_sdtr; 1935 ms->tgts[tgt].sync_params = ASYNC_PARAMS; 1936 ms->tgts[tgt].current_req = NULL; 1937 } 1938 1939 if ((cfp = of_get_property(mesh, "clock-frequency", NULL))) 1940 ms->clk_freq = *cfp; 1941 else { 1942 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n"); 1943 ms->clk_freq = 50000000; 1944 } 1945 1946 /* The maximum sync rate is clock / 5; increase 1947 * mesh_sync_period if necessary. 1948 */ 1949 minper = 1000000000 / (ms->clk_freq / 5); /* ns */ 1950 if (mesh_sync_period < minper) 1951 mesh_sync_period = minper; 1952 1953 /* Power up the chip */ 1954 set_mesh_power(ms, 1); 1955 1956 /* Set it up */ 1957 mesh_init(ms); 1958 1959 /* Request interrupt */ 1960 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) { 1961 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr); 1962 goto out_shutdown; 1963 } 1964 1965 /* Add scsi host & scan */ 1966 if (scsi_add_host(mesh_host, &mdev->ofdev.dev)) 1967 goto out_release_irq; 1968 scsi_scan_host(mesh_host); 1969 1970 return 0; 1971 1972 out_release_irq: 1973 free_irq(ms->meshintr, ms); 1974 out_shutdown: 1975 /* shutdown & reset bus in case of error or macos can be confused 1976 * at reboot if the bus was set to synchronous mode already 1977 */ 1978 mesh_shutdown(mdev); 1979 set_mesh_power(ms, 0); 1980 pci_free_consistent(macio_get_pci_dev(mdev), ms->dma_cmd_size, 1981 ms->dma_cmd_space, ms->dma_cmd_bus); 1982 out_unmap: 1983 iounmap(ms->dma); 1984 iounmap(ms->mesh); 1985 out_free: 1986 scsi_host_put(mesh_host); 1987 out_release: 1988 macio_release_resources(mdev); 1989 1990 return -ENODEV; 1991 } 1992 1993 static int mesh_remove(struct macio_dev *mdev) 1994 { 1995 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); 1996 struct Scsi_Host *mesh_host = ms->host; 1997 1998 scsi_remove_host(mesh_host); 1999 2000 free_irq(ms->meshintr, ms); 2001 2002 /* Reset scsi bus */ 2003 mesh_shutdown(mdev); 2004 2005 /* Shut down chip & termination */ 2006 set_mesh_power(ms, 0); 2007 2008 /* Unmap registers & dma controller */ 2009 iounmap(ms->mesh); 2010 iounmap(ms->dma); 2011 2012 /* Free DMA commands memory */ 2013 pci_free_consistent(macio_get_pci_dev(mdev), ms->dma_cmd_size, 2014 ms->dma_cmd_space, ms->dma_cmd_bus); 2015 2016 /* Release memory resources */ 2017 macio_release_resources(mdev); 2018 2019 scsi_host_put(mesh_host); 2020 2021 return 0; 2022 } 2023 2024 2025 static struct of_device_id mesh_match[] = 2026 { 2027 { 2028 .name = "mesh", 2029 }, 2030 { 2031 .type = "scsi", 2032 .compatible = "chrp,mesh0" 2033 }, 2034 {}, 2035 }; 2036 MODULE_DEVICE_TABLE (of, mesh_match); 2037 2038 static struct macio_driver mesh_driver = 2039 { 2040 .name = "mesh", 2041 .match_table = mesh_match, 2042 .probe = mesh_probe, 2043 .remove = mesh_remove, 2044 .shutdown = mesh_shutdown, 2045 #ifdef CONFIG_PM 2046 .suspend = mesh_suspend, 2047 .resume = mesh_resume, 2048 #endif 2049 }; 2050 2051 2052 static int __init init_mesh(void) 2053 { 2054 2055 /* Calculate sync rate from module parameters */ 2056 if (sync_rate > 10) 2057 sync_rate = 10; 2058 if (sync_rate > 0) { 2059 printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate); 2060 mesh_sync_period = 1000 / sync_rate; /* ns */ 2061 mesh_sync_offset = 15; 2062 } else 2063 printk(KERN_INFO "mesh: configured for asynchronous\n"); 2064 2065 return macio_register_driver(&mesh_driver); 2066 } 2067 2068 static void __exit exit_mesh(void) 2069 { 2070 return macio_unregister_driver(&mesh_driver); 2071 } 2072 2073 module_init(init_mesh); 2074 module_exit(exit_mesh); 2075