1 /* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2003-2013 LSI Corporation 5 * Copyright (c) 2013-2014 Avago Technologies 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 * 20 * FILE: megaraid_sas.h 21 * 22 * Authors: Avago Technologies 23 * Kashyap Desai <kashyap.desai@avagotech.com> 24 * Sumit Saxena <sumit.saxena@avagotech.com> 25 * 26 * Send feedback to: megaraidlinux.pdl@avagotech.com 27 * 28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, 29 * San Jose, California 95131 30 */ 31 32 #ifndef LSI_MEGARAID_SAS_H 33 #define LSI_MEGARAID_SAS_H 34 35 /* 36 * MegaRAID SAS Driver meta data 37 */ 38 #define MEGASAS_VERSION "07.701.17.00-rc1" 39 #define MEGASAS_RELDATE "March 2, 2017" 40 41 /* 42 * Device IDs 43 */ 44 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 45 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 51 #define PCI_DEVICE_ID_LSI_FUSION 0x005b 52 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f 53 #define PCI_DEVICE_ID_LSI_INVADER 0x005d 54 #define PCI_DEVICE_ID_LSI_FURY 0x005f 55 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce 56 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf 57 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052 58 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053 59 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014 60 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016 61 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017 62 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B 63 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C 64 65 /* 66 * Intel HBA SSDIDs 67 */ 68 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 69 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 70 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 71 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 72 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 73 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 74 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B 75 76 /* 77 * Intruder HBA SSDIDs 78 */ 79 #define MEGARAID_INTRUDER_SSDID1 0x9371 80 #define MEGARAID_INTRUDER_SSDID2 0x9390 81 #define MEGARAID_INTRUDER_SSDID3 0x9370 82 83 /* 84 * Intel HBA branding 85 */ 86 #define MEGARAID_INTEL_RS3DC080_BRANDING \ 87 "Intel(R) RAID Controller RS3DC080" 88 #define MEGARAID_INTEL_RS3DC040_BRANDING \ 89 "Intel(R) RAID Controller RS3DC040" 90 #define MEGARAID_INTEL_RS3SC008_BRANDING \ 91 "Intel(R) RAID Controller RS3SC008" 92 #define MEGARAID_INTEL_RS3MC044_BRANDING \ 93 "Intel(R) RAID Controller RS3MC044" 94 #define MEGARAID_INTEL_RS3WC080_BRANDING \ 95 "Intel(R) RAID Controller RS3WC080" 96 #define MEGARAID_INTEL_RS3WC040_BRANDING \ 97 "Intel(R) RAID Controller RS3WC040" 98 #define MEGARAID_INTEL_RMS3BC160_BRANDING \ 99 "Intel(R) Integrated RAID Module RMS3BC160" 100 101 /* 102 * ===================================== 103 * MegaRAID SAS MFI firmware definitions 104 * ===================================== 105 */ 106 107 /* 108 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 109 * protocol between the software and firmware. Commands are issued using 110 * "message frames" 111 */ 112 113 /* 114 * FW posts its state in upper 4 bits of outbound_msg_0 register 115 */ 116 #define MFI_STATE_MASK 0xF0000000 117 #define MFI_STATE_UNDEFINED 0x00000000 118 #define MFI_STATE_BB_INIT 0x10000000 119 #define MFI_STATE_FW_INIT 0x40000000 120 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 121 #define MFI_STATE_FW_INIT_2 0x70000000 122 #define MFI_STATE_DEVICE_SCAN 0x80000000 123 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 124 #define MFI_STATE_FLUSH_CACHE 0xA0000000 125 #define MFI_STATE_READY 0xB0000000 126 #define MFI_STATE_OPERATIONAL 0xC0000000 127 #define MFI_STATE_FAULT 0xF0000000 128 #define MFI_STATE_FORCE_OCR 0x00000080 129 #define MFI_STATE_DMADONE 0x00000008 130 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004 131 #define MFI_RESET_REQUIRED 0x00000001 132 #define MFI_RESET_ADAPTER 0x00000002 133 #define MEGAMFI_FRAME_SIZE 64 134 135 /* 136 * During FW init, clear pending cmds & reset state using inbound_msg_0 137 * 138 * ABORT : Abort all pending cmds 139 * READY : Move from OPERATIONAL to READY state; discard queue info 140 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 141 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 142 * HOTPLUG : Resume from Hotplug 143 * MFI_STOP_ADP : Send signal to FW to stop processing 144 */ 145 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 146 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 147 #define DIAG_WRITE_ENABLE (0x00000080) 148 #define DIAG_RESET_ADAPTER (0x00000004) 149 150 #define MFI_ADP_RESET 0x00000040 151 #define MFI_INIT_ABORT 0x00000001 152 #define MFI_INIT_READY 0x00000002 153 #define MFI_INIT_MFIMODE 0x00000004 154 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 155 #define MFI_INIT_HOTPLUG 0x00000010 156 #define MFI_STOP_ADP 0x00000020 157 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 158 MFI_INIT_MFIMODE| \ 159 MFI_INIT_ABORT 160 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 161 162 /* 163 * MFI frame flags 164 */ 165 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 166 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 167 #define MFI_FRAME_SGL32 0x0000 168 #define MFI_FRAME_SGL64 0x0002 169 #define MFI_FRAME_SENSE32 0x0000 170 #define MFI_FRAME_SENSE64 0x0004 171 #define MFI_FRAME_DIR_NONE 0x0000 172 #define MFI_FRAME_DIR_WRITE 0x0008 173 #define MFI_FRAME_DIR_READ 0x0010 174 #define MFI_FRAME_DIR_BOTH 0x0018 175 #define MFI_FRAME_IEEE 0x0020 176 177 /* Driver internal */ 178 #define DRV_DCMD_POLLED_MODE 0x1 179 #define DRV_DCMD_SKIP_REFIRE 0x2 180 181 /* 182 * Definition for cmd_status 183 */ 184 #define MFI_CMD_STATUS_POLL_MODE 0xFF 185 186 /* 187 * MFI command opcodes 188 */ 189 #define MFI_CMD_INIT 0x00 190 #define MFI_CMD_LD_READ 0x01 191 #define MFI_CMD_LD_WRITE 0x02 192 #define MFI_CMD_LD_SCSI_IO 0x03 193 #define MFI_CMD_PD_SCSI_IO 0x04 194 #define MFI_CMD_DCMD 0x05 195 #define MFI_CMD_ABORT 0x06 196 #define MFI_CMD_SMP 0x07 197 #define MFI_CMD_STP 0x08 198 #define MFI_CMD_INVALID 0xff 199 200 #define MR_DCMD_CTRL_GET_INFO 0x01010000 201 #define MR_DCMD_LD_GET_LIST 0x03010000 202 #define MR_DCMD_LD_LIST_QUERY 0x03010100 203 204 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 205 #define MR_FLUSH_CTRL_CACHE 0x01 206 #define MR_FLUSH_DISK_CACHE 0x02 207 208 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 209 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 210 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 211 212 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 213 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 214 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 215 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 216 217 #define MR_DCMD_CLUSTER 0x08000000 218 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 219 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 220 #define MR_DCMD_PD_LIST_QUERY 0x02010100 221 222 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100 223 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600) 224 #define MR_DCMD_PD_GET_INFO 0x02020000 225 226 /* 227 * Global functions 228 */ 229 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance); 230 231 232 /* 233 * MFI command completion codes 234 */ 235 enum MFI_STAT { 236 MFI_STAT_OK = 0x00, 237 MFI_STAT_INVALID_CMD = 0x01, 238 MFI_STAT_INVALID_DCMD = 0x02, 239 MFI_STAT_INVALID_PARAMETER = 0x03, 240 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 241 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 242 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 243 MFI_STAT_APP_IN_USE = 0x07, 244 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 245 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 246 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 247 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 248 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 249 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 250 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 251 MFI_STAT_FLASH_BUSY = 0x0f, 252 MFI_STAT_FLASH_ERROR = 0x10, 253 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 254 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 255 MFI_STAT_FLASH_NOT_OPEN = 0x13, 256 MFI_STAT_FLASH_NOT_STARTED = 0x14, 257 MFI_STAT_FLUSH_FAILED = 0x15, 258 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 259 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 260 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 261 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 262 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 263 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 264 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 265 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 266 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 267 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 268 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 269 MFI_STAT_MFC_HW_ERROR = 0x21, 270 MFI_STAT_NO_HW_PRESENT = 0x22, 271 MFI_STAT_NOT_FOUND = 0x23, 272 MFI_STAT_NOT_IN_ENCL = 0x24, 273 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 274 MFI_STAT_PD_TYPE_WRONG = 0x26, 275 MFI_STAT_PR_DISABLED = 0x27, 276 MFI_STAT_ROW_INDEX_INVALID = 0x28, 277 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 278 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 279 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 280 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 281 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 282 MFI_STAT_SCSI_IO_FAILED = 0x2e, 283 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 284 MFI_STAT_SHUTDOWN_FAILED = 0x30, 285 MFI_STAT_TIME_NOT_SET = 0x31, 286 MFI_STAT_WRONG_STATE = 0x32, 287 MFI_STAT_LD_OFFLINE = 0x33, 288 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 289 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 290 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 291 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 292 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 293 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 294 295 MFI_STAT_INVALID_STATUS = 0xFF 296 }; 297 298 enum mfi_evt_class { 299 MFI_EVT_CLASS_DEBUG = -2, 300 MFI_EVT_CLASS_PROGRESS = -1, 301 MFI_EVT_CLASS_INFO = 0, 302 MFI_EVT_CLASS_WARNING = 1, 303 MFI_EVT_CLASS_CRITICAL = 2, 304 MFI_EVT_CLASS_FATAL = 3, 305 MFI_EVT_CLASS_DEAD = 4 306 }; 307 308 /* 309 * Crash dump related defines 310 */ 311 #define MAX_CRASH_DUMP_SIZE 512 312 #define CRASH_DMA_BUF_SIZE (1024 * 1024) 313 314 enum MR_FW_CRASH_DUMP_STATE { 315 UNAVAILABLE = 0, 316 AVAILABLE = 1, 317 COPYING = 2, 318 COPIED = 3, 319 COPY_ERROR = 4, 320 }; 321 322 enum _MR_CRASH_BUF_STATUS { 323 MR_CRASH_BUF_TURN_OFF = 0, 324 MR_CRASH_BUF_TURN_ON = 1, 325 }; 326 327 /* 328 * Number of mailbox bytes in DCMD message frame 329 */ 330 #define MFI_MBOX_SIZE 12 331 332 enum MR_EVT_CLASS { 333 334 MR_EVT_CLASS_DEBUG = -2, 335 MR_EVT_CLASS_PROGRESS = -1, 336 MR_EVT_CLASS_INFO = 0, 337 MR_EVT_CLASS_WARNING = 1, 338 MR_EVT_CLASS_CRITICAL = 2, 339 MR_EVT_CLASS_FATAL = 3, 340 MR_EVT_CLASS_DEAD = 4, 341 342 }; 343 344 enum MR_EVT_LOCALE { 345 346 MR_EVT_LOCALE_LD = 0x0001, 347 MR_EVT_LOCALE_PD = 0x0002, 348 MR_EVT_LOCALE_ENCL = 0x0004, 349 MR_EVT_LOCALE_BBU = 0x0008, 350 MR_EVT_LOCALE_SAS = 0x0010, 351 MR_EVT_LOCALE_CTRL = 0x0020, 352 MR_EVT_LOCALE_CONFIG = 0x0040, 353 MR_EVT_LOCALE_CLUSTER = 0x0080, 354 MR_EVT_LOCALE_ALL = 0xffff, 355 356 }; 357 358 enum MR_EVT_ARGS { 359 360 MR_EVT_ARGS_NONE, 361 MR_EVT_ARGS_CDB_SENSE, 362 MR_EVT_ARGS_LD, 363 MR_EVT_ARGS_LD_COUNT, 364 MR_EVT_ARGS_LD_LBA, 365 MR_EVT_ARGS_LD_OWNER, 366 MR_EVT_ARGS_LD_LBA_PD_LBA, 367 MR_EVT_ARGS_LD_PROG, 368 MR_EVT_ARGS_LD_STATE, 369 MR_EVT_ARGS_LD_STRIP, 370 MR_EVT_ARGS_PD, 371 MR_EVT_ARGS_PD_ERR, 372 MR_EVT_ARGS_PD_LBA, 373 MR_EVT_ARGS_PD_LBA_LD, 374 MR_EVT_ARGS_PD_PROG, 375 MR_EVT_ARGS_PD_STATE, 376 MR_EVT_ARGS_PCI, 377 MR_EVT_ARGS_RATE, 378 MR_EVT_ARGS_STR, 379 MR_EVT_ARGS_TIME, 380 MR_EVT_ARGS_ECC, 381 MR_EVT_ARGS_LD_PROP, 382 MR_EVT_ARGS_PD_SPARE, 383 MR_EVT_ARGS_PD_INDEX, 384 MR_EVT_ARGS_DIAG_PASS, 385 MR_EVT_ARGS_DIAG_FAIL, 386 MR_EVT_ARGS_PD_LBA_LBA, 387 MR_EVT_ARGS_PORT_PHY, 388 MR_EVT_ARGS_PD_MISSING, 389 MR_EVT_ARGS_PD_ADDRESS, 390 MR_EVT_ARGS_BITMAP, 391 MR_EVT_ARGS_CONNECTOR, 392 MR_EVT_ARGS_PD_PD, 393 MR_EVT_ARGS_PD_FRU, 394 MR_EVT_ARGS_PD_PATHINFO, 395 MR_EVT_ARGS_PD_POWER_STATE, 396 MR_EVT_ARGS_GENERIC, 397 }; 398 399 400 #define SGE_BUFFER_SIZE 4096 401 #define MEGASAS_CLUSTER_ID_SIZE 16 402 /* 403 * define constants for device list query options 404 */ 405 enum MR_PD_QUERY_TYPE { 406 MR_PD_QUERY_TYPE_ALL = 0, 407 MR_PD_QUERY_TYPE_STATE = 1, 408 MR_PD_QUERY_TYPE_POWER_STATE = 2, 409 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 410 MR_PD_QUERY_TYPE_SPEED = 4, 411 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 412 }; 413 414 enum MR_LD_QUERY_TYPE { 415 MR_LD_QUERY_TYPE_ALL = 0, 416 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, 417 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, 418 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, 419 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, 420 }; 421 422 423 #define MR_EVT_CFG_CLEARED 0x0004 424 #define MR_EVT_LD_STATE_CHANGE 0x0051 425 #define MR_EVT_PD_INSERTED 0x005b 426 #define MR_EVT_PD_REMOVED 0x0070 427 #define MR_EVT_LD_CREATED 0x008a 428 #define MR_EVT_LD_DELETED 0x008b 429 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 430 #define MR_EVT_LD_OFFLINE 0x00fc 431 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 432 #define MR_EVT_CTRL_PROP_CHANGED 0x012f 433 434 enum MR_PD_STATE { 435 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 436 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 437 MR_PD_STATE_HOT_SPARE = 0x02, 438 MR_PD_STATE_OFFLINE = 0x10, 439 MR_PD_STATE_FAILED = 0x11, 440 MR_PD_STATE_REBUILD = 0x14, 441 MR_PD_STATE_ONLINE = 0x18, 442 MR_PD_STATE_COPYBACK = 0x20, 443 MR_PD_STATE_SYSTEM = 0x40, 444 }; 445 446 union MR_PD_REF { 447 struct { 448 u16 deviceId; 449 u16 seqNum; 450 } mrPdRef; 451 u32 ref; 452 }; 453 454 /* 455 * define the DDF Type bit structure 456 */ 457 union MR_PD_DDF_TYPE { 458 struct { 459 union { 460 struct { 461 #ifndef __BIG_ENDIAN_BITFIELD 462 u16 forcedPDGUID:1; 463 u16 inVD:1; 464 u16 isGlobalSpare:1; 465 u16 isSpare:1; 466 u16 isForeign:1; 467 u16 reserved:7; 468 u16 intf:4; 469 #else 470 u16 intf:4; 471 u16 reserved:7; 472 u16 isForeign:1; 473 u16 isSpare:1; 474 u16 isGlobalSpare:1; 475 u16 inVD:1; 476 u16 forcedPDGUID:1; 477 #endif 478 } pdType; 479 u16 type; 480 }; 481 u16 reserved; 482 } ddf; 483 struct { 484 u32 reserved; 485 } nonDisk; 486 u32 type; 487 } __packed; 488 489 /* 490 * defines the progress structure 491 */ 492 union MR_PROGRESS { 493 struct { 494 u16 progress; 495 union { 496 u16 elapsedSecs; 497 u16 elapsedSecsForLastPercent; 498 }; 499 } mrProgress; 500 u32 w; 501 } __packed; 502 503 /* 504 * defines the physical drive progress structure 505 */ 506 struct MR_PD_PROGRESS { 507 struct { 508 #ifndef MFI_BIG_ENDIAN 509 u32 rbld:1; 510 u32 patrol:1; 511 u32 clear:1; 512 u32 copyBack:1; 513 u32 erase:1; 514 u32 locate:1; 515 u32 reserved:26; 516 #else 517 u32 reserved:26; 518 u32 locate:1; 519 u32 erase:1; 520 u32 copyBack:1; 521 u32 clear:1; 522 u32 patrol:1; 523 u32 rbld:1; 524 #endif 525 } active; 526 union MR_PROGRESS rbld; 527 union MR_PROGRESS patrol; 528 union { 529 union MR_PROGRESS clear; 530 union MR_PROGRESS erase; 531 }; 532 533 struct { 534 #ifndef MFI_BIG_ENDIAN 535 u32 rbld:1; 536 u32 patrol:1; 537 u32 clear:1; 538 u32 copyBack:1; 539 u32 erase:1; 540 u32 reserved:27; 541 #else 542 u32 reserved:27; 543 u32 erase:1; 544 u32 copyBack:1; 545 u32 clear:1; 546 u32 patrol:1; 547 u32 rbld:1; 548 #endif 549 } pause; 550 551 union MR_PROGRESS reserved[3]; 552 } __packed; 553 554 struct MR_PD_INFO { 555 union MR_PD_REF ref; 556 u8 inquiryData[96]; 557 u8 vpdPage83[64]; 558 u8 notSupported; 559 u8 scsiDevType; 560 561 union { 562 u8 connectedPortBitmap; 563 u8 connectedPortNumbers; 564 }; 565 566 u8 deviceSpeed; 567 u32 mediaErrCount; 568 u32 otherErrCount; 569 u32 predFailCount; 570 u32 lastPredFailEventSeqNum; 571 572 u16 fwState; 573 u8 disabledForRemoval; 574 u8 linkSpeed; 575 union MR_PD_DDF_TYPE state; 576 577 struct { 578 u8 count; 579 #ifndef __BIG_ENDIAN_BITFIELD 580 u8 isPathBroken:4; 581 u8 reserved3:3; 582 u8 widePortCapable:1; 583 #else 584 u8 widePortCapable:1; 585 u8 reserved3:3; 586 u8 isPathBroken:4; 587 #endif 588 589 u8 connectorIndex[2]; 590 u8 reserved[4]; 591 u64 sasAddr[2]; 592 u8 reserved2[16]; 593 } pathInfo; 594 595 u64 rawSize; 596 u64 nonCoercedSize; 597 u64 coercedSize; 598 u16 enclDeviceId; 599 u8 enclIndex; 600 601 union { 602 u8 slotNumber; 603 u8 enclConnectorIndex; 604 }; 605 606 struct MR_PD_PROGRESS progInfo; 607 u8 badBlockTableFull; 608 u8 unusableInCurrentConfig; 609 u8 vpdPage83Ext[64]; 610 u8 powerState; 611 u8 enclPosition; 612 u32 allowedOps; 613 u16 copyBackPartnerId; 614 u16 enclPartnerDeviceId; 615 struct { 616 #ifndef __BIG_ENDIAN_BITFIELD 617 u16 fdeCapable:1; 618 u16 fdeEnabled:1; 619 u16 secured:1; 620 u16 locked:1; 621 u16 foreign:1; 622 u16 needsEKM:1; 623 u16 reserved:10; 624 #else 625 u16 reserved:10; 626 u16 needsEKM:1; 627 u16 foreign:1; 628 u16 locked:1; 629 u16 secured:1; 630 u16 fdeEnabled:1; 631 u16 fdeCapable:1; 632 #endif 633 } security; 634 u8 mediaType; 635 u8 notCertified; 636 u8 bridgeVendor[8]; 637 u8 bridgeProductIdentification[16]; 638 u8 bridgeProductRevisionLevel[4]; 639 u8 satBridgeExists; 640 641 u8 interfaceType; 642 u8 temperature; 643 u8 emulatedBlockSize; 644 u16 userDataBlockSize; 645 u16 reserved2; 646 647 struct { 648 #ifndef __BIG_ENDIAN_BITFIELD 649 u32 piType:3; 650 u32 piFormatted:1; 651 u32 piEligible:1; 652 u32 NCQ:1; 653 u32 WCE:1; 654 u32 commissionedSpare:1; 655 u32 emergencySpare:1; 656 u32 ineligibleForSSCD:1; 657 u32 ineligibleForLd:1; 658 u32 useSSEraseType:1; 659 u32 wceUnchanged:1; 660 u32 supportScsiUnmap:1; 661 u32 reserved:18; 662 #else 663 u32 reserved:18; 664 u32 supportScsiUnmap:1; 665 u32 wceUnchanged:1; 666 u32 useSSEraseType:1; 667 u32 ineligibleForLd:1; 668 u32 ineligibleForSSCD:1; 669 u32 emergencySpare:1; 670 u32 commissionedSpare:1; 671 u32 WCE:1; 672 u32 NCQ:1; 673 u32 piEligible:1; 674 u32 piFormatted:1; 675 u32 piType:3; 676 #endif 677 } properties; 678 679 u64 shieldDiagCompletionTime; 680 u8 shieldCounter; 681 682 u8 linkSpeedOther; 683 u8 reserved4[2]; 684 685 struct { 686 #ifndef __BIG_ENDIAN_BITFIELD 687 u32 bbmErrCountSupported:1; 688 u32 bbmErrCount:31; 689 #else 690 u32 bbmErrCount:31; 691 u32 bbmErrCountSupported:1; 692 #endif 693 } bbmErr; 694 695 u8 reserved1[512-428]; 696 } __packed; 697 698 /* 699 * Definition of structure used to expose attributes of VD or JBOD 700 * (this structure is to be filled by firmware when MR_DCMD_DRV_GET_TARGET_PROP 701 * is fired by driver) 702 */ 703 struct MR_TARGET_PROPERTIES { 704 u32 max_io_size_kb; 705 u32 device_qdepth; 706 u32 sector_size; 707 u8 reserved[500]; 708 } __packed; 709 710 /* 711 * defines the physical drive address structure 712 */ 713 struct MR_PD_ADDRESS { 714 __le16 deviceId; 715 u16 enclDeviceId; 716 717 union { 718 struct { 719 u8 enclIndex; 720 u8 slotNumber; 721 } mrPdAddress; 722 struct { 723 u8 enclPosition; 724 u8 enclConnectorIndex; 725 } mrEnclAddress; 726 }; 727 u8 scsiDevType; 728 union { 729 u8 connectedPortBitmap; 730 u8 connectedPortNumbers; 731 }; 732 u64 sasAddr[2]; 733 } __packed; 734 735 /* 736 * defines the physical drive list structure 737 */ 738 struct MR_PD_LIST { 739 __le32 size; 740 __le32 count; 741 struct MR_PD_ADDRESS addr[1]; 742 } __packed; 743 744 struct megasas_pd_list { 745 u16 tid; 746 u8 driveType; 747 u8 driveState; 748 } __packed; 749 750 /* 751 * defines the logical drive reference structure 752 */ 753 union MR_LD_REF { 754 struct { 755 u8 targetId; 756 u8 reserved; 757 __le16 seqNum; 758 }; 759 __le32 ref; 760 } __packed; 761 762 /* 763 * defines the logical drive list structure 764 */ 765 struct MR_LD_LIST { 766 __le32 ldCount; 767 __le32 reserved; 768 struct { 769 union MR_LD_REF ref; 770 u8 state; 771 u8 reserved[3]; 772 __le64 size; 773 } ldList[MAX_LOGICAL_DRIVES_EXT]; 774 } __packed; 775 776 struct MR_LD_TARGETID_LIST { 777 __le32 size; 778 __le32 count; 779 u8 pad[3]; 780 u8 targetId[MAX_LOGICAL_DRIVES_EXT]; 781 }; 782 783 784 /* 785 * SAS controller properties 786 */ 787 struct megasas_ctrl_prop { 788 789 u16 seq_num; 790 u16 pred_fail_poll_interval; 791 u16 intr_throttle_count; 792 u16 intr_throttle_timeouts; 793 u8 rebuild_rate; 794 u8 patrol_read_rate; 795 u8 bgi_rate; 796 u8 cc_rate; 797 u8 recon_rate; 798 u8 cache_flush_interval; 799 u8 spinup_drv_count; 800 u8 spinup_delay; 801 u8 cluster_enable; 802 u8 coercion_mode; 803 u8 alarm_enable; 804 u8 disable_auto_rebuild; 805 u8 disable_battery_warn; 806 u8 ecc_bucket_size; 807 u16 ecc_bucket_leak_rate; 808 u8 restore_hotspare_on_insertion; 809 u8 expose_encl_devices; 810 u8 maintainPdFailHistory; 811 u8 disallowHostRequestReordering; 812 u8 abortCCOnError; 813 u8 loadBalanceMode; 814 u8 disableAutoDetectBackplane; 815 816 u8 snapVDSpace; 817 818 /* 819 * Add properties that can be controlled by 820 * a bit in the following structure. 821 */ 822 struct { 823 #if defined(__BIG_ENDIAN_BITFIELD) 824 u32 reserved:18; 825 u32 enableJBOD:1; 826 u32 disableSpinDownHS:1; 827 u32 allowBootWithPinnedCache:1; 828 u32 disableOnlineCtrlReset:1; 829 u32 enableSecretKeyControl:1; 830 u32 autoEnhancedImport:1; 831 u32 enableSpinDownUnconfigured:1; 832 u32 SSDPatrolReadEnabled:1; 833 u32 SSDSMARTerEnabled:1; 834 u32 disableNCQ:1; 835 u32 useFdeOnly:1; 836 u32 prCorrectUnconfiguredAreas:1; 837 u32 SMARTerEnabled:1; 838 u32 copyBackDisabled:1; 839 #else 840 u32 copyBackDisabled:1; 841 u32 SMARTerEnabled:1; 842 u32 prCorrectUnconfiguredAreas:1; 843 u32 useFdeOnly:1; 844 u32 disableNCQ:1; 845 u32 SSDSMARTerEnabled:1; 846 u32 SSDPatrolReadEnabled:1; 847 u32 enableSpinDownUnconfigured:1; 848 u32 autoEnhancedImport:1; 849 u32 enableSecretKeyControl:1; 850 u32 disableOnlineCtrlReset:1; 851 u32 allowBootWithPinnedCache:1; 852 u32 disableSpinDownHS:1; 853 u32 enableJBOD:1; 854 u32 reserved:18; 855 #endif 856 } OnOffProperties; 857 u8 autoSnapVDSpace; 858 u8 viewSpace; 859 __le16 spinDownTime; 860 u8 reserved[24]; 861 } __packed; 862 863 /* 864 * SAS controller information 865 */ 866 struct megasas_ctrl_info { 867 868 /* 869 * PCI device information 870 */ 871 struct { 872 873 __le16 vendor_id; 874 __le16 device_id; 875 __le16 sub_vendor_id; 876 __le16 sub_device_id; 877 u8 reserved[24]; 878 879 } __attribute__ ((packed)) pci; 880 881 /* 882 * Host interface information 883 */ 884 struct { 885 886 u8 PCIX:1; 887 u8 PCIE:1; 888 u8 iSCSI:1; 889 u8 SAS_3G:1; 890 u8 SRIOV:1; 891 u8 reserved_0:3; 892 u8 reserved_1[6]; 893 u8 port_count; 894 u64 port_addr[8]; 895 896 } __attribute__ ((packed)) host_interface; 897 898 /* 899 * Device (backend) interface information 900 */ 901 struct { 902 903 u8 SPI:1; 904 u8 SAS_3G:1; 905 u8 SATA_1_5G:1; 906 u8 SATA_3G:1; 907 u8 reserved_0:4; 908 u8 reserved_1[6]; 909 u8 port_count; 910 u64 port_addr[8]; 911 912 } __attribute__ ((packed)) device_interface; 913 914 /* 915 * List of components residing in flash. All str are null terminated 916 */ 917 __le32 image_check_word; 918 __le32 image_component_count; 919 920 struct { 921 922 char name[8]; 923 char version[32]; 924 char build_date[16]; 925 char built_time[16]; 926 927 } __attribute__ ((packed)) image_component[8]; 928 929 /* 930 * List of flash components that have been flashed on the card, but 931 * are not in use, pending reset of the adapter. This list will be 932 * empty if a flash operation has not occurred. All stings are null 933 * terminated 934 */ 935 __le32 pending_image_component_count; 936 937 struct { 938 939 char name[8]; 940 char version[32]; 941 char build_date[16]; 942 char build_time[16]; 943 944 } __attribute__ ((packed)) pending_image_component[8]; 945 946 u8 max_arms; 947 u8 max_spans; 948 u8 max_arrays; 949 u8 max_lds; 950 951 char product_name[80]; 952 char serial_no[32]; 953 954 /* 955 * Other physical/controller/operation information. Indicates the 956 * presence of the hardware 957 */ 958 struct { 959 960 u32 bbu:1; 961 u32 alarm:1; 962 u32 nvram:1; 963 u32 uart:1; 964 u32 reserved:28; 965 966 } __attribute__ ((packed)) hw_present; 967 968 __le32 current_fw_time; 969 970 /* 971 * Maximum data transfer sizes 972 */ 973 __le16 max_concurrent_cmds; 974 __le16 max_sge_count; 975 __le32 max_request_size; 976 977 /* 978 * Logical and physical device counts 979 */ 980 __le16 ld_present_count; 981 __le16 ld_degraded_count; 982 __le16 ld_offline_count; 983 984 __le16 pd_present_count; 985 __le16 pd_disk_present_count; 986 __le16 pd_disk_pred_failure_count; 987 __le16 pd_disk_failed_count; 988 989 /* 990 * Memory size information 991 */ 992 __le16 nvram_size; 993 __le16 memory_size; 994 __le16 flash_size; 995 996 /* 997 * Error counters 998 */ 999 __le16 mem_correctable_error_count; 1000 __le16 mem_uncorrectable_error_count; 1001 1002 /* 1003 * Cluster information 1004 */ 1005 u8 cluster_permitted; 1006 u8 cluster_active; 1007 1008 /* 1009 * Additional max data transfer sizes 1010 */ 1011 __le16 max_strips_per_io; 1012 1013 /* 1014 * Controller capabilities structures 1015 */ 1016 struct { 1017 1018 u32 raid_level_0:1; 1019 u32 raid_level_1:1; 1020 u32 raid_level_5:1; 1021 u32 raid_level_1E:1; 1022 u32 raid_level_6:1; 1023 u32 reserved:27; 1024 1025 } __attribute__ ((packed)) raid_levels; 1026 1027 struct { 1028 1029 u32 rbld_rate:1; 1030 u32 cc_rate:1; 1031 u32 bgi_rate:1; 1032 u32 recon_rate:1; 1033 u32 patrol_rate:1; 1034 u32 alarm_control:1; 1035 u32 cluster_supported:1; 1036 u32 bbu:1; 1037 u32 spanning_allowed:1; 1038 u32 dedicated_hotspares:1; 1039 u32 revertible_hotspares:1; 1040 u32 foreign_config_import:1; 1041 u32 self_diagnostic:1; 1042 u32 mixed_redundancy_arr:1; 1043 u32 global_hot_spares:1; 1044 u32 reserved:17; 1045 1046 } __attribute__ ((packed)) adapter_operations; 1047 1048 struct { 1049 1050 u32 read_policy:1; 1051 u32 write_policy:1; 1052 u32 io_policy:1; 1053 u32 access_policy:1; 1054 u32 disk_cache_policy:1; 1055 u32 reserved:27; 1056 1057 } __attribute__ ((packed)) ld_operations; 1058 1059 struct { 1060 1061 u8 min; 1062 u8 max; 1063 u8 reserved[2]; 1064 1065 } __attribute__ ((packed)) stripe_sz_ops; 1066 1067 struct { 1068 1069 u32 force_online:1; 1070 u32 force_offline:1; 1071 u32 force_rebuild:1; 1072 u32 reserved:29; 1073 1074 } __attribute__ ((packed)) pd_operations; 1075 1076 struct { 1077 1078 u32 ctrl_supports_sas:1; 1079 u32 ctrl_supports_sata:1; 1080 u32 allow_mix_in_encl:1; 1081 u32 allow_mix_in_ld:1; 1082 u32 allow_sata_in_cluster:1; 1083 u32 reserved:27; 1084 1085 } __attribute__ ((packed)) pd_mix_support; 1086 1087 /* 1088 * Define ECC single-bit-error bucket information 1089 */ 1090 u8 ecc_bucket_count; 1091 u8 reserved_2[11]; 1092 1093 /* 1094 * Include the controller properties (changeable items) 1095 */ 1096 struct megasas_ctrl_prop properties; 1097 1098 /* 1099 * Define FW pkg version (set in envt v'bles on OEM basis) 1100 */ 1101 char package_version[0x60]; 1102 1103 1104 /* 1105 * If adapterOperations.supportMoreThan8Phys is set, 1106 * and deviceInterface.portCount is greater than 8, 1107 * SAS Addrs for first 8 ports shall be populated in 1108 * deviceInterface.portAddr, and the rest shall be 1109 * populated in deviceInterfacePortAddr2. 1110 */ 1111 __le64 deviceInterfacePortAddr2[8]; /*6a0h */ 1112 u8 reserved3[128]; /*6e0h */ 1113 1114 struct { /*760h */ 1115 u16 minPdRaidLevel_0:4; 1116 u16 maxPdRaidLevel_0:12; 1117 1118 u16 minPdRaidLevel_1:4; 1119 u16 maxPdRaidLevel_1:12; 1120 1121 u16 minPdRaidLevel_5:4; 1122 u16 maxPdRaidLevel_5:12; 1123 1124 u16 minPdRaidLevel_1E:4; 1125 u16 maxPdRaidLevel_1E:12; 1126 1127 u16 minPdRaidLevel_6:4; 1128 u16 maxPdRaidLevel_6:12; 1129 1130 u16 minPdRaidLevel_10:4; 1131 u16 maxPdRaidLevel_10:12; 1132 1133 u16 minPdRaidLevel_50:4; 1134 u16 maxPdRaidLevel_50:12; 1135 1136 u16 minPdRaidLevel_60:4; 1137 u16 maxPdRaidLevel_60:12; 1138 1139 u16 minPdRaidLevel_1E_RLQ0:4; 1140 u16 maxPdRaidLevel_1E_RLQ0:12; 1141 1142 u16 minPdRaidLevel_1E0_RLQ0:4; 1143 u16 maxPdRaidLevel_1E0_RLQ0:12; 1144 1145 u16 reserved[6]; 1146 } pdsForRaidLevels; 1147 1148 __le16 maxPds; /*780h */ 1149 __le16 maxDedHSPs; /*782h */ 1150 __le16 maxGlobalHSP; /*784h */ 1151 __le16 ddfSize; /*786h */ 1152 u8 maxLdsPerArray; /*788h */ 1153 u8 partitionsInDDF; /*789h */ 1154 u8 lockKeyBinding; /*78ah */ 1155 u8 maxPITsPerLd; /*78bh */ 1156 u8 maxViewsPerLd; /*78ch */ 1157 u8 maxTargetId; /*78dh */ 1158 __le16 maxBvlVdSize; /*78eh */ 1159 1160 __le16 maxConfigurableSSCSize; /*790h */ 1161 __le16 currentSSCsize; /*792h */ 1162 1163 char expanderFwVersion[12]; /*794h */ 1164 1165 __le16 PFKTrialTimeRemaining; /*7A0h */ 1166 1167 __le16 cacheMemorySize; /*7A2h */ 1168 1169 struct { /*7A4h */ 1170 #if defined(__BIG_ENDIAN_BITFIELD) 1171 u32 reserved:5; 1172 u32 activePassive:2; 1173 u32 supportConfigAutoBalance:1; 1174 u32 mpio:1; 1175 u32 supportDataLDonSSCArray:1; 1176 u32 supportPointInTimeProgress:1; 1177 u32 supportUnevenSpans:1; 1178 u32 dedicatedHotSparesLimited:1; 1179 u32 headlessMode:1; 1180 u32 supportEmulatedDrives:1; 1181 u32 supportResetNow:1; 1182 u32 realTimeScheduler:1; 1183 u32 supportSSDPatrolRead:1; 1184 u32 supportPerfTuning:1; 1185 u32 disableOnlinePFKChange:1; 1186 u32 supportJBOD:1; 1187 u32 supportBootTimePFKChange:1; 1188 u32 supportSetLinkSpeed:1; 1189 u32 supportEmergencySpares:1; 1190 u32 supportSuspendResumeBGops:1; 1191 u32 blockSSDWriteCacheChange:1; 1192 u32 supportShieldState:1; 1193 u32 supportLdBBMInfo:1; 1194 u32 supportLdPIType3:1; 1195 u32 supportLdPIType2:1; 1196 u32 supportLdPIType1:1; 1197 u32 supportPIcontroller:1; 1198 #else 1199 u32 supportPIcontroller:1; 1200 u32 supportLdPIType1:1; 1201 u32 supportLdPIType2:1; 1202 u32 supportLdPIType3:1; 1203 u32 supportLdBBMInfo:1; 1204 u32 supportShieldState:1; 1205 u32 blockSSDWriteCacheChange:1; 1206 u32 supportSuspendResumeBGops:1; 1207 u32 supportEmergencySpares:1; 1208 u32 supportSetLinkSpeed:1; 1209 u32 supportBootTimePFKChange:1; 1210 u32 supportJBOD:1; 1211 u32 disableOnlinePFKChange:1; 1212 u32 supportPerfTuning:1; 1213 u32 supportSSDPatrolRead:1; 1214 u32 realTimeScheduler:1; 1215 1216 u32 supportResetNow:1; 1217 u32 supportEmulatedDrives:1; 1218 u32 headlessMode:1; 1219 u32 dedicatedHotSparesLimited:1; 1220 1221 1222 u32 supportUnevenSpans:1; 1223 u32 supportPointInTimeProgress:1; 1224 u32 supportDataLDonSSCArray:1; 1225 u32 mpio:1; 1226 u32 supportConfigAutoBalance:1; 1227 u32 activePassive:2; 1228 u32 reserved:5; 1229 #endif 1230 } adapterOperations2; 1231 1232 u8 driverVersion[32]; /*7A8h */ 1233 u8 maxDAPdCountSpinup60; /*7C8h */ 1234 u8 temperatureROC; /*7C9h */ 1235 u8 temperatureCtrl; /*7CAh */ 1236 u8 reserved4; /*7CBh */ 1237 __le16 maxConfigurablePds; /*7CCh */ 1238 1239 1240 u8 reserved5[2]; /*0x7CDh */ 1241 1242 /* 1243 * HA cluster information 1244 */ 1245 struct { 1246 #if defined(__BIG_ENDIAN_BITFIELD) 1247 u32 reserved:25; 1248 u32 passive:1; 1249 u32 premiumFeatureMismatch:1; 1250 u32 ctrlPropIncompatible:1; 1251 u32 fwVersionMismatch:1; 1252 u32 hwIncompatible:1; 1253 u32 peerIsIncompatible:1; 1254 u32 peerIsPresent:1; 1255 #else 1256 u32 peerIsPresent:1; 1257 u32 peerIsIncompatible:1; 1258 u32 hwIncompatible:1; 1259 u32 fwVersionMismatch:1; 1260 u32 ctrlPropIncompatible:1; 1261 u32 premiumFeatureMismatch:1; 1262 u32 passive:1; 1263 u32 reserved:25; 1264 #endif 1265 } cluster; 1266 1267 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */ 1268 struct { 1269 u8 maxVFsSupported; /*0x7E4*/ 1270 u8 numVFsEnabled; /*0x7E5*/ 1271 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/ 1272 u8 reserved; /*0x7E7*/ 1273 } iov; 1274 1275 struct { 1276 #if defined(__BIG_ENDIAN_BITFIELD) 1277 u32 reserved:7; 1278 u32 useSeqNumJbodFP:1; 1279 u32 supportExtendedSSCSize:1; 1280 u32 supportDiskCacheSettingForSysPDs:1; 1281 u32 supportCPLDUpdate:1; 1282 u32 supportTTYLogCompression:1; 1283 u32 discardCacheDuringLDDelete:1; 1284 u32 supportSecurityonJBOD:1; 1285 u32 supportCacheBypassModes:1; 1286 u32 supportDisableSESMonitoring:1; 1287 u32 supportForceFlash:1; 1288 u32 supportNVDRAM:1; 1289 u32 supportDrvActivityLEDSetting:1; 1290 u32 supportAllowedOpsforDrvRemoval:1; 1291 u32 supportHOQRebuild:1; 1292 u32 supportForceTo512e:1; 1293 u32 supportNVCacheErase:1; 1294 u32 supportDebugQueue:1; 1295 u32 supportSwZone:1; 1296 u32 supportCrashDump:1; 1297 u32 supportMaxExtLDs:1; 1298 u32 supportT10RebuildAssist:1; 1299 u32 supportDisableImmediateIO:1; 1300 u32 supportThermalPollInterval:1; 1301 u32 supportPersonalityChange:2; 1302 #else 1303 u32 supportPersonalityChange:2; 1304 u32 supportThermalPollInterval:1; 1305 u32 supportDisableImmediateIO:1; 1306 u32 supportT10RebuildAssist:1; 1307 u32 supportMaxExtLDs:1; 1308 u32 supportCrashDump:1; 1309 u32 supportSwZone:1; 1310 u32 supportDebugQueue:1; 1311 u32 supportNVCacheErase:1; 1312 u32 supportForceTo512e:1; 1313 u32 supportHOQRebuild:1; 1314 u32 supportAllowedOpsforDrvRemoval:1; 1315 u32 supportDrvActivityLEDSetting:1; 1316 u32 supportNVDRAM:1; 1317 u32 supportForceFlash:1; 1318 u32 supportDisableSESMonitoring:1; 1319 u32 supportCacheBypassModes:1; 1320 u32 supportSecurityonJBOD:1; 1321 u32 discardCacheDuringLDDelete:1; 1322 u32 supportTTYLogCompression:1; 1323 u32 supportCPLDUpdate:1; 1324 u32 supportDiskCacheSettingForSysPDs:1; 1325 u32 supportExtendedSSCSize:1; 1326 u32 useSeqNumJbodFP:1; 1327 u32 reserved:7; 1328 #endif 1329 } adapterOperations3; 1330 1331 struct { 1332 #if defined(__BIG_ENDIAN_BITFIELD) 1333 u8 reserved:7; 1334 /* Indicates whether the CPLD image is part of 1335 * the package and stored in flash 1336 */ 1337 u8 cpld_in_flash:1; 1338 #else 1339 u8 cpld_in_flash:1; 1340 u8 reserved:7; 1341 #endif 1342 u8 reserved1[3]; 1343 /* Null terminated string. Has the version 1344 * information if cpld_in_flash = FALSE 1345 */ 1346 u8 userCodeDefinition[12]; 1347 } cpld; /* Valid only if upgradableCPLD is TRUE */ 1348 1349 struct { 1350 #if defined(__BIG_ENDIAN_BITFIELD) 1351 u16 reserved:8; 1352 u16 fw_swaps_bbu_vpd_info:1; 1353 u16 support_pd_map_target_id:1; 1354 u16 support_ses_ctrl_in_multipathcfg:1; 1355 u16 image_upload_supported:1; 1356 u16 support_encrypted_mfc:1; 1357 u16 supported_enc_algo:1; 1358 u16 support_ibutton_less:1; 1359 u16 ctrl_info_ext_supported:1; 1360 #else 1361 1362 u16 ctrl_info_ext_supported:1; 1363 u16 support_ibutton_less:1; 1364 u16 supported_enc_algo:1; 1365 u16 support_encrypted_mfc:1; 1366 u16 image_upload_supported:1; 1367 /* FW supports LUN based association and target port based */ 1368 u16 support_ses_ctrl_in_multipathcfg:1; 1369 /* association for the SES device connected in multipath mode */ 1370 /* FW defines Jbod target Id within MR_PD_CFG_SEQ */ 1371 u16 support_pd_map_target_id:1; 1372 /* FW swaps relevant fields in MR_BBU_VPD_INFO_FIXED to 1373 * provide the data in little endian order 1374 */ 1375 u16 fw_swaps_bbu_vpd_info:1; 1376 u16 reserved:8; 1377 #endif 1378 } adapter_operations4; 1379 u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */ 1380 } __packed; 1381 1382 /* 1383 * =============================== 1384 * MegaRAID SAS driver definitions 1385 * =============================== 1386 */ 1387 #define MEGASAS_MAX_PD_CHANNELS 2 1388 #define MEGASAS_MAX_LD_CHANNELS 2 1389 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 1390 MEGASAS_MAX_LD_CHANNELS) 1391 #define MEGASAS_MAX_DEV_PER_CHANNEL 128 1392 #define MEGASAS_DEFAULT_INIT_ID -1 1393 #define MEGASAS_MAX_LUN 8 1394 #define MEGASAS_DEFAULT_CMD_PER_LUN 256 1395 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 1396 MEGASAS_MAX_DEV_PER_CHANNEL) 1397 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 1398 MEGASAS_MAX_DEV_PER_CHANNEL) 1399 1400 #define MEGASAS_MAX_SECTORS (2*1024) 1401 #define MEGASAS_MAX_SECTORS_IEEE (2*128) 1402 #define MEGASAS_DBG_LVL 1 1403 1404 #define MEGASAS_FW_BUSY 1 1405 1406 /* Driver's internal Logging levels*/ 1407 #define OCR_LOGS (1 << 0) 1408 1409 #define SCAN_PD_CHANNEL 0x1 1410 #define SCAN_VD_CHANNEL 0x2 1411 1412 #define MEGASAS_KDUMP_QUEUE_DEPTH 100 1413 #define MR_LARGE_IO_MIN_SIZE (32 * 1024) 1414 #define MR_R1_LDIO_PIGGYBACK_DEFAULT 4 1415 1416 enum MR_SCSI_CMD_TYPE { 1417 READ_WRITE_LDIO = 0, 1418 NON_READ_WRITE_LDIO = 1, 1419 READ_WRITE_SYSPDIO = 2, 1420 NON_READ_WRITE_SYSPDIO = 3, 1421 }; 1422 1423 enum DCMD_TIMEOUT_ACTION { 1424 INITIATE_OCR = 0, 1425 KILL_ADAPTER = 1, 1426 IGNORE_TIMEOUT = 2, 1427 }; 1428 1429 enum FW_BOOT_CONTEXT { 1430 PROBE_CONTEXT = 0, 1431 OCR_CONTEXT = 1, 1432 }; 1433 1434 /* Frame Type */ 1435 #define IO_FRAME 0 1436 #define PTHRU_FRAME 1 1437 1438 /* 1439 * When SCSI mid-layer calls driver's reset routine, driver waits for 1440 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1441 * that the driver cannot _actually_ abort or reset pending commands. While 1442 * it is waiting for the commands to complete, it prints a diagnostic message 1443 * every MEGASAS_RESET_NOTICE_INTERVAL seconds 1444 */ 1445 #define MEGASAS_RESET_WAIT_TIME 180 1446 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 1447 #define MEGASAS_RESET_NOTICE_INTERVAL 5 1448 #define MEGASAS_IOCTL_CMD 0 1449 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 1450 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 1451 #define MEGASAS_BLOCKED_CMD_TIMEOUT 60 1452 /* 1453 * FW reports the maximum of number of commands that it can accept (maximum 1454 * commands that can be outstanding) at any time. The driver must report a 1455 * lower number to the mid layer because it can issue a few internal commands 1456 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1457 * is shown below 1458 */ 1459 #define MEGASAS_INT_CMDS 32 1460 #define MEGASAS_SKINNY_INT_CMDS 5 1461 #define MEGASAS_FUSION_INTERNAL_CMDS 8 1462 #define MEGASAS_FUSION_IOCTL_CMDS 3 1463 #define MEGASAS_MFI_IOCTL_CMDS 27 1464 1465 #define MEGASAS_MAX_MSIX_QUEUES 128 1466 /* 1467 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1468 * SGLs based on the size of dma_addr_t 1469 */ 1470 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 1471 1472 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 1473 1474 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1475 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1476 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 1477 1478 #define MFI_OB_INTR_STATUS_MASK 0x00000002 1479 #define MFI_POLL_TIMEOUT_SECS 60 1480 #define MFI_IO_TIMEOUT_SECS 180 1481 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ) 1482 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30) 1483 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300 1484 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1485 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1486 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 1487 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1488 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1489 1490 #define MFI_1068_PCSR_OFFSET 0x84 1491 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1492 #define MFI_1068_FW_READY 0xDDDD0000 1493 1494 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F 1495 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 1496 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1497 #define MR_MAX_MSIX_REG_ARRAY 16 1498 #define MR_RDPQ_MODE_OFFSET 0X00800000 1499 1500 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16 1501 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF 1502 #define MR_MIN_MAP_SIZE 0x10000 1503 /* 64k */ 1504 1505 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 1506 1507 /* 1508 * register set for both 1068 and 1078 controllers 1509 * structure extended for 1078 registers 1510 */ 1511 1512 struct megasas_register_set { 1513 u32 doorbell; /*0000h*/ 1514 u32 fusion_seq_offset; /*0004h*/ 1515 u32 fusion_host_diag; /*0008h*/ 1516 u32 reserved_01; /*000Ch*/ 1517 1518 u32 inbound_msg_0; /*0010h*/ 1519 u32 inbound_msg_1; /*0014h*/ 1520 u32 outbound_msg_0; /*0018h*/ 1521 u32 outbound_msg_1; /*001Ch*/ 1522 1523 u32 inbound_doorbell; /*0020h*/ 1524 u32 inbound_intr_status; /*0024h*/ 1525 u32 inbound_intr_mask; /*0028h*/ 1526 1527 u32 outbound_doorbell; /*002Ch*/ 1528 u32 outbound_intr_status; /*0030h*/ 1529 u32 outbound_intr_mask; /*0034h*/ 1530 1531 u32 reserved_1[2]; /*0038h*/ 1532 1533 u32 inbound_queue_port; /*0040h*/ 1534 u32 outbound_queue_port; /*0044h*/ 1535 1536 u32 reserved_2[9]; /*0048h*/ 1537 u32 reply_post_host_index; /*006Ch*/ 1538 u32 reserved_2_2[12]; /*0070h*/ 1539 1540 u32 outbound_doorbell_clear; /*00A0h*/ 1541 1542 u32 reserved_3[3]; /*00A4h*/ 1543 1544 u32 outbound_scratch_pad ; /*00B0h*/ 1545 u32 outbound_scratch_pad_2; /*00B4h*/ 1546 u32 outbound_scratch_pad_3; /*00B8h*/ 1547 u32 outbound_scratch_pad_4; /*00BCh*/ 1548 1549 1550 u32 inbound_low_queue_port ; /*00C0h*/ 1551 1552 u32 inbound_high_queue_port ; /*00C4h*/ 1553 1554 u32 inbound_single_queue_port; /*00C8h*/ 1555 u32 res_6[11]; /*CCh*/ 1556 u32 host_diag; 1557 u32 seq_offset; 1558 u32 index_registers[807]; /*00CCh*/ 1559 } __attribute__ ((packed)); 1560 1561 struct megasas_sge32 { 1562 1563 __le32 phys_addr; 1564 __le32 length; 1565 1566 } __attribute__ ((packed)); 1567 1568 struct megasas_sge64 { 1569 1570 __le64 phys_addr; 1571 __le32 length; 1572 1573 } __attribute__ ((packed)); 1574 1575 struct megasas_sge_skinny { 1576 __le64 phys_addr; 1577 __le32 length; 1578 __le32 flag; 1579 } __packed; 1580 1581 union megasas_sgl { 1582 1583 struct megasas_sge32 sge32[1]; 1584 struct megasas_sge64 sge64[1]; 1585 struct megasas_sge_skinny sge_skinny[1]; 1586 1587 } __attribute__ ((packed)); 1588 1589 struct megasas_header { 1590 1591 u8 cmd; /*00h */ 1592 u8 sense_len; /*01h */ 1593 u8 cmd_status; /*02h */ 1594 u8 scsi_status; /*03h */ 1595 1596 u8 target_id; /*04h */ 1597 u8 lun; /*05h */ 1598 u8 cdb_len; /*06h */ 1599 u8 sge_count; /*07h */ 1600 1601 __le32 context; /*08h */ 1602 __le32 pad_0; /*0Ch */ 1603 1604 __le16 flags; /*10h */ 1605 __le16 timeout; /*12h */ 1606 __le32 data_xferlen; /*14h */ 1607 1608 } __attribute__ ((packed)); 1609 1610 union megasas_sgl_frame { 1611 1612 struct megasas_sge32 sge32[8]; 1613 struct megasas_sge64 sge64[5]; 1614 1615 } __attribute__ ((packed)); 1616 1617 typedef union _MFI_CAPABILITIES { 1618 struct { 1619 #if defined(__BIG_ENDIAN_BITFIELD) 1620 u32 reserved:19; 1621 u32 support_pd_map_target_id:1; 1622 u32 support_qd_throttling:1; 1623 u32 support_fp_rlbypass:1; 1624 u32 support_vfid_in_ioframe:1; 1625 u32 support_ext_io_size:1; 1626 u32 support_ext_queue_depth:1; 1627 u32 security_protocol_cmds_fw:1; 1628 u32 support_core_affinity:1; 1629 u32 support_ndrive_r1_lb:1; 1630 u32 support_max_255lds:1; 1631 u32 support_fastpath_wb:1; 1632 u32 support_additional_msix:1; 1633 u32 support_fp_remote_lun:1; 1634 #else 1635 u32 support_fp_remote_lun:1; 1636 u32 support_additional_msix:1; 1637 u32 support_fastpath_wb:1; 1638 u32 support_max_255lds:1; 1639 u32 support_ndrive_r1_lb:1; 1640 u32 support_core_affinity:1; 1641 u32 security_protocol_cmds_fw:1; 1642 u32 support_ext_queue_depth:1; 1643 u32 support_ext_io_size:1; 1644 u32 support_vfid_in_ioframe:1; 1645 u32 support_fp_rlbypass:1; 1646 u32 support_qd_throttling:1; 1647 u32 support_pd_map_target_id:1; 1648 u32 reserved:19; 1649 #endif 1650 } mfi_capabilities; 1651 __le32 reg; 1652 } MFI_CAPABILITIES; 1653 1654 struct megasas_init_frame { 1655 1656 u8 cmd; /*00h */ 1657 u8 reserved_0; /*01h */ 1658 u8 cmd_status; /*02h */ 1659 1660 u8 reserved_1; /*03h */ 1661 MFI_CAPABILITIES driver_operations; /*04h*/ 1662 1663 __le32 context; /*08h */ 1664 __le32 pad_0; /*0Ch */ 1665 1666 __le16 flags; /*10h */ 1667 __le16 reserved_3; /*12h */ 1668 __le32 data_xfer_len; /*14h */ 1669 1670 __le32 queue_info_new_phys_addr_lo; /*18h */ 1671 __le32 queue_info_new_phys_addr_hi; /*1Ch */ 1672 __le32 queue_info_old_phys_addr_lo; /*20h */ 1673 __le32 queue_info_old_phys_addr_hi; /*24h */ 1674 __le32 reserved_4[2]; /*28h */ 1675 __le32 system_info_lo; /*30h */ 1676 __le32 system_info_hi; /*34h */ 1677 __le32 reserved_5[2]; /*38h */ 1678 1679 } __attribute__ ((packed)); 1680 1681 struct megasas_init_queue_info { 1682 1683 __le32 init_flags; /*00h */ 1684 __le32 reply_queue_entries; /*04h */ 1685 1686 __le32 reply_queue_start_phys_addr_lo; /*08h */ 1687 __le32 reply_queue_start_phys_addr_hi; /*0Ch */ 1688 __le32 producer_index_phys_addr_lo; /*10h */ 1689 __le32 producer_index_phys_addr_hi; /*14h */ 1690 __le32 consumer_index_phys_addr_lo; /*18h */ 1691 __le32 consumer_index_phys_addr_hi; /*1Ch */ 1692 1693 } __attribute__ ((packed)); 1694 1695 struct megasas_io_frame { 1696 1697 u8 cmd; /*00h */ 1698 u8 sense_len; /*01h */ 1699 u8 cmd_status; /*02h */ 1700 u8 scsi_status; /*03h */ 1701 1702 u8 target_id; /*04h */ 1703 u8 access_byte; /*05h */ 1704 u8 reserved_0; /*06h */ 1705 u8 sge_count; /*07h */ 1706 1707 __le32 context; /*08h */ 1708 __le32 pad_0; /*0Ch */ 1709 1710 __le16 flags; /*10h */ 1711 __le16 timeout; /*12h */ 1712 __le32 lba_count; /*14h */ 1713 1714 __le32 sense_buf_phys_addr_lo; /*18h */ 1715 __le32 sense_buf_phys_addr_hi; /*1Ch */ 1716 1717 __le32 start_lba_lo; /*20h */ 1718 __le32 start_lba_hi; /*24h */ 1719 1720 union megasas_sgl sgl; /*28h */ 1721 1722 } __attribute__ ((packed)); 1723 1724 struct megasas_pthru_frame { 1725 1726 u8 cmd; /*00h */ 1727 u8 sense_len; /*01h */ 1728 u8 cmd_status; /*02h */ 1729 u8 scsi_status; /*03h */ 1730 1731 u8 target_id; /*04h */ 1732 u8 lun; /*05h */ 1733 u8 cdb_len; /*06h */ 1734 u8 sge_count; /*07h */ 1735 1736 __le32 context; /*08h */ 1737 __le32 pad_0; /*0Ch */ 1738 1739 __le16 flags; /*10h */ 1740 __le16 timeout; /*12h */ 1741 __le32 data_xfer_len; /*14h */ 1742 1743 __le32 sense_buf_phys_addr_lo; /*18h */ 1744 __le32 sense_buf_phys_addr_hi; /*1Ch */ 1745 1746 u8 cdb[16]; /*20h */ 1747 union megasas_sgl sgl; /*30h */ 1748 1749 } __attribute__ ((packed)); 1750 1751 struct megasas_dcmd_frame { 1752 1753 u8 cmd; /*00h */ 1754 u8 reserved_0; /*01h */ 1755 u8 cmd_status; /*02h */ 1756 u8 reserved_1[4]; /*03h */ 1757 u8 sge_count; /*07h */ 1758 1759 __le32 context; /*08h */ 1760 __le32 pad_0; /*0Ch */ 1761 1762 __le16 flags; /*10h */ 1763 __le16 timeout; /*12h */ 1764 1765 __le32 data_xfer_len; /*14h */ 1766 __le32 opcode; /*18h */ 1767 1768 union { /*1Ch */ 1769 u8 b[12]; 1770 __le16 s[6]; 1771 __le32 w[3]; 1772 } mbox; 1773 1774 union megasas_sgl sgl; /*28h */ 1775 1776 } __attribute__ ((packed)); 1777 1778 struct megasas_abort_frame { 1779 1780 u8 cmd; /*00h */ 1781 u8 reserved_0; /*01h */ 1782 u8 cmd_status; /*02h */ 1783 1784 u8 reserved_1; /*03h */ 1785 __le32 reserved_2; /*04h */ 1786 1787 __le32 context; /*08h */ 1788 __le32 pad_0; /*0Ch */ 1789 1790 __le16 flags; /*10h */ 1791 __le16 reserved_3; /*12h */ 1792 __le32 reserved_4; /*14h */ 1793 1794 __le32 abort_context; /*18h */ 1795 __le32 pad_1; /*1Ch */ 1796 1797 __le32 abort_mfi_phys_addr_lo; /*20h */ 1798 __le32 abort_mfi_phys_addr_hi; /*24h */ 1799 1800 __le32 reserved_5[6]; /*28h */ 1801 1802 } __attribute__ ((packed)); 1803 1804 struct megasas_smp_frame { 1805 1806 u8 cmd; /*00h */ 1807 u8 reserved_1; /*01h */ 1808 u8 cmd_status; /*02h */ 1809 u8 connection_status; /*03h */ 1810 1811 u8 reserved_2[3]; /*04h */ 1812 u8 sge_count; /*07h */ 1813 1814 __le32 context; /*08h */ 1815 __le32 pad_0; /*0Ch */ 1816 1817 __le16 flags; /*10h */ 1818 __le16 timeout; /*12h */ 1819 1820 __le32 data_xfer_len; /*14h */ 1821 __le64 sas_addr; /*18h */ 1822 1823 union { 1824 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1825 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1826 } sgl; 1827 1828 } __attribute__ ((packed)); 1829 1830 struct megasas_stp_frame { 1831 1832 u8 cmd; /*00h */ 1833 u8 reserved_1; /*01h */ 1834 u8 cmd_status; /*02h */ 1835 u8 reserved_2; /*03h */ 1836 1837 u8 target_id; /*04h */ 1838 u8 reserved_3[2]; /*05h */ 1839 u8 sge_count; /*07h */ 1840 1841 __le32 context; /*08h */ 1842 __le32 pad_0; /*0Ch */ 1843 1844 __le16 flags; /*10h */ 1845 __le16 timeout; /*12h */ 1846 1847 __le32 data_xfer_len; /*14h */ 1848 1849 __le16 fis[10]; /*18h */ 1850 __le32 stp_flags; 1851 1852 union { 1853 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1854 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1855 } sgl; 1856 1857 } __attribute__ ((packed)); 1858 1859 union megasas_frame { 1860 1861 struct megasas_header hdr; 1862 struct megasas_init_frame init; 1863 struct megasas_io_frame io; 1864 struct megasas_pthru_frame pthru; 1865 struct megasas_dcmd_frame dcmd; 1866 struct megasas_abort_frame abort; 1867 struct megasas_smp_frame smp; 1868 struct megasas_stp_frame stp; 1869 1870 u8 raw_bytes[64]; 1871 }; 1872 1873 /** 1874 * struct MR_PRIV_DEVICE - sdev private hostdata 1875 * @is_tm_capable: firmware managed tm_capable flag 1876 * @tm_busy: TM request is in progress 1877 */ 1878 struct MR_PRIV_DEVICE { 1879 bool is_tm_capable; 1880 bool tm_busy; 1881 atomic_t r1_ldio_hint; 1882 u8 interface_type; 1883 }; 1884 struct megasas_cmd; 1885 1886 union megasas_evt_class_locale { 1887 1888 struct { 1889 #ifndef __BIG_ENDIAN_BITFIELD 1890 u16 locale; 1891 u8 reserved; 1892 s8 class; 1893 #else 1894 s8 class; 1895 u8 reserved; 1896 u16 locale; 1897 #endif 1898 } __attribute__ ((packed)) members; 1899 1900 u32 word; 1901 1902 } __attribute__ ((packed)); 1903 1904 struct megasas_evt_log_info { 1905 __le32 newest_seq_num; 1906 __le32 oldest_seq_num; 1907 __le32 clear_seq_num; 1908 __le32 shutdown_seq_num; 1909 __le32 boot_seq_num; 1910 1911 } __attribute__ ((packed)); 1912 1913 struct megasas_progress { 1914 1915 __le16 progress; 1916 __le16 elapsed_seconds; 1917 1918 } __attribute__ ((packed)); 1919 1920 struct megasas_evtarg_ld { 1921 1922 u16 target_id; 1923 u8 ld_index; 1924 u8 reserved; 1925 1926 } __attribute__ ((packed)); 1927 1928 struct megasas_evtarg_pd { 1929 u16 device_id; 1930 u8 encl_index; 1931 u8 slot_number; 1932 1933 } __attribute__ ((packed)); 1934 1935 struct megasas_evt_detail { 1936 1937 __le32 seq_num; 1938 __le32 time_stamp; 1939 __le32 code; 1940 union megasas_evt_class_locale cl; 1941 u8 arg_type; 1942 u8 reserved1[15]; 1943 1944 union { 1945 struct { 1946 struct megasas_evtarg_pd pd; 1947 u8 cdb_length; 1948 u8 sense_length; 1949 u8 reserved[2]; 1950 u8 cdb[16]; 1951 u8 sense[64]; 1952 } __attribute__ ((packed)) cdbSense; 1953 1954 struct megasas_evtarg_ld ld; 1955 1956 struct { 1957 struct megasas_evtarg_ld ld; 1958 __le64 count; 1959 } __attribute__ ((packed)) ld_count; 1960 1961 struct { 1962 __le64 lba; 1963 struct megasas_evtarg_ld ld; 1964 } __attribute__ ((packed)) ld_lba; 1965 1966 struct { 1967 struct megasas_evtarg_ld ld; 1968 __le32 prevOwner; 1969 __le32 newOwner; 1970 } __attribute__ ((packed)) ld_owner; 1971 1972 struct { 1973 u64 ld_lba; 1974 u64 pd_lba; 1975 struct megasas_evtarg_ld ld; 1976 struct megasas_evtarg_pd pd; 1977 } __attribute__ ((packed)) ld_lba_pd_lba; 1978 1979 struct { 1980 struct megasas_evtarg_ld ld; 1981 struct megasas_progress prog; 1982 } __attribute__ ((packed)) ld_prog; 1983 1984 struct { 1985 struct megasas_evtarg_ld ld; 1986 u32 prev_state; 1987 u32 new_state; 1988 } __attribute__ ((packed)) ld_state; 1989 1990 struct { 1991 u64 strip; 1992 struct megasas_evtarg_ld ld; 1993 } __attribute__ ((packed)) ld_strip; 1994 1995 struct megasas_evtarg_pd pd; 1996 1997 struct { 1998 struct megasas_evtarg_pd pd; 1999 u32 err; 2000 } __attribute__ ((packed)) pd_err; 2001 2002 struct { 2003 u64 lba; 2004 struct megasas_evtarg_pd pd; 2005 } __attribute__ ((packed)) pd_lba; 2006 2007 struct { 2008 u64 lba; 2009 struct megasas_evtarg_pd pd; 2010 struct megasas_evtarg_ld ld; 2011 } __attribute__ ((packed)) pd_lba_ld; 2012 2013 struct { 2014 struct megasas_evtarg_pd pd; 2015 struct megasas_progress prog; 2016 } __attribute__ ((packed)) pd_prog; 2017 2018 struct { 2019 struct megasas_evtarg_pd pd; 2020 u32 prevState; 2021 u32 newState; 2022 } __attribute__ ((packed)) pd_state; 2023 2024 struct { 2025 u16 vendorId; 2026 __le16 deviceId; 2027 u16 subVendorId; 2028 u16 subDeviceId; 2029 } __attribute__ ((packed)) pci; 2030 2031 u32 rate; 2032 char str[96]; 2033 2034 struct { 2035 u32 rtc; 2036 u32 elapsedSeconds; 2037 } __attribute__ ((packed)) time; 2038 2039 struct { 2040 u32 ecar; 2041 u32 elog; 2042 char str[64]; 2043 } __attribute__ ((packed)) ecc; 2044 2045 u8 b[96]; 2046 __le16 s[48]; 2047 __le32 w[24]; 2048 __le64 d[12]; 2049 } args; 2050 2051 char description[128]; 2052 2053 } __attribute__ ((packed)); 2054 2055 struct megasas_aen_event { 2056 struct delayed_work hotplug_work; 2057 struct megasas_instance *instance; 2058 }; 2059 2060 struct megasas_irq_context { 2061 struct megasas_instance *instance; 2062 u32 MSIxIndex; 2063 }; 2064 2065 struct MR_DRV_SYSTEM_INFO { 2066 u8 infoVersion; 2067 u8 systemIdLength; 2068 u16 reserved0; 2069 u8 systemId[64]; 2070 u8 reserved[1980]; 2071 }; 2072 2073 enum MR_PD_TYPE { 2074 UNKNOWN_DRIVE = 0, 2075 PARALLEL_SCSI = 1, 2076 SAS_PD = 2, 2077 SATA_PD = 3, 2078 FC_PD = 4, 2079 NVME_PD = 5, 2080 }; 2081 2082 /* JBOD Queue depth definitions */ 2083 #define MEGASAS_SATA_QD 32 2084 #define MEGASAS_SAS_QD 64 2085 #define MEGASAS_DEFAULT_PD_QD 64 2086 #define MEGASAS_NVME_QD 32 2087 2088 #define MR_DEFAULT_NVME_PAGE_SIZE 4096 2089 #define MR_DEFAULT_NVME_PAGE_SHIFT 12 2090 #define MR_DEFAULT_NVME_MDTS_KB 128 2091 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF 2092 2093 struct megasas_instance { 2094 2095 __le32 *producer; 2096 dma_addr_t producer_h; 2097 __le32 *consumer; 2098 dma_addr_t consumer_h; 2099 struct MR_DRV_SYSTEM_INFO *system_info_buf; 2100 dma_addr_t system_info_h; 2101 struct MR_LD_VF_AFFILIATION *vf_affiliation; 2102 dma_addr_t vf_affiliation_h; 2103 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111; 2104 dma_addr_t vf_affiliation_111_h; 2105 struct MR_CTRL_HB_HOST_MEM *hb_host_mem; 2106 dma_addr_t hb_host_mem_h; 2107 struct MR_PD_INFO *pd_info; 2108 dma_addr_t pd_info_h; 2109 struct MR_TARGET_PROPERTIES *tgt_prop; 2110 dma_addr_t tgt_prop_h; 2111 2112 __le32 *reply_queue; 2113 dma_addr_t reply_queue_h; 2114 2115 u32 *crash_dump_buf; 2116 dma_addr_t crash_dump_h; 2117 void *crash_buf[MAX_CRASH_DUMP_SIZE]; 2118 u32 crash_buf_pages; 2119 unsigned int fw_crash_buffer_size; 2120 unsigned int fw_crash_state; 2121 unsigned int fw_crash_buffer_offset; 2122 u32 drv_buf_index; 2123 u32 drv_buf_alloc; 2124 u32 crash_dump_fw_support; 2125 u32 crash_dump_drv_support; 2126 u32 crash_dump_app_support; 2127 u32 secure_jbod_support; 2128 u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */ 2129 bool use_seqnum_jbod_fp; /* Added for PD sequence */ 2130 spinlock_t crashdump_lock; 2131 2132 struct megasas_register_set __iomem *reg_set; 2133 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; 2134 struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 2135 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; 2136 u8 ld_ids[MEGASAS_MAX_LD_IDS]; 2137 s8 init_id; 2138 2139 u16 max_num_sge; 2140 u16 max_fw_cmds; 2141 u16 max_mpt_cmds; 2142 u16 max_mfi_cmds; 2143 u16 max_scsi_cmds; 2144 u16 ldio_threshold; 2145 u16 cur_can_queue; 2146 u32 max_sectors_per_req; 2147 struct megasas_aen_event *ev; 2148 2149 struct megasas_cmd **cmd_list; 2150 struct list_head cmd_pool; 2151 /* used to sync fire the cmd to fw */ 2152 spinlock_t mfi_pool_lock; 2153 /* used to sync fire the cmd to fw */ 2154 spinlock_t hba_lock; 2155 /* used to synch producer, consumer ptrs in dpc */ 2156 spinlock_t stream_lock; 2157 spinlock_t completion_lock; 2158 struct dma_pool *frame_dma_pool; 2159 struct dma_pool *sense_dma_pool; 2160 2161 struct megasas_evt_detail *evt_detail; 2162 dma_addr_t evt_detail_h; 2163 struct megasas_cmd *aen_cmd; 2164 struct mutex hba_mutex; 2165 struct semaphore ioctl_sem; 2166 2167 struct Scsi_Host *host; 2168 2169 wait_queue_head_t int_cmd_wait_q; 2170 wait_queue_head_t abort_cmd_wait_q; 2171 2172 struct pci_dev *pdev; 2173 u32 unique_id; 2174 u32 fw_support_ieee; 2175 2176 atomic_t fw_outstanding; 2177 atomic_t ldio_outstanding; 2178 atomic_t fw_reset_no_pci_access; 2179 atomic_t ieee_sgl; 2180 atomic_t prp_sgl; 2181 atomic_t sge_holes_type1; 2182 atomic_t sge_holes_type2; 2183 atomic_t sge_holes_type3; 2184 2185 struct megasas_instance_template *instancet; 2186 struct tasklet_struct isr_tasklet; 2187 struct work_struct work_init; 2188 struct work_struct crash_init; 2189 2190 u8 flag; 2191 u8 unload; 2192 u8 flag_ieee; 2193 u8 issuepend_done; 2194 u8 disableOnlineCtrlReset; 2195 u8 UnevenSpanSupport; 2196 2197 u8 supportmax256vd; 2198 u8 pd_list_not_supported; 2199 u16 fw_supported_vd_count; 2200 u16 fw_supported_pd_count; 2201 2202 u16 drv_supported_vd_count; 2203 u16 drv_supported_pd_count; 2204 2205 atomic_t adprecovery; 2206 unsigned long last_time; 2207 u32 mfiStatus; 2208 u32 last_seq_num; 2209 2210 struct list_head internal_reset_pending_q; 2211 2212 /* Ptr to hba specific information */ 2213 void *ctrl_context; 2214 u32 ctrl_context_pages; 2215 struct megasas_ctrl_info *ctrl_info; 2216 unsigned int msix_vectors; 2217 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 2218 u64 map_id; 2219 u64 pd_seq_map_id; 2220 struct megasas_cmd *map_update_cmd; 2221 struct megasas_cmd *jbod_seq_cmd; 2222 unsigned long bar; 2223 long reset_flags; 2224 struct mutex reset_mutex; 2225 struct timer_list sriov_heartbeat_timer; 2226 char skip_heartbeat_timer_del; 2227 u8 requestorId; 2228 char PlasmaFW111; 2229 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; 2230 u8 peerIsPresent; 2231 u8 passive; 2232 u16 throttlequeuedepth; 2233 u8 mask_interrupts; 2234 u16 max_chain_frame_sz; 2235 u8 is_imr; 2236 u8 is_rdpq; 2237 bool dev_handle; 2238 bool fw_sync_cache_support; 2239 u32 mfi_frame_size; 2240 bool is_ventura; 2241 bool msix_combined; 2242 u16 max_raid_mapsize; 2243 /* preffered count to send as LDIO irrspective of FP capable.*/ 2244 u8 r1_ldio_hint_default; 2245 u32 nvme_page_size; 2246 }; 2247 struct MR_LD_VF_MAP { 2248 u32 size; 2249 union MR_LD_REF ref; 2250 u8 ldVfCount; 2251 u8 reserved[6]; 2252 u8 policy[1]; 2253 }; 2254 2255 struct MR_LD_VF_AFFILIATION { 2256 u32 size; 2257 u8 ldCount; 2258 u8 vfCount; 2259 u8 thisVf; 2260 u8 reserved[9]; 2261 struct MR_LD_VF_MAP map[1]; 2262 }; 2263 2264 /* Plasma 1.11 FW backward compatibility structures */ 2265 #define IOV_111_OFFSET 0x7CE 2266 #define MAX_VIRTUAL_FUNCTIONS 8 2267 #define MR_LD_ACCESS_HIDDEN 15 2268 2269 struct IOV_111 { 2270 u8 maxVFsSupported; 2271 u8 numVFsEnabled; 2272 u8 requestorId; 2273 u8 reserved[5]; 2274 }; 2275 2276 struct MR_LD_VF_MAP_111 { 2277 u8 targetId; 2278 u8 reserved[3]; 2279 u8 policy[MAX_VIRTUAL_FUNCTIONS]; 2280 }; 2281 2282 struct MR_LD_VF_AFFILIATION_111 { 2283 u8 vdCount; 2284 u8 vfCount; 2285 u8 thisVf; 2286 u8 reserved[5]; 2287 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES]; 2288 }; 2289 2290 struct MR_CTRL_HB_HOST_MEM { 2291 struct { 2292 u32 fwCounter; /* Firmware heart beat counter */ 2293 struct { 2294 u32 debugmode:1; /* 1=Firmware is in debug mode. 2295 Heart beat will not be updated. */ 2296 u32 reserved:31; 2297 } debug; 2298 u32 reserved_fw[6]; 2299 u32 driverCounter; /* Driver heart beat counter. 0x20 */ 2300 u32 reserved_driver[7]; 2301 } HB; 2302 u8 pad[0x400-0x40]; 2303 }; 2304 2305 enum { 2306 MEGASAS_HBA_OPERATIONAL = 0, 2307 MEGASAS_ADPRESET_SM_INFAULT = 1, 2308 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 2309 MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 2310 MEGASAS_HW_CRITICAL_ERROR = 4, 2311 MEGASAS_ADPRESET_SM_POLLING = 5, 2312 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 2313 }; 2314 2315 struct megasas_instance_template { 2316 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 2317 u32, struct megasas_register_set __iomem *); 2318 2319 void (*enable_intr)(struct megasas_instance *); 2320 void (*disable_intr)(struct megasas_instance *); 2321 2322 int (*clear_intr)(struct megasas_register_set __iomem *); 2323 2324 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 2325 int (*adp_reset)(struct megasas_instance *, \ 2326 struct megasas_register_set __iomem *); 2327 int (*check_reset)(struct megasas_instance *, \ 2328 struct megasas_register_set __iomem *); 2329 irqreturn_t (*service_isr)(int irq, void *devp); 2330 void (*tasklet)(unsigned long); 2331 u32 (*init_adapter)(struct megasas_instance *); 2332 u32 (*build_and_issue_cmd) (struct megasas_instance *, 2333 struct scsi_cmnd *); 2334 void (*issue_dcmd)(struct megasas_instance *instance, 2335 struct megasas_cmd *cmd); 2336 }; 2337 2338 #define MEGASAS_IS_LOGICAL(sdev) \ 2339 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1) 2340 2341 #define MEGASAS_DEV_INDEX(scp) \ 2342 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 2343 scp->device->id) 2344 2345 #define MEGASAS_PD_INDEX(scp) \ 2346 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 2347 scp->device->id) 2348 2349 struct megasas_cmd { 2350 2351 union megasas_frame *frame; 2352 dma_addr_t frame_phys_addr; 2353 u8 *sense; 2354 dma_addr_t sense_phys_addr; 2355 2356 u32 index; 2357 u8 sync_cmd; 2358 u8 cmd_status_drv; 2359 u8 abort_aen; 2360 u8 retry_for_fw_reset; 2361 2362 2363 struct list_head list; 2364 struct scsi_cmnd *scmd; 2365 u8 flags; 2366 2367 struct megasas_instance *instance; 2368 union { 2369 struct { 2370 u16 smid; 2371 u16 resvd; 2372 } context; 2373 u32 frame_count; 2374 }; 2375 }; 2376 2377 #define MAX_MGMT_ADAPTERS 1024 2378 #define MAX_IOCTL_SGE 16 2379 2380 struct megasas_iocpacket { 2381 2382 u16 host_no; 2383 u16 __pad1; 2384 u32 sgl_off; 2385 u32 sge_count; 2386 u32 sense_off; 2387 u32 sense_len; 2388 union { 2389 u8 raw[128]; 2390 struct megasas_header hdr; 2391 } frame; 2392 2393 struct iovec sgl[MAX_IOCTL_SGE]; 2394 2395 } __attribute__ ((packed)); 2396 2397 struct megasas_aen { 2398 u16 host_no; 2399 u16 __pad1; 2400 u32 seq_num; 2401 u32 class_locale_word; 2402 } __attribute__ ((packed)); 2403 2404 #ifdef CONFIG_COMPAT 2405 struct compat_megasas_iocpacket { 2406 u16 host_no; 2407 u16 __pad1; 2408 u32 sgl_off; 2409 u32 sge_count; 2410 u32 sense_off; 2411 u32 sense_len; 2412 union { 2413 u8 raw[128]; 2414 struct megasas_header hdr; 2415 } frame; 2416 struct compat_iovec sgl[MAX_IOCTL_SGE]; 2417 } __attribute__ ((packed)); 2418 2419 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 2420 #endif 2421 2422 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 2423 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 2424 2425 struct megasas_mgmt_info { 2426 2427 u16 count; 2428 struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 2429 int max_index; 2430 }; 2431 2432 enum MEGASAS_OCR_CAUSE { 2433 FW_FAULT_OCR = 0, 2434 SCSIIO_TIMEOUT_OCR = 1, 2435 MFI_IO_TIMEOUT_OCR = 2, 2436 }; 2437 2438 enum DCMD_RETURN_STATUS { 2439 DCMD_SUCCESS = 0, 2440 DCMD_TIMEOUT = 1, 2441 DCMD_FAILED = 2, 2442 DCMD_NOT_FIRED = 3, 2443 }; 2444 2445 u8 2446 MR_BuildRaidContext(struct megasas_instance *instance, 2447 struct IO_REQUEST_INFO *io_info, 2448 struct RAID_CONTEXT *pRAID_Context, 2449 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN); 2450 u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map); 2451 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 2452 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map); 2453 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map); 2454 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map); 2455 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 2456 2457 __le16 get_updated_dev_handle(struct megasas_instance *instance, 2458 struct LD_LOAD_BALANCE_INFO *lbInfo, 2459 struct IO_REQUEST_INFO *in_info, 2460 struct MR_DRV_RAID_MAP_ALL *drv_map); 2461 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map, 2462 struct LD_LOAD_BALANCE_INFO *lbInfo); 2463 int megasas_get_ctrl_info(struct megasas_instance *instance); 2464 /* PD sequence */ 2465 int 2466 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend); 2467 void megasas_set_dynamic_target_properties(struct scsi_device *sdev); 2468 int megasas_set_crash_dump_params(struct megasas_instance *instance, 2469 u8 crash_buf_state); 2470 void megasas_free_host_crash_buffer(struct megasas_instance *instance); 2471 void megasas_fusion_crash_dump_wq(struct work_struct *work); 2472 2473 void megasas_return_cmd_fusion(struct megasas_instance *instance, 2474 struct megasas_cmd_fusion *cmd); 2475 int megasas_issue_blocked_cmd(struct megasas_instance *instance, 2476 struct megasas_cmd *cmd, int timeout); 2477 void __megasas_return_cmd(struct megasas_instance *instance, 2478 struct megasas_cmd *cmd); 2479 2480 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance, 2481 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion); 2482 int megasas_cmd_type(struct scsi_cmnd *cmd); 2483 void megasas_setup_jbod_map(struct megasas_instance *instance); 2484 2485 void megasas_update_sdev_properties(struct scsi_device *sdev); 2486 int megasas_reset_fusion(struct Scsi_Host *shost, int reason); 2487 int megasas_task_abort_fusion(struct scsi_cmnd *scmd); 2488 int megasas_reset_target_fusion(struct scsi_cmnd *scmd); 2489 u32 mega_mod64(u64 dividend, u32 divisor); 2490 int megasas_alloc_fusion_context(struct megasas_instance *instance); 2491 void megasas_free_fusion_context(struct megasas_instance *instance); 2492 #endif /*LSI_MEGARAID_SAS_H */ 2493