1 /* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2003-2013 LSI Corporation 5 * Copyright (c) 2013-2014 Avago Technologies 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 2 10 * of the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 * 20 * FILE: megaraid_sas.h 21 * 22 * Authors: Avago Technologies 23 * Kashyap Desai <kashyap.desai@avagotech.com> 24 * Sumit Saxena <sumit.saxena@avagotech.com> 25 * 26 * Send feedback to: megaraidlinux.pdl@avagotech.com 27 * 28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90, 29 * San Jose, California 95131 30 */ 31 32 #ifndef LSI_MEGARAID_SAS_H 33 #define LSI_MEGARAID_SAS_H 34 35 /* 36 * MegaRAID SAS Driver meta data 37 */ 38 #define MEGASAS_VERSION "06.810.09.00-rc1" 39 #define MEGASAS_RELDATE "Jan. 28, 2016" 40 41 /* 42 * Device IDs 43 */ 44 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060 45 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C 46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413 47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078 48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079 49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073 50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071 51 #define PCI_DEVICE_ID_LSI_FUSION 0x005b 52 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f 53 #define PCI_DEVICE_ID_LSI_INVADER 0x005d 54 #define PCI_DEVICE_ID_LSI_FURY 0x005f 55 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce 56 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf 57 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052 58 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053 59 60 /* 61 * Intel HBA SSDIDs 62 */ 63 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360 64 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362 65 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380 66 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381 67 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341 68 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343 69 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B 70 71 /* 72 * Intruder HBA SSDIDs 73 */ 74 #define MEGARAID_INTRUDER_SSDID1 0x9371 75 #define MEGARAID_INTRUDER_SSDID2 0x9390 76 #define MEGARAID_INTRUDER_SSDID3 0x9370 77 78 /* 79 * Intel HBA branding 80 */ 81 #define MEGARAID_INTEL_RS3DC080_BRANDING \ 82 "Intel(R) RAID Controller RS3DC080" 83 #define MEGARAID_INTEL_RS3DC040_BRANDING \ 84 "Intel(R) RAID Controller RS3DC040" 85 #define MEGARAID_INTEL_RS3SC008_BRANDING \ 86 "Intel(R) RAID Controller RS3SC008" 87 #define MEGARAID_INTEL_RS3MC044_BRANDING \ 88 "Intel(R) RAID Controller RS3MC044" 89 #define MEGARAID_INTEL_RS3WC080_BRANDING \ 90 "Intel(R) RAID Controller RS3WC080" 91 #define MEGARAID_INTEL_RS3WC040_BRANDING \ 92 "Intel(R) RAID Controller RS3WC040" 93 #define MEGARAID_INTEL_RMS3BC160_BRANDING \ 94 "Intel(R) Integrated RAID Module RMS3BC160" 95 96 /* 97 * ===================================== 98 * MegaRAID SAS MFI firmware definitions 99 * ===================================== 100 */ 101 102 /* 103 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 104 * protocol between the software and firmware. Commands are issued using 105 * "message frames" 106 */ 107 108 /* 109 * FW posts its state in upper 4 bits of outbound_msg_0 register 110 */ 111 #define MFI_STATE_MASK 0xF0000000 112 #define MFI_STATE_UNDEFINED 0x00000000 113 #define MFI_STATE_BB_INIT 0x10000000 114 #define MFI_STATE_FW_INIT 0x40000000 115 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 116 #define MFI_STATE_FW_INIT_2 0x70000000 117 #define MFI_STATE_DEVICE_SCAN 0x80000000 118 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 119 #define MFI_STATE_FLUSH_CACHE 0xA0000000 120 #define MFI_STATE_READY 0xB0000000 121 #define MFI_STATE_OPERATIONAL 0xC0000000 122 #define MFI_STATE_FAULT 0xF0000000 123 #define MFI_STATE_FORCE_OCR 0x00000080 124 #define MFI_STATE_DMADONE 0x00000008 125 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004 126 #define MFI_RESET_REQUIRED 0x00000001 127 #define MFI_RESET_ADAPTER 0x00000002 128 #define MEGAMFI_FRAME_SIZE 64 129 130 /* 131 * During FW init, clear pending cmds & reset state using inbound_msg_0 132 * 133 * ABORT : Abort all pending cmds 134 * READY : Move from OPERATIONAL to READY state; discard queue info 135 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 136 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 137 * HOTPLUG : Resume from Hotplug 138 * MFI_STOP_ADP : Send signal to FW to stop processing 139 */ 140 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */ 141 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */ 142 #define DIAG_WRITE_ENABLE (0x00000080) 143 #define DIAG_RESET_ADAPTER (0x00000004) 144 145 #define MFI_ADP_RESET 0x00000040 146 #define MFI_INIT_ABORT 0x00000001 147 #define MFI_INIT_READY 0x00000002 148 #define MFI_INIT_MFIMODE 0x00000004 149 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 150 #define MFI_INIT_HOTPLUG 0x00000010 151 #define MFI_STOP_ADP 0x00000020 152 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 153 MFI_INIT_MFIMODE| \ 154 MFI_INIT_ABORT 155 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) 156 157 /* 158 * MFI frame flags 159 */ 160 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 161 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 162 #define MFI_FRAME_SGL32 0x0000 163 #define MFI_FRAME_SGL64 0x0002 164 #define MFI_FRAME_SENSE32 0x0000 165 #define MFI_FRAME_SENSE64 0x0004 166 #define MFI_FRAME_DIR_NONE 0x0000 167 #define MFI_FRAME_DIR_WRITE 0x0008 168 #define MFI_FRAME_DIR_READ 0x0010 169 #define MFI_FRAME_DIR_BOTH 0x0018 170 #define MFI_FRAME_IEEE 0x0020 171 172 /* Driver internal */ 173 #define DRV_DCMD_POLLED_MODE 0x1 174 #define DRV_DCMD_SKIP_REFIRE 0x2 175 176 /* 177 * Definition for cmd_status 178 */ 179 #define MFI_CMD_STATUS_POLL_MODE 0xFF 180 181 /* 182 * MFI command opcodes 183 */ 184 #define MFI_CMD_INIT 0x00 185 #define MFI_CMD_LD_READ 0x01 186 #define MFI_CMD_LD_WRITE 0x02 187 #define MFI_CMD_LD_SCSI_IO 0x03 188 #define MFI_CMD_PD_SCSI_IO 0x04 189 #define MFI_CMD_DCMD 0x05 190 #define MFI_CMD_ABORT 0x06 191 #define MFI_CMD_SMP 0x07 192 #define MFI_CMD_STP 0x08 193 #define MFI_CMD_INVALID 0xff 194 195 #define MR_DCMD_CTRL_GET_INFO 0x01010000 196 #define MR_DCMD_LD_GET_LIST 0x03010000 197 #define MR_DCMD_LD_LIST_QUERY 0x03010100 198 199 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 200 #define MR_FLUSH_CTRL_CACHE 0x01 201 #define MR_FLUSH_DISK_CACHE 0x02 202 203 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 204 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 205 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 206 207 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 208 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 209 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 210 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 211 212 #define MR_DCMD_CLUSTER 0x08000000 213 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 214 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 215 #define MR_DCMD_PD_LIST_QUERY 0x02010100 216 217 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100 218 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600) 219 #define MR_DCMD_PD_GET_INFO 0x02020000 220 221 /* 222 * Global functions 223 */ 224 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance); 225 226 227 /* 228 * MFI command completion codes 229 */ 230 enum MFI_STAT { 231 MFI_STAT_OK = 0x00, 232 MFI_STAT_INVALID_CMD = 0x01, 233 MFI_STAT_INVALID_DCMD = 0x02, 234 MFI_STAT_INVALID_PARAMETER = 0x03, 235 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 236 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 237 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 238 MFI_STAT_APP_IN_USE = 0x07, 239 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 240 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 241 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 242 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 243 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 244 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 245 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 246 MFI_STAT_FLASH_BUSY = 0x0f, 247 MFI_STAT_FLASH_ERROR = 0x10, 248 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 249 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 250 MFI_STAT_FLASH_NOT_OPEN = 0x13, 251 MFI_STAT_FLASH_NOT_STARTED = 0x14, 252 MFI_STAT_FLUSH_FAILED = 0x15, 253 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 254 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 255 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 256 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 257 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 258 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 259 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 260 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 261 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 262 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 263 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 264 MFI_STAT_MFC_HW_ERROR = 0x21, 265 MFI_STAT_NO_HW_PRESENT = 0x22, 266 MFI_STAT_NOT_FOUND = 0x23, 267 MFI_STAT_NOT_IN_ENCL = 0x24, 268 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 269 MFI_STAT_PD_TYPE_WRONG = 0x26, 270 MFI_STAT_PR_DISABLED = 0x27, 271 MFI_STAT_ROW_INDEX_INVALID = 0x28, 272 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 273 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 274 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 275 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 276 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 277 MFI_STAT_SCSI_IO_FAILED = 0x2e, 278 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 279 MFI_STAT_SHUTDOWN_FAILED = 0x30, 280 MFI_STAT_TIME_NOT_SET = 0x31, 281 MFI_STAT_WRONG_STATE = 0x32, 282 MFI_STAT_LD_OFFLINE = 0x33, 283 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 284 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 285 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 286 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 287 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 288 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 289 290 MFI_STAT_INVALID_STATUS = 0xFF 291 }; 292 293 enum mfi_evt_class { 294 MFI_EVT_CLASS_DEBUG = -2, 295 MFI_EVT_CLASS_PROGRESS = -1, 296 MFI_EVT_CLASS_INFO = 0, 297 MFI_EVT_CLASS_WARNING = 1, 298 MFI_EVT_CLASS_CRITICAL = 2, 299 MFI_EVT_CLASS_FATAL = 3, 300 MFI_EVT_CLASS_DEAD = 4 301 }; 302 303 /* 304 * Crash dump related defines 305 */ 306 #define MAX_CRASH_DUMP_SIZE 512 307 #define CRASH_DMA_BUF_SIZE (1024 * 1024) 308 309 enum MR_FW_CRASH_DUMP_STATE { 310 UNAVAILABLE = 0, 311 AVAILABLE = 1, 312 COPYING = 2, 313 COPIED = 3, 314 COPY_ERROR = 4, 315 }; 316 317 enum _MR_CRASH_BUF_STATUS { 318 MR_CRASH_BUF_TURN_OFF = 0, 319 MR_CRASH_BUF_TURN_ON = 1, 320 }; 321 322 /* 323 * Number of mailbox bytes in DCMD message frame 324 */ 325 #define MFI_MBOX_SIZE 12 326 327 enum MR_EVT_CLASS { 328 329 MR_EVT_CLASS_DEBUG = -2, 330 MR_EVT_CLASS_PROGRESS = -1, 331 MR_EVT_CLASS_INFO = 0, 332 MR_EVT_CLASS_WARNING = 1, 333 MR_EVT_CLASS_CRITICAL = 2, 334 MR_EVT_CLASS_FATAL = 3, 335 MR_EVT_CLASS_DEAD = 4, 336 337 }; 338 339 enum MR_EVT_LOCALE { 340 341 MR_EVT_LOCALE_LD = 0x0001, 342 MR_EVT_LOCALE_PD = 0x0002, 343 MR_EVT_LOCALE_ENCL = 0x0004, 344 MR_EVT_LOCALE_BBU = 0x0008, 345 MR_EVT_LOCALE_SAS = 0x0010, 346 MR_EVT_LOCALE_CTRL = 0x0020, 347 MR_EVT_LOCALE_CONFIG = 0x0040, 348 MR_EVT_LOCALE_CLUSTER = 0x0080, 349 MR_EVT_LOCALE_ALL = 0xffff, 350 351 }; 352 353 enum MR_EVT_ARGS { 354 355 MR_EVT_ARGS_NONE, 356 MR_EVT_ARGS_CDB_SENSE, 357 MR_EVT_ARGS_LD, 358 MR_EVT_ARGS_LD_COUNT, 359 MR_EVT_ARGS_LD_LBA, 360 MR_EVT_ARGS_LD_OWNER, 361 MR_EVT_ARGS_LD_LBA_PD_LBA, 362 MR_EVT_ARGS_LD_PROG, 363 MR_EVT_ARGS_LD_STATE, 364 MR_EVT_ARGS_LD_STRIP, 365 MR_EVT_ARGS_PD, 366 MR_EVT_ARGS_PD_ERR, 367 MR_EVT_ARGS_PD_LBA, 368 MR_EVT_ARGS_PD_LBA_LD, 369 MR_EVT_ARGS_PD_PROG, 370 MR_EVT_ARGS_PD_STATE, 371 MR_EVT_ARGS_PCI, 372 MR_EVT_ARGS_RATE, 373 MR_EVT_ARGS_STR, 374 MR_EVT_ARGS_TIME, 375 MR_EVT_ARGS_ECC, 376 MR_EVT_ARGS_LD_PROP, 377 MR_EVT_ARGS_PD_SPARE, 378 MR_EVT_ARGS_PD_INDEX, 379 MR_EVT_ARGS_DIAG_PASS, 380 MR_EVT_ARGS_DIAG_FAIL, 381 MR_EVT_ARGS_PD_LBA_LBA, 382 MR_EVT_ARGS_PORT_PHY, 383 MR_EVT_ARGS_PD_MISSING, 384 MR_EVT_ARGS_PD_ADDRESS, 385 MR_EVT_ARGS_BITMAP, 386 MR_EVT_ARGS_CONNECTOR, 387 MR_EVT_ARGS_PD_PD, 388 MR_EVT_ARGS_PD_FRU, 389 MR_EVT_ARGS_PD_PATHINFO, 390 MR_EVT_ARGS_PD_POWER_STATE, 391 MR_EVT_ARGS_GENERIC, 392 }; 393 394 395 #define SGE_BUFFER_SIZE 4096 396 #define MEGASAS_CLUSTER_ID_SIZE 16 397 /* 398 * define constants for device list query options 399 */ 400 enum MR_PD_QUERY_TYPE { 401 MR_PD_QUERY_TYPE_ALL = 0, 402 MR_PD_QUERY_TYPE_STATE = 1, 403 MR_PD_QUERY_TYPE_POWER_STATE = 2, 404 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 405 MR_PD_QUERY_TYPE_SPEED = 4, 406 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 407 }; 408 409 enum MR_LD_QUERY_TYPE { 410 MR_LD_QUERY_TYPE_ALL = 0, 411 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1, 412 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2, 413 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3, 414 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4, 415 }; 416 417 418 #define MR_EVT_CFG_CLEARED 0x0004 419 #define MR_EVT_LD_STATE_CHANGE 0x0051 420 #define MR_EVT_PD_INSERTED 0x005b 421 #define MR_EVT_PD_REMOVED 0x0070 422 #define MR_EVT_LD_CREATED 0x008a 423 #define MR_EVT_LD_DELETED 0x008b 424 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 425 #define MR_EVT_LD_OFFLINE 0x00fc 426 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 427 #define MR_EVT_CTRL_PROP_CHANGED 0x012f 428 429 enum MR_PD_STATE { 430 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 431 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 432 MR_PD_STATE_HOT_SPARE = 0x02, 433 MR_PD_STATE_OFFLINE = 0x10, 434 MR_PD_STATE_FAILED = 0x11, 435 MR_PD_STATE_REBUILD = 0x14, 436 MR_PD_STATE_ONLINE = 0x18, 437 MR_PD_STATE_COPYBACK = 0x20, 438 MR_PD_STATE_SYSTEM = 0x40, 439 }; 440 441 union MR_PD_REF { 442 struct { 443 u16 deviceId; 444 u16 seqNum; 445 } mrPdRef; 446 u32 ref; 447 }; 448 449 /* 450 * define the DDF Type bit structure 451 */ 452 union MR_PD_DDF_TYPE { 453 struct { 454 union { 455 struct { 456 #ifndef __BIG_ENDIAN_BITFIELD 457 u16 forcedPDGUID:1; 458 u16 inVD:1; 459 u16 isGlobalSpare:1; 460 u16 isSpare:1; 461 u16 isForeign:1; 462 u16 reserved:7; 463 u16 intf:4; 464 #else 465 u16 intf:4; 466 u16 reserved:7; 467 u16 isForeign:1; 468 u16 isSpare:1; 469 u16 isGlobalSpare:1; 470 u16 inVD:1; 471 u16 forcedPDGUID:1; 472 #endif 473 } pdType; 474 u16 type; 475 }; 476 u16 reserved; 477 } ddf; 478 struct { 479 u32 reserved; 480 } nonDisk; 481 u32 type; 482 } __packed; 483 484 /* 485 * defines the progress structure 486 */ 487 union MR_PROGRESS { 488 struct { 489 u16 progress; 490 union { 491 u16 elapsedSecs; 492 u16 elapsedSecsForLastPercent; 493 }; 494 } mrProgress; 495 u32 w; 496 } __packed; 497 498 /* 499 * defines the physical drive progress structure 500 */ 501 struct MR_PD_PROGRESS { 502 struct { 503 #ifndef MFI_BIG_ENDIAN 504 u32 rbld:1; 505 u32 patrol:1; 506 u32 clear:1; 507 u32 copyBack:1; 508 u32 erase:1; 509 u32 locate:1; 510 u32 reserved:26; 511 #else 512 u32 reserved:26; 513 u32 locate:1; 514 u32 erase:1; 515 u32 copyBack:1; 516 u32 clear:1; 517 u32 patrol:1; 518 u32 rbld:1; 519 #endif 520 } active; 521 union MR_PROGRESS rbld; 522 union MR_PROGRESS patrol; 523 union { 524 union MR_PROGRESS clear; 525 union MR_PROGRESS erase; 526 }; 527 528 struct { 529 #ifndef MFI_BIG_ENDIAN 530 u32 rbld:1; 531 u32 patrol:1; 532 u32 clear:1; 533 u32 copyBack:1; 534 u32 erase:1; 535 u32 reserved:27; 536 #else 537 u32 reserved:27; 538 u32 erase:1; 539 u32 copyBack:1; 540 u32 clear:1; 541 u32 patrol:1; 542 u32 rbld:1; 543 #endif 544 } pause; 545 546 union MR_PROGRESS reserved[3]; 547 } __packed; 548 549 struct MR_PD_INFO { 550 union MR_PD_REF ref; 551 u8 inquiryData[96]; 552 u8 vpdPage83[64]; 553 u8 notSupported; 554 u8 scsiDevType; 555 556 union { 557 u8 connectedPortBitmap; 558 u8 connectedPortNumbers; 559 }; 560 561 u8 deviceSpeed; 562 u32 mediaErrCount; 563 u32 otherErrCount; 564 u32 predFailCount; 565 u32 lastPredFailEventSeqNum; 566 567 u16 fwState; 568 u8 disabledForRemoval; 569 u8 linkSpeed; 570 union MR_PD_DDF_TYPE state; 571 572 struct { 573 u8 count; 574 #ifndef __BIG_ENDIAN_BITFIELD 575 u8 isPathBroken:4; 576 u8 reserved3:3; 577 u8 widePortCapable:1; 578 #else 579 u8 widePortCapable:1; 580 u8 reserved3:3; 581 u8 isPathBroken:4; 582 #endif 583 584 u8 connectorIndex[2]; 585 u8 reserved[4]; 586 u64 sasAddr[2]; 587 u8 reserved2[16]; 588 } pathInfo; 589 590 u64 rawSize; 591 u64 nonCoercedSize; 592 u64 coercedSize; 593 u16 enclDeviceId; 594 u8 enclIndex; 595 596 union { 597 u8 slotNumber; 598 u8 enclConnectorIndex; 599 }; 600 601 struct MR_PD_PROGRESS progInfo; 602 u8 badBlockTableFull; 603 u8 unusableInCurrentConfig; 604 u8 vpdPage83Ext[64]; 605 u8 powerState; 606 u8 enclPosition; 607 u32 allowedOps; 608 u16 copyBackPartnerId; 609 u16 enclPartnerDeviceId; 610 struct { 611 #ifndef __BIG_ENDIAN_BITFIELD 612 u16 fdeCapable:1; 613 u16 fdeEnabled:1; 614 u16 secured:1; 615 u16 locked:1; 616 u16 foreign:1; 617 u16 needsEKM:1; 618 u16 reserved:10; 619 #else 620 u16 reserved:10; 621 u16 needsEKM:1; 622 u16 foreign:1; 623 u16 locked:1; 624 u16 secured:1; 625 u16 fdeEnabled:1; 626 u16 fdeCapable:1; 627 #endif 628 } security; 629 u8 mediaType; 630 u8 notCertified; 631 u8 bridgeVendor[8]; 632 u8 bridgeProductIdentification[16]; 633 u8 bridgeProductRevisionLevel[4]; 634 u8 satBridgeExists; 635 636 u8 interfaceType; 637 u8 temperature; 638 u8 emulatedBlockSize; 639 u16 userDataBlockSize; 640 u16 reserved2; 641 642 struct { 643 #ifndef __BIG_ENDIAN_BITFIELD 644 u32 piType:3; 645 u32 piFormatted:1; 646 u32 piEligible:1; 647 u32 NCQ:1; 648 u32 WCE:1; 649 u32 commissionedSpare:1; 650 u32 emergencySpare:1; 651 u32 ineligibleForSSCD:1; 652 u32 ineligibleForLd:1; 653 u32 useSSEraseType:1; 654 u32 wceUnchanged:1; 655 u32 supportScsiUnmap:1; 656 u32 reserved:18; 657 #else 658 u32 reserved:18; 659 u32 supportScsiUnmap:1; 660 u32 wceUnchanged:1; 661 u32 useSSEraseType:1; 662 u32 ineligibleForLd:1; 663 u32 ineligibleForSSCD:1; 664 u32 emergencySpare:1; 665 u32 commissionedSpare:1; 666 u32 WCE:1; 667 u32 NCQ:1; 668 u32 piEligible:1; 669 u32 piFormatted:1; 670 u32 piType:3; 671 #endif 672 } properties; 673 674 u64 shieldDiagCompletionTime; 675 u8 shieldCounter; 676 677 u8 linkSpeedOther; 678 u8 reserved4[2]; 679 680 struct { 681 #ifndef __BIG_ENDIAN_BITFIELD 682 u32 bbmErrCountSupported:1; 683 u32 bbmErrCount:31; 684 #else 685 u32 bbmErrCount:31; 686 u32 bbmErrCountSupported:1; 687 #endif 688 } bbmErr; 689 690 u8 reserved1[512-428]; 691 } __packed; 692 693 /* 694 * defines the physical drive address structure 695 */ 696 struct MR_PD_ADDRESS { 697 __le16 deviceId; 698 u16 enclDeviceId; 699 700 union { 701 struct { 702 u8 enclIndex; 703 u8 slotNumber; 704 } mrPdAddress; 705 struct { 706 u8 enclPosition; 707 u8 enclConnectorIndex; 708 } mrEnclAddress; 709 }; 710 u8 scsiDevType; 711 union { 712 u8 connectedPortBitmap; 713 u8 connectedPortNumbers; 714 }; 715 u64 sasAddr[2]; 716 } __packed; 717 718 /* 719 * defines the physical drive list structure 720 */ 721 struct MR_PD_LIST { 722 __le32 size; 723 __le32 count; 724 struct MR_PD_ADDRESS addr[1]; 725 } __packed; 726 727 struct megasas_pd_list { 728 u16 tid; 729 u8 driveType; 730 u8 driveState; 731 u8 interface; 732 } __packed; 733 734 /* 735 * defines the logical drive reference structure 736 */ 737 union MR_LD_REF { 738 struct { 739 u8 targetId; 740 u8 reserved; 741 __le16 seqNum; 742 }; 743 __le32 ref; 744 } __packed; 745 746 /* 747 * defines the logical drive list structure 748 */ 749 struct MR_LD_LIST { 750 __le32 ldCount; 751 __le32 reserved; 752 struct { 753 union MR_LD_REF ref; 754 u8 state; 755 u8 reserved[3]; 756 __le64 size; 757 } ldList[MAX_LOGICAL_DRIVES_EXT]; 758 } __packed; 759 760 struct MR_LD_TARGETID_LIST { 761 __le32 size; 762 __le32 count; 763 u8 pad[3]; 764 u8 targetId[MAX_LOGICAL_DRIVES_EXT]; 765 }; 766 767 768 /* 769 * SAS controller properties 770 */ 771 struct megasas_ctrl_prop { 772 773 u16 seq_num; 774 u16 pred_fail_poll_interval; 775 u16 intr_throttle_count; 776 u16 intr_throttle_timeouts; 777 u8 rebuild_rate; 778 u8 patrol_read_rate; 779 u8 bgi_rate; 780 u8 cc_rate; 781 u8 recon_rate; 782 u8 cache_flush_interval; 783 u8 spinup_drv_count; 784 u8 spinup_delay; 785 u8 cluster_enable; 786 u8 coercion_mode; 787 u8 alarm_enable; 788 u8 disable_auto_rebuild; 789 u8 disable_battery_warn; 790 u8 ecc_bucket_size; 791 u16 ecc_bucket_leak_rate; 792 u8 restore_hotspare_on_insertion; 793 u8 expose_encl_devices; 794 u8 maintainPdFailHistory; 795 u8 disallowHostRequestReordering; 796 u8 abortCCOnError; 797 u8 loadBalanceMode; 798 u8 disableAutoDetectBackplane; 799 800 u8 snapVDSpace; 801 802 /* 803 * Add properties that can be controlled by 804 * a bit in the following structure. 805 */ 806 struct { 807 #if defined(__BIG_ENDIAN_BITFIELD) 808 u32 reserved:18; 809 u32 enableJBOD:1; 810 u32 disableSpinDownHS:1; 811 u32 allowBootWithPinnedCache:1; 812 u32 disableOnlineCtrlReset:1; 813 u32 enableSecretKeyControl:1; 814 u32 autoEnhancedImport:1; 815 u32 enableSpinDownUnconfigured:1; 816 u32 SSDPatrolReadEnabled:1; 817 u32 SSDSMARTerEnabled:1; 818 u32 disableNCQ:1; 819 u32 useFdeOnly:1; 820 u32 prCorrectUnconfiguredAreas:1; 821 u32 SMARTerEnabled:1; 822 u32 copyBackDisabled:1; 823 #else 824 u32 copyBackDisabled:1; 825 u32 SMARTerEnabled:1; 826 u32 prCorrectUnconfiguredAreas:1; 827 u32 useFdeOnly:1; 828 u32 disableNCQ:1; 829 u32 SSDSMARTerEnabled:1; 830 u32 SSDPatrolReadEnabled:1; 831 u32 enableSpinDownUnconfigured:1; 832 u32 autoEnhancedImport:1; 833 u32 enableSecretKeyControl:1; 834 u32 disableOnlineCtrlReset:1; 835 u32 allowBootWithPinnedCache:1; 836 u32 disableSpinDownHS:1; 837 u32 enableJBOD:1; 838 u32 reserved:18; 839 #endif 840 } OnOffProperties; 841 u8 autoSnapVDSpace; 842 u8 viewSpace; 843 __le16 spinDownTime; 844 u8 reserved[24]; 845 } __packed; 846 847 /* 848 * SAS controller information 849 */ 850 struct megasas_ctrl_info { 851 852 /* 853 * PCI device information 854 */ 855 struct { 856 857 __le16 vendor_id; 858 __le16 device_id; 859 __le16 sub_vendor_id; 860 __le16 sub_device_id; 861 u8 reserved[24]; 862 863 } __attribute__ ((packed)) pci; 864 865 /* 866 * Host interface information 867 */ 868 struct { 869 870 u8 PCIX:1; 871 u8 PCIE:1; 872 u8 iSCSI:1; 873 u8 SAS_3G:1; 874 u8 SRIOV:1; 875 u8 reserved_0:3; 876 u8 reserved_1[6]; 877 u8 port_count; 878 u64 port_addr[8]; 879 880 } __attribute__ ((packed)) host_interface; 881 882 /* 883 * Device (backend) interface information 884 */ 885 struct { 886 887 u8 SPI:1; 888 u8 SAS_3G:1; 889 u8 SATA_1_5G:1; 890 u8 SATA_3G:1; 891 u8 reserved_0:4; 892 u8 reserved_1[6]; 893 u8 port_count; 894 u64 port_addr[8]; 895 896 } __attribute__ ((packed)) device_interface; 897 898 /* 899 * List of components residing in flash. All str are null terminated 900 */ 901 __le32 image_check_word; 902 __le32 image_component_count; 903 904 struct { 905 906 char name[8]; 907 char version[32]; 908 char build_date[16]; 909 char built_time[16]; 910 911 } __attribute__ ((packed)) image_component[8]; 912 913 /* 914 * List of flash components that have been flashed on the card, but 915 * are not in use, pending reset of the adapter. This list will be 916 * empty if a flash operation has not occurred. All stings are null 917 * terminated 918 */ 919 __le32 pending_image_component_count; 920 921 struct { 922 923 char name[8]; 924 char version[32]; 925 char build_date[16]; 926 char build_time[16]; 927 928 } __attribute__ ((packed)) pending_image_component[8]; 929 930 u8 max_arms; 931 u8 max_spans; 932 u8 max_arrays; 933 u8 max_lds; 934 935 char product_name[80]; 936 char serial_no[32]; 937 938 /* 939 * Other physical/controller/operation information. Indicates the 940 * presence of the hardware 941 */ 942 struct { 943 944 u32 bbu:1; 945 u32 alarm:1; 946 u32 nvram:1; 947 u32 uart:1; 948 u32 reserved:28; 949 950 } __attribute__ ((packed)) hw_present; 951 952 __le32 current_fw_time; 953 954 /* 955 * Maximum data transfer sizes 956 */ 957 __le16 max_concurrent_cmds; 958 __le16 max_sge_count; 959 __le32 max_request_size; 960 961 /* 962 * Logical and physical device counts 963 */ 964 __le16 ld_present_count; 965 __le16 ld_degraded_count; 966 __le16 ld_offline_count; 967 968 __le16 pd_present_count; 969 __le16 pd_disk_present_count; 970 __le16 pd_disk_pred_failure_count; 971 __le16 pd_disk_failed_count; 972 973 /* 974 * Memory size information 975 */ 976 __le16 nvram_size; 977 __le16 memory_size; 978 __le16 flash_size; 979 980 /* 981 * Error counters 982 */ 983 __le16 mem_correctable_error_count; 984 __le16 mem_uncorrectable_error_count; 985 986 /* 987 * Cluster information 988 */ 989 u8 cluster_permitted; 990 u8 cluster_active; 991 992 /* 993 * Additional max data transfer sizes 994 */ 995 __le16 max_strips_per_io; 996 997 /* 998 * Controller capabilities structures 999 */ 1000 struct { 1001 1002 u32 raid_level_0:1; 1003 u32 raid_level_1:1; 1004 u32 raid_level_5:1; 1005 u32 raid_level_1E:1; 1006 u32 raid_level_6:1; 1007 u32 reserved:27; 1008 1009 } __attribute__ ((packed)) raid_levels; 1010 1011 struct { 1012 1013 u32 rbld_rate:1; 1014 u32 cc_rate:1; 1015 u32 bgi_rate:1; 1016 u32 recon_rate:1; 1017 u32 patrol_rate:1; 1018 u32 alarm_control:1; 1019 u32 cluster_supported:1; 1020 u32 bbu:1; 1021 u32 spanning_allowed:1; 1022 u32 dedicated_hotspares:1; 1023 u32 revertible_hotspares:1; 1024 u32 foreign_config_import:1; 1025 u32 self_diagnostic:1; 1026 u32 mixed_redundancy_arr:1; 1027 u32 global_hot_spares:1; 1028 u32 reserved:17; 1029 1030 } __attribute__ ((packed)) adapter_operations; 1031 1032 struct { 1033 1034 u32 read_policy:1; 1035 u32 write_policy:1; 1036 u32 io_policy:1; 1037 u32 access_policy:1; 1038 u32 disk_cache_policy:1; 1039 u32 reserved:27; 1040 1041 } __attribute__ ((packed)) ld_operations; 1042 1043 struct { 1044 1045 u8 min; 1046 u8 max; 1047 u8 reserved[2]; 1048 1049 } __attribute__ ((packed)) stripe_sz_ops; 1050 1051 struct { 1052 1053 u32 force_online:1; 1054 u32 force_offline:1; 1055 u32 force_rebuild:1; 1056 u32 reserved:29; 1057 1058 } __attribute__ ((packed)) pd_operations; 1059 1060 struct { 1061 1062 u32 ctrl_supports_sas:1; 1063 u32 ctrl_supports_sata:1; 1064 u32 allow_mix_in_encl:1; 1065 u32 allow_mix_in_ld:1; 1066 u32 allow_sata_in_cluster:1; 1067 u32 reserved:27; 1068 1069 } __attribute__ ((packed)) pd_mix_support; 1070 1071 /* 1072 * Define ECC single-bit-error bucket information 1073 */ 1074 u8 ecc_bucket_count; 1075 u8 reserved_2[11]; 1076 1077 /* 1078 * Include the controller properties (changeable items) 1079 */ 1080 struct megasas_ctrl_prop properties; 1081 1082 /* 1083 * Define FW pkg version (set in envt v'bles on OEM basis) 1084 */ 1085 char package_version[0x60]; 1086 1087 1088 /* 1089 * If adapterOperations.supportMoreThan8Phys is set, 1090 * and deviceInterface.portCount is greater than 8, 1091 * SAS Addrs for first 8 ports shall be populated in 1092 * deviceInterface.portAddr, and the rest shall be 1093 * populated in deviceInterfacePortAddr2. 1094 */ 1095 __le64 deviceInterfacePortAddr2[8]; /*6a0h */ 1096 u8 reserved3[128]; /*6e0h */ 1097 1098 struct { /*760h */ 1099 u16 minPdRaidLevel_0:4; 1100 u16 maxPdRaidLevel_0:12; 1101 1102 u16 minPdRaidLevel_1:4; 1103 u16 maxPdRaidLevel_1:12; 1104 1105 u16 minPdRaidLevel_5:4; 1106 u16 maxPdRaidLevel_5:12; 1107 1108 u16 minPdRaidLevel_1E:4; 1109 u16 maxPdRaidLevel_1E:12; 1110 1111 u16 minPdRaidLevel_6:4; 1112 u16 maxPdRaidLevel_6:12; 1113 1114 u16 minPdRaidLevel_10:4; 1115 u16 maxPdRaidLevel_10:12; 1116 1117 u16 minPdRaidLevel_50:4; 1118 u16 maxPdRaidLevel_50:12; 1119 1120 u16 minPdRaidLevel_60:4; 1121 u16 maxPdRaidLevel_60:12; 1122 1123 u16 minPdRaidLevel_1E_RLQ0:4; 1124 u16 maxPdRaidLevel_1E_RLQ0:12; 1125 1126 u16 minPdRaidLevel_1E0_RLQ0:4; 1127 u16 maxPdRaidLevel_1E0_RLQ0:12; 1128 1129 u16 reserved[6]; 1130 } pdsForRaidLevels; 1131 1132 __le16 maxPds; /*780h */ 1133 __le16 maxDedHSPs; /*782h */ 1134 __le16 maxGlobalHSP; /*784h */ 1135 __le16 ddfSize; /*786h */ 1136 u8 maxLdsPerArray; /*788h */ 1137 u8 partitionsInDDF; /*789h */ 1138 u8 lockKeyBinding; /*78ah */ 1139 u8 maxPITsPerLd; /*78bh */ 1140 u8 maxViewsPerLd; /*78ch */ 1141 u8 maxTargetId; /*78dh */ 1142 __le16 maxBvlVdSize; /*78eh */ 1143 1144 __le16 maxConfigurableSSCSize; /*790h */ 1145 __le16 currentSSCsize; /*792h */ 1146 1147 char expanderFwVersion[12]; /*794h */ 1148 1149 __le16 PFKTrialTimeRemaining; /*7A0h */ 1150 1151 __le16 cacheMemorySize; /*7A2h */ 1152 1153 struct { /*7A4h */ 1154 #if defined(__BIG_ENDIAN_BITFIELD) 1155 u32 reserved:5; 1156 u32 activePassive:2; 1157 u32 supportConfigAutoBalance:1; 1158 u32 mpio:1; 1159 u32 supportDataLDonSSCArray:1; 1160 u32 supportPointInTimeProgress:1; 1161 u32 supportUnevenSpans:1; 1162 u32 dedicatedHotSparesLimited:1; 1163 u32 headlessMode:1; 1164 u32 supportEmulatedDrives:1; 1165 u32 supportResetNow:1; 1166 u32 realTimeScheduler:1; 1167 u32 supportSSDPatrolRead:1; 1168 u32 supportPerfTuning:1; 1169 u32 disableOnlinePFKChange:1; 1170 u32 supportJBOD:1; 1171 u32 supportBootTimePFKChange:1; 1172 u32 supportSetLinkSpeed:1; 1173 u32 supportEmergencySpares:1; 1174 u32 supportSuspendResumeBGops:1; 1175 u32 blockSSDWriteCacheChange:1; 1176 u32 supportShieldState:1; 1177 u32 supportLdBBMInfo:1; 1178 u32 supportLdPIType3:1; 1179 u32 supportLdPIType2:1; 1180 u32 supportLdPIType1:1; 1181 u32 supportPIcontroller:1; 1182 #else 1183 u32 supportPIcontroller:1; 1184 u32 supportLdPIType1:1; 1185 u32 supportLdPIType2:1; 1186 u32 supportLdPIType3:1; 1187 u32 supportLdBBMInfo:1; 1188 u32 supportShieldState:1; 1189 u32 blockSSDWriteCacheChange:1; 1190 u32 supportSuspendResumeBGops:1; 1191 u32 supportEmergencySpares:1; 1192 u32 supportSetLinkSpeed:1; 1193 u32 supportBootTimePFKChange:1; 1194 u32 supportJBOD:1; 1195 u32 disableOnlinePFKChange:1; 1196 u32 supportPerfTuning:1; 1197 u32 supportSSDPatrolRead:1; 1198 u32 realTimeScheduler:1; 1199 1200 u32 supportResetNow:1; 1201 u32 supportEmulatedDrives:1; 1202 u32 headlessMode:1; 1203 u32 dedicatedHotSparesLimited:1; 1204 1205 1206 u32 supportUnevenSpans:1; 1207 u32 supportPointInTimeProgress:1; 1208 u32 supportDataLDonSSCArray:1; 1209 u32 mpio:1; 1210 u32 supportConfigAutoBalance:1; 1211 u32 activePassive:2; 1212 u32 reserved:5; 1213 #endif 1214 } adapterOperations2; 1215 1216 u8 driverVersion[32]; /*7A8h */ 1217 u8 maxDAPdCountSpinup60; /*7C8h */ 1218 u8 temperatureROC; /*7C9h */ 1219 u8 temperatureCtrl; /*7CAh */ 1220 u8 reserved4; /*7CBh */ 1221 __le16 maxConfigurablePds; /*7CCh */ 1222 1223 1224 u8 reserved5[2]; /*0x7CDh */ 1225 1226 /* 1227 * HA cluster information 1228 */ 1229 struct { 1230 #if defined(__BIG_ENDIAN_BITFIELD) 1231 u32 reserved:25; 1232 u32 passive:1; 1233 u32 premiumFeatureMismatch:1; 1234 u32 ctrlPropIncompatible:1; 1235 u32 fwVersionMismatch:1; 1236 u32 hwIncompatible:1; 1237 u32 peerIsIncompatible:1; 1238 u32 peerIsPresent:1; 1239 #else 1240 u32 peerIsPresent:1; 1241 u32 peerIsIncompatible:1; 1242 u32 hwIncompatible:1; 1243 u32 fwVersionMismatch:1; 1244 u32 ctrlPropIncompatible:1; 1245 u32 premiumFeatureMismatch:1; 1246 u32 passive:1; 1247 u32 reserved:25; 1248 #endif 1249 } cluster; 1250 1251 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */ 1252 struct { 1253 u8 maxVFsSupported; /*0x7E4*/ 1254 u8 numVFsEnabled; /*0x7E5*/ 1255 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/ 1256 u8 reserved; /*0x7E7*/ 1257 } iov; 1258 1259 struct { 1260 #if defined(__BIG_ENDIAN_BITFIELD) 1261 u32 reserved:7; 1262 u32 useSeqNumJbodFP:1; 1263 u32 supportExtendedSSCSize:1; 1264 u32 supportDiskCacheSettingForSysPDs:1; 1265 u32 supportCPLDUpdate:1; 1266 u32 supportTTYLogCompression:1; 1267 u32 discardCacheDuringLDDelete:1; 1268 u32 supportSecurityonJBOD:1; 1269 u32 supportCacheBypassModes:1; 1270 u32 supportDisableSESMonitoring:1; 1271 u32 supportForceFlash:1; 1272 u32 supportNVDRAM:1; 1273 u32 supportDrvActivityLEDSetting:1; 1274 u32 supportAllowedOpsforDrvRemoval:1; 1275 u32 supportHOQRebuild:1; 1276 u32 supportForceTo512e:1; 1277 u32 supportNVCacheErase:1; 1278 u32 supportDebugQueue:1; 1279 u32 supportSwZone:1; 1280 u32 supportCrashDump:1; 1281 u32 supportMaxExtLDs:1; 1282 u32 supportT10RebuildAssist:1; 1283 u32 supportDisableImmediateIO:1; 1284 u32 supportThermalPollInterval:1; 1285 u32 supportPersonalityChange:2; 1286 #else 1287 u32 supportPersonalityChange:2; 1288 u32 supportThermalPollInterval:1; 1289 u32 supportDisableImmediateIO:1; 1290 u32 supportT10RebuildAssist:1; 1291 u32 supportMaxExtLDs:1; 1292 u32 supportCrashDump:1; 1293 u32 supportSwZone:1; 1294 u32 supportDebugQueue:1; 1295 u32 supportNVCacheErase:1; 1296 u32 supportForceTo512e:1; 1297 u32 supportHOQRebuild:1; 1298 u32 supportAllowedOpsforDrvRemoval:1; 1299 u32 supportDrvActivityLEDSetting:1; 1300 u32 supportNVDRAM:1; 1301 u32 supportForceFlash:1; 1302 u32 supportDisableSESMonitoring:1; 1303 u32 supportCacheBypassModes:1; 1304 u32 supportSecurityonJBOD:1; 1305 u32 discardCacheDuringLDDelete:1; 1306 u32 supportTTYLogCompression:1; 1307 u32 supportCPLDUpdate:1; 1308 u32 supportDiskCacheSettingForSysPDs:1; 1309 u32 supportExtendedSSCSize:1; 1310 u32 useSeqNumJbodFP:1; 1311 u32 reserved:7; 1312 #endif 1313 } adapterOperations3; 1314 1315 u8 pad[0x800-0x7EC]; 1316 } __packed; 1317 1318 /* 1319 * =============================== 1320 * MegaRAID SAS driver definitions 1321 * =============================== 1322 */ 1323 #define MEGASAS_MAX_PD_CHANNELS 2 1324 #define MEGASAS_MAX_LD_CHANNELS 2 1325 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \ 1326 MEGASAS_MAX_LD_CHANNELS) 1327 #define MEGASAS_MAX_DEV_PER_CHANNEL 128 1328 #define MEGASAS_DEFAULT_INIT_ID -1 1329 #define MEGASAS_MAX_LUN 8 1330 #define MEGASAS_DEFAULT_CMD_PER_LUN 256 1331 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \ 1332 MEGASAS_MAX_DEV_PER_CHANNEL) 1333 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \ 1334 MEGASAS_MAX_DEV_PER_CHANNEL) 1335 1336 #define MEGASAS_MAX_SECTORS (2*1024) 1337 #define MEGASAS_MAX_SECTORS_IEEE (2*128) 1338 #define MEGASAS_DBG_LVL 1 1339 1340 #define MEGASAS_FW_BUSY 1 1341 1342 #define VD_EXT_DEBUG 0 1343 1344 #define SCAN_PD_CHANNEL 0x1 1345 #define SCAN_VD_CHANNEL 0x2 1346 1347 enum MR_SCSI_CMD_TYPE { 1348 READ_WRITE_LDIO = 0, 1349 NON_READ_WRITE_LDIO = 1, 1350 READ_WRITE_SYSPDIO = 2, 1351 NON_READ_WRITE_SYSPDIO = 3, 1352 }; 1353 1354 enum DCMD_TIMEOUT_ACTION { 1355 INITIATE_OCR = 0, 1356 KILL_ADAPTER = 1, 1357 IGNORE_TIMEOUT = 2, 1358 }; 1359 1360 enum FW_BOOT_CONTEXT { 1361 PROBE_CONTEXT = 0, 1362 OCR_CONTEXT = 1, 1363 }; 1364 1365 /* Frame Type */ 1366 #define IO_FRAME 0 1367 #define PTHRU_FRAME 1 1368 1369 /* 1370 * When SCSI mid-layer calls driver's reset routine, driver waits for 1371 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1372 * that the driver cannot _actually_ abort or reset pending commands. While 1373 * it is waiting for the commands to complete, it prints a diagnostic message 1374 * every MEGASAS_RESET_NOTICE_INTERVAL seconds 1375 */ 1376 #define MEGASAS_RESET_WAIT_TIME 180 1377 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180 1378 #define MEGASAS_RESET_NOTICE_INTERVAL 5 1379 #define MEGASAS_IOCTL_CMD 0 1380 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90 1381 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16 1382 #define MEGASAS_BLOCKED_CMD_TIMEOUT 60 1383 /* 1384 * FW reports the maximum of number of commands that it can accept (maximum 1385 * commands that can be outstanding) at any time. The driver must report a 1386 * lower number to the mid layer because it can issue a few internal commands 1387 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1388 * is shown below 1389 */ 1390 #define MEGASAS_INT_CMDS 32 1391 #define MEGASAS_SKINNY_INT_CMDS 5 1392 #define MEGASAS_FUSION_INTERNAL_CMDS 5 1393 #define MEGASAS_FUSION_IOCTL_CMDS 3 1394 #define MEGASAS_MFI_IOCTL_CMDS 27 1395 1396 #define MEGASAS_MAX_MSIX_QUEUES 128 1397 /* 1398 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1399 * SGLs based on the size of dma_addr_t 1400 */ 1401 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 1402 1403 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 1404 1405 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1406 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1407 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 1408 1409 #define MFI_OB_INTR_STATUS_MASK 0x00000002 1410 #define MFI_POLL_TIMEOUT_SECS 60 1411 #define MFI_IO_TIMEOUT_SECS 180 1412 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ) 1413 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30) 1414 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300 1415 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1416 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1417 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004) 1418 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1419 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1420 1421 #define MFI_1068_PCSR_OFFSET 0x84 1422 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1423 #define MFI_1068_FW_READY 0xDDDD0000 1424 1425 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F 1426 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000 1427 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1428 #define MR_MAX_MSIX_REG_ARRAY 16 1429 #define MR_RDPQ_MODE_OFFSET 0X00800000 1430 /* 1431 * register set for both 1068 and 1078 controllers 1432 * structure extended for 1078 registers 1433 */ 1434 1435 struct megasas_register_set { 1436 u32 doorbell; /*0000h*/ 1437 u32 fusion_seq_offset; /*0004h*/ 1438 u32 fusion_host_diag; /*0008h*/ 1439 u32 reserved_01; /*000Ch*/ 1440 1441 u32 inbound_msg_0; /*0010h*/ 1442 u32 inbound_msg_1; /*0014h*/ 1443 u32 outbound_msg_0; /*0018h*/ 1444 u32 outbound_msg_1; /*001Ch*/ 1445 1446 u32 inbound_doorbell; /*0020h*/ 1447 u32 inbound_intr_status; /*0024h*/ 1448 u32 inbound_intr_mask; /*0028h*/ 1449 1450 u32 outbound_doorbell; /*002Ch*/ 1451 u32 outbound_intr_status; /*0030h*/ 1452 u32 outbound_intr_mask; /*0034h*/ 1453 1454 u32 reserved_1[2]; /*0038h*/ 1455 1456 u32 inbound_queue_port; /*0040h*/ 1457 u32 outbound_queue_port; /*0044h*/ 1458 1459 u32 reserved_2[9]; /*0048h*/ 1460 u32 reply_post_host_index; /*006Ch*/ 1461 u32 reserved_2_2[12]; /*0070h*/ 1462 1463 u32 outbound_doorbell_clear; /*00A0h*/ 1464 1465 u32 reserved_3[3]; /*00A4h*/ 1466 1467 u32 outbound_scratch_pad ; /*00B0h*/ 1468 u32 outbound_scratch_pad_2; /*00B4h*/ 1469 u32 outbound_scratch_pad_3; /*00B8h*/ 1470 1471 u32 reserved_4; /*00BCh*/ 1472 1473 u32 inbound_low_queue_port ; /*00C0h*/ 1474 1475 u32 inbound_high_queue_port ; /*00C4h*/ 1476 1477 u32 reserved_5; /*00C8h*/ 1478 u32 res_6[11]; /*CCh*/ 1479 u32 host_diag; 1480 u32 seq_offset; 1481 u32 index_registers[807]; /*00CCh*/ 1482 } __attribute__ ((packed)); 1483 1484 struct megasas_sge32 { 1485 1486 __le32 phys_addr; 1487 __le32 length; 1488 1489 } __attribute__ ((packed)); 1490 1491 struct megasas_sge64 { 1492 1493 __le64 phys_addr; 1494 __le32 length; 1495 1496 } __attribute__ ((packed)); 1497 1498 struct megasas_sge_skinny { 1499 __le64 phys_addr; 1500 __le32 length; 1501 __le32 flag; 1502 } __packed; 1503 1504 union megasas_sgl { 1505 1506 struct megasas_sge32 sge32[1]; 1507 struct megasas_sge64 sge64[1]; 1508 struct megasas_sge_skinny sge_skinny[1]; 1509 1510 } __attribute__ ((packed)); 1511 1512 struct megasas_header { 1513 1514 u8 cmd; /*00h */ 1515 u8 sense_len; /*01h */ 1516 u8 cmd_status; /*02h */ 1517 u8 scsi_status; /*03h */ 1518 1519 u8 target_id; /*04h */ 1520 u8 lun; /*05h */ 1521 u8 cdb_len; /*06h */ 1522 u8 sge_count; /*07h */ 1523 1524 __le32 context; /*08h */ 1525 __le32 pad_0; /*0Ch */ 1526 1527 __le16 flags; /*10h */ 1528 __le16 timeout; /*12h */ 1529 __le32 data_xferlen; /*14h */ 1530 1531 } __attribute__ ((packed)); 1532 1533 union megasas_sgl_frame { 1534 1535 struct megasas_sge32 sge32[8]; 1536 struct megasas_sge64 sge64[5]; 1537 1538 } __attribute__ ((packed)); 1539 1540 typedef union _MFI_CAPABILITIES { 1541 struct { 1542 #if defined(__BIG_ENDIAN_BITFIELD) 1543 u32 reserved:20; 1544 u32 support_qd_throttling:1; 1545 u32 support_fp_rlbypass:1; 1546 u32 support_vfid_in_ioframe:1; 1547 u32 support_ext_io_size:1; 1548 u32 support_ext_queue_depth:1; 1549 u32 security_protocol_cmds_fw:1; 1550 u32 support_core_affinity:1; 1551 u32 support_ndrive_r1_lb:1; 1552 u32 support_max_255lds:1; 1553 u32 support_fastpath_wb:1; 1554 u32 support_additional_msix:1; 1555 u32 support_fp_remote_lun:1; 1556 #else 1557 u32 support_fp_remote_lun:1; 1558 u32 support_additional_msix:1; 1559 u32 support_fastpath_wb:1; 1560 u32 support_max_255lds:1; 1561 u32 support_ndrive_r1_lb:1; 1562 u32 support_core_affinity:1; 1563 u32 security_protocol_cmds_fw:1; 1564 u32 support_ext_queue_depth:1; 1565 u32 support_ext_io_size:1; 1566 u32 support_vfid_in_ioframe:1; 1567 u32 support_fp_rlbypass:1; 1568 u32 support_qd_throttling:1; 1569 u32 reserved:20; 1570 #endif 1571 } mfi_capabilities; 1572 __le32 reg; 1573 } MFI_CAPABILITIES; 1574 1575 struct megasas_init_frame { 1576 1577 u8 cmd; /*00h */ 1578 u8 reserved_0; /*01h */ 1579 u8 cmd_status; /*02h */ 1580 1581 u8 reserved_1; /*03h */ 1582 MFI_CAPABILITIES driver_operations; /*04h*/ 1583 1584 __le32 context; /*08h */ 1585 __le32 pad_0; /*0Ch */ 1586 1587 __le16 flags; /*10h */ 1588 __le16 reserved_3; /*12h */ 1589 __le32 data_xfer_len; /*14h */ 1590 1591 __le32 queue_info_new_phys_addr_lo; /*18h */ 1592 __le32 queue_info_new_phys_addr_hi; /*1Ch */ 1593 __le32 queue_info_old_phys_addr_lo; /*20h */ 1594 __le32 queue_info_old_phys_addr_hi; /*24h */ 1595 __le32 reserved_4[2]; /*28h */ 1596 __le32 system_info_lo; /*30h */ 1597 __le32 system_info_hi; /*34h */ 1598 __le32 reserved_5[2]; /*38h */ 1599 1600 } __attribute__ ((packed)); 1601 1602 struct megasas_init_queue_info { 1603 1604 __le32 init_flags; /*00h */ 1605 __le32 reply_queue_entries; /*04h */ 1606 1607 __le32 reply_queue_start_phys_addr_lo; /*08h */ 1608 __le32 reply_queue_start_phys_addr_hi; /*0Ch */ 1609 __le32 producer_index_phys_addr_lo; /*10h */ 1610 __le32 producer_index_phys_addr_hi; /*14h */ 1611 __le32 consumer_index_phys_addr_lo; /*18h */ 1612 __le32 consumer_index_phys_addr_hi; /*1Ch */ 1613 1614 } __attribute__ ((packed)); 1615 1616 struct megasas_io_frame { 1617 1618 u8 cmd; /*00h */ 1619 u8 sense_len; /*01h */ 1620 u8 cmd_status; /*02h */ 1621 u8 scsi_status; /*03h */ 1622 1623 u8 target_id; /*04h */ 1624 u8 access_byte; /*05h */ 1625 u8 reserved_0; /*06h */ 1626 u8 sge_count; /*07h */ 1627 1628 __le32 context; /*08h */ 1629 __le32 pad_0; /*0Ch */ 1630 1631 __le16 flags; /*10h */ 1632 __le16 timeout; /*12h */ 1633 __le32 lba_count; /*14h */ 1634 1635 __le32 sense_buf_phys_addr_lo; /*18h */ 1636 __le32 sense_buf_phys_addr_hi; /*1Ch */ 1637 1638 __le32 start_lba_lo; /*20h */ 1639 __le32 start_lba_hi; /*24h */ 1640 1641 union megasas_sgl sgl; /*28h */ 1642 1643 } __attribute__ ((packed)); 1644 1645 struct megasas_pthru_frame { 1646 1647 u8 cmd; /*00h */ 1648 u8 sense_len; /*01h */ 1649 u8 cmd_status; /*02h */ 1650 u8 scsi_status; /*03h */ 1651 1652 u8 target_id; /*04h */ 1653 u8 lun; /*05h */ 1654 u8 cdb_len; /*06h */ 1655 u8 sge_count; /*07h */ 1656 1657 __le32 context; /*08h */ 1658 __le32 pad_0; /*0Ch */ 1659 1660 __le16 flags; /*10h */ 1661 __le16 timeout; /*12h */ 1662 __le32 data_xfer_len; /*14h */ 1663 1664 __le32 sense_buf_phys_addr_lo; /*18h */ 1665 __le32 sense_buf_phys_addr_hi; /*1Ch */ 1666 1667 u8 cdb[16]; /*20h */ 1668 union megasas_sgl sgl; /*30h */ 1669 1670 } __attribute__ ((packed)); 1671 1672 struct megasas_dcmd_frame { 1673 1674 u8 cmd; /*00h */ 1675 u8 reserved_0; /*01h */ 1676 u8 cmd_status; /*02h */ 1677 u8 reserved_1[4]; /*03h */ 1678 u8 sge_count; /*07h */ 1679 1680 __le32 context; /*08h */ 1681 __le32 pad_0; /*0Ch */ 1682 1683 __le16 flags; /*10h */ 1684 __le16 timeout; /*12h */ 1685 1686 __le32 data_xfer_len; /*14h */ 1687 __le32 opcode; /*18h */ 1688 1689 union { /*1Ch */ 1690 u8 b[12]; 1691 __le16 s[6]; 1692 __le32 w[3]; 1693 } mbox; 1694 1695 union megasas_sgl sgl; /*28h */ 1696 1697 } __attribute__ ((packed)); 1698 1699 struct megasas_abort_frame { 1700 1701 u8 cmd; /*00h */ 1702 u8 reserved_0; /*01h */ 1703 u8 cmd_status; /*02h */ 1704 1705 u8 reserved_1; /*03h */ 1706 __le32 reserved_2; /*04h */ 1707 1708 __le32 context; /*08h */ 1709 __le32 pad_0; /*0Ch */ 1710 1711 __le16 flags; /*10h */ 1712 __le16 reserved_3; /*12h */ 1713 __le32 reserved_4; /*14h */ 1714 1715 __le32 abort_context; /*18h */ 1716 __le32 pad_1; /*1Ch */ 1717 1718 __le32 abort_mfi_phys_addr_lo; /*20h */ 1719 __le32 abort_mfi_phys_addr_hi; /*24h */ 1720 1721 __le32 reserved_5[6]; /*28h */ 1722 1723 } __attribute__ ((packed)); 1724 1725 struct megasas_smp_frame { 1726 1727 u8 cmd; /*00h */ 1728 u8 reserved_1; /*01h */ 1729 u8 cmd_status; /*02h */ 1730 u8 connection_status; /*03h */ 1731 1732 u8 reserved_2[3]; /*04h */ 1733 u8 sge_count; /*07h */ 1734 1735 __le32 context; /*08h */ 1736 __le32 pad_0; /*0Ch */ 1737 1738 __le16 flags; /*10h */ 1739 __le16 timeout; /*12h */ 1740 1741 __le32 data_xfer_len; /*14h */ 1742 __le64 sas_addr; /*18h */ 1743 1744 union { 1745 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */ 1746 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */ 1747 } sgl; 1748 1749 } __attribute__ ((packed)); 1750 1751 struct megasas_stp_frame { 1752 1753 u8 cmd; /*00h */ 1754 u8 reserved_1; /*01h */ 1755 u8 cmd_status; /*02h */ 1756 u8 reserved_2; /*03h */ 1757 1758 u8 target_id; /*04h */ 1759 u8 reserved_3[2]; /*05h */ 1760 u8 sge_count; /*07h */ 1761 1762 __le32 context; /*08h */ 1763 __le32 pad_0; /*0Ch */ 1764 1765 __le16 flags; /*10h */ 1766 __le16 timeout; /*12h */ 1767 1768 __le32 data_xfer_len; /*14h */ 1769 1770 __le16 fis[10]; /*18h */ 1771 __le32 stp_flags; 1772 1773 union { 1774 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */ 1775 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */ 1776 } sgl; 1777 1778 } __attribute__ ((packed)); 1779 1780 union megasas_frame { 1781 1782 struct megasas_header hdr; 1783 struct megasas_init_frame init; 1784 struct megasas_io_frame io; 1785 struct megasas_pthru_frame pthru; 1786 struct megasas_dcmd_frame dcmd; 1787 struct megasas_abort_frame abort; 1788 struct megasas_smp_frame smp; 1789 struct megasas_stp_frame stp; 1790 1791 u8 raw_bytes[64]; 1792 }; 1793 1794 /** 1795 * struct MR_PRIV_DEVICE - sdev private hostdata 1796 * @is_tm_capable: firmware managed tm_capable flag 1797 * @tm_busy: TM request is in progress 1798 */ 1799 struct MR_PRIV_DEVICE { 1800 bool is_tm_capable; 1801 bool tm_busy; 1802 }; 1803 struct megasas_cmd; 1804 1805 union megasas_evt_class_locale { 1806 1807 struct { 1808 #ifndef __BIG_ENDIAN_BITFIELD 1809 u16 locale; 1810 u8 reserved; 1811 s8 class; 1812 #else 1813 s8 class; 1814 u8 reserved; 1815 u16 locale; 1816 #endif 1817 } __attribute__ ((packed)) members; 1818 1819 u32 word; 1820 1821 } __attribute__ ((packed)); 1822 1823 struct megasas_evt_log_info { 1824 __le32 newest_seq_num; 1825 __le32 oldest_seq_num; 1826 __le32 clear_seq_num; 1827 __le32 shutdown_seq_num; 1828 __le32 boot_seq_num; 1829 1830 } __attribute__ ((packed)); 1831 1832 struct megasas_progress { 1833 1834 __le16 progress; 1835 __le16 elapsed_seconds; 1836 1837 } __attribute__ ((packed)); 1838 1839 struct megasas_evtarg_ld { 1840 1841 u16 target_id; 1842 u8 ld_index; 1843 u8 reserved; 1844 1845 } __attribute__ ((packed)); 1846 1847 struct megasas_evtarg_pd { 1848 u16 device_id; 1849 u8 encl_index; 1850 u8 slot_number; 1851 1852 } __attribute__ ((packed)); 1853 1854 struct megasas_evt_detail { 1855 1856 __le32 seq_num; 1857 __le32 time_stamp; 1858 __le32 code; 1859 union megasas_evt_class_locale cl; 1860 u8 arg_type; 1861 u8 reserved1[15]; 1862 1863 union { 1864 struct { 1865 struct megasas_evtarg_pd pd; 1866 u8 cdb_length; 1867 u8 sense_length; 1868 u8 reserved[2]; 1869 u8 cdb[16]; 1870 u8 sense[64]; 1871 } __attribute__ ((packed)) cdbSense; 1872 1873 struct megasas_evtarg_ld ld; 1874 1875 struct { 1876 struct megasas_evtarg_ld ld; 1877 __le64 count; 1878 } __attribute__ ((packed)) ld_count; 1879 1880 struct { 1881 __le64 lba; 1882 struct megasas_evtarg_ld ld; 1883 } __attribute__ ((packed)) ld_lba; 1884 1885 struct { 1886 struct megasas_evtarg_ld ld; 1887 __le32 prevOwner; 1888 __le32 newOwner; 1889 } __attribute__ ((packed)) ld_owner; 1890 1891 struct { 1892 u64 ld_lba; 1893 u64 pd_lba; 1894 struct megasas_evtarg_ld ld; 1895 struct megasas_evtarg_pd pd; 1896 } __attribute__ ((packed)) ld_lba_pd_lba; 1897 1898 struct { 1899 struct megasas_evtarg_ld ld; 1900 struct megasas_progress prog; 1901 } __attribute__ ((packed)) ld_prog; 1902 1903 struct { 1904 struct megasas_evtarg_ld ld; 1905 u32 prev_state; 1906 u32 new_state; 1907 } __attribute__ ((packed)) ld_state; 1908 1909 struct { 1910 u64 strip; 1911 struct megasas_evtarg_ld ld; 1912 } __attribute__ ((packed)) ld_strip; 1913 1914 struct megasas_evtarg_pd pd; 1915 1916 struct { 1917 struct megasas_evtarg_pd pd; 1918 u32 err; 1919 } __attribute__ ((packed)) pd_err; 1920 1921 struct { 1922 u64 lba; 1923 struct megasas_evtarg_pd pd; 1924 } __attribute__ ((packed)) pd_lba; 1925 1926 struct { 1927 u64 lba; 1928 struct megasas_evtarg_pd pd; 1929 struct megasas_evtarg_ld ld; 1930 } __attribute__ ((packed)) pd_lba_ld; 1931 1932 struct { 1933 struct megasas_evtarg_pd pd; 1934 struct megasas_progress prog; 1935 } __attribute__ ((packed)) pd_prog; 1936 1937 struct { 1938 struct megasas_evtarg_pd pd; 1939 u32 prevState; 1940 u32 newState; 1941 } __attribute__ ((packed)) pd_state; 1942 1943 struct { 1944 u16 vendorId; 1945 __le16 deviceId; 1946 u16 subVendorId; 1947 u16 subDeviceId; 1948 } __attribute__ ((packed)) pci; 1949 1950 u32 rate; 1951 char str[96]; 1952 1953 struct { 1954 u32 rtc; 1955 u32 elapsedSeconds; 1956 } __attribute__ ((packed)) time; 1957 1958 struct { 1959 u32 ecar; 1960 u32 elog; 1961 char str[64]; 1962 } __attribute__ ((packed)) ecc; 1963 1964 u8 b[96]; 1965 __le16 s[48]; 1966 __le32 w[24]; 1967 __le64 d[12]; 1968 } args; 1969 1970 char description[128]; 1971 1972 } __attribute__ ((packed)); 1973 1974 struct megasas_aen_event { 1975 struct delayed_work hotplug_work; 1976 struct megasas_instance *instance; 1977 }; 1978 1979 struct megasas_irq_context { 1980 struct megasas_instance *instance; 1981 u32 MSIxIndex; 1982 }; 1983 1984 struct MR_DRV_SYSTEM_INFO { 1985 u8 infoVersion; 1986 u8 systemIdLength; 1987 u16 reserved0; 1988 u8 systemId[64]; 1989 u8 reserved[1980]; 1990 }; 1991 1992 enum MR_PD_TYPE { 1993 UNKNOWN_DRIVE = 0, 1994 PARALLEL_SCSI = 1, 1995 SAS_PD = 2, 1996 SATA_PD = 3, 1997 FC_PD = 4, 1998 }; 1999 2000 /* JBOD Queue depth definitions */ 2001 #define MEGASAS_SATA_QD 32 2002 #define MEGASAS_SAS_QD 64 2003 #define MEGASAS_DEFAULT_PD_QD 64 2004 2005 struct megasas_instance { 2006 2007 __le32 *producer; 2008 dma_addr_t producer_h; 2009 __le32 *consumer; 2010 dma_addr_t consumer_h; 2011 struct MR_DRV_SYSTEM_INFO *system_info_buf; 2012 dma_addr_t system_info_h; 2013 struct MR_LD_VF_AFFILIATION *vf_affiliation; 2014 dma_addr_t vf_affiliation_h; 2015 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111; 2016 dma_addr_t vf_affiliation_111_h; 2017 struct MR_CTRL_HB_HOST_MEM *hb_host_mem; 2018 dma_addr_t hb_host_mem_h; 2019 struct MR_PD_INFO *pd_info; 2020 dma_addr_t pd_info_h; 2021 2022 __le32 *reply_queue; 2023 dma_addr_t reply_queue_h; 2024 2025 u32 *crash_dump_buf; 2026 dma_addr_t crash_dump_h; 2027 void *crash_buf[MAX_CRASH_DUMP_SIZE]; 2028 u32 crash_buf_pages; 2029 unsigned int fw_crash_buffer_size; 2030 unsigned int fw_crash_state; 2031 unsigned int fw_crash_buffer_offset; 2032 u32 drv_buf_index; 2033 u32 drv_buf_alloc; 2034 u32 crash_dump_fw_support; 2035 u32 crash_dump_drv_support; 2036 u32 crash_dump_app_support; 2037 u32 secure_jbod_support; 2038 bool use_seqnum_jbod_fp; /* Added for PD sequence */ 2039 spinlock_t crashdump_lock; 2040 2041 struct megasas_register_set __iomem *reg_set; 2042 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; 2043 struct megasas_pd_list pd_list[MEGASAS_MAX_PD]; 2044 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD]; 2045 u8 ld_ids[MEGASAS_MAX_LD_IDS]; 2046 s8 init_id; 2047 2048 u16 max_num_sge; 2049 u16 max_fw_cmds; 2050 u16 max_mfi_cmds; 2051 u16 max_scsi_cmds; 2052 u16 ldio_threshold; 2053 u16 cur_can_queue; 2054 u32 max_sectors_per_req; 2055 struct megasas_aen_event *ev; 2056 2057 struct megasas_cmd **cmd_list; 2058 struct list_head cmd_pool; 2059 /* used to sync fire the cmd to fw */ 2060 spinlock_t mfi_pool_lock; 2061 /* used to sync fire the cmd to fw */ 2062 spinlock_t hba_lock; 2063 /* used to synch producer, consumer ptrs in dpc */ 2064 spinlock_t completion_lock; 2065 struct dma_pool *frame_dma_pool; 2066 struct dma_pool *sense_dma_pool; 2067 2068 struct megasas_evt_detail *evt_detail; 2069 dma_addr_t evt_detail_h; 2070 struct megasas_cmd *aen_cmd; 2071 struct mutex hba_mutex; 2072 struct semaphore ioctl_sem; 2073 2074 struct Scsi_Host *host; 2075 2076 wait_queue_head_t int_cmd_wait_q; 2077 wait_queue_head_t abort_cmd_wait_q; 2078 2079 struct pci_dev *pdev; 2080 u32 unique_id; 2081 u32 fw_support_ieee; 2082 2083 atomic_t fw_outstanding; 2084 atomic_t ldio_outstanding; 2085 atomic_t fw_reset_no_pci_access; 2086 2087 struct megasas_instance_template *instancet; 2088 struct tasklet_struct isr_tasklet; 2089 struct work_struct work_init; 2090 struct work_struct crash_init; 2091 2092 u8 flag; 2093 u8 unload; 2094 u8 flag_ieee; 2095 u8 issuepend_done; 2096 u8 disableOnlineCtrlReset; 2097 u8 UnevenSpanSupport; 2098 2099 u8 supportmax256vd; 2100 u8 pd_list_not_supported; 2101 u16 fw_supported_vd_count; 2102 u16 fw_supported_pd_count; 2103 2104 u16 drv_supported_vd_count; 2105 u16 drv_supported_pd_count; 2106 2107 atomic_t adprecovery; 2108 unsigned long last_time; 2109 u32 mfiStatus; 2110 u32 last_seq_num; 2111 2112 struct list_head internal_reset_pending_q; 2113 2114 /* Ptr to hba specific information */ 2115 void *ctrl_context; 2116 u32 ctrl_context_pages; 2117 struct megasas_ctrl_info *ctrl_info; 2118 unsigned int msix_vectors; 2119 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES]; 2120 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES]; 2121 u64 map_id; 2122 u64 pd_seq_map_id; 2123 struct megasas_cmd *map_update_cmd; 2124 struct megasas_cmd *jbod_seq_cmd; 2125 unsigned long bar; 2126 long reset_flags; 2127 struct mutex reset_mutex; 2128 struct timer_list sriov_heartbeat_timer; 2129 char skip_heartbeat_timer_del; 2130 u8 requestorId; 2131 char PlasmaFW111; 2132 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; 2133 u8 peerIsPresent; 2134 u8 passive; 2135 u16 throttlequeuedepth; 2136 u8 mask_interrupts; 2137 u16 max_chain_frame_sz; 2138 u8 is_imr; 2139 u8 is_rdpq; 2140 bool dev_handle; 2141 }; 2142 struct MR_LD_VF_MAP { 2143 u32 size; 2144 union MR_LD_REF ref; 2145 u8 ldVfCount; 2146 u8 reserved[6]; 2147 u8 policy[1]; 2148 }; 2149 2150 struct MR_LD_VF_AFFILIATION { 2151 u32 size; 2152 u8 ldCount; 2153 u8 vfCount; 2154 u8 thisVf; 2155 u8 reserved[9]; 2156 struct MR_LD_VF_MAP map[1]; 2157 }; 2158 2159 /* Plasma 1.11 FW backward compatibility structures */ 2160 #define IOV_111_OFFSET 0x7CE 2161 #define MAX_VIRTUAL_FUNCTIONS 8 2162 #define MR_LD_ACCESS_HIDDEN 15 2163 2164 struct IOV_111 { 2165 u8 maxVFsSupported; 2166 u8 numVFsEnabled; 2167 u8 requestorId; 2168 u8 reserved[5]; 2169 }; 2170 2171 struct MR_LD_VF_MAP_111 { 2172 u8 targetId; 2173 u8 reserved[3]; 2174 u8 policy[MAX_VIRTUAL_FUNCTIONS]; 2175 }; 2176 2177 struct MR_LD_VF_AFFILIATION_111 { 2178 u8 vdCount; 2179 u8 vfCount; 2180 u8 thisVf; 2181 u8 reserved[5]; 2182 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES]; 2183 }; 2184 2185 struct MR_CTRL_HB_HOST_MEM { 2186 struct { 2187 u32 fwCounter; /* Firmware heart beat counter */ 2188 struct { 2189 u32 debugmode:1; /* 1=Firmware is in debug mode. 2190 Heart beat will not be updated. */ 2191 u32 reserved:31; 2192 } debug; 2193 u32 reserved_fw[6]; 2194 u32 driverCounter; /* Driver heart beat counter. 0x20 */ 2195 u32 reserved_driver[7]; 2196 } HB; 2197 u8 pad[0x400-0x40]; 2198 }; 2199 2200 enum { 2201 MEGASAS_HBA_OPERATIONAL = 0, 2202 MEGASAS_ADPRESET_SM_INFAULT = 1, 2203 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 2204 MEGASAS_ADPRESET_SM_OPERATIONAL = 3, 2205 MEGASAS_HW_CRITICAL_ERROR = 4, 2206 MEGASAS_ADPRESET_SM_POLLING = 5, 2207 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 2208 }; 2209 2210 struct megasas_instance_template { 2211 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \ 2212 u32, struct megasas_register_set __iomem *); 2213 2214 void (*enable_intr)(struct megasas_instance *); 2215 void (*disable_intr)(struct megasas_instance *); 2216 2217 int (*clear_intr)(struct megasas_register_set __iomem *); 2218 2219 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *); 2220 int (*adp_reset)(struct megasas_instance *, \ 2221 struct megasas_register_set __iomem *); 2222 int (*check_reset)(struct megasas_instance *, \ 2223 struct megasas_register_set __iomem *); 2224 irqreturn_t (*service_isr)(int irq, void *devp); 2225 void (*tasklet)(unsigned long); 2226 u32 (*init_adapter)(struct megasas_instance *); 2227 u32 (*build_and_issue_cmd) (struct megasas_instance *, 2228 struct scsi_cmnd *); 2229 int (*issue_dcmd)(struct megasas_instance *instance, 2230 struct megasas_cmd *cmd); 2231 }; 2232 2233 #define MEGASAS_IS_LOGICAL(scp) \ 2234 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1 2235 2236 #define MEGASAS_DEV_INDEX(scp) \ 2237 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 2238 scp->device->id) 2239 2240 #define MEGASAS_PD_INDEX(scp) \ 2241 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \ 2242 scp->device->id) 2243 2244 struct megasas_cmd { 2245 2246 union megasas_frame *frame; 2247 dma_addr_t frame_phys_addr; 2248 u8 *sense; 2249 dma_addr_t sense_phys_addr; 2250 2251 u32 index; 2252 u8 sync_cmd; 2253 u8 cmd_status_drv; 2254 u8 abort_aen; 2255 u8 retry_for_fw_reset; 2256 2257 2258 struct list_head list; 2259 struct scsi_cmnd *scmd; 2260 u8 flags; 2261 2262 struct megasas_instance *instance; 2263 union { 2264 struct { 2265 u16 smid; 2266 u16 resvd; 2267 } context; 2268 u32 frame_count; 2269 }; 2270 }; 2271 2272 #define MAX_MGMT_ADAPTERS 1024 2273 #define MAX_IOCTL_SGE 16 2274 2275 struct megasas_iocpacket { 2276 2277 u16 host_no; 2278 u16 __pad1; 2279 u32 sgl_off; 2280 u32 sge_count; 2281 u32 sense_off; 2282 u32 sense_len; 2283 union { 2284 u8 raw[128]; 2285 struct megasas_header hdr; 2286 } frame; 2287 2288 struct iovec sgl[MAX_IOCTL_SGE]; 2289 2290 } __attribute__ ((packed)); 2291 2292 struct megasas_aen { 2293 u16 host_no; 2294 u16 __pad1; 2295 u32 seq_num; 2296 u32 class_locale_word; 2297 } __attribute__ ((packed)); 2298 2299 #ifdef CONFIG_COMPAT 2300 struct compat_megasas_iocpacket { 2301 u16 host_no; 2302 u16 __pad1; 2303 u32 sgl_off; 2304 u32 sge_count; 2305 u32 sense_off; 2306 u32 sense_len; 2307 union { 2308 u8 raw[128]; 2309 struct megasas_header hdr; 2310 } frame; 2311 struct compat_iovec sgl[MAX_IOCTL_SGE]; 2312 } __attribute__ ((packed)); 2313 2314 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket) 2315 #endif 2316 2317 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket) 2318 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen) 2319 2320 struct megasas_mgmt_info { 2321 2322 u16 count; 2323 struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 2324 int max_index; 2325 }; 2326 2327 enum MEGASAS_OCR_CAUSE { 2328 FW_FAULT_OCR = 0, 2329 SCSIIO_TIMEOUT_OCR = 1, 2330 MFI_IO_TIMEOUT_OCR = 2, 2331 }; 2332 2333 enum DCMD_RETURN_STATUS { 2334 DCMD_SUCCESS = 0, 2335 DCMD_TIMEOUT = 1, 2336 DCMD_FAILED = 2, 2337 DCMD_NOT_FIRED = 3, 2338 }; 2339 2340 u8 2341 MR_BuildRaidContext(struct megasas_instance *instance, 2342 struct IO_REQUEST_INFO *io_info, 2343 struct RAID_CONTEXT *pRAID_Context, 2344 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN); 2345 u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map); 2346 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 2347 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map); 2348 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map); 2349 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map); 2350 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map); 2351 2352 __le16 get_updated_dev_handle(struct megasas_instance *instance, 2353 struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info); 2354 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map, 2355 struct LD_LOAD_BALANCE_INFO *lbInfo); 2356 int megasas_get_ctrl_info(struct megasas_instance *instance); 2357 /* PD sequence */ 2358 int 2359 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend); 2360 int megasas_set_crash_dump_params(struct megasas_instance *instance, 2361 u8 crash_buf_state); 2362 void megasas_free_host_crash_buffer(struct megasas_instance *instance); 2363 void megasas_fusion_crash_dump_wq(struct work_struct *work); 2364 2365 void megasas_return_cmd_fusion(struct megasas_instance *instance, 2366 struct megasas_cmd_fusion *cmd); 2367 int megasas_issue_blocked_cmd(struct megasas_instance *instance, 2368 struct megasas_cmd *cmd, int timeout); 2369 void __megasas_return_cmd(struct megasas_instance *instance, 2370 struct megasas_cmd *cmd); 2371 2372 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance, 2373 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion); 2374 int megasas_cmd_type(struct scsi_cmnd *cmd); 2375 void megasas_setup_jbod_map(struct megasas_instance *instance); 2376 2377 void megasas_update_sdev_properties(struct scsi_device *sdev); 2378 int megasas_reset_fusion(struct Scsi_Host *shost, int reason); 2379 int megasas_task_abort_fusion(struct scsi_cmnd *scmd); 2380 int megasas_reset_target_fusion(struct scsi_cmnd *scmd); 2381 #endif /*LSI_MEGARAID_SAS_H */ 2382