1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2021 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #include <uapi/scsi/fc/fc_fs.h> 24 #include <uapi/scsi/fc/fc_els.h> 25 26 /* Macros to deal with bit fields. Each bit field must have 3 #defines 27 * associated with it (_SHIFT, _MASK, and _WORD). 28 * EG. For a bit field that is in the 7th bit of the "field4" field of a 29 * structure and is 2 bits in size the following #defines must exist: 30 * struct temp { 31 * uint32_t field1; 32 * uint32_t field2; 33 * uint32_t field3; 34 * uint32_t field4; 35 * #define example_bit_field_SHIFT 7 36 * #define example_bit_field_MASK 0x03 37 * #define example_bit_field_WORD field4 38 * uint32_t field5; 39 * }; 40 * Then the macros below may be used to get or set the value of that field. 41 * EG. To get the value of the bit field from the above example: 42 * struct temp t1; 43 * value = bf_get(example_bit_field, &t1); 44 * And then to set that bit field: 45 * bf_set(example_bit_field, &t1, 2); 46 * Or clear that bit field: 47 * bf_set(example_bit_field, &t1, 0); 48 */ 49 #define bf_get_be32(name, ptr) \ 50 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 51 #define bf_get_le32(name, ptr) \ 52 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 53 #define bf_get(name, ptr) \ 54 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 55 #define bf_set_le32(name, ptr, value) \ 56 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 57 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 58 ~(name##_MASK << name##_SHIFT))))) 59 #define bf_set(name, ptr, value) \ 60 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 61 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 62 63 struct dma_address { 64 uint32_t addr_lo; 65 uint32_t addr_hi; 66 }; 67 68 struct lpfc_sli_intf { 69 uint32_t word0; 70 #define lpfc_sli_intf_valid_SHIFT 29 71 #define lpfc_sli_intf_valid_MASK 0x00000007 72 #define lpfc_sli_intf_valid_WORD word0 73 #define LPFC_SLI_INTF_VALID 6 74 #define lpfc_sli_intf_sli_hint2_SHIFT 24 75 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 76 #define lpfc_sli_intf_sli_hint2_WORD word0 77 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 78 #define lpfc_sli_intf_sli_hint1_SHIFT 16 79 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 80 #define lpfc_sli_intf_sli_hint1_WORD word0 81 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 82 #define LPFC_SLI_INTF_SLI_HINT1_1 1 83 #define LPFC_SLI_INTF_SLI_HINT1_2 2 84 #define lpfc_sli_intf_if_type_SHIFT 12 85 #define lpfc_sli_intf_if_type_MASK 0x0000000F 86 #define lpfc_sli_intf_if_type_WORD word0 87 #define LPFC_SLI_INTF_IF_TYPE_0 0 88 #define LPFC_SLI_INTF_IF_TYPE_1 1 89 #define LPFC_SLI_INTF_IF_TYPE_2 2 90 #define LPFC_SLI_INTF_IF_TYPE_6 6 91 #define lpfc_sli_intf_sli_family_SHIFT 8 92 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 93 #define lpfc_sli_intf_sli_family_WORD word0 94 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 95 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 96 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 97 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 98 #define LPFC_SLI_INTF_FAMILY_G6 0xc 99 #define LPFC_SLI_INTF_FAMILY_G7 0xd 100 #define LPFC_SLI_INTF_FAMILY_G7P 0xe 101 #define lpfc_sli_intf_slirev_SHIFT 4 102 #define lpfc_sli_intf_slirev_MASK 0x0000000F 103 #define lpfc_sli_intf_slirev_WORD word0 104 #define LPFC_SLI_INTF_REV_SLI3 3 105 #define LPFC_SLI_INTF_REV_SLI4 4 106 #define lpfc_sli_intf_func_type_SHIFT 0 107 #define lpfc_sli_intf_func_type_MASK 0x00000001 108 #define lpfc_sli_intf_func_type_WORD word0 109 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 110 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 111 }; 112 113 #define LPFC_SLI4_MBX_EMBED true 114 #define LPFC_SLI4_MBX_NEMBED false 115 116 #define LPFC_SLI4_MB_WORD_COUNT 64 117 #define LPFC_MAX_MQ_PAGE 8 118 #define LPFC_MAX_WQ_PAGE_V0 4 119 #define LPFC_MAX_WQ_PAGE 8 120 #define LPFC_MAX_RQ_PAGE 8 121 #define LPFC_MAX_CQ_PAGE 4 122 #define LPFC_MAX_EQ_PAGE 8 123 124 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 125 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 126 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 127 128 /* Define SLI4 Alignment requirements. */ 129 #define LPFC_ALIGN_16_BYTE 16 130 #define LPFC_ALIGN_64_BYTE 64 131 #define SLI4_PAGE_SIZE 4096 132 133 /* Define SLI4 specific definitions. */ 134 #define LPFC_MQ_CQE_BYTE_OFFSET 256 135 #define LPFC_MBX_CMD_HDR_LENGTH 16 136 #define LPFC_MBX_ERROR_RANGE 0x4000 137 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 138 #define LPFC_BMBX_BIT1_ADDR_LO 0 139 #define LPFC_RPI_HDR_COUNT 64 140 #define LPFC_HDR_TEMPLATE_SIZE 4096 141 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 142 #define LPFC_FCF_RECORD_WD_CNT 132 143 #define LPFC_ENTIRE_FCF_DATABASE 0 144 #define LPFC_DFLT_FCF_INDEX 0 145 146 /* Virtual function numbers */ 147 #define LPFC_VF0 0 148 #define LPFC_VF1 1 149 #define LPFC_VF2 2 150 #define LPFC_VF3 3 151 #define LPFC_VF4 4 152 #define LPFC_VF5 5 153 #define LPFC_VF6 6 154 #define LPFC_VF7 7 155 #define LPFC_VF8 8 156 #define LPFC_VF9 9 157 #define LPFC_VF10 10 158 #define LPFC_VF11 11 159 #define LPFC_VF12 12 160 #define LPFC_VF13 13 161 #define LPFC_VF14 14 162 #define LPFC_VF15 15 163 #define LPFC_VF16 16 164 #define LPFC_VF17 17 165 #define LPFC_VF18 18 166 #define LPFC_VF19 19 167 #define LPFC_VF20 20 168 #define LPFC_VF21 21 169 #define LPFC_VF22 22 170 #define LPFC_VF23 23 171 #define LPFC_VF24 24 172 #define LPFC_VF25 25 173 #define LPFC_VF26 26 174 #define LPFC_VF27 27 175 #define LPFC_VF28 28 176 #define LPFC_VF29 29 177 #define LPFC_VF30 30 178 #define LPFC_VF31 31 179 180 /* PCI function numbers */ 181 #define LPFC_PCI_FUNC0 0 182 #define LPFC_PCI_FUNC1 1 183 #define LPFC_PCI_FUNC2 2 184 #define LPFC_PCI_FUNC3 3 185 #define LPFC_PCI_FUNC4 4 186 187 /* SLI4 interface type-2 PDEV_CTL register */ 188 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 189 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 190 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 191 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 192 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 193 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 194 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 195 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 196 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 197 198 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 199 200 /* Active interrupt test count */ 201 #define LPFC_ACT_INTR_CNT 4 202 203 /* Algrithmns for scheduling FCP commands to WQs */ 204 #define LPFC_FCP_SCHED_BY_HDWQ 0 205 #define LPFC_FCP_SCHED_BY_CPU 1 206 207 /* Algrithmns for NameServer Query after RSCN */ 208 #define LPFC_NS_QUERY_GID_FT 0 209 #define LPFC_NS_QUERY_GID_PT 1 210 211 /* Delay Multiplier constant */ 212 #define LPFC_DMULT_CONST 651042 213 #define LPFC_DMULT_MAX 1023 214 215 /* Configuration of Interrupts / sec for entire HBA port */ 216 #define LPFC_MIN_IMAX 5000 217 #define LPFC_MAX_IMAX 5000000 218 #define LPFC_DEF_IMAX 0 219 220 #define LPFC_MAX_AUTO_EQ_DELAY 120 221 #define LPFC_EQ_DELAY_STEP 15 222 #define LPFC_EQD_ISR_TRIGGER 20000 223 /* 1s intervals */ 224 #define LPFC_EQ_DELAY_MSECS 1000 225 226 #define LPFC_MIN_CPU_MAP 0 227 #define LPFC_MAX_CPU_MAP 1 228 #define LPFC_HBA_CPU_MAP 1 229 230 /* PORT_CAPABILITIES constants. */ 231 #define LPFC_MAX_SUPPORTED_PAGES 8 232 233 struct ulp_bde64 { 234 union ULP_BDE_TUS { 235 uint32_t w; 236 struct { 237 #ifdef __BIG_ENDIAN_BITFIELD 238 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 239 VALUE !! */ 240 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 241 #else /* __LITTLE_ENDIAN_BITFIELD */ 242 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 243 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 244 VALUE !! */ 245 #endif 246 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 247 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 248 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 249 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 250 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 251 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 252 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 253 } f; 254 } tus; 255 uint32_t addrLow; 256 uint32_t addrHigh; 257 }; 258 259 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 260 #define LPFC_MAX_BDE_IMM_SIZE 64 261 262 struct lpfc_sli4_flags { 263 uint32_t word0; 264 #define lpfc_idx_rsrc_rdy_SHIFT 0 265 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 266 #define lpfc_idx_rsrc_rdy_WORD word0 267 #define LPFC_IDX_RSRC_RDY 1 268 #define lpfc_rpi_rsrc_rdy_SHIFT 1 269 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 270 #define lpfc_rpi_rsrc_rdy_WORD word0 271 #define LPFC_RPI_RSRC_RDY 1 272 #define lpfc_vpi_rsrc_rdy_SHIFT 2 273 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 274 #define lpfc_vpi_rsrc_rdy_WORD word0 275 #define LPFC_VPI_RSRC_RDY 1 276 #define lpfc_vfi_rsrc_rdy_SHIFT 3 277 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 278 #define lpfc_vfi_rsrc_rdy_WORD word0 279 #define LPFC_VFI_RSRC_RDY 1 280 #define lpfc_ftr_ashdr_SHIFT 4 281 #define lpfc_ftr_ashdr_MASK 0x00000001 282 #define lpfc_ftr_ashdr_WORD word0 283 }; 284 285 struct sli4_bls_rsp { 286 uint32_t word0_rsvd; /* Word0 must be reserved */ 287 uint32_t word1; 288 #define lpfc_abts_orig_SHIFT 0 289 #define lpfc_abts_orig_MASK 0x00000001 290 #define lpfc_abts_orig_WORD word1 291 #define LPFC_ABTS_UNSOL_RSP 1 292 #define LPFC_ABTS_UNSOL_INT 0 293 uint32_t word2; 294 #define lpfc_abts_rxid_SHIFT 0 295 #define lpfc_abts_rxid_MASK 0x0000FFFF 296 #define lpfc_abts_rxid_WORD word2 297 #define lpfc_abts_oxid_SHIFT 16 298 #define lpfc_abts_oxid_MASK 0x0000FFFF 299 #define lpfc_abts_oxid_WORD word2 300 uint32_t word3; 301 #define lpfc_vndr_code_SHIFT 0 302 #define lpfc_vndr_code_MASK 0x000000FF 303 #define lpfc_vndr_code_WORD word3 304 #define lpfc_rsn_expln_SHIFT 8 305 #define lpfc_rsn_expln_MASK 0x000000FF 306 #define lpfc_rsn_expln_WORD word3 307 #define lpfc_rsn_code_SHIFT 16 308 #define lpfc_rsn_code_MASK 0x000000FF 309 #define lpfc_rsn_code_WORD word3 310 311 uint32_t word4; 312 uint32_t word5_rsvd; /* Word5 must be reserved */ 313 }; 314 315 /* event queue entry structure */ 316 struct lpfc_eqe { 317 uint32_t word0; 318 #define lpfc_eqe_resource_id_SHIFT 16 319 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 320 #define lpfc_eqe_resource_id_WORD word0 321 #define lpfc_eqe_minor_code_SHIFT 4 322 #define lpfc_eqe_minor_code_MASK 0x00000FFF 323 #define lpfc_eqe_minor_code_WORD word0 324 #define lpfc_eqe_major_code_SHIFT 1 325 #define lpfc_eqe_major_code_MASK 0x00000007 326 #define lpfc_eqe_major_code_WORD word0 327 #define lpfc_eqe_valid_SHIFT 0 328 #define lpfc_eqe_valid_MASK 0x00000001 329 #define lpfc_eqe_valid_WORD word0 330 }; 331 332 /* completion queue entry structure (common fields for all cqe types) */ 333 struct lpfc_cqe { 334 uint32_t reserved0; 335 uint32_t reserved1; 336 uint32_t reserved2; 337 uint32_t word3; 338 #define lpfc_cqe_valid_SHIFT 31 339 #define lpfc_cqe_valid_MASK 0x00000001 340 #define lpfc_cqe_valid_WORD word3 341 #define lpfc_cqe_code_SHIFT 16 342 #define lpfc_cqe_code_MASK 0x000000FF 343 #define lpfc_cqe_code_WORD word3 344 }; 345 346 /* Completion Queue Entry Status Codes */ 347 #define CQE_STATUS_SUCCESS 0x0 348 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 349 #define CQE_STATUS_REMOTE_STOP 0x2 350 #define CQE_STATUS_LOCAL_REJECT 0x3 351 #define CQE_STATUS_NPORT_RJT 0x4 352 #define CQE_STATUS_FABRIC_RJT 0x5 353 #define CQE_STATUS_NPORT_BSY 0x6 354 #define CQE_STATUS_FABRIC_BSY 0x7 355 #define CQE_STATUS_INTERMED_RSP 0x8 356 #define CQE_STATUS_LS_RJT 0x9 357 #define CQE_STATUS_CMD_REJECT 0xb 358 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 359 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 360 #define CQE_STATUS_DI_ERROR 0x16 361 362 /* Used when mapping CQE status to IOCB */ 363 #define LPFC_IOCB_STATUS_MASK 0xf 364 365 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 366 #define CQE_HW_STATUS_NO_ERR 0x0 367 #define CQE_HW_STATUS_UNDERRUN 0x1 368 #define CQE_HW_STATUS_OVERRUN 0x2 369 370 /* Completion Queue Entry Codes */ 371 #define CQE_CODE_COMPL_WQE 0x1 372 #define CQE_CODE_RELEASE_WQE 0x2 373 #define CQE_CODE_RECEIVE 0x4 374 #define CQE_CODE_XRI_ABORTED 0x5 375 #define CQE_CODE_RECEIVE_V1 0x9 376 #define CQE_CODE_NVME_ERSP 0xd 377 378 /* 379 * Define mask value for xri_aborted and wcqe completed CQE extended status. 380 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 381 */ 382 #define WCQE_PARAM_MASK 0x1FF 383 384 /* completion queue entry for wqe completions */ 385 struct lpfc_wcqe_complete { 386 uint32_t word0; 387 #define lpfc_wcqe_c_request_tag_SHIFT 16 388 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 389 #define lpfc_wcqe_c_request_tag_WORD word0 390 #define lpfc_wcqe_c_status_SHIFT 8 391 #define lpfc_wcqe_c_status_MASK 0x000000FF 392 #define lpfc_wcqe_c_status_WORD word0 393 #define lpfc_wcqe_c_hw_status_SHIFT 0 394 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 395 #define lpfc_wcqe_c_hw_status_WORD word0 396 #define lpfc_wcqe_c_ersp0_SHIFT 0 397 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 398 #define lpfc_wcqe_c_ersp0_WORD word0 399 uint32_t total_data_placed; 400 #define lpfc_wcqe_c_cmf_cg_SHIFT 31 401 #define lpfc_wcqe_c_cmf_cg_MASK 0x00000001 402 #define lpfc_wcqe_c_cmf_cg_WORD total_data_placed 403 #define lpfc_wcqe_c_cmf_bw_SHIFT 0 404 #define lpfc_wcqe_c_cmf_bw_MASK 0x0FFFFFFF 405 #define lpfc_wcqe_c_cmf_bw_WORD total_data_placed 406 uint32_t parameter; 407 #define lpfc_wcqe_c_bg_edir_SHIFT 5 408 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 409 #define lpfc_wcqe_c_bg_edir_WORD parameter 410 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 411 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 412 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 413 #define lpfc_wcqe_c_bg_re_SHIFT 2 414 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 415 #define lpfc_wcqe_c_bg_re_WORD parameter 416 #define lpfc_wcqe_c_bg_ae_SHIFT 1 417 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 418 #define lpfc_wcqe_c_bg_ae_WORD parameter 419 #define lpfc_wcqe_c_bg_ge_SHIFT 0 420 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 421 #define lpfc_wcqe_c_bg_ge_WORD parameter 422 uint32_t word3; 423 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 424 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 425 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 426 #define lpfc_wcqe_c_xb_SHIFT 28 427 #define lpfc_wcqe_c_xb_MASK 0x00000001 428 #define lpfc_wcqe_c_xb_WORD word3 429 #define lpfc_wcqe_c_pv_SHIFT 27 430 #define lpfc_wcqe_c_pv_MASK 0x00000001 431 #define lpfc_wcqe_c_pv_WORD word3 432 #define lpfc_wcqe_c_priority_SHIFT 24 433 #define lpfc_wcqe_c_priority_MASK 0x00000007 434 #define lpfc_wcqe_c_priority_WORD word3 435 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 436 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 437 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 438 #define lpfc_wcqe_c_sqhead_SHIFT 0 439 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 440 #define lpfc_wcqe_c_sqhead_WORD word3 441 }; 442 443 /* completion queue entry for wqe release */ 444 struct lpfc_wcqe_release { 445 uint32_t reserved0; 446 uint32_t reserved1; 447 uint32_t word2; 448 #define lpfc_wcqe_r_wq_id_SHIFT 16 449 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 450 #define lpfc_wcqe_r_wq_id_WORD word2 451 #define lpfc_wcqe_r_wqe_index_SHIFT 0 452 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 453 #define lpfc_wcqe_r_wqe_index_WORD word2 454 uint32_t word3; 455 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 456 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 457 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 458 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 459 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 460 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 461 }; 462 463 struct sli4_wcqe_xri_aborted { 464 uint32_t word0; 465 #define lpfc_wcqe_xa_status_SHIFT 8 466 #define lpfc_wcqe_xa_status_MASK 0x000000FF 467 #define lpfc_wcqe_xa_status_WORD word0 468 uint32_t parameter; 469 uint32_t word2; 470 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 471 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 472 #define lpfc_wcqe_xa_remote_xid_WORD word2 473 #define lpfc_wcqe_xa_xri_SHIFT 0 474 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 475 #define lpfc_wcqe_xa_xri_WORD word2 476 uint32_t word3; 477 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 478 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 479 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 480 #define lpfc_wcqe_xa_ia_SHIFT 30 481 #define lpfc_wcqe_xa_ia_MASK 0x00000001 482 #define lpfc_wcqe_xa_ia_WORD word3 483 #define CQE_XRI_ABORTED_IA_REMOTE 0 484 #define CQE_XRI_ABORTED_IA_LOCAL 1 485 #define lpfc_wcqe_xa_br_SHIFT 29 486 #define lpfc_wcqe_xa_br_MASK 0x00000001 487 #define lpfc_wcqe_xa_br_WORD word3 488 #define CQE_XRI_ABORTED_BR_BA_ACC 0 489 #define CQE_XRI_ABORTED_BR_BA_RJT 1 490 #define lpfc_wcqe_xa_eo_SHIFT 28 491 #define lpfc_wcqe_xa_eo_MASK 0x00000001 492 #define lpfc_wcqe_xa_eo_WORD word3 493 #define CQE_XRI_ABORTED_EO_REMOTE 0 494 #define CQE_XRI_ABORTED_EO_LOCAL 1 495 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 496 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 497 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 498 }; 499 500 /* completion queue entry structure for rqe completion */ 501 struct lpfc_rcqe { 502 uint32_t word0; 503 #define lpfc_rcqe_bindex_SHIFT 16 504 #define lpfc_rcqe_bindex_MASK 0x0000FFF 505 #define lpfc_rcqe_bindex_WORD word0 506 #define lpfc_rcqe_status_SHIFT 8 507 #define lpfc_rcqe_status_MASK 0x000000FF 508 #define lpfc_rcqe_status_WORD word0 509 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 510 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 511 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 512 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 513 uint32_t word1; 514 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 515 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 516 #define lpfc_rcqe_fcf_id_v1_WORD word1 517 uint32_t word2; 518 #define lpfc_rcqe_length_SHIFT 16 519 #define lpfc_rcqe_length_MASK 0x0000FFFF 520 #define lpfc_rcqe_length_WORD word2 521 #define lpfc_rcqe_rq_id_SHIFT 6 522 #define lpfc_rcqe_rq_id_MASK 0x000003FF 523 #define lpfc_rcqe_rq_id_WORD word2 524 #define lpfc_rcqe_fcf_id_SHIFT 0 525 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 526 #define lpfc_rcqe_fcf_id_WORD word2 527 #define lpfc_rcqe_rq_id_v1_SHIFT 0 528 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 529 #define lpfc_rcqe_rq_id_v1_WORD word2 530 uint32_t word3; 531 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 532 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 533 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 534 #define lpfc_rcqe_port_SHIFT 30 535 #define lpfc_rcqe_port_MASK 0x00000001 536 #define lpfc_rcqe_port_WORD word3 537 #define lpfc_rcqe_hdr_length_SHIFT 24 538 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 539 #define lpfc_rcqe_hdr_length_WORD word3 540 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 541 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 542 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 543 #define lpfc_rcqe_eof_SHIFT 8 544 #define lpfc_rcqe_eof_MASK 0x000000FF 545 #define lpfc_rcqe_eof_WORD word3 546 #define FCOE_EOFn 0x41 547 #define FCOE_EOFt 0x42 548 #define FCOE_EOFni 0x49 549 #define FCOE_EOFa 0x50 550 #define lpfc_rcqe_sof_SHIFT 0 551 #define lpfc_rcqe_sof_MASK 0x000000FF 552 #define lpfc_rcqe_sof_WORD word3 553 #define FCOE_SOFi2 0x2d 554 #define FCOE_SOFi3 0x2e 555 #define FCOE_SOFn2 0x35 556 #define FCOE_SOFn3 0x36 557 }; 558 559 struct lpfc_rqe { 560 uint32_t address_hi; 561 uint32_t address_lo; 562 }; 563 564 /* buffer descriptors */ 565 struct lpfc_bde4 { 566 uint32_t addr_hi; 567 uint32_t addr_lo; 568 uint32_t word2; 569 #define lpfc_bde4_last_SHIFT 31 570 #define lpfc_bde4_last_MASK 0x00000001 571 #define lpfc_bde4_last_WORD word2 572 #define lpfc_bde4_sge_offset_SHIFT 0 573 #define lpfc_bde4_sge_offset_MASK 0x000003FF 574 #define lpfc_bde4_sge_offset_WORD word2 575 uint32_t word3; 576 #define lpfc_bde4_length_SHIFT 0 577 #define lpfc_bde4_length_MASK 0x000000FF 578 #define lpfc_bde4_length_WORD word3 579 }; 580 581 struct lpfc_register { 582 uint32_t word0; 583 }; 584 585 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 586 #define LPFC_PORT_SEM_MASK 0xF000 587 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 588 #define LPFC_UERR_STATUS_HI 0x00A4 589 #define LPFC_UERR_STATUS_LO 0x00A0 590 #define LPFC_UE_MASK_HI 0x00AC 591 #define LPFC_UE_MASK_LO 0x00A8 592 593 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 594 #define LPFC_SLI_INTF 0x0058 595 #define LPFC_SLI_ASIC_VER 0x009C 596 597 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 598 #define lpfc_port_smphr_perr_SHIFT 31 599 #define lpfc_port_smphr_perr_MASK 0x1 600 #define lpfc_port_smphr_perr_WORD word0 601 #define lpfc_port_smphr_sfi_SHIFT 30 602 #define lpfc_port_smphr_sfi_MASK 0x1 603 #define lpfc_port_smphr_sfi_WORD word0 604 #define lpfc_port_smphr_nip_SHIFT 29 605 #define lpfc_port_smphr_nip_MASK 0x1 606 #define lpfc_port_smphr_nip_WORD word0 607 #define lpfc_port_smphr_ipc_SHIFT 28 608 #define lpfc_port_smphr_ipc_MASK 0x1 609 #define lpfc_port_smphr_ipc_WORD word0 610 #define lpfc_port_smphr_scr1_SHIFT 27 611 #define lpfc_port_smphr_scr1_MASK 0x1 612 #define lpfc_port_smphr_scr1_WORD word0 613 #define lpfc_port_smphr_scr2_SHIFT 26 614 #define lpfc_port_smphr_scr2_MASK 0x1 615 #define lpfc_port_smphr_scr2_WORD word0 616 #define lpfc_port_smphr_host_scratch_SHIFT 16 617 #define lpfc_port_smphr_host_scratch_MASK 0xFF 618 #define lpfc_port_smphr_host_scratch_WORD word0 619 #define lpfc_port_smphr_port_status_SHIFT 0 620 #define lpfc_port_smphr_port_status_MASK 0xFFFF 621 #define lpfc_port_smphr_port_status_WORD word0 622 623 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 624 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 625 #define LPFC_POST_STAGE_HOST_RDY 0x0002 626 #define LPFC_POST_STAGE_BE_RESET 0x0003 627 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 628 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 629 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 630 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 631 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 632 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 633 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 634 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 635 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 636 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 637 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 638 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 639 #define LPFC_POST_STAGE_ARMFW_START 0x0800 640 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 641 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 642 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 643 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 644 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 645 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 646 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 647 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 648 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 649 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 650 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 651 #define LPFC_POST_STAGE_RC_DONE 0x0B07 652 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 653 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 654 #define LPFC_POST_STAGE_PORT_READY 0xC000 655 #define LPFC_POST_STAGE_PORT_UE 0xF000 656 657 #define LPFC_CTL_PORT_STA_OFFSET 0x404 658 #define lpfc_sliport_status_err_SHIFT 31 659 #define lpfc_sliport_status_err_MASK 0x1 660 #define lpfc_sliport_status_err_WORD word0 661 #define lpfc_sliport_status_end_SHIFT 30 662 #define lpfc_sliport_status_end_MASK 0x1 663 #define lpfc_sliport_status_end_WORD word0 664 #define lpfc_sliport_status_oti_SHIFT 29 665 #define lpfc_sliport_status_oti_MASK 0x1 666 #define lpfc_sliport_status_oti_WORD word0 667 #define lpfc_sliport_status_dip_SHIFT 25 668 #define lpfc_sliport_status_dip_MASK 0x1 669 #define lpfc_sliport_status_dip_WORD word0 670 #define lpfc_sliport_status_rn_SHIFT 24 671 #define lpfc_sliport_status_rn_MASK 0x1 672 #define lpfc_sliport_status_rn_WORD word0 673 #define lpfc_sliport_status_rdy_SHIFT 23 674 #define lpfc_sliport_status_rdy_MASK 0x1 675 #define lpfc_sliport_status_rdy_WORD word0 676 #define lpfc_sliport_status_pldv_SHIFT 0 677 #define lpfc_sliport_status_pldv_MASK 0x1 678 #define lpfc_sliport_status_pldv_WORD word0 679 #define CFG_PLD 0x3C 680 #define MAX_IF_TYPE_2_RESETS 6 681 682 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 683 #define lpfc_sliport_ctrl_end_SHIFT 30 684 #define lpfc_sliport_ctrl_end_MASK 0x1 685 #define lpfc_sliport_ctrl_end_WORD word0 686 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 687 #define LPFC_SLIPORT_BIG_ENDIAN 1 688 #define lpfc_sliport_ctrl_ip_SHIFT 27 689 #define lpfc_sliport_ctrl_ip_MASK 0x1 690 #define lpfc_sliport_ctrl_ip_WORD word0 691 #define LPFC_SLIPORT_INIT_PORT 1 692 693 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 694 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 695 696 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 697 #define lpfc_sliport_eqdelay_delay_SHIFT 16 698 #define lpfc_sliport_eqdelay_delay_MASK 0xffff 699 #define lpfc_sliport_eqdelay_delay_WORD word0 700 #define lpfc_sliport_eqdelay_id_SHIFT 0 701 #define lpfc_sliport_eqdelay_id_MASK 0xfff 702 #define lpfc_sliport_eqdelay_id_WORD word0 703 #define LPFC_SEC_TO_USEC 1000000 704 #define LPFC_SEC_TO_MSEC 1000 705 706 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 707 * reside in BAR 2. 708 */ 709 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 710 711 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 712 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 713 714 #define LPFC_HST_ISR0 0x0C18 715 #define LPFC_HST_ISR1 0x0C1C 716 #define LPFC_HST_ISR2 0x0C20 717 #define LPFC_HST_ISR3 0x0C24 718 #define LPFC_HST_ISR4 0x0C28 719 720 #define LPFC_HST_IMR0 0x0C48 721 #define LPFC_HST_IMR1 0x0C4C 722 #define LPFC_HST_IMR2 0x0C50 723 #define LPFC_HST_IMR3 0x0C54 724 #define LPFC_HST_IMR4 0x0C58 725 726 #define LPFC_HST_ISCR0 0x0C78 727 #define LPFC_HST_ISCR1 0x0C7C 728 #define LPFC_HST_ISCR2 0x0C80 729 #define LPFC_HST_ISCR3 0x0C84 730 #define LPFC_HST_ISCR4 0x0C88 731 732 #define LPFC_SLI4_INTR0 BIT0 733 #define LPFC_SLI4_INTR1 BIT1 734 #define LPFC_SLI4_INTR2 BIT2 735 #define LPFC_SLI4_INTR3 BIT3 736 #define LPFC_SLI4_INTR4 BIT4 737 #define LPFC_SLI4_INTR5 BIT5 738 #define LPFC_SLI4_INTR6 BIT6 739 #define LPFC_SLI4_INTR7 BIT7 740 #define LPFC_SLI4_INTR8 BIT8 741 #define LPFC_SLI4_INTR9 BIT9 742 #define LPFC_SLI4_INTR10 BIT10 743 #define LPFC_SLI4_INTR11 BIT11 744 #define LPFC_SLI4_INTR12 BIT12 745 #define LPFC_SLI4_INTR13 BIT13 746 #define LPFC_SLI4_INTR14 BIT14 747 #define LPFC_SLI4_INTR15 BIT15 748 #define LPFC_SLI4_INTR16 BIT16 749 #define LPFC_SLI4_INTR17 BIT17 750 #define LPFC_SLI4_INTR18 BIT18 751 #define LPFC_SLI4_INTR19 BIT19 752 #define LPFC_SLI4_INTR20 BIT20 753 #define LPFC_SLI4_INTR21 BIT21 754 #define LPFC_SLI4_INTR22 BIT22 755 #define LPFC_SLI4_INTR23 BIT23 756 #define LPFC_SLI4_INTR24 BIT24 757 #define LPFC_SLI4_INTR25 BIT25 758 #define LPFC_SLI4_INTR26 BIT26 759 #define LPFC_SLI4_INTR27 BIT27 760 #define LPFC_SLI4_INTR28 BIT28 761 #define LPFC_SLI4_INTR29 BIT29 762 #define LPFC_SLI4_INTR30 BIT30 763 #define LPFC_SLI4_INTR31 BIT31 764 765 /* 766 * The Doorbell registers defined here exist in different BAR 767 * register sets depending on the UCNA Port's reported if_type 768 * value. For UCNA ports running SLI4 and if_type 0, they reside in 769 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 770 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 771 * BAR2. The offsets and base address are different, so the driver 772 * has to compute the register addresses accordingly 773 */ 774 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 775 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 776 #define LPFC_IF6_RQ_DOORBELL 0x0080 777 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 778 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 779 #define lpfc_rq_db_list_fm_num_posted_WORD word0 780 #define lpfc_rq_db_list_fm_index_SHIFT 16 781 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 782 #define lpfc_rq_db_list_fm_index_WORD word0 783 #define lpfc_rq_db_list_fm_id_SHIFT 0 784 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 785 #define lpfc_rq_db_list_fm_id_WORD word0 786 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 787 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 788 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 789 #define lpfc_rq_db_ring_fm_id_SHIFT 0 790 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 791 #define lpfc_rq_db_ring_fm_id_WORD word0 792 793 #define LPFC_ULP0_WQ_DOORBELL 0x0040 794 #define LPFC_ULP1_WQ_DOORBELL 0x0060 795 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 796 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 797 #define lpfc_wq_db_list_fm_num_posted_WORD word0 798 #define lpfc_wq_db_list_fm_index_SHIFT 16 799 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 800 #define lpfc_wq_db_list_fm_index_WORD word0 801 #define lpfc_wq_db_list_fm_id_SHIFT 0 802 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 803 #define lpfc_wq_db_list_fm_id_WORD word0 804 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 805 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 806 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 807 #define lpfc_wq_db_ring_fm_id_SHIFT 0 808 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 809 #define lpfc_wq_db_ring_fm_id_WORD word0 810 811 #define LPFC_IF6_WQ_DOORBELL 0x0040 812 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 813 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 814 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 815 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 816 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 817 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0 818 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 819 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 820 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 821 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0 822 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 823 #define lpfc_if6_wq_db_list_fm_id_WORD word0 824 825 #define LPFC_EQCQ_DOORBELL 0x0120 826 #define lpfc_eqcq_doorbell_se_SHIFT 31 827 #define lpfc_eqcq_doorbell_se_MASK 0x0001 828 #define lpfc_eqcq_doorbell_se_WORD word0 829 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 830 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 831 #define lpfc_eqcq_doorbell_arm_SHIFT 29 832 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 833 #define lpfc_eqcq_doorbell_arm_WORD word0 834 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 835 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 836 #define lpfc_eqcq_doorbell_num_released_WORD word0 837 #define lpfc_eqcq_doorbell_qt_SHIFT 10 838 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 839 #define lpfc_eqcq_doorbell_qt_WORD word0 840 #define LPFC_QUEUE_TYPE_COMPLETION 0 841 #define LPFC_QUEUE_TYPE_EVENT 1 842 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 843 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 844 #define lpfc_eqcq_doorbell_eqci_WORD word0 845 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 846 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 847 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 848 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 849 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 850 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 851 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 852 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 853 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 854 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 855 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 856 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 857 #define LPFC_CQID_HI_FIELD_SHIFT 10 858 #define LPFC_EQID_HI_FIELD_SHIFT 9 859 860 #define LPFC_IF6_CQ_DOORBELL 0x00C0 861 #define lpfc_if6_cq_doorbell_se_SHIFT 31 862 #define lpfc_if6_cq_doorbell_se_MASK 0x0001 863 #define lpfc_if6_cq_doorbell_se_WORD word0 864 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 865 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 866 #define lpfc_if6_cq_doorbell_arm_SHIFT 29 867 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001 868 #define lpfc_if6_cq_doorbell_arm_WORD word0 869 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16 870 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 871 #define lpfc_if6_cq_doorbell_num_released_WORD word0 872 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0 873 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 874 #define lpfc_if6_cq_doorbell_cqid_WORD word0 875 876 #define LPFC_IF6_EQ_DOORBELL 0x0120 877 #define lpfc_if6_eq_doorbell_io_SHIFT 31 878 #define lpfc_if6_eq_doorbell_io_MASK 0x0001 879 #define lpfc_if6_eq_doorbell_io_WORD word0 880 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 881 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 882 #define lpfc_if6_eq_doorbell_arm_SHIFT 29 883 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001 884 #define lpfc_if6_eq_doorbell_arm_WORD word0 885 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16 886 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 887 #define lpfc_if6_eq_doorbell_num_released_WORD word0 888 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0 889 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 890 #define lpfc_if6_eq_doorbell_eqid_WORD word0 891 892 #define LPFC_BMBX 0x0160 893 #define lpfc_bmbx_addr_SHIFT 2 894 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 895 #define lpfc_bmbx_addr_WORD word0 896 #define lpfc_bmbx_hi_SHIFT 1 897 #define lpfc_bmbx_hi_MASK 0x0001 898 #define lpfc_bmbx_hi_WORD word0 899 #define lpfc_bmbx_rdy_SHIFT 0 900 #define lpfc_bmbx_rdy_MASK 0x0001 901 #define lpfc_bmbx_rdy_WORD word0 902 903 #define LPFC_MQ_DOORBELL 0x0140 904 #define LPFC_IF6_MQ_DOORBELL 0x0160 905 #define lpfc_mq_doorbell_num_posted_SHIFT 16 906 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 907 #define lpfc_mq_doorbell_num_posted_WORD word0 908 #define lpfc_mq_doorbell_id_SHIFT 0 909 #define lpfc_mq_doorbell_id_MASK 0xFFFF 910 #define lpfc_mq_doorbell_id_WORD word0 911 912 struct lpfc_sli4_cfg_mhdr { 913 uint32_t word1; 914 #define lpfc_mbox_hdr_emb_SHIFT 0 915 #define lpfc_mbox_hdr_emb_MASK 0x00000001 916 #define lpfc_mbox_hdr_emb_WORD word1 917 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 918 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 919 #define lpfc_mbox_hdr_sge_cnt_WORD word1 920 uint32_t payload_length; 921 uint32_t tag_lo; 922 uint32_t tag_hi; 923 uint32_t reserved5; 924 }; 925 926 union lpfc_sli4_cfg_shdr { 927 struct { 928 uint32_t word6; 929 #define lpfc_mbox_hdr_opcode_SHIFT 0 930 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 931 #define lpfc_mbox_hdr_opcode_WORD word6 932 #define lpfc_mbox_hdr_subsystem_SHIFT 8 933 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 934 #define lpfc_mbox_hdr_subsystem_WORD word6 935 #define lpfc_mbox_hdr_port_number_SHIFT 16 936 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 937 #define lpfc_mbox_hdr_port_number_WORD word6 938 #define lpfc_mbox_hdr_domain_SHIFT 24 939 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 940 #define lpfc_mbox_hdr_domain_WORD word6 941 uint32_t timeout; 942 uint32_t request_length; 943 uint32_t word9; 944 #define lpfc_mbox_hdr_version_SHIFT 0 945 #define lpfc_mbox_hdr_version_MASK 0x000000FF 946 #define lpfc_mbox_hdr_version_WORD word9 947 #define lpfc_mbox_hdr_pf_num_SHIFT 16 948 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 949 #define lpfc_mbox_hdr_pf_num_WORD word9 950 #define lpfc_mbox_hdr_vh_num_SHIFT 24 951 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 952 #define lpfc_mbox_hdr_vh_num_WORD word9 953 #define LPFC_Q_CREATE_VERSION_2 2 954 #define LPFC_Q_CREATE_VERSION_1 1 955 #define LPFC_Q_CREATE_VERSION_0 0 956 #define LPFC_OPCODE_VERSION_0 0 957 #define LPFC_OPCODE_VERSION_1 1 958 } request; 959 struct { 960 uint32_t word6; 961 #define lpfc_mbox_hdr_opcode_SHIFT 0 962 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 963 #define lpfc_mbox_hdr_opcode_WORD word6 964 #define lpfc_mbox_hdr_subsystem_SHIFT 8 965 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 966 #define lpfc_mbox_hdr_subsystem_WORD word6 967 #define lpfc_mbox_hdr_domain_SHIFT 24 968 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 969 #define lpfc_mbox_hdr_domain_WORD word6 970 uint32_t word7; 971 #define lpfc_mbox_hdr_status_SHIFT 0 972 #define lpfc_mbox_hdr_status_MASK 0x000000FF 973 #define lpfc_mbox_hdr_status_WORD word7 974 #define lpfc_mbox_hdr_add_status_SHIFT 8 975 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 976 #define lpfc_mbox_hdr_add_status_WORD word7 977 #define LPFC_ADD_STATUS_INCOMPAT_OBJ 0xA2 978 #define lpfc_mbox_hdr_add_status_2_SHIFT 16 979 #define lpfc_mbox_hdr_add_status_2_MASK 0x000000FF 980 #define lpfc_mbox_hdr_add_status_2_WORD word7 981 #define LPFC_ADD_STATUS_2_INCOMPAT_FLASH 0x01 982 #define LPFC_ADD_STATUS_2_INCORRECT_ASIC 0x02 983 uint32_t response_length; 984 uint32_t actual_response_length; 985 } response; 986 }; 987 988 /* Mailbox Header structures. 989 * struct mbox_header is defined for first generation SLI4_CFG mailbox 990 * calls deployed for BE-based ports. 991 * 992 * struct sli4_mbox_header is defined for second generation SLI4 993 * ports that don't deploy the SLI4_CFG mechanism. 994 */ 995 struct mbox_header { 996 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 997 union lpfc_sli4_cfg_shdr cfg_shdr; 998 }; 999 1000 #define LPFC_EXTENT_LOCAL 0 1001 #define LPFC_TIMEOUT_DEFAULT 0 1002 #define LPFC_EXTENT_VERSION_DEFAULT 0 1003 1004 /* Subsystem Definitions */ 1005 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 1006 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 1007 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 1008 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 1009 1010 /* Device Specific Definitions */ 1011 1012 /* The HOST ENDIAN defines are in Big Endian format. */ 1013 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 1014 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 1015 1016 /* Common Opcodes */ 1017 #define LPFC_MBOX_OPCODE_NA 0x00 1018 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 1019 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 1020 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 1021 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 1022 #define LPFC_MBOX_OPCODE_NOP 0x21 1023 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 1024 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 1025 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 1026 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 1027 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 1028 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 1029 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 1030 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 1031 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 1032 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 1033 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 1034 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 1035 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 1036 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 1037 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 1038 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1039 #define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF 0x8E 1040 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1041 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1042 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1043 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1044 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1045 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1046 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1047 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1048 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1049 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1050 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1051 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1052 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1053 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1054 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1055 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1056 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1057 1058 /* FCoE Opcodes */ 1059 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1060 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1061 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1062 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1063 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1064 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1065 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1066 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1067 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1068 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1069 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1070 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1071 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1072 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1073 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1074 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42 1075 1076 /* Low level Opcodes */ 1077 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1078 1079 /* Mailbox command structures */ 1080 struct eq_context { 1081 uint32_t word0; 1082 #define lpfc_eq_context_size_SHIFT 31 1083 #define lpfc_eq_context_size_MASK 0x00000001 1084 #define lpfc_eq_context_size_WORD word0 1085 #define LPFC_EQE_SIZE_4 0x0 1086 #define LPFC_EQE_SIZE_16 0x1 1087 #define lpfc_eq_context_valid_SHIFT 29 1088 #define lpfc_eq_context_valid_MASK 0x00000001 1089 #define lpfc_eq_context_valid_WORD word0 1090 #define lpfc_eq_context_autovalid_SHIFT 28 1091 #define lpfc_eq_context_autovalid_MASK 0x00000001 1092 #define lpfc_eq_context_autovalid_WORD word0 1093 uint32_t word1; 1094 #define lpfc_eq_context_count_SHIFT 26 1095 #define lpfc_eq_context_count_MASK 0x00000003 1096 #define lpfc_eq_context_count_WORD word1 1097 #define LPFC_EQ_CNT_256 0x0 1098 #define LPFC_EQ_CNT_512 0x1 1099 #define LPFC_EQ_CNT_1024 0x2 1100 #define LPFC_EQ_CNT_2048 0x3 1101 #define LPFC_EQ_CNT_4096 0x4 1102 uint32_t word2; 1103 #define lpfc_eq_context_delay_multi_SHIFT 13 1104 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 1105 #define lpfc_eq_context_delay_multi_WORD word2 1106 uint32_t reserved3; 1107 }; 1108 1109 struct eq_delay_info { 1110 uint32_t eq_id; 1111 uint32_t phase; 1112 uint32_t delay_multi; 1113 }; 1114 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1115 1116 struct sgl_page_pairs { 1117 uint32_t sgl_pg0_addr_lo; 1118 uint32_t sgl_pg0_addr_hi; 1119 uint32_t sgl_pg1_addr_lo; 1120 uint32_t sgl_pg1_addr_hi; 1121 }; 1122 1123 struct lpfc_mbx_post_sgl_pages { 1124 struct mbox_header header; 1125 uint32_t word0; 1126 #define lpfc_post_sgl_pages_xri_SHIFT 0 1127 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1128 #define lpfc_post_sgl_pages_xri_WORD word0 1129 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1130 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1131 #define lpfc_post_sgl_pages_xricnt_WORD word0 1132 struct sgl_page_pairs sgl_pg_pairs[1]; 1133 }; 1134 1135 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1136 struct lpfc_mbx_post_uembed_sgl_page1 { 1137 union lpfc_sli4_cfg_shdr cfg_shdr; 1138 uint32_t word0; 1139 struct sgl_page_pairs sgl_pg_pairs; 1140 }; 1141 1142 struct lpfc_mbx_sge { 1143 uint32_t pa_lo; 1144 uint32_t pa_hi; 1145 uint32_t length; 1146 }; 1147 1148 struct lpfc_mbx_host_buf { 1149 uint32_t length; 1150 uint32_t pa_lo; 1151 uint32_t pa_hi; 1152 }; 1153 1154 struct lpfc_mbx_nembed_cmd { 1155 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1156 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1157 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1158 }; 1159 1160 struct lpfc_mbx_nembed_sge_virt { 1161 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1162 }; 1163 1164 #define LPFC_MBX_OBJECT_NAME_LEN_DW 26 1165 struct lpfc_mbx_read_object { /* Version 0 */ 1166 struct mbox_header header; 1167 union { 1168 struct { 1169 uint32_t word0; 1170 #define lpfc_mbx_rd_object_rlen_SHIFT 0 1171 #define lpfc_mbx_rd_object_rlen_MASK 0x00FFFFFF 1172 #define lpfc_mbx_rd_object_rlen_WORD word0 1173 uint32_t rd_object_offset; 1174 __le32 rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW]; 1175 #define LPFC_OBJ_NAME_SZ 104 /* 26 x sizeof(uint32_t) is 104. */ 1176 uint32_t rd_object_cnt; 1177 struct lpfc_mbx_host_buf rd_object_hbuf[4]; 1178 } request; 1179 struct { 1180 uint32_t rd_object_actual_rlen; 1181 uint32_t word1; 1182 #define lpfc_mbx_rd_object_eof_SHIFT 31 1183 #define lpfc_mbx_rd_object_eof_MASK 0x1 1184 #define lpfc_mbx_rd_object_eof_WORD word1 1185 } response; 1186 } u; 1187 }; 1188 1189 struct lpfc_mbx_eq_create { 1190 struct mbox_header header; 1191 union { 1192 struct { 1193 uint32_t word0; 1194 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1195 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1196 #define lpfc_mbx_eq_create_num_pages_WORD word0 1197 struct eq_context context; 1198 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1199 } request; 1200 struct { 1201 uint32_t word0; 1202 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1203 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1204 #define lpfc_mbx_eq_create_q_id_WORD word0 1205 } response; 1206 } u; 1207 }; 1208 1209 struct lpfc_mbx_modify_eq_delay { 1210 struct mbox_header header; 1211 union { 1212 struct { 1213 uint32_t num_eq; 1214 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1215 } request; 1216 struct { 1217 uint32_t word0; 1218 } response; 1219 } u; 1220 }; 1221 1222 struct lpfc_mbx_eq_destroy { 1223 struct mbox_header header; 1224 union { 1225 struct { 1226 uint32_t word0; 1227 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1228 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1229 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1230 } request; 1231 struct { 1232 uint32_t word0; 1233 } response; 1234 } u; 1235 }; 1236 1237 struct lpfc_mbx_nop { 1238 struct mbox_header header; 1239 uint32_t context[2]; 1240 }; 1241 1242 1243 1244 struct lpfc_mbx_set_ras_fwlog { 1245 struct mbox_header header; 1246 union { 1247 struct { 1248 uint32_t word4; 1249 #define lpfc_fwlog_enable_SHIFT 0 1250 #define lpfc_fwlog_enable_MASK 0x00000001 1251 #define lpfc_fwlog_enable_WORD word4 1252 #define lpfc_fwlog_loglvl_SHIFT 8 1253 #define lpfc_fwlog_loglvl_MASK 0x0000000F 1254 #define lpfc_fwlog_loglvl_WORD word4 1255 #define lpfc_fwlog_ra_SHIFT 15 1256 #define lpfc_fwlog_ra_WORD 0x00000008 1257 #define lpfc_fwlog_buffcnt_SHIFT 16 1258 #define lpfc_fwlog_buffcnt_MASK 0x000000FF 1259 #define lpfc_fwlog_buffcnt_WORD word4 1260 #define lpfc_fwlog_buffsz_SHIFT 24 1261 #define lpfc_fwlog_buffsz_MASK 0x000000FF 1262 #define lpfc_fwlog_buffsz_WORD word4 1263 uint32_t word5; 1264 #define lpfc_fwlog_acqe_SHIFT 0 1265 #define lpfc_fwlog_acqe_MASK 0x0000FFFF 1266 #define lpfc_fwlog_acqe_WORD word5 1267 #define lpfc_fwlog_cqid_SHIFT 16 1268 #define lpfc_fwlog_cqid_MASK 0x0000FFFF 1269 #define lpfc_fwlog_cqid_WORD word5 1270 #define LPFC_MAX_FWLOG_PAGE 16 1271 struct dma_address lwpd; 1272 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1273 } request; 1274 struct { 1275 uint32_t word0; 1276 } response; 1277 } u; 1278 }; 1279 1280 1281 struct cq_context { 1282 uint32_t word0; 1283 #define lpfc_cq_context_event_SHIFT 31 1284 #define lpfc_cq_context_event_MASK 0x00000001 1285 #define lpfc_cq_context_event_WORD word0 1286 #define lpfc_cq_context_valid_SHIFT 29 1287 #define lpfc_cq_context_valid_MASK 0x00000001 1288 #define lpfc_cq_context_valid_WORD word0 1289 #define lpfc_cq_context_count_SHIFT 27 1290 #define lpfc_cq_context_count_MASK 0x00000003 1291 #define lpfc_cq_context_count_WORD word0 1292 #define LPFC_CQ_CNT_256 0x0 1293 #define LPFC_CQ_CNT_512 0x1 1294 #define LPFC_CQ_CNT_1024 0x2 1295 #define LPFC_CQ_CNT_WORD7 0x3 1296 #define lpfc_cq_context_autovalid_SHIFT 15 1297 #define lpfc_cq_context_autovalid_MASK 0x00000001 1298 #define lpfc_cq_context_autovalid_WORD word0 1299 uint32_t word1; 1300 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1301 #define lpfc_cq_eq_id_MASK 0x000000FF 1302 #define lpfc_cq_eq_id_WORD word1 1303 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1304 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1305 #define lpfc_cq_eq_id_2_WORD word1 1306 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1307 uint32_t reserved1; 1308 }; 1309 1310 struct lpfc_mbx_cq_create { 1311 struct mbox_header header; 1312 union { 1313 struct { 1314 uint32_t word0; 1315 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1316 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1317 #define lpfc_mbx_cq_create_page_size_WORD word0 1318 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1319 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1320 #define lpfc_mbx_cq_create_num_pages_WORD word0 1321 struct cq_context context; 1322 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1323 } request; 1324 struct { 1325 uint32_t word0; 1326 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1327 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1328 #define lpfc_mbx_cq_create_q_id_WORD word0 1329 } response; 1330 } u; 1331 }; 1332 1333 struct lpfc_mbx_cq_create_set { 1334 union lpfc_sli4_cfg_shdr cfg_shdr; 1335 union { 1336 struct { 1337 uint32_t word0; 1338 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1339 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1340 #define lpfc_mbx_cq_create_set_page_size_WORD word0 1341 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1342 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1343 #define lpfc_mbx_cq_create_set_num_pages_WORD word0 1344 uint32_t word1; 1345 #define lpfc_mbx_cq_create_set_evt_SHIFT 31 1346 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1347 #define lpfc_mbx_cq_create_set_evt_WORD word1 1348 #define lpfc_mbx_cq_create_set_valid_SHIFT 29 1349 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1350 #define lpfc_mbx_cq_create_set_valid_WORD word1 1351 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1352 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1353 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1354 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1355 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1356 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1357 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1358 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1359 #define lpfc_mbx_cq_create_set_autovalid_WORD word1 1360 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1361 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1362 #define lpfc_mbx_cq_create_set_nodelay_WORD word1 1363 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1364 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1365 #define lpfc_mbx_cq_create_set_clswm_WORD word1 1366 uint32_t word2; 1367 #define lpfc_mbx_cq_create_set_arm_SHIFT 31 1368 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1369 #define lpfc_mbx_cq_create_set_arm_WORD word2 1370 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1371 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1372 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1373 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1374 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1375 #define lpfc_mbx_cq_create_set_num_cq_WORD word2 1376 uint32_t word3; 1377 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1378 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1379 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1380 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1381 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1382 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1383 uint32_t word4; 1384 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1385 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1386 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1387 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1388 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1389 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1390 uint32_t word5; 1391 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1392 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1393 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1394 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1395 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1396 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1397 uint32_t word6; 1398 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1399 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1400 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1401 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1402 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1403 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1404 uint32_t word7; 1405 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1406 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1407 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1408 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1409 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1410 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1411 uint32_t word8; 1412 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1413 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1414 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1415 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1416 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1417 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1418 uint32_t word9; 1419 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1420 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1421 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1422 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1423 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1424 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1425 uint32_t word10; 1426 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1427 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1428 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1429 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1430 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1431 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1432 struct dma_address page[1]; 1433 } request; 1434 struct { 1435 uint32_t word0; 1436 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1437 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1438 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1439 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1440 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1441 #define lpfc_mbx_cq_create_set_base_id_WORD word0 1442 } response; 1443 } u; 1444 }; 1445 1446 struct lpfc_mbx_cq_destroy { 1447 struct mbox_header header; 1448 union { 1449 struct { 1450 uint32_t word0; 1451 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1452 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1453 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1454 } request; 1455 struct { 1456 uint32_t word0; 1457 } response; 1458 } u; 1459 }; 1460 1461 struct wq_context { 1462 uint32_t reserved0; 1463 uint32_t reserved1; 1464 uint32_t reserved2; 1465 uint32_t reserved3; 1466 }; 1467 1468 struct lpfc_mbx_wq_create { 1469 struct mbox_header header; 1470 union { 1471 struct { /* Version 0 Request */ 1472 uint32_t word0; 1473 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1474 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1475 #define lpfc_mbx_wq_create_num_pages_WORD word0 1476 #define lpfc_mbx_wq_create_dua_SHIFT 8 1477 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1478 #define lpfc_mbx_wq_create_dua_WORD word0 1479 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1480 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1481 #define lpfc_mbx_wq_create_cq_id_WORD word0 1482 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1483 uint32_t word9; 1484 #define lpfc_mbx_wq_create_bua_SHIFT 0 1485 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1486 #define lpfc_mbx_wq_create_bua_WORD word9 1487 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1488 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1489 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1490 } request; 1491 struct { /* Version 1 Request */ 1492 uint32_t word0; /* Word 0 is the same as in v0 */ 1493 uint32_t word1; 1494 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1495 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1496 #define lpfc_mbx_wq_create_page_size_WORD word1 1497 #define LPFC_WQ_PAGE_SIZE_4096 0x1 1498 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1499 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1500 #define lpfc_mbx_wq_create_dpp_req_WORD word1 1501 #define lpfc_mbx_wq_create_doe_SHIFT 14 1502 #define lpfc_mbx_wq_create_doe_MASK 0x00000001 1503 #define lpfc_mbx_wq_create_doe_WORD word1 1504 #define lpfc_mbx_wq_create_toe_SHIFT 13 1505 #define lpfc_mbx_wq_create_toe_MASK 0x00000001 1506 #define lpfc_mbx_wq_create_toe_WORD word1 1507 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1508 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1509 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1510 #define LPFC_WQ_WQE_SIZE_64 0x5 1511 #define LPFC_WQ_WQE_SIZE_128 0x6 1512 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1513 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1514 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1515 uint32_t word2; 1516 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1517 } request_1; 1518 struct { 1519 uint32_t word0; 1520 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1521 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1522 #define lpfc_mbx_wq_create_q_id_WORD word0 1523 uint32_t doorbell_offset; 1524 uint32_t word2; 1525 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1526 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1527 #define lpfc_mbx_wq_create_bar_set_WORD word2 1528 #define WQ_PCI_BAR_0_AND_1 0x00 1529 #define WQ_PCI_BAR_2_AND_3 0x01 1530 #define WQ_PCI_BAR_4_AND_5 0x02 1531 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1532 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1533 #define lpfc_mbx_wq_create_db_format_WORD word2 1534 } response; 1535 struct { 1536 uint32_t word0; 1537 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1538 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1539 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1540 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1541 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1542 #define lpfc_mbx_wq_create_v1_q_id_WORD word0 1543 uint32_t word1; 1544 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1545 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1546 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1547 uint32_t doorbell_offset; 1548 uint32_t word3; 1549 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1550 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1551 #define lpfc_mbx_wq_create_dpp_id_WORD word3 1552 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1553 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1554 #define lpfc_mbx_wq_create_dpp_bar_WORD word3 1555 uint32_t dpp_offset; 1556 } response_1; 1557 } u; 1558 }; 1559 1560 struct lpfc_mbx_wq_destroy { 1561 struct mbox_header header; 1562 union { 1563 struct { 1564 uint32_t word0; 1565 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1566 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1567 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1568 } request; 1569 struct { 1570 uint32_t word0; 1571 } response; 1572 } u; 1573 }; 1574 1575 #define LPFC_HDR_BUF_SIZE 128 1576 #define LPFC_DATA_BUF_SIZE 2048 1577 #define LPFC_NVMET_DATA_BUF_SIZE 128 1578 struct rq_context { 1579 uint32_t word0; 1580 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1581 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1582 #define lpfc_rq_context_rqe_count_WORD word0 1583 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1584 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1585 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1586 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1587 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1588 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1589 #define lpfc_rq_context_rqe_count_1_WORD word0 1590 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1591 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1592 #define lpfc_rq_context_rqe_size_WORD word0 1593 #define LPFC_RQE_SIZE_8 2 1594 #define LPFC_RQE_SIZE_16 3 1595 #define LPFC_RQE_SIZE_32 4 1596 #define LPFC_RQE_SIZE_64 5 1597 #define LPFC_RQE_SIZE_128 6 1598 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1599 #define lpfc_rq_context_page_size_MASK 0x000000FF 1600 #define lpfc_rq_context_page_size_WORD word0 1601 #define LPFC_RQ_PAGE_SIZE_4096 0x1 1602 uint32_t word1; 1603 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1604 #define lpfc_rq_context_data_size_MASK 0x0000FFFF 1605 #define lpfc_rq_context_data_size_WORD word1 1606 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1607 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1608 #define lpfc_rq_context_hdr_size_WORD word1 1609 uint32_t word2; 1610 #define lpfc_rq_context_cq_id_SHIFT 16 1611 #define lpfc_rq_context_cq_id_MASK 0x0000FFFF 1612 #define lpfc_rq_context_cq_id_WORD word2 1613 #define lpfc_rq_context_buf_size_SHIFT 0 1614 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1615 #define lpfc_rq_context_buf_size_WORD word2 1616 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1617 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1618 #define lpfc_rq_context_base_cq_WORD word2 1619 uint32_t buffer_size; /* Version 1 Only */ 1620 }; 1621 1622 struct lpfc_mbx_rq_create { 1623 struct mbox_header header; 1624 union { 1625 struct { 1626 uint32_t word0; 1627 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1628 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1629 #define lpfc_mbx_rq_create_num_pages_WORD word0 1630 #define lpfc_mbx_rq_create_dua_SHIFT 16 1631 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1632 #define lpfc_mbx_rq_create_dua_WORD word0 1633 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1634 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1635 #define lpfc_mbx_rq_create_bqu_WORD word0 1636 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1637 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1638 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1639 struct rq_context context; 1640 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1641 } request; 1642 struct { 1643 uint32_t word0; 1644 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1645 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1646 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1647 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1648 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1649 #define lpfc_mbx_rq_create_q_id_WORD word0 1650 uint32_t doorbell_offset; 1651 uint32_t word2; 1652 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1653 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1654 #define lpfc_mbx_rq_create_bar_set_WORD word2 1655 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1656 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1657 #define lpfc_mbx_rq_create_db_format_WORD word2 1658 } response; 1659 } u; 1660 }; 1661 1662 struct lpfc_mbx_rq_create_v2 { 1663 union lpfc_sli4_cfg_shdr cfg_shdr; 1664 union { 1665 struct { 1666 uint32_t word0; 1667 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1668 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1669 #define lpfc_mbx_rq_create_num_pages_WORD word0 1670 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1671 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1672 #define lpfc_mbx_rq_create_rq_cnt_WORD word0 1673 #define lpfc_mbx_rq_create_dua_SHIFT 16 1674 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1675 #define lpfc_mbx_rq_create_dua_WORD word0 1676 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1677 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1678 #define lpfc_mbx_rq_create_bqu_WORD word0 1679 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1680 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1681 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1682 #define lpfc_mbx_rq_create_dim_SHIFT 29 1683 #define lpfc_mbx_rq_create_dim_MASK 0x00000001 1684 #define lpfc_mbx_rq_create_dim_WORD word0 1685 #define lpfc_mbx_rq_create_dfd_SHIFT 30 1686 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1687 #define lpfc_mbx_rq_create_dfd_WORD word0 1688 #define lpfc_mbx_rq_create_dnb_SHIFT 31 1689 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1690 #define lpfc_mbx_rq_create_dnb_WORD word0 1691 struct rq_context context; 1692 struct dma_address page[1]; 1693 } request; 1694 struct { 1695 uint32_t word0; 1696 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1697 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1698 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1699 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1700 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1701 #define lpfc_mbx_rq_create_q_id_WORD word0 1702 uint32_t doorbell_offset; 1703 uint32_t word2; 1704 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1705 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1706 #define lpfc_mbx_rq_create_bar_set_WORD word2 1707 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1708 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1709 #define lpfc_mbx_rq_create_db_format_WORD word2 1710 } response; 1711 } u; 1712 }; 1713 1714 struct lpfc_mbx_rq_destroy { 1715 struct mbox_header header; 1716 union { 1717 struct { 1718 uint32_t word0; 1719 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1720 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1721 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1722 } request; 1723 struct { 1724 uint32_t word0; 1725 } response; 1726 } u; 1727 }; 1728 1729 struct mq_context { 1730 uint32_t word0; 1731 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1732 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1733 #define lpfc_mq_context_cq_id_WORD word0 1734 #define lpfc_mq_context_ring_size_SHIFT 16 1735 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1736 #define lpfc_mq_context_ring_size_WORD word0 1737 #define LPFC_MQ_RING_SIZE_16 0x5 1738 #define LPFC_MQ_RING_SIZE_32 0x6 1739 #define LPFC_MQ_RING_SIZE_64 0x7 1740 #define LPFC_MQ_RING_SIZE_128 0x8 1741 uint32_t word1; 1742 #define lpfc_mq_context_valid_SHIFT 31 1743 #define lpfc_mq_context_valid_MASK 0x00000001 1744 #define lpfc_mq_context_valid_WORD word1 1745 uint32_t reserved2; 1746 uint32_t reserved3; 1747 }; 1748 1749 struct lpfc_mbx_mq_create { 1750 struct mbox_header header; 1751 union { 1752 struct { 1753 uint32_t word0; 1754 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1755 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1756 #define lpfc_mbx_mq_create_num_pages_WORD word0 1757 struct mq_context context; 1758 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1759 } request; 1760 struct { 1761 uint32_t word0; 1762 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1763 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1764 #define lpfc_mbx_mq_create_q_id_WORD word0 1765 } response; 1766 } u; 1767 }; 1768 1769 struct lpfc_mbx_mq_create_ext { 1770 struct mbox_header header; 1771 union { 1772 struct { 1773 uint32_t word0; 1774 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1775 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1776 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1777 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1778 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1779 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1780 uint32_t async_evt_bmap; 1781 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1782 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1783 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1784 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1785 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1786 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1787 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1788 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1789 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1790 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1791 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1792 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1793 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1794 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1795 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1796 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1797 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1798 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1799 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1800 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1801 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1802 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1803 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1804 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1805 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1806 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1807 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1808 struct mq_context context; 1809 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1810 } request; 1811 struct { 1812 uint32_t word0; 1813 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1814 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1815 #define lpfc_mbx_mq_create_q_id_WORD word0 1816 } response; 1817 } u; 1818 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1819 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1820 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1821 }; 1822 1823 struct lpfc_mbx_mq_destroy { 1824 struct mbox_header header; 1825 union { 1826 struct { 1827 uint32_t word0; 1828 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1829 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1830 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1831 } request; 1832 struct { 1833 uint32_t word0; 1834 } response; 1835 } u; 1836 }; 1837 1838 /* Start Gen 2 SLI4 Mailbox definitions: */ 1839 1840 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1841 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1842 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1843 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1844 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1845 1846 struct lpfc_mbx_get_rsrc_extent_info { 1847 struct mbox_header header; 1848 union { 1849 struct { 1850 uint32_t word4; 1851 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1852 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1853 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1854 } req; 1855 struct { 1856 uint32_t word4; 1857 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1858 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1859 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1860 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1861 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1862 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1863 } rsp; 1864 } u; 1865 }; 1866 1867 struct lpfc_mbx_query_fw_config { 1868 struct mbox_header header; 1869 struct { 1870 uint32_t config_number; 1871 #define LPFC_FC_FCOE 0x00000007 1872 uint32_t asic_revision; 1873 uint32_t physical_port; 1874 uint32_t function_mode; 1875 #define LPFC_FCOE_INI_MODE 0x00000040 1876 #define LPFC_FCOE_TGT_MODE 0x00000080 1877 #define LPFC_DUA_MODE 0x00000800 1878 uint32_t ulp0_mode; 1879 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1880 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1881 uint32_t ulp0_nap_words[12]; 1882 uint32_t ulp1_mode; 1883 uint32_t ulp1_nap_words[12]; 1884 uint32_t function_capabilities; 1885 uint32_t cqid_base; 1886 uint32_t cqid_tot; 1887 uint32_t eqid_base; 1888 uint32_t eqid_tot; 1889 uint32_t ulp0_nap2_words[2]; 1890 uint32_t ulp1_nap2_words[2]; 1891 } rsp; 1892 }; 1893 1894 struct lpfc_mbx_set_beacon_config { 1895 struct mbox_header header; 1896 uint32_t word4; 1897 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1898 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1899 #define lpfc_mbx_set_beacon_port_num_WORD word4 1900 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1901 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1902 #define lpfc_mbx_set_beacon_port_type_WORD word4 1903 #define lpfc_mbx_set_beacon_state_SHIFT 8 1904 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1905 #define lpfc_mbx_set_beacon_state_WORD word4 1906 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1907 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1908 #define lpfc_mbx_set_beacon_duration_WORD word4 1909 1910 /* COMMON_SET_BEACON_CONFIG_V1 */ 1911 #define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1912 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1913 #define lpfc_mbx_set_beacon_duration_v1_WORD word4 1914 uint32_t word5; /* RESERVED */ 1915 }; 1916 1917 struct lpfc_id_range { 1918 uint32_t word5; 1919 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1920 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1921 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1922 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1923 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1924 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1925 }; 1926 1927 struct lpfc_mbx_set_link_diag_state { 1928 struct mbox_header header; 1929 union { 1930 struct { 1931 uint32_t word0; 1932 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1933 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1934 #define lpfc_mbx_set_diag_state_diag_WORD word0 1935 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1936 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1937 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1938 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1939 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1940 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1941 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1942 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1943 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1944 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1945 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1946 } req; 1947 struct { 1948 uint32_t word0; 1949 } rsp; 1950 } u; 1951 }; 1952 1953 struct lpfc_mbx_set_link_diag_loopback { 1954 struct mbox_header header; 1955 union { 1956 struct { 1957 uint32_t word0; 1958 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1959 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1960 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1961 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1962 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1963 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1964 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3 1965 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1966 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1967 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1968 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1969 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1970 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1971 } req; 1972 struct { 1973 uint32_t word0; 1974 } rsp; 1975 } u; 1976 }; 1977 1978 struct lpfc_mbx_run_link_diag_test { 1979 struct mbox_header header; 1980 union { 1981 struct { 1982 uint32_t word0; 1983 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1984 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1985 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1986 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1987 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1988 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1989 uint32_t word1; 1990 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1991 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1992 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1993 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1994 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1995 #define lpfc_mbx_run_diag_test_loops_WORD word1 1996 uint32_t word2; 1997 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1998 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1999 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 2000 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 2001 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 2002 #define lpfc_mbx_run_diag_test_err_act_WORD word2 2003 } req; 2004 struct { 2005 uint32_t word0; 2006 } rsp; 2007 } u; 2008 }; 2009 2010 /* 2011 * struct lpfc_mbx_alloc_rsrc_extents: 2012 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 2013 * 6 words of header + 4 words of shared subcommand header + 2014 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 2015 * 2016 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 2017 * for extents payload. 2018 * 2019 * 212/2 (bytes per extent) = 106 extents. 2020 * 106/2 (extents per word) = 53 words. 2021 * lpfc_id_range id is statically size to 53. 2022 * 2023 * This mailbox definition is used for ALLOC or GET_ALLOCATED 2024 * extent ranges. For ALLOC, the type and cnt are required. 2025 * For GET_ALLOCATED, only the type is required. 2026 */ 2027 struct lpfc_mbx_alloc_rsrc_extents { 2028 struct mbox_header header; 2029 union { 2030 struct { 2031 uint32_t word4; 2032 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 2033 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 2034 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 2035 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 2036 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 2037 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 2038 } req; 2039 struct { 2040 uint32_t word4; 2041 #define lpfc_mbx_rsrc_cnt_SHIFT 0 2042 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 2043 #define lpfc_mbx_rsrc_cnt_WORD word4 2044 struct lpfc_id_range id[53]; 2045 } rsp; 2046 } u; 2047 }; 2048 2049 /* 2050 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 2051 * structure shares the same SHIFT/MASK/WORD defines provided in the 2052 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 2053 * the structures defined above. This non-embedded structure provides for the 2054 * maximum number of extents supported by the port. 2055 */ 2056 struct lpfc_mbx_nembed_rsrc_extent { 2057 union lpfc_sli4_cfg_shdr cfg_shdr; 2058 uint32_t word4; 2059 struct lpfc_id_range id; 2060 }; 2061 2062 struct lpfc_mbx_dealloc_rsrc_extents { 2063 struct mbox_header header; 2064 struct { 2065 uint32_t word4; 2066 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 2067 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 2068 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 2069 } req; 2070 2071 }; 2072 2073 /* Start SLI4 FCoE specific mbox structures. */ 2074 2075 struct lpfc_mbx_post_hdr_tmpl { 2076 struct mbox_header header; 2077 uint32_t word10; 2078 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2079 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2080 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2081 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2082 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2083 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2084 uint32_t rpi_paddr_lo; 2085 uint32_t rpi_paddr_hi; 2086 }; 2087 2088 struct sli4_sge { /* SLI-4 */ 2089 uint32_t addr_hi; 2090 uint32_t addr_lo; 2091 2092 uint32_t word2; 2093 #define lpfc_sli4_sge_offset_SHIFT 0 2094 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2095 #define lpfc_sli4_sge_offset_WORD word2 2096 #define lpfc_sli4_sge_type_SHIFT 27 2097 #define lpfc_sli4_sge_type_MASK 0x0000000F 2098 #define lpfc_sli4_sge_type_WORD word2 2099 #define LPFC_SGE_TYPE_DATA 0x0 2100 #define LPFC_SGE_TYPE_DIF 0x4 2101 #define LPFC_SGE_TYPE_LSP 0x5 2102 #define LPFC_SGE_TYPE_PEDIF 0x6 2103 #define LPFC_SGE_TYPE_PESEED 0x7 2104 #define LPFC_SGE_TYPE_DISEED 0x8 2105 #define LPFC_SGE_TYPE_ENC 0x9 2106 #define LPFC_SGE_TYPE_ATM 0xA 2107 #define LPFC_SGE_TYPE_SKIP 0xC 2108 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2109 #define lpfc_sli4_sge_last_MASK 0x00000001 2110 #define lpfc_sli4_sge_last_WORD word2 2111 uint32_t sge_len; 2112 }; 2113 2114 struct sli4_hybrid_sgl { 2115 struct list_head list_node; 2116 struct sli4_sge *dma_sgl; 2117 dma_addr_t dma_phys_sgl; 2118 }; 2119 2120 struct fcp_cmd_rsp_buf { 2121 struct list_head list_node; 2122 2123 /* for storing cmd/rsp dma alloc'ed virt_addr */ 2124 struct fcp_cmnd *fcp_cmnd; 2125 struct fcp_rsp *fcp_rsp; 2126 2127 /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */ 2128 dma_addr_t fcp_cmd_rsp_dma_handle; 2129 }; 2130 2131 struct sli4_sge_diseed { /* SLI-4 */ 2132 uint32_t ref_tag; 2133 uint32_t ref_tag_tran; 2134 2135 uint32_t word2; 2136 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 2137 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2138 #define lpfc_sli4_sge_dif_apptran_WORD word2 2139 #define lpfc_sli4_sge_dif_af_SHIFT 24 2140 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 2141 #define lpfc_sli4_sge_dif_af_WORD word2 2142 #define lpfc_sli4_sge_dif_na_SHIFT 25 2143 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 2144 #define lpfc_sli4_sge_dif_na_WORD word2 2145 #define lpfc_sli4_sge_dif_hi_SHIFT 26 2146 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2147 #define lpfc_sli4_sge_dif_hi_WORD word2 2148 #define lpfc_sli4_sge_dif_type_SHIFT 27 2149 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2150 #define lpfc_sli4_sge_dif_type_WORD word2 2151 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2152 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 2153 #define lpfc_sli4_sge_dif_last_WORD word2 2154 uint32_t word3; 2155 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 2156 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2157 #define lpfc_sli4_sge_dif_apptag_WORD word3 2158 #define lpfc_sli4_sge_dif_bs_SHIFT 16 2159 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2160 #define lpfc_sli4_sge_dif_bs_WORD word3 2161 #define lpfc_sli4_sge_dif_ai_SHIFT 19 2162 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2163 #define lpfc_sli4_sge_dif_ai_WORD word3 2164 #define lpfc_sli4_sge_dif_me_SHIFT 20 2165 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 2166 #define lpfc_sli4_sge_dif_me_WORD word3 2167 #define lpfc_sli4_sge_dif_re_SHIFT 21 2168 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 2169 #define lpfc_sli4_sge_dif_re_WORD word3 2170 #define lpfc_sli4_sge_dif_ce_SHIFT 22 2171 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2172 #define lpfc_sli4_sge_dif_ce_WORD word3 2173 #define lpfc_sli4_sge_dif_nr_SHIFT 23 2174 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2175 #define lpfc_sli4_sge_dif_nr_WORD word3 2176 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 2177 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2178 #define lpfc_sli4_sge_dif_oprx_WORD word3 2179 #define lpfc_sli4_sge_dif_optx_SHIFT 28 2180 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2181 #define lpfc_sli4_sge_dif_optx_WORD word3 2182 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2183 }; 2184 2185 struct fcf_record { 2186 uint32_t max_rcv_size; 2187 uint32_t fka_adv_period; 2188 uint32_t fip_priority; 2189 uint32_t word3; 2190 #define lpfc_fcf_record_mac_0_SHIFT 0 2191 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 2192 #define lpfc_fcf_record_mac_0_WORD word3 2193 #define lpfc_fcf_record_mac_1_SHIFT 8 2194 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 2195 #define lpfc_fcf_record_mac_1_WORD word3 2196 #define lpfc_fcf_record_mac_2_SHIFT 16 2197 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 2198 #define lpfc_fcf_record_mac_2_WORD word3 2199 #define lpfc_fcf_record_mac_3_SHIFT 24 2200 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 2201 #define lpfc_fcf_record_mac_3_WORD word3 2202 uint32_t word4; 2203 #define lpfc_fcf_record_mac_4_SHIFT 0 2204 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 2205 #define lpfc_fcf_record_mac_4_WORD word4 2206 #define lpfc_fcf_record_mac_5_SHIFT 8 2207 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 2208 #define lpfc_fcf_record_mac_5_WORD word4 2209 #define lpfc_fcf_record_fcf_avail_SHIFT 16 2210 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2211 #define lpfc_fcf_record_fcf_avail_WORD word4 2212 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2213 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2214 #define lpfc_fcf_record_mac_addr_prov_WORD word4 2215 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2216 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2217 uint32_t word5; 2218 #define lpfc_fcf_record_fab_name_0_SHIFT 0 2219 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2220 #define lpfc_fcf_record_fab_name_0_WORD word5 2221 #define lpfc_fcf_record_fab_name_1_SHIFT 8 2222 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2223 #define lpfc_fcf_record_fab_name_1_WORD word5 2224 #define lpfc_fcf_record_fab_name_2_SHIFT 16 2225 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2226 #define lpfc_fcf_record_fab_name_2_WORD word5 2227 #define lpfc_fcf_record_fab_name_3_SHIFT 24 2228 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2229 #define lpfc_fcf_record_fab_name_3_WORD word5 2230 uint32_t word6; 2231 #define lpfc_fcf_record_fab_name_4_SHIFT 0 2232 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2233 #define lpfc_fcf_record_fab_name_4_WORD word6 2234 #define lpfc_fcf_record_fab_name_5_SHIFT 8 2235 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2236 #define lpfc_fcf_record_fab_name_5_WORD word6 2237 #define lpfc_fcf_record_fab_name_6_SHIFT 16 2238 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2239 #define lpfc_fcf_record_fab_name_6_WORD word6 2240 #define lpfc_fcf_record_fab_name_7_SHIFT 24 2241 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2242 #define lpfc_fcf_record_fab_name_7_WORD word6 2243 uint32_t word7; 2244 #define lpfc_fcf_record_fc_map_0_SHIFT 0 2245 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2246 #define lpfc_fcf_record_fc_map_0_WORD word7 2247 #define lpfc_fcf_record_fc_map_1_SHIFT 8 2248 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2249 #define lpfc_fcf_record_fc_map_1_WORD word7 2250 #define lpfc_fcf_record_fc_map_2_SHIFT 16 2251 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2252 #define lpfc_fcf_record_fc_map_2_WORD word7 2253 #define lpfc_fcf_record_fcf_valid_SHIFT 24 2254 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2255 #define lpfc_fcf_record_fcf_valid_WORD word7 2256 #define lpfc_fcf_record_fcf_fc_SHIFT 25 2257 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2258 #define lpfc_fcf_record_fcf_fc_WORD word7 2259 #define lpfc_fcf_record_fcf_sol_SHIFT 31 2260 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2261 #define lpfc_fcf_record_fcf_sol_WORD word7 2262 uint32_t word8; 2263 #define lpfc_fcf_record_fcf_index_SHIFT 0 2264 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2265 #define lpfc_fcf_record_fcf_index_WORD word8 2266 #define lpfc_fcf_record_fcf_state_SHIFT 16 2267 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2268 #define lpfc_fcf_record_fcf_state_WORD word8 2269 uint8_t vlan_bitmap[512]; 2270 uint32_t word137; 2271 #define lpfc_fcf_record_switch_name_0_SHIFT 0 2272 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2273 #define lpfc_fcf_record_switch_name_0_WORD word137 2274 #define lpfc_fcf_record_switch_name_1_SHIFT 8 2275 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2276 #define lpfc_fcf_record_switch_name_1_WORD word137 2277 #define lpfc_fcf_record_switch_name_2_SHIFT 16 2278 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2279 #define lpfc_fcf_record_switch_name_2_WORD word137 2280 #define lpfc_fcf_record_switch_name_3_SHIFT 24 2281 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2282 #define lpfc_fcf_record_switch_name_3_WORD word137 2283 uint32_t word138; 2284 #define lpfc_fcf_record_switch_name_4_SHIFT 0 2285 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2286 #define lpfc_fcf_record_switch_name_4_WORD word138 2287 #define lpfc_fcf_record_switch_name_5_SHIFT 8 2288 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2289 #define lpfc_fcf_record_switch_name_5_WORD word138 2290 #define lpfc_fcf_record_switch_name_6_SHIFT 16 2291 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2292 #define lpfc_fcf_record_switch_name_6_WORD word138 2293 #define lpfc_fcf_record_switch_name_7_SHIFT 24 2294 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2295 #define lpfc_fcf_record_switch_name_7_WORD word138 2296 }; 2297 2298 struct lpfc_mbx_read_fcf_tbl { 2299 union lpfc_sli4_cfg_shdr cfg_shdr; 2300 union { 2301 struct { 2302 uint32_t word10; 2303 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2304 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2305 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2306 } request; 2307 struct { 2308 uint32_t eventag; 2309 } response; 2310 } u; 2311 uint32_t word11; 2312 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2313 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2314 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2315 }; 2316 2317 struct lpfc_mbx_add_fcf_tbl_entry { 2318 union lpfc_sli4_cfg_shdr cfg_shdr; 2319 uint32_t word10; 2320 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2321 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2322 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2323 struct lpfc_mbx_sge fcf_sge; 2324 }; 2325 2326 struct lpfc_mbx_del_fcf_tbl_entry { 2327 struct mbox_header header; 2328 uint32_t word10; 2329 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2330 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2331 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 2332 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2333 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2334 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 2335 }; 2336 2337 struct lpfc_mbx_redisc_fcf_tbl { 2338 struct mbox_header header; 2339 uint32_t word10; 2340 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 2341 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2342 #define lpfc_mbx_redisc_fcf_count_WORD word10 2343 uint32_t resvd; 2344 uint32_t word12; 2345 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 2346 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2347 #define lpfc_mbx_redisc_fcf_index_WORD word12 2348 }; 2349 2350 /* Status field for embedded SLI_CONFIG mailbox command */ 2351 #define STATUS_SUCCESS 0x0 2352 #define STATUS_FAILED 0x1 2353 #define STATUS_ILLEGAL_REQUEST 0x2 2354 #define STATUS_ILLEGAL_FIELD 0x3 2355 #define STATUS_INSUFFICIENT_BUFFER 0x4 2356 #define STATUS_UNAUTHORIZED_REQUEST 0x5 2357 #define STATUS_FLASHROM_SAVE_FAILED 0x17 2358 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 2359 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2360 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2361 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2362 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2363 #define STATUS_ASSERT_FAILED 0x1e 2364 #define STATUS_INVALID_SESSION 0x1f 2365 #define STATUS_INVALID_CONNECTION 0x20 2366 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2367 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2368 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2369 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2370 #define STATUS_FLASHROM_READ_FAILED 0x27 2371 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 2372 #define STATUS_ERROR_ACITMAIN 0x2a 2373 #define STATUS_REBOOT_REQUIRED 0x2c 2374 #define STATUS_FCF_IN_USE 0x3a 2375 #define STATUS_FCF_TABLE_EMPTY 0x43 2376 2377 /* 2378 * Additional status field for embedded SLI_CONFIG mailbox 2379 * command. 2380 */ 2381 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2382 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2383 #define ADD_STATUS_INVALID_REQUEST 0x4B 2384 #define ADD_STATUS_INVALID_OBJECT_NAME 0xA0 2385 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58 2386 2387 struct lpfc_mbx_sli4_config { 2388 struct mbox_header header; 2389 }; 2390 2391 struct lpfc_mbx_init_vfi { 2392 uint32_t word1; 2393 #define lpfc_init_vfi_vr_SHIFT 31 2394 #define lpfc_init_vfi_vr_MASK 0x00000001 2395 #define lpfc_init_vfi_vr_WORD word1 2396 #define lpfc_init_vfi_vt_SHIFT 30 2397 #define lpfc_init_vfi_vt_MASK 0x00000001 2398 #define lpfc_init_vfi_vt_WORD word1 2399 #define lpfc_init_vfi_vf_SHIFT 29 2400 #define lpfc_init_vfi_vf_MASK 0x00000001 2401 #define lpfc_init_vfi_vf_WORD word1 2402 #define lpfc_init_vfi_vp_SHIFT 28 2403 #define lpfc_init_vfi_vp_MASK 0x00000001 2404 #define lpfc_init_vfi_vp_WORD word1 2405 #define lpfc_init_vfi_vfi_SHIFT 0 2406 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2407 #define lpfc_init_vfi_vfi_WORD word1 2408 uint32_t word2; 2409 #define lpfc_init_vfi_vpi_SHIFT 16 2410 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2411 #define lpfc_init_vfi_vpi_WORD word2 2412 #define lpfc_init_vfi_fcfi_SHIFT 0 2413 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2414 #define lpfc_init_vfi_fcfi_WORD word2 2415 uint32_t word3; 2416 #define lpfc_init_vfi_pri_SHIFT 13 2417 #define lpfc_init_vfi_pri_MASK 0x00000007 2418 #define lpfc_init_vfi_pri_WORD word3 2419 #define lpfc_init_vfi_vf_id_SHIFT 1 2420 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2421 #define lpfc_init_vfi_vf_id_WORD word3 2422 uint32_t word4; 2423 #define lpfc_init_vfi_hop_count_SHIFT 24 2424 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 2425 #define lpfc_init_vfi_hop_count_WORD word4 2426 }; 2427 #define MBX_VFI_IN_USE 0x9F02 2428 2429 2430 struct lpfc_mbx_reg_vfi { 2431 uint32_t word1; 2432 #define lpfc_reg_vfi_upd_SHIFT 29 2433 #define lpfc_reg_vfi_upd_MASK 0x00000001 2434 #define lpfc_reg_vfi_upd_WORD word1 2435 #define lpfc_reg_vfi_vp_SHIFT 28 2436 #define lpfc_reg_vfi_vp_MASK 0x00000001 2437 #define lpfc_reg_vfi_vp_WORD word1 2438 #define lpfc_reg_vfi_vfi_SHIFT 0 2439 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2440 #define lpfc_reg_vfi_vfi_WORD word1 2441 uint32_t word2; 2442 #define lpfc_reg_vfi_vpi_SHIFT 16 2443 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2444 #define lpfc_reg_vfi_vpi_WORD word2 2445 #define lpfc_reg_vfi_fcfi_SHIFT 0 2446 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2447 #define lpfc_reg_vfi_fcfi_WORD word2 2448 uint32_t wwn[2]; 2449 struct ulp_bde64 bde; 2450 uint32_t e_d_tov; 2451 uint32_t r_a_tov; 2452 uint32_t word10; 2453 #define lpfc_reg_vfi_nport_id_SHIFT 0 2454 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2455 #define lpfc_reg_vfi_nport_id_WORD word10 2456 #define lpfc_reg_vfi_bbcr_SHIFT 27 2457 #define lpfc_reg_vfi_bbcr_MASK 0x00000001 2458 #define lpfc_reg_vfi_bbcr_WORD word10 2459 #define lpfc_reg_vfi_bbscn_SHIFT 28 2460 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2461 #define lpfc_reg_vfi_bbscn_WORD word10 2462 }; 2463 2464 struct lpfc_mbx_init_vpi { 2465 uint32_t word1; 2466 #define lpfc_init_vpi_vfi_SHIFT 16 2467 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2468 #define lpfc_init_vpi_vfi_WORD word1 2469 #define lpfc_init_vpi_vpi_SHIFT 0 2470 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2471 #define lpfc_init_vpi_vpi_WORD word1 2472 }; 2473 2474 struct lpfc_mbx_read_vpi { 2475 uint32_t word1_rsvd; 2476 uint32_t word2; 2477 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2478 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2479 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2480 uint32_t word3_rsvd; 2481 uint32_t word4; 2482 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2483 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2484 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2485 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2486 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2487 #define lpfc_mbx_read_vpi_pb_WORD word4 2488 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2489 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2490 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2491 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2492 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2493 #define lpfc_mbx_read_vpi_ns_WORD word4 2494 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2495 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2496 #define lpfc_mbx_read_vpi_hl_WORD word4 2497 uint32_t word5_rsvd; 2498 uint32_t word6; 2499 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2500 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2501 #define lpfc_mbx_read_vpi_vpi_WORD word6 2502 uint32_t word7; 2503 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2504 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2505 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2506 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2507 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2508 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2509 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2510 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2511 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2512 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2513 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2514 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2515 uint32_t word8; 2516 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2517 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2518 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2519 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2520 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2521 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2522 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2523 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2524 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2525 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2526 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2527 #define lpfc_mbx_read_vpi_vv_WORD word8 2528 }; 2529 2530 struct lpfc_mbx_unreg_vfi { 2531 uint32_t word1_rsvd; 2532 uint32_t word2; 2533 #define lpfc_unreg_vfi_vfi_SHIFT 0 2534 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2535 #define lpfc_unreg_vfi_vfi_WORD word2 2536 }; 2537 2538 struct lpfc_mbx_resume_rpi { 2539 uint32_t word1; 2540 #define lpfc_resume_rpi_index_SHIFT 0 2541 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2542 #define lpfc_resume_rpi_index_WORD word1 2543 #define lpfc_resume_rpi_ii_SHIFT 30 2544 #define lpfc_resume_rpi_ii_MASK 0x00000003 2545 #define lpfc_resume_rpi_ii_WORD word1 2546 #define RESUME_INDEX_RPI 0 2547 #define RESUME_INDEX_VPI 1 2548 #define RESUME_INDEX_VFI 2 2549 #define RESUME_INDEX_FCFI 3 2550 uint32_t event_tag; 2551 }; 2552 2553 #define REG_FCF_INVALID_QID 0xFFFF 2554 struct lpfc_mbx_reg_fcfi { 2555 uint32_t word1; 2556 #define lpfc_reg_fcfi_info_index_SHIFT 0 2557 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2558 #define lpfc_reg_fcfi_info_index_WORD word1 2559 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2560 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2561 #define lpfc_reg_fcfi_fcfi_WORD word1 2562 uint32_t word2; 2563 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2564 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2565 #define lpfc_reg_fcfi_rq_id1_WORD word2 2566 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2567 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2568 #define lpfc_reg_fcfi_rq_id0_WORD word2 2569 uint32_t word3; 2570 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2571 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2572 #define lpfc_reg_fcfi_rq_id3_WORD word3 2573 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2574 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2575 #define lpfc_reg_fcfi_rq_id2_WORD word3 2576 uint32_t word4; 2577 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2578 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2579 #define lpfc_reg_fcfi_type_match0_WORD word4 2580 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2581 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2582 #define lpfc_reg_fcfi_type_mask0_WORD word4 2583 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2584 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2585 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2586 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2587 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2588 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2589 uint32_t word5; 2590 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2591 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2592 #define lpfc_reg_fcfi_type_match1_WORD word5 2593 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2594 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2595 #define lpfc_reg_fcfi_type_mask1_WORD word5 2596 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2597 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2598 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2599 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2600 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2601 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2602 uint32_t word6; 2603 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2604 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2605 #define lpfc_reg_fcfi_type_match2_WORD word6 2606 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2607 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2608 #define lpfc_reg_fcfi_type_mask2_WORD word6 2609 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2610 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2611 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2612 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2613 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2614 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2615 uint32_t word7; 2616 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2617 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2618 #define lpfc_reg_fcfi_type_match3_WORD word7 2619 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2620 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2621 #define lpfc_reg_fcfi_type_mask3_WORD word7 2622 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2623 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2624 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2625 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2626 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2627 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2628 uint32_t word8; 2629 #define lpfc_reg_fcfi_mam_SHIFT 13 2630 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2631 #define lpfc_reg_fcfi_mam_WORD word8 2632 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2633 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2634 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2635 #define lpfc_reg_fcfi_vv_SHIFT 12 2636 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2637 #define lpfc_reg_fcfi_vv_WORD word8 2638 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2639 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2640 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2641 }; 2642 2643 struct lpfc_mbx_reg_fcfi_mrq { 2644 uint32_t word1; 2645 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2646 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2647 #define lpfc_reg_fcfi_mrq_info_index_WORD word1 2648 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2649 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2650 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2651 uint32_t word2; 2652 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2653 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2654 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2655 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2656 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2657 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2658 uint32_t word3; 2659 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2660 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2661 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2662 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2663 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2664 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2665 uint32_t word4; 2666 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2667 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2668 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2669 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2670 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2671 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2672 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2673 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2674 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2675 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2676 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2677 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2678 uint32_t word5; 2679 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2680 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2681 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2682 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2683 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2684 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2685 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2686 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2687 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2688 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2689 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2690 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2691 uint32_t word6; 2692 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2693 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2694 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2695 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2696 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2697 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2698 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2699 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2700 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2701 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2702 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2703 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2704 uint32_t word7; 2705 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2706 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2707 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2708 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2709 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2710 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2711 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2712 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2713 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2714 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2715 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2716 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2717 uint32_t word8; 2718 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2719 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2720 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2721 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2722 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2723 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2724 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2725 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2726 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2727 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2728 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2729 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2730 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2731 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2732 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2733 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2734 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2735 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2736 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2737 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2738 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2739 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2740 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2741 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2742 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2743 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2744 #define lpfc_reg_fcfi_mrq_pt7_WORD word8 2745 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2746 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2747 #define lpfc_reg_fcfi_mrq_pt6_WORD word8 2748 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2749 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2750 #define lpfc_reg_fcfi_mrq_pt5_WORD word8 2751 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2752 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2753 #define lpfc_reg_fcfi_mrq_pt4_WORD word8 2754 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2755 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2756 #define lpfc_reg_fcfi_mrq_pt3_WORD word8 2757 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2758 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2759 #define lpfc_reg_fcfi_mrq_pt2_WORD word8 2760 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2761 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2762 #define lpfc_reg_fcfi_mrq_pt1_WORD word8 2763 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2764 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2765 #define lpfc_reg_fcfi_mrq_pt0_WORD word8 2766 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2767 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2768 #define lpfc_reg_fcfi_mrq_xmv_WORD word8 2769 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2770 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2771 #define lpfc_reg_fcfi_mrq_mode_WORD word8 2772 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2773 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2774 #define lpfc_reg_fcfi_mrq_vv_WORD word8 2775 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2776 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2777 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2778 uint32_t word9; 2779 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2780 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2781 #define lpfc_reg_fcfi_mrq_policy_WORD word9 2782 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2783 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2784 #define lpfc_reg_fcfi_mrq_filter_WORD word9 2785 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2786 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2787 #define lpfc_reg_fcfi_mrq_npairs_WORD word9 2788 uint32_t word10; 2789 uint32_t word11; 2790 uint32_t word12; 2791 uint32_t word13; 2792 uint32_t word14; 2793 uint32_t word15; 2794 uint32_t word16; 2795 }; 2796 2797 struct lpfc_mbx_unreg_fcfi { 2798 uint32_t word1_rsv; 2799 uint32_t word2; 2800 #define lpfc_unreg_fcfi_SHIFT 0 2801 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2802 #define lpfc_unreg_fcfi_WORD word2 2803 }; 2804 2805 struct lpfc_mbx_read_rev { 2806 uint32_t word1; 2807 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2808 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2809 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2810 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2811 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2812 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2813 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2814 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2815 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2816 #define LPFC_PREDCBX_CEE_MODE 0 2817 #define LPFC_DCBX_CEE_MODE 1 2818 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2819 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2820 #define lpfc_mbx_rd_rev_vpd_WORD word1 2821 uint32_t first_hw_rev; 2822 #define LPFC_G7_ASIC_1 0xd 2823 uint32_t second_hw_rev; 2824 uint32_t word4_rsvd; 2825 uint32_t third_hw_rev; 2826 uint32_t word6; 2827 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2828 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2829 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2830 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2831 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2832 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2833 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2834 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2835 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2836 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2837 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2838 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2839 uint32_t word7_rsvd; 2840 uint32_t fw_id_rev; 2841 uint8_t fw_name[16]; 2842 uint32_t ulp_fw_id_rev; 2843 uint8_t ulp_fw_name[16]; 2844 uint32_t word18_47_rsvd[30]; 2845 uint32_t word48; 2846 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2847 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2848 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2849 uint32_t vpd_paddr_low; 2850 uint32_t vpd_paddr_high; 2851 uint32_t avail_vpd_len; 2852 uint32_t rsvd_52_63[12]; 2853 }; 2854 2855 struct lpfc_mbx_read_config { 2856 uint32_t word1; 2857 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2858 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2859 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2860 #define lpfc_mbx_rd_conf_wcs_SHIFT 28 /* warning signaling */ 2861 #define lpfc_mbx_rd_conf_wcs_MASK 0x00000001 2862 #define lpfc_mbx_rd_conf_wcs_WORD word1 2863 #define lpfc_mbx_rd_conf_acs_SHIFT 27 /* alarm signaling */ 2864 #define lpfc_mbx_rd_conf_acs_MASK 0x00000001 2865 #define lpfc_mbx_rd_conf_acs_WORD word1 2866 uint32_t word2; 2867 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2868 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2869 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2870 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2871 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2872 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2873 #define LPFC_LNK_TYPE_GE 0 2874 #define LPFC_LNK_TYPE_FC 1 2875 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2876 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2877 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2878 #define lpfc_mbx_rd_conf_trunk_SHIFT 12 2879 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F 2880 #define lpfc_mbx_rd_conf_trunk_WORD word2 2881 #define lpfc_mbx_rd_conf_pt_SHIFT 20 2882 #define lpfc_mbx_rd_conf_pt_MASK 0x00000003 2883 #define lpfc_mbx_rd_conf_pt_WORD word2 2884 #define lpfc_mbx_rd_conf_tf_SHIFT 22 2885 #define lpfc_mbx_rd_conf_tf_MASK 0x00000001 2886 #define lpfc_mbx_rd_conf_tf_WORD word2 2887 #define lpfc_mbx_rd_conf_ptv_SHIFT 23 2888 #define lpfc_mbx_rd_conf_ptv_MASK 0x00000001 2889 #define lpfc_mbx_rd_conf_ptv_WORD word2 2890 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2891 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2892 #define lpfc_mbx_rd_conf_topology_WORD word2 2893 uint32_t rsvd_3; 2894 uint32_t word4; 2895 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2896 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2897 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2898 uint32_t rsvd_5; 2899 uint32_t word6; 2900 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2901 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2902 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2903 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2904 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2905 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2906 uint32_t rsvd_7; 2907 uint32_t word8; 2908 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2909 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2910 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2911 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2912 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2913 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2914 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2915 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2916 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2917 uint32_t word9; 2918 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2919 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2920 #define lpfc_mbx_rd_conf_lmt_WORD word9 2921 uint32_t rsvd_10; 2922 uint32_t rsvd_11; 2923 uint32_t word12; 2924 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2925 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2926 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2927 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2928 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2929 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2930 uint32_t word13; 2931 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2932 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2933 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2934 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2935 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2936 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2937 uint32_t word14; 2938 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2939 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2940 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2941 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2942 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2943 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2944 uint32_t word15; 2945 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2946 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2947 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2948 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2949 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2950 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2951 uint32_t word16; 2952 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2953 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2954 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2955 uint32_t word17; 2956 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2957 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2958 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2959 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2960 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2961 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2962 uint32_t word18; 2963 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2964 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2965 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2966 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2967 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2968 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2969 }; 2970 2971 struct lpfc_mbx_request_features { 2972 uint32_t word1; 2973 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2974 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2975 #define lpfc_mbx_rq_ftr_qry_WORD word1 2976 uint32_t word2; 2977 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2978 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2979 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2980 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2981 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2982 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2983 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2984 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2985 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2986 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2987 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2988 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2989 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2990 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2991 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2992 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2993 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2994 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2995 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2996 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2997 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2998 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2999 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 3000 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 3001 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 3002 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 3003 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 3004 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 3005 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 3006 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 3007 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 3008 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 3009 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 3010 #define lpfc_mbx_rq_ftr_rq_ashdr_SHIFT 17 3011 #define lpfc_mbx_rq_ftr_rq_ashdr_MASK 0x00000001 3012 #define lpfc_mbx_rq_ftr_rq_ashdr_WORD word2 3013 uint32_t word3; 3014 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 3015 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 3016 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 3017 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 3018 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 3019 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 3020 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 3021 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 3022 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 3023 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 3024 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 3025 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 3026 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 3027 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 3028 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 3029 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 3030 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 3031 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 3032 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 3033 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 3034 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 3035 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 3036 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 3037 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 3038 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 3039 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 3040 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 3041 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 3042 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 3043 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 3044 #define lpfc_mbx_rq_ftr_rsp_ashdr_SHIFT 17 3045 #define lpfc_mbx_rq_ftr_rsp_ashdr_MASK 0x00000001 3046 #define lpfc_mbx_rq_ftr_rsp_ashdr_WORD word3 3047 }; 3048 3049 struct lpfc_mbx_memory_dump_type3 { 3050 uint32_t word1; 3051 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 3052 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 3053 #define lpfc_mbx_memory_dump_type3_type_WORD word1 3054 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 3055 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 3056 #define lpfc_mbx_memory_dump_type3_link_WORD word1 3057 uint32_t word2; 3058 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 3059 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3060 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3061 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3062 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3063 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 3064 uint32_t word3; 3065 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3066 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3067 #define lpfc_mbx_memory_dump_type3_length_WORD word3 3068 uint32_t addr_lo; 3069 uint32_t addr_hi; 3070 uint32_t return_len; 3071 }; 3072 3073 #define DMP_PAGE_A0 0xa0 3074 #define DMP_PAGE_A2 0xa2 3075 #define DMP_SFF_PAGE_A0_SIZE 256 3076 #define DMP_SFF_PAGE_A2_SIZE 256 3077 3078 #define SFP_WAVELENGTH_LC1310 1310 3079 #define SFP_WAVELENGTH_LL1550 1550 3080 3081 3082 /* 3083 * * SFF-8472 TABLE 3.4 3084 * */ 3085 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3086 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3087 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3088 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3089 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3090 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3091 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3092 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3093 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3094 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3095 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3096 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3097 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3098 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3099 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3100 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3101 3102 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3103 3104 #define SSF_IDENTIFIER 0 3105 #define SSF_EXT_IDENTIFIER 1 3106 #define SSF_CONNECTOR 2 3107 #define SSF_TRANSCEIVER_CODE_B0 3 3108 #define SSF_TRANSCEIVER_CODE_B1 4 3109 #define SSF_TRANSCEIVER_CODE_B2 5 3110 #define SSF_TRANSCEIVER_CODE_B3 6 3111 #define SSF_TRANSCEIVER_CODE_B4 7 3112 #define SSF_TRANSCEIVER_CODE_B5 8 3113 #define SSF_TRANSCEIVER_CODE_B6 9 3114 #define SSF_TRANSCEIVER_CODE_B7 10 3115 #define SSF_ENCODING 11 3116 #define SSF_BR_NOMINAL 12 3117 #define SSF_RATE_IDENTIFIER 13 3118 #define SSF_LENGTH_9UM_KM 14 3119 #define SSF_LENGTH_9UM 15 3120 #define SSF_LENGTH_50UM_OM2 16 3121 #define SSF_LENGTH_62UM_OM1 17 3122 #define SFF_LENGTH_COPPER 18 3123 #define SSF_LENGTH_50UM_OM3 19 3124 #define SSF_VENDOR_NAME 20 3125 #define SSF_VENDOR_OUI 36 3126 #define SSF_VENDOR_PN 40 3127 #define SSF_VENDOR_REV 56 3128 #define SSF_WAVELENGTH_B1 60 3129 #define SSF_WAVELENGTH_B0 61 3130 #define SSF_CC_BASE 63 3131 #define SSF_OPTIONS_B1 64 3132 #define SSF_OPTIONS_B0 65 3133 #define SSF_BR_MAX 66 3134 #define SSF_BR_MIN 67 3135 #define SSF_VENDOR_SN 68 3136 #define SSF_DATE_CODE 84 3137 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 3138 #define SSF_ENHANCED_OPTIONS 93 3139 #define SFF_8472_COMPLIANCE 94 3140 #define SSF_CC_EXT 95 3141 #define SSF_A0_VENDOR_SPECIFIC 96 3142 3143 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3144 3145 #define SSF_TEMP_HIGH_ALARM 0 3146 #define SSF_TEMP_LOW_ALARM 2 3147 #define SSF_TEMP_HIGH_WARNING 4 3148 #define SSF_TEMP_LOW_WARNING 6 3149 #define SSF_VOLTAGE_HIGH_ALARM 8 3150 #define SSF_VOLTAGE_LOW_ALARM 10 3151 #define SSF_VOLTAGE_HIGH_WARNING 12 3152 #define SSF_VOLTAGE_LOW_WARNING 14 3153 #define SSF_BIAS_HIGH_ALARM 16 3154 #define SSF_BIAS_LOW_ALARM 18 3155 #define SSF_BIAS_HIGH_WARNING 20 3156 #define SSF_BIAS_LOW_WARNING 22 3157 #define SSF_TXPOWER_HIGH_ALARM 24 3158 #define SSF_TXPOWER_LOW_ALARM 26 3159 #define SSF_TXPOWER_HIGH_WARNING 28 3160 #define SSF_TXPOWER_LOW_WARNING 30 3161 #define SSF_RXPOWER_HIGH_ALARM 32 3162 #define SSF_RXPOWER_LOW_ALARM 34 3163 #define SSF_RXPOWER_HIGH_WARNING 36 3164 #define SSF_RXPOWER_LOW_WARNING 38 3165 #define SSF_EXT_CAL_CONSTANTS 56 3166 #define SSF_CC_DMI 95 3167 #define SFF_TEMPERATURE_B1 96 3168 #define SFF_TEMPERATURE_B0 97 3169 #define SFF_VCC_B1 98 3170 #define SFF_VCC_B0 99 3171 #define SFF_TX_BIAS_CURRENT_B1 100 3172 #define SFF_TX_BIAS_CURRENT_B0 101 3173 #define SFF_TXPOWER_B1 102 3174 #define SFF_TXPOWER_B0 103 3175 #define SFF_RXPOWER_B1 104 3176 #define SFF_RXPOWER_B0 105 3177 #define SSF_STATUS_CONTROL 110 3178 #define SSF_ALARM_FLAGS 112 3179 #define SSF_WARNING_FLAGS 116 3180 #define SSF_EXT_TATUS_CONTROL_B1 118 3181 #define SSF_EXT_TATUS_CONTROL_B0 119 3182 #define SSF_A2_VENDOR_SPECIFIC 120 3183 #define SSF_USER_EEPROM 128 3184 #define SSF_VENDOR_CONTROL 148 3185 3186 3187 /* 3188 * Tranceiver codes Fibre Channel SFF-8472 3189 * Table 3.5. 3190 */ 3191 3192 struct sff_trasnceiver_codes_byte0 { 3193 uint8_t inifiband:4; 3194 uint8_t teng_ethernet:4; 3195 }; 3196 3197 struct sff_trasnceiver_codes_byte1 { 3198 uint8_t sonet:6; 3199 uint8_t escon:2; 3200 }; 3201 3202 struct sff_trasnceiver_codes_byte2 { 3203 uint8_t soNet:8; 3204 }; 3205 3206 struct sff_trasnceiver_codes_byte3 { 3207 uint8_t ethernet:8; 3208 }; 3209 3210 struct sff_trasnceiver_codes_byte4 { 3211 uint8_t fc_el_lo:1; 3212 uint8_t fc_lw_laser:1; 3213 uint8_t fc_sw_laser:1; 3214 uint8_t fc_md_distance:1; 3215 uint8_t fc_lg_distance:1; 3216 uint8_t fc_int_distance:1; 3217 uint8_t fc_short_distance:1; 3218 uint8_t fc_vld_distance:1; 3219 }; 3220 3221 struct sff_trasnceiver_codes_byte5 { 3222 uint8_t reserved1:1; 3223 uint8_t reserved2:1; 3224 uint8_t fc_sfp_active:1; /* Active cable */ 3225 uint8_t fc_sfp_passive:1; /* Passive cable */ 3226 uint8_t fc_lw_laser:1; /* Longwave laser */ 3227 uint8_t fc_sw_laser_sl:1; 3228 uint8_t fc_sw_laser_sn:1; 3229 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3230 }; 3231 3232 struct sff_trasnceiver_codes_byte6 { 3233 uint8_t fc_tm_sm:1; /* Single Mode */ 3234 uint8_t reserved:1; 3235 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3236 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3237 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3238 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3239 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3240 }; 3241 3242 struct sff_trasnceiver_codes_byte7 { 3243 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3244 uint8_t reserve:1; 3245 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3246 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3247 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3248 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3249 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3250 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3251 }; 3252 3253 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3254 struct user_eeprom { 3255 uint8_t vendor_name[16]; 3256 uint8_t vendor_oui[3]; 3257 uint8_t vendor_pn[816]; 3258 uint8_t vendor_rev[4]; 3259 uint8_t vendor_sn[16]; 3260 uint8_t datecode[6]; 3261 uint8_t lot_code[2]; 3262 uint8_t reserved191[57]; 3263 }; 3264 3265 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3266 &(~((SLI4_PAGE_SIZE)-1))) 3267 3268 struct lpfc_sli4_parameters { 3269 uint32_t word0; 3270 #define cfg_prot_type_SHIFT 0 3271 #define cfg_prot_type_MASK 0x000000FF 3272 #define cfg_prot_type_WORD word0 3273 uint32_t word1; 3274 #define cfg_ft_SHIFT 0 3275 #define cfg_ft_MASK 0x00000001 3276 #define cfg_ft_WORD word1 3277 #define cfg_sli_rev_SHIFT 4 3278 #define cfg_sli_rev_MASK 0x0000000f 3279 #define cfg_sli_rev_WORD word1 3280 #define cfg_sli_family_SHIFT 8 3281 #define cfg_sli_family_MASK 0x0000000f 3282 #define cfg_sli_family_WORD word1 3283 #define cfg_if_type_SHIFT 12 3284 #define cfg_if_type_MASK 0x0000000f 3285 #define cfg_if_type_WORD word1 3286 #define cfg_sli_hint_1_SHIFT 16 3287 #define cfg_sli_hint_1_MASK 0x000000ff 3288 #define cfg_sli_hint_1_WORD word1 3289 #define cfg_sli_hint_2_SHIFT 24 3290 #define cfg_sli_hint_2_MASK 0x0000001f 3291 #define cfg_sli_hint_2_WORD word1 3292 uint32_t word2; 3293 #define cfg_eqav_SHIFT 31 3294 #define cfg_eqav_MASK 0x00000001 3295 #define cfg_eqav_WORD word2 3296 uint32_t word3; 3297 uint32_t word4; 3298 #define cfg_cqv_SHIFT 14 3299 #define cfg_cqv_MASK 0x00000003 3300 #define cfg_cqv_WORD word4 3301 #define cfg_cqpsize_SHIFT 16 3302 #define cfg_cqpsize_MASK 0x000000ff 3303 #define cfg_cqpsize_WORD word4 3304 #define cfg_cqav_SHIFT 31 3305 #define cfg_cqav_MASK 0x00000001 3306 #define cfg_cqav_WORD word4 3307 uint32_t word5; 3308 uint32_t word6; 3309 #define cfg_mqv_SHIFT 14 3310 #define cfg_mqv_MASK 0x00000003 3311 #define cfg_mqv_WORD word6 3312 uint32_t word7; 3313 uint32_t word8; 3314 #define cfg_wqpcnt_SHIFT 0 3315 #define cfg_wqpcnt_MASK 0x0000000f 3316 #define cfg_wqpcnt_WORD word8 3317 #define cfg_wqsize_SHIFT 8 3318 #define cfg_wqsize_MASK 0x0000000f 3319 #define cfg_wqsize_WORD word8 3320 #define cfg_wqv_SHIFT 14 3321 #define cfg_wqv_MASK 0x00000003 3322 #define cfg_wqv_WORD word8 3323 #define cfg_wqpsize_SHIFT 16 3324 #define cfg_wqpsize_MASK 0x000000ff 3325 #define cfg_wqpsize_WORD word8 3326 uint32_t word9; 3327 uint32_t word10; 3328 #define cfg_rqv_SHIFT 14 3329 #define cfg_rqv_MASK 0x00000003 3330 #define cfg_rqv_WORD word10 3331 uint32_t word11; 3332 #define cfg_rq_db_window_SHIFT 28 3333 #define cfg_rq_db_window_MASK 0x0000000f 3334 #define cfg_rq_db_window_WORD word11 3335 uint32_t word12; 3336 #define cfg_fcoe_SHIFT 0 3337 #define cfg_fcoe_MASK 0x00000001 3338 #define cfg_fcoe_WORD word12 3339 #define cfg_ext_SHIFT 1 3340 #define cfg_ext_MASK 0x00000001 3341 #define cfg_ext_WORD word12 3342 #define cfg_hdrr_SHIFT 2 3343 #define cfg_hdrr_MASK 0x00000001 3344 #define cfg_hdrr_WORD word12 3345 #define cfg_phwq_SHIFT 15 3346 #define cfg_phwq_MASK 0x00000001 3347 #define cfg_phwq_WORD word12 3348 #define cfg_oas_SHIFT 25 3349 #define cfg_oas_MASK 0x00000001 3350 #define cfg_oas_WORD word12 3351 #define cfg_loopbk_scope_SHIFT 28 3352 #define cfg_loopbk_scope_MASK 0x0000000f 3353 #define cfg_loopbk_scope_WORD word12 3354 uint32_t sge_supp_len; 3355 uint32_t word14; 3356 #define cfg_sgl_page_cnt_SHIFT 0 3357 #define cfg_sgl_page_cnt_MASK 0x0000000f 3358 #define cfg_sgl_page_cnt_WORD word14 3359 #define cfg_sgl_page_size_SHIFT 8 3360 #define cfg_sgl_page_size_MASK 0x000000ff 3361 #define cfg_sgl_page_size_WORD word14 3362 #define cfg_sgl_pp_align_SHIFT 16 3363 #define cfg_sgl_pp_align_MASK 0x000000ff 3364 #define cfg_sgl_pp_align_WORD word14 3365 uint32_t word15; 3366 uint32_t word16; 3367 uint32_t word17; 3368 uint32_t word18; 3369 uint32_t word19; 3370 #define cfg_ext_embed_cb_SHIFT 0 3371 #define cfg_ext_embed_cb_MASK 0x00000001 3372 #define cfg_ext_embed_cb_WORD word19 3373 #define cfg_mds_diags_SHIFT 1 3374 #define cfg_mds_diags_MASK 0x00000001 3375 #define cfg_mds_diags_WORD word19 3376 #define cfg_nvme_SHIFT 3 3377 #define cfg_nvme_MASK 0x00000001 3378 #define cfg_nvme_WORD word19 3379 #define cfg_xib_SHIFT 4 3380 #define cfg_xib_MASK 0x00000001 3381 #define cfg_xib_WORD word19 3382 #define cfg_xpsgl_SHIFT 6 3383 #define cfg_xpsgl_MASK 0x00000001 3384 #define cfg_xpsgl_WORD word19 3385 #define cfg_eqdr_SHIFT 8 3386 #define cfg_eqdr_MASK 0x00000001 3387 #define cfg_eqdr_WORD word19 3388 #define cfg_nosr_SHIFT 9 3389 #define cfg_nosr_MASK 0x00000001 3390 #define cfg_nosr_WORD word19 3391 #define cfg_bv1s_SHIFT 10 3392 #define cfg_bv1s_MASK 0x00000001 3393 #define cfg_bv1s_WORD word19 3394 3395 #define cfg_nsler_SHIFT 12 3396 #define cfg_nsler_MASK 0x00000001 3397 #define cfg_nsler_WORD word19 3398 #define cfg_pvl_SHIFT 13 3399 #define cfg_pvl_MASK 0x00000001 3400 #define cfg_pvl_WORD word19 3401 3402 #define cfg_pbde_SHIFT 20 3403 #define cfg_pbde_MASK 0x00000001 3404 #define cfg_pbde_WORD word19 3405 3406 uint32_t word20; 3407 #define cfg_max_tow_xri_SHIFT 0 3408 #define cfg_max_tow_xri_MASK 0x0000ffff 3409 #define cfg_max_tow_xri_WORD word20 3410 3411 uint32_t word21; 3412 #define cfg_mi_ver_SHIFT 0 3413 #define cfg_mi_ver_MASK 0x0000ffff 3414 #define cfg_mi_ver_WORD word21 3415 #define cfg_cmf_SHIFT 24 3416 #define cfg_cmf_MASK 0x000000ff 3417 #define cfg_cmf_WORD word21 3418 3419 uint32_t mib_size; 3420 uint32_t word23; /* RESERVED */ 3421 3422 uint32_t word24; 3423 #define cfg_frag_field_offset_SHIFT 0 3424 #define cfg_frag_field_offset_MASK 0x0000ffff 3425 #define cfg_frag_field_offset_WORD word24 3426 3427 #define cfg_frag_field_size_SHIFT 16 3428 #define cfg_frag_field_size_MASK 0x0000ffff 3429 #define cfg_frag_field_size_WORD word24 3430 3431 uint32_t word25; 3432 #define cfg_sgl_field_offset_SHIFT 0 3433 #define cfg_sgl_field_offset_MASK 0x0000ffff 3434 #define cfg_sgl_field_offset_WORD word25 3435 3436 #define cfg_sgl_field_size_SHIFT 16 3437 #define cfg_sgl_field_size_MASK 0x0000ffff 3438 #define cfg_sgl_field_size_WORD word25 3439 3440 uint32_t word26; /* Chain SGE initial value LOW */ 3441 uint32_t word27; /* Chain SGE initial value HIGH */ 3442 #define LPFC_NODELAY_MAX_IO 32 3443 }; 3444 3445 #define LPFC_SET_UE_RECOVERY 0x10 3446 #define LPFC_SET_MDS_DIAGS 0x12 3447 #define LPFC_SET_CGN_SIGNAL 0x1f 3448 #define LPFC_SET_DUAL_DUMP 0x1e 3449 #define LPFC_SET_ENABLE_MI 0x21 3450 #define LPFC_SET_ENABLE_CMF 0x24 3451 struct lpfc_mbx_set_feature { 3452 struct mbox_header header; 3453 uint32_t feature; 3454 uint32_t param_len; 3455 uint32_t word6; 3456 #define lpfc_mbx_set_feature_UER_SHIFT 0 3457 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 3458 #define lpfc_mbx_set_feature_UER_WORD word6 3459 #define lpfc_mbx_set_feature_mds_SHIFT 2 3460 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 3461 #define lpfc_mbx_set_feature_mds_WORD word6 3462 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3463 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3464 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3465 #define lpfc_mbx_set_feature_CGN_warn_freq_SHIFT 0 3466 #define lpfc_mbx_set_feature_CGN_warn_freq_MASK 0x0000ffff 3467 #define lpfc_mbx_set_feature_CGN_warn_freq_WORD word6 3468 #define lpfc_mbx_set_feature_dd_SHIFT 0 3469 #define lpfc_mbx_set_feature_dd_MASK 0x00000001 3470 #define lpfc_mbx_set_feature_dd_WORD word6 3471 #define lpfc_mbx_set_feature_ddquery_SHIFT 1 3472 #define lpfc_mbx_set_feature_ddquery_MASK 0x00000001 3473 #define lpfc_mbx_set_feature_ddquery_WORD word6 3474 #define LPFC_DISABLE_DUAL_DUMP 0 3475 #define LPFC_ENABLE_DUAL_DUMP 1 3476 #define LPFC_QUERY_OP_DUAL_DUMP 2 3477 #define lpfc_mbx_set_feature_cmf_SHIFT 0 3478 #define lpfc_mbx_set_feature_cmf_MASK 0x00000001 3479 #define lpfc_mbx_set_feature_cmf_WORD word6 3480 #define lpfc_mbx_set_feature_mi_SHIFT 0 3481 #define lpfc_mbx_set_feature_mi_MASK 0x0000ffff 3482 #define lpfc_mbx_set_feature_mi_WORD word6 3483 #define lpfc_mbx_set_feature_milunq_SHIFT 16 3484 #define lpfc_mbx_set_feature_milunq_MASK 0x0000ffff 3485 #define lpfc_mbx_set_feature_milunq_WORD word6 3486 uint32_t word7; 3487 #define lpfc_mbx_set_feature_UERP_SHIFT 0 3488 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3489 #define lpfc_mbx_set_feature_UERP_WORD word7 3490 #define lpfc_mbx_set_feature_UESR_SHIFT 16 3491 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3492 #define lpfc_mbx_set_feature_UESR_WORD word7 3493 #define lpfc_mbx_set_feature_CGN_alarm_freq_SHIFT 0 3494 #define lpfc_mbx_set_feature_CGN_alarm_freq_MASK 0x0000ffff 3495 #define lpfc_mbx_set_feature_CGN_alarm_freq_WORD word7 3496 u32 word8; 3497 #define lpfc_mbx_set_feature_CGN_acqe_freq_SHIFT 0 3498 #define lpfc_mbx_set_feature_CGN_acqe_freq_MASK 0x000000ff 3499 #define lpfc_mbx_set_feature_CGN_acqe_freq_WORD word8 3500 }; 3501 3502 3503 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3504 #define LPFC_SET_HOST_DATE_TIME 0x4 3505 3506 struct lpfc_mbx_set_host_date_time { 3507 uint32_t word6; 3508 #define lpfc_mbx_set_host_month_WORD word6 3509 #define lpfc_mbx_set_host_month_SHIFT 16 3510 #define lpfc_mbx_set_host_month_MASK 0xFF 3511 #define lpfc_mbx_set_host_day_WORD word6 3512 #define lpfc_mbx_set_host_day_SHIFT 8 3513 #define lpfc_mbx_set_host_day_MASK 0xFF 3514 #define lpfc_mbx_set_host_year_WORD word6 3515 #define lpfc_mbx_set_host_year_SHIFT 0 3516 #define lpfc_mbx_set_host_year_MASK 0xFF 3517 uint32_t word7; 3518 #define lpfc_mbx_set_host_hour_WORD word7 3519 #define lpfc_mbx_set_host_hour_SHIFT 16 3520 #define lpfc_mbx_set_host_hour_MASK 0xFF 3521 #define lpfc_mbx_set_host_min_WORD word7 3522 #define lpfc_mbx_set_host_min_SHIFT 8 3523 #define lpfc_mbx_set_host_min_MASK 0xFF 3524 #define lpfc_mbx_set_host_sec_WORD word7 3525 #define lpfc_mbx_set_host_sec_SHIFT 0 3526 #define lpfc_mbx_set_host_sec_MASK 0xFF 3527 }; 3528 3529 struct lpfc_mbx_set_host_data { 3530 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3531 struct mbox_header header; 3532 uint32_t param_id; 3533 uint32_t param_len; 3534 union { 3535 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3536 struct lpfc_mbx_set_host_date_time tm; 3537 } un; 3538 }; 3539 3540 struct lpfc_mbx_set_trunk_mode { 3541 struct mbox_header header; 3542 uint32_t word0; 3543 #define lpfc_mbx_set_trunk_mode_WORD word0 3544 #define lpfc_mbx_set_trunk_mode_SHIFT 0 3545 #define lpfc_mbx_set_trunk_mode_MASK 0xFF 3546 uint32_t word1; 3547 uint32_t word2; 3548 }; 3549 3550 struct lpfc_mbx_get_sli4_parameters { 3551 struct mbox_header header; 3552 struct lpfc_sli4_parameters sli4_parameters; 3553 }; 3554 3555 struct lpfc_mbx_reg_congestion_buf { 3556 struct mbox_header header; 3557 uint32_t word0; 3558 #define lpfc_mbx_reg_cgn_buf_type_WORD word0 3559 #define lpfc_mbx_reg_cgn_buf_type_SHIFT 0 3560 #define lpfc_mbx_reg_cgn_buf_type_MASK 0xFF 3561 #define lpfc_mbx_reg_cgn_buf_cnt_WORD word0 3562 #define lpfc_mbx_reg_cgn_buf_cnt_SHIFT 16 3563 #define lpfc_mbx_reg_cgn_buf_cnt_MASK 0xFF 3564 uint32_t word1; 3565 uint32_t length; 3566 uint32_t addr_lo; 3567 uint32_t addr_hi; 3568 }; 3569 3570 struct lpfc_rscr_desc_generic { 3571 #define LPFC_RSRC_DESC_WSIZE 22 3572 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3573 }; 3574 3575 struct lpfc_rsrc_desc_pcie { 3576 uint32_t word0; 3577 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 3578 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3579 #define lpfc_rsrc_desc_pcie_type_WORD word0 3580 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3581 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 3582 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3583 #define lpfc_rsrc_desc_pcie_length_WORD word0 3584 uint32_t word1; 3585 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3586 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3587 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3588 uint32_t reserved; 3589 uint32_t word3; 3590 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3591 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3592 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3593 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3594 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3595 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3596 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3597 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3598 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3599 uint32_t word4; 3600 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3601 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3602 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3603 }; 3604 3605 struct lpfc_rsrc_desc_fcfcoe { 3606 uint32_t word0; 3607 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3608 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3609 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3610 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3611 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3612 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3613 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3614 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3615 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3616 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3617 uint32_t word1; 3618 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3619 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3620 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3621 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3622 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3623 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3624 uint32_t word2; 3625 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3626 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3627 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3628 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3629 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3630 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3631 uint32_t word3; 3632 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3633 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3634 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3635 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3636 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3637 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3638 uint32_t word4; 3639 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3640 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3641 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3642 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3643 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3644 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3645 uint32_t word5; 3646 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3647 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3648 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3649 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3650 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3651 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3652 uint32_t word6; 3653 uint32_t word7; 3654 uint32_t word8; 3655 uint32_t word9; 3656 uint32_t word10; 3657 uint32_t word11; 3658 uint32_t word12; 3659 uint32_t word13; 3660 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3661 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3662 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3663 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3664 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3665 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3666 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3667 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3668 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3669 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3670 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3671 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3672 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3673 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3674 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3675 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3676 uint32_t bw_min; 3677 uint32_t bw_max; 3678 uint32_t iops_min; 3679 uint32_t iops_max; 3680 uint32_t reserved[4]; 3681 }; 3682 3683 struct lpfc_func_cfg { 3684 #define LPFC_RSRC_DESC_MAX_NUM 2 3685 uint32_t rsrc_desc_count; 3686 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3687 }; 3688 3689 struct lpfc_mbx_get_func_cfg { 3690 struct mbox_header header; 3691 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3692 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3693 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3694 struct lpfc_func_cfg func_cfg; 3695 }; 3696 3697 struct lpfc_prof_cfg { 3698 #define LPFC_RSRC_DESC_MAX_NUM 2 3699 uint32_t rsrc_desc_count; 3700 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3701 }; 3702 3703 struct lpfc_mbx_get_prof_cfg { 3704 struct mbox_header header; 3705 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3706 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3707 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3708 union { 3709 struct { 3710 uint32_t word10; 3711 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3712 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3713 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3714 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3715 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3716 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3717 } request; 3718 struct { 3719 struct lpfc_prof_cfg prof_cfg; 3720 } response; 3721 } u; 3722 }; 3723 3724 struct lpfc_controller_attribute { 3725 uint32_t version_string[8]; 3726 uint32_t manufacturer_name[8]; 3727 uint32_t supported_modes; 3728 uint32_t word17; 3729 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3730 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3731 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3732 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3733 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3734 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3735 #define lpfc_cntl_attr_flash_id_SHIFT 16 3736 #define lpfc_cntl_attr_flash_id_MASK 0x000000ff 3737 #define lpfc_cntl_attr_flash_id_WORD word17 3738 uint32_t mbx_da_struct_ver; 3739 uint32_t ep_fw_da_struct_ver; 3740 uint32_t ncsi_ver_str[3]; 3741 uint32_t dflt_ext_timeout; 3742 uint32_t model_number[8]; 3743 uint32_t description[16]; 3744 uint32_t serial_number[8]; 3745 uint32_t ip_ver_str[8]; 3746 uint32_t fw_ver_str[8]; 3747 uint32_t bios_ver_str[8]; 3748 uint32_t redboot_ver_str[8]; 3749 uint32_t driver_ver_str[8]; 3750 uint32_t flash_fw_ver_str[8]; 3751 uint32_t functionality; 3752 uint32_t word105; 3753 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3754 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3755 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3756 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3757 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3758 #define lpfc_cntl_attr_asic_rev_WORD word105 3759 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3760 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3761 #define lpfc_cntl_attr_gen_guid0_WORD word105 3762 uint32_t gen_guid1_12[3]; 3763 uint32_t word109; 3764 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3765 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3766 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3767 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3768 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3769 #define lpfc_cntl_attr_gen_guid15_WORD word109 3770 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3771 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3772 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3773 uint32_t word110; 3774 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3775 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3776 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3777 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3778 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3779 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3780 uint32_t word111; 3781 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3782 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3783 #define lpfc_cntl_attr_cache_valid_WORD word111 3784 #define lpfc_cntl_attr_hba_status_SHIFT 8 3785 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3786 #define lpfc_cntl_attr_hba_status_WORD word111 3787 #define lpfc_cntl_attr_max_domain_SHIFT 16 3788 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3789 #define lpfc_cntl_attr_max_domain_WORD word111 3790 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3791 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3792 #define lpfc_cntl_attr_lnk_numb_WORD word111 3793 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3794 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3795 #define lpfc_cntl_attr_lnk_type_WORD word111 3796 uint32_t fw_post_status; 3797 uint32_t hba_mtu[8]; 3798 uint32_t word121; 3799 uint32_t reserved1[3]; 3800 uint32_t word125; 3801 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3802 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3803 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3804 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3805 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3806 #define lpfc_cntl_attr_pci_device_id_WORD word125 3807 uint32_t word126; 3808 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3809 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3810 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3811 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3812 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3813 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3814 uint32_t word127; 3815 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3816 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3817 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3818 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3819 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3820 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3821 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3822 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3823 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3824 #define lpfc_cntl_attr_inf_type_SHIFT 24 3825 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3826 #define lpfc_cntl_attr_inf_type_WORD word127 3827 uint32_t unique_id[2]; 3828 uint32_t word130; 3829 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3830 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3831 #define lpfc_cntl_attr_num_netfil_WORD word130 3832 uint32_t reserved2[4]; 3833 }; 3834 3835 struct lpfc_mbx_get_cntl_attributes { 3836 union lpfc_sli4_cfg_shdr cfg_shdr; 3837 struct lpfc_controller_attribute cntl_attr; 3838 }; 3839 3840 struct lpfc_mbx_get_port_name { 3841 struct mbox_header header; 3842 union { 3843 struct { 3844 uint32_t word4; 3845 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3846 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3847 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3848 } request; 3849 struct { 3850 uint32_t word4; 3851 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3852 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3853 #define lpfc_mbx_get_port_name_name0_WORD word4 3854 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3855 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3856 #define lpfc_mbx_get_port_name_name1_WORD word4 3857 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3858 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3859 #define lpfc_mbx_get_port_name_name2_WORD word4 3860 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3861 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3862 #define lpfc_mbx_get_port_name_name3_WORD word4 3863 #define LPFC_LINK_NUMBER_0 0 3864 #define LPFC_LINK_NUMBER_1 1 3865 #define LPFC_LINK_NUMBER_2 2 3866 #define LPFC_LINK_NUMBER_3 3 3867 } response; 3868 } u; 3869 }; 3870 3871 /* Mailbox Completion Queue Error Messages */ 3872 #define MB_CQE_STATUS_SUCCESS 0x0 3873 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3874 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3875 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3876 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3877 #define MB_CQE_STATUS_DMA_FAILED 0x5 3878 3879 3880 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3881 struct lpfc_mbx_wr_object { 3882 struct mbox_header header; 3883 union { 3884 struct { 3885 uint32_t word4; 3886 #define lpfc_wr_object_eof_SHIFT 31 3887 #define lpfc_wr_object_eof_MASK 0x00000001 3888 #define lpfc_wr_object_eof_WORD word4 3889 #define lpfc_wr_object_eas_SHIFT 29 3890 #define lpfc_wr_object_eas_MASK 0x00000001 3891 #define lpfc_wr_object_eas_WORD word4 3892 #define lpfc_wr_object_write_length_SHIFT 0 3893 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3894 #define lpfc_wr_object_write_length_WORD word4 3895 uint32_t write_offset; 3896 uint32_t object_name[LPFC_MBX_OBJECT_NAME_LEN_DW]; 3897 uint32_t bde_count; 3898 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3899 } request; 3900 struct { 3901 uint32_t actual_write_length; 3902 uint32_t word5; 3903 #define lpfc_wr_object_change_status_SHIFT 0 3904 #define lpfc_wr_object_change_status_MASK 0x000000FF 3905 #define lpfc_wr_object_change_status_WORD word5 3906 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00 3907 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01 3908 #define LPFC_CHANGE_STATUS_FW_RESET 0x02 3909 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04 3910 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05 3911 #define lpfc_wr_object_csf_SHIFT 8 3912 #define lpfc_wr_object_csf_MASK 0x00000001 3913 #define lpfc_wr_object_csf_WORD word5 3914 } response; 3915 } u; 3916 }; 3917 3918 /* mailbox queue entry structure */ 3919 struct lpfc_mqe { 3920 uint32_t word0; 3921 #define lpfc_mqe_status_SHIFT 16 3922 #define lpfc_mqe_status_MASK 0x0000FFFF 3923 #define lpfc_mqe_status_WORD word0 3924 #define lpfc_mqe_command_SHIFT 8 3925 #define lpfc_mqe_command_MASK 0x000000FF 3926 #define lpfc_mqe_command_WORD word0 3927 union { 3928 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3929 /* sli4 mailbox commands */ 3930 struct lpfc_mbx_sli4_config sli4_config; 3931 struct lpfc_mbx_init_vfi init_vfi; 3932 struct lpfc_mbx_reg_vfi reg_vfi; 3933 struct lpfc_mbx_reg_vfi unreg_vfi; 3934 struct lpfc_mbx_init_vpi init_vpi; 3935 struct lpfc_mbx_resume_rpi resume_rpi; 3936 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3937 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3938 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3939 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3940 struct lpfc_mbx_reg_fcfi reg_fcfi; 3941 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3942 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3943 struct lpfc_mbx_mq_create mq_create; 3944 struct lpfc_mbx_mq_create_ext mq_create_ext; 3945 struct lpfc_mbx_read_object read_object; 3946 struct lpfc_mbx_eq_create eq_create; 3947 struct lpfc_mbx_modify_eq_delay eq_delay; 3948 struct lpfc_mbx_cq_create cq_create; 3949 struct lpfc_mbx_cq_create_set cq_create_set; 3950 struct lpfc_mbx_wq_create wq_create; 3951 struct lpfc_mbx_rq_create rq_create; 3952 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3953 struct lpfc_mbx_mq_destroy mq_destroy; 3954 struct lpfc_mbx_eq_destroy eq_destroy; 3955 struct lpfc_mbx_cq_destroy cq_destroy; 3956 struct lpfc_mbx_wq_destroy wq_destroy; 3957 struct lpfc_mbx_rq_destroy rq_destroy; 3958 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3959 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3960 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3961 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3962 struct lpfc_mbx_nembed_cmd nembed_cmd; 3963 struct lpfc_mbx_read_rev read_rev; 3964 struct lpfc_mbx_read_vpi read_vpi; 3965 struct lpfc_mbx_read_config rd_config; 3966 struct lpfc_mbx_request_features req_ftrs; 3967 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3968 struct lpfc_mbx_query_fw_config query_fw_cfg; 3969 struct lpfc_mbx_set_beacon_config beacon_config; 3970 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3971 struct lpfc_mbx_reg_congestion_buf reg_congestion_buf; 3972 struct lpfc_mbx_set_link_diag_state link_diag_state; 3973 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3974 struct lpfc_mbx_run_link_diag_test link_diag_test; 3975 struct lpfc_mbx_get_func_cfg get_func_cfg; 3976 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3977 struct lpfc_mbx_wr_object wr_object; 3978 struct lpfc_mbx_get_port_name get_port_name; 3979 struct lpfc_mbx_set_feature set_feature; 3980 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3981 struct lpfc_mbx_set_host_data set_host_data; 3982 struct lpfc_mbx_set_trunk_mode set_trunk_mode; 3983 struct lpfc_mbx_nop nop; 3984 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 3985 } un; 3986 }; 3987 3988 struct lpfc_mcqe { 3989 uint32_t word0; 3990 #define lpfc_mcqe_status_SHIFT 0 3991 #define lpfc_mcqe_status_MASK 0x0000FFFF 3992 #define lpfc_mcqe_status_WORD word0 3993 #define lpfc_mcqe_ext_status_SHIFT 16 3994 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3995 #define lpfc_mcqe_ext_status_WORD word0 3996 uint32_t mcqe_tag0; 3997 uint32_t mcqe_tag1; 3998 uint32_t trailer; 3999 #define lpfc_trailer_valid_SHIFT 31 4000 #define lpfc_trailer_valid_MASK 0x00000001 4001 #define lpfc_trailer_valid_WORD trailer 4002 #define lpfc_trailer_async_SHIFT 30 4003 #define lpfc_trailer_async_MASK 0x00000001 4004 #define lpfc_trailer_async_WORD trailer 4005 #define lpfc_trailer_hpi_SHIFT 29 4006 #define lpfc_trailer_hpi_MASK 0x00000001 4007 #define lpfc_trailer_hpi_WORD trailer 4008 #define lpfc_trailer_completed_SHIFT 28 4009 #define lpfc_trailer_completed_MASK 0x00000001 4010 #define lpfc_trailer_completed_WORD trailer 4011 #define lpfc_trailer_consumed_SHIFT 27 4012 #define lpfc_trailer_consumed_MASK 0x00000001 4013 #define lpfc_trailer_consumed_WORD trailer 4014 #define lpfc_trailer_type_SHIFT 16 4015 #define lpfc_trailer_type_MASK 0x000000FF 4016 #define lpfc_trailer_type_WORD trailer 4017 #define lpfc_trailer_code_SHIFT 8 4018 #define lpfc_trailer_code_MASK 0x000000FF 4019 #define lpfc_trailer_code_WORD trailer 4020 #define LPFC_TRAILER_CODE_LINK 0x1 4021 #define LPFC_TRAILER_CODE_FCOE 0x2 4022 #define LPFC_TRAILER_CODE_DCBX 0x3 4023 #define LPFC_TRAILER_CODE_GRP5 0x5 4024 #define LPFC_TRAILER_CODE_FC 0x10 4025 #define LPFC_TRAILER_CODE_SLI 0x11 4026 #define LPFC_TRAILER_CODE_CMSTAT 0x13 4027 }; 4028 4029 struct lpfc_acqe_link { 4030 uint32_t word0; 4031 #define lpfc_acqe_link_speed_SHIFT 24 4032 #define lpfc_acqe_link_speed_MASK 0x000000FF 4033 #define lpfc_acqe_link_speed_WORD word0 4034 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 4035 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 4036 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 4037 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 4038 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 4039 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 4040 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 4041 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 4042 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 4043 #define lpfc_acqe_link_duplex_SHIFT 16 4044 #define lpfc_acqe_link_duplex_MASK 0x000000FF 4045 #define lpfc_acqe_link_duplex_WORD word0 4046 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 4047 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 4048 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 4049 #define lpfc_acqe_link_status_SHIFT 8 4050 #define lpfc_acqe_link_status_MASK 0x000000FF 4051 #define lpfc_acqe_link_status_WORD word0 4052 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 4053 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 4054 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 4055 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 4056 #define lpfc_acqe_link_type_SHIFT 6 4057 #define lpfc_acqe_link_type_MASK 0x00000003 4058 #define lpfc_acqe_link_type_WORD word0 4059 #define lpfc_acqe_link_number_SHIFT 0 4060 #define lpfc_acqe_link_number_MASK 0x0000003F 4061 #define lpfc_acqe_link_number_WORD word0 4062 uint32_t word1; 4063 #define lpfc_acqe_link_fault_SHIFT 0 4064 #define lpfc_acqe_link_fault_MASK 0x000000FF 4065 #define lpfc_acqe_link_fault_WORD word1 4066 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 4067 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 4068 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 4069 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 4070 #define lpfc_acqe_logical_link_speed_SHIFT 16 4071 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 4072 #define lpfc_acqe_logical_link_speed_WORD word1 4073 uint32_t event_tag; 4074 uint32_t trailer; 4075 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 4076 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 4077 }; 4078 4079 struct lpfc_acqe_fip { 4080 uint32_t index; 4081 uint32_t word1; 4082 #define lpfc_acqe_fip_fcf_count_SHIFT 0 4083 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 4084 #define lpfc_acqe_fip_fcf_count_WORD word1 4085 #define lpfc_acqe_fip_event_type_SHIFT 16 4086 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 4087 #define lpfc_acqe_fip_event_type_WORD word1 4088 uint32_t event_tag; 4089 uint32_t trailer; 4090 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 4091 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 4092 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 4093 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 4094 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 4095 }; 4096 4097 struct lpfc_acqe_dcbx { 4098 uint32_t tlv_ttl; 4099 uint32_t reserved; 4100 uint32_t event_tag; 4101 uint32_t trailer; 4102 }; 4103 4104 struct lpfc_acqe_grp5 { 4105 uint32_t word0; 4106 #define lpfc_acqe_grp5_type_SHIFT 6 4107 #define lpfc_acqe_grp5_type_MASK 0x00000003 4108 #define lpfc_acqe_grp5_type_WORD word0 4109 #define lpfc_acqe_grp5_number_SHIFT 0 4110 #define lpfc_acqe_grp5_number_MASK 0x0000003F 4111 #define lpfc_acqe_grp5_number_WORD word0 4112 uint32_t word1; 4113 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 4114 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 4115 #define lpfc_acqe_grp5_llink_spd_WORD word1 4116 uint32_t event_tag; 4117 uint32_t trailer; 4118 }; 4119 4120 extern const char *const trunk_errmsg[]; 4121 4122 struct lpfc_acqe_fc_la { 4123 uint32_t word0; 4124 #define lpfc_acqe_fc_la_speed_SHIFT 24 4125 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4126 #define lpfc_acqe_fc_la_speed_WORD word0 4127 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4128 #define LPFC_FC_LA_SPEED_1G 0x1 4129 #define LPFC_FC_LA_SPEED_2G 0x2 4130 #define LPFC_FC_LA_SPEED_4G 0x4 4131 #define LPFC_FC_LA_SPEED_8G 0x8 4132 #define LPFC_FC_LA_SPEED_10G 0xA 4133 #define LPFC_FC_LA_SPEED_16G 0x10 4134 #define LPFC_FC_LA_SPEED_32G 0x20 4135 #define LPFC_FC_LA_SPEED_64G 0x21 4136 #define LPFC_FC_LA_SPEED_128G 0x22 4137 #define LPFC_FC_LA_SPEED_256G 0x23 4138 #define lpfc_acqe_fc_la_topology_SHIFT 16 4139 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4140 #define lpfc_acqe_fc_la_topology_WORD word0 4141 #define LPFC_FC_LA_TOP_UNKOWN 0x0 4142 #define LPFC_FC_LA_TOP_P2P 0x1 4143 #define LPFC_FC_LA_TOP_FCAL 0x2 4144 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4145 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4146 #define lpfc_acqe_fc_la_att_type_SHIFT 8 4147 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4148 #define lpfc_acqe_fc_la_att_type_WORD word0 4149 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 4150 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4151 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4152 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4153 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4154 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4155 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7 4156 #define lpfc_acqe_fc_la_port_type_SHIFT 6 4157 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4158 #define lpfc_acqe_fc_la_port_type_WORD word0 4159 #define LPFC_LINK_TYPE_ETHERNET 0x0 4160 #define LPFC_LINK_TYPE_FC 0x1 4161 #define lpfc_acqe_fc_la_port_number_SHIFT 0 4162 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4163 #define lpfc_acqe_fc_la_port_number_WORD word0 4164 4165 /* Attention Type is 0x07 (Trunking Event) word0 */ 4166 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16 4167 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001 4168 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0 4169 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17 4170 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001 4171 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0 4172 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18 4173 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001 4174 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0 4175 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19 4176 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001 4177 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0 4178 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20 4179 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001 4180 #define lpfc_acqe_fc_la_trunk_config_port0_WORD word0 4181 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21 4182 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001 4183 #define lpfc_acqe_fc_la_trunk_config_port1_WORD word0 4184 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22 4185 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001 4186 #define lpfc_acqe_fc_la_trunk_config_port2_WORD word0 4187 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23 4188 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001 4189 #define lpfc_acqe_fc_la_trunk_config_port3_WORD word0 4190 uint32_t word1; 4191 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4192 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4193 #define lpfc_acqe_fc_la_llink_spd_WORD word1 4194 #define lpfc_acqe_fc_la_fault_SHIFT 0 4195 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4196 #define lpfc_acqe_fc_la_fault_WORD word1 4197 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0 4198 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F 4199 #define lpfc_acqe_fc_la_trunk_fault_WORD word1 4200 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4 4201 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F 4202 #define lpfc_acqe_fc_la_trunk_linkmask_WORD word1 4203 #define LPFC_FC_LA_FAULT_NONE 0x0 4204 #define LPFC_FC_LA_FAULT_LOCAL 0x1 4205 #define LPFC_FC_LA_FAULT_REMOTE 0x2 4206 uint32_t event_tag; 4207 uint32_t trailer; 4208 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4209 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4210 }; 4211 4212 struct lpfc_acqe_misconfigured_event { 4213 struct { 4214 uint32_t word0; 4215 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 4216 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4217 #define lpfc_sli_misconfigured_port0_state_WORD word0 4218 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 4219 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4220 #define lpfc_sli_misconfigured_port1_state_WORD word0 4221 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 4222 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4223 #define lpfc_sli_misconfigured_port2_state_WORD word0 4224 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 4225 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4226 #define lpfc_sli_misconfigured_port3_state_WORD word0 4227 uint32_t word1; 4228 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 4229 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4230 #define lpfc_sli_misconfigured_port0_op_WORD word1 4231 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4232 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4233 #define lpfc_sli_misconfigured_port0_severity_WORD word1 4234 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 4235 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4236 #define lpfc_sli_misconfigured_port1_op_WORD word1 4237 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4238 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4239 #define lpfc_sli_misconfigured_port1_severity_WORD word1 4240 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 4241 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4242 #define lpfc_sli_misconfigured_port2_op_WORD word1 4243 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4244 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4245 #define lpfc_sli_misconfigured_port2_severity_WORD word1 4246 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 4247 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4248 #define lpfc_sli_misconfigured_port3_op_WORD word1 4249 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4250 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4251 #define lpfc_sli_misconfigured_port3_severity_WORD word1 4252 } theEvent; 4253 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 4254 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4255 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4256 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4257 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4258 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4259 }; 4260 4261 struct lpfc_acqe_cgn_signal { 4262 u32 word0; 4263 #define lpfc_warn_acqe_SHIFT 0 4264 #define lpfc_warn_acqe_MASK 0x7FFFFFFF 4265 #define lpfc_warn_acqe_WORD word0 4266 #define lpfc_imm_acqe_SHIFT 31 4267 #define lpfc_imm_acqe_MASK 0x1 4268 #define lpfc_imm_acqe_WORD word0 4269 u32 alarm_cnt; 4270 u32 word2; 4271 u32 trailer; 4272 }; 4273 4274 struct lpfc_acqe_sli { 4275 uint32_t event_data1; 4276 uint32_t event_data2; 4277 uint32_t reserved; 4278 uint32_t trailer; 4279 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4280 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4281 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4282 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4283 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4284 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4285 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4286 #define LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG 0xE 4287 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF 4288 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10 4289 #define LPFC_SLI_EVENT_TYPE_CGN_SIGNAL 0x11 4290 }; 4291 4292 /* 4293 * Define the bootstrap mailbox (bmbx) region used to communicate 4294 * mailbox command between the host and port. The mailbox consists 4295 * of a payload area of 256 bytes and a completion queue of length 4296 * 16 bytes. 4297 */ 4298 struct lpfc_bmbx_create { 4299 struct lpfc_mqe mqe; 4300 struct lpfc_mcqe mcqe; 4301 }; 4302 4303 #define SGL_ALIGN_SZ 64 4304 #define SGL_PAGE_SIZE 4096 4305 /* align SGL addr on a size boundary - adjust address up */ 4306 #define NO_XRI 0xffff 4307 4308 struct wqe_common { 4309 uint32_t word6; 4310 #define wqe_xri_tag_SHIFT 0 4311 #define wqe_xri_tag_MASK 0x0000FFFF 4312 #define wqe_xri_tag_WORD word6 4313 #define wqe_ctxt_tag_SHIFT 16 4314 #define wqe_ctxt_tag_MASK 0x0000FFFF 4315 #define wqe_ctxt_tag_WORD word6 4316 uint32_t word7; 4317 #define wqe_dif_SHIFT 0 4318 #define wqe_dif_MASK 0x00000003 4319 #define wqe_dif_WORD word7 4320 #define LPFC_WQE_DIF_PASSTHRU 1 4321 #define LPFC_WQE_DIF_STRIP 2 4322 #define LPFC_WQE_DIF_INSERT 3 4323 #define wqe_ct_SHIFT 2 4324 #define wqe_ct_MASK 0x00000003 4325 #define wqe_ct_WORD word7 4326 #define wqe_status_SHIFT 4 4327 #define wqe_status_MASK 0x0000000f 4328 #define wqe_status_WORD word7 4329 #define wqe_cmnd_SHIFT 8 4330 #define wqe_cmnd_MASK 0x000000ff 4331 #define wqe_cmnd_WORD word7 4332 #define wqe_class_SHIFT 16 4333 #define wqe_class_MASK 0x00000007 4334 #define wqe_class_WORD word7 4335 #define wqe_ar_SHIFT 19 4336 #define wqe_ar_MASK 0x00000001 4337 #define wqe_ar_WORD word7 4338 #define wqe_ag_SHIFT wqe_ar_SHIFT 4339 #define wqe_ag_MASK wqe_ar_MASK 4340 #define wqe_ag_WORD wqe_ar_WORD 4341 #define wqe_pu_SHIFT 20 4342 #define wqe_pu_MASK 0x00000003 4343 #define wqe_pu_WORD word7 4344 #define wqe_erp_SHIFT 22 4345 #define wqe_erp_MASK 0x00000001 4346 #define wqe_erp_WORD word7 4347 #define wqe_conf_SHIFT wqe_erp_SHIFT 4348 #define wqe_conf_MASK wqe_erp_MASK 4349 #define wqe_conf_WORD wqe_erp_WORD 4350 #define wqe_lnk_SHIFT 23 4351 #define wqe_lnk_MASK 0x00000001 4352 #define wqe_lnk_WORD word7 4353 #define wqe_tmo_SHIFT 24 4354 #define wqe_tmo_MASK 0x000000ff 4355 #define wqe_tmo_WORD word7 4356 uint32_t abort_tag; /* word 8 in WQE */ 4357 uint32_t word9; 4358 #define wqe_reqtag_SHIFT 0 4359 #define wqe_reqtag_MASK 0x0000FFFF 4360 #define wqe_reqtag_WORD word9 4361 #define wqe_temp_rpi_SHIFT 16 4362 #define wqe_temp_rpi_MASK 0x0000FFFF 4363 #define wqe_temp_rpi_WORD word9 4364 #define wqe_rcvoxid_SHIFT 16 4365 #define wqe_rcvoxid_MASK 0x0000FFFF 4366 #define wqe_rcvoxid_WORD word9 4367 #define wqe_sof_SHIFT 24 4368 #define wqe_sof_MASK 0x000000FF 4369 #define wqe_sof_WORD word9 4370 #define wqe_eof_SHIFT 16 4371 #define wqe_eof_MASK 0x000000FF 4372 #define wqe_eof_WORD word9 4373 uint32_t word10; 4374 #define wqe_ebde_cnt_SHIFT 0 4375 #define wqe_ebde_cnt_MASK 0x0000000f 4376 #define wqe_ebde_cnt_WORD word10 4377 #define wqe_xchg_SHIFT 4 4378 #define wqe_xchg_MASK 0x00000001 4379 #define wqe_xchg_WORD word10 4380 #define LPFC_SCSI_XCHG 0x0 4381 #define LPFC_NVME_XCHG 0x1 4382 #define wqe_appid_SHIFT 5 4383 #define wqe_appid_MASK 0x00000001 4384 #define wqe_appid_WORD word10 4385 #define wqe_oas_SHIFT 6 4386 #define wqe_oas_MASK 0x00000001 4387 #define wqe_oas_WORD word10 4388 #define wqe_lenloc_SHIFT 7 4389 #define wqe_lenloc_MASK 0x00000003 4390 #define wqe_lenloc_WORD word10 4391 #define LPFC_WQE_LENLOC_NONE 0 4392 #define LPFC_WQE_LENLOC_WORD3 1 4393 #define LPFC_WQE_LENLOC_WORD12 2 4394 #define LPFC_WQE_LENLOC_WORD4 3 4395 #define wqe_qosd_SHIFT 9 4396 #define wqe_qosd_MASK 0x00000001 4397 #define wqe_qosd_WORD word10 4398 #define wqe_xbl_SHIFT 11 4399 #define wqe_xbl_MASK 0x00000001 4400 #define wqe_xbl_WORD word10 4401 #define wqe_iod_SHIFT 13 4402 #define wqe_iod_MASK 0x00000001 4403 #define wqe_iod_WORD word10 4404 #define LPFC_WQE_IOD_NONE 0 4405 #define LPFC_WQE_IOD_WRITE 0 4406 #define LPFC_WQE_IOD_READ 1 4407 #define wqe_dbde_SHIFT 14 4408 #define wqe_dbde_MASK 0x00000001 4409 #define wqe_dbde_WORD word10 4410 #define wqe_wqes_SHIFT 15 4411 #define wqe_wqes_MASK 0x00000001 4412 #define wqe_wqes_WORD word10 4413 /* Note that this field overlaps above fields */ 4414 #define wqe_wqid_SHIFT 1 4415 #define wqe_wqid_MASK 0x00007fff 4416 #define wqe_wqid_WORD word10 4417 #define wqe_pri_SHIFT 16 4418 #define wqe_pri_MASK 0x00000007 4419 #define wqe_pri_WORD word10 4420 #define wqe_pv_SHIFT 19 4421 #define wqe_pv_MASK 0x00000001 4422 #define wqe_pv_WORD word10 4423 #define wqe_xc_SHIFT 21 4424 #define wqe_xc_MASK 0x00000001 4425 #define wqe_xc_WORD word10 4426 #define wqe_sr_SHIFT 22 4427 #define wqe_sr_MASK 0x00000001 4428 #define wqe_sr_WORD word10 4429 #define wqe_ccpe_SHIFT 23 4430 #define wqe_ccpe_MASK 0x00000001 4431 #define wqe_ccpe_WORD word10 4432 #define wqe_ccp_SHIFT 24 4433 #define wqe_ccp_MASK 0x000000ff 4434 #define wqe_ccp_WORD word10 4435 uint32_t word11; 4436 #define wqe_cmd_type_SHIFT 0 4437 #define wqe_cmd_type_MASK 0x0000000f 4438 #define wqe_cmd_type_WORD word11 4439 #define wqe_els_id_SHIFT 4 4440 #define wqe_els_id_MASK 0x00000003 4441 #define wqe_els_id_WORD word11 4442 #define LPFC_ELS_ID_FLOGI 3 4443 #define LPFC_ELS_ID_FDISC 2 4444 #define LPFC_ELS_ID_LOGO 1 4445 #define LPFC_ELS_ID_DEFAULT 0 4446 #define wqe_irsp_SHIFT 4 4447 #define wqe_irsp_MASK 0x00000001 4448 #define wqe_irsp_WORD word11 4449 #define wqe_pbde_SHIFT 5 4450 #define wqe_pbde_MASK 0x00000001 4451 #define wqe_pbde_WORD word11 4452 #define wqe_sup_SHIFT 6 4453 #define wqe_sup_MASK 0x00000001 4454 #define wqe_sup_WORD word11 4455 #define wqe_wqec_SHIFT 7 4456 #define wqe_wqec_MASK 0x00000001 4457 #define wqe_wqec_WORD word11 4458 #define wqe_irsplen_SHIFT 8 4459 #define wqe_irsplen_MASK 0x0000000f 4460 #define wqe_irsplen_WORD word11 4461 #define wqe_cqid_SHIFT 16 4462 #define wqe_cqid_MASK 0x0000ffff 4463 #define wqe_cqid_WORD word11 4464 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4465 }; 4466 4467 struct wqe_did { 4468 uint32_t word5; 4469 #define wqe_els_did_SHIFT 0 4470 #define wqe_els_did_MASK 0x00FFFFFF 4471 #define wqe_els_did_WORD word5 4472 #define wqe_xmit_bls_pt_SHIFT 28 4473 #define wqe_xmit_bls_pt_MASK 0x00000003 4474 #define wqe_xmit_bls_pt_WORD word5 4475 #define wqe_xmit_bls_ar_SHIFT 30 4476 #define wqe_xmit_bls_ar_MASK 0x00000001 4477 #define wqe_xmit_bls_ar_WORD word5 4478 #define wqe_xmit_bls_xo_SHIFT 31 4479 #define wqe_xmit_bls_xo_MASK 0x00000001 4480 #define wqe_xmit_bls_xo_WORD word5 4481 }; 4482 4483 struct lpfc_wqe_generic{ 4484 struct ulp_bde64 bde; 4485 uint32_t word3; 4486 uint32_t word4; 4487 uint32_t word5; 4488 struct wqe_common wqe_com; 4489 uint32_t payload[4]; 4490 }; 4491 4492 struct els_request64_wqe { 4493 struct ulp_bde64 bde; 4494 uint32_t payload_len; 4495 uint32_t word4; 4496 #define els_req64_sid_SHIFT 0 4497 #define els_req64_sid_MASK 0x00FFFFFF 4498 #define els_req64_sid_WORD word4 4499 #define els_req64_sp_SHIFT 24 4500 #define els_req64_sp_MASK 0x00000001 4501 #define els_req64_sp_WORD word4 4502 #define els_req64_vf_SHIFT 25 4503 #define els_req64_vf_MASK 0x00000001 4504 #define els_req64_vf_WORD word4 4505 struct wqe_did wqe_dest; 4506 struct wqe_common wqe_com; /* words 6-11 */ 4507 uint32_t word12; 4508 #define els_req64_vfid_SHIFT 1 4509 #define els_req64_vfid_MASK 0x00000FFF 4510 #define els_req64_vfid_WORD word12 4511 #define els_req64_pri_SHIFT 13 4512 #define els_req64_pri_MASK 0x00000007 4513 #define els_req64_pri_WORD word12 4514 uint32_t word13; 4515 #define els_req64_hopcnt_SHIFT 24 4516 #define els_req64_hopcnt_MASK 0x000000ff 4517 #define els_req64_hopcnt_WORD word13 4518 uint32_t word14; 4519 uint32_t max_response_payload_len; 4520 }; 4521 4522 struct xmit_els_rsp64_wqe { 4523 struct ulp_bde64 bde; 4524 uint32_t response_payload_len; 4525 uint32_t word4; 4526 #define els_rsp64_sid_SHIFT 0 4527 #define els_rsp64_sid_MASK 0x00FFFFFF 4528 #define els_rsp64_sid_WORD word4 4529 #define els_rsp64_sp_SHIFT 24 4530 #define els_rsp64_sp_MASK 0x00000001 4531 #define els_rsp64_sp_WORD word4 4532 struct wqe_did wqe_dest; 4533 struct wqe_common wqe_com; /* words 6-11 */ 4534 uint32_t word12; 4535 #define wqe_rsp_temp_rpi_SHIFT 0 4536 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4537 #define wqe_rsp_temp_rpi_WORD word12 4538 uint32_t rsvd_13_15[3]; 4539 }; 4540 4541 struct xmit_bls_rsp64_wqe { 4542 uint32_t payload0; 4543 /* Payload0 for BA_ACC */ 4544 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4545 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4546 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 4547 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4548 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4549 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4550 /* Payload0 for BA_RJT */ 4551 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4552 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4553 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 4554 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 4555 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4556 #define xmit_bls_rsp64_rjt_expc_WORD payload0 4557 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4558 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4559 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4560 uint32_t word1; 4561 #define xmit_bls_rsp64_rxid_SHIFT 0 4562 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4563 #define xmit_bls_rsp64_rxid_WORD word1 4564 #define xmit_bls_rsp64_oxid_SHIFT 16 4565 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4566 #define xmit_bls_rsp64_oxid_WORD word1 4567 uint32_t word2; 4568 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 4569 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4570 #define xmit_bls_rsp64_seqcnthi_WORD word2 4571 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 4572 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4573 #define xmit_bls_rsp64_seqcntlo_WORD word2 4574 uint32_t rsrvd3; 4575 uint32_t rsrvd4; 4576 struct wqe_did wqe_dest; 4577 struct wqe_common wqe_com; /* words 6-11 */ 4578 uint32_t word12; 4579 #define xmit_bls_rsp64_temprpi_SHIFT 0 4580 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4581 #define xmit_bls_rsp64_temprpi_WORD word12 4582 uint32_t rsvd_13_15[3]; 4583 }; 4584 4585 struct wqe_rctl_dfctl { 4586 uint32_t word5; 4587 #define wqe_si_SHIFT 2 4588 #define wqe_si_MASK 0x000000001 4589 #define wqe_si_WORD word5 4590 #define wqe_la_SHIFT 3 4591 #define wqe_la_MASK 0x000000001 4592 #define wqe_la_WORD word5 4593 #define wqe_xo_SHIFT 6 4594 #define wqe_xo_MASK 0x000000001 4595 #define wqe_xo_WORD word5 4596 #define wqe_ls_SHIFT 7 4597 #define wqe_ls_MASK 0x000000001 4598 #define wqe_ls_WORD word5 4599 #define wqe_dfctl_SHIFT 8 4600 #define wqe_dfctl_MASK 0x0000000ff 4601 #define wqe_dfctl_WORD word5 4602 #define wqe_type_SHIFT 16 4603 #define wqe_type_MASK 0x0000000ff 4604 #define wqe_type_WORD word5 4605 #define wqe_rctl_SHIFT 24 4606 #define wqe_rctl_MASK 0x0000000ff 4607 #define wqe_rctl_WORD word5 4608 }; 4609 4610 struct xmit_seq64_wqe { 4611 struct ulp_bde64 bde; 4612 uint32_t rsvd3; 4613 uint32_t relative_offset; 4614 struct wqe_rctl_dfctl wge_ctl; 4615 struct wqe_common wqe_com; /* words 6-11 */ 4616 uint32_t xmit_len; 4617 uint32_t rsvd_12_15[3]; 4618 }; 4619 struct xmit_bcast64_wqe { 4620 struct ulp_bde64 bde; 4621 uint32_t seq_payload_len; 4622 uint32_t rsvd4; 4623 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4624 struct wqe_common wqe_com; /* words 6-11 */ 4625 uint32_t rsvd_12_15[4]; 4626 }; 4627 4628 struct gen_req64_wqe { 4629 struct ulp_bde64 bde; 4630 uint32_t request_payload_len; 4631 uint32_t relative_offset; 4632 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4633 struct wqe_common wqe_com; /* words 6-11 */ 4634 uint32_t rsvd_12_14[3]; 4635 uint32_t max_response_payload_len; 4636 }; 4637 4638 /* Define NVME PRLI request to fabric. NVME is a 4639 * fabric-only protocol. 4640 * Updated to red-lined v1.08 on Sept 16, 2016 4641 */ 4642 struct lpfc_nvme_prli { 4643 uint32_t word1; 4644 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4645 #define prli_acc_rsp_code_SHIFT 8 4646 #define prli_acc_rsp_code_MASK 0x0000000f 4647 #define prli_acc_rsp_code_WORD word1 4648 #define prli_estabImagePair_SHIFT 13 4649 #define prli_estabImagePair_MASK 0x00000001 4650 #define prli_estabImagePair_WORD word1 4651 #define prli_type_code_ext_SHIFT 16 4652 #define prli_type_code_ext_MASK 0x000000ff 4653 #define prli_type_code_ext_WORD word1 4654 #define prli_type_code_SHIFT 24 4655 #define prli_type_code_MASK 0x000000ff 4656 #define prli_type_code_WORD word1 4657 uint32_t word_rsvd2; 4658 uint32_t word_rsvd3; 4659 4660 uint32_t word4; 4661 #define prli_fba_SHIFT 0 4662 #define prli_fba_MASK 0x00000001 4663 #define prli_fba_WORD word4 4664 #define prli_disc_SHIFT 3 4665 #define prli_disc_MASK 0x00000001 4666 #define prli_disc_WORD word4 4667 #define prli_tgt_SHIFT 4 4668 #define prli_tgt_MASK 0x00000001 4669 #define prli_tgt_WORD word4 4670 #define prli_init_SHIFT 5 4671 #define prli_init_MASK 0x00000001 4672 #define prli_init_WORD word4 4673 #define prli_conf_SHIFT 7 4674 #define prli_conf_MASK 0x00000001 4675 #define prli_conf_WORD word4 4676 #define prli_nsler_SHIFT 8 4677 #define prli_nsler_MASK 0x00000001 4678 #define prli_nsler_WORD word4 4679 uint32_t word5; 4680 #define prli_fb_sz_SHIFT 0 4681 #define prli_fb_sz_MASK 0x0000ffff 4682 #define prli_fb_sz_WORD word5 4683 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4684 }; 4685 4686 struct create_xri_wqe { 4687 uint32_t rsrvd[5]; /* words 0-4 */ 4688 struct wqe_did wqe_dest; /* word 5 */ 4689 struct wqe_common wqe_com; /* words 6-11 */ 4690 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4691 }; 4692 4693 #define INHIBIT_ABORT 1 4694 #define T_REQUEST_TAG 3 4695 #define T_XRI_TAG 1 4696 4697 struct cmf_sync_wqe { 4698 uint32_t rsrvd[3]; 4699 uint32_t word3; 4700 #define cmf_sync_interval_SHIFT 0 4701 #define cmf_sync_interval_MASK 0x00000ffff 4702 #define cmf_sync_interval_WORD word3 4703 #define cmf_sync_afpin_SHIFT 16 4704 #define cmf_sync_afpin_MASK 0x000000001 4705 #define cmf_sync_afpin_WORD word3 4706 #define cmf_sync_asig_SHIFT 17 4707 #define cmf_sync_asig_MASK 0x000000001 4708 #define cmf_sync_asig_WORD word3 4709 #define cmf_sync_op_SHIFT 20 4710 #define cmf_sync_op_MASK 0x00000000f 4711 #define cmf_sync_op_WORD word3 4712 #define cmf_sync_ver_SHIFT 24 4713 #define cmf_sync_ver_MASK 0x0000000ff 4714 #define cmf_sync_ver_WORD word3 4715 #define LPFC_CMF_SYNC_VER 1 4716 uint32_t event_tag; 4717 uint32_t word5; 4718 #define cmf_sync_wsigmax_SHIFT 0 4719 #define cmf_sync_wsigmax_MASK 0x00000ffff 4720 #define cmf_sync_wsigmax_WORD word5 4721 #define cmf_sync_wsigcnt_SHIFT 16 4722 #define cmf_sync_wsigcnt_MASK 0x00000ffff 4723 #define cmf_sync_wsigcnt_WORD word5 4724 uint32_t word6; 4725 uint32_t word7; 4726 #define cmf_sync_cmnd_SHIFT 8 4727 #define cmf_sync_cmnd_MASK 0x0000000ff 4728 #define cmf_sync_cmnd_WORD word7 4729 uint32_t word8; 4730 uint32_t word9; 4731 #define cmf_sync_reqtag_SHIFT 0 4732 #define cmf_sync_reqtag_MASK 0x00000ffff 4733 #define cmf_sync_reqtag_WORD word9 4734 #define cmf_sync_wfpinmax_SHIFT 16 4735 #define cmf_sync_wfpinmax_MASK 0x0000000ff 4736 #define cmf_sync_wfpinmax_WORD word9 4737 #define cmf_sync_wfpincnt_SHIFT 24 4738 #define cmf_sync_wfpincnt_MASK 0x0000000ff 4739 #define cmf_sync_wfpincnt_WORD word9 4740 uint32_t word10; 4741 #define cmf_sync_qosd_SHIFT 9 4742 #define cmf_sync_qosd_MASK 0x00000001 4743 #define cmf_sync_qosd_WORD word10 4744 uint32_t word11; 4745 #define cmf_sync_cmd_type_SHIFT 0 4746 #define cmf_sync_cmd_type_MASK 0x0000000f 4747 #define cmf_sync_cmd_type_WORD word11 4748 #define cmf_sync_wqec_SHIFT 7 4749 #define cmf_sync_wqec_MASK 0x00000001 4750 #define cmf_sync_wqec_WORD word11 4751 #define cmf_sync_cqid_SHIFT 16 4752 #define cmf_sync_cqid_MASK 0x0000ffff 4753 #define cmf_sync_cqid_WORD word11 4754 uint32_t read_bytes; 4755 uint32_t word13; 4756 uint32_t word14; 4757 uint32_t word15; 4758 }; 4759 4760 struct abort_cmd_wqe { 4761 uint32_t rsrvd[3]; 4762 uint32_t word3; 4763 #define abort_cmd_ia_SHIFT 0 4764 #define abort_cmd_ia_MASK 0x000000001 4765 #define abort_cmd_ia_WORD word3 4766 #define abort_cmd_criteria_SHIFT 8 4767 #define abort_cmd_criteria_MASK 0x0000000ff 4768 #define abort_cmd_criteria_WORD word3 4769 uint32_t rsrvd4; 4770 uint32_t rsrvd5; 4771 struct wqe_common wqe_com; /* words 6-11 */ 4772 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4773 }; 4774 4775 struct fcp_iwrite64_wqe { 4776 struct ulp_bde64 bde; 4777 uint32_t word3; 4778 #define cmd_buff_len_SHIFT 16 4779 #define cmd_buff_len_MASK 0x00000ffff 4780 #define cmd_buff_len_WORD word3 4781 #define payload_offset_len_SHIFT 0 4782 #define payload_offset_len_MASK 0x0000ffff 4783 #define payload_offset_len_WORD word3 4784 uint32_t total_xfer_len; 4785 uint32_t initial_xfer_len; 4786 struct wqe_common wqe_com; /* words 6-11 */ 4787 uint32_t rsrvd12; 4788 struct ulp_bde64 ph_bde; /* words 13-15 */ 4789 }; 4790 4791 struct fcp_iread64_wqe { 4792 struct ulp_bde64 bde; 4793 uint32_t word3; 4794 #define cmd_buff_len_SHIFT 16 4795 #define cmd_buff_len_MASK 0x00000ffff 4796 #define cmd_buff_len_WORD word3 4797 #define payload_offset_len_SHIFT 0 4798 #define payload_offset_len_MASK 0x0000ffff 4799 #define payload_offset_len_WORD word3 4800 uint32_t total_xfer_len; /* word 4 */ 4801 uint32_t rsrvd5; /* word 5 */ 4802 struct wqe_common wqe_com; /* words 6-11 */ 4803 uint32_t rsrvd12; 4804 struct ulp_bde64 ph_bde; /* words 13-15 */ 4805 }; 4806 4807 struct fcp_icmnd64_wqe { 4808 struct ulp_bde64 bde; /* words 0-2 */ 4809 uint32_t word3; 4810 #define cmd_buff_len_SHIFT 16 4811 #define cmd_buff_len_MASK 0x00000ffff 4812 #define cmd_buff_len_WORD word3 4813 #define payload_offset_len_SHIFT 0 4814 #define payload_offset_len_MASK 0x0000ffff 4815 #define payload_offset_len_WORD word3 4816 uint32_t rsrvd4; /* word 4 */ 4817 uint32_t rsrvd5; /* word 5 */ 4818 struct wqe_common wqe_com; /* words 6-11 */ 4819 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4820 }; 4821 4822 struct fcp_trsp64_wqe { 4823 struct ulp_bde64 bde; 4824 uint32_t response_len; 4825 uint32_t rsvd_4_5[2]; 4826 struct wqe_common wqe_com; /* words 6-11 */ 4827 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4828 }; 4829 4830 struct fcp_tsend64_wqe { 4831 struct ulp_bde64 bde; 4832 uint32_t payload_offset_len; 4833 uint32_t relative_offset; 4834 uint32_t reserved; 4835 struct wqe_common wqe_com; /* words 6-11 */ 4836 uint32_t fcp_data_len; /* word 12 */ 4837 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4838 }; 4839 4840 struct fcp_treceive64_wqe { 4841 struct ulp_bde64 bde; 4842 uint32_t payload_offset_len; 4843 uint32_t relative_offset; 4844 uint32_t reserved; 4845 struct wqe_common wqe_com; /* words 6-11 */ 4846 uint32_t fcp_data_len; /* word 12 */ 4847 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4848 }; 4849 #define TXRDY_PAYLOAD_LEN 12 4850 4851 #define CMD_SEND_FRAME 0xE1 4852 4853 struct send_frame_wqe { 4854 struct ulp_bde64 bde; /* words 0-2 */ 4855 uint32_t frame_len; /* word 3 */ 4856 uint32_t fc_hdr_wd0; /* word 4 */ 4857 uint32_t fc_hdr_wd1; /* word 5 */ 4858 struct wqe_common wqe_com; /* words 6-11 */ 4859 uint32_t fc_hdr_wd2; /* word 12 */ 4860 uint32_t fc_hdr_wd3; /* word 13 */ 4861 uint32_t fc_hdr_wd4; /* word 14 */ 4862 uint32_t fc_hdr_wd5; /* word 15 */ 4863 }; 4864 4865 #define ELS_RDF_REG_TAG_CNT 4 4866 struct lpfc_els_rdf_reg_desc { 4867 struct fc_df_desc_fpin_reg reg_desc; /* descriptor header */ 4868 __be32 desc_tags[ELS_RDF_REG_TAG_CNT]; 4869 /* tags in reg_desc */ 4870 }; 4871 4872 struct lpfc_els_rdf_req { 4873 struct fc_els_rdf rdf; /* hdr up to descriptors */ 4874 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4875 }; 4876 4877 struct lpfc_els_rdf_rsp { 4878 struct fc_els_rdf_resp rdf_resp; /* hdr up to descriptors */ 4879 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4880 }; 4881 4882 union lpfc_wqe { 4883 uint32_t words[16]; 4884 struct lpfc_wqe_generic generic; 4885 struct fcp_icmnd64_wqe fcp_icmd; 4886 struct fcp_iread64_wqe fcp_iread; 4887 struct fcp_iwrite64_wqe fcp_iwrite; 4888 struct abort_cmd_wqe abort_cmd; 4889 struct cmf_sync_wqe cmf_sync; 4890 struct create_xri_wqe create_xri; 4891 struct xmit_bcast64_wqe xmit_bcast64; 4892 struct xmit_seq64_wqe xmit_sequence; 4893 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4894 struct xmit_els_rsp64_wqe xmit_els_rsp; 4895 struct els_request64_wqe els_req; 4896 struct gen_req64_wqe gen_req; 4897 struct fcp_trsp64_wqe fcp_trsp; 4898 struct fcp_tsend64_wqe fcp_tsend; 4899 struct fcp_treceive64_wqe fcp_treceive; 4900 struct send_frame_wqe send_frame; 4901 }; 4902 4903 union lpfc_wqe128 { 4904 uint32_t words[32]; 4905 struct lpfc_wqe_generic generic; 4906 struct fcp_icmnd64_wqe fcp_icmd; 4907 struct fcp_iread64_wqe fcp_iread; 4908 struct fcp_iwrite64_wqe fcp_iwrite; 4909 struct abort_cmd_wqe abort_cmd; 4910 struct cmf_sync_wqe cmf_sync; 4911 struct create_xri_wqe create_xri; 4912 struct xmit_bcast64_wqe xmit_bcast64; 4913 struct xmit_seq64_wqe xmit_sequence; 4914 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4915 struct xmit_els_rsp64_wqe xmit_els_rsp; 4916 struct els_request64_wqe els_req; 4917 struct gen_req64_wqe gen_req; 4918 struct fcp_trsp64_wqe fcp_trsp; 4919 struct fcp_tsend64_wqe fcp_tsend; 4920 struct fcp_treceive64_wqe fcp_treceive; 4921 struct send_frame_wqe send_frame; 4922 }; 4923 4924 #define MAGIC_NUMBER_G6 0xFEAA0003 4925 #define MAGIC_NUMBER_G7 0xFEAA0005 4926 #define MAGIC_NUMBER_G7P 0xFEAA0020 4927 4928 struct lpfc_grp_hdr { 4929 uint32_t size; 4930 uint32_t magic_number; 4931 uint32_t word2; 4932 #define lpfc_grp_hdr_file_type_SHIFT 24 4933 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4934 #define lpfc_grp_hdr_file_type_WORD word2 4935 #define lpfc_grp_hdr_id_SHIFT 16 4936 #define lpfc_grp_hdr_id_MASK 0x000000FF 4937 #define lpfc_grp_hdr_id_WORD word2 4938 uint8_t rev_name[128]; 4939 uint8_t date[12]; 4940 uint8_t revision[32]; 4941 }; 4942 4943 /* Defines for WQE command type */ 4944 #define FCP_COMMAND 0x0 4945 #define NVME_READ_CMD 0x0 4946 #define FCP_COMMAND_DATA_OUT 0x1 4947 #define NVME_WRITE_CMD 0x1 4948 #define COMMAND_DATA_IN 0x0 4949 #define COMMAND_DATA_OUT 0x1 4950 #define FCP_COMMAND_TRECEIVE 0x2 4951 #define FCP_COMMAND_TRSP 0x3 4952 #define FCP_COMMAND_TSEND 0x7 4953 #define OTHER_COMMAND 0x8 4954 #define CMF_SYNC_COMMAND 0xA 4955 #define ELS_COMMAND_NON_FIP 0xC 4956 #define ELS_COMMAND_FIP 0xD 4957 4958 #define LPFC_NVME_EMBED_CMD 0x0 4959 #define LPFC_NVME_EMBED_WRITE 0x1 4960 #define LPFC_NVME_EMBED_READ 0x2 4961 4962 /* WQE Commands */ 4963 #define CMD_ABORT_XRI_WQE 0x0F 4964 #define CMD_XMIT_SEQUENCE64_WQE 0x82 4965 #define CMD_XMIT_BCAST64_WQE 0x84 4966 #define CMD_ELS_REQUEST64_WQE 0x8A 4967 #define CMD_XMIT_ELS_RSP64_WQE 0x95 4968 #define CMD_XMIT_BLS_RSP64_WQE 0x97 4969 #define CMD_FCP_IWRITE64_WQE 0x98 4970 #define CMD_FCP_IREAD64_WQE 0x9A 4971 #define CMD_FCP_ICMND64_WQE 0x9C 4972 #define CMD_FCP_TSEND64_WQE 0x9F 4973 #define CMD_FCP_TRECEIVE64_WQE 0xA1 4974 #define CMD_FCP_TRSP64_WQE 0xA3 4975 #define CMD_GEN_REQUEST64_WQE 0xC2 4976 #define CMD_CMF_SYNC_WQE 0xE8 4977 4978 #define CMD_WQE_MASK 0xff 4979 4980 4981 #define LPFC_FW_DUMP 1 4982 #define LPFC_FW_RESET 2 4983 #define LPFC_DV_RESET 3 4984 4985 /* On some kernels, enum fc_ls_tlv_dtag does not have 4986 * these 2 enums defined, on other kernels it does. 4987 * To get aound this we need to add these 2 defines here. 4988 */ 4989 #ifndef ELS_DTAG_LNK_FAULT_CAP 4990 #define ELS_DTAG_LNK_FAULT_CAP 0x0001000D 4991 #endif 4992 #ifndef ELS_DTAG_CG_SIGNAL_CAP 4993 #define ELS_DTAG_CG_SIGNAL_CAP 0x0001000F 4994 #endif 4995 4996 /* 4997 * Initializer useful for decoding FPIN string table. 4998 */ 4999 #define FC_FPIN_CONGN_SEVERITY_INIT { \ 5000 { FPIN_CONGN_SEVERITY_WARNING, "Warning" }, \ 5001 { FPIN_CONGN_SEVERITY_ERROR, "Alarm" }, \ 5002 } 5003 5004 /* EDC supports two descriptors. When allocated, it is the 5005 * size of this structure plus each supported descriptor. 5006 */ 5007 struct lpfc_els_edc_req { 5008 struct fc_els_edc edc; /* hdr up to descriptors */ 5009 struct fc_diag_cg_sig_desc cgn_desc; /* 1st descriptor */ 5010 }; 5011 5012 /* Minimum structure defines for the EDC response. 5013 * Balance is in buffer. 5014 */ 5015 struct lpfc_els_edc_rsp { 5016 struct fc_els_edc_resp edc_rsp; /* hdr up to descriptors */ 5017 struct fc_diag_cg_sig_desc cgn_desc; /* 1st descriptor */ 5018 }; 5019 5020 /* Used for logging FPIN messages */ 5021 #define LPFC_FPIN_WWPN_LINE_SZ 128 5022 #define LPFC_FPIN_WWPN_LINE_CNT 6 5023 #define LPFC_FPIN_WWPN_NUM_LINE 6 5024