1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2009 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 /* Macros to deal with bit fields. Each bit field must have 3 #defines 22 * associated with it (_SHIFT, _MASK, and _WORD). 23 * EG. For a bit field that is in the 7th bit of the "field4" field of a 24 * structure and is 2 bits in size the following #defines must exist: 25 * struct temp { 26 * uint32_t field1; 27 * uint32_t field2; 28 * uint32_t field3; 29 * uint32_t field4; 30 * #define example_bit_field_SHIFT 7 31 * #define example_bit_field_MASK 0x03 32 * #define example_bit_field_WORD field4 33 * uint32_t field5; 34 * }; 35 * Then the macros below may be used to get or set the value of that field. 36 * EG. To get the value of the bit field from the above example: 37 * struct temp t1; 38 * value = bf_get(example_bit_field, &t1); 39 * And then to set that bit field: 40 * bf_set(example_bit_field, &t1, 2); 41 * Or clear that bit field: 42 * bf_set(example_bit_field, &t1, 0); 43 */ 44 #define bf_get_be32(name, ptr) \ 45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 46 #define bf_get_le32(name, ptr) \ 47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get(name, ptr) \ 49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 50 #define bf_set_le32(name, ptr, value) \ 51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 53 ~(name##_MASK << name##_SHIFT))))) 54 #define bf_set(name, ptr, value) \ 55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 57 58 struct dma_address { 59 uint32_t addr_lo; 60 uint32_t addr_hi; 61 }; 62 63 struct lpfc_sli_intf { 64 uint32_t word0; 65 #define lpfc_sli_intf_valid_SHIFT 29 66 #define lpfc_sli_intf_valid_MASK 0x00000007 67 #define lpfc_sli_intf_valid_WORD word0 68 #define LPFC_SLI_INTF_VALID 6 69 #define lpfc_sli_intf_sli_hint2_SHIFT 24 70 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 71 #define lpfc_sli_intf_sli_hint2_WORD word0 72 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 73 #define lpfc_sli_intf_sli_hint1_SHIFT 16 74 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 75 #define lpfc_sli_intf_sli_hint1_WORD word0 76 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 77 #define LPFC_SLI_INTF_SLI_HINT1_1 1 78 #define LPFC_SLI_INTF_SLI_HINT1_2 2 79 #define lpfc_sli_intf_if_type_SHIFT 12 80 #define lpfc_sli_intf_if_type_MASK 0x0000000F 81 #define lpfc_sli_intf_if_type_WORD word0 82 #define LPFC_SLI_INTF_IF_TYPE_0 0 83 #define LPFC_SLI_INTF_IF_TYPE_1 1 84 #define LPFC_SLI_INTF_IF_TYPE_2 2 85 #define lpfc_sli_intf_sli_family_SHIFT 8 86 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 87 #define lpfc_sli_intf_sli_family_WORD word0 88 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 89 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 92 #define lpfc_sli_intf_slirev_SHIFT 4 93 #define lpfc_sli_intf_slirev_MASK 0x0000000F 94 #define lpfc_sli_intf_slirev_WORD word0 95 #define LPFC_SLI_INTF_REV_SLI3 3 96 #define LPFC_SLI_INTF_REV_SLI4 4 97 #define lpfc_sli_intf_func_type_SHIFT 0 98 #define lpfc_sli_intf_func_type_MASK 0x00000001 99 #define lpfc_sli_intf_func_type_WORD word0 100 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 101 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 102 }; 103 104 #define LPFC_SLI4_MBX_EMBED true 105 #define LPFC_SLI4_MBX_NEMBED false 106 107 #define LPFC_SLI4_MB_WORD_COUNT 64 108 #define LPFC_MAX_MQ_PAGE 8 109 #define LPFC_MAX_WQ_PAGE 8 110 #define LPFC_MAX_CQ_PAGE 4 111 #define LPFC_MAX_EQ_PAGE 8 112 113 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 114 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 115 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 116 117 /* Define SLI4 Alignment requirements. */ 118 #define LPFC_ALIGN_16_BYTE 16 119 #define LPFC_ALIGN_64_BYTE 64 120 121 /* Define SLI4 specific definitions. */ 122 #define LPFC_MQ_CQE_BYTE_OFFSET 256 123 #define LPFC_MBX_CMD_HDR_LENGTH 16 124 #define LPFC_MBX_ERROR_RANGE 0x4000 125 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 126 #define LPFC_BMBX_BIT1_ADDR_LO 0 127 #define LPFC_RPI_HDR_COUNT 64 128 #define LPFC_HDR_TEMPLATE_SIZE 4096 129 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 130 #define LPFC_FCF_RECORD_WD_CNT 132 131 #define LPFC_ENTIRE_FCF_DATABASE 0 132 #define LPFC_DFLT_FCF_INDEX 0 133 134 /* Virtual function numbers */ 135 #define LPFC_VF0 0 136 #define LPFC_VF1 1 137 #define LPFC_VF2 2 138 #define LPFC_VF3 3 139 #define LPFC_VF4 4 140 #define LPFC_VF5 5 141 #define LPFC_VF6 6 142 #define LPFC_VF7 7 143 #define LPFC_VF8 8 144 #define LPFC_VF9 9 145 #define LPFC_VF10 10 146 #define LPFC_VF11 11 147 #define LPFC_VF12 12 148 #define LPFC_VF13 13 149 #define LPFC_VF14 14 150 #define LPFC_VF15 15 151 #define LPFC_VF16 16 152 #define LPFC_VF17 17 153 #define LPFC_VF18 18 154 #define LPFC_VF19 19 155 #define LPFC_VF20 20 156 #define LPFC_VF21 21 157 #define LPFC_VF22 22 158 #define LPFC_VF23 23 159 #define LPFC_VF24 24 160 #define LPFC_VF25 25 161 #define LPFC_VF26 26 162 #define LPFC_VF27 27 163 #define LPFC_VF28 28 164 #define LPFC_VF29 29 165 #define LPFC_VF30 30 166 #define LPFC_VF31 31 167 168 /* PCI function numbers */ 169 #define LPFC_PCI_FUNC0 0 170 #define LPFC_PCI_FUNC1 1 171 #define LPFC_PCI_FUNC2 2 172 #define LPFC_PCI_FUNC3 3 173 #define LPFC_PCI_FUNC4 4 174 175 /* SLI4 interface type-2 PDEV_CTL register */ 176 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 177 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 178 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 179 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 180 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 181 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 182 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 183 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 184 185 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 186 187 /* Active interrupt test count */ 188 #define LPFC_ACT_INTR_CNT 4 189 190 /* Delay Multiplier constant */ 191 #define LPFC_DMULT_CONST 651042 192 #define LPFC_MIM_IMAX 636 193 #define LPFC_FP_DEF_IMAX 10000 194 #define LPFC_SP_DEF_IMAX 10000 195 196 /* PORT_CAPABILITIES constants. */ 197 #define LPFC_MAX_SUPPORTED_PAGES 8 198 199 struct ulp_bde64 { 200 union ULP_BDE_TUS { 201 uint32_t w; 202 struct { 203 #ifdef __BIG_ENDIAN_BITFIELD 204 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 205 VALUE !! */ 206 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 207 #else /* __LITTLE_ENDIAN_BITFIELD */ 208 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 209 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 210 VALUE !! */ 211 #endif 212 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 213 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 214 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 215 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 216 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 217 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 218 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 219 } f; 220 } tus; 221 uint32_t addrLow; 222 uint32_t addrHigh; 223 }; 224 225 struct lpfc_sli4_flags { 226 uint32_t word0; 227 #define lpfc_idx_rsrc_rdy_SHIFT 0 228 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 229 #define lpfc_idx_rsrc_rdy_WORD word0 230 #define LPFC_IDX_RSRC_RDY 1 231 #define lpfc_xri_rsrc_rdy_SHIFT 1 232 #define lpfc_xri_rsrc_rdy_MASK 0x00000001 233 #define lpfc_xri_rsrc_rdy_WORD word0 234 #define LPFC_XRI_RSRC_RDY 1 235 #define lpfc_rpi_rsrc_rdy_SHIFT 2 236 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 237 #define lpfc_rpi_rsrc_rdy_WORD word0 238 #define LPFC_RPI_RSRC_RDY 1 239 #define lpfc_vpi_rsrc_rdy_SHIFT 3 240 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 241 #define lpfc_vpi_rsrc_rdy_WORD word0 242 #define LPFC_VPI_RSRC_RDY 1 243 #define lpfc_vfi_rsrc_rdy_SHIFT 4 244 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 245 #define lpfc_vfi_rsrc_rdy_WORD word0 246 #define LPFC_VFI_RSRC_RDY 1 247 }; 248 249 struct sli4_bls_rsp { 250 uint32_t word0_rsvd; /* Word0 must be reserved */ 251 uint32_t word1; 252 #define lpfc_abts_orig_SHIFT 0 253 #define lpfc_abts_orig_MASK 0x00000001 254 #define lpfc_abts_orig_WORD word1 255 #define LPFC_ABTS_UNSOL_RSP 1 256 #define LPFC_ABTS_UNSOL_INT 0 257 uint32_t word2; 258 #define lpfc_abts_rxid_SHIFT 0 259 #define lpfc_abts_rxid_MASK 0x0000FFFF 260 #define lpfc_abts_rxid_WORD word2 261 #define lpfc_abts_oxid_SHIFT 16 262 #define lpfc_abts_oxid_MASK 0x0000FFFF 263 #define lpfc_abts_oxid_WORD word2 264 uint32_t word3; 265 #define lpfc_vndr_code_SHIFT 0 266 #define lpfc_vndr_code_MASK 0x000000FF 267 #define lpfc_vndr_code_WORD word3 268 #define lpfc_rsn_expln_SHIFT 8 269 #define lpfc_rsn_expln_MASK 0x000000FF 270 #define lpfc_rsn_expln_WORD word3 271 #define lpfc_rsn_code_SHIFT 16 272 #define lpfc_rsn_code_MASK 0x000000FF 273 #define lpfc_rsn_code_WORD word3 274 275 uint32_t word4; 276 uint32_t word5_rsvd; /* Word5 must be reserved */ 277 }; 278 279 /* event queue entry structure */ 280 struct lpfc_eqe { 281 uint32_t word0; 282 #define lpfc_eqe_resource_id_SHIFT 16 283 #define lpfc_eqe_resource_id_MASK 0x000000FF 284 #define lpfc_eqe_resource_id_WORD word0 285 #define lpfc_eqe_minor_code_SHIFT 4 286 #define lpfc_eqe_minor_code_MASK 0x00000FFF 287 #define lpfc_eqe_minor_code_WORD word0 288 #define lpfc_eqe_major_code_SHIFT 1 289 #define lpfc_eqe_major_code_MASK 0x00000007 290 #define lpfc_eqe_major_code_WORD word0 291 #define lpfc_eqe_valid_SHIFT 0 292 #define lpfc_eqe_valid_MASK 0x00000001 293 #define lpfc_eqe_valid_WORD word0 294 }; 295 296 /* completion queue entry structure (common fields for all cqe types) */ 297 struct lpfc_cqe { 298 uint32_t reserved0; 299 uint32_t reserved1; 300 uint32_t reserved2; 301 uint32_t word3; 302 #define lpfc_cqe_valid_SHIFT 31 303 #define lpfc_cqe_valid_MASK 0x00000001 304 #define lpfc_cqe_valid_WORD word3 305 #define lpfc_cqe_code_SHIFT 16 306 #define lpfc_cqe_code_MASK 0x000000FF 307 #define lpfc_cqe_code_WORD word3 308 }; 309 310 /* Completion Queue Entry Status Codes */ 311 #define CQE_STATUS_SUCCESS 0x0 312 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 313 #define CQE_STATUS_REMOTE_STOP 0x2 314 #define CQE_STATUS_LOCAL_REJECT 0x3 315 #define CQE_STATUS_NPORT_RJT 0x4 316 #define CQE_STATUS_FABRIC_RJT 0x5 317 #define CQE_STATUS_NPORT_BSY 0x6 318 #define CQE_STATUS_FABRIC_BSY 0x7 319 #define CQE_STATUS_INTERMED_RSP 0x8 320 #define CQE_STATUS_LS_RJT 0x9 321 #define CQE_STATUS_CMD_REJECT 0xb 322 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 323 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 324 325 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 326 #define CQE_HW_STATUS_NO_ERR 0x0 327 #define CQE_HW_STATUS_UNDERRUN 0x1 328 #define CQE_HW_STATUS_OVERRUN 0x2 329 330 /* Completion Queue Entry Codes */ 331 #define CQE_CODE_COMPL_WQE 0x1 332 #define CQE_CODE_RELEASE_WQE 0x2 333 #define CQE_CODE_RECEIVE 0x4 334 #define CQE_CODE_XRI_ABORTED 0x5 335 #define CQE_CODE_RECEIVE_V1 0x9 336 337 /* completion queue entry for wqe completions */ 338 struct lpfc_wcqe_complete { 339 uint32_t word0; 340 #define lpfc_wcqe_c_request_tag_SHIFT 16 341 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 342 #define lpfc_wcqe_c_request_tag_WORD word0 343 #define lpfc_wcqe_c_status_SHIFT 8 344 #define lpfc_wcqe_c_status_MASK 0x000000FF 345 #define lpfc_wcqe_c_status_WORD word0 346 #define lpfc_wcqe_c_hw_status_SHIFT 0 347 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 348 #define lpfc_wcqe_c_hw_status_WORD word0 349 uint32_t total_data_placed; 350 uint32_t parameter; 351 uint32_t word3; 352 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 353 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 354 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 355 #define lpfc_wcqe_c_xb_SHIFT 28 356 #define lpfc_wcqe_c_xb_MASK 0x00000001 357 #define lpfc_wcqe_c_xb_WORD word3 358 #define lpfc_wcqe_c_pv_SHIFT 27 359 #define lpfc_wcqe_c_pv_MASK 0x00000001 360 #define lpfc_wcqe_c_pv_WORD word3 361 #define lpfc_wcqe_c_priority_SHIFT 24 362 #define lpfc_wcqe_c_priority_MASK 0x00000007 363 #define lpfc_wcqe_c_priority_WORD word3 364 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 365 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 366 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 367 }; 368 369 /* completion queue entry for wqe release */ 370 struct lpfc_wcqe_release { 371 uint32_t reserved0; 372 uint32_t reserved1; 373 uint32_t word2; 374 #define lpfc_wcqe_r_wq_id_SHIFT 16 375 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 376 #define lpfc_wcqe_r_wq_id_WORD word2 377 #define lpfc_wcqe_r_wqe_index_SHIFT 0 378 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 379 #define lpfc_wcqe_r_wqe_index_WORD word2 380 uint32_t word3; 381 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 382 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 383 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 384 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 385 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 386 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 387 }; 388 389 struct sli4_wcqe_xri_aborted { 390 uint32_t word0; 391 #define lpfc_wcqe_xa_status_SHIFT 8 392 #define lpfc_wcqe_xa_status_MASK 0x000000FF 393 #define lpfc_wcqe_xa_status_WORD word0 394 uint32_t parameter; 395 uint32_t word2; 396 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 397 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 398 #define lpfc_wcqe_xa_remote_xid_WORD word2 399 #define lpfc_wcqe_xa_xri_SHIFT 0 400 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 401 #define lpfc_wcqe_xa_xri_WORD word2 402 uint32_t word3; 403 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 404 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 405 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 406 #define lpfc_wcqe_xa_ia_SHIFT 30 407 #define lpfc_wcqe_xa_ia_MASK 0x00000001 408 #define lpfc_wcqe_xa_ia_WORD word3 409 #define CQE_XRI_ABORTED_IA_REMOTE 0 410 #define CQE_XRI_ABORTED_IA_LOCAL 1 411 #define lpfc_wcqe_xa_br_SHIFT 29 412 #define lpfc_wcqe_xa_br_MASK 0x00000001 413 #define lpfc_wcqe_xa_br_WORD word3 414 #define CQE_XRI_ABORTED_BR_BA_ACC 0 415 #define CQE_XRI_ABORTED_BR_BA_RJT 1 416 #define lpfc_wcqe_xa_eo_SHIFT 28 417 #define lpfc_wcqe_xa_eo_MASK 0x00000001 418 #define lpfc_wcqe_xa_eo_WORD word3 419 #define CQE_XRI_ABORTED_EO_REMOTE 0 420 #define CQE_XRI_ABORTED_EO_LOCAL 1 421 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 422 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 423 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 424 }; 425 426 /* completion queue entry structure for rqe completion */ 427 struct lpfc_rcqe { 428 uint32_t word0; 429 #define lpfc_rcqe_bindex_SHIFT 16 430 #define lpfc_rcqe_bindex_MASK 0x0000FFF 431 #define lpfc_rcqe_bindex_WORD word0 432 #define lpfc_rcqe_status_SHIFT 8 433 #define lpfc_rcqe_status_MASK 0x000000FF 434 #define lpfc_rcqe_status_WORD word0 435 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 436 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 437 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 438 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 439 uint32_t word1; 440 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 441 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 442 #define lpfc_rcqe_fcf_id_v1_WORD word1 443 uint32_t word2; 444 #define lpfc_rcqe_length_SHIFT 16 445 #define lpfc_rcqe_length_MASK 0x0000FFFF 446 #define lpfc_rcqe_length_WORD word2 447 #define lpfc_rcqe_rq_id_SHIFT 6 448 #define lpfc_rcqe_rq_id_MASK 0x000003FF 449 #define lpfc_rcqe_rq_id_WORD word2 450 #define lpfc_rcqe_fcf_id_SHIFT 0 451 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 452 #define lpfc_rcqe_fcf_id_WORD word2 453 #define lpfc_rcqe_rq_id_v1_SHIFT 0 454 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 455 #define lpfc_rcqe_rq_id_v1_WORD word2 456 uint32_t word3; 457 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 458 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 459 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 460 #define lpfc_rcqe_port_SHIFT 30 461 #define lpfc_rcqe_port_MASK 0x00000001 462 #define lpfc_rcqe_port_WORD word3 463 #define lpfc_rcqe_hdr_length_SHIFT 24 464 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 465 #define lpfc_rcqe_hdr_length_WORD word3 466 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 467 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 468 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 469 #define lpfc_rcqe_eof_SHIFT 8 470 #define lpfc_rcqe_eof_MASK 0x000000FF 471 #define lpfc_rcqe_eof_WORD word3 472 #define FCOE_EOFn 0x41 473 #define FCOE_EOFt 0x42 474 #define FCOE_EOFni 0x49 475 #define FCOE_EOFa 0x50 476 #define lpfc_rcqe_sof_SHIFT 0 477 #define lpfc_rcqe_sof_MASK 0x000000FF 478 #define lpfc_rcqe_sof_WORD word3 479 #define FCOE_SOFi2 0x2d 480 #define FCOE_SOFi3 0x2e 481 #define FCOE_SOFn2 0x35 482 #define FCOE_SOFn3 0x36 483 }; 484 485 struct lpfc_rqe { 486 uint32_t address_hi; 487 uint32_t address_lo; 488 }; 489 490 /* buffer descriptors */ 491 struct lpfc_bde4 { 492 uint32_t addr_hi; 493 uint32_t addr_lo; 494 uint32_t word2; 495 #define lpfc_bde4_last_SHIFT 31 496 #define lpfc_bde4_last_MASK 0x00000001 497 #define lpfc_bde4_last_WORD word2 498 #define lpfc_bde4_sge_offset_SHIFT 0 499 #define lpfc_bde4_sge_offset_MASK 0x000003FF 500 #define lpfc_bde4_sge_offset_WORD word2 501 uint32_t word3; 502 #define lpfc_bde4_length_SHIFT 0 503 #define lpfc_bde4_length_MASK 0x000000FF 504 #define lpfc_bde4_length_WORD word3 505 }; 506 507 struct lpfc_register { 508 uint32_t word0; 509 }; 510 511 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 512 #define LPFC_UERR_STATUS_HI 0x00A4 513 #define LPFC_UERR_STATUS_LO 0x00A0 514 #define LPFC_UE_MASK_HI 0x00AC 515 #define LPFC_UE_MASK_LO 0x00A8 516 517 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 518 #define LPFC_SLI_INTF 0x0058 519 520 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 521 #define lpfc_port_smphr_perr_SHIFT 31 522 #define lpfc_port_smphr_perr_MASK 0x1 523 #define lpfc_port_smphr_perr_WORD word0 524 #define lpfc_port_smphr_sfi_SHIFT 30 525 #define lpfc_port_smphr_sfi_MASK 0x1 526 #define lpfc_port_smphr_sfi_WORD word0 527 #define lpfc_port_smphr_nip_SHIFT 29 528 #define lpfc_port_smphr_nip_MASK 0x1 529 #define lpfc_port_smphr_nip_WORD word0 530 #define lpfc_port_smphr_ipc_SHIFT 28 531 #define lpfc_port_smphr_ipc_MASK 0x1 532 #define lpfc_port_smphr_ipc_WORD word0 533 #define lpfc_port_smphr_scr1_SHIFT 27 534 #define lpfc_port_smphr_scr1_MASK 0x1 535 #define lpfc_port_smphr_scr1_WORD word0 536 #define lpfc_port_smphr_scr2_SHIFT 26 537 #define lpfc_port_smphr_scr2_MASK 0x1 538 #define lpfc_port_smphr_scr2_WORD word0 539 #define lpfc_port_smphr_host_scratch_SHIFT 16 540 #define lpfc_port_smphr_host_scratch_MASK 0xFF 541 #define lpfc_port_smphr_host_scratch_WORD word0 542 #define lpfc_port_smphr_port_status_SHIFT 0 543 #define lpfc_port_smphr_port_status_MASK 0xFFFF 544 #define lpfc_port_smphr_port_status_WORD word0 545 546 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 547 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 548 #define LPFC_POST_STAGE_HOST_RDY 0x0002 549 #define LPFC_POST_STAGE_BE_RESET 0x0003 550 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 551 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 552 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 553 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 554 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 555 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 556 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 557 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 558 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 559 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 560 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 561 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 562 #define LPFC_POST_STAGE_ARMFW_START 0x0800 563 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 564 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 565 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 566 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 567 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 568 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 569 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 570 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 571 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 572 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 573 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 574 #define LPFC_POST_STAGE_RC_DONE 0x0B07 575 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 576 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 577 #define LPFC_POST_STAGE_PORT_READY 0xC000 578 #define LPFC_POST_STAGE_PORT_UE 0xF000 579 580 #define LPFC_CTL_PORT_STA_OFFSET 0x404 581 #define lpfc_sliport_status_err_SHIFT 31 582 #define lpfc_sliport_status_err_MASK 0x1 583 #define lpfc_sliport_status_err_WORD word0 584 #define lpfc_sliport_status_end_SHIFT 30 585 #define lpfc_sliport_status_end_MASK 0x1 586 #define lpfc_sliport_status_end_WORD word0 587 #define lpfc_sliport_status_oti_SHIFT 29 588 #define lpfc_sliport_status_oti_MASK 0x1 589 #define lpfc_sliport_status_oti_WORD word0 590 #define lpfc_sliport_status_rn_SHIFT 24 591 #define lpfc_sliport_status_rn_MASK 0x1 592 #define lpfc_sliport_status_rn_WORD word0 593 #define lpfc_sliport_status_rdy_SHIFT 23 594 #define lpfc_sliport_status_rdy_MASK 0x1 595 #define lpfc_sliport_status_rdy_WORD word0 596 #define MAX_IF_TYPE_2_RESETS 1000 597 598 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 599 #define lpfc_sliport_ctrl_end_SHIFT 30 600 #define lpfc_sliport_ctrl_end_MASK 0x1 601 #define lpfc_sliport_ctrl_end_WORD word0 602 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 603 #define LPFC_SLIPORT_BIG_ENDIAN 1 604 #define lpfc_sliport_ctrl_ip_SHIFT 27 605 #define lpfc_sliport_ctrl_ip_MASK 0x1 606 #define lpfc_sliport_ctrl_ip_WORD word0 607 #define LPFC_SLIPORT_INIT_PORT 1 608 609 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 610 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 611 612 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 613 * reside in BAR 2. 614 */ 615 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 616 617 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 618 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 619 620 #define LPFC_HST_ISR0 0x0C18 621 #define LPFC_HST_ISR1 0x0C1C 622 #define LPFC_HST_ISR2 0x0C20 623 #define LPFC_HST_ISR3 0x0C24 624 #define LPFC_HST_ISR4 0x0C28 625 626 #define LPFC_HST_IMR0 0x0C48 627 #define LPFC_HST_IMR1 0x0C4C 628 #define LPFC_HST_IMR2 0x0C50 629 #define LPFC_HST_IMR3 0x0C54 630 #define LPFC_HST_IMR4 0x0C58 631 632 #define LPFC_HST_ISCR0 0x0C78 633 #define LPFC_HST_ISCR1 0x0C7C 634 #define LPFC_HST_ISCR2 0x0C80 635 #define LPFC_HST_ISCR3 0x0C84 636 #define LPFC_HST_ISCR4 0x0C88 637 638 #define LPFC_SLI4_INTR0 BIT0 639 #define LPFC_SLI4_INTR1 BIT1 640 #define LPFC_SLI4_INTR2 BIT2 641 #define LPFC_SLI4_INTR3 BIT3 642 #define LPFC_SLI4_INTR4 BIT4 643 #define LPFC_SLI4_INTR5 BIT5 644 #define LPFC_SLI4_INTR6 BIT6 645 #define LPFC_SLI4_INTR7 BIT7 646 #define LPFC_SLI4_INTR8 BIT8 647 #define LPFC_SLI4_INTR9 BIT9 648 #define LPFC_SLI4_INTR10 BIT10 649 #define LPFC_SLI4_INTR11 BIT11 650 #define LPFC_SLI4_INTR12 BIT12 651 #define LPFC_SLI4_INTR13 BIT13 652 #define LPFC_SLI4_INTR14 BIT14 653 #define LPFC_SLI4_INTR15 BIT15 654 #define LPFC_SLI4_INTR16 BIT16 655 #define LPFC_SLI4_INTR17 BIT17 656 #define LPFC_SLI4_INTR18 BIT18 657 #define LPFC_SLI4_INTR19 BIT19 658 #define LPFC_SLI4_INTR20 BIT20 659 #define LPFC_SLI4_INTR21 BIT21 660 #define LPFC_SLI4_INTR22 BIT22 661 #define LPFC_SLI4_INTR23 BIT23 662 #define LPFC_SLI4_INTR24 BIT24 663 #define LPFC_SLI4_INTR25 BIT25 664 #define LPFC_SLI4_INTR26 BIT26 665 #define LPFC_SLI4_INTR27 BIT27 666 #define LPFC_SLI4_INTR28 BIT28 667 #define LPFC_SLI4_INTR29 BIT29 668 #define LPFC_SLI4_INTR30 BIT30 669 #define LPFC_SLI4_INTR31 BIT31 670 671 /* 672 * The Doorbell registers defined here exist in different BAR 673 * register sets depending on the UCNA Port's reported if_type 674 * value. For UCNA ports running SLI4 and if_type 0, they reside in 675 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 676 * BAR0. The offsets are the same so the driver must account for 677 * any base address difference. 678 */ 679 #define LPFC_RQ_DOORBELL 0x00A0 680 #define lpfc_rq_doorbell_num_posted_SHIFT 16 681 #define lpfc_rq_doorbell_num_posted_MASK 0x3FFF 682 #define lpfc_rq_doorbell_num_posted_WORD word0 683 #define lpfc_rq_doorbell_id_SHIFT 0 684 #define lpfc_rq_doorbell_id_MASK 0xFFFF 685 #define lpfc_rq_doorbell_id_WORD word0 686 687 #define LPFC_WQ_DOORBELL 0x0040 688 #define lpfc_wq_doorbell_num_posted_SHIFT 24 689 #define lpfc_wq_doorbell_num_posted_MASK 0x00FF 690 #define lpfc_wq_doorbell_num_posted_WORD word0 691 #define lpfc_wq_doorbell_index_SHIFT 16 692 #define lpfc_wq_doorbell_index_MASK 0x00FF 693 #define lpfc_wq_doorbell_index_WORD word0 694 #define lpfc_wq_doorbell_id_SHIFT 0 695 #define lpfc_wq_doorbell_id_MASK 0xFFFF 696 #define lpfc_wq_doorbell_id_WORD word0 697 698 #define LPFC_EQCQ_DOORBELL 0x0120 699 #define lpfc_eqcq_doorbell_se_SHIFT 31 700 #define lpfc_eqcq_doorbell_se_MASK 0x0001 701 #define lpfc_eqcq_doorbell_se_WORD word0 702 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 703 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 704 #define lpfc_eqcq_doorbell_arm_SHIFT 29 705 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 706 #define lpfc_eqcq_doorbell_arm_WORD word0 707 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 708 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 709 #define lpfc_eqcq_doorbell_num_released_WORD word0 710 #define lpfc_eqcq_doorbell_qt_SHIFT 10 711 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 712 #define lpfc_eqcq_doorbell_qt_WORD word0 713 #define LPFC_QUEUE_TYPE_COMPLETION 0 714 #define LPFC_QUEUE_TYPE_EVENT 1 715 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 716 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 717 #define lpfc_eqcq_doorbell_eqci_WORD word0 718 #define lpfc_eqcq_doorbell_cqid_SHIFT 0 719 #define lpfc_eqcq_doorbell_cqid_MASK 0x03FF 720 #define lpfc_eqcq_doorbell_cqid_WORD word0 721 #define lpfc_eqcq_doorbell_eqid_SHIFT 0 722 #define lpfc_eqcq_doorbell_eqid_MASK 0x01FF 723 #define lpfc_eqcq_doorbell_eqid_WORD word0 724 725 #define LPFC_BMBX 0x0160 726 #define lpfc_bmbx_addr_SHIFT 2 727 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 728 #define lpfc_bmbx_addr_WORD word0 729 #define lpfc_bmbx_hi_SHIFT 1 730 #define lpfc_bmbx_hi_MASK 0x0001 731 #define lpfc_bmbx_hi_WORD word0 732 #define lpfc_bmbx_rdy_SHIFT 0 733 #define lpfc_bmbx_rdy_MASK 0x0001 734 #define lpfc_bmbx_rdy_WORD word0 735 736 #define LPFC_MQ_DOORBELL 0x0140 737 #define lpfc_mq_doorbell_num_posted_SHIFT 16 738 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 739 #define lpfc_mq_doorbell_num_posted_WORD word0 740 #define lpfc_mq_doorbell_id_SHIFT 0 741 #define lpfc_mq_doorbell_id_MASK 0xFFFF 742 #define lpfc_mq_doorbell_id_WORD word0 743 744 struct lpfc_sli4_cfg_mhdr { 745 uint32_t word1; 746 #define lpfc_mbox_hdr_emb_SHIFT 0 747 #define lpfc_mbox_hdr_emb_MASK 0x00000001 748 #define lpfc_mbox_hdr_emb_WORD word1 749 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 750 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 751 #define lpfc_mbox_hdr_sge_cnt_WORD word1 752 uint32_t payload_length; 753 uint32_t tag_lo; 754 uint32_t tag_hi; 755 uint32_t reserved5; 756 }; 757 758 union lpfc_sli4_cfg_shdr { 759 struct { 760 uint32_t word6; 761 #define lpfc_mbox_hdr_opcode_SHIFT 0 762 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 763 #define lpfc_mbox_hdr_opcode_WORD word6 764 #define lpfc_mbox_hdr_subsystem_SHIFT 8 765 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 766 #define lpfc_mbox_hdr_subsystem_WORD word6 767 #define lpfc_mbox_hdr_port_number_SHIFT 16 768 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 769 #define lpfc_mbox_hdr_port_number_WORD word6 770 #define lpfc_mbox_hdr_domain_SHIFT 24 771 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 772 #define lpfc_mbox_hdr_domain_WORD word6 773 uint32_t timeout; 774 uint32_t request_length; 775 uint32_t word9; 776 #define lpfc_mbox_hdr_version_SHIFT 0 777 #define lpfc_mbox_hdr_version_MASK 0x000000FF 778 #define lpfc_mbox_hdr_version_WORD word9 779 #define lpfc_mbox_hdr_pf_num_SHIFT 16 780 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 781 #define lpfc_mbox_hdr_pf_num_WORD word9 782 #define lpfc_mbox_hdr_vh_num_SHIFT 24 783 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 784 #define lpfc_mbox_hdr_vh_num_WORD word9 785 #define LPFC_Q_CREATE_VERSION_2 2 786 #define LPFC_Q_CREATE_VERSION_1 1 787 #define LPFC_Q_CREATE_VERSION_0 0 788 #define LPFC_OPCODE_VERSION_0 0 789 #define LPFC_OPCODE_VERSION_1 1 790 } request; 791 struct { 792 uint32_t word6; 793 #define lpfc_mbox_hdr_opcode_SHIFT 0 794 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 795 #define lpfc_mbox_hdr_opcode_WORD word6 796 #define lpfc_mbox_hdr_subsystem_SHIFT 8 797 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 798 #define lpfc_mbox_hdr_subsystem_WORD word6 799 #define lpfc_mbox_hdr_domain_SHIFT 24 800 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 801 #define lpfc_mbox_hdr_domain_WORD word6 802 uint32_t word7; 803 #define lpfc_mbox_hdr_status_SHIFT 0 804 #define lpfc_mbox_hdr_status_MASK 0x000000FF 805 #define lpfc_mbox_hdr_status_WORD word7 806 #define lpfc_mbox_hdr_add_status_SHIFT 8 807 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 808 #define lpfc_mbox_hdr_add_status_WORD word7 809 uint32_t response_length; 810 uint32_t actual_response_length; 811 } response; 812 }; 813 814 /* Mailbox Header structures. 815 * struct mbox_header is defined for first generation SLI4_CFG mailbox 816 * calls deployed for BE-based ports. 817 * 818 * struct sli4_mbox_header is defined for second generation SLI4 819 * ports that don't deploy the SLI4_CFG mechanism. 820 */ 821 struct mbox_header { 822 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 823 union lpfc_sli4_cfg_shdr cfg_shdr; 824 }; 825 826 #define LPFC_EXTENT_LOCAL 0 827 #define LPFC_TIMEOUT_DEFAULT 0 828 #define LPFC_EXTENT_VERSION_DEFAULT 0 829 830 /* Subsystem Definitions */ 831 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 832 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 833 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 834 835 /* Device Specific Definitions */ 836 837 /* The HOST ENDIAN defines are in Big Endian format. */ 838 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 839 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 840 841 /* Common Opcodes */ 842 #define LPFC_MBOX_OPCODE_NA 0x00 843 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 844 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 845 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 846 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 847 #define LPFC_MBOX_OPCODE_NOP 0x21 848 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 849 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 850 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 851 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 852 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 853 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 854 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 855 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 856 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 857 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 858 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 859 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 860 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 861 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 862 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 863 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 864 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 865 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 866 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 867 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 868 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 869 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 870 871 /* FCoE Opcodes */ 872 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 873 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 874 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 875 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 876 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 877 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 878 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 879 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 880 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 881 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 882 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 883 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 884 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 885 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 886 887 /* Mailbox command structures */ 888 struct eq_context { 889 uint32_t word0; 890 #define lpfc_eq_context_size_SHIFT 31 891 #define lpfc_eq_context_size_MASK 0x00000001 892 #define lpfc_eq_context_size_WORD word0 893 #define LPFC_EQE_SIZE_4 0x0 894 #define LPFC_EQE_SIZE_16 0x1 895 #define lpfc_eq_context_valid_SHIFT 29 896 #define lpfc_eq_context_valid_MASK 0x00000001 897 #define lpfc_eq_context_valid_WORD word0 898 uint32_t word1; 899 #define lpfc_eq_context_count_SHIFT 26 900 #define lpfc_eq_context_count_MASK 0x00000003 901 #define lpfc_eq_context_count_WORD word1 902 #define LPFC_EQ_CNT_256 0x0 903 #define LPFC_EQ_CNT_512 0x1 904 #define LPFC_EQ_CNT_1024 0x2 905 #define LPFC_EQ_CNT_2048 0x3 906 #define LPFC_EQ_CNT_4096 0x4 907 uint32_t word2; 908 #define lpfc_eq_context_delay_multi_SHIFT 13 909 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 910 #define lpfc_eq_context_delay_multi_WORD word2 911 uint32_t reserved3; 912 }; 913 914 struct sgl_page_pairs { 915 uint32_t sgl_pg0_addr_lo; 916 uint32_t sgl_pg0_addr_hi; 917 uint32_t sgl_pg1_addr_lo; 918 uint32_t sgl_pg1_addr_hi; 919 }; 920 921 struct lpfc_mbx_post_sgl_pages { 922 struct mbox_header header; 923 uint32_t word0; 924 #define lpfc_post_sgl_pages_xri_SHIFT 0 925 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 926 #define lpfc_post_sgl_pages_xri_WORD word0 927 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 928 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 929 #define lpfc_post_sgl_pages_xricnt_WORD word0 930 struct sgl_page_pairs sgl_pg_pairs[1]; 931 }; 932 933 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 934 struct lpfc_mbx_post_uembed_sgl_page1 { 935 union lpfc_sli4_cfg_shdr cfg_shdr; 936 uint32_t word0; 937 struct sgl_page_pairs sgl_pg_pairs; 938 }; 939 940 struct lpfc_mbx_sge { 941 uint32_t pa_lo; 942 uint32_t pa_hi; 943 uint32_t length; 944 }; 945 946 struct lpfc_mbx_nembed_cmd { 947 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 948 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 949 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 950 }; 951 952 struct lpfc_mbx_nembed_sge_virt { 953 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 954 }; 955 956 struct lpfc_mbx_eq_create { 957 struct mbox_header header; 958 union { 959 struct { 960 uint32_t word0; 961 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 962 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 963 #define lpfc_mbx_eq_create_num_pages_WORD word0 964 struct eq_context context; 965 struct dma_address page[LPFC_MAX_EQ_PAGE]; 966 } request; 967 struct { 968 uint32_t word0; 969 #define lpfc_mbx_eq_create_q_id_SHIFT 0 970 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 971 #define lpfc_mbx_eq_create_q_id_WORD word0 972 } response; 973 } u; 974 }; 975 976 struct lpfc_mbx_eq_destroy { 977 struct mbox_header header; 978 union { 979 struct { 980 uint32_t word0; 981 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 982 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 983 #define lpfc_mbx_eq_destroy_q_id_WORD word0 984 } request; 985 struct { 986 uint32_t word0; 987 } response; 988 } u; 989 }; 990 991 struct lpfc_mbx_nop { 992 struct mbox_header header; 993 uint32_t context[2]; 994 }; 995 996 struct cq_context { 997 uint32_t word0; 998 #define lpfc_cq_context_event_SHIFT 31 999 #define lpfc_cq_context_event_MASK 0x00000001 1000 #define lpfc_cq_context_event_WORD word0 1001 #define lpfc_cq_context_valid_SHIFT 29 1002 #define lpfc_cq_context_valid_MASK 0x00000001 1003 #define lpfc_cq_context_valid_WORD word0 1004 #define lpfc_cq_context_count_SHIFT 27 1005 #define lpfc_cq_context_count_MASK 0x00000003 1006 #define lpfc_cq_context_count_WORD word0 1007 #define LPFC_CQ_CNT_256 0x0 1008 #define LPFC_CQ_CNT_512 0x1 1009 #define LPFC_CQ_CNT_1024 0x2 1010 uint32_t word1; 1011 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1012 #define lpfc_cq_eq_id_MASK 0x000000FF 1013 #define lpfc_cq_eq_id_WORD word1 1014 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1015 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1016 #define lpfc_cq_eq_id_2_WORD word1 1017 uint32_t reserved0; 1018 uint32_t reserved1; 1019 }; 1020 1021 struct lpfc_mbx_cq_create { 1022 struct mbox_header header; 1023 union { 1024 struct { 1025 uint32_t word0; 1026 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1027 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1028 #define lpfc_mbx_cq_create_page_size_WORD word0 1029 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1030 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1031 #define lpfc_mbx_cq_create_num_pages_WORD word0 1032 struct cq_context context; 1033 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1034 } request; 1035 struct { 1036 uint32_t word0; 1037 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1038 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1039 #define lpfc_mbx_cq_create_q_id_WORD word0 1040 } response; 1041 } u; 1042 }; 1043 1044 struct lpfc_mbx_cq_destroy { 1045 struct mbox_header header; 1046 union { 1047 struct { 1048 uint32_t word0; 1049 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1050 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1051 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1052 } request; 1053 struct { 1054 uint32_t word0; 1055 } response; 1056 } u; 1057 }; 1058 1059 struct wq_context { 1060 uint32_t reserved0; 1061 uint32_t reserved1; 1062 uint32_t reserved2; 1063 uint32_t reserved3; 1064 }; 1065 1066 struct lpfc_mbx_wq_create { 1067 struct mbox_header header; 1068 union { 1069 struct { /* Version 0 Request */ 1070 uint32_t word0; 1071 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1072 #define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF 1073 #define lpfc_mbx_wq_create_num_pages_WORD word0 1074 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1075 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1076 #define lpfc_mbx_wq_create_cq_id_WORD word0 1077 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1078 } request; 1079 struct { /* Version 1 Request */ 1080 uint32_t word0; /* Word 0 is the same as in v0 */ 1081 uint32_t word1; 1082 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1083 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1084 #define lpfc_mbx_wq_create_page_size_WORD word1 1085 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1086 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1087 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1088 #define LPFC_WQ_WQE_SIZE_64 0x5 1089 #define LPFC_WQ_WQE_SIZE_128 0x6 1090 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1091 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1092 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1093 uint32_t word2; 1094 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1095 } request_1; 1096 struct { 1097 uint32_t word0; 1098 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1099 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1100 #define lpfc_mbx_wq_create_q_id_WORD word0 1101 } response; 1102 } u; 1103 }; 1104 1105 struct lpfc_mbx_wq_destroy { 1106 struct mbox_header header; 1107 union { 1108 struct { 1109 uint32_t word0; 1110 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1111 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1112 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1113 } request; 1114 struct { 1115 uint32_t word0; 1116 } response; 1117 } u; 1118 }; 1119 1120 #define LPFC_HDR_BUF_SIZE 128 1121 #define LPFC_DATA_BUF_SIZE 2048 1122 struct rq_context { 1123 uint32_t word0; 1124 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1125 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1126 #define lpfc_rq_context_rqe_count_WORD word0 1127 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1128 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1129 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1130 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1131 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */ 1132 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1133 #define lpfc_rq_context_rqe_count_1_WORD word0 1134 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */ 1135 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1136 #define lpfc_rq_context_rqe_size_WORD word0 1137 #define LPFC_RQE_SIZE_8 2 1138 #define LPFC_RQE_SIZE_16 3 1139 #define LPFC_RQE_SIZE_32 4 1140 #define LPFC_RQE_SIZE_64 5 1141 #define LPFC_RQE_SIZE_128 6 1142 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1143 #define lpfc_rq_context_page_size_MASK 0x000000FF 1144 #define lpfc_rq_context_page_size_WORD word0 1145 uint32_t reserved1; 1146 uint32_t word2; 1147 #define lpfc_rq_context_cq_id_SHIFT 16 1148 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1149 #define lpfc_rq_context_cq_id_WORD word2 1150 #define lpfc_rq_context_buf_size_SHIFT 0 1151 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1152 #define lpfc_rq_context_buf_size_WORD word2 1153 uint32_t buffer_size; /* Version 1 Only */ 1154 }; 1155 1156 struct lpfc_mbx_rq_create { 1157 struct mbox_header header; 1158 union { 1159 struct { 1160 uint32_t word0; 1161 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1162 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1163 #define lpfc_mbx_rq_create_num_pages_WORD word0 1164 struct rq_context context; 1165 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1166 } request; 1167 struct { 1168 uint32_t word0; 1169 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1170 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1171 #define lpfc_mbx_rq_create_q_id_WORD word0 1172 } response; 1173 } u; 1174 }; 1175 1176 struct lpfc_mbx_rq_destroy { 1177 struct mbox_header header; 1178 union { 1179 struct { 1180 uint32_t word0; 1181 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1182 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1183 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1184 } request; 1185 struct { 1186 uint32_t word0; 1187 } response; 1188 } u; 1189 }; 1190 1191 struct mq_context { 1192 uint32_t word0; 1193 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1194 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1195 #define lpfc_mq_context_cq_id_WORD word0 1196 #define lpfc_mq_context_ring_size_SHIFT 16 1197 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1198 #define lpfc_mq_context_ring_size_WORD word0 1199 #define LPFC_MQ_RING_SIZE_16 0x5 1200 #define LPFC_MQ_RING_SIZE_32 0x6 1201 #define LPFC_MQ_RING_SIZE_64 0x7 1202 #define LPFC_MQ_RING_SIZE_128 0x8 1203 uint32_t word1; 1204 #define lpfc_mq_context_valid_SHIFT 31 1205 #define lpfc_mq_context_valid_MASK 0x00000001 1206 #define lpfc_mq_context_valid_WORD word1 1207 uint32_t reserved2; 1208 uint32_t reserved3; 1209 }; 1210 1211 struct lpfc_mbx_mq_create { 1212 struct mbox_header header; 1213 union { 1214 struct { 1215 uint32_t word0; 1216 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1217 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1218 #define lpfc_mbx_mq_create_num_pages_WORD word0 1219 struct mq_context context; 1220 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1221 } request; 1222 struct { 1223 uint32_t word0; 1224 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1225 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1226 #define lpfc_mbx_mq_create_q_id_WORD word0 1227 } response; 1228 } u; 1229 }; 1230 1231 struct lpfc_mbx_mq_create_ext { 1232 struct mbox_header header; 1233 union { 1234 struct { 1235 uint32_t word0; 1236 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1237 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1238 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1239 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1240 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1241 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1242 uint32_t async_evt_bmap; 1243 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1244 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1245 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1246 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1247 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1248 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1249 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1250 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1251 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1252 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1253 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1254 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1255 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1256 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1257 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1258 struct mq_context context; 1259 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1260 } request; 1261 struct { 1262 uint32_t word0; 1263 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1264 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1265 #define lpfc_mbx_mq_create_q_id_WORD word0 1266 } response; 1267 } u; 1268 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1269 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1270 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1271 }; 1272 1273 struct lpfc_mbx_mq_destroy { 1274 struct mbox_header header; 1275 union { 1276 struct { 1277 uint32_t word0; 1278 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1279 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1280 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1281 } request; 1282 struct { 1283 uint32_t word0; 1284 } response; 1285 } u; 1286 }; 1287 1288 /* Start Gen 2 SLI4 Mailbox definitions: */ 1289 1290 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1291 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1292 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1293 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1294 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1295 1296 struct lpfc_mbx_get_rsrc_extent_info { 1297 struct mbox_header header; 1298 union { 1299 struct { 1300 uint32_t word4; 1301 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1302 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1303 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1304 } req; 1305 struct { 1306 uint32_t word4; 1307 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1308 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1309 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1310 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1311 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1312 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1313 } rsp; 1314 } u; 1315 }; 1316 1317 struct lpfc_id_range { 1318 uint32_t word5; 1319 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1320 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1321 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1322 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1323 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1324 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1325 }; 1326 1327 struct lpfc_mbx_set_link_diag_state { 1328 struct mbox_header header; 1329 union { 1330 struct { 1331 uint32_t word0; 1332 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1333 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1334 #define lpfc_mbx_set_diag_state_diag_WORD word0 1335 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1336 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1337 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1338 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1339 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1340 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1341 } req; 1342 struct { 1343 uint32_t word0; 1344 } rsp; 1345 } u; 1346 }; 1347 1348 struct lpfc_mbx_set_link_diag_loopback { 1349 struct mbox_header header; 1350 union { 1351 struct { 1352 uint32_t word0; 1353 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1354 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1355 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1356 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1357 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1358 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1359 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1360 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1361 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1362 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1363 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1364 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1365 } req; 1366 struct { 1367 uint32_t word0; 1368 } rsp; 1369 } u; 1370 }; 1371 1372 struct lpfc_mbx_run_link_diag_test { 1373 struct mbox_header header; 1374 union { 1375 struct { 1376 uint32_t word0; 1377 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1378 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1379 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1380 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1381 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1382 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1383 uint32_t word1; 1384 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1385 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1386 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1387 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1388 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1389 #define lpfc_mbx_run_diag_test_loops_WORD word1 1390 uint32_t word2; 1391 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1392 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1393 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1394 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1395 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1396 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1397 } req; 1398 struct { 1399 uint32_t word0; 1400 } rsp; 1401 } u; 1402 }; 1403 1404 /* 1405 * struct lpfc_mbx_alloc_rsrc_extents: 1406 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1407 * 6 words of header + 4 words of shared subcommand header + 1408 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1409 * 1410 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1411 * for extents payload. 1412 * 1413 * 212/2 (bytes per extent) = 106 extents. 1414 * 106/2 (extents per word) = 53 words. 1415 * lpfc_id_range id is statically size to 53. 1416 * 1417 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1418 * extent ranges. For ALLOC, the type and cnt are required. 1419 * For GET_ALLOCATED, only the type is required. 1420 */ 1421 struct lpfc_mbx_alloc_rsrc_extents { 1422 struct mbox_header header; 1423 union { 1424 struct { 1425 uint32_t word4; 1426 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1427 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1428 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1429 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1430 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1431 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1432 } req; 1433 struct { 1434 uint32_t word4; 1435 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1436 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1437 #define lpfc_mbx_rsrc_cnt_WORD word4 1438 struct lpfc_id_range id[53]; 1439 } rsp; 1440 } u; 1441 }; 1442 1443 /* 1444 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1445 * structure shares the same SHIFT/MASK/WORD defines provided in the 1446 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1447 * the structures defined above. This non-embedded structure provides for the 1448 * maximum number of extents supported by the port. 1449 */ 1450 struct lpfc_mbx_nembed_rsrc_extent { 1451 union lpfc_sli4_cfg_shdr cfg_shdr; 1452 uint32_t word4; 1453 struct lpfc_id_range id; 1454 }; 1455 1456 struct lpfc_mbx_dealloc_rsrc_extents { 1457 struct mbox_header header; 1458 struct { 1459 uint32_t word4; 1460 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1461 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1462 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1463 } req; 1464 1465 }; 1466 1467 /* Start SLI4 FCoE specific mbox structures. */ 1468 1469 struct lpfc_mbx_post_hdr_tmpl { 1470 struct mbox_header header; 1471 uint32_t word10; 1472 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1473 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1474 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1475 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1476 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1477 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1478 uint32_t rpi_paddr_lo; 1479 uint32_t rpi_paddr_hi; 1480 }; 1481 1482 struct sli4_sge { /* SLI-4 */ 1483 uint32_t addr_hi; 1484 uint32_t addr_lo; 1485 1486 uint32_t word2; 1487 #define lpfc_sli4_sge_offset_SHIFT 0 1488 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1489 #define lpfc_sli4_sge_offset_WORD word2 1490 #define lpfc_sli4_sge_type_SHIFT 27 1491 #define lpfc_sli4_sge_type_MASK 0x0000000F 1492 #define lpfc_sli4_sge_type_WORD word2 1493 #define LPFC_SGE_TYPE_DATA 0x0 1494 #define LPFC_SGE_TYPE_DIF 0x4 1495 #define LPFC_SGE_TYPE_LSP 0x5 1496 #define LPFC_SGE_TYPE_PEDIF 0x6 1497 #define LPFC_SGE_TYPE_PESEED 0x7 1498 #define LPFC_SGE_TYPE_DISEED 0x8 1499 #define LPFC_SGE_TYPE_ENC 0x9 1500 #define LPFC_SGE_TYPE_ATM 0xA 1501 #define LPFC_SGE_TYPE_SKIP 0xC 1502 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1503 #define lpfc_sli4_sge_last_MASK 0x00000001 1504 #define lpfc_sli4_sge_last_WORD word2 1505 uint32_t sge_len; 1506 }; 1507 1508 struct sli4_sge_diseed { /* SLI-4 */ 1509 uint32_t ref_tag; 1510 uint32_t ref_tag_tran; 1511 1512 uint32_t word2; 1513 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 1514 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 1515 #define lpfc_sli4_sge_dif_apptran_WORD word2 1516 #define lpfc_sli4_sge_dif_af_SHIFT 24 1517 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 1518 #define lpfc_sli4_sge_dif_af_WORD word2 1519 #define lpfc_sli4_sge_dif_na_SHIFT 25 1520 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 1521 #define lpfc_sli4_sge_dif_na_WORD word2 1522 #define lpfc_sli4_sge_dif_hi_SHIFT 26 1523 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 1524 #define lpfc_sli4_sge_dif_hi_WORD word2 1525 #define lpfc_sli4_sge_dif_type_SHIFT 27 1526 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 1527 #define lpfc_sli4_sge_dif_type_WORD word2 1528 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1529 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 1530 #define lpfc_sli4_sge_dif_last_WORD word2 1531 uint32_t word3; 1532 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 1533 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 1534 #define lpfc_sli4_sge_dif_apptag_WORD word3 1535 #define lpfc_sli4_sge_dif_bs_SHIFT 16 1536 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 1537 #define lpfc_sli4_sge_dif_bs_WORD word3 1538 #define lpfc_sli4_sge_dif_ai_SHIFT 19 1539 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 1540 #define lpfc_sli4_sge_dif_ai_WORD word3 1541 #define lpfc_sli4_sge_dif_me_SHIFT 20 1542 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 1543 #define lpfc_sli4_sge_dif_me_WORD word3 1544 #define lpfc_sli4_sge_dif_re_SHIFT 21 1545 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 1546 #define lpfc_sli4_sge_dif_re_WORD word3 1547 #define lpfc_sli4_sge_dif_ce_SHIFT 22 1548 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 1549 #define lpfc_sli4_sge_dif_ce_WORD word3 1550 #define lpfc_sli4_sge_dif_nr_SHIFT 23 1551 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 1552 #define lpfc_sli4_sge_dif_nr_WORD word3 1553 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 1554 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 1555 #define lpfc_sli4_sge_dif_oprx_WORD word3 1556 #define lpfc_sli4_sge_dif_optx_SHIFT 28 1557 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 1558 #define lpfc_sli4_sge_dif_optx_WORD word3 1559 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 1560 }; 1561 1562 struct fcf_record { 1563 uint32_t max_rcv_size; 1564 uint32_t fka_adv_period; 1565 uint32_t fip_priority; 1566 uint32_t word3; 1567 #define lpfc_fcf_record_mac_0_SHIFT 0 1568 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1569 #define lpfc_fcf_record_mac_0_WORD word3 1570 #define lpfc_fcf_record_mac_1_SHIFT 8 1571 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1572 #define lpfc_fcf_record_mac_1_WORD word3 1573 #define lpfc_fcf_record_mac_2_SHIFT 16 1574 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1575 #define lpfc_fcf_record_mac_2_WORD word3 1576 #define lpfc_fcf_record_mac_3_SHIFT 24 1577 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1578 #define lpfc_fcf_record_mac_3_WORD word3 1579 uint32_t word4; 1580 #define lpfc_fcf_record_mac_4_SHIFT 0 1581 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1582 #define lpfc_fcf_record_mac_4_WORD word4 1583 #define lpfc_fcf_record_mac_5_SHIFT 8 1584 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1585 #define lpfc_fcf_record_mac_5_WORD word4 1586 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1587 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1588 #define lpfc_fcf_record_fcf_avail_WORD word4 1589 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1590 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1591 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1592 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1593 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1594 uint32_t word5; 1595 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1596 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1597 #define lpfc_fcf_record_fab_name_0_WORD word5 1598 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1599 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1600 #define lpfc_fcf_record_fab_name_1_WORD word5 1601 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1602 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1603 #define lpfc_fcf_record_fab_name_2_WORD word5 1604 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1605 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1606 #define lpfc_fcf_record_fab_name_3_WORD word5 1607 uint32_t word6; 1608 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1609 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1610 #define lpfc_fcf_record_fab_name_4_WORD word6 1611 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1612 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1613 #define lpfc_fcf_record_fab_name_5_WORD word6 1614 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1615 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 1616 #define lpfc_fcf_record_fab_name_6_WORD word6 1617 #define lpfc_fcf_record_fab_name_7_SHIFT 24 1618 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 1619 #define lpfc_fcf_record_fab_name_7_WORD word6 1620 uint32_t word7; 1621 #define lpfc_fcf_record_fc_map_0_SHIFT 0 1622 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 1623 #define lpfc_fcf_record_fc_map_0_WORD word7 1624 #define lpfc_fcf_record_fc_map_1_SHIFT 8 1625 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 1626 #define lpfc_fcf_record_fc_map_1_WORD word7 1627 #define lpfc_fcf_record_fc_map_2_SHIFT 16 1628 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 1629 #define lpfc_fcf_record_fc_map_2_WORD word7 1630 #define lpfc_fcf_record_fcf_valid_SHIFT 24 1631 #define lpfc_fcf_record_fcf_valid_MASK 0x000000FF 1632 #define lpfc_fcf_record_fcf_valid_WORD word7 1633 uint32_t word8; 1634 #define lpfc_fcf_record_fcf_index_SHIFT 0 1635 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 1636 #define lpfc_fcf_record_fcf_index_WORD word8 1637 #define lpfc_fcf_record_fcf_state_SHIFT 16 1638 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 1639 #define lpfc_fcf_record_fcf_state_WORD word8 1640 uint8_t vlan_bitmap[512]; 1641 uint32_t word137; 1642 #define lpfc_fcf_record_switch_name_0_SHIFT 0 1643 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 1644 #define lpfc_fcf_record_switch_name_0_WORD word137 1645 #define lpfc_fcf_record_switch_name_1_SHIFT 8 1646 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 1647 #define lpfc_fcf_record_switch_name_1_WORD word137 1648 #define lpfc_fcf_record_switch_name_2_SHIFT 16 1649 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 1650 #define lpfc_fcf_record_switch_name_2_WORD word137 1651 #define lpfc_fcf_record_switch_name_3_SHIFT 24 1652 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 1653 #define lpfc_fcf_record_switch_name_3_WORD word137 1654 uint32_t word138; 1655 #define lpfc_fcf_record_switch_name_4_SHIFT 0 1656 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 1657 #define lpfc_fcf_record_switch_name_4_WORD word138 1658 #define lpfc_fcf_record_switch_name_5_SHIFT 8 1659 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 1660 #define lpfc_fcf_record_switch_name_5_WORD word138 1661 #define lpfc_fcf_record_switch_name_6_SHIFT 16 1662 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 1663 #define lpfc_fcf_record_switch_name_6_WORD word138 1664 #define lpfc_fcf_record_switch_name_7_SHIFT 24 1665 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 1666 #define lpfc_fcf_record_switch_name_7_WORD word138 1667 }; 1668 1669 struct lpfc_mbx_read_fcf_tbl { 1670 union lpfc_sli4_cfg_shdr cfg_shdr; 1671 union { 1672 struct { 1673 uint32_t word10; 1674 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 1675 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 1676 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 1677 } request; 1678 struct { 1679 uint32_t eventag; 1680 } response; 1681 } u; 1682 uint32_t word11; 1683 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 1684 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 1685 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 1686 }; 1687 1688 struct lpfc_mbx_add_fcf_tbl_entry { 1689 union lpfc_sli4_cfg_shdr cfg_shdr; 1690 uint32_t word10; 1691 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 1692 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 1693 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 1694 struct lpfc_mbx_sge fcf_sge; 1695 }; 1696 1697 struct lpfc_mbx_del_fcf_tbl_entry { 1698 struct mbox_header header; 1699 uint32_t word10; 1700 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 1701 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 1702 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 1703 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 1704 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 1705 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 1706 }; 1707 1708 struct lpfc_mbx_redisc_fcf_tbl { 1709 struct mbox_header header; 1710 uint32_t word10; 1711 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 1712 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 1713 #define lpfc_mbx_redisc_fcf_count_WORD word10 1714 uint32_t resvd; 1715 uint32_t word12; 1716 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 1717 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 1718 #define lpfc_mbx_redisc_fcf_index_WORD word12 1719 }; 1720 1721 struct lpfc_mbx_query_fw_cfg { 1722 struct mbox_header header; 1723 uint32_t config_number; 1724 uint32_t asic_rev; 1725 uint32_t phys_port; 1726 uint32_t function_mode; 1727 /* firmware Function Mode */ 1728 #define lpfc_function_mode_toe_SHIFT 0 1729 #define lpfc_function_mode_toe_MASK 0x00000001 1730 #define lpfc_function_mode_toe_WORD function_mode 1731 #define lpfc_function_mode_nic_SHIFT 1 1732 #define lpfc_function_mode_nic_MASK 0x00000001 1733 #define lpfc_function_mode_nic_WORD function_mode 1734 #define lpfc_function_mode_rdma_SHIFT 2 1735 #define lpfc_function_mode_rdma_MASK 0x00000001 1736 #define lpfc_function_mode_rdma_WORD function_mode 1737 #define lpfc_function_mode_vm_SHIFT 3 1738 #define lpfc_function_mode_vm_MASK 0x00000001 1739 #define lpfc_function_mode_vm_WORD function_mode 1740 #define lpfc_function_mode_iscsi_i_SHIFT 4 1741 #define lpfc_function_mode_iscsi_i_MASK 0x00000001 1742 #define lpfc_function_mode_iscsi_i_WORD function_mode 1743 #define lpfc_function_mode_iscsi_t_SHIFT 5 1744 #define lpfc_function_mode_iscsi_t_MASK 0x00000001 1745 #define lpfc_function_mode_iscsi_t_WORD function_mode 1746 #define lpfc_function_mode_fcoe_i_SHIFT 6 1747 #define lpfc_function_mode_fcoe_i_MASK 0x00000001 1748 #define lpfc_function_mode_fcoe_i_WORD function_mode 1749 #define lpfc_function_mode_fcoe_t_SHIFT 7 1750 #define lpfc_function_mode_fcoe_t_MASK 0x00000001 1751 #define lpfc_function_mode_fcoe_t_WORD function_mode 1752 #define lpfc_function_mode_dal_SHIFT 8 1753 #define lpfc_function_mode_dal_MASK 0x00000001 1754 #define lpfc_function_mode_dal_WORD function_mode 1755 #define lpfc_function_mode_lro_SHIFT 9 1756 #define lpfc_function_mode_lro_MASK 0x00000001 1757 #define lpfc_function_mode_lro_WORD function_mode 1758 #define lpfc_function_mode_flex10_SHIFT 10 1759 #define lpfc_function_mode_flex10_MASK 0x00000001 1760 #define lpfc_function_mode_flex10_WORD function_mode 1761 #define lpfc_function_mode_ncsi_SHIFT 11 1762 #define lpfc_function_mode_ncsi_MASK 0x00000001 1763 #define lpfc_function_mode_ncsi_WORD function_mode 1764 }; 1765 1766 /* Status field for embedded SLI_CONFIG mailbox command */ 1767 #define STATUS_SUCCESS 0x0 1768 #define STATUS_FAILED 0x1 1769 #define STATUS_ILLEGAL_REQUEST 0x2 1770 #define STATUS_ILLEGAL_FIELD 0x3 1771 #define STATUS_INSUFFICIENT_BUFFER 0x4 1772 #define STATUS_UNAUTHORIZED_REQUEST 0x5 1773 #define STATUS_FLASHROM_SAVE_FAILED 0x17 1774 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 1775 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 1776 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 1777 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 1778 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 1779 #define STATUS_ASSERT_FAILED 0x1e 1780 #define STATUS_INVALID_SESSION 0x1f 1781 #define STATUS_INVALID_CONNECTION 0x20 1782 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 1783 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 1784 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 1785 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 1786 #define STATUS_FLASHROM_READ_FAILED 0x27 1787 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 1788 #define STATUS_ERROR_ACITMAIN 0x2a 1789 #define STATUS_REBOOT_REQUIRED 0x2c 1790 #define STATUS_FCF_IN_USE 0x3a 1791 #define STATUS_FCF_TABLE_EMPTY 0x43 1792 1793 struct lpfc_mbx_sli4_config { 1794 struct mbox_header header; 1795 }; 1796 1797 struct lpfc_mbx_init_vfi { 1798 uint32_t word1; 1799 #define lpfc_init_vfi_vr_SHIFT 31 1800 #define lpfc_init_vfi_vr_MASK 0x00000001 1801 #define lpfc_init_vfi_vr_WORD word1 1802 #define lpfc_init_vfi_vt_SHIFT 30 1803 #define lpfc_init_vfi_vt_MASK 0x00000001 1804 #define lpfc_init_vfi_vt_WORD word1 1805 #define lpfc_init_vfi_vf_SHIFT 29 1806 #define lpfc_init_vfi_vf_MASK 0x00000001 1807 #define lpfc_init_vfi_vf_WORD word1 1808 #define lpfc_init_vfi_vp_SHIFT 28 1809 #define lpfc_init_vfi_vp_MASK 0x00000001 1810 #define lpfc_init_vfi_vp_WORD word1 1811 #define lpfc_init_vfi_vfi_SHIFT 0 1812 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1813 #define lpfc_init_vfi_vfi_WORD word1 1814 uint32_t word2; 1815 #define lpfc_init_vfi_vpi_SHIFT 16 1816 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 1817 #define lpfc_init_vfi_vpi_WORD word2 1818 #define lpfc_init_vfi_fcfi_SHIFT 0 1819 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1820 #define lpfc_init_vfi_fcfi_WORD word2 1821 uint32_t word3; 1822 #define lpfc_init_vfi_pri_SHIFT 13 1823 #define lpfc_init_vfi_pri_MASK 0x00000007 1824 #define lpfc_init_vfi_pri_WORD word3 1825 #define lpfc_init_vfi_vf_id_SHIFT 1 1826 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 1827 #define lpfc_init_vfi_vf_id_WORD word3 1828 uint32_t word4; 1829 #define lpfc_init_vfi_hop_count_SHIFT 24 1830 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 1831 #define lpfc_init_vfi_hop_count_WORD word4 1832 }; 1833 #define MBX_VFI_IN_USE 0x9F02 1834 1835 1836 struct lpfc_mbx_reg_vfi { 1837 uint32_t word1; 1838 #define lpfc_reg_vfi_vp_SHIFT 28 1839 #define lpfc_reg_vfi_vp_MASK 0x00000001 1840 #define lpfc_reg_vfi_vp_WORD word1 1841 #define lpfc_reg_vfi_vfi_SHIFT 0 1842 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 1843 #define lpfc_reg_vfi_vfi_WORD word1 1844 uint32_t word2; 1845 #define lpfc_reg_vfi_vpi_SHIFT 16 1846 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 1847 #define lpfc_reg_vfi_vpi_WORD word2 1848 #define lpfc_reg_vfi_fcfi_SHIFT 0 1849 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 1850 #define lpfc_reg_vfi_fcfi_WORD word2 1851 uint32_t wwn[2]; 1852 struct ulp_bde64 bde; 1853 uint32_t e_d_tov; 1854 uint32_t r_a_tov; 1855 uint32_t word10; 1856 #define lpfc_reg_vfi_nport_id_SHIFT 0 1857 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 1858 #define lpfc_reg_vfi_nport_id_WORD word10 1859 }; 1860 1861 struct lpfc_mbx_init_vpi { 1862 uint32_t word1; 1863 #define lpfc_init_vpi_vfi_SHIFT 16 1864 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 1865 #define lpfc_init_vpi_vfi_WORD word1 1866 #define lpfc_init_vpi_vpi_SHIFT 0 1867 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 1868 #define lpfc_init_vpi_vpi_WORD word1 1869 }; 1870 1871 struct lpfc_mbx_read_vpi { 1872 uint32_t word1_rsvd; 1873 uint32_t word2; 1874 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 1875 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 1876 #define lpfc_mbx_read_vpi_vnportid_WORD word2 1877 uint32_t word3_rsvd; 1878 uint32_t word4; 1879 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 1880 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 1881 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 1882 #define lpfc_mbx_read_vpi_pb_SHIFT 15 1883 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 1884 #define lpfc_mbx_read_vpi_pb_WORD word4 1885 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 1886 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 1887 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 1888 #define lpfc_mbx_read_vpi_ns_SHIFT 30 1889 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 1890 #define lpfc_mbx_read_vpi_ns_WORD word4 1891 #define lpfc_mbx_read_vpi_hl_SHIFT 31 1892 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 1893 #define lpfc_mbx_read_vpi_hl_WORD word4 1894 uint32_t word5_rsvd; 1895 uint32_t word6; 1896 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 1897 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 1898 #define lpfc_mbx_read_vpi_vpi_WORD word6 1899 uint32_t word7; 1900 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 1901 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 1902 #define lpfc_mbx_read_vpi_mac_0_WORD word7 1903 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 1904 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 1905 #define lpfc_mbx_read_vpi_mac_1_WORD word7 1906 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 1907 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 1908 #define lpfc_mbx_read_vpi_mac_2_WORD word7 1909 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 1910 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 1911 #define lpfc_mbx_read_vpi_mac_3_WORD word7 1912 uint32_t word8; 1913 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 1914 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 1915 #define lpfc_mbx_read_vpi_mac_4_WORD word8 1916 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 1917 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 1918 #define lpfc_mbx_read_vpi_mac_5_WORD word8 1919 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 1920 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 1921 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 1922 #define lpfc_mbx_read_vpi_vv_SHIFT 28 1923 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 1924 #define lpfc_mbx_read_vpi_vv_WORD word8 1925 }; 1926 1927 struct lpfc_mbx_unreg_vfi { 1928 uint32_t word1_rsvd; 1929 uint32_t word2; 1930 #define lpfc_unreg_vfi_vfi_SHIFT 0 1931 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 1932 #define lpfc_unreg_vfi_vfi_WORD word2 1933 }; 1934 1935 struct lpfc_mbx_resume_rpi { 1936 uint32_t word1; 1937 #define lpfc_resume_rpi_index_SHIFT 0 1938 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 1939 #define lpfc_resume_rpi_index_WORD word1 1940 #define lpfc_resume_rpi_ii_SHIFT 30 1941 #define lpfc_resume_rpi_ii_MASK 0x00000003 1942 #define lpfc_resume_rpi_ii_WORD word1 1943 #define RESUME_INDEX_RPI 0 1944 #define RESUME_INDEX_VPI 1 1945 #define RESUME_INDEX_VFI 2 1946 #define RESUME_INDEX_FCFI 3 1947 uint32_t event_tag; 1948 }; 1949 1950 #define REG_FCF_INVALID_QID 0xFFFF 1951 struct lpfc_mbx_reg_fcfi { 1952 uint32_t word1; 1953 #define lpfc_reg_fcfi_info_index_SHIFT 0 1954 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 1955 #define lpfc_reg_fcfi_info_index_WORD word1 1956 #define lpfc_reg_fcfi_fcfi_SHIFT 16 1957 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 1958 #define lpfc_reg_fcfi_fcfi_WORD word1 1959 uint32_t word2; 1960 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 1961 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 1962 #define lpfc_reg_fcfi_rq_id1_WORD word2 1963 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 1964 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 1965 #define lpfc_reg_fcfi_rq_id0_WORD word2 1966 uint32_t word3; 1967 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 1968 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 1969 #define lpfc_reg_fcfi_rq_id3_WORD word3 1970 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 1971 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 1972 #define lpfc_reg_fcfi_rq_id2_WORD word3 1973 uint32_t word4; 1974 #define lpfc_reg_fcfi_type_match0_SHIFT 24 1975 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 1976 #define lpfc_reg_fcfi_type_match0_WORD word4 1977 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 1978 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 1979 #define lpfc_reg_fcfi_type_mask0_WORD word4 1980 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 1981 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 1982 #define lpfc_reg_fcfi_rctl_match0_WORD word4 1983 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 1984 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 1985 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 1986 uint32_t word5; 1987 #define lpfc_reg_fcfi_type_match1_SHIFT 24 1988 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 1989 #define lpfc_reg_fcfi_type_match1_WORD word5 1990 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 1991 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 1992 #define lpfc_reg_fcfi_type_mask1_WORD word5 1993 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 1994 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 1995 #define lpfc_reg_fcfi_rctl_match1_WORD word5 1996 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 1997 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 1998 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 1999 uint32_t word6; 2000 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2001 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2002 #define lpfc_reg_fcfi_type_match2_WORD word6 2003 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2004 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2005 #define lpfc_reg_fcfi_type_mask2_WORD word6 2006 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2007 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2008 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2009 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2010 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2011 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2012 uint32_t word7; 2013 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2014 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2015 #define lpfc_reg_fcfi_type_match3_WORD word7 2016 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2017 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2018 #define lpfc_reg_fcfi_type_mask3_WORD word7 2019 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2020 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2021 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2022 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2023 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2024 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2025 uint32_t word8; 2026 #define lpfc_reg_fcfi_mam_SHIFT 13 2027 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2028 #define lpfc_reg_fcfi_mam_WORD word8 2029 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2030 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2031 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2032 #define lpfc_reg_fcfi_vv_SHIFT 12 2033 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2034 #define lpfc_reg_fcfi_vv_WORD word8 2035 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2036 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2037 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2038 }; 2039 2040 struct lpfc_mbx_unreg_fcfi { 2041 uint32_t word1_rsv; 2042 uint32_t word2; 2043 #define lpfc_unreg_fcfi_SHIFT 0 2044 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2045 #define lpfc_unreg_fcfi_WORD word2 2046 }; 2047 2048 struct lpfc_mbx_read_rev { 2049 uint32_t word1; 2050 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2051 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2052 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2053 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2054 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2055 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2056 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2057 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2058 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2059 #define LPFC_PREDCBX_CEE_MODE 0 2060 #define LPFC_DCBX_CEE_MODE 1 2061 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2062 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2063 #define lpfc_mbx_rd_rev_vpd_WORD word1 2064 uint32_t first_hw_rev; 2065 uint32_t second_hw_rev; 2066 uint32_t word4_rsvd; 2067 uint32_t third_hw_rev; 2068 uint32_t word6; 2069 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2070 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2071 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2072 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2073 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2074 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2075 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2076 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2077 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2078 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2079 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2080 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2081 uint32_t word7_rsvd; 2082 uint32_t fw_id_rev; 2083 uint8_t fw_name[16]; 2084 uint32_t ulp_fw_id_rev; 2085 uint8_t ulp_fw_name[16]; 2086 uint32_t word18_47_rsvd[30]; 2087 uint32_t word48; 2088 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2089 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2090 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2091 uint32_t vpd_paddr_low; 2092 uint32_t vpd_paddr_high; 2093 uint32_t avail_vpd_len; 2094 uint32_t rsvd_52_63[12]; 2095 }; 2096 2097 struct lpfc_mbx_read_config { 2098 uint32_t word1; 2099 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2100 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2101 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2102 uint32_t word2; 2103 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2104 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2105 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2106 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2107 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2108 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2109 #define LPFC_LNK_TYPE_GE 0 2110 #define LPFC_LNK_TYPE_FC 1 2111 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2112 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2113 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2114 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2115 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2116 #define lpfc_mbx_rd_conf_topology_WORD word2 2117 uint32_t rsvd_3; 2118 uint32_t word4; 2119 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2120 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2121 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2122 uint32_t rsvd_5; 2123 uint32_t word6; 2124 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2125 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2126 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2127 uint32_t rsvd_7; 2128 uint32_t rsvd_8; 2129 uint32_t word9; 2130 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2131 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2132 #define lpfc_mbx_rd_conf_lmt_WORD word9 2133 uint32_t rsvd_10; 2134 uint32_t rsvd_11; 2135 uint32_t word12; 2136 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2137 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2138 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2139 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2140 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2141 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2142 uint32_t word13; 2143 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2144 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2145 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2146 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2147 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2148 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2149 uint32_t word14; 2150 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2151 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2152 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2153 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2154 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2155 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2156 uint32_t word15; 2157 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2158 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2159 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2160 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2161 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2162 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2163 uint32_t word16; 2164 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2165 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2166 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2167 uint32_t word17; 2168 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2169 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2170 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2171 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2172 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2173 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2174 uint32_t word18; 2175 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2176 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2177 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2178 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2179 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2180 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2181 }; 2182 2183 struct lpfc_mbx_request_features { 2184 uint32_t word1; 2185 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2186 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2187 #define lpfc_mbx_rq_ftr_qry_WORD word1 2188 uint32_t word2; 2189 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2190 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2191 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2192 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2193 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2194 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2195 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2196 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2197 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2198 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2199 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2200 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2201 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2202 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2203 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2204 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2205 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2206 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2207 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2208 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2209 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2210 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2211 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2212 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2213 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2214 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2215 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2216 uint32_t word3; 2217 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2218 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2219 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2220 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2221 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2222 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2223 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2224 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2225 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2226 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2227 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2228 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2229 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2230 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2231 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2232 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2233 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2234 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2235 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2236 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2237 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2238 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2239 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2240 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2241 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2242 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2243 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2244 }; 2245 2246 struct lpfc_mbx_supp_pages { 2247 uint32_t word1; 2248 #define qs_SHIFT 0 2249 #define qs_MASK 0x00000001 2250 #define qs_WORD word1 2251 #define wr_SHIFT 1 2252 #define wr_MASK 0x00000001 2253 #define wr_WORD word1 2254 #define pf_SHIFT 8 2255 #define pf_MASK 0x000000ff 2256 #define pf_WORD word1 2257 #define cpn_SHIFT 16 2258 #define cpn_MASK 0x000000ff 2259 #define cpn_WORD word1 2260 uint32_t word2; 2261 #define list_offset_SHIFT 0 2262 #define list_offset_MASK 0x000000ff 2263 #define list_offset_WORD word2 2264 #define next_offset_SHIFT 8 2265 #define next_offset_MASK 0x000000ff 2266 #define next_offset_WORD word2 2267 #define elem_cnt_SHIFT 16 2268 #define elem_cnt_MASK 0x000000ff 2269 #define elem_cnt_WORD word2 2270 uint32_t word3; 2271 #define pn_0_SHIFT 24 2272 #define pn_0_MASK 0x000000ff 2273 #define pn_0_WORD word3 2274 #define pn_1_SHIFT 16 2275 #define pn_1_MASK 0x000000ff 2276 #define pn_1_WORD word3 2277 #define pn_2_SHIFT 8 2278 #define pn_2_MASK 0x000000ff 2279 #define pn_2_WORD word3 2280 #define pn_3_SHIFT 0 2281 #define pn_3_MASK 0x000000ff 2282 #define pn_3_WORD word3 2283 uint32_t word4; 2284 #define pn_4_SHIFT 24 2285 #define pn_4_MASK 0x000000ff 2286 #define pn_4_WORD word4 2287 #define pn_5_SHIFT 16 2288 #define pn_5_MASK 0x000000ff 2289 #define pn_5_WORD word4 2290 #define pn_6_SHIFT 8 2291 #define pn_6_MASK 0x000000ff 2292 #define pn_6_WORD word4 2293 #define pn_7_SHIFT 0 2294 #define pn_7_MASK 0x000000ff 2295 #define pn_7_WORD word4 2296 uint32_t rsvd[27]; 2297 #define LPFC_SUPP_PAGES 0 2298 #define LPFC_BLOCK_GUARD_PROFILES 1 2299 #define LPFC_SLI4_PARAMETERS 2 2300 }; 2301 2302 struct lpfc_mbx_pc_sli4_params { 2303 uint32_t word1; 2304 #define qs_SHIFT 0 2305 #define qs_MASK 0x00000001 2306 #define qs_WORD word1 2307 #define wr_SHIFT 1 2308 #define wr_MASK 0x00000001 2309 #define wr_WORD word1 2310 #define pf_SHIFT 8 2311 #define pf_MASK 0x000000ff 2312 #define pf_WORD word1 2313 #define cpn_SHIFT 16 2314 #define cpn_MASK 0x000000ff 2315 #define cpn_WORD word1 2316 uint32_t word2; 2317 #define if_type_SHIFT 0 2318 #define if_type_MASK 0x00000007 2319 #define if_type_WORD word2 2320 #define sli_rev_SHIFT 4 2321 #define sli_rev_MASK 0x0000000f 2322 #define sli_rev_WORD word2 2323 #define sli_family_SHIFT 8 2324 #define sli_family_MASK 0x000000ff 2325 #define sli_family_WORD word2 2326 #define featurelevel_1_SHIFT 16 2327 #define featurelevel_1_MASK 0x000000ff 2328 #define featurelevel_1_WORD word2 2329 #define featurelevel_2_SHIFT 24 2330 #define featurelevel_2_MASK 0x0000001f 2331 #define featurelevel_2_WORD word2 2332 uint32_t word3; 2333 #define fcoe_SHIFT 0 2334 #define fcoe_MASK 0x00000001 2335 #define fcoe_WORD word3 2336 #define fc_SHIFT 1 2337 #define fc_MASK 0x00000001 2338 #define fc_WORD word3 2339 #define nic_SHIFT 2 2340 #define nic_MASK 0x00000001 2341 #define nic_WORD word3 2342 #define iscsi_SHIFT 3 2343 #define iscsi_MASK 0x00000001 2344 #define iscsi_WORD word3 2345 #define rdma_SHIFT 4 2346 #define rdma_MASK 0x00000001 2347 #define rdma_WORD word3 2348 uint32_t sge_supp_len; 2349 #define SLI4_PAGE_SIZE 4096 2350 uint32_t word5; 2351 #define if_page_sz_SHIFT 0 2352 #define if_page_sz_MASK 0x0000ffff 2353 #define if_page_sz_WORD word5 2354 #define loopbk_scope_SHIFT 24 2355 #define loopbk_scope_MASK 0x0000000f 2356 #define loopbk_scope_WORD word5 2357 #define rq_db_window_SHIFT 28 2358 #define rq_db_window_MASK 0x0000000f 2359 #define rq_db_window_WORD word5 2360 uint32_t word6; 2361 #define eq_pages_SHIFT 0 2362 #define eq_pages_MASK 0x0000000f 2363 #define eq_pages_WORD word6 2364 #define eqe_size_SHIFT 8 2365 #define eqe_size_MASK 0x000000ff 2366 #define eqe_size_WORD word6 2367 uint32_t word7; 2368 #define cq_pages_SHIFT 0 2369 #define cq_pages_MASK 0x0000000f 2370 #define cq_pages_WORD word7 2371 #define cqe_size_SHIFT 8 2372 #define cqe_size_MASK 0x000000ff 2373 #define cqe_size_WORD word7 2374 uint32_t word8; 2375 #define mq_pages_SHIFT 0 2376 #define mq_pages_MASK 0x0000000f 2377 #define mq_pages_WORD word8 2378 #define mqe_size_SHIFT 8 2379 #define mqe_size_MASK 0x000000ff 2380 #define mqe_size_WORD word8 2381 #define mq_elem_cnt_SHIFT 16 2382 #define mq_elem_cnt_MASK 0x000000ff 2383 #define mq_elem_cnt_WORD word8 2384 uint32_t word9; 2385 #define wq_pages_SHIFT 0 2386 #define wq_pages_MASK 0x0000ffff 2387 #define wq_pages_WORD word9 2388 #define wqe_size_SHIFT 8 2389 #define wqe_size_MASK 0x000000ff 2390 #define wqe_size_WORD word9 2391 uint32_t word10; 2392 #define rq_pages_SHIFT 0 2393 #define rq_pages_MASK 0x0000ffff 2394 #define rq_pages_WORD word10 2395 #define rqe_size_SHIFT 8 2396 #define rqe_size_MASK 0x000000ff 2397 #define rqe_size_WORD word10 2398 uint32_t word11; 2399 #define hdr_pages_SHIFT 0 2400 #define hdr_pages_MASK 0x0000000f 2401 #define hdr_pages_WORD word11 2402 #define hdr_size_SHIFT 8 2403 #define hdr_size_MASK 0x0000000f 2404 #define hdr_size_WORD word11 2405 #define hdr_pp_align_SHIFT 16 2406 #define hdr_pp_align_MASK 0x0000ffff 2407 #define hdr_pp_align_WORD word11 2408 uint32_t word12; 2409 #define sgl_pages_SHIFT 0 2410 #define sgl_pages_MASK 0x0000000f 2411 #define sgl_pages_WORD word12 2412 #define sgl_pp_align_SHIFT 16 2413 #define sgl_pp_align_MASK 0x0000ffff 2414 #define sgl_pp_align_WORD word12 2415 uint32_t rsvd_13_63[51]; 2416 }; 2417 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 2418 &(~((SLI4_PAGE_SIZE)-1))) 2419 2420 struct lpfc_sli4_parameters { 2421 uint32_t word0; 2422 #define cfg_prot_type_SHIFT 0 2423 #define cfg_prot_type_MASK 0x000000FF 2424 #define cfg_prot_type_WORD word0 2425 uint32_t word1; 2426 #define cfg_ft_SHIFT 0 2427 #define cfg_ft_MASK 0x00000001 2428 #define cfg_ft_WORD word1 2429 #define cfg_sli_rev_SHIFT 4 2430 #define cfg_sli_rev_MASK 0x0000000f 2431 #define cfg_sli_rev_WORD word1 2432 #define cfg_sli_family_SHIFT 8 2433 #define cfg_sli_family_MASK 0x0000000f 2434 #define cfg_sli_family_WORD word1 2435 #define cfg_if_type_SHIFT 12 2436 #define cfg_if_type_MASK 0x0000000f 2437 #define cfg_if_type_WORD word1 2438 #define cfg_sli_hint_1_SHIFT 16 2439 #define cfg_sli_hint_1_MASK 0x000000ff 2440 #define cfg_sli_hint_1_WORD word1 2441 #define cfg_sli_hint_2_SHIFT 24 2442 #define cfg_sli_hint_2_MASK 0x0000001f 2443 #define cfg_sli_hint_2_WORD word1 2444 uint32_t word2; 2445 uint32_t word3; 2446 uint32_t word4; 2447 #define cfg_cqv_SHIFT 14 2448 #define cfg_cqv_MASK 0x00000003 2449 #define cfg_cqv_WORD word4 2450 uint32_t word5; 2451 uint32_t word6; 2452 #define cfg_mqv_SHIFT 14 2453 #define cfg_mqv_MASK 0x00000003 2454 #define cfg_mqv_WORD word6 2455 uint32_t word7; 2456 uint32_t word8; 2457 #define cfg_wqv_SHIFT 14 2458 #define cfg_wqv_MASK 0x00000003 2459 #define cfg_wqv_WORD word8 2460 uint32_t word9; 2461 uint32_t word10; 2462 #define cfg_rqv_SHIFT 14 2463 #define cfg_rqv_MASK 0x00000003 2464 #define cfg_rqv_WORD word10 2465 uint32_t word11; 2466 #define cfg_rq_db_window_SHIFT 28 2467 #define cfg_rq_db_window_MASK 0x0000000f 2468 #define cfg_rq_db_window_WORD word11 2469 uint32_t word12; 2470 #define cfg_fcoe_SHIFT 0 2471 #define cfg_fcoe_MASK 0x00000001 2472 #define cfg_fcoe_WORD word12 2473 #define cfg_ext_SHIFT 1 2474 #define cfg_ext_MASK 0x00000001 2475 #define cfg_ext_WORD word12 2476 #define cfg_hdrr_SHIFT 2 2477 #define cfg_hdrr_MASK 0x00000001 2478 #define cfg_hdrr_WORD word12 2479 #define cfg_phwq_SHIFT 15 2480 #define cfg_phwq_MASK 0x00000001 2481 #define cfg_phwq_WORD word12 2482 #define cfg_loopbk_scope_SHIFT 28 2483 #define cfg_loopbk_scope_MASK 0x0000000f 2484 #define cfg_loopbk_scope_WORD word12 2485 uint32_t sge_supp_len; 2486 uint32_t word14; 2487 #define cfg_sgl_page_cnt_SHIFT 0 2488 #define cfg_sgl_page_cnt_MASK 0x0000000f 2489 #define cfg_sgl_page_cnt_WORD word14 2490 #define cfg_sgl_page_size_SHIFT 8 2491 #define cfg_sgl_page_size_MASK 0x000000ff 2492 #define cfg_sgl_page_size_WORD word14 2493 #define cfg_sgl_pp_align_SHIFT 16 2494 #define cfg_sgl_pp_align_MASK 0x000000ff 2495 #define cfg_sgl_pp_align_WORD word14 2496 uint32_t word15; 2497 uint32_t word16; 2498 uint32_t word17; 2499 uint32_t word18; 2500 uint32_t word19; 2501 }; 2502 2503 struct lpfc_mbx_get_sli4_parameters { 2504 struct mbox_header header; 2505 struct lpfc_sli4_parameters sli4_parameters; 2506 }; 2507 2508 struct lpfc_rscr_desc_generic { 2509 #define LPFC_RSRC_DESC_WSIZE 18 2510 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 2511 }; 2512 2513 struct lpfc_rsrc_desc_pcie { 2514 uint32_t word0; 2515 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 2516 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 2517 #define lpfc_rsrc_desc_pcie_type_WORD word0 2518 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 2519 uint32_t word1; 2520 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 2521 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 2522 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 2523 uint32_t reserved; 2524 uint32_t word3; 2525 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 2526 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 2527 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 2528 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 2529 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 2530 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 2531 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 2532 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 2533 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 2534 uint32_t word4; 2535 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 2536 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 2537 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 2538 }; 2539 2540 struct lpfc_rsrc_desc_fcfcoe { 2541 uint32_t word0; 2542 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 2543 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 2544 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 2545 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 2546 uint32_t word1; 2547 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 2548 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 2549 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 2550 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 2551 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 2552 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 2553 uint32_t word2; 2554 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 2555 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 2556 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 2557 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 2558 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 2559 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 2560 uint32_t word3; 2561 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 2562 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 2563 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 2564 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 2565 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 2566 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 2567 uint32_t word4; 2568 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 2569 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 2570 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 2571 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 2572 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 2573 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 2574 uint32_t word5; 2575 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 2576 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 2577 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 2578 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 2579 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 2580 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 2581 uint32_t word6; 2582 uint32_t word7; 2583 uint32_t word8; 2584 uint32_t word9; 2585 uint32_t word10; 2586 uint32_t word11; 2587 uint32_t word12; 2588 uint32_t word13; 2589 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 2590 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 2591 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 2592 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 2593 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 2594 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 2595 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 2596 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 2597 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 2598 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 2599 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 2600 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 2601 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 2602 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 2603 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 2604 }; 2605 2606 struct lpfc_func_cfg { 2607 #define LPFC_RSRC_DESC_MAX_NUM 2 2608 uint32_t rsrc_desc_count; 2609 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2610 }; 2611 2612 struct lpfc_mbx_get_func_cfg { 2613 struct mbox_header header; 2614 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2615 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2616 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2617 struct lpfc_func_cfg func_cfg; 2618 }; 2619 2620 struct lpfc_prof_cfg { 2621 #define LPFC_RSRC_DESC_MAX_NUM 2 2622 uint32_t rsrc_desc_count; 2623 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2624 }; 2625 2626 struct lpfc_mbx_get_prof_cfg { 2627 struct mbox_header header; 2628 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2629 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2630 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2631 union { 2632 struct { 2633 uint32_t word10; 2634 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 2635 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 2636 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 2637 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 2638 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 2639 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 2640 } request; 2641 struct { 2642 struct lpfc_prof_cfg prof_cfg; 2643 } response; 2644 } u; 2645 }; 2646 2647 struct lpfc_controller_attribute { 2648 uint32_t version_string[8]; 2649 uint32_t manufacturer_name[8]; 2650 uint32_t supported_modes; 2651 uint32_t word17; 2652 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 2653 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 2654 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 2655 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 2656 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 2657 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 2658 uint32_t mbx_da_struct_ver; 2659 uint32_t ep_fw_da_struct_ver; 2660 uint32_t ncsi_ver_str[3]; 2661 uint32_t dflt_ext_timeout; 2662 uint32_t model_number[8]; 2663 uint32_t description[16]; 2664 uint32_t serial_number[8]; 2665 uint32_t ip_ver_str[8]; 2666 uint32_t fw_ver_str[8]; 2667 uint32_t bios_ver_str[8]; 2668 uint32_t redboot_ver_str[8]; 2669 uint32_t driver_ver_str[8]; 2670 uint32_t flash_fw_ver_str[8]; 2671 uint32_t functionality; 2672 uint32_t word105; 2673 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 2674 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 2675 #define lpfc_cntl_attr_max_cbd_len_WORD word105 2676 #define lpfc_cntl_attr_asic_rev_SHIFT 16 2677 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 2678 #define lpfc_cntl_attr_asic_rev_WORD word105 2679 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 2680 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 2681 #define lpfc_cntl_attr_gen_guid0_WORD word105 2682 uint32_t gen_guid1_12[3]; 2683 uint32_t word109; 2684 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 2685 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 2686 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 2687 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 2688 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 2689 #define lpfc_cntl_attr_gen_guid15_WORD word109 2690 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 2691 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 2692 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 2693 uint32_t word110; 2694 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 2695 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 2696 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 2697 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 2698 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 2699 #define lpfc_cntl_attr_multi_func_dev_WORD word110 2700 uint32_t word111; 2701 #define lpfc_cntl_attr_cache_valid_SHIFT 0 2702 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 2703 #define lpfc_cntl_attr_cache_valid_WORD word111 2704 #define lpfc_cntl_attr_hba_status_SHIFT 8 2705 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 2706 #define lpfc_cntl_attr_hba_status_WORD word111 2707 #define lpfc_cntl_attr_max_domain_SHIFT 16 2708 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 2709 #define lpfc_cntl_attr_max_domain_WORD word111 2710 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 2711 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 2712 #define lpfc_cntl_attr_lnk_numb_WORD word111 2713 #define lpfc_cntl_attr_lnk_type_SHIFT 30 2714 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 2715 #define lpfc_cntl_attr_lnk_type_WORD word111 2716 uint32_t fw_post_status; 2717 uint32_t hba_mtu[8]; 2718 uint32_t word121; 2719 uint32_t reserved1[3]; 2720 uint32_t word125; 2721 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 2722 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 2723 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 2724 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 2725 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 2726 #define lpfc_cntl_attr_pci_device_id_WORD word125 2727 uint32_t word126; 2728 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 2729 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 2730 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 2731 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 2732 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 2733 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 2734 uint32_t word127; 2735 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 2736 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 2737 #define lpfc_cntl_attr_pci_bus_num_WORD word127 2738 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 2739 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 2740 #define lpfc_cntl_attr_pci_dev_num_WORD word127 2741 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 2742 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 2743 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 2744 #define lpfc_cntl_attr_inf_type_SHIFT 24 2745 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 2746 #define lpfc_cntl_attr_inf_type_WORD word127 2747 uint32_t unique_id[2]; 2748 uint32_t word130; 2749 #define lpfc_cntl_attr_num_netfil_SHIFT 0 2750 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 2751 #define lpfc_cntl_attr_num_netfil_WORD word130 2752 uint32_t reserved2[4]; 2753 }; 2754 2755 struct lpfc_mbx_get_cntl_attributes { 2756 union lpfc_sli4_cfg_shdr cfg_shdr; 2757 struct lpfc_controller_attribute cntl_attr; 2758 }; 2759 2760 struct lpfc_mbx_get_port_name { 2761 struct mbox_header header; 2762 union { 2763 struct { 2764 uint32_t word4; 2765 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 2766 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 2767 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 2768 } request; 2769 struct { 2770 uint32_t word4; 2771 #define lpfc_mbx_get_port_name_name0_SHIFT 0 2772 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 2773 #define lpfc_mbx_get_port_name_name0_WORD word4 2774 #define lpfc_mbx_get_port_name_name1_SHIFT 8 2775 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 2776 #define lpfc_mbx_get_port_name_name1_WORD word4 2777 #define lpfc_mbx_get_port_name_name2_SHIFT 16 2778 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 2779 #define lpfc_mbx_get_port_name_name2_WORD word4 2780 #define lpfc_mbx_get_port_name_name3_SHIFT 24 2781 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 2782 #define lpfc_mbx_get_port_name_name3_WORD word4 2783 #define LPFC_LINK_NUMBER_0 0 2784 #define LPFC_LINK_NUMBER_1 1 2785 #define LPFC_LINK_NUMBER_2 2 2786 #define LPFC_LINK_NUMBER_3 3 2787 } response; 2788 } u; 2789 }; 2790 2791 /* Mailbox Completion Queue Error Messages */ 2792 #define MB_CQE_STATUS_SUCCESS 0x0 2793 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 2794 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 2795 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 2796 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 2797 #define MB_CQE_STATUS_DMA_FAILED 0x5 2798 2799 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8 2800 struct lpfc_mbx_wr_object { 2801 struct mbox_header header; 2802 union { 2803 struct { 2804 uint32_t word4; 2805 #define lpfc_wr_object_eof_SHIFT 31 2806 #define lpfc_wr_object_eof_MASK 0x00000001 2807 #define lpfc_wr_object_eof_WORD word4 2808 #define lpfc_wr_object_write_length_SHIFT 0 2809 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 2810 #define lpfc_wr_object_write_length_WORD word4 2811 uint32_t write_offset; 2812 uint32_t object_name[26]; 2813 uint32_t bde_count; 2814 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 2815 } request; 2816 struct { 2817 uint32_t actual_write_length; 2818 } response; 2819 } u; 2820 }; 2821 2822 /* mailbox queue entry structure */ 2823 struct lpfc_mqe { 2824 uint32_t word0; 2825 #define lpfc_mqe_status_SHIFT 16 2826 #define lpfc_mqe_status_MASK 0x0000FFFF 2827 #define lpfc_mqe_status_WORD word0 2828 #define lpfc_mqe_command_SHIFT 8 2829 #define lpfc_mqe_command_MASK 0x000000FF 2830 #define lpfc_mqe_command_WORD word0 2831 union { 2832 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 2833 /* sli4 mailbox commands */ 2834 struct lpfc_mbx_sli4_config sli4_config; 2835 struct lpfc_mbx_init_vfi init_vfi; 2836 struct lpfc_mbx_reg_vfi reg_vfi; 2837 struct lpfc_mbx_reg_vfi unreg_vfi; 2838 struct lpfc_mbx_init_vpi init_vpi; 2839 struct lpfc_mbx_resume_rpi resume_rpi; 2840 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 2841 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 2842 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 2843 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 2844 struct lpfc_mbx_reg_fcfi reg_fcfi; 2845 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 2846 struct lpfc_mbx_mq_create mq_create; 2847 struct lpfc_mbx_mq_create_ext mq_create_ext; 2848 struct lpfc_mbx_eq_create eq_create; 2849 struct lpfc_mbx_cq_create cq_create; 2850 struct lpfc_mbx_wq_create wq_create; 2851 struct lpfc_mbx_rq_create rq_create; 2852 struct lpfc_mbx_mq_destroy mq_destroy; 2853 struct lpfc_mbx_eq_destroy eq_destroy; 2854 struct lpfc_mbx_cq_destroy cq_destroy; 2855 struct lpfc_mbx_wq_destroy wq_destroy; 2856 struct lpfc_mbx_rq_destroy rq_destroy; 2857 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 2858 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 2859 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 2860 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 2861 struct lpfc_mbx_nembed_cmd nembed_cmd; 2862 struct lpfc_mbx_read_rev read_rev; 2863 struct lpfc_mbx_read_vpi read_vpi; 2864 struct lpfc_mbx_read_config rd_config; 2865 struct lpfc_mbx_request_features req_ftrs; 2866 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 2867 struct lpfc_mbx_query_fw_cfg query_fw_cfg; 2868 struct lpfc_mbx_supp_pages supp_pages; 2869 struct lpfc_mbx_pc_sli4_params sli4_params; 2870 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 2871 struct lpfc_mbx_set_link_diag_state link_diag_state; 2872 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 2873 struct lpfc_mbx_run_link_diag_test link_diag_test; 2874 struct lpfc_mbx_get_func_cfg get_func_cfg; 2875 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 2876 struct lpfc_mbx_wr_object wr_object; 2877 struct lpfc_mbx_get_port_name get_port_name; 2878 struct lpfc_mbx_nop nop; 2879 } un; 2880 }; 2881 2882 struct lpfc_mcqe { 2883 uint32_t word0; 2884 #define lpfc_mcqe_status_SHIFT 0 2885 #define lpfc_mcqe_status_MASK 0x0000FFFF 2886 #define lpfc_mcqe_status_WORD word0 2887 #define lpfc_mcqe_ext_status_SHIFT 16 2888 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 2889 #define lpfc_mcqe_ext_status_WORD word0 2890 uint32_t mcqe_tag0; 2891 uint32_t mcqe_tag1; 2892 uint32_t trailer; 2893 #define lpfc_trailer_valid_SHIFT 31 2894 #define lpfc_trailer_valid_MASK 0x00000001 2895 #define lpfc_trailer_valid_WORD trailer 2896 #define lpfc_trailer_async_SHIFT 30 2897 #define lpfc_trailer_async_MASK 0x00000001 2898 #define lpfc_trailer_async_WORD trailer 2899 #define lpfc_trailer_hpi_SHIFT 29 2900 #define lpfc_trailer_hpi_MASK 0x00000001 2901 #define lpfc_trailer_hpi_WORD trailer 2902 #define lpfc_trailer_completed_SHIFT 28 2903 #define lpfc_trailer_completed_MASK 0x00000001 2904 #define lpfc_trailer_completed_WORD trailer 2905 #define lpfc_trailer_consumed_SHIFT 27 2906 #define lpfc_trailer_consumed_MASK 0x00000001 2907 #define lpfc_trailer_consumed_WORD trailer 2908 #define lpfc_trailer_type_SHIFT 16 2909 #define lpfc_trailer_type_MASK 0x000000FF 2910 #define lpfc_trailer_type_WORD trailer 2911 #define lpfc_trailer_code_SHIFT 8 2912 #define lpfc_trailer_code_MASK 0x000000FF 2913 #define lpfc_trailer_code_WORD trailer 2914 #define LPFC_TRAILER_CODE_LINK 0x1 2915 #define LPFC_TRAILER_CODE_FCOE 0x2 2916 #define LPFC_TRAILER_CODE_DCBX 0x3 2917 #define LPFC_TRAILER_CODE_GRP5 0x5 2918 #define LPFC_TRAILER_CODE_FC 0x10 2919 #define LPFC_TRAILER_CODE_SLI 0x11 2920 }; 2921 2922 struct lpfc_acqe_link { 2923 uint32_t word0; 2924 #define lpfc_acqe_link_speed_SHIFT 24 2925 #define lpfc_acqe_link_speed_MASK 0x000000FF 2926 #define lpfc_acqe_link_speed_WORD word0 2927 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 2928 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 2929 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 2930 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 2931 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 2932 #define lpfc_acqe_link_duplex_SHIFT 16 2933 #define lpfc_acqe_link_duplex_MASK 0x000000FF 2934 #define lpfc_acqe_link_duplex_WORD word0 2935 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 2936 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 2937 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 2938 #define lpfc_acqe_link_status_SHIFT 8 2939 #define lpfc_acqe_link_status_MASK 0x000000FF 2940 #define lpfc_acqe_link_status_WORD word0 2941 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 2942 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 2943 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 2944 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 2945 #define lpfc_acqe_link_type_SHIFT 6 2946 #define lpfc_acqe_link_type_MASK 0x00000003 2947 #define lpfc_acqe_link_type_WORD word0 2948 #define lpfc_acqe_link_number_SHIFT 0 2949 #define lpfc_acqe_link_number_MASK 0x0000003F 2950 #define lpfc_acqe_link_number_WORD word0 2951 uint32_t word1; 2952 #define lpfc_acqe_link_fault_SHIFT 0 2953 #define lpfc_acqe_link_fault_MASK 0x000000FF 2954 #define lpfc_acqe_link_fault_WORD word1 2955 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 2956 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 2957 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 2958 #define lpfc_acqe_logical_link_speed_SHIFT 16 2959 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 2960 #define lpfc_acqe_logical_link_speed_WORD word1 2961 uint32_t event_tag; 2962 uint32_t trailer; 2963 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 2964 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 2965 }; 2966 2967 struct lpfc_acqe_fip { 2968 uint32_t index; 2969 uint32_t word1; 2970 #define lpfc_acqe_fip_fcf_count_SHIFT 0 2971 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 2972 #define lpfc_acqe_fip_fcf_count_WORD word1 2973 #define lpfc_acqe_fip_event_type_SHIFT 16 2974 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 2975 #define lpfc_acqe_fip_event_type_WORD word1 2976 uint32_t event_tag; 2977 uint32_t trailer; 2978 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 2979 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 2980 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 2981 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 2982 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 2983 }; 2984 2985 struct lpfc_acqe_dcbx { 2986 uint32_t tlv_ttl; 2987 uint32_t reserved; 2988 uint32_t event_tag; 2989 uint32_t trailer; 2990 }; 2991 2992 struct lpfc_acqe_grp5 { 2993 uint32_t word0; 2994 #define lpfc_acqe_grp5_type_SHIFT 6 2995 #define lpfc_acqe_grp5_type_MASK 0x00000003 2996 #define lpfc_acqe_grp5_type_WORD word0 2997 #define lpfc_acqe_grp5_number_SHIFT 0 2998 #define lpfc_acqe_grp5_number_MASK 0x0000003F 2999 #define lpfc_acqe_grp5_number_WORD word0 3000 uint32_t word1; 3001 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3002 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3003 #define lpfc_acqe_grp5_llink_spd_WORD word1 3004 uint32_t event_tag; 3005 uint32_t trailer; 3006 }; 3007 3008 struct lpfc_acqe_fc_la { 3009 uint32_t word0; 3010 #define lpfc_acqe_fc_la_speed_SHIFT 24 3011 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3012 #define lpfc_acqe_fc_la_speed_WORD word0 3013 #define LPFC_FC_LA_SPEED_UNKOWN 0x0 3014 #define LPFC_FC_LA_SPEED_1G 0x1 3015 #define LPFC_FC_LA_SPEED_2G 0x2 3016 #define LPFC_FC_LA_SPEED_4G 0x4 3017 #define LPFC_FC_LA_SPEED_8G 0x8 3018 #define LPFC_FC_LA_SPEED_10G 0xA 3019 #define LPFC_FC_LA_SPEED_16G 0x10 3020 #define lpfc_acqe_fc_la_topology_SHIFT 16 3021 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 3022 #define lpfc_acqe_fc_la_topology_WORD word0 3023 #define LPFC_FC_LA_TOP_UNKOWN 0x0 3024 #define LPFC_FC_LA_TOP_P2P 0x1 3025 #define LPFC_FC_LA_TOP_FCAL 0x2 3026 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 3027 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 3028 #define lpfc_acqe_fc_la_att_type_SHIFT 8 3029 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 3030 #define lpfc_acqe_fc_la_att_type_WORD word0 3031 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 3032 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 3033 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 3034 #define lpfc_acqe_fc_la_port_type_SHIFT 6 3035 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 3036 #define lpfc_acqe_fc_la_port_type_WORD word0 3037 #define LPFC_LINK_TYPE_ETHERNET 0x0 3038 #define LPFC_LINK_TYPE_FC 0x1 3039 #define lpfc_acqe_fc_la_port_number_SHIFT 0 3040 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 3041 #define lpfc_acqe_fc_la_port_number_WORD word0 3042 uint32_t word1; 3043 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 3044 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 3045 #define lpfc_acqe_fc_la_llink_spd_WORD word1 3046 #define lpfc_acqe_fc_la_fault_SHIFT 0 3047 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 3048 #define lpfc_acqe_fc_la_fault_WORD word1 3049 #define LPFC_FC_LA_FAULT_NONE 0x0 3050 #define LPFC_FC_LA_FAULT_LOCAL 0x1 3051 #define LPFC_FC_LA_FAULT_REMOTE 0x2 3052 uint32_t event_tag; 3053 uint32_t trailer; 3054 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 3055 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 3056 }; 3057 3058 struct lpfc_acqe_sli { 3059 uint32_t event_data1; 3060 uint32_t event_data2; 3061 uint32_t reserved; 3062 uint32_t trailer; 3063 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 3064 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 3065 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 3066 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 3067 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 3068 }; 3069 3070 /* 3071 * Define the bootstrap mailbox (bmbx) region used to communicate 3072 * mailbox command between the host and port. The mailbox consists 3073 * of a payload area of 256 bytes and a completion queue of length 3074 * 16 bytes. 3075 */ 3076 struct lpfc_bmbx_create { 3077 struct lpfc_mqe mqe; 3078 struct lpfc_mcqe mcqe; 3079 }; 3080 3081 #define SGL_ALIGN_SZ 64 3082 #define SGL_PAGE_SIZE 4096 3083 /* align SGL addr on a size boundary - adjust address up */ 3084 #define NO_XRI 0xffff 3085 3086 struct wqe_common { 3087 uint32_t word6; 3088 #define wqe_xri_tag_SHIFT 0 3089 #define wqe_xri_tag_MASK 0x0000FFFF 3090 #define wqe_xri_tag_WORD word6 3091 #define wqe_ctxt_tag_SHIFT 16 3092 #define wqe_ctxt_tag_MASK 0x0000FFFF 3093 #define wqe_ctxt_tag_WORD word6 3094 uint32_t word7; 3095 #define wqe_dif_SHIFT 0 3096 #define wqe_dif_MASK 0x00000003 3097 #define wqe_dif_WORD word7 3098 #define wqe_ct_SHIFT 2 3099 #define wqe_ct_MASK 0x00000003 3100 #define wqe_ct_WORD word7 3101 #define wqe_status_SHIFT 4 3102 #define wqe_status_MASK 0x0000000f 3103 #define wqe_status_WORD word7 3104 #define wqe_cmnd_SHIFT 8 3105 #define wqe_cmnd_MASK 0x000000ff 3106 #define wqe_cmnd_WORD word7 3107 #define wqe_class_SHIFT 16 3108 #define wqe_class_MASK 0x00000007 3109 #define wqe_class_WORD word7 3110 #define wqe_ar_SHIFT 19 3111 #define wqe_ar_MASK 0x00000001 3112 #define wqe_ar_WORD word7 3113 #define wqe_ag_SHIFT wqe_ar_SHIFT 3114 #define wqe_ag_MASK wqe_ar_MASK 3115 #define wqe_ag_WORD wqe_ar_WORD 3116 #define wqe_pu_SHIFT 20 3117 #define wqe_pu_MASK 0x00000003 3118 #define wqe_pu_WORD word7 3119 #define wqe_erp_SHIFT 22 3120 #define wqe_erp_MASK 0x00000001 3121 #define wqe_erp_WORD word7 3122 #define wqe_conf_SHIFT wqe_erp_SHIFT 3123 #define wqe_conf_MASK wqe_erp_MASK 3124 #define wqe_conf_WORD wqe_erp_WORD 3125 #define wqe_lnk_SHIFT 23 3126 #define wqe_lnk_MASK 0x00000001 3127 #define wqe_lnk_WORD word7 3128 #define wqe_tmo_SHIFT 24 3129 #define wqe_tmo_MASK 0x000000ff 3130 #define wqe_tmo_WORD word7 3131 uint32_t abort_tag; /* word 8 in WQE */ 3132 uint32_t word9; 3133 #define wqe_reqtag_SHIFT 0 3134 #define wqe_reqtag_MASK 0x0000FFFF 3135 #define wqe_reqtag_WORD word9 3136 #define wqe_temp_rpi_SHIFT 16 3137 #define wqe_temp_rpi_MASK 0x0000FFFF 3138 #define wqe_temp_rpi_WORD word9 3139 #define wqe_rcvoxid_SHIFT 16 3140 #define wqe_rcvoxid_MASK 0x0000FFFF 3141 #define wqe_rcvoxid_WORD word9 3142 uint32_t word10; 3143 #define wqe_ebde_cnt_SHIFT 0 3144 #define wqe_ebde_cnt_MASK 0x0000000f 3145 #define wqe_ebde_cnt_WORD word10 3146 #define wqe_lenloc_SHIFT 7 3147 #define wqe_lenloc_MASK 0x00000003 3148 #define wqe_lenloc_WORD word10 3149 #define LPFC_WQE_LENLOC_NONE 0 3150 #define LPFC_WQE_LENLOC_WORD3 1 3151 #define LPFC_WQE_LENLOC_WORD12 2 3152 #define LPFC_WQE_LENLOC_WORD4 3 3153 #define wqe_qosd_SHIFT 9 3154 #define wqe_qosd_MASK 0x00000001 3155 #define wqe_qosd_WORD word10 3156 #define wqe_xbl_SHIFT 11 3157 #define wqe_xbl_MASK 0x00000001 3158 #define wqe_xbl_WORD word10 3159 #define wqe_iod_SHIFT 13 3160 #define wqe_iod_MASK 0x00000001 3161 #define wqe_iod_WORD word10 3162 #define LPFC_WQE_IOD_WRITE 0 3163 #define LPFC_WQE_IOD_READ 1 3164 #define wqe_dbde_SHIFT 14 3165 #define wqe_dbde_MASK 0x00000001 3166 #define wqe_dbde_WORD word10 3167 #define wqe_wqes_SHIFT 15 3168 #define wqe_wqes_MASK 0x00000001 3169 #define wqe_wqes_WORD word10 3170 /* Note that this field overlaps above fields */ 3171 #define wqe_wqid_SHIFT 1 3172 #define wqe_wqid_MASK 0x00007fff 3173 #define wqe_wqid_WORD word10 3174 #define wqe_pri_SHIFT 16 3175 #define wqe_pri_MASK 0x00000007 3176 #define wqe_pri_WORD word10 3177 #define wqe_pv_SHIFT 19 3178 #define wqe_pv_MASK 0x00000001 3179 #define wqe_pv_WORD word10 3180 #define wqe_xc_SHIFT 21 3181 #define wqe_xc_MASK 0x00000001 3182 #define wqe_xc_WORD word10 3183 #define wqe_sr_SHIFT 22 3184 #define wqe_sr_MASK 0x00000001 3185 #define wqe_sr_WORD word10 3186 #define wqe_ccpe_SHIFT 23 3187 #define wqe_ccpe_MASK 0x00000001 3188 #define wqe_ccpe_WORD word10 3189 #define wqe_ccp_SHIFT 24 3190 #define wqe_ccp_MASK 0x000000ff 3191 #define wqe_ccp_WORD word10 3192 uint32_t word11; 3193 #define wqe_cmd_type_SHIFT 0 3194 #define wqe_cmd_type_MASK 0x0000000f 3195 #define wqe_cmd_type_WORD word11 3196 #define wqe_els_id_SHIFT 4 3197 #define wqe_els_id_MASK 0x00000003 3198 #define wqe_els_id_WORD word11 3199 #define LPFC_ELS_ID_FLOGI 3 3200 #define LPFC_ELS_ID_FDISC 2 3201 #define LPFC_ELS_ID_LOGO 1 3202 #define LPFC_ELS_ID_DEFAULT 0 3203 #define wqe_wqec_SHIFT 7 3204 #define wqe_wqec_MASK 0x00000001 3205 #define wqe_wqec_WORD word11 3206 #define wqe_cqid_SHIFT 16 3207 #define wqe_cqid_MASK 0x0000ffff 3208 #define wqe_cqid_WORD word11 3209 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 3210 }; 3211 3212 struct wqe_did { 3213 uint32_t word5; 3214 #define wqe_els_did_SHIFT 0 3215 #define wqe_els_did_MASK 0x00FFFFFF 3216 #define wqe_els_did_WORD word5 3217 #define wqe_xmit_bls_pt_SHIFT 28 3218 #define wqe_xmit_bls_pt_MASK 0x00000003 3219 #define wqe_xmit_bls_pt_WORD word5 3220 #define wqe_xmit_bls_ar_SHIFT 30 3221 #define wqe_xmit_bls_ar_MASK 0x00000001 3222 #define wqe_xmit_bls_ar_WORD word5 3223 #define wqe_xmit_bls_xo_SHIFT 31 3224 #define wqe_xmit_bls_xo_MASK 0x00000001 3225 #define wqe_xmit_bls_xo_WORD word5 3226 }; 3227 3228 struct lpfc_wqe_generic{ 3229 struct ulp_bde64 bde; 3230 uint32_t word3; 3231 uint32_t word4; 3232 uint32_t word5; 3233 struct wqe_common wqe_com; 3234 uint32_t payload[4]; 3235 }; 3236 3237 struct els_request64_wqe { 3238 struct ulp_bde64 bde; 3239 uint32_t payload_len; 3240 uint32_t word4; 3241 #define els_req64_sid_SHIFT 0 3242 #define els_req64_sid_MASK 0x00FFFFFF 3243 #define els_req64_sid_WORD word4 3244 #define els_req64_sp_SHIFT 24 3245 #define els_req64_sp_MASK 0x00000001 3246 #define els_req64_sp_WORD word4 3247 #define els_req64_vf_SHIFT 25 3248 #define els_req64_vf_MASK 0x00000001 3249 #define els_req64_vf_WORD word4 3250 struct wqe_did wqe_dest; 3251 struct wqe_common wqe_com; /* words 6-11 */ 3252 uint32_t word12; 3253 #define els_req64_vfid_SHIFT 1 3254 #define els_req64_vfid_MASK 0x00000FFF 3255 #define els_req64_vfid_WORD word12 3256 #define els_req64_pri_SHIFT 13 3257 #define els_req64_pri_MASK 0x00000007 3258 #define els_req64_pri_WORD word12 3259 uint32_t word13; 3260 #define els_req64_hopcnt_SHIFT 24 3261 #define els_req64_hopcnt_MASK 0x000000ff 3262 #define els_req64_hopcnt_WORD word13 3263 uint32_t reserved[2]; 3264 }; 3265 3266 struct xmit_els_rsp64_wqe { 3267 struct ulp_bde64 bde; 3268 uint32_t response_payload_len; 3269 uint32_t rsvd4; 3270 struct wqe_did wqe_dest; 3271 struct wqe_common wqe_com; /* words 6-11 */ 3272 uint32_t word12; 3273 #define wqe_rsp_temp_rpi_SHIFT 0 3274 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 3275 #define wqe_rsp_temp_rpi_WORD word12 3276 uint32_t rsvd_13_15[3]; 3277 }; 3278 3279 struct xmit_bls_rsp64_wqe { 3280 uint32_t payload0; 3281 /* Payload0 for BA_ACC */ 3282 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 3283 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 3284 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 3285 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 3286 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 3287 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 3288 /* Payload0 for BA_RJT */ 3289 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 3290 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 3291 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 3292 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 3293 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 3294 #define xmit_bls_rsp64_rjt_expc_WORD payload0 3295 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 3296 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 3297 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 3298 uint32_t word1; 3299 #define xmit_bls_rsp64_rxid_SHIFT 0 3300 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 3301 #define xmit_bls_rsp64_rxid_WORD word1 3302 #define xmit_bls_rsp64_oxid_SHIFT 16 3303 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 3304 #define xmit_bls_rsp64_oxid_WORD word1 3305 uint32_t word2; 3306 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 3307 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 3308 #define xmit_bls_rsp64_seqcnthi_WORD word2 3309 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 3310 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 3311 #define xmit_bls_rsp64_seqcntlo_WORD word2 3312 uint32_t rsrvd3; 3313 uint32_t rsrvd4; 3314 struct wqe_did wqe_dest; 3315 struct wqe_common wqe_com; /* words 6-11 */ 3316 uint32_t rsvd_12_15[4]; 3317 }; 3318 3319 struct wqe_rctl_dfctl { 3320 uint32_t word5; 3321 #define wqe_si_SHIFT 2 3322 #define wqe_si_MASK 0x000000001 3323 #define wqe_si_WORD word5 3324 #define wqe_la_SHIFT 3 3325 #define wqe_la_MASK 0x000000001 3326 #define wqe_la_WORD word5 3327 #define wqe_xo_SHIFT 6 3328 #define wqe_xo_MASK 0x000000001 3329 #define wqe_xo_WORD word5 3330 #define wqe_ls_SHIFT 7 3331 #define wqe_ls_MASK 0x000000001 3332 #define wqe_ls_WORD word5 3333 #define wqe_dfctl_SHIFT 8 3334 #define wqe_dfctl_MASK 0x0000000ff 3335 #define wqe_dfctl_WORD word5 3336 #define wqe_type_SHIFT 16 3337 #define wqe_type_MASK 0x0000000ff 3338 #define wqe_type_WORD word5 3339 #define wqe_rctl_SHIFT 24 3340 #define wqe_rctl_MASK 0x0000000ff 3341 #define wqe_rctl_WORD word5 3342 }; 3343 3344 struct xmit_seq64_wqe { 3345 struct ulp_bde64 bde; 3346 uint32_t rsvd3; 3347 uint32_t relative_offset; 3348 struct wqe_rctl_dfctl wge_ctl; 3349 struct wqe_common wqe_com; /* words 6-11 */ 3350 uint32_t xmit_len; 3351 uint32_t rsvd_12_15[3]; 3352 }; 3353 struct xmit_bcast64_wqe { 3354 struct ulp_bde64 bde; 3355 uint32_t seq_payload_len; 3356 uint32_t rsvd4; 3357 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3358 struct wqe_common wqe_com; /* words 6-11 */ 3359 uint32_t rsvd_12_15[4]; 3360 }; 3361 3362 struct gen_req64_wqe { 3363 struct ulp_bde64 bde; 3364 uint32_t request_payload_len; 3365 uint32_t relative_offset; 3366 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3367 struct wqe_common wqe_com; /* words 6-11 */ 3368 uint32_t rsvd_12_15[4]; 3369 }; 3370 3371 struct create_xri_wqe { 3372 uint32_t rsrvd[5]; /* words 0-4 */ 3373 struct wqe_did wqe_dest; /* word 5 */ 3374 struct wqe_common wqe_com; /* words 6-11 */ 3375 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3376 }; 3377 3378 #define T_REQUEST_TAG 3 3379 #define T_XRI_TAG 1 3380 3381 struct abort_cmd_wqe { 3382 uint32_t rsrvd[3]; 3383 uint32_t word3; 3384 #define abort_cmd_ia_SHIFT 0 3385 #define abort_cmd_ia_MASK 0x000000001 3386 #define abort_cmd_ia_WORD word3 3387 #define abort_cmd_criteria_SHIFT 8 3388 #define abort_cmd_criteria_MASK 0x0000000ff 3389 #define abort_cmd_criteria_WORD word3 3390 uint32_t rsrvd4; 3391 uint32_t rsrvd5; 3392 struct wqe_common wqe_com; /* words 6-11 */ 3393 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3394 }; 3395 3396 struct fcp_iwrite64_wqe { 3397 struct ulp_bde64 bde; 3398 uint32_t payload_offset_len; 3399 uint32_t total_xfer_len; 3400 uint32_t initial_xfer_len; 3401 struct wqe_common wqe_com; /* words 6-11 */ 3402 uint32_t rsrvd12; 3403 struct ulp_bde64 ph_bde; /* words 13-15 */ 3404 }; 3405 3406 struct fcp_iread64_wqe { 3407 struct ulp_bde64 bde; 3408 uint32_t payload_offset_len; /* word 3 */ 3409 uint32_t total_xfer_len; /* word 4 */ 3410 uint32_t rsrvd5; /* word 5 */ 3411 struct wqe_common wqe_com; /* words 6-11 */ 3412 uint32_t rsrvd12; 3413 struct ulp_bde64 ph_bde; /* words 13-15 */ 3414 }; 3415 3416 struct fcp_icmnd64_wqe { 3417 struct ulp_bde64 bde; /* words 0-2 */ 3418 uint32_t rsrvd3; /* word 3 */ 3419 uint32_t rsrvd4; /* word 4 */ 3420 uint32_t rsrvd5; /* word 5 */ 3421 struct wqe_common wqe_com; /* words 6-11 */ 3422 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3423 }; 3424 3425 3426 union lpfc_wqe { 3427 uint32_t words[16]; 3428 struct lpfc_wqe_generic generic; 3429 struct fcp_icmnd64_wqe fcp_icmd; 3430 struct fcp_iread64_wqe fcp_iread; 3431 struct fcp_iwrite64_wqe fcp_iwrite; 3432 struct abort_cmd_wqe abort_cmd; 3433 struct create_xri_wqe create_xri; 3434 struct xmit_bcast64_wqe xmit_bcast64; 3435 struct xmit_seq64_wqe xmit_sequence; 3436 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 3437 struct xmit_els_rsp64_wqe xmit_els_rsp; 3438 struct els_request64_wqe els_req; 3439 struct gen_req64_wqe gen_req; 3440 }; 3441 3442 #define LPFC_GROUP_OJECT_MAGIC_NUM 0xfeaa0001 3443 #define LPFC_FILE_TYPE_GROUP 0xf7 3444 #define LPFC_FILE_ID_GROUP 0xa2 3445 struct lpfc_grp_hdr { 3446 uint32_t size; 3447 uint32_t magic_number; 3448 uint32_t word2; 3449 #define lpfc_grp_hdr_file_type_SHIFT 24 3450 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 3451 #define lpfc_grp_hdr_file_type_WORD word2 3452 #define lpfc_grp_hdr_id_SHIFT 16 3453 #define lpfc_grp_hdr_id_MASK 0x000000FF 3454 #define lpfc_grp_hdr_id_WORD word2 3455 uint8_t rev_name[128]; 3456 uint8_t date[12]; 3457 uint8_t revision[32]; 3458 }; 3459 3460 #define FCP_COMMAND 0x0 3461 #define FCP_COMMAND_DATA_OUT 0x1 3462 #define ELS_COMMAND_NON_FIP 0xC 3463 #define ELS_COMMAND_FIP 0xD 3464 #define OTHER_COMMAND 0x8 3465 3466 #define LPFC_FW_DUMP 1 3467 #define LPFC_FW_RESET 2 3468 #define LPFC_DV_RESET 3 3469