1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2009-2012 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 /* Macros to deal with bit fields. Each bit field must have 3 #defines 22 * associated with it (_SHIFT, _MASK, and _WORD). 23 * EG. For a bit field that is in the 7th bit of the "field4" field of a 24 * structure and is 2 bits in size the following #defines must exist: 25 * struct temp { 26 * uint32_t field1; 27 * uint32_t field2; 28 * uint32_t field3; 29 * uint32_t field4; 30 * #define example_bit_field_SHIFT 7 31 * #define example_bit_field_MASK 0x03 32 * #define example_bit_field_WORD field4 33 * uint32_t field5; 34 * }; 35 * Then the macros below may be used to get or set the value of that field. 36 * EG. To get the value of the bit field from the above example: 37 * struct temp t1; 38 * value = bf_get(example_bit_field, &t1); 39 * And then to set that bit field: 40 * bf_set(example_bit_field, &t1, 2); 41 * Or clear that bit field: 42 * bf_set(example_bit_field, &t1, 0); 43 */ 44 #define bf_get_be32(name, ptr) \ 45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 46 #define bf_get_le32(name, ptr) \ 47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get(name, ptr) \ 49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 50 #define bf_set_le32(name, ptr, value) \ 51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 53 ~(name##_MASK << name##_SHIFT))))) 54 #define bf_set(name, ptr, value) \ 55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 57 58 struct dma_address { 59 uint32_t addr_lo; 60 uint32_t addr_hi; 61 }; 62 63 struct lpfc_sli_intf { 64 uint32_t word0; 65 #define lpfc_sli_intf_valid_SHIFT 29 66 #define lpfc_sli_intf_valid_MASK 0x00000007 67 #define lpfc_sli_intf_valid_WORD word0 68 #define LPFC_SLI_INTF_VALID 6 69 #define lpfc_sli_intf_sli_hint2_SHIFT 24 70 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 71 #define lpfc_sli_intf_sli_hint2_WORD word0 72 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 73 #define lpfc_sli_intf_sli_hint1_SHIFT 16 74 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 75 #define lpfc_sli_intf_sli_hint1_WORD word0 76 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 77 #define LPFC_SLI_INTF_SLI_HINT1_1 1 78 #define LPFC_SLI_INTF_SLI_HINT1_2 2 79 #define lpfc_sli_intf_if_type_SHIFT 12 80 #define lpfc_sli_intf_if_type_MASK 0x0000000F 81 #define lpfc_sli_intf_if_type_WORD word0 82 #define LPFC_SLI_INTF_IF_TYPE_0 0 83 #define LPFC_SLI_INTF_IF_TYPE_1 1 84 #define LPFC_SLI_INTF_IF_TYPE_2 2 85 #define lpfc_sli_intf_sli_family_SHIFT 8 86 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 87 #define lpfc_sli_intf_sli_family_WORD word0 88 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 89 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 92 #define lpfc_sli_intf_slirev_SHIFT 4 93 #define lpfc_sli_intf_slirev_MASK 0x0000000F 94 #define lpfc_sli_intf_slirev_WORD word0 95 #define LPFC_SLI_INTF_REV_SLI3 3 96 #define LPFC_SLI_INTF_REV_SLI4 4 97 #define lpfc_sli_intf_func_type_SHIFT 0 98 #define lpfc_sli_intf_func_type_MASK 0x00000001 99 #define lpfc_sli_intf_func_type_WORD word0 100 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 101 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 102 }; 103 104 #define LPFC_SLI4_MBX_EMBED true 105 #define LPFC_SLI4_MBX_NEMBED false 106 107 #define LPFC_SLI4_MB_WORD_COUNT 64 108 #define LPFC_MAX_MQ_PAGE 8 109 #define LPFC_MAX_WQ_PAGE 8 110 #define LPFC_MAX_CQ_PAGE 4 111 #define LPFC_MAX_EQ_PAGE 8 112 113 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 114 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 115 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 116 117 /* Define SLI4 Alignment requirements. */ 118 #define LPFC_ALIGN_16_BYTE 16 119 #define LPFC_ALIGN_64_BYTE 64 120 121 /* Define SLI4 specific definitions. */ 122 #define LPFC_MQ_CQE_BYTE_OFFSET 256 123 #define LPFC_MBX_CMD_HDR_LENGTH 16 124 #define LPFC_MBX_ERROR_RANGE 0x4000 125 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 126 #define LPFC_BMBX_BIT1_ADDR_LO 0 127 #define LPFC_RPI_HDR_COUNT 64 128 #define LPFC_HDR_TEMPLATE_SIZE 4096 129 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 130 #define LPFC_FCF_RECORD_WD_CNT 132 131 #define LPFC_ENTIRE_FCF_DATABASE 0 132 #define LPFC_DFLT_FCF_INDEX 0 133 134 /* Virtual function numbers */ 135 #define LPFC_VF0 0 136 #define LPFC_VF1 1 137 #define LPFC_VF2 2 138 #define LPFC_VF3 3 139 #define LPFC_VF4 4 140 #define LPFC_VF5 5 141 #define LPFC_VF6 6 142 #define LPFC_VF7 7 143 #define LPFC_VF8 8 144 #define LPFC_VF9 9 145 #define LPFC_VF10 10 146 #define LPFC_VF11 11 147 #define LPFC_VF12 12 148 #define LPFC_VF13 13 149 #define LPFC_VF14 14 150 #define LPFC_VF15 15 151 #define LPFC_VF16 16 152 #define LPFC_VF17 17 153 #define LPFC_VF18 18 154 #define LPFC_VF19 19 155 #define LPFC_VF20 20 156 #define LPFC_VF21 21 157 #define LPFC_VF22 22 158 #define LPFC_VF23 23 159 #define LPFC_VF24 24 160 #define LPFC_VF25 25 161 #define LPFC_VF26 26 162 #define LPFC_VF27 27 163 #define LPFC_VF28 28 164 #define LPFC_VF29 29 165 #define LPFC_VF30 30 166 #define LPFC_VF31 31 167 168 /* PCI function numbers */ 169 #define LPFC_PCI_FUNC0 0 170 #define LPFC_PCI_FUNC1 1 171 #define LPFC_PCI_FUNC2 2 172 #define LPFC_PCI_FUNC3 3 173 #define LPFC_PCI_FUNC4 4 174 175 /* SLI4 interface type-2 PDEV_CTL register */ 176 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 177 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 178 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 179 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 180 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 181 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 182 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 183 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 184 185 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 186 187 /* Active interrupt test count */ 188 #define LPFC_ACT_INTR_CNT 4 189 190 /* Delay Multiplier constant */ 191 #define LPFC_DMULT_CONST 651042 192 #define LPFC_MIM_IMAX 636 193 #define LPFC_FP_DEF_IMAX 10000 194 #define LPFC_SP_DEF_IMAX 10000 195 196 /* PORT_CAPABILITIES constants. */ 197 #define LPFC_MAX_SUPPORTED_PAGES 8 198 199 struct ulp_bde64 { 200 union ULP_BDE_TUS { 201 uint32_t w; 202 struct { 203 #ifdef __BIG_ENDIAN_BITFIELD 204 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 205 VALUE !! */ 206 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 207 #else /* __LITTLE_ENDIAN_BITFIELD */ 208 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 209 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 210 VALUE !! */ 211 #endif 212 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 213 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 214 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 215 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 216 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 217 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 218 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 219 } f; 220 } tus; 221 uint32_t addrLow; 222 uint32_t addrHigh; 223 }; 224 225 struct lpfc_sli4_flags { 226 uint32_t word0; 227 #define lpfc_idx_rsrc_rdy_SHIFT 0 228 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 229 #define lpfc_idx_rsrc_rdy_WORD word0 230 #define LPFC_IDX_RSRC_RDY 1 231 #define lpfc_rpi_rsrc_rdy_SHIFT 1 232 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 233 #define lpfc_rpi_rsrc_rdy_WORD word0 234 #define LPFC_RPI_RSRC_RDY 1 235 #define lpfc_vpi_rsrc_rdy_SHIFT 2 236 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 237 #define lpfc_vpi_rsrc_rdy_WORD word0 238 #define LPFC_VPI_RSRC_RDY 1 239 #define lpfc_vfi_rsrc_rdy_SHIFT 3 240 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 241 #define lpfc_vfi_rsrc_rdy_WORD word0 242 #define LPFC_VFI_RSRC_RDY 1 243 }; 244 245 struct sli4_bls_rsp { 246 uint32_t word0_rsvd; /* Word0 must be reserved */ 247 uint32_t word1; 248 #define lpfc_abts_orig_SHIFT 0 249 #define lpfc_abts_orig_MASK 0x00000001 250 #define lpfc_abts_orig_WORD word1 251 #define LPFC_ABTS_UNSOL_RSP 1 252 #define LPFC_ABTS_UNSOL_INT 0 253 uint32_t word2; 254 #define lpfc_abts_rxid_SHIFT 0 255 #define lpfc_abts_rxid_MASK 0x0000FFFF 256 #define lpfc_abts_rxid_WORD word2 257 #define lpfc_abts_oxid_SHIFT 16 258 #define lpfc_abts_oxid_MASK 0x0000FFFF 259 #define lpfc_abts_oxid_WORD word2 260 uint32_t word3; 261 #define lpfc_vndr_code_SHIFT 0 262 #define lpfc_vndr_code_MASK 0x000000FF 263 #define lpfc_vndr_code_WORD word3 264 #define lpfc_rsn_expln_SHIFT 8 265 #define lpfc_rsn_expln_MASK 0x000000FF 266 #define lpfc_rsn_expln_WORD word3 267 #define lpfc_rsn_code_SHIFT 16 268 #define lpfc_rsn_code_MASK 0x000000FF 269 #define lpfc_rsn_code_WORD word3 270 271 uint32_t word4; 272 uint32_t word5_rsvd; /* Word5 must be reserved */ 273 }; 274 275 /* event queue entry structure */ 276 struct lpfc_eqe { 277 uint32_t word0; 278 #define lpfc_eqe_resource_id_SHIFT 16 279 #define lpfc_eqe_resource_id_MASK 0x000000FF 280 #define lpfc_eqe_resource_id_WORD word0 281 #define lpfc_eqe_minor_code_SHIFT 4 282 #define lpfc_eqe_minor_code_MASK 0x00000FFF 283 #define lpfc_eqe_minor_code_WORD word0 284 #define lpfc_eqe_major_code_SHIFT 1 285 #define lpfc_eqe_major_code_MASK 0x00000007 286 #define lpfc_eqe_major_code_WORD word0 287 #define lpfc_eqe_valid_SHIFT 0 288 #define lpfc_eqe_valid_MASK 0x00000001 289 #define lpfc_eqe_valid_WORD word0 290 }; 291 292 /* completion queue entry structure (common fields for all cqe types) */ 293 struct lpfc_cqe { 294 uint32_t reserved0; 295 uint32_t reserved1; 296 uint32_t reserved2; 297 uint32_t word3; 298 #define lpfc_cqe_valid_SHIFT 31 299 #define lpfc_cqe_valid_MASK 0x00000001 300 #define lpfc_cqe_valid_WORD word3 301 #define lpfc_cqe_code_SHIFT 16 302 #define lpfc_cqe_code_MASK 0x000000FF 303 #define lpfc_cqe_code_WORD word3 304 }; 305 306 /* Completion Queue Entry Status Codes */ 307 #define CQE_STATUS_SUCCESS 0x0 308 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 309 #define CQE_STATUS_REMOTE_STOP 0x2 310 #define CQE_STATUS_LOCAL_REJECT 0x3 311 #define CQE_STATUS_NPORT_RJT 0x4 312 #define CQE_STATUS_FABRIC_RJT 0x5 313 #define CQE_STATUS_NPORT_BSY 0x6 314 #define CQE_STATUS_FABRIC_BSY 0x7 315 #define CQE_STATUS_INTERMED_RSP 0x8 316 #define CQE_STATUS_LS_RJT 0x9 317 #define CQE_STATUS_CMD_REJECT 0xb 318 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 319 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 320 #define CQE_STATUS_DI_ERROR 0x16 321 322 /* Used when mapping CQE status to IOCB */ 323 #define LPFC_IOCB_STATUS_MASK 0xf 324 325 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 326 #define CQE_HW_STATUS_NO_ERR 0x0 327 #define CQE_HW_STATUS_UNDERRUN 0x1 328 #define CQE_HW_STATUS_OVERRUN 0x2 329 330 /* Completion Queue Entry Codes */ 331 #define CQE_CODE_COMPL_WQE 0x1 332 #define CQE_CODE_RELEASE_WQE 0x2 333 #define CQE_CODE_RECEIVE 0x4 334 #define CQE_CODE_XRI_ABORTED 0x5 335 #define CQE_CODE_RECEIVE_V1 0x9 336 337 /* 338 * Define mask value for xri_aborted and wcqe completed CQE extended status. 339 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 340 */ 341 #define WCQE_PARAM_MASK 0x1FF; 342 343 /* completion queue entry for wqe completions */ 344 struct lpfc_wcqe_complete { 345 uint32_t word0; 346 #define lpfc_wcqe_c_request_tag_SHIFT 16 347 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 348 #define lpfc_wcqe_c_request_tag_WORD word0 349 #define lpfc_wcqe_c_status_SHIFT 8 350 #define lpfc_wcqe_c_status_MASK 0x000000FF 351 #define lpfc_wcqe_c_status_WORD word0 352 #define lpfc_wcqe_c_hw_status_SHIFT 0 353 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 354 #define lpfc_wcqe_c_hw_status_WORD word0 355 uint32_t total_data_placed; 356 uint32_t parameter; 357 #define lpfc_wcqe_c_bg_edir_SHIFT 5 358 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 359 #define lpfc_wcqe_c_bg_edir_WORD parameter 360 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 361 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 362 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 363 #define lpfc_wcqe_c_bg_re_SHIFT 2 364 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 365 #define lpfc_wcqe_c_bg_re_WORD parameter 366 #define lpfc_wcqe_c_bg_ae_SHIFT 1 367 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 368 #define lpfc_wcqe_c_bg_ae_WORD parameter 369 #define lpfc_wcqe_c_bg_ge_SHIFT 0 370 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 371 #define lpfc_wcqe_c_bg_ge_WORD parameter 372 uint32_t word3; 373 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 374 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 375 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 376 #define lpfc_wcqe_c_xb_SHIFT 28 377 #define lpfc_wcqe_c_xb_MASK 0x00000001 378 #define lpfc_wcqe_c_xb_WORD word3 379 #define lpfc_wcqe_c_pv_SHIFT 27 380 #define lpfc_wcqe_c_pv_MASK 0x00000001 381 #define lpfc_wcqe_c_pv_WORD word3 382 #define lpfc_wcqe_c_priority_SHIFT 24 383 #define lpfc_wcqe_c_priority_MASK 0x00000007 384 #define lpfc_wcqe_c_priority_WORD word3 385 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 386 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 387 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 388 }; 389 390 /* completion queue entry for wqe release */ 391 struct lpfc_wcqe_release { 392 uint32_t reserved0; 393 uint32_t reserved1; 394 uint32_t word2; 395 #define lpfc_wcqe_r_wq_id_SHIFT 16 396 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 397 #define lpfc_wcqe_r_wq_id_WORD word2 398 #define lpfc_wcqe_r_wqe_index_SHIFT 0 399 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 400 #define lpfc_wcqe_r_wqe_index_WORD word2 401 uint32_t word3; 402 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 403 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 404 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 405 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 406 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 407 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 408 }; 409 410 struct sli4_wcqe_xri_aborted { 411 uint32_t word0; 412 #define lpfc_wcqe_xa_status_SHIFT 8 413 #define lpfc_wcqe_xa_status_MASK 0x000000FF 414 #define lpfc_wcqe_xa_status_WORD word0 415 uint32_t parameter; 416 uint32_t word2; 417 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 418 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 419 #define lpfc_wcqe_xa_remote_xid_WORD word2 420 #define lpfc_wcqe_xa_xri_SHIFT 0 421 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 422 #define lpfc_wcqe_xa_xri_WORD word2 423 uint32_t word3; 424 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 425 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 426 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 427 #define lpfc_wcqe_xa_ia_SHIFT 30 428 #define lpfc_wcqe_xa_ia_MASK 0x00000001 429 #define lpfc_wcqe_xa_ia_WORD word3 430 #define CQE_XRI_ABORTED_IA_REMOTE 0 431 #define CQE_XRI_ABORTED_IA_LOCAL 1 432 #define lpfc_wcqe_xa_br_SHIFT 29 433 #define lpfc_wcqe_xa_br_MASK 0x00000001 434 #define lpfc_wcqe_xa_br_WORD word3 435 #define CQE_XRI_ABORTED_BR_BA_ACC 0 436 #define CQE_XRI_ABORTED_BR_BA_RJT 1 437 #define lpfc_wcqe_xa_eo_SHIFT 28 438 #define lpfc_wcqe_xa_eo_MASK 0x00000001 439 #define lpfc_wcqe_xa_eo_WORD word3 440 #define CQE_XRI_ABORTED_EO_REMOTE 0 441 #define CQE_XRI_ABORTED_EO_LOCAL 1 442 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 443 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 444 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 445 }; 446 447 /* completion queue entry structure for rqe completion */ 448 struct lpfc_rcqe { 449 uint32_t word0; 450 #define lpfc_rcqe_bindex_SHIFT 16 451 #define lpfc_rcqe_bindex_MASK 0x0000FFF 452 #define lpfc_rcqe_bindex_WORD word0 453 #define lpfc_rcqe_status_SHIFT 8 454 #define lpfc_rcqe_status_MASK 0x000000FF 455 #define lpfc_rcqe_status_WORD word0 456 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 457 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 458 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 459 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 460 uint32_t word1; 461 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 462 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 463 #define lpfc_rcqe_fcf_id_v1_WORD word1 464 uint32_t word2; 465 #define lpfc_rcqe_length_SHIFT 16 466 #define lpfc_rcqe_length_MASK 0x0000FFFF 467 #define lpfc_rcqe_length_WORD word2 468 #define lpfc_rcqe_rq_id_SHIFT 6 469 #define lpfc_rcqe_rq_id_MASK 0x000003FF 470 #define lpfc_rcqe_rq_id_WORD word2 471 #define lpfc_rcqe_fcf_id_SHIFT 0 472 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 473 #define lpfc_rcqe_fcf_id_WORD word2 474 #define lpfc_rcqe_rq_id_v1_SHIFT 0 475 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 476 #define lpfc_rcqe_rq_id_v1_WORD word2 477 uint32_t word3; 478 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 479 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 480 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 481 #define lpfc_rcqe_port_SHIFT 30 482 #define lpfc_rcqe_port_MASK 0x00000001 483 #define lpfc_rcqe_port_WORD word3 484 #define lpfc_rcqe_hdr_length_SHIFT 24 485 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 486 #define lpfc_rcqe_hdr_length_WORD word3 487 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 488 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 489 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 490 #define lpfc_rcqe_eof_SHIFT 8 491 #define lpfc_rcqe_eof_MASK 0x000000FF 492 #define lpfc_rcqe_eof_WORD word3 493 #define FCOE_EOFn 0x41 494 #define FCOE_EOFt 0x42 495 #define FCOE_EOFni 0x49 496 #define FCOE_EOFa 0x50 497 #define lpfc_rcqe_sof_SHIFT 0 498 #define lpfc_rcqe_sof_MASK 0x000000FF 499 #define lpfc_rcqe_sof_WORD word3 500 #define FCOE_SOFi2 0x2d 501 #define FCOE_SOFi3 0x2e 502 #define FCOE_SOFn2 0x35 503 #define FCOE_SOFn3 0x36 504 }; 505 506 struct lpfc_rqe { 507 uint32_t address_hi; 508 uint32_t address_lo; 509 }; 510 511 /* buffer descriptors */ 512 struct lpfc_bde4 { 513 uint32_t addr_hi; 514 uint32_t addr_lo; 515 uint32_t word2; 516 #define lpfc_bde4_last_SHIFT 31 517 #define lpfc_bde4_last_MASK 0x00000001 518 #define lpfc_bde4_last_WORD word2 519 #define lpfc_bde4_sge_offset_SHIFT 0 520 #define lpfc_bde4_sge_offset_MASK 0x000003FF 521 #define lpfc_bde4_sge_offset_WORD word2 522 uint32_t word3; 523 #define lpfc_bde4_length_SHIFT 0 524 #define lpfc_bde4_length_MASK 0x000000FF 525 #define lpfc_bde4_length_WORD word3 526 }; 527 528 struct lpfc_register { 529 uint32_t word0; 530 }; 531 532 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 533 #define LPFC_UERR_STATUS_HI 0x00A4 534 #define LPFC_UERR_STATUS_LO 0x00A0 535 #define LPFC_UE_MASK_HI 0x00AC 536 #define LPFC_UE_MASK_LO 0x00A8 537 538 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 539 #define LPFC_SLI_INTF 0x0058 540 541 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 542 #define lpfc_port_smphr_perr_SHIFT 31 543 #define lpfc_port_smphr_perr_MASK 0x1 544 #define lpfc_port_smphr_perr_WORD word0 545 #define lpfc_port_smphr_sfi_SHIFT 30 546 #define lpfc_port_smphr_sfi_MASK 0x1 547 #define lpfc_port_smphr_sfi_WORD word0 548 #define lpfc_port_smphr_nip_SHIFT 29 549 #define lpfc_port_smphr_nip_MASK 0x1 550 #define lpfc_port_smphr_nip_WORD word0 551 #define lpfc_port_smphr_ipc_SHIFT 28 552 #define lpfc_port_smphr_ipc_MASK 0x1 553 #define lpfc_port_smphr_ipc_WORD word0 554 #define lpfc_port_smphr_scr1_SHIFT 27 555 #define lpfc_port_smphr_scr1_MASK 0x1 556 #define lpfc_port_smphr_scr1_WORD word0 557 #define lpfc_port_smphr_scr2_SHIFT 26 558 #define lpfc_port_smphr_scr2_MASK 0x1 559 #define lpfc_port_smphr_scr2_WORD word0 560 #define lpfc_port_smphr_host_scratch_SHIFT 16 561 #define lpfc_port_smphr_host_scratch_MASK 0xFF 562 #define lpfc_port_smphr_host_scratch_WORD word0 563 #define lpfc_port_smphr_port_status_SHIFT 0 564 #define lpfc_port_smphr_port_status_MASK 0xFFFF 565 #define lpfc_port_smphr_port_status_WORD word0 566 567 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 568 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 569 #define LPFC_POST_STAGE_HOST_RDY 0x0002 570 #define LPFC_POST_STAGE_BE_RESET 0x0003 571 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 572 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 573 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 574 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 575 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 576 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 577 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 578 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 579 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 580 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 581 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 582 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 583 #define LPFC_POST_STAGE_ARMFW_START 0x0800 584 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 585 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 586 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 587 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 588 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 589 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 590 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 591 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 592 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 593 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 594 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 595 #define LPFC_POST_STAGE_RC_DONE 0x0B07 596 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 597 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 598 #define LPFC_POST_STAGE_PORT_READY 0xC000 599 #define LPFC_POST_STAGE_PORT_UE 0xF000 600 601 #define LPFC_CTL_PORT_STA_OFFSET 0x404 602 #define lpfc_sliport_status_err_SHIFT 31 603 #define lpfc_sliport_status_err_MASK 0x1 604 #define lpfc_sliport_status_err_WORD word0 605 #define lpfc_sliport_status_end_SHIFT 30 606 #define lpfc_sliport_status_end_MASK 0x1 607 #define lpfc_sliport_status_end_WORD word0 608 #define lpfc_sliport_status_oti_SHIFT 29 609 #define lpfc_sliport_status_oti_MASK 0x1 610 #define lpfc_sliport_status_oti_WORD word0 611 #define lpfc_sliport_status_rn_SHIFT 24 612 #define lpfc_sliport_status_rn_MASK 0x1 613 #define lpfc_sliport_status_rn_WORD word0 614 #define lpfc_sliport_status_rdy_SHIFT 23 615 #define lpfc_sliport_status_rdy_MASK 0x1 616 #define lpfc_sliport_status_rdy_WORD word0 617 #define MAX_IF_TYPE_2_RESETS 1000 618 619 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 620 #define lpfc_sliport_ctrl_end_SHIFT 30 621 #define lpfc_sliport_ctrl_end_MASK 0x1 622 #define lpfc_sliport_ctrl_end_WORD word0 623 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 624 #define LPFC_SLIPORT_BIG_ENDIAN 1 625 #define lpfc_sliport_ctrl_ip_SHIFT 27 626 #define lpfc_sliport_ctrl_ip_MASK 0x1 627 #define lpfc_sliport_ctrl_ip_WORD word0 628 #define LPFC_SLIPORT_INIT_PORT 1 629 630 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 631 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 632 633 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 634 * reside in BAR 2. 635 */ 636 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 637 638 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 639 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 640 641 #define LPFC_HST_ISR0 0x0C18 642 #define LPFC_HST_ISR1 0x0C1C 643 #define LPFC_HST_ISR2 0x0C20 644 #define LPFC_HST_ISR3 0x0C24 645 #define LPFC_HST_ISR4 0x0C28 646 647 #define LPFC_HST_IMR0 0x0C48 648 #define LPFC_HST_IMR1 0x0C4C 649 #define LPFC_HST_IMR2 0x0C50 650 #define LPFC_HST_IMR3 0x0C54 651 #define LPFC_HST_IMR4 0x0C58 652 653 #define LPFC_HST_ISCR0 0x0C78 654 #define LPFC_HST_ISCR1 0x0C7C 655 #define LPFC_HST_ISCR2 0x0C80 656 #define LPFC_HST_ISCR3 0x0C84 657 #define LPFC_HST_ISCR4 0x0C88 658 659 #define LPFC_SLI4_INTR0 BIT0 660 #define LPFC_SLI4_INTR1 BIT1 661 #define LPFC_SLI4_INTR2 BIT2 662 #define LPFC_SLI4_INTR3 BIT3 663 #define LPFC_SLI4_INTR4 BIT4 664 #define LPFC_SLI4_INTR5 BIT5 665 #define LPFC_SLI4_INTR6 BIT6 666 #define LPFC_SLI4_INTR7 BIT7 667 #define LPFC_SLI4_INTR8 BIT8 668 #define LPFC_SLI4_INTR9 BIT9 669 #define LPFC_SLI4_INTR10 BIT10 670 #define LPFC_SLI4_INTR11 BIT11 671 #define LPFC_SLI4_INTR12 BIT12 672 #define LPFC_SLI4_INTR13 BIT13 673 #define LPFC_SLI4_INTR14 BIT14 674 #define LPFC_SLI4_INTR15 BIT15 675 #define LPFC_SLI4_INTR16 BIT16 676 #define LPFC_SLI4_INTR17 BIT17 677 #define LPFC_SLI4_INTR18 BIT18 678 #define LPFC_SLI4_INTR19 BIT19 679 #define LPFC_SLI4_INTR20 BIT20 680 #define LPFC_SLI4_INTR21 BIT21 681 #define LPFC_SLI4_INTR22 BIT22 682 #define LPFC_SLI4_INTR23 BIT23 683 #define LPFC_SLI4_INTR24 BIT24 684 #define LPFC_SLI4_INTR25 BIT25 685 #define LPFC_SLI4_INTR26 BIT26 686 #define LPFC_SLI4_INTR27 BIT27 687 #define LPFC_SLI4_INTR28 BIT28 688 #define LPFC_SLI4_INTR29 BIT29 689 #define LPFC_SLI4_INTR30 BIT30 690 #define LPFC_SLI4_INTR31 BIT31 691 692 /* 693 * The Doorbell registers defined here exist in different BAR 694 * register sets depending on the UCNA Port's reported if_type 695 * value. For UCNA ports running SLI4 and if_type 0, they reside in 696 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 697 * BAR0. The offsets are the same so the driver must account for 698 * any base address difference. 699 */ 700 #define LPFC_RQ_DOORBELL 0x00A0 701 #define lpfc_rq_doorbell_num_posted_SHIFT 16 702 #define lpfc_rq_doorbell_num_posted_MASK 0x3FFF 703 #define lpfc_rq_doorbell_num_posted_WORD word0 704 #define lpfc_rq_doorbell_id_SHIFT 0 705 #define lpfc_rq_doorbell_id_MASK 0xFFFF 706 #define lpfc_rq_doorbell_id_WORD word0 707 708 #define LPFC_WQ_DOORBELL 0x0040 709 #define lpfc_wq_doorbell_num_posted_SHIFT 24 710 #define lpfc_wq_doorbell_num_posted_MASK 0x00FF 711 #define lpfc_wq_doorbell_num_posted_WORD word0 712 #define lpfc_wq_doorbell_index_SHIFT 16 713 #define lpfc_wq_doorbell_index_MASK 0x00FF 714 #define lpfc_wq_doorbell_index_WORD word0 715 #define lpfc_wq_doorbell_id_SHIFT 0 716 #define lpfc_wq_doorbell_id_MASK 0xFFFF 717 #define lpfc_wq_doorbell_id_WORD word0 718 719 #define LPFC_EQCQ_DOORBELL 0x0120 720 #define lpfc_eqcq_doorbell_se_SHIFT 31 721 #define lpfc_eqcq_doorbell_se_MASK 0x0001 722 #define lpfc_eqcq_doorbell_se_WORD word0 723 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 724 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 725 #define lpfc_eqcq_doorbell_arm_SHIFT 29 726 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 727 #define lpfc_eqcq_doorbell_arm_WORD word0 728 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 729 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 730 #define lpfc_eqcq_doorbell_num_released_WORD word0 731 #define lpfc_eqcq_doorbell_qt_SHIFT 10 732 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 733 #define lpfc_eqcq_doorbell_qt_WORD word0 734 #define LPFC_QUEUE_TYPE_COMPLETION 0 735 #define LPFC_QUEUE_TYPE_EVENT 1 736 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 737 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 738 #define lpfc_eqcq_doorbell_eqci_WORD word0 739 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 740 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 741 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 742 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 743 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 744 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 745 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 746 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 747 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 748 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 749 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 750 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 751 #define LPFC_CQID_HI_FIELD_SHIFT 10 752 #define LPFC_EQID_HI_FIELD_SHIFT 9 753 754 #define LPFC_BMBX 0x0160 755 #define lpfc_bmbx_addr_SHIFT 2 756 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 757 #define lpfc_bmbx_addr_WORD word0 758 #define lpfc_bmbx_hi_SHIFT 1 759 #define lpfc_bmbx_hi_MASK 0x0001 760 #define lpfc_bmbx_hi_WORD word0 761 #define lpfc_bmbx_rdy_SHIFT 0 762 #define lpfc_bmbx_rdy_MASK 0x0001 763 #define lpfc_bmbx_rdy_WORD word0 764 765 #define LPFC_MQ_DOORBELL 0x0140 766 #define lpfc_mq_doorbell_num_posted_SHIFT 16 767 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 768 #define lpfc_mq_doorbell_num_posted_WORD word0 769 #define lpfc_mq_doorbell_id_SHIFT 0 770 #define lpfc_mq_doorbell_id_MASK 0xFFFF 771 #define lpfc_mq_doorbell_id_WORD word0 772 773 struct lpfc_sli4_cfg_mhdr { 774 uint32_t word1; 775 #define lpfc_mbox_hdr_emb_SHIFT 0 776 #define lpfc_mbox_hdr_emb_MASK 0x00000001 777 #define lpfc_mbox_hdr_emb_WORD word1 778 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 779 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 780 #define lpfc_mbox_hdr_sge_cnt_WORD word1 781 uint32_t payload_length; 782 uint32_t tag_lo; 783 uint32_t tag_hi; 784 uint32_t reserved5; 785 }; 786 787 union lpfc_sli4_cfg_shdr { 788 struct { 789 uint32_t word6; 790 #define lpfc_mbox_hdr_opcode_SHIFT 0 791 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 792 #define lpfc_mbox_hdr_opcode_WORD word6 793 #define lpfc_mbox_hdr_subsystem_SHIFT 8 794 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 795 #define lpfc_mbox_hdr_subsystem_WORD word6 796 #define lpfc_mbox_hdr_port_number_SHIFT 16 797 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 798 #define lpfc_mbox_hdr_port_number_WORD word6 799 #define lpfc_mbox_hdr_domain_SHIFT 24 800 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 801 #define lpfc_mbox_hdr_domain_WORD word6 802 uint32_t timeout; 803 uint32_t request_length; 804 uint32_t word9; 805 #define lpfc_mbox_hdr_version_SHIFT 0 806 #define lpfc_mbox_hdr_version_MASK 0x000000FF 807 #define lpfc_mbox_hdr_version_WORD word9 808 #define lpfc_mbox_hdr_pf_num_SHIFT 16 809 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 810 #define lpfc_mbox_hdr_pf_num_WORD word9 811 #define lpfc_mbox_hdr_vh_num_SHIFT 24 812 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 813 #define lpfc_mbox_hdr_vh_num_WORD word9 814 #define LPFC_Q_CREATE_VERSION_2 2 815 #define LPFC_Q_CREATE_VERSION_1 1 816 #define LPFC_Q_CREATE_VERSION_0 0 817 #define LPFC_OPCODE_VERSION_0 0 818 #define LPFC_OPCODE_VERSION_1 1 819 } request; 820 struct { 821 uint32_t word6; 822 #define lpfc_mbox_hdr_opcode_SHIFT 0 823 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 824 #define lpfc_mbox_hdr_opcode_WORD word6 825 #define lpfc_mbox_hdr_subsystem_SHIFT 8 826 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 827 #define lpfc_mbox_hdr_subsystem_WORD word6 828 #define lpfc_mbox_hdr_domain_SHIFT 24 829 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 830 #define lpfc_mbox_hdr_domain_WORD word6 831 uint32_t word7; 832 #define lpfc_mbox_hdr_status_SHIFT 0 833 #define lpfc_mbox_hdr_status_MASK 0x000000FF 834 #define lpfc_mbox_hdr_status_WORD word7 835 #define lpfc_mbox_hdr_add_status_SHIFT 8 836 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 837 #define lpfc_mbox_hdr_add_status_WORD word7 838 uint32_t response_length; 839 uint32_t actual_response_length; 840 } response; 841 }; 842 843 /* Mailbox Header structures. 844 * struct mbox_header is defined for first generation SLI4_CFG mailbox 845 * calls deployed for BE-based ports. 846 * 847 * struct sli4_mbox_header is defined for second generation SLI4 848 * ports that don't deploy the SLI4_CFG mechanism. 849 */ 850 struct mbox_header { 851 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 852 union lpfc_sli4_cfg_shdr cfg_shdr; 853 }; 854 855 #define LPFC_EXTENT_LOCAL 0 856 #define LPFC_TIMEOUT_DEFAULT 0 857 #define LPFC_EXTENT_VERSION_DEFAULT 0 858 859 /* Subsystem Definitions */ 860 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 861 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 862 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 863 864 /* Device Specific Definitions */ 865 866 /* The HOST ENDIAN defines are in Big Endian format. */ 867 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 868 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 869 870 /* Common Opcodes */ 871 #define LPFC_MBOX_OPCODE_NA 0x00 872 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 873 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 874 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 875 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 876 #define LPFC_MBOX_OPCODE_NOP 0x21 877 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 878 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 879 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 880 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 881 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 882 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 883 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 884 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 885 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 886 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 887 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 888 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 889 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 890 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 891 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 892 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 893 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 894 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 895 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 896 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 897 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 898 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 899 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 900 901 /* FCoE Opcodes */ 902 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 903 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 904 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 905 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 906 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 907 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 908 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 909 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 910 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 911 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 912 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 913 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 914 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 915 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 916 917 /* Mailbox command structures */ 918 struct eq_context { 919 uint32_t word0; 920 #define lpfc_eq_context_size_SHIFT 31 921 #define lpfc_eq_context_size_MASK 0x00000001 922 #define lpfc_eq_context_size_WORD word0 923 #define LPFC_EQE_SIZE_4 0x0 924 #define LPFC_EQE_SIZE_16 0x1 925 #define lpfc_eq_context_valid_SHIFT 29 926 #define lpfc_eq_context_valid_MASK 0x00000001 927 #define lpfc_eq_context_valid_WORD word0 928 uint32_t word1; 929 #define lpfc_eq_context_count_SHIFT 26 930 #define lpfc_eq_context_count_MASK 0x00000003 931 #define lpfc_eq_context_count_WORD word1 932 #define LPFC_EQ_CNT_256 0x0 933 #define LPFC_EQ_CNT_512 0x1 934 #define LPFC_EQ_CNT_1024 0x2 935 #define LPFC_EQ_CNT_2048 0x3 936 #define LPFC_EQ_CNT_4096 0x4 937 uint32_t word2; 938 #define lpfc_eq_context_delay_multi_SHIFT 13 939 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 940 #define lpfc_eq_context_delay_multi_WORD word2 941 uint32_t reserved3; 942 }; 943 944 struct eq_delay_info { 945 uint32_t eq_id; 946 uint32_t phase; 947 uint32_t delay_multi; 948 }; 949 #define LPFC_MAX_EQ_DELAY 8 950 951 struct sgl_page_pairs { 952 uint32_t sgl_pg0_addr_lo; 953 uint32_t sgl_pg0_addr_hi; 954 uint32_t sgl_pg1_addr_lo; 955 uint32_t sgl_pg1_addr_hi; 956 }; 957 958 struct lpfc_mbx_post_sgl_pages { 959 struct mbox_header header; 960 uint32_t word0; 961 #define lpfc_post_sgl_pages_xri_SHIFT 0 962 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 963 #define lpfc_post_sgl_pages_xri_WORD word0 964 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 965 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 966 #define lpfc_post_sgl_pages_xricnt_WORD word0 967 struct sgl_page_pairs sgl_pg_pairs[1]; 968 }; 969 970 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 971 struct lpfc_mbx_post_uembed_sgl_page1 { 972 union lpfc_sli4_cfg_shdr cfg_shdr; 973 uint32_t word0; 974 struct sgl_page_pairs sgl_pg_pairs; 975 }; 976 977 struct lpfc_mbx_sge { 978 uint32_t pa_lo; 979 uint32_t pa_hi; 980 uint32_t length; 981 }; 982 983 struct lpfc_mbx_nembed_cmd { 984 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 985 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 986 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 987 }; 988 989 struct lpfc_mbx_nembed_sge_virt { 990 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 991 }; 992 993 struct lpfc_mbx_eq_create { 994 struct mbox_header header; 995 union { 996 struct { 997 uint32_t word0; 998 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 999 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1000 #define lpfc_mbx_eq_create_num_pages_WORD word0 1001 struct eq_context context; 1002 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1003 } request; 1004 struct { 1005 uint32_t word0; 1006 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1007 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1008 #define lpfc_mbx_eq_create_q_id_WORD word0 1009 } response; 1010 } u; 1011 }; 1012 1013 struct lpfc_mbx_modify_eq_delay { 1014 struct mbox_header header; 1015 union { 1016 struct { 1017 uint32_t num_eq; 1018 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY]; 1019 } request; 1020 struct { 1021 uint32_t word0; 1022 } response; 1023 } u; 1024 }; 1025 1026 struct lpfc_mbx_eq_destroy { 1027 struct mbox_header header; 1028 union { 1029 struct { 1030 uint32_t word0; 1031 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1032 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1033 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1034 } request; 1035 struct { 1036 uint32_t word0; 1037 } response; 1038 } u; 1039 }; 1040 1041 struct lpfc_mbx_nop { 1042 struct mbox_header header; 1043 uint32_t context[2]; 1044 }; 1045 1046 struct cq_context { 1047 uint32_t word0; 1048 #define lpfc_cq_context_event_SHIFT 31 1049 #define lpfc_cq_context_event_MASK 0x00000001 1050 #define lpfc_cq_context_event_WORD word0 1051 #define lpfc_cq_context_valid_SHIFT 29 1052 #define lpfc_cq_context_valid_MASK 0x00000001 1053 #define lpfc_cq_context_valid_WORD word0 1054 #define lpfc_cq_context_count_SHIFT 27 1055 #define lpfc_cq_context_count_MASK 0x00000003 1056 #define lpfc_cq_context_count_WORD word0 1057 #define LPFC_CQ_CNT_256 0x0 1058 #define LPFC_CQ_CNT_512 0x1 1059 #define LPFC_CQ_CNT_1024 0x2 1060 uint32_t word1; 1061 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1062 #define lpfc_cq_eq_id_MASK 0x000000FF 1063 #define lpfc_cq_eq_id_WORD word1 1064 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1065 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1066 #define lpfc_cq_eq_id_2_WORD word1 1067 uint32_t reserved0; 1068 uint32_t reserved1; 1069 }; 1070 1071 struct lpfc_mbx_cq_create { 1072 struct mbox_header header; 1073 union { 1074 struct { 1075 uint32_t word0; 1076 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1077 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1078 #define lpfc_mbx_cq_create_page_size_WORD word0 1079 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1080 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1081 #define lpfc_mbx_cq_create_num_pages_WORD word0 1082 struct cq_context context; 1083 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1084 } request; 1085 struct { 1086 uint32_t word0; 1087 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1088 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1089 #define lpfc_mbx_cq_create_q_id_WORD word0 1090 } response; 1091 } u; 1092 }; 1093 1094 struct lpfc_mbx_cq_destroy { 1095 struct mbox_header header; 1096 union { 1097 struct { 1098 uint32_t word0; 1099 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1100 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1101 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1102 } request; 1103 struct { 1104 uint32_t word0; 1105 } response; 1106 } u; 1107 }; 1108 1109 struct wq_context { 1110 uint32_t reserved0; 1111 uint32_t reserved1; 1112 uint32_t reserved2; 1113 uint32_t reserved3; 1114 }; 1115 1116 struct lpfc_mbx_wq_create { 1117 struct mbox_header header; 1118 union { 1119 struct { /* Version 0 Request */ 1120 uint32_t word0; 1121 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1122 #define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF 1123 #define lpfc_mbx_wq_create_num_pages_WORD word0 1124 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1125 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1126 #define lpfc_mbx_wq_create_cq_id_WORD word0 1127 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1128 } request; 1129 struct { /* Version 1 Request */ 1130 uint32_t word0; /* Word 0 is the same as in v0 */ 1131 uint32_t word1; 1132 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1133 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1134 #define lpfc_mbx_wq_create_page_size_WORD word1 1135 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1136 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1137 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1138 #define LPFC_WQ_WQE_SIZE_64 0x5 1139 #define LPFC_WQ_WQE_SIZE_128 0x6 1140 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1141 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1142 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1143 uint32_t word2; 1144 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1145 } request_1; 1146 struct { 1147 uint32_t word0; 1148 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1149 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1150 #define lpfc_mbx_wq_create_q_id_WORD word0 1151 } response; 1152 } u; 1153 }; 1154 1155 struct lpfc_mbx_wq_destroy { 1156 struct mbox_header header; 1157 union { 1158 struct { 1159 uint32_t word0; 1160 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1161 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1162 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1163 } request; 1164 struct { 1165 uint32_t word0; 1166 } response; 1167 } u; 1168 }; 1169 1170 #define LPFC_HDR_BUF_SIZE 128 1171 #define LPFC_DATA_BUF_SIZE 2048 1172 struct rq_context { 1173 uint32_t word0; 1174 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1175 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1176 #define lpfc_rq_context_rqe_count_WORD word0 1177 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1178 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1179 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1180 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1181 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */ 1182 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1183 #define lpfc_rq_context_rqe_count_1_WORD word0 1184 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */ 1185 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1186 #define lpfc_rq_context_rqe_size_WORD word0 1187 #define LPFC_RQE_SIZE_8 2 1188 #define LPFC_RQE_SIZE_16 3 1189 #define LPFC_RQE_SIZE_32 4 1190 #define LPFC_RQE_SIZE_64 5 1191 #define LPFC_RQE_SIZE_128 6 1192 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1193 #define lpfc_rq_context_page_size_MASK 0x000000FF 1194 #define lpfc_rq_context_page_size_WORD word0 1195 uint32_t reserved1; 1196 uint32_t word2; 1197 #define lpfc_rq_context_cq_id_SHIFT 16 1198 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1199 #define lpfc_rq_context_cq_id_WORD word2 1200 #define lpfc_rq_context_buf_size_SHIFT 0 1201 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1202 #define lpfc_rq_context_buf_size_WORD word2 1203 uint32_t buffer_size; /* Version 1 Only */ 1204 }; 1205 1206 struct lpfc_mbx_rq_create { 1207 struct mbox_header header; 1208 union { 1209 struct { 1210 uint32_t word0; 1211 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1212 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1213 #define lpfc_mbx_rq_create_num_pages_WORD word0 1214 struct rq_context context; 1215 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1216 } request; 1217 struct { 1218 uint32_t word0; 1219 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1220 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1221 #define lpfc_mbx_rq_create_q_id_WORD word0 1222 } response; 1223 } u; 1224 }; 1225 1226 struct lpfc_mbx_rq_destroy { 1227 struct mbox_header header; 1228 union { 1229 struct { 1230 uint32_t word0; 1231 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1232 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1233 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1234 } request; 1235 struct { 1236 uint32_t word0; 1237 } response; 1238 } u; 1239 }; 1240 1241 struct mq_context { 1242 uint32_t word0; 1243 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1244 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1245 #define lpfc_mq_context_cq_id_WORD word0 1246 #define lpfc_mq_context_ring_size_SHIFT 16 1247 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1248 #define lpfc_mq_context_ring_size_WORD word0 1249 #define LPFC_MQ_RING_SIZE_16 0x5 1250 #define LPFC_MQ_RING_SIZE_32 0x6 1251 #define LPFC_MQ_RING_SIZE_64 0x7 1252 #define LPFC_MQ_RING_SIZE_128 0x8 1253 uint32_t word1; 1254 #define lpfc_mq_context_valid_SHIFT 31 1255 #define lpfc_mq_context_valid_MASK 0x00000001 1256 #define lpfc_mq_context_valid_WORD word1 1257 uint32_t reserved2; 1258 uint32_t reserved3; 1259 }; 1260 1261 struct lpfc_mbx_mq_create { 1262 struct mbox_header header; 1263 union { 1264 struct { 1265 uint32_t word0; 1266 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1267 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1268 #define lpfc_mbx_mq_create_num_pages_WORD word0 1269 struct mq_context context; 1270 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1271 } request; 1272 struct { 1273 uint32_t word0; 1274 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1275 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1276 #define lpfc_mbx_mq_create_q_id_WORD word0 1277 } response; 1278 } u; 1279 }; 1280 1281 struct lpfc_mbx_mq_create_ext { 1282 struct mbox_header header; 1283 union { 1284 struct { 1285 uint32_t word0; 1286 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1287 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1288 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1289 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1290 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1291 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1292 uint32_t async_evt_bmap; 1293 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1294 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1295 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1296 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1297 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1298 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1299 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1300 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1301 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1302 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1303 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1304 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1305 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1306 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1307 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1308 struct mq_context context; 1309 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1310 } request; 1311 struct { 1312 uint32_t word0; 1313 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1314 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1315 #define lpfc_mbx_mq_create_q_id_WORD word0 1316 } response; 1317 } u; 1318 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1319 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1320 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1321 }; 1322 1323 struct lpfc_mbx_mq_destroy { 1324 struct mbox_header header; 1325 union { 1326 struct { 1327 uint32_t word0; 1328 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1329 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1330 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1331 } request; 1332 struct { 1333 uint32_t word0; 1334 } response; 1335 } u; 1336 }; 1337 1338 /* Start Gen 2 SLI4 Mailbox definitions: */ 1339 1340 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1341 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1342 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1343 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1344 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1345 1346 struct lpfc_mbx_get_rsrc_extent_info { 1347 struct mbox_header header; 1348 union { 1349 struct { 1350 uint32_t word4; 1351 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1352 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1353 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1354 } req; 1355 struct { 1356 uint32_t word4; 1357 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1358 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1359 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1360 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1361 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1362 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1363 } rsp; 1364 } u; 1365 }; 1366 1367 struct lpfc_id_range { 1368 uint32_t word5; 1369 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1370 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1371 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1372 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1373 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1374 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1375 }; 1376 1377 struct lpfc_mbx_set_link_diag_state { 1378 struct mbox_header header; 1379 union { 1380 struct { 1381 uint32_t word0; 1382 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1383 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1384 #define lpfc_mbx_set_diag_state_diag_WORD word0 1385 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1386 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1387 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1388 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1389 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1390 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1391 } req; 1392 struct { 1393 uint32_t word0; 1394 } rsp; 1395 } u; 1396 }; 1397 1398 struct lpfc_mbx_set_link_diag_loopback { 1399 struct mbox_header header; 1400 union { 1401 struct { 1402 uint32_t word0; 1403 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1404 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1405 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1406 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1407 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1408 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1409 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1410 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1411 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1412 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1413 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1414 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1415 } req; 1416 struct { 1417 uint32_t word0; 1418 } rsp; 1419 } u; 1420 }; 1421 1422 struct lpfc_mbx_run_link_diag_test { 1423 struct mbox_header header; 1424 union { 1425 struct { 1426 uint32_t word0; 1427 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1428 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1429 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1430 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1431 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1432 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1433 uint32_t word1; 1434 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1435 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1436 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1437 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1438 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1439 #define lpfc_mbx_run_diag_test_loops_WORD word1 1440 uint32_t word2; 1441 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1442 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1443 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1444 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1445 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1446 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1447 } req; 1448 struct { 1449 uint32_t word0; 1450 } rsp; 1451 } u; 1452 }; 1453 1454 /* 1455 * struct lpfc_mbx_alloc_rsrc_extents: 1456 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1457 * 6 words of header + 4 words of shared subcommand header + 1458 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1459 * 1460 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1461 * for extents payload. 1462 * 1463 * 212/2 (bytes per extent) = 106 extents. 1464 * 106/2 (extents per word) = 53 words. 1465 * lpfc_id_range id is statically size to 53. 1466 * 1467 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1468 * extent ranges. For ALLOC, the type and cnt are required. 1469 * For GET_ALLOCATED, only the type is required. 1470 */ 1471 struct lpfc_mbx_alloc_rsrc_extents { 1472 struct mbox_header header; 1473 union { 1474 struct { 1475 uint32_t word4; 1476 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1477 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1478 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1479 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1480 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1481 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1482 } req; 1483 struct { 1484 uint32_t word4; 1485 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1486 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1487 #define lpfc_mbx_rsrc_cnt_WORD word4 1488 struct lpfc_id_range id[53]; 1489 } rsp; 1490 } u; 1491 }; 1492 1493 /* 1494 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1495 * structure shares the same SHIFT/MASK/WORD defines provided in the 1496 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1497 * the structures defined above. This non-embedded structure provides for the 1498 * maximum number of extents supported by the port. 1499 */ 1500 struct lpfc_mbx_nembed_rsrc_extent { 1501 union lpfc_sli4_cfg_shdr cfg_shdr; 1502 uint32_t word4; 1503 struct lpfc_id_range id; 1504 }; 1505 1506 struct lpfc_mbx_dealloc_rsrc_extents { 1507 struct mbox_header header; 1508 struct { 1509 uint32_t word4; 1510 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1511 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1512 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1513 } req; 1514 1515 }; 1516 1517 /* Start SLI4 FCoE specific mbox structures. */ 1518 1519 struct lpfc_mbx_post_hdr_tmpl { 1520 struct mbox_header header; 1521 uint32_t word10; 1522 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1523 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1524 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1525 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1526 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1527 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1528 uint32_t rpi_paddr_lo; 1529 uint32_t rpi_paddr_hi; 1530 }; 1531 1532 struct sli4_sge { /* SLI-4 */ 1533 uint32_t addr_hi; 1534 uint32_t addr_lo; 1535 1536 uint32_t word2; 1537 #define lpfc_sli4_sge_offset_SHIFT 0 1538 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1539 #define lpfc_sli4_sge_offset_WORD word2 1540 #define lpfc_sli4_sge_type_SHIFT 27 1541 #define lpfc_sli4_sge_type_MASK 0x0000000F 1542 #define lpfc_sli4_sge_type_WORD word2 1543 #define LPFC_SGE_TYPE_DATA 0x0 1544 #define LPFC_SGE_TYPE_DIF 0x4 1545 #define LPFC_SGE_TYPE_LSP 0x5 1546 #define LPFC_SGE_TYPE_PEDIF 0x6 1547 #define LPFC_SGE_TYPE_PESEED 0x7 1548 #define LPFC_SGE_TYPE_DISEED 0x8 1549 #define LPFC_SGE_TYPE_ENC 0x9 1550 #define LPFC_SGE_TYPE_ATM 0xA 1551 #define LPFC_SGE_TYPE_SKIP 0xC 1552 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1553 #define lpfc_sli4_sge_last_MASK 0x00000001 1554 #define lpfc_sli4_sge_last_WORD word2 1555 uint32_t sge_len; 1556 }; 1557 1558 struct sli4_sge_diseed { /* SLI-4 */ 1559 uint32_t ref_tag; 1560 uint32_t ref_tag_tran; 1561 1562 uint32_t word2; 1563 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 1564 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 1565 #define lpfc_sli4_sge_dif_apptran_WORD word2 1566 #define lpfc_sli4_sge_dif_af_SHIFT 24 1567 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 1568 #define lpfc_sli4_sge_dif_af_WORD word2 1569 #define lpfc_sli4_sge_dif_na_SHIFT 25 1570 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 1571 #define lpfc_sli4_sge_dif_na_WORD word2 1572 #define lpfc_sli4_sge_dif_hi_SHIFT 26 1573 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 1574 #define lpfc_sli4_sge_dif_hi_WORD word2 1575 #define lpfc_sli4_sge_dif_type_SHIFT 27 1576 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 1577 #define lpfc_sli4_sge_dif_type_WORD word2 1578 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1579 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 1580 #define lpfc_sli4_sge_dif_last_WORD word2 1581 uint32_t word3; 1582 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 1583 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 1584 #define lpfc_sli4_sge_dif_apptag_WORD word3 1585 #define lpfc_sli4_sge_dif_bs_SHIFT 16 1586 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 1587 #define lpfc_sli4_sge_dif_bs_WORD word3 1588 #define lpfc_sli4_sge_dif_ai_SHIFT 19 1589 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 1590 #define lpfc_sli4_sge_dif_ai_WORD word3 1591 #define lpfc_sli4_sge_dif_me_SHIFT 20 1592 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 1593 #define lpfc_sli4_sge_dif_me_WORD word3 1594 #define lpfc_sli4_sge_dif_re_SHIFT 21 1595 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 1596 #define lpfc_sli4_sge_dif_re_WORD word3 1597 #define lpfc_sli4_sge_dif_ce_SHIFT 22 1598 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 1599 #define lpfc_sli4_sge_dif_ce_WORD word3 1600 #define lpfc_sli4_sge_dif_nr_SHIFT 23 1601 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 1602 #define lpfc_sli4_sge_dif_nr_WORD word3 1603 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 1604 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 1605 #define lpfc_sli4_sge_dif_oprx_WORD word3 1606 #define lpfc_sli4_sge_dif_optx_SHIFT 28 1607 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 1608 #define lpfc_sli4_sge_dif_optx_WORD word3 1609 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 1610 }; 1611 1612 struct fcf_record { 1613 uint32_t max_rcv_size; 1614 uint32_t fka_adv_period; 1615 uint32_t fip_priority; 1616 uint32_t word3; 1617 #define lpfc_fcf_record_mac_0_SHIFT 0 1618 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1619 #define lpfc_fcf_record_mac_0_WORD word3 1620 #define lpfc_fcf_record_mac_1_SHIFT 8 1621 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1622 #define lpfc_fcf_record_mac_1_WORD word3 1623 #define lpfc_fcf_record_mac_2_SHIFT 16 1624 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1625 #define lpfc_fcf_record_mac_2_WORD word3 1626 #define lpfc_fcf_record_mac_3_SHIFT 24 1627 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1628 #define lpfc_fcf_record_mac_3_WORD word3 1629 uint32_t word4; 1630 #define lpfc_fcf_record_mac_4_SHIFT 0 1631 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1632 #define lpfc_fcf_record_mac_4_WORD word4 1633 #define lpfc_fcf_record_mac_5_SHIFT 8 1634 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1635 #define lpfc_fcf_record_mac_5_WORD word4 1636 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1637 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1638 #define lpfc_fcf_record_fcf_avail_WORD word4 1639 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1640 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1641 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1642 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1643 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1644 uint32_t word5; 1645 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1646 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1647 #define lpfc_fcf_record_fab_name_0_WORD word5 1648 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1649 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1650 #define lpfc_fcf_record_fab_name_1_WORD word5 1651 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1652 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1653 #define lpfc_fcf_record_fab_name_2_WORD word5 1654 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1655 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1656 #define lpfc_fcf_record_fab_name_3_WORD word5 1657 uint32_t word6; 1658 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1659 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1660 #define lpfc_fcf_record_fab_name_4_WORD word6 1661 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1662 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1663 #define lpfc_fcf_record_fab_name_5_WORD word6 1664 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1665 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 1666 #define lpfc_fcf_record_fab_name_6_WORD word6 1667 #define lpfc_fcf_record_fab_name_7_SHIFT 24 1668 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 1669 #define lpfc_fcf_record_fab_name_7_WORD word6 1670 uint32_t word7; 1671 #define lpfc_fcf_record_fc_map_0_SHIFT 0 1672 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 1673 #define lpfc_fcf_record_fc_map_0_WORD word7 1674 #define lpfc_fcf_record_fc_map_1_SHIFT 8 1675 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 1676 #define lpfc_fcf_record_fc_map_1_WORD word7 1677 #define lpfc_fcf_record_fc_map_2_SHIFT 16 1678 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 1679 #define lpfc_fcf_record_fc_map_2_WORD word7 1680 #define lpfc_fcf_record_fcf_valid_SHIFT 24 1681 #define lpfc_fcf_record_fcf_valid_MASK 0x000000FF 1682 #define lpfc_fcf_record_fcf_valid_WORD word7 1683 uint32_t word8; 1684 #define lpfc_fcf_record_fcf_index_SHIFT 0 1685 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 1686 #define lpfc_fcf_record_fcf_index_WORD word8 1687 #define lpfc_fcf_record_fcf_state_SHIFT 16 1688 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 1689 #define lpfc_fcf_record_fcf_state_WORD word8 1690 uint8_t vlan_bitmap[512]; 1691 uint32_t word137; 1692 #define lpfc_fcf_record_switch_name_0_SHIFT 0 1693 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 1694 #define lpfc_fcf_record_switch_name_0_WORD word137 1695 #define lpfc_fcf_record_switch_name_1_SHIFT 8 1696 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 1697 #define lpfc_fcf_record_switch_name_1_WORD word137 1698 #define lpfc_fcf_record_switch_name_2_SHIFT 16 1699 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 1700 #define lpfc_fcf_record_switch_name_2_WORD word137 1701 #define lpfc_fcf_record_switch_name_3_SHIFT 24 1702 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 1703 #define lpfc_fcf_record_switch_name_3_WORD word137 1704 uint32_t word138; 1705 #define lpfc_fcf_record_switch_name_4_SHIFT 0 1706 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 1707 #define lpfc_fcf_record_switch_name_4_WORD word138 1708 #define lpfc_fcf_record_switch_name_5_SHIFT 8 1709 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 1710 #define lpfc_fcf_record_switch_name_5_WORD word138 1711 #define lpfc_fcf_record_switch_name_6_SHIFT 16 1712 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 1713 #define lpfc_fcf_record_switch_name_6_WORD word138 1714 #define lpfc_fcf_record_switch_name_7_SHIFT 24 1715 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 1716 #define lpfc_fcf_record_switch_name_7_WORD word138 1717 }; 1718 1719 struct lpfc_mbx_read_fcf_tbl { 1720 union lpfc_sli4_cfg_shdr cfg_shdr; 1721 union { 1722 struct { 1723 uint32_t word10; 1724 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 1725 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 1726 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 1727 } request; 1728 struct { 1729 uint32_t eventag; 1730 } response; 1731 } u; 1732 uint32_t word11; 1733 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 1734 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 1735 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 1736 }; 1737 1738 struct lpfc_mbx_add_fcf_tbl_entry { 1739 union lpfc_sli4_cfg_shdr cfg_shdr; 1740 uint32_t word10; 1741 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 1742 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 1743 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 1744 struct lpfc_mbx_sge fcf_sge; 1745 }; 1746 1747 struct lpfc_mbx_del_fcf_tbl_entry { 1748 struct mbox_header header; 1749 uint32_t word10; 1750 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 1751 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 1752 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 1753 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 1754 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 1755 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 1756 }; 1757 1758 struct lpfc_mbx_redisc_fcf_tbl { 1759 struct mbox_header header; 1760 uint32_t word10; 1761 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 1762 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 1763 #define lpfc_mbx_redisc_fcf_count_WORD word10 1764 uint32_t resvd; 1765 uint32_t word12; 1766 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 1767 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 1768 #define lpfc_mbx_redisc_fcf_index_WORD word12 1769 }; 1770 1771 struct lpfc_mbx_query_fw_cfg { 1772 struct mbox_header header; 1773 uint32_t config_number; 1774 uint32_t asic_rev; 1775 uint32_t phys_port; 1776 uint32_t function_mode; 1777 /* firmware Function Mode */ 1778 #define lpfc_function_mode_toe_SHIFT 0 1779 #define lpfc_function_mode_toe_MASK 0x00000001 1780 #define lpfc_function_mode_toe_WORD function_mode 1781 #define lpfc_function_mode_nic_SHIFT 1 1782 #define lpfc_function_mode_nic_MASK 0x00000001 1783 #define lpfc_function_mode_nic_WORD function_mode 1784 #define lpfc_function_mode_rdma_SHIFT 2 1785 #define lpfc_function_mode_rdma_MASK 0x00000001 1786 #define lpfc_function_mode_rdma_WORD function_mode 1787 #define lpfc_function_mode_vm_SHIFT 3 1788 #define lpfc_function_mode_vm_MASK 0x00000001 1789 #define lpfc_function_mode_vm_WORD function_mode 1790 #define lpfc_function_mode_iscsi_i_SHIFT 4 1791 #define lpfc_function_mode_iscsi_i_MASK 0x00000001 1792 #define lpfc_function_mode_iscsi_i_WORD function_mode 1793 #define lpfc_function_mode_iscsi_t_SHIFT 5 1794 #define lpfc_function_mode_iscsi_t_MASK 0x00000001 1795 #define lpfc_function_mode_iscsi_t_WORD function_mode 1796 #define lpfc_function_mode_fcoe_i_SHIFT 6 1797 #define lpfc_function_mode_fcoe_i_MASK 0x00000001 1798 #define lpfc_function_mode_fcoe_i_WORD function_mode 1799 #define lpfc_function_mode_fcoe_t_SHIFT 7 1800 #define lpfc_function_mode_fcoe_t_MASK 0x00000001 1801 #define lpfc_function_mode_fcoe_t_WORD function_mode 1802 #define lpfc_function_mode_dal_SHIFT 8 1803 #define lpfc_function_mode_dal_MASK 0x00000001 1804 #define lpfc_function_mode_dal_WORD function_mode 1805 #define lpfc_function_mode_lro_SHIFT 9 1806 #define lpfc_function_mode_lro_MASK 0x00000001 1807 #define lpfc_function_mode_lro_WORD function_mode 1808 #define lpfc_function_mode_flex10_SHIFT 10 1809 #define lpfc_function_mode_flex10_MASK 0x00000001 1810 #define lpfc_function_mode_flex10_WORD function_mode 1811 #define lpfc_function_mode_ncsi_SHIFT 11 1812 #define lpfc_function_mode_ncsi_MASK 0x00000001 1813 #define lpfc_function_mode_ncsi_WORD function_mode 1814 }; 1815 1816 /* Status field for embedded SLI_CONFIG mailbox command */ 1817 #define STATUS_SUCCESS 0x0 1818 #define STATUS_FAILED 0x1 1819 #define STATUS_ILLEGAL_REQUEST 0x2 1820 #define STATUS_ILLEGAL_FIELD 0x3 1821 #define STATUS_INSUFFICIENT_BUFFER 0x4 1822 #define STATUS_UNAUTHORIZED_REQUEST 0x5 1823 #define STATUS_FLASHROM_SAVE_FAILED 0x17 1824 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 1825 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 1826 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 1827 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 1828 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 1829 #define STATUS_ASSERT_FAILED 0x1e 1830 #define STATUS_INVALID_SESSION 0x1f 1831 #define STATUS_INVALID_CONNECTION 0x20 1832 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 1833 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 1834 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 1835 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 1836 #define STATUS_FLASHROM_READ_FAILED 0x27 1837 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 1838 #define STATUS_ERROR_ACITMAIN 0x2a 1839 #define STATUS_REBOOT_REQUIRED 0x2c 1840 #define STATUS_FCF_IN_USE 0x3a 1841 #define STATUS_FCF_TABLE_EMPTY 0x43 1842 1843 struct lpfc_mbx_sli4_config { 1844 struct mbox_header header; 1845 }; 1846 1847 struct lpfc_mbx_init_vfi { 1848 uint32_t word1; 1849 #define lpfc_init_vfi_vr_SHIFT 31 1850 #define lpfc_init_vfi_vr_MASK 0x00000001 1851 #define lpfc_init_vfi_vr_WORD word1 1852 #define lpfc_init_vfi_vt_SHIFT 30 1853 #define lpfc_init_vfi_vt_MASK 0x00000001 1854 #define lpfc_init_vfi_vt_WORD word1 1855 #define lpfc_init_vfi_vf_SHIFT 29 1856 #define lpfc_init_vfi_vf_MASK 0x00000001 1857 #define lpfc_init_vfi_vf_WORD word1 1858 #define lpfc_init_vfi_vp_SHIFT 28 1859 #define lpfc_init_vfi_vp_MASK 0x00000001 1860 #define lpfc_init_vfi_vp_WORD word1 1861 #define lpfc_init_vfi_vfi_SHIFT 0 1862 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1863 #define lpfc_init_vfi_vfi_WORD word1 1864 uint32_t word2; 1865 #define lpfc_init_vfi_vpi_SHIFT 16 1866 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 1867 #define lpfc_init_vfi_vpi_WORD word2 1868 #define lpfc_init_vfi_fcfi_SHIFT 0 1869 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1870 #define lpfc_init_vfi_fcfi_WORD word2 1871 uint32_t word3; 1872 #define lpfc_init_vfi_pri_SHIFT 13 1873 #define lpfc_init_vfi_pri_MASK 0x00000007 1874 #define lpfc_init_vfi_pri_WORD word3 1875 #define lpfc_init_vfi_vf_id_SHIFT 1 1876 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 1877 #define lpfc_init_vfi_vf_id_WORD word3 1878 uint32_t word4; 1879 #define lpfc_init_vfi_hop_count_SHIFT 24 1880 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 1881 #define lpfc_init_vfi_hop_count_WORD word4 1882 }; 1883 #define MBX_VFI_IN_USE 0x9F02 1884 1885 1886 struct lpfc_mbx_reg_vfi { 1887 uint32_t word1; 1888 #define lpfc_reg_vfi_vp_SHIFT 28 1889 #define lpfc_reg_vfi_vp_MASK 0x00000001 1890 #define lpfc_reg_vfi_vp_WORD word1 1891 #define lpfc_reg_vfi_vfi_SHIFT 0 1892 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 1893 #define lpfc_reg_vfi_vfi_WORD word1 1894 uint32_t word2; 1895 #define lpfc_reg_vfi_vpi_SHIFT 16 1896 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 1897 #define lpfc_reg_vfi_vpi_WORD word2 1898 #define lpfc_reg_vfi_fcfi_SHIFT 0 1899 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 1900 #define lpfc_reg_vfi_fcfi_WORD word2 1901 uint32_t wwn[2]; 1902 struct ulp_bde64 bde; 1903 uint32_t e_d_tov; 1904 uint32_t r_a_tov; 1905 uint32_t word10; 1906 #define lpfc_reg_vfi_nport_id_SHIFT 0 1907 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 1908 #define lpfc_reg_vfi_nport_id_WORD word10 1909 }; 1910 1911 struct lpfc_mbx_init_vpi { 1912 uint32_t word1; 1913 #define lpfc_init_vpi_vfi_SHIFT 16 1914 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 1915 #define lpfc_init_vpi_vfi_WORD word1 1916 #define lpfc_init_vpi_vpi_SHIFT 0 1917 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 1918 #define lpfc_init_vpi_vpi_WORD word1 1919 }; 1920 1921 struct lpfc_mbx_read_vpi { 1922 uint32_t word1_rsvd; 1923 uint32_t word2; 1924 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 1925 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 1926 #define lpfc_mbx_read_vpi_vnportid_WORD word2 1927 uint32_t word3_rsvd; 1928 uint32_t word4; 1929 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 1930 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 1931 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 1932 #define lpfc_mbx_read_vpi_pb_SHIFT 15 1933 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 1934 #define lpfc_mbx_read_vpi_pb_WORD word4 1935 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 1936 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 1937 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 1938 #define lpfc_mbx_read_vpi_ns_SHIFT 30 1939 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 1940 #define lpfc_mbx_read_vpi_ns_WORD word4 1941 #define lpfc_mbx_read_vpi_hl_SHIFT 31 1942 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 1943 #define lpfc_mbx_read_vpi_hl_WORD word4 1944 uint32_t word5_rsvd; 1945 uint32_t word6; 1946 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 1947 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 1948 #define lpfc_mbx_read_vpi_vpi_WORD word6 1949 uint32_t word7; 1950 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 1951 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 1952 #define lpfc_mbx_read_vpi_mac_0_WORD word7 1953 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 1954 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 1955 #define lpfc_mbx_read_vpi_mac_1_WORD word7 1956 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 1957 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 1958 #define lpfc_mbx_read_vpi_mac_2_WORD word7 1959 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 1960 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 1961 #define lpfc_mbx_read_vpi_mac_3_WORD word7 1962 uint32_t word8; 1963 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 1964 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 1965 #define lpfc_mbx_read_vpi_mac_4_WORD word8 1966 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 1967 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 1968 #define lpfc_mbx_read_vpi_mac_5_WORD word8 1969 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 1970 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 1971 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 1972 #define lpfc_mbx_read_vpi_vv_SHIFT 28 1973 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 1974 #define lpfc_mbx_read_vpi_vv_WORD word8 1975 }; 1976 1977 struct lpfc_mbx_unreg_vfi { 1978 uint32_t word1_rsvd; 1979 uint32_t word2; 1980 #define lpfc_unreg_vfi_vfi_SHIFT 0 1981 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 1982 #define lpfc_unreg_vfi_vfi_WORD word2 1983 }; 1984 1985 struct lpfc_mbx_resume_rpi { 1986 uint32_t word1; 1987 #define lpfc_resume_rpi_index_SHIFT 0 1988 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 1989 #define lpfc_resume_rpi_index_WORD word1 1990 #define lpfc_resume_rpi_ii_SHIFT 30 1991 #define lpfc_resume_rpi_ii_MASK 0x00000003 1992 #define lpfc_resume_rpi_ii_WORD word1 1993 #define RESUME_INDEX_RPI 0 1994 #define RESUME_INDEX_VPI 1 1995 #define RESUME_INDEX_VFI 2 1996 #define RESUME_INDEX_FCFI 3 1997 uint32_t event_tag; 1998 }; 1999 2000 #define REG_FCF_INVALID_QID 0xFFFF 2001 struct lpfc_mbx_reg_fcfi { 2002 uint32_t word1; 2003 #define lpfc_reg_fcfi_info_index_SHIFT 0 2004 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2005 #define lpfc_reg_fcfi_info_index_WORD word1 2006 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2007 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2008 #define lpfc_reg_fcfi_fcfi_WORD word1 2009 uint32_t word2; 2010 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2011 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2012 #define lpfc_reg_fcfi_rq_id1_WORD word2 2013 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2014 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2015 #define lpfc_reg_fcfi_rq_id0_WORD word2 2016 uint32_t word3; 2017 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2018 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2019 #define lpfc_reg_fcfi_rq_id3_WORD word3 2020 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2021 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2022 #define lpfc_reg_fcfi_rq_id2_WORD word3 2023 uint32_t word4; 2024 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2025 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2026 #define lpfc_reg_fcfi_type_match0_WORD word4 2027 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2028 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2029 #define lpfc_reg_fcfi_type_mask0_WORD word4 2030 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2031 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2032 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2033 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2034 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2035 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2036 uint32_t word5; 2037 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2038 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2039 #define lpfc_reg_fcfi_type_match1_WORD word5 2040 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2041 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2042 #define lpfc_reg_fcfi_type_mask1_WORD word5 2043 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2044 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2045 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2046 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2047 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2048 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2049 uint32_t word6; 2050 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2051 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2052 #define lpfc_reg_fcfi_type_match2_WORD word6 2053 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2054 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2055 #define lpfc_reg_fcfi_type_mask2_WORD word6 2056 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2057 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2058 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2059 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2060 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2061 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2062 uint32_t word7; 2063 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2064 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2065 #define lpfc_reg_fcfi_type_match3_WORD word7 2066 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2067 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2068 #define lpfc_reg_fcfi_type_mask3_WORD word7 2069 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2070 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2071 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2072 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2073 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2074 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2075 uint32_t word8; 2076 #define lpfc_reg_fcfi_mam_SHIFT 13 2077 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2078 #define lpfc_reg_fcfi_mam_WORD word8 2079 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2080 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2081 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2082 #define lpfc_reg_fcfi_vv_SHIFT 12 2083 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2084 #define lpfc_reg_fcfi_vv_WORD word8 2085 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2086 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2087 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2088 }; 2089 2090 struct lpfc_mbx_unreg_fcfi { 2091 uint32_t word1_rsv; 2092 uint32_t word2; 2093 #define lpfc_unreg_fcfi_SHIFT 0 2094 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2095 #define lpfc_unreg_fcfi_WORD word2 2096 }; 2097 2098 struct lpfc_mbx_read_rev { 2099 uint32_t word1; 2100 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2101 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2102 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2103 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2104 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2105 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2106 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2107 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2108 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2109 #define LPFC_PREDCBX_CEE_MODE 0 2110 #define LPFC_DCBX_CEE_MODE 1 2111 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2112 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2113 #define lpfc_mbx_rd_rev_vpd_WORD word1 2114 uint32_t first_hw_rev; 2115 uint32_t second_hw_rev; 2116 uint32_t word4_rsvd; 2117 uint32_t third_hw_rev; 2118 uint32_t word6; 2119 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2120 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2121 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2122 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2123 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2124 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2125 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2126 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2127 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2128 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2129 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2130 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2131 uint32_t word7_rsvd; 2132 uint32_t fw_id_rev; 2133 uint8_t fw_name[16]; 2134 uint32_t ulp_fw_id_rev; 2135 uint8_t ulp_fw_name[16]; 2136 uint32_t word18_47_rsvd[30]; 2137 uint32_t word48; 2138 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2139 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2140 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2141 uint32_t vpd_paddr_low; 2142 uint32_t vpd_paddr_high; 2143 uint32_t avail_vpd_len; 2144 uint32_t rsvd_52_63[12]; 2145 }; 2146 2147 struct lpfc_mbx_read_config { 2148 uint32_t word1; 2149 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2150 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2151 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2152 uint32_t word2; 2153 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2154 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2155 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2156 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2157 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2158 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2159 #define LPFC_LNK_TYPE_GE 0 2160 #define LPFC_LNK_TYPE_FC 1 2161 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2162 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2163 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2164 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2165 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2166 #define lpfc_mbx_rd_conf_topology_WORD word2 2167 uint32_t rsvd_3; 2168 uint32_t word4; 2169 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2170 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2171 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2172 uint32_t rsvd_5; 2173 uint32_t word6; 2174 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2175 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2176 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2177 uint32_t rsvd_7; 2178 uint32_t rsvd_8; 2179 uint32_t word9; 2180 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2181 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2182 #define lpfc_mbx_rd_conf_lmt_WORD word9 2183 uint32_t rsvd_10; 2184 uint32_t rsvd_11; 2185 uint32_t word12; 2186 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2187 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2188 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2189 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2190 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2191 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2192 uint32_t word13; 2193 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2194 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2195 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2196 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2197 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2198 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2199 uint32_t word14; 2200 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2201 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2202 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2203 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2204 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2205 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2206 uint32_t word15; 2207 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2208 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2209 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2210 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2211 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2212 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2213 uint32_t word16; 2214 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2215 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2216 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2217 uint32_t word17; 2218 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2219 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2220 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2221 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2222 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2223 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2224 uint32_t word18; 2225 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2226 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2227 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2228 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2229 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2230 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2231 }; 2232 2233 struct lpfc_mbx_request_features { 2234 uint32_t word1; 2235 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2236 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2237 #define lpfc_mbx_rq_ftr_qry_WORD word1 2238 uint32_t word2; 2239 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2240 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2241 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2242 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2243 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2244 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2245 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2246 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2247 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2248 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2249 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2250 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2251 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2252 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2253 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2254 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2255 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2256 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2257 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2258 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2259 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2260 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2261 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2262 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2263 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2264 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2265 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2266 uint32_t word3; 2267 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2268 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2269 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2270 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2271 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2272 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2273 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2274 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2275 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2276 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2277 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2278 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2279 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2280 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2281 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2282 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2283 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2284 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2285 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2286 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2287 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2288 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2289 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2290 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2291 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2292 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2293 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2294 }; 2295 2296 struct lpfc_mbx_supp_pages { 2297 uint32_t word1; 2298 #define qs_SHIFT 0 2299 #define qs_MASK 0x00000001 2300 #define qs_WORD word1 2301 #define wr_SHIFT 1 2302 #define wr_MASK 0x00000001 2303 #define wr_WORD word1 2304 #define pf_SHIFT 8 2305 #define pf_MASK 0x000000ff 2306 #define pf_WORD word1 2307 #define cpn_SHIFT 16 2308 #define cpn_MASK 0x000000ff 2309 #define cpn_WORD word1 2310 uint32_t word2; 2311 #define list_offset_SHIFT 0 2312 #define list_offset_MASK 0x000000ff 2313 #define list_offset_WORD word2 2314 #define next_offset_SHIFT 8 2315 #define next_offset_MASK 0x000000ff 2316 #define next_offset_WORD word2 2317 #define elem_cnt_SHIFT 16 2318 #define elem_cnt_MASK 0x000000ff 2319 #define elem_cnt_WORD word2 2320 uint32_t word3; 2321 #define pn_0_SHIFT 24 2322 #define pn_0_MASK 0x000000ff 2323 #define pn_0_WORD word3 2324 #define pn_1_SHIFT 16 2325 #define pn_1_MASK 0x000000ff 2326 #define pn_1_WORD word3 2327 #define pn_2_SHIFT 8 2328 #define pn_2_MASK 0x000000ff 2329 #define pn_2_WORD word3 2330 #define pn_3_SHIFT 0 2331 #define pn_3_MASK 0x000000ff 2332 #define pn_3_WORD word3 2333 uint32_t word4; 2334 #define pn_4_SHIFT 24 2335 #define pn_4_MASK 0x000000ff 2336 #define pn_4_WORD word4 2337 #define pn_5_SHIFT 16 2338 #define pn_5_MASK 0x000000ff 2339 #define pn_5_WORD word4 2340 #define pn_6_SHIFT 8 2341 #define pn_6_MASK 0x000000ff 2342 #define pn_6_WORD word4 2343 #define pn_7_SHIFT 0 2344 #define pn_7_MASK 0x000000ff 2345 #define pn_7_WORD word4 2346 uint32_t rsvd[27]; 2347 #define LPFC_SUPP_PAGES 0 2348 #define LPFC_BLOCK_GUARD_PROFILES 1 2349 #define LPFC_SLI4_PARAMETERS 2 2350 }; 2351 2352 struct lpfc_mbx_pc_sli4_params { 2353 uint32_t word1; 2354 #define qs_SHIFT 0 2355 #define qs_MASK 0x00000001 2356 #define qs_WORD word1 2357 #define wr_SHIFT 1 2358 #define wr_MASK 0x00000001 2359 #define wr_WORD word1 2360 #define pf_SHIFT 8 2361 #define pf_MASK 0x000000ff 2362 #define pf_WORD word1 2363 #define cpn_SHIFT 16 2364 #define cpn_MASK 0x000000ff 2365 #define cpn_WORD word1 2366 uint32_t word2; 2367 #define if_type_SHIFT 0 2368 #define if_type_MASK 0x00000007 2369 #define if_type_WORD word2 2370 #define sli_rev_SHIFT 4 2371 #define sli_rev_MASK 0x0000000f 2372 #define sli_rev_WORD word2 2373 #define sli_family_SHIFT 8 2374 #define sli_family_MASK 0x000000ff 2375 #define sli_family_WORD word2 2376 #define featurelevel_1_SHIFT 16 2377 #define featurelevel_1_MASK 0x000000ff 2378 #define featurelevel_1_WORD word2 2379 #define featurelevel_2_SHIFT 24 2380 #define featurelevel_2_MASK 0x0000001f 2381 #define featurelevel_2_WORD word2 2382 uint32_t word3; 2383 #define fcoe_SHIFT 0 2384 #define fcoe_MASK 0x00000001 2385 #define fcoe_WORD word3 2386 #define fc_SHIFT 1 2387 #define fc_MASK 0x00000001 2388 #define fc_WORD word3 2389 #define nic_SHIFT 2 2390 #define nic_MASK 0x00000001 2391 #define nic_WORD word3 2392 #define iscsi_SHIFT 3 2393 #define iscsi_MASK 0x00000001 2394 #define iscsi_WORD word3 2395 #define rdma_SHIFT 4 2396 #define rdma_MASK 0x00000001 2397 #define rdma_WORD word3 2398 uint32_t sge_supp_len; 2399 #define SLI4_PAGE_SIZE 4096 2400 uint32_t word5; 2401 #define if_page_sz_SHIFT 0 2402 #define if_page_sz_MASK 0x0000ffff 2403 #define if_page_sz_WORD word5 2404 #define loopbk_scope_SHIFT 24 2405 #define loopbk_scope_MASK 0x0000000f 2406 #define loopbk_scope_WORD word5 2407 #define rq_db_window_SHIFT 28 2408 #define rq_db_window_MASK 0x0000000f 2409 #define rq_db_window_WORD word5 2410 uint32_t word6; 2411 #define eq_pages_SHIFT 0 2412 #define eq_pages_MASK 0x0000000f 2413 #define eq_pages_WORD word6 2414 #define eqe_size_SHIFT 8 2415 #define eqe_size_MASK 0x000000ff 2416 #define eqe_size_WORD word6 2417 uint32_t word7; 2418 #define cq_pages_SHIFT 0 2419 #define cq_pages_MASK 0x0000000f 2420 #define cq_pages_WORD word7 2421 #define cqe_size_SHIFT 8 2422 #define cqe_size_MASK 0x000000ff 2423 #define cqe_size_WORD word7 2424 uint32_t word8; 2425 #define mq_pages_SHIFT 0 2426 #define mq_pages_MASK 0x0000000f 2427 #define mq_pages_WORD word8 2428 #define mqe_size_SHIFT 8 2429 #define mqe_size_MASK 0x000000ff 2430 #define mqe_size_WORD word8 2431 #define mq_elem_cnt_SHIFT 16 2432 #define mq_elem_cnt_MASK 0x000000ff 2433 #define mq_elem_cnt_WORD word8 2434 uint32_t word9; 2435 #define wq_pages_SHIFT 0 2436 #define wq_pages_MASK 0x0000ffff 2437 #define wq_pages_WORD word9 2438 #define wqe_size_SHIFT 8 2439 #define wqe_size_MASK 0x000000ff 2440 #define wqe_size_WORD word9 2441 uint32_t word10; 2442 #define rq_pages_SHIFT 0 2443 #define rq_pages_MASK 0x0000ffff 2444 #define rq_pages_WORD word10 2445 #define rqe_size_SHIFT 8 2446 #define rqe_size_MASK 0x000000ff 2447 #define rqe_size_WORD word10 2448 uint32_t word11; 2449 #define hdr_pages_SHIFT 0 2450 #define hdr_pages_MASK 0x0000000f 2451 #define hdr_pages_WORD word11 2452 #define hdr_size_SHIFT 8 2453 #define hdr_size_MASK 0x0000000f 2454 #define hdr_size_WORD word11 2455 #define hdr_pp_align_SHIFT 16 2456 #define hdr_pp_align_MASK 0x0000ffff 2457 #define hdr_pp_align_WORD word11 2458 uint32_t word12; 2459 #define sgl_pages_SHIFT 0 2460 #define sgl_pages_MASK 0x0000000f 2461 #define sgl_pages_WORD word12 2462 #define sgl_pp_align_SHIFT 16 2463 #define sgl_pp_align_MASK 0x0000ffff 2464 #define sgl_pp_align_WORD word12 2465 uint32_t rsvd_13_63[51]; 2466 }; 2467 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 2468 &(~((SLI4_PAGE_SIZE)-1))) 2469 2470 struct lpfc_sli4_parameters { 2471 uint32_t word0; 2472 #define cfg_prot_type_SHIFT 0 2473 #define cfg_prot_type_MASK 0x000000FF 2474 #define cfg_prot_type_WORD word0 2475 uint32_t word1; 2476 #define cfg_ft_SHIFT 0 2477 #define cfg_ft_MASK 0x00000001 2478 #define cfg_ft_WORD word1 2479 #define cfg_sli_rev_SHIFT 4 2480 #define cfg_sli_rev_MASK 0x0000000f 2481 #define cfg_sli_rev_WORD word1 2482 #define cfg_sli_family_SHIFT 8 2483 #define cfg_sli_family_MASK 0x0000000f 2484 #define cfg_sli_family_WORD word1 2485 #define cfg_if_type_SHIFT 12 2486 #define cfg_if_type_MASK 0x0000000f 2487 #define cfg_if_type_WORD word1 2488 #define cfg_sli_hint_1_SHIFT 16 2489 #define cfg_sli_hint_1_MASK 0x000000ff 2490 #define cfg_sli_hint_1_WORD word1 2491 #define cfg_sli_hint_2_SHIFT 24 2492 #define cfg_sli_hint_2_MASK 0x0000001f 2493 #define cfg_sli_hint_2_WORD word1 2494 uint32_t word2; 2495 uint32_t word3; 2496 uint32_t word4; 2497 #define cfg_cqv_SHIFT 14 2498 #define cfg_cqv_MASK 0x00000003 2499 #define cfg_cqv_WORD word4 2500 uint32_t word5; 2501 uint32_t word6; 2502 #define cfg_mqv_SHIFT 14 2503 #define cfg_mqv_MASK 0x00000003 2504 #define cfg_mqv_WORD word6 2505 uint32_t word7; 2506 uint32_t word8; 2507 #define cfg_wqv_SHIFT 14 2508 #define cfg_wqv_MASK 0x00000003 2509 #define cfg_wqv_WORD word8 2510 uint32_t word9; 2511 uint32_t word10; 2512 #define cfg_rqv_SHIFT 14 2513 #define cfg_rqv_MASK 0x00000003 2514 #define cfg_rqv_WORD word10 2515 uint32_t word11; 2516 #define cfg_rq_db_window_SHIFT 28 2517 #define cfg_rq_db_window_MASK 0x0000000f 2518 #define cfg_rq_db_window_WORD word11 2519 uint32_t word12; 2520 #define cfg_fcoe_SHIFT 0 2521 #define cfg_fcoe_MASK 0x00000001 2522 #define cfg_fcoe_WORD word12 2523 #define cfg_ext_SHIFT 1 2524 #define cfg_ext_MASK 0x00000001 2525 #define cfg_ext_WORD word12 2526 #define cfg_hdrr_SHIFT 2 2527 #define cfg_hdrr_MASK 0x00000001 2528 #define cfg_hdrr_WORD word12 2529 #define cfg_phwq_SHIFT 15 2530 #define cfg_phwq_MASK 0x00000001 2531 #define cfg_phwq_WORD word12 2532 #define cfg_loopbk_scope_SHIFT 28 2533 #define cfg_loopbk_scope_MASK 0x0000000f 2534 #define cfg_loopbk_scope_WORD word12 2535 uint32_t sge_supp_len; 2536 uint32_t word14; 2537 #define cfg_sgl_page_cnt_SHIFT 0 2538 #define cfg_sgl_page_cnt_MASK 0x0000000f 2539 #define cfg_sgl_page_cnt_WORD word14 2540 #define cfg_sgl_page_size_SHIFT 8 2541 #define cfg_sgl_page_size_MASK 0x000000ff 2542 #define cfg_sgl_page_size_WORD word14 2543 #define cfg_sgl_pp_align_SHIFT 16 2544 #define cfg_sgl_pp_align_MASK 0x000000ff 2545 #define cfg_sgl_pp_align_WORD word14 2546 uint32_t word15; 2547 uint32_t word16; 2548 uint32_t word17; 2549 uint32_t word18; 2550 uint32_t word19; 2551 }; 2552 2553 struct lpfc_mbx_get_sli4_parameters { 2554 struct mbox_header header; 2555 struct lpfc_sli4_parameters sli4_parameters; 2556 }; 2557 2558 struct lpfc_rscr_desc_generic { 2559 #define LPFC_RSRC_DESC_WSIZE 18 2560 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 2561 }; 2562 2563 struct lpfc_rsrc_desc_pcie { 2564 uint32_t word0; 2565 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 2566 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 2567 #define lpfc_rsrc_desc_pcie_type_WORD word0 2568 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 2569 uint32_t word1; 2570 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 2571 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 2572 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 2573 uint32_t reserved; 2574 uint32_t word3; 2575 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 2576 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 2577 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 2578 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 2579 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 2580 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 2581 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 2582 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 2583 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 2584 uint32_t word4; 2585 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 2586 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 2587 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 2588 }; 2589 2590 struct lpfc_rsrc_desc_fcfcoe { 2591 uint32_t word0; 2592 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 2593 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 2594 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 2595 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 2596 uint32_t word1; 2597 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 2598 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 2599 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 2600 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 2601 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 2602 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 2603 uint32_t word2; 2604 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 2605 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 2606 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 2607 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 2608 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 2609 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 2610 uint32_t word3; 2611 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 2612 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 2613 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 2614 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 2615 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 2616 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 2617 uint32_t word4; 2618 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 2619 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 2620 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 2621 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 2622 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 2623 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 2624 uint32_t word5; 2625 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 2626 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 2627 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 2628 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 2629 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 2630 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 2631 uint32_t word6; 2632 uint32_t word7; 2633 uint32_t word8; 2634 uint32_t word9; 2635 uint32_t word10; 2636 uint32_t word11; 2637 uint32_t word12; 2638 uint32_t word13; 2639 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 2640 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 2641 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 2642 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 2643 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 2644 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 2645 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 2646 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 2647 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 2648 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 2649 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 2650 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 2651 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 2652 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 2653 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 2654 }; 2655 2656 struct lpfc_func_cfg { 2657 #define LPFC_RSRC_DESC_MAX_NUM 2 2658 uint32_t rsrc_desc_count; 2659 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2660 }; 2661 2662 struct lpfc_mbx_get_func_cfg { 2663 struct mbox_header header; 2664 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2665 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2666 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2667 struct lpfc_func_cfg func_cfg; 2668 }; 2669 2670 struct lpfc_prof_cfg { 2671 #define LPFC_RSRC_DESC_MAX_NUM 2 2672 uint32_t rsrc_desc_count; 2673 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2674 }; 2675 2676 struct lpfc_mbx_get_prof_cfg { 2677 struct mbox_header header; 2678 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2679 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2680 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2681 union { 2682 struct { 2683 uint32_t word10; 2684 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 2685 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 2686 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 2687 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 2688 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 2689 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 2690 } request; 2691 struct { 2692 struct lpfc_prof_cfg prof_cfg; 2693 } response; 2694 } u; 2695 }; 2696 2697 struct lpfc_controller_attribute { 2698 uint32_t version_string[8]; 2699 uint32_t manufacturer_name[8]; 2700 uint32_t supported_modes; 2701 uint32_t word17; 2702 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 2703 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 2704 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 2705 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 2706 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 2707 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 2708 uint32_t mbx_da_struct_ver; 2709 uint32_t ep_fw_da_struct_ver; 2710 uint32_t ncsi_ver_str[3]; 2711 uint32_t dflt_ext_timeout; 2712 uint32_t model_number[8]; 2713 uint32_t description[16]; 2714 uint32_t serial_number[8]; 2715 uint32_t ip_ver_str[8]; 2716 uint32_t fw_ver_str[8]; 2717 uint32_t bios_ver_str[8]; 2718 uint32_t redboot_ver_str[8]; 2719 uint32_t driver_ver_str[8]; 2720 uint32_t flash_fw_ver_str[8]; 2721 uint32_t functionality; 2722 uint32_t word105; 2723 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 2724 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 2725 #define lpfc_cntl_attr_max_cbd_len_WORD word105 2726 #define lpfc_cntl_attr_asic_rev_SHIFT 16 2727 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 2728 #define lpfc_cntl_attr_asic_rev_WORD word105 2729 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 2730 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 2731 #define lpfc_cntl_attr_gen_guid0_WORD word105 2732 uint32_t gen_guid1_12[3]; 2733 uint32_t word109; 2734 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 2735 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 2736 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 2737 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 2738 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 2739 #define lpfc_cntl_attr_gen_guid15_WORD word109 2740 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 2741 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 2742 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 2743 uint32_t word110; 2744 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 2745 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 2746 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 2747 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 2748 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 2749 #define lpfc_cntl_attr_multi_func_dev_WORD word110 2750 uint32_t word111; 2751 #define lpfc_cntl_attr_cache_valid_SHIFT 0 2752 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 2753 #define lpfc_cntl_attr_cache_valid_WORD word111 2754 #define lpfc_cntl_attr_hba_status_SHIFT 8 2755 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 2756 #define lpfc_cntl_attr_hba_status_WORD word111 2757 #define lpfc_cntl_attr_max_domain_SHIFT 16 2758 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 2759 #define lpfc_cntl_attr_max_domain_WORD word111 2760 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 2761 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 2762 #define lpfc_cntl_attr_lnk_numb_WORD word111 2763 #define lpfc_cntl_attr_lnk_type_SHIFT 30 2764 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 2765 #define lpfc_cntl_attr_lnk_type_WORD word111 2766 uint32_t fw_post_status; 2767 uint32_t hba_mtu[8]; 2768 uint32_t word121; 2769 uint32_t reserved1[3]; 2770 uint32_t word125; 2771 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 2772 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 2773 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 2774 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 2775 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 2776 #define lpfc_cntl_attr_pci_device_id_WORD word125 2777 uint32_t word126; 2778 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 2779 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 2780 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 2781 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 2782 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 2783 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 2784 uint32_t word127; 2785 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 2786 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 2787 #define lpfc_cntl_attr_pci_bus_num_WORD word127 2788 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 2789 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 2790 #define lpfc_cntl_attr_pci_dev_num_WORD word127 2791 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 2792 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 2793 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 2794 #define lpfc_cntl_attr_inf_type_SHIFT 24 2795 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 2796 #define lpfc_cntl_attr_inf_type_WORD word127 2797 uint32_t unique_id[2]; 2798 uint32_t word130; 2799 #define lpfc_cntl_attr_num_netfil_SHIFT 0 2800 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 2801 #define lpfc_cntl_attr_num_netfil_WORD word130 2802 uint32_t reserved2[4]; 2803 }; 2804 2805 struct lpfc_mbx_get_cntl_attributes { 2806 union lpfc_sli4_cfg_shdr cfg_shdr; 2807 struct lpfc_controller_attribute cntl_attr; 2808 }; 2809 2810 struct lpfc_mbx_get_port_name { 2811 struct mbox_header header; 2812 union { 2813 struct { 2814 uint32_t word4; 2815 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 2816 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 2817 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 2818 } request; 2819 struct { 2820 uint32_t word4; 2821 #define lpfc_mbx_get_port_name_name0_SHIFT 0 2822 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 2823 #define lpfc_mbx_get_port_name_name0_WORD word4 2824 #define lpfc_mbx_get_port_name_name1_SHIFT 8 2825 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 2826 #define lpfc_mbx_get_port_name_name1_WORD word4 2827 #define lpfc_mbx_get_port_name_name2_SHIFT 16 2828 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 2829 #define lpfc_mbx_get_port_name_name2_WORD word4 2830 #define lpfc_mbx_get_port_name_name3_SHIFT 24 2831 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 2832 #define lpfc_mbx_get_port_name_name3_WORD word4 2833 #define LPFC_LINK_NUMBER_0 0 2834 #define LPFC_LINK_NUMBER_1 1 2835 #define LPFC_LINK_NUMBER_2 2 2836 #define LPFC_LINK_NUMBER_3 3 2837 } response; 2838 } u; 2839 }; 2840 2841 /* Mailbox Completion Queue Error Messages */ 2842 #define MB_CQE_STATUS_SUCCESS 0x0 2843 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 2844 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 2845 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 2846 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 2847 #define MB_CQE_STATUS_DMA_FAILED 0x5 2848 2849 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8 2850 struct lpfc_mbx_wr_object { 2851 struct mbox_header header; 2852 union { 2853 struct { 2854 uint32_t word4; 2855 #define lpfc_wr_object_eof_SHIFT 31 2856 #define lpfc_wr_object_eof_MASK 0x00000001 2857 #define lpfc_wr_object_eof_WORD word4 2858 #define lpfc_wr_object_write_length_SHIFT 0 2859 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 2860 #define lpfc_wr_object_write_length_WORD word4 2861 uint32_t write_offset; 2862 uint32_t object_name[26]; 2863 uint32_t bde_count; 2864 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 2865 } request; 2866 struct { 2867 uint32_t actual_write_length; 2868 } response; 2869 } u; 2870 }; 2871 2872 /* mailbox queue entry structure */ 2873 struct lpfc_mqe { 2874 uint32_t word0; 2875 #define lpfc_mqe_status_SHIFT 16 2876 #define lpfc_mqe_status_MASK 0x0000FFFF 2877 #define lpfc_mqe_status_WORD word0 2878 #define lpfc_mqe_command_SHIFT 8 2879 #define lpfc_mqe_command_MASK 0x000000FF 2880 #define lpfc_mqe_command_WORD word0 2881 union { 2882 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 2883 /* sli4 mailbox commands */ 2884 struct lpfc_mbx_sli4_config sli4_config; 2885 struct lpfc_mbx_init_vfi init_vfi; 2886 struct lpfc_mbx_reg_vfi reg_vfi; 2887 struct lpfc_mbx_reg_vfi unreg_vfi; 2888 struct lpfc_mbx_init_vpi init_vpi; 2889 struct lpfc_mbx_resume_rpi resume_rpi; 2890 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 2891 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 2892 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 2893 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 2894 struct lpfc_mbx_reg_fcfi reg_fcfi; 2895 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 2896 struct lpfc_mbx_mq_create mq_create; 2897 struct lpfc_mbx_mq_create_ext mq_create_ext; 2898 struct lpfc_mbx_eq_create eq_create; 2899 struct lpfc_mbx_modify_eq_delay eq_delay; 2900 struct lpfc_mbx_cq_create cq_create; 2901 struct lpfc_mbx_wq_create wq_create; 2902 struct lpfc_mbx_rq_create rq_create; 2903 struct lpfc_mbx_mq_destroy mq_destroy; 2904 struct lpfc_mbx_eq_destroy eq_destroy; 2905 struct lpfc_mbx_cq_destroy cq_destroy; 2906 struct lpfc_mbx_wq_destroy wq_destroy; 2907 struct lpfc_mbx_rq_destroy rq_destroy; 2908 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 2909 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 2910 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 2911 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 2912 struct lpfc_mbx_nembed_cmd nembed_cmd; 2913 struct lpfc_mbx_read_rev read_rev; 2914 struct lpfc_mbx_read_vpi read_vpi; 2915 struct lpfc_mbx_read_config rd_config; 2916 struct lpfc_mbx_request_features req_ftrs; 2917 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 2918 struct lpfc_mbx_query_fw_cfg query_fw_cfg; 2919 struct lpfc_mbx_supp_pages supp_pages; 2920 struct lpfc_mbx_pc_sli4_params sli4_params; 2921 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 2922 struct lpfc_mbx_set_link_diag_state link_diag_state; 2923 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 2924 struct lpfc_mbx_run_link_diag_test link_diag_test; 2925 struct lpfc_mbx_get_func_cfg get_func_cfg; 2926 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 2927 struct lpfc_mbx_wr_object wr_object; 2928 struct lpfc_mbx_get_port_name get_port_name; 2929 struct lpfc_mbx_nop nop; 2930 } un; 2931 }; 2932 2933 struct lpfc_mcqe { 2934 uint32_t word0; 2935 #define lpfc_mcqe_status_SHIFT 0 2936 #define lpfc_mcqe_status_MASK 0x0000FFFF 2937 #define lpfc_mcqe_status_WORD word0 2938 #define lpfc_mcqe_ext_status_SHIFT 16 2939 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 2940 #define lpfc_mcqe_ext_status_WORD word0 2941 uint32_t mcqe_tag0; 2942 uint32_t mcqe_tag1; 2943 uint32_t trailer; 2944 #define lpfc_trailer_valid_SHIFT 31 2945 #define lpfc_trailer_valid_MASK 0x00000001 2946 #define lpfc_trailer_valid_WORD trailer 2947 #define lpfc_trailer_async_SHIFT 30 2948 #define lpfc_trailer_async_MASK 0x00000001 2949 #define lpfc_trailer_async_WORD trailer 2950 #define lpfc_trailer_hpi_SHIFT 29 2951 #define lpfc_trailer_hpi_MASK 0x00000001 2952 #define lpfc_trailer_hpi_WORD trailer 2953 #define lpfc_trailer_completed_SHIFT 28 2954 #define lpfc_trailer_completed_MASK 0x00000001 2955 #define lpfc_trailer_completed_WORD trailer 2956 #define lpfc_trailer_consumed_SHIFT 27 2957 #define lpfc_trailer_consumed_MASK 0x00000001 2958 #define lpfc_trailer_consumed_WORD trailer 2959 #define lpfc_trailer_type_SHIFT 16 2960 #define lpfc_trailer_type_MASK 0x000000FF 2961 #define lpfc_trailer_type_WORD trailer 2962 #define lpfc_trailer_code_SHIFT 8 2963 #define lpfc_trailer_code_MASK 0x000000FF 2964 #define lpfc_trailer_code_WORD trailer 2965 #define LPFC_TRAILER_CODE_LINK 0x1 2966 #define LPFC_TRAILER_CODE_FCOE 0x2 2967 #define LPFC_TRAILER_CODE_DCBX 0x3 2968 #define LPFC_TRAILER_CODE_GRP5 0x5 2969 #define LPFC_TRAILER_CODE_FC 0x10 2970 #define LPFC_TRAILER_CODE_SLI 0x11 2971 }; 2972 2973 struct lpfc_acqe_link { 2974 uint32_t word0; 2975 #define lpfc_acqe_link_speed_SHIFT 24 2976 #define lpfc_acqe_link_speed_MASK 0x000000FF 2977 #define lpfc_acqe_link_speed_WORD word0 2978 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 2979 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 2980 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 2981 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 2982 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 2983 #define lpfc_acqe_link_duplex_SHIFT 16 2984 #define lpfc_acqe_link_duplex_MASK 0x000000FF 2985 #define lpfc_acqe_link_duplex_WORD word0 2986 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 2987 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 2988 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 2989 #define lpfc_acqe_link_status_SHIFT 8 2990 #define lpfc_acqe_link_status_MASK 0x000000FF 2991 #define lpfc_acqe_link_status_WORD word0 2992 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 2993 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 2994 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 2995 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 2996 #define lpfc_acqe_link_type_SHIFT 6 2997 #define lpfc_acqe_link_type_MASK 0x00000003 2998 #define lpfc_acqe_link_type_WORD word0 2999 #define lpfc_acqe_link_number_SHIFT 0 3000 #define lpfc_acqe_link_number_MASK 0x0000003F 3001 #define lpfc_acqe_link_number_WORD word0 3002 uint32_t word1; 3003 #define lpfc_acqe_link_fault_SHIFT 0 3004 #define lpfc_acqe_link_fault_MASK 0x000000FF 3005 #define lpfc_acqe_link_fault_WORD word1 3006 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3007 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3008 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3009 #define lpfc_acqe_logical_link_speed_SHIFT 16 3010 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 3011 #define lpfc_acqe_logical_link_speed_WORD word1 3012 uint32_t event_tag; 3013 uint32_t trailer; 3014 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 3015 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 3016 }; 3017 3018 struct lpfc_acqe_fip { 3019 uint32_t index; 3020 uint32_t word1; 3021 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3022 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3023 #define lpfc_acqe_fip_fcf_count_WORD word1 3024 #define lpfc_acqe_fip_event_type_SHIFT 16 3025 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3026 #define lpfc_acqe_fip_event_type_WORD word1 3027 uint32_t event_tag; 3028 uint32_t trailer; 3029 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3030 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3031 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3032 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3033 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3034 }; 3035 3036 struct lpfc_acqe_dcbx { 3037 uint32_t tlv_ttl; 3038 uint32_t reserved; 3039 uint32_t event_tag; 3040 uint32_t trailer; 3041 }; 3042 3043 struct lpfc_acqe_grp5 { 3044 uint32_t word0; 3045 #define lpfc_acqe_grp5_type_SHIFT 6 3046 #define lpfc_acqe_grp5_type_MASK 0x00000003 3047 #define lpfc_acqe_grp5_type_WORD word0 3048 #define lpfc_acqe_grp5_number_SHIFT 0 3049 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3050 #define lpfc_acqe_grp5_number_WORD word0 3051 uint32_t word1; 3052 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3053 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3054 #define lpfc_acqe_grp5_llink_spd_WORD word1 3055 uint32_t event_tag; 3056 uint32_t trailer; 3057 }; 3058 3059 struct lpfc_acqe_fc_la { 3060 uint32_t word0; 3061 #define lpfc_acqe_fc_la_speed_SHIFT 24 3062 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3063 #define lpfc_acqe_fc_la_speed_WORD word0 3064 #define LPFC_FC_LA_SPEED_UNKOWN 0x0 3065 #define LPFC_FC_LA_SPEED_1G 0x1 3066 #define LPFC_FC_LA_SPEED_2G 0x2 3067 #define LPFC_FC_LA_SPEED_4G 0x4 3068 #define LPFC_FC_LA_SPEED_8G 0x8 3069 #define LPFC_FC_LA_SPEED_10G 0xA 3070 #define LPFC_FC_LA_SPEED_16G 0x10 3071 #define lpfc_acqe_fc_la_topology_SHIFT 16 3072 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 3073 #define lpfc_acqe_fc_la_topology_WORD word0 3074 #define LPFC_FC_LA_TOP_UNKOWN 0x0 3075 #define LPFC_FC_LA_TOP_P2P 0x1 3076 #define LPFC_FC_LA_TOP_FCAL 0x2 3077 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 3078 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 3079 #define lpfc_acqe_fc_la_att_type_SHIFT 8 3080 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 3081 #define lpfc_acqe_fc_la_att_type_WORD word0 3082 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 3083 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 3084 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 3085 #define lpfc_acqe_fc_la_port_type_SHIFT 6 3086 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 3087 #define lpfc_acqe_fc_la_port_type_WORD word0 3088 #define LPFC_LINK_TYPE_ETHERNET 0x0 3089 #define LPFC_LINK_TYPE_FC 0x1 3090 #define lpfc_acqe_fc_la_port_number_SHIFT 0 3091 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 3092 #define lpfc_acqe_fc_la_port_number_WORD word0 3093 uint32_t word1; 3094 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 3095 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 3096 #define lpfc_acqe_fc_la_llink_spd_WORD word1 3097 #define lpfc_acqe_fc_la_fault_SHIFT 0 3098 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 3099 #define lpfc_acqe_fc_la_fault_WORD word1 3100 #define LPFC_FC_LA_FAULT_NONE 0x0 3101 #define LPFC_FC_LA_FAULT_LOCAL 0x1 3102 #define LPFC_FC_LA_FAULT_REMOTE 0x2 3103 uint32_t event_tag; 3104 uint32_t trailer; 3105 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 3106 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 3107 }; 3108 3109 struct lpfc_acqe_misconfigured_event { 3110 struct { 3111 uint32_t word0; 3112 #define lpfc_sli_misconfigured_port0_SHIFT 0 3113 #define lpfc_sli_misconfigured_port0_MASK 0x000000FF 3114 #define lpfc_sli_misconfigured_port0_WORD word0 3115 #define lpfc_sli_misconfigured_port1_SHIFT 8 3116 #define lpfc_sli_misconfigured_port1_MASK 0x000000FF 3117 #define lpfc_sli_misconfigured_port1_WORD word0 3118 #define lpfc_sli_misconfigured_port2_SHIFT 16 3119 #define lpfc_sli_misconfigured_port2_MASK 0x000000FF 3120 #define lpfc_sli_misconfigured_port2_WORD word0 3121 #define lpfc_sli_misconfigured_port3_SHIFT 24 3122 #define lpfc_sli_misconfigured_port3_MASK 0x000000FF 3123 #define lpfc_sli_misconfigured_port3_WORD word0 3124 } theEvent; 3125 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 3126 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 3127 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 3128 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 3129 }; 3130 3131 struct lpfc_acqe_sli { 3132 uint32_t event_data1; 3133 uint32_t event_data2; 3134 uint32_t reserved; 3135 uint32_t trailer; 3136 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 3137 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 3138 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 3139 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 3140 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 3141 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 3142 }; 3143 3144 /* 3145 * Define the bootstrap mailbox (bmbx) region used to communicate 3146 * mailbox command between the host and port. The mailbox consists 3147 * of a payload area of 256 bytes and a completion queue of length 3148 * 16 bytes. 3149 */ 3150 struct lpfc_bmbx_create { 3151 struct lpfc_mqe mqe; 3152 struct lpfc_mcqe mcqe; 3153 }; 3154 3155 #define SGL_ALIGN_SZ 64 3156 #define SGL_PAGE_SIZE 4096 3157 /* align SGL addr on a size boundary - adjust address up */ 3158 #define NO_XRI 0xffff 3159 3160 struct wqe_common { 3161 uint32_t word6; 3162 #define wqe_xri_tag_SHIFT 0 3163 #define wqe_xri_tag_MASK 0x0000FFFF 3164 #define wqe_xri_tag_WORD word6 3165 #define wqe_ctxt_tag_SHIFT 16 3166 #define wqe_ctxt_tag_MASK 0x0000FFFF 3167 #define wqe_ctxt_tag_WORD word6 3168 uint32_t word7; 3169 #define wqe_dif_SHIFT 0 3170 #define wqe_dif_MASK 0x00000003 3171 #define wqe_dif_WORD word7 3172 #define wqe_ct_SHIFT 2 3173 #define wqe_ct_MASK 0x00000003 3174 #define wqe_ct_WORD word7 3175 #define wqe_status_SHIFT 4 3176 #define wqe_status_MASK 0x0000000f 3177 #define wqe_status_WORD word7 3178 #define wqe_cmnd_SHIFT 8 3179 #define wqe_cmnd_MASK 0x000000ff 3180 #define wqe_cmnd_WORD word7 3181 #define wqe_class_SHIFT 16 3182 #define wqe_class_MASK 0x00000007 3183 #define wqe_class_WORD word7 3184 #define wqe_ar_SHIFT 19 3185 #define wqe_ar_MASK 0x00000001 3186 #define wqe_ar_WORD word7 3187 #define wqe_ag_SHIFT wqe_ar_SHIFT 3188 #define wqe_ag_MASK wqe_ar_MASK 3189 #define wqe_ag_WORD wqe_ar_WORD 3190 #define wqe_pu_SHIFT 20 3191 #define wqe_pu_MASK 0x00000003 3192 #define wqe_pu_WORD word7 3193 #define wqe_erp_SHIFT 22 3194 #define wqe_erp_MASK 0x00000001 3195 #define wqe_erp_WORD word7 3196 #define wqe_conf_SHIFT wqe_erp_SHIFT 3197 #define wqe_conf_MASK wqe_erp_MASK 3198 #define wqe_conf_WORD wqe_erp_WORD 3199 #define wqe_lnk_SHIFT 23 3200 #define wqe_lnk_MASK 0x00000001 3201 #define wqe_lnk_WORD word7 3202 #define wqe_tmo_SHIFT 24 3203 #define wqe_tmo_MASK 0x000000ff 3204 #define wqe_tmo_WORD word7 3205 uint32_t abort_tag; /* word 8 in WQE */ 3206 uint32_t word9; 3207 #define wqe_reqtag_SHIFT 0 3208 #define wqe_reqtag_MASK 0x0000FFFF 3209 #define wqe_reqtag_WORD word9 3210 #define wqe_temp_rpi_SHIFT 16 3211 #define wqe_temp_rpi_MASK 0x0000FFFF 3212 #define wqe_temp_rpi_WORD word9 3213 #define wqe_rcvoxid_SHIFT 16 3214 #define wqe_rcvoxid_MASK 0x0000FFFF 3215 #define wqe_rcvoxid_WORD word9 3216 uint32_t word10; 3217 #define wqe_ebde_cnt_SHIFT 0 3218 #define wqe_ebde_cnt_MASK 0x0000000f 3219 #define wqe_ebde_cnt_WORD word10 3220 #define wqe_lenloc_SHIFT 7 3221 #define wqe_lenloc_MASK 0x00000003 3222 #define wqe_lenloc_WORD word10 3223 #define LPFC_WQE_LENLOC_NONE 0 3224 #define LPFC_WQE_LENLOC_WORD3 1 3225 #define LPFC_WQE_LENLOC_WORD12 2 3226 #define LPFC_WQE_LENLOC_WORD4 3 3227 #define wqe_qosd_SHIFT 9 3228 #define wqe_qosd_MASK 0x00000001 3229 #define wqe_qosd_WORD word10 3230 #define wqe_xbl_SHIFT 11 3231 #define wqe_xbl_MASK 0x00000001 3232 #define wqe_xbl_WORD word10 3233 #define wqe_iod_SHIFT 13 3234 #define wqe_iod_MASK 0x00000001 3235 #define wqe_iod_WORD word10 3236 #define LPFC_WQE_IOD_WRITE 0 3237 #define LPFC_WQE_IOD_READ 1 3238 #define wqe_dbde_SHIFT 14 3239 #define wqe_dbde_MASK 0x00000001 3240 #define wqe_dbde_WORD word10 3241 #define wqe_wqes_SHIFT 15 3242 #define wqe_wqes_MASK 0x00000001 3243 #define wqe_wqes_WORD word10 3244 /* Note that this field overlaps above fields */ 3245 #define wqe_wqid_SHIFT 1 3246 #define wqe_wqid_MASK 0x00007fff 3247 #define wqe_wqid_WORD word10 3248 #define wqe_pri_SHIFT 16 3249 #define wqe_pri_MASK 0x00000007 3250 #define wqe_pri_WORD word10 3251 #define wqe_pv_SHIFT 19 3252 #define wqe_pv_MASK 0x00000001 3253 #define wqe_pv_WORD word10 3254 #define wqe_xc_SHIFT 21 3255 #define wqe_xc_MASK 0x00000001 3256 #define wqe_xc_WORD word10 3257 #define wqe_sr_SHIFT 22 3258 #define wqe_sr_MASK 0x00000001 3259 #define wqe_sr_WORD word10 3260 #define wqe_ccpe_SHIFT 23 3261 #define wqe_ccpe_MASK 0x00000001 3262 #define wqe_ccpe_WORD word10 3263 #define wqe_ccp_SHIFT 24 3264 #define wqe_ccp_MASK 0x000000ff 3265 #define wqe_ccp_WORD word10 3266 uint32_t word11; 3267 #define wqe_cmd_type_SHIFT 0 3268 #define wqe_cmd_type_MASK 0x0000000f 3269 #define wqe_cmd_type_WORD word11 3270 #define wqe_els_id_SHIFT 4 3271 #define wqe_els_id_MASK 0x00000003 3272 #define wqe_els_id_WORD word11 3273 #define LPFC_ELS_ID_FLOGI 3 3274 #define LPFC_ELS_ID_FDISC 2 3275 #define LPFC_ELS_ID_LOGO 1 3276 #define LPFC_ELS_ID_DEFAULT 0 3277 #define wqe_wqec_SHIFT 7 3278 #define wqe_wqec_MASK 0x00000001 3279 #define wqe_wqec_WORD word11 3280 #define wqe_cqid_SHIFT 16 3281 #define wqe_cqid_MASK 0x0000ffff 3282 #define wqe_cqid_WORD word11 3283 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 3284 }; 3285 3286 struct wqe_did { 3287 uint32_t word5; 3288 #define wqe_els_did_SHIFT 0 3289 #define wqe_els_did_MASK 0x00FFFFFF 3290 #define wqe_els_did_WORD word5 3291 #define wqe_xmit_bls_pt_SHIFT 28 3292 #define wqe_xmit_bls_pt_MASK 0x00000003 3293 #define wqe_xmit_bls_pt_WORD word5 3294 #define wqe_xmit_bls_ar_SHIFT 30 3295 #define wqe_xmit_bls_ar_MASK 0x00000001 3296 #define wqe_xmit_bls_ar_WORD word5 3297 #define wqe_xmit_bls_xo_SHIFT 31 3298 #define wqe_xmit_bls_xo_MASK 0x00000001 3299 #define wqe_xmit_bls_xo_WORD word5 3300 }; 3301 3302 struct lpfc_wqe_generic{ 3303 struct ulp_bde64 bde; 3304 uint32_t word3; 3305 uint32_t word4; 3306 uint32_t word5; 3307 struct wqe_common wqe_com; 3308 uint32_t payload[4]; 3309 }; 3310 3311 struct els_request64_wqe { 3312 struct ulp_bde64 bde; 3313 uint32_t payload_len; 3314 uint32_t word4; 3315 #define els_req64_sid_SHIFT 0 3316 #define els_req64_sid_MASK 0x00FFFFFF 3317 #define els_req64_sid_WORD word4 3318 #define els_req64_sp_SHIFT 24 3319 #define els_req64_sp_MASK 0x00000001 3320 #define els_req64_sp_WORD word4 3321 #define els_req64_vf_SHIFT 25 3322 #define els_req64_vf_MASK 0x00000001 3323 #define els_req64_vf_WORD word4 3324 struct wqe_did wqe_dest; 3325 struct wqe_common wqe_com; /* words 6-11 */ 3326 uint32_t word12; 3327 #define els_req64_vfid_SHIFT 1 3328 #define els_req64_vfid_MASK 0x00000FFF 3329 #define els_req64_vfid_WORD word12 3330 #define els_req64_pri_SHIFT 13 3331 #define els_req64_pri_MASK 0x00000007 3332 #define els_req64_pri_WORD word12 3333 uint32_t word13; 3334 #define els_req64_hopcnt_SHIFT 24 3335 #define els_req64_hopcnt_MASK 0x000000ff 3336 #define els_req64_hopcnt_WORD word13 3337 uint32_t reserved[2]; 3338 }; 3339 3340 struct xmit_els_rsp64_wqe { 3341 struct ulp_bde64 bde; 3342 uint32_t response_payload_len; 3343 uint32_t word4; 3344 #define els_rsp64_sid_SHIFT 0 3345 #define els_rsp64_sid_MASK 0x00FFFFFF 3346 #define els_rsp64_sid_WORD word4 3347 #define els_rsp64_sp_SHIFT 24 3348 #define els_rsp64_sp_MASK 0x00000001 3349 #define els_rsp64_sp_WORD word4 3350 struct wqe_did wqe_dest; 3351 struct wqe_common wqe_com; /* words 6-11 */ 3352 uint32_t word12; 3353 #define wqe_rsp_temp_rpi_SHIFT 0 3354 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 3355 #define wqe_rsp_temp_rpi_WORD word12 3356 uint32_t rsvd_13_15[3]; 3357 }; 3358 3359 struct xmit_bls_rsp64_wqe { 3360 uint32_t payload0; 3361 /* Payload0 for BA_ACC */ 3362 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 3363 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 3364 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 3365 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 3366 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 3367 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 3368 /* Payload0 for BA_RJT */ 3369 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 3370 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 3371 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 3372 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 3373 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 3374 #define xmit_bls_rsp64_rjt_expc_WORD payload0 3375 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 3376 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 3377 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 3378 uint32_t word1; 3379 #define xmit_bls_rsp64_rxid_SHIFT 0 3380 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 3381 #define xmit_bls_rsp64_rxid_WORD word1 3382 #define xmit_bls_rsp64_oxid_SHIFT 16 3383 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 3384 #define xmit_bls_rsp64_oxid_WORD word1 3385 uint32_t word2; 3386 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 3387 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 3388 #define xmit_bls_rsp64_seqcnthi_WORD word2 3389 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 3390 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 3391 #define xmit_bls_rsp64_seqcntlo_WORD word2 3392 uint32_t rsrvd3; 3393 uint32_t rsrvd4; 3394 struct wqe_did wqe_dest; 3395 struct wqe_common wqe_com; /* words 6-11 */ 3396 uint32_t word12; 3397 #define xmit_bls_rsp64_temprpi_SHIFT 0 3398 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 3399 #define xmit_bls_rsp64_temprpi_WORD word12 3400 uint32_t rsvd_13_15[3]; 3401 }; 3402 3403 struct wqe_rctl_dfctl { 3404 uint32_t word5; 3405 #define wqe_si_SHIFT 2 3406 #define wqe_si_MASK 0x000000001 3407 #define wqe_si_WORD word5 3408 #define wqe_la_SHIFT 3 3409 #define wqe_la_MASK 0x000000001 3410 #define wqe_la_WORD word5 3411 #define wqe_xo_SHIFT 6 3412 #define wqe_xo_MASK 0x000000001 3413 #define wqe_xo_WORD word5 3414 #define wqe_ls_SHIFT 7 3415 #define wqe_ls_MASK 0x000000001 3416 #define wqe_ls_WORD word5 3417 #define wqe_dfctl_SHIFT 8 3418 #define wqe_dfctl_MASK 0x0000000ff 3419 #define wqe_dfctl_WORD word5 3420 #define wqe_type_SHIFT 16 3421 #define wqe_type_MASK 0x0000000ff 3422 #define wqe_type_WORD word5 3423 #define wqe_rctl_SHIFT 24 3424 #define wqe_rctl_MASK 0x0000000ff 3425 #define wqe_rctl_WORD word5 3426 }; 3427 3428 struct xmit_seq64_wqe { 3429 struct ulp_bde64 bde; 3430 uint32_t rsvd3; 3431 uint32_t relative_offset; 3432 struct wqe_rctl_dfctl wge_ctl; 3433 struct wqe_common wqe_com; /* words 6-11 */ 3434 uint32_t xmit_len; 3435 uint32_t rsvd_12_15[3]; 3436 }; 3437 struct xmit_bcast64_wqe { 3438 struct ulp_bde64 bde; 3439 uint32_t seq_payload_len; 3440 uint32_t rsvd4; 3441 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3442 struct wqe_common wqe_com; /* words 6-11 */ 3443 uint32_t rsvd_12_15[4]; 3444 }; 3445 3446 struct gen_req64_wqe { 3447 struct ulp_bde64 bde; 3448 uint32_t request_payload_len; 3449 uint32_t relative_offset; 3450 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3451 struct wqe_common wqe_com; /* words 6-11 */ 3452 uint32_t rsvd_12_15[4]; 3453 }; 3454 3455 struct create_xri_wqe { 3456 uint32_t rsrvd[5]; /* words 0-4 */ 3457 struct wqe_did wqe_dest; /* word 5 */ 3458 struct wqe_common wqe_com; /* words 6-11 */ 3459 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3460 }; 3461 3462 #define T_REQUEST_TAG 3 3463 #define T_XRI_TAG 1 3464 3465 struct abort_cmd_wqe { 3466 uint32_t rsrvd[3]; 3467 uint32_t word3; 3468 #define abort_cmd_ia_SHIFT 0 3469 #define abort_cmd_ia_MASK 0x000000001 3470 #define abort_cmd_ia_WORD word3 3471 #define abort_cmd_criteria_SHIFT 8 3472 #define abort_cmd_criteria_MASK 0x0000000ff 3473 #define abort_cmd_criteria_WORD word3 3474 uint32_t rsrvd4; 3475 uint32_t rsrvd5; 3476 struct wqe_common wqe_com; /* words 6-11 */ 3477 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3478 }; 3479 3480 struct fcp_iwrite64_wqe { 3481 struct ulp_bde64 bde; 3482 uint32_t payload_offset_len; 3483 uint32_t total_xfer_len; 3484 uint32_t initial_xfer_len; 3485 struct wqe_common wqe_com; /* words 6-11 */ 3486 uint32_t rsrvd12; 3487 struct ulp_bde64 ph_bde; /* words 13-15 */ 3488 }; 3489 3490 struct fcp_iread64_wqe { 3491 struct ulp_bde64 bde; 3492 uint32_t payload_offset_len; /* word 3 */ 3493 uint32_t total_xfer_len; /* word 4 */ 3494 uint32_t rsrvd5; /* word 5 */ 3495 struct wqe_common wqe_com; /* words 6-11 */ 3496 uint32_t rsrvd12; 3497 struct ulp_bde64 ph_bde; /* words 13-15 */ 3498 }; 3499 3500 struct fcp_icmnd64_wqe { 3501 struct ulp_bde64 bde; /* words 0-2 */ 3502 uint32_t rsrvd3; /* word 3 */ 3503 uint32_t rsrvd4; /* word 4 */ 3504 uint32_t rsrvd5; /* word 5 */ 3505 struct wqe_common wqe_com; /* words 6-11 */ 3506 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3507 }; 3508 3509 3510 union lpfc_wqe { 3511 uint32_t words[16]; 3512 struct lpfc_wqe_generic generic; 3513 struct fcp_icmnd64_wqe fcp_icmd; 3514 struct fcp_iread64_wqe fcp_iread; 3515 struct fcp_iwrite64_wqe fcp_iwrite; 3516 struct abort_cmd_wqe abort_cmd; 3517 struct create_xri_wqe create_xri; 3518 struct xmit_bcast64_wqe xmit_bcast64; 3519 struct xmit_seq64_wqe xmit_sequence; 3520 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 3521 struct xmit_els_rsp64_wqe xmit_els_rsp; 3522 struct els_request64_wqe els_req; 3523 struct gen_req64_wqe gen_req; 3524 }; 3525 3526 #define LPFC_GROUP_OJECT_MAGIC_NUM 0xfeaa0001 3527 #define LPFC_FILE_TYPE_GROUP 0xf7 3528 #define LPFC_FILE_ID_GROUP 0xa2 3529 struct lpfc_grp_hdr { 3530 uint32_t size; 3531 uint32_t magic_number; 3532 uint32_t word2; 3533 #define lpfc_grp_hdr_file_type_SHIFT 24 3534 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 3535 #define lpfc_grp_hdr_file_type_WORD word2 3536 #define lpfc_grp_hdr_id_SHIFT 16 3537 #define lpfc_grp_hdr_id_MASK 0x000000FF 3538 #define lpfc_grp_hdr_id_WORD word2 3539 uint8_t rev_name[128]; 3540 uint8_t date[12]; 3541 uint8_t revision[32]; 3542 }; 3543 3544 #define FCP_COMMAND 0x0 3545 #define FCP_COMMAND_DATA_OUT 0x1 3546 #define ELS_COMMAND_NON_FIP 0xC 3547 #define ELS_COMMAND_FIP 0xD 3548 #define OTHER_COMMAND 0x8 3549 3550 #define LPFC_FW_DUMP 1 3551 #define LPFC_FW_RESET 2 3552 #define LPFC_DV_RESET 3 3553