1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #include <uapi/scsi/fc/fc_fs.h> 24 #include <uapi/scsi/fc/fc_els.h> 25 26 /* Macros to deal with bit fields. Each bit field must have 3 #defines 27 * associated with it (_SHIFT, _MASK, and _WORD). 28 * EG. For a bit field that is in the 7th bit of the "field4" field of a 29 * structure and is 2 bits in size the following #defines must exist: 30 * struct temp { 31 * uint32_t field1; 32 * uint32_t field2; 33 * uint32_t field3; 34 * uint32_t field4; 35 * #define example_bit_field_SHIFT 7 36 * #define example_bit_field_MASK 0x03 37 * #define example_bit_field_WORD field4 38 * uint32_t field5; 39 * }; 40 * Then the macros below may be used to get or set the value of that field. 41 * EG. To get the value of the bit field from the above example: 42 * struct temp t1; 43 * value = bf_get(example_bit_field, &t1); 44 * And then to set that bit field: 45 * bf_set(example_bit_field, &t1, 2); 46 * Or clear that bit field: 47 * bf_set(example_bit_field, &t1, 0); 48 */ 49 #define bf_get_be32(name, ptr) \ 50 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 51 #define bf_get_le32(name, ptr) \ 52 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 53 #define bf_get(name, ptr) \ 54 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 55 #define bf_set_le32(name, ptr, value) \ 56 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 57 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 58 ~(name##_MASK << name##_SHIFT))))) 59 #define bf_set(name, ptr, value) \ 60 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 61 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 62 63 #define get_wqe_reqtag(x) (((x)->wqe.words[9] >> 0) & 0xFFFF) 64 #define get_wqe_tmo(x) (((x)->wqe.words[7] >> 24) & 0x00FF) 65 66 #define get_job_ulpword(x, y) ((x)->iocb.un.ulpWord[y]) 67 68 #define set_job_ulpstatus(x, y) bf_set(lpfc_wcqe_c_status, &(x)->wcqe_cmpl, y) 69 #define set_job_ulpword4(x, y) ((&(x)->wcqe_cmpl)->parameter = y) 70 71 struct dma_address { 72 uint32_t addr_lo; 73 uint32_t addr_hi; 74 }; 75 76 struct lpfc_sli_intf { 77 uint32_t word0; 78 #define lpfc_sli_intf_valid_SHIFT 29 79 #define lpfc_sli_intf_valid_MASK 0x00000007 80 #define lpfc_sli_intf_valid_WORD word0 81 #define LPFC_SLI_INTF_VALID 6 82 #define lpfc_sli_intf_sli_hint2_SHIFT 24 83 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 84 #define lpfc_sli_intf_sli_hint2_WORD word0 85 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 86 #define lpfc_sli_intf_sli_hint1_SHIFT 16 87 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 88 #define lpfc_sli_intf_sli_hint1_WORD word0 89 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 90 #define LPFC_SLI_INTF_SLI_HINT1_1 1 91 #define LPFC_SLI_INTF_SLI_HINT1_2 2 92 #define lpfc_sli_intf_if_type_SHIFT 12 93 #define lpfc_sli_intf_if_type_MASK 0x0000000F 94 #define lpfc_sli_intf_if_type_WORD word0 95 #define LPFC_SLI_INTF_IF_TYPE_0 0 96 #define LPFC_SLI_INTF_IF_TYPE_1 1 97 #define LPFC_SLI_INTF_IF_TYPE_2 2 98 #define LPFC_SLI_INTF_IF_TYPE_6 6 99 #define lpfc_sli_intf_sli_family_SHIFT 8 100 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 101 #define lpfc_sli_intf_sli_family_WORD word0 102 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 103 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 104 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 105 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 106 #define LPFC_SLI_INTF_FAMILY_G6 0xc 107 #define LPFC_SLI_INTF_FAMILY_G7 0xd 108 #define LPFC_SLI_INTF_FAMILY_G7P 0xe 109 #define lpfc_sli_intf_slirev_SHIFT 4 110 #define lpfc_sli_intf_slirev_MASK 0x0000000F 111 #define lpfc_sli_intf_slirev_WORD word0 112 #define LPFC_SLI_INTF_REV_SLI3 3 113 #define LPFC_SLI_INTF_REV_SLI4 4 114 #define lpfc_sli_intf_func_type_SHIFT 0 115 #define lpfc_sli_intf_func_type_MASK 0x00000001 116 #define lpfc_sli_intf_func_type_WORD word0 117 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 118 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 119 }; 120 121 #define LPFC_SLI4_MBX_EMBED true 122 #define LPFC_SLI4_MBX_NEMBED false 123 124 #define LPFC_SLI4_MB_WORD_COUNT 64 125 #define LPFC_MAX_MQ_PAGE 8 126 #define LPFC_MAX_WQ_PAGE_V0 4 127 #define LPFC_MAX_WQ_PAGE 8 128 #define LPFC_MAX_RQ_PAGE 8 129 #define LPFC_MAX_CQ_PAGE 4 130 #define LPFC_MAX_EQ_PAGE 8 131 132 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 133 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 134 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 135 136 /* Define SLI4 Alignment requirements. */ 137 #define LPFC_ALIGN_16_BYTE 16 138 #define LPFC_ALIGN_64_BYTE 64 139 #define SLI4_PAGE_SIZE 4096 140 141 /* Define SLI4 specific definitions. */ 142 #define LPFC_MQ_CQE_BYTE_OFFSET 256 143 #define LPFC_MBX_CMD_HDR_LENGTH 16 144 #define LPFC_MBX_ERROR_RANGE 0x4000 145 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 146 #define LPFC_BMBX_BIT1_ADDR_LO 0 147 #define LPFC_RPI_HDR_COUNT 64 148 #define LPFC_HDR_TEMPLATE_SIZE 4096 149 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 150 #define LPFC_FCF_RECORD_WD_CNT 132 151 #define LPFC_ENTIRE_FCF_DATABASE 0 152 #define LPFC_DFLT_FCF_INDEX 0 153 154 /* Virtual function numbers */ 155 #define LPFC_VF0 0 156 #define LPFC_VF1 1 157 #define LPFC_VF2 2 158 #define LPFC_VF3 3 159 #define LPFC_VF4 4 160 #define LPFC_VF5 5 161 #define LPFC_VF6 6 162 #define LPFC_VF7 7 163 #define LPFC_VF8 8 164 #define LPFC_VF9 9 165 #define LPFC_VF10 10 166 #define LPFC_VF11 11 167 #define LPFC_VF12 12 168 #define LPFC_VF13 13 169 #define LPFC_VF14 14 170 #define LPFC_VF15 15 171 #define LPFC_VF16 16 172 #define LPFC_VF17 17 173 #define LPFC_VF18 18 174 #define LPFC_VF19 19 175 #define LPFC_VF20 20 176 #define LPFC_VF21 21 177 #define LPFC_VF22 22 178 #define LPFC_VF23 23 179 #define LPFC_VF24 24 180 #define LPFC_VF25 25 181 #define LPFC_VF26 26 182 #define LPFC_VF27 27 183 #define LPFC_VF28 28 184 #define LPFC_VF29 29 185 #define LPFC_VF30 30 186 #define LPFC_VF31 31 187 188 /* PCI function numbers */ 189 #define LPFC_PCI_FUNC0 0 190 #define LPFC_PCI_FUNC1 1 191 #define LPFC_PCI_FUNC2 2 192 #define LPFC_PCI_FUNC3 3 193 #define LPFC_PCI_FUNC4 4 194 195 /* SLI4 interface type-2 PDEV_CTL register */ 196 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 197 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 198 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 199 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 200 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 201 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 202 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 203 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 204 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 205 206 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 207 208 /* Active interrupt test count */ 209 #define LPFC_ACT_INTR_CNT 4 210 211 /* Algrithmns for scheduling FCP commands to WQs */ 212 #define LPFC_FCP_SCHED_BY_HDWQ 0 213 #define LPFC_FCP_SCHED_BY_CPU 1 214 215 /* Algrithmns for NameServer Query after RSCN */ 216 #define LPFC_NS_QUERY_GID_FT 0 217 #define LPFC_NS_QUERY_GID_PT 1 218 219 /* Delay Multiplier constant */ 220 #define LPFC_DMULT_CONST 651042 221 #define LPFC_DMULT_MAX 1023 222 223 /* Configuration of Interrupts / sec for entire HBA port */ 224 #define LPFC_MIN_IMAX 5000 225 #define LPFC_MAX_IMAX 5000000 226 #define LPFC_DEF_IMAX 0 227 228 #define LPFC_MAX_AUTO_EQ_DELAY 120 229 #define LPFC_EQ_DELAY_STEP 15 230 #define LPFC_EQD_ISR_TRIGGER 20000 231 /* 1s intervals */ 232 #define LPFC_EQ_DELAY_MSECS 1000 233 234 #define LPFC_MIN_CPU_MAP 0 235 #define LPFC_MAX_CPU_MAP 1 236 #define LPFC_HBA_CPU_MAP 1 237 238 /* PORT_CAPABILITIES constants. */ 239 #define LPFC_MAX_SUPPORTED_PAGES 8 240 241 enum ulp_bde64_word3 { 242 ULP_BDE64_SIZE_MASK = 0xffffff, 243 244 ULP_BDE64_TYPE_SHIFT = 24, 245 ULP_BDE64_TYPE_MASK = (0xff << ULP_BDE64_TYPE_SHIFT), 246 247 /* BDE (Host_resident) */ 248 ULP_BDE64_TYPE_BDE_64 = (0x00 << ULP_BDE64_TYPE_SHIFT), 249 /* Immediate Data BDE */ 250 ULP_BDE64_TYPE_BDE_IMMED = (0x01 << ULP_BDE64_TYPE_SHIFT), 251 /* BDE (Port-resident) */ 252 ULP_BDE64_TYPE_BDE_64P = (0x02 << ULP_BDE64_TYPE_SHIFT), 253 /* Input BDE (Host-resident) */ 254 ULP_BDE64_TYPE_BDE_64I = (0x08 << ULP_BDE64_TYPE_SHIFT), 255 /* Input BDE (Port-resident) */ 256 ULP_BDE64_TYPE_BDE_64IP = (0x0A << ULP_BDE64_TYPE_SHIFT), 257 /* BLP (Host-resident) */ 258 ULP_BDE64_TYPE_BLP_64 = (0x40 << ULP_BDE64_TYPE_SHIFT), 259 /* BLP (Port-resident) */ 260 ULP_BDE64_TYPE_BLP_64P = (0x42 << ULP_BDE64_TYPE_SHIFT), 261 }; 262 263 struct ulp_bde64_le { 264 __le32 type_size; /* type 31:24, size 23:0 */ 265 __le32 addr_low; 266 __le32 addr_high; 267 }; 268 269 struct ulp_bde64 { 270 union ULP_BDE_TUS { 271 uint32_t w; 272 struct { 273 #ifdef __BIG_ENDIAN_BITFIELD 274 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 275 VALUE !! */ 276 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 277 #else /* __LITTLE_ENDIAN_BITFIELD */ 278 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 279 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 280 VALUE !! */ 281 #endif 282 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 283 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 284 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 285 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 286 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 287 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 288 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 289 } f; 290 } tus; 291 uint32_t addrLow; 292 uint32_t addrHigh; 293 }; 294 295 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 296 #define LPFC_MAX_BDE_IMM_SIZE 64 297 298 struct lpfc_sli4_flags { 299 uint32_t word0; 300 #define lpfc_idx_rsrc_rdy_SHIFT 0 301 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 302 #define lpfc_idx_rsrc_rdy_WORD word0 303 #define LPFC_IDX_RSRC_RDY 1 304 #define lpfc_rpi_rsrc_rdy_SHIFT 1 305 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 306 #define lpfc_rpi_rsrc_rdy_WORD word0 307 #define LPFC_RPI_RSRC_RDY 1 308 #define lpfc_vpi_rsrc_rdy_SHIFT 2 309 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 310 #define lpfc_vpi_rsrc_rdy_WORD word0 311 #define LPFC_VPI_RSRC_RDY 1 312 #define lpfc_vfi_rsrc_rdy_SHIFT 3 313 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 314 #define lpfc_vfi_rsrc_rdy_WORD word0 315 #define LPFC_VFI_RSRC_RDY 1 316 #define lpfc_ftr_ashdr_SHIFT 4 317 #define lpfc_ftr_ashdr_MASK 0x00000001 318 #define lpfc_ftr_ashdr_WORD word0 319 }; 320 321 struct sli4_bls_rsp { 322 uint32_t word0_rsvd; /* Word0 must be reserved */ 323 uint32_t word1; 324 #define lpfc_abts_orig_SHIFT 0 325 #define lpfc_abts_orig_MASK 0x00000001 326 #define lpfc_abts_orig_WORD word1 327 #define LPFC_ABTS_UNSOL_RSP 1 328 #define LPFC_ABTS_UNSOL_INT 0 329 uint32_t word2; 330 #define lpfc_abts_rxid_SHIFT 0 331 #define lpfc_abts_rxid_MASK 0x0000FFFF 332 #define lpfc_abts_rxid_WORD word2 333 #define lpfc_abts_oxid_SHIFT 16 334 #define lpfc_abts_oxid_MASK 0x0000FFFF 335 #define lpfc_abts_oxid_WORD word2 336 uint32_t word3; 337 #define lpfc_vndr_code_SHIFT 0 338 #define lpfc_vndr_code_MASK 0x000000FF 339 #define lpfc_vndr_code_WORD word3 340 #define lpfc_rsn_expln_SHIFT 8 341 #define lpfc_rsn_expln_MASK 0x000000FF 342 #define lpfc_rsn_expln_WORD word3 343 #define lpfc_rsn_code_SHIFT 16 344 #define lpfc_rsn_code_MASK 0x000000FF 345 #define lpfc_rsn_code_WORD word3 346 347 uint32_t word4; 348 uint32_t word5_rsvd; /* Word5 must be reserved */ 349 }; 350 351 /* event queue entry structure */ 352 struct lpfc_eqe { 353 uint32_t word0; 354 #define lpfc_eqe_resource_id_SHIFT 16 355 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 356 #define lpfc_eqe_resource_id_WORD word0 357 #define lpfc_eqe_minor_code_SHIFT 4 358 #define lpfc_eqe_minor_code_MASK 0x00000FFF 359 #define lpfc_eqe_minor_code_WORD word0 360 #define lpfc_eqe_major_code_SHIFT 1 361 #define lpfc_eqe_major_code_MASK 0x00000007 362 #define lpfc_eqe_major_code_WORD word0 363 #define lpfc_eqe_valid_SHIFT 0 364 #define lpfc_eqe_valid_MASK 0x00000001 365 #define lpfc_eqe_valid_WORD word0 366 }; 367 368 /* completion queue entry structure (common fields for all cqe types) */ 369 struct lpfc_cqe { 370 uint32_t reserved0; 371 uint32_t reserved1; 372 uint32_t reserved2; 373 uint32_t word3; 374 #define lpfc_cqe_valid_SHIFT 31 375 #define lpfc_cqe_valid_MASK 0x00000001 376 #define lpfc_cqe_valid_WORD word3 377 #define lpfc_cqe_code_SHIFT 16 378 #define lpfc_cqe_code_MASK 0x000000FF 379 #define lpfc_cqe_code_WORD word3 380 }; 381 382 /* Completion Queue Entry Status Codes */ 383 #define CQE_STATUS_SUCCESS 0x0 384 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 385 #define CQE_STATUS_REMOTE_STOP 0x2 386 #define CQE_STATUS_LOCAL_REJECT 0x3 387 #define CQE_STATUS_NPORT_RJT 0x4 388 #define CQE_STATUS_FABRIC_RJT 0x5 389 #define CQE_STATUS_NPORT_BSY 0x6 390 #define CQE_STATUS_FABRIC_BSY 0x7 391 #define CQE_STATUS_INTERMED_RSP 0x8 392 #define CQE_STATUS_LS_RJT 0x9 393 #define CQE_STATUS_CMD_REJECT 0xb 394 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 395 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 396 #define CQE_STATUS_DI_ERROR 0x16 397 398 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 399 #define CQE_HW_STATUS_NO_ERR 0x0 400 #define CQE_HW_STATUS_UNDERRUN 0x1 401 #define CQE_HW_STATUS_OVERRUN 0x2 402 403 /* Completion Queue Entry Codes */ 404 #define CQE_CODE_COMPL_WQE 0x1 405 #define CQE_CODE_RELEASE_WQE 0x2 406 #define CQE_CODE_RECEIVE 0x4 407 #define CQE_CODE_XRI_ABORTED 0x5 408 #define CQE_CODE_RECEIVE_V1 0x9 409 #define CQE_CODE_NVME_ERSP 0xd 410 411 /* 412 * Define mask value for xri_aborted and wcqe completed CQE extended status. 413 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 414 */ 415 #define WCQE_PARAM_MASK 0x1FF 416 417 /* completion queue entry for wqe completions */ 418 struct lpfc_wcqe_complete { 419 uint32_t word0; 420 #define lpfc_wcqe_c_request_tag_SHIFT 16 421 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 422 #define lpfc_wcqe_c_request_tag_WORD word0 423 #define lpfc_wcqe_c_status_SHIFT 8 424 #define lpfc_wcqe_c_status_MASK 0x000000FF 425 #define lpfc_wcqe_c_status_WORD word0 426 #define lpfc_wcqe_c_hw_status_SHIFT 0 427 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 428 #define lpfc_wcqe_c_hw_status_WORD word0 429 #define lpfc_wcqe_c_ersp0_SHIFT 0 430 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 431 #define lpfc_wcqe_c_ersp0_WORD word0 432 uint32_t total_data_placed; 433 #define lpfc_wcqe_c_cmf_cg_SHIFT 31 434 #define lpfc_wcqe_c_cmf_cg_MASK 0x00000001 435 #define lpfc_wcqe_c_cmf_cg_WORD total_data_placed 436 #define lpfc_wcqe_c_cmf_bw_SHIFT 0 437 #define lpfc_wcqe_c_cmf_bw_MASK 0x0FFFFFFF 438 #define lpfc_wcqe_c_cmf_bw_WORD total_data_placed 439 uint32_t parameter; 440 #define lpfc_wcqe_c_enc_SHIFT 31 441 #define lpfc_wcqe_c_enc_MASK 0x00000001 442 #define lpfc_wcqe_c_enc_WORD parameter 443 #define lpfc_wcqe_c_enc_lvl_SHIFT 30 444 #define lpfc_wcqe_c_enc_lvl_MASK 0x00000001 445 #define lpfc_wcqe_c_enc_lvl_WORD parameter 446 #define lpfc_wcqe_c_bg_edir_SHIFT 5 447 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 448 #define lpfc_wcqe_c_bg_edir_WORD parameter 449 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 450 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 451 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 452 #define lpfc_wcqe_c_bg_re_SHIFT 2 453 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 454 #define lpfc_wcqe_c_bg_re_WORD parameter 455 #define lpfc_wcqe_c_bg_ae_SHIFT 1 456 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 457 #define lpfc_wcqe_c_bg_ae_WORD parameter 458 #define lpfc_wcqe_c_bg_ge_SHIFT 0 459 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 460 #define lpfc_wcqe_c_bg_ge_WORD parameter 461 uint32_t word3; 462 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 463 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 464 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 465 #define lpfc_wcqe_c_xb_SHIFT 28 466 #define lpfc_wcqe_c_xb_MASK 0x00000001 467 #define lpfc_wcqe_c_xb_WORD word3 468 #define lpfc_wcqe_c_pv_SHIFT 27 469 #define lpfc_wcqe_c_pv_MASK 0x00000001 470 #define lpfc_wcqe_c_pv_WORD word3 471 #define lpfc_wcqe_c_priority_SHIFT 24 472 #define lpfc_wcqe_c_priority_MASK 0x00000007 473 #define lpfc_wcqe_c_priority_WORD word3 474 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 475 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 476 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 477 #define lpfc_wcqe_c_sqhead_SHIFT 0 478 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 479 #define lpfc_wcqe_c_sqhead_WORD word3 480 }; 481 482 /* completion queue entry for wqe release */ 483 struct lpfc_wcqe_release { 484 uint32_t reserved0; 485 uint32_t reserved1; 486 uint32_t word2; 487 #define lpfc_wcqe_r_wq_id_SHIFT 16 488 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 489 #define lpfc_wcqe_r_wq_id_WORD word2 490 #define lpfc_wcqe_r_wqe_index_SHIFT 0 491 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 492 #define lpfc_wcqe_r_wqe_index_WORD word2 493 uint32_t word3; 494 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 495 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 496 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 497 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 498 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 499 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 500 }; 501 502 struct sli4_wcqe_xri_aborted { 503 uint32_t word0; 504 #define lpfc_wcqe_xa_status_SHIFT 8 505 #define lpfc_wcqe_xa_status_MASK 0x000000FF 506 #define lpfc_wcqe_xa_status_WORD word0 507 uint32_t parameter; 508 uint32_t word2; 509 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 510 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 511 #define lpfc_wcqe_xa_remote_xid_WORD word2 512 #define lpfc_wcqe_xa_xri_SHIFT 0 513 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 514 #define lpfc_wcqe_xa_xri_WORD word2 515 uint32_t word3; 516 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 517 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 518 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 519 #define lpfc_wcqe_xa_ia_SHIFT 30 520 #define lpfc_wcqe_xa_ia_MASK 0x00000001 521 #define lpfc_wcqe_xa_ia_WORD word3 522 #define CQE_XRI_ABORTED_IA_REMOTE 0 523 #define CQE_XRI_ABORTED_IA_LOCAL 1 524 #define lpfc_wcqe_xa_br_SHIFT 29 525 #define lpfc_wcqe_xa_br_MASK 0x00000001 526 #define lpfc_wcqe_xa_br_WORD word3 527 #define CQE_XRI_ABORTED_BR_BA_ACC 0 528 #define CQE_XRI_ABORTED_BR_BA_RJT 1 529 #define lpfc_wcqe_xa_eo_SHIFT 28 530 #define lpfc_wcqe_xa_eo_MASK 0x00000001 531 #define lpfc_wcqe_xa_eo_WORD word3 532 #define CQE_XRI_ABORTED_EO_REMOTE 0 533 #define CQE_XRI_ABORTED_EO_LOCAL 1 534 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 535 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 536 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 537 }; 538 539 /* completion queue entry structure for rqe completion */ 540 struct lpfc_rcqe { 541 uint32_t word0; 542 #define lpfc_rcqe_iv_SHIFT 31 543 #define lpfc_rcqe_iv_MASK 0x00000001 544 #define lpfc_rcqe_iv_WORD word0 545 #define lpfc_rcqe_status_SHIFT 8 546 #define lpfc_rcqe_status_MASK 0x000000FF 547 #define lpfc_rcqe_status_WORD word0 548 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 549 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 550 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 551 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 552 #define FC_STATUS_RQ_DMA_FAILURE 0x14 /* DMA failure */ 553 uint32_t word1; 554 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 555 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 556 #define lpfc_rcqe_fcf_id_v1_WORD word1 557 uint32_t word2; 558 #define lpfc_rcqe_length_SHIFT 16 559 #define lpfc_rcqe_length_MASK 0x0000FFFF 560 #define lpfc_rcqe_length_WORD word2 561 #define lpfc_rcqe_rq_id_SHIFT 6 562 #define lpfc_rcqe_rq_id_MASK 0x000003FF 563 #define lpfc_rcqe_rq_id_WORD word2 564 #define lpfc_rcqe_fcf_id_SHIFT 0 565 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 566 #define lpfc_rcqe_fcf_id_WORD word2 567 #define lpfc_rcqe_rq_id_v1_SHIFT 0 568 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 569 #define lpfc_rcqe_rq_id_v1_WORD word2 570 uint32_t word3; 571 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 572 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 573 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 574 #define lpfc_rcqe_port_SHIFT 30 575 #define lpfc_rcqe_port_MASK 0x00000001 576 #define lpfc_rcqe_port_WORD word3 577 #define lpfc_rcqe_hdr_length_SHIFT 24 578 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 579 #define lpfc_rcqe_hdr_length_WORD word3 580 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 581 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 582 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 583 #define lpfc_rcqe_eof_SHIFT 8 584 #define lpfc_rcqe_eof_MASK 0x000000FF 585 #define lpfc_rcqe_eof_WORD word3 586 #define FCOE_EOFn 0x41 587 #define FCOE_EOFt 0x42 588 #define FCOE_EOFni 0x49 589 #define FCOE_EOFa 0x50 590 #define lpfc_rcqe_sof_SHIFT 0 591 #define lpfc_rcqe_sof_MASK 0x000000FF 592 #define lpfc_rcqe_sof_WORD word3 593 #define FCOE_SOFi2 0x2d 594 #define FCOE_SOFi3 0x2e 595 #define FCOE_SOFn2 0x35 596 #define FCOE_SOFn3 0x36 597 }; 598 599 struct lpfc_rqe { 600 uint32_t address_hi; 601 uint32_t address_lo; 602 }; 603 604 /* buffer descriptors */ 605 struct lpfc_bde4 { 606 uint32_t addr_hi; 607 uint32_t addr_lo; 608 uint32_t word2; 609 #define lpfc_bde4_last_SHIFT 31 610 #define lpfc_bde4_last_MASK 0x00000001 611 #define lpfc_bde4_last_WORD word2 612 #define lpfc_bde4_sge_offset_SHIFT 0 613 #define lpfc_bde4_sge_offset_MASK 0x000003FF 614 #define lpfc_bde4_sge_offset_WORD word2 615 uint32_t word3; 616 #define lpfc_bde4_length_SHIFT 0 617 #define lpfc_bde4_length_MASK 0x000000FF 618 #define lpfc_bde4_length_WORD word3 619 }; 620 621 struct lpfc_register { 622 uint32_t word0; 623 }; 624 625 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 626 #define LPFC_PORT_SEM_MASK 0xF000 627 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 628 #define LPFC_UERR_STATUS_HI 0x00A4 629 #define LPFC_UERR_STATUS_LO 0x00A0 630 #define LPFC_UE_MASK_HI 0x00AC 631 #define LPFC_UE_MASK_LO 0x00A8 632 633 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 634 #define LPFC_SLI_INTF 0x0058 635 #define LPFC_SLI_ASIC_VER 0x009C 636 637 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 638 #define lpfc_port_smphr_perr_SHIFT 31 639 #define lpfc_port_smphr_perr_MASK 0x1 640 #define lpfc_port_smphr_perr_WORD word0 641 #define lpfc_port_smphr_sfi_SHIFT 30 642 #define lpfc_port_smphr_sfi_MASK 0x1 643 #define lpfc_port_smphr_sfi_WORD word0 644 #define lpfc_port_smphr_nip_SHIFT 29 645 #define lpfc_port_smphr_nip_MASK 0x1 646 #define lpfc_port_smphr_nip_WORD word0 647 #define lpfc_port_smphr_ipc_SHIFT 28 648 #define lpfc_port_smphr_ipc_MASK 0x1 649 #define lpfc_port_smphr_ipc_WORD word0 650 #define lpfc_port_smphr_scr1_SHIFT 27 651 #define lpfc_port_smphr_scr1_MASK 0x1 652 #define lpfc_port_smphr_scr1_WORD word0 653 #define lpfc_port_smphr_scr2_SHIFT 26 654 #define lpfc_port_smphr_scr2_MASK 0x1 655 #define lpfc_port_smphr_scr2_WORD word0 656 #define lpfc_port_smphr_host_scratch_SHIFT 16 657 #define lpfc_port_smphr_host_scratch_MASK 0xFF 658 #define lpfc_port_smphr_host_scratch_WORD word0 659 #define lpfc_port_smphr_port_status_SHIFT 0 660 #define lpfc_port_smphr_port_status_MASK 0xFFFF 661 #define lpfc_port_smphr_port_status_WORD word0 662 663 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 664 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 665 #define LPFC_POST_STAGE_HOST_RDY 0x0002 666 #define LPFC_POST_STAGE_BE_RESET 0x0003 667 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 668 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 669 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 670 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 671 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 672 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 673 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 674 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 675 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 676 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 677 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 678 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 679 #define LPFC_POST_STAGE_ARMFW_START 0x0800 680 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 681 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 682 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 683 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 684 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 685 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 686 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 687 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 688 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 689 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 690 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 691 #define LPFC_POST_STAGE_RC_DONE 0x0B07 692 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 693 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 694 #define LPFC_POST_STAGE_PORT_READY 0xC000 695 #define LPFC_POST_STAGE_PORT_UE 0xF000 696 697 #define LPFC_CTL_PORT_STA_OFFSET 0x404 698 #define lpfc_sliport_status_err_SHIFT 31 699 #define lpfc_sliport_status_err_MASK 0x1 700 #define lpfc_sliport_status_err_WORD word0 701 #define lpfc_sliport_status_end_SHIFT 30 702 #define lpfc_sliport_status_end_MASK 0x1 703 #define lpfc_sliport_status_end_WORD word0 704 #define lpfc_sliport_status_oti_SHIFT 29 705 #define lpfc_sliport_status_oti_MASK 0x1 706 #define lpfc_sliport_status_oti_WORD word0 707 #define lpfc_sliport_status_dip_SHIFT 25 708 #define lpfc_sliport_status_dip_MASK 0x1 709 #define lpfc_sliport_status_dip_WORD word0 710 #define lpfc_sliport_status_rn_SHIFT 24 711 #define lpfc_sliport_status_rn_MASK 0x1 712 #define lpfc_sliport_status_rn_WORD word0 713 #define lpfc_sliport_status_rdy_SHIFT 23 714 #define lpfc_sliport_status_rdy_MASK 0x1 715 #define lpfc_sliport_status_rdy_WORD word0 716 #define lpfc_sliport_status_pldv_SHIFT 0 717 #define lpfc_sliport_status_pldv_MASK 0x1 718 #define lpfc_sliport_status_pldv_WORD word0 719 #define CFG_PLD 0x3C 720 #define MAX_IF_TYPE_2_RESETS 6 721 722 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 723 #define lpfc_sliport_ctrl_end_SHIFT 30 724 #define lpfc_sliport_ctrl_end_MASK 0x1 725 #define lpfc_sliport_ctrl_end_WORD word0 726 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 727 #define LPFC_SLIPORT_BIG_ENDIAN 1 728 #define lpfc_sliport_ctrl_ip_SHIFT 27 729 #define lpfc_sliport_ctrl_ip_MASK 0x1 730 #define lpfc_sliport_ctrl_ip_WORD word0 731 #define LPFC_SLIPORT_INIT_PORT 1 732 733 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 734 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 735 736 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 737 #define lpfc_sliport_eqdelay_delay_SHIFT 16 738 #define lpfc_sliport_eqdelay_delay_MASK 0xffff 739 #define lpfc_sliport_eqdelay_delay_WORD word0 740 #define lpfc_sliport_eqdelay_id_SHIFT 0 741 #define lpfc_sliport_eqdelay_id_MASK 0xfff 742 #define lpfc_sliport_eqdelay_id_WORD word0 743 #define LPFC_SEC_TO_USEC 1000000 744 #define LPFC_SEC_TO_MSEC 1000 745 #define LPFC_MSECS_TO_SECS(msecs) ((msecs) / 1000) 746 747 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 748 * reside in BAR 2. 749 */ 750 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 751 752 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 753 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 754 755 #define LPFC_HST_ISR0 0x0C18 756 #define LPFC_HST_ISR1 0x0C1C 757 #define LPFC_HST_ISR2 0x0C20 758 #define LPFC_HST_ISR3 0x0C24 759 #define LPFC_HST_ISR4 0x0C28 760 761 #define LPFC_HST_IMR0 0x0C48 762 #define LPFC_HST_IMR1 0x0C4C 763 #define LPFC_HST_IMR2 0x0C50 764 #define LPFC_HST_IMR3 0x0C54 765 #define LPFC_HST_IMR4 0x0C58 766 767 #define LPFC_HST_ISCR0 0x0C78 768 #define LPFC_HST_ISCR1 0x0C7C 769 #define LPFC_HST_ISCR2 0x0C80 770 #define LPFC_HST_ISCR3 0x0C84 771 #define LPFC_HST_ISCR4 0x0C88 772 773 #define LPFC_SLI4_INTR0 BIT0 774 #define LPFC_SLI4_INTR1 BIT1 775 #define LPFC_SLI4_INTR2 BIT2 776 #define LPFC_SLI4_INTR3 BIT3 777 #define LPFC_SLI4_INTR4 BIT4 778 #define LPFC_SLI4_INTR5 BIT5 779 #define LPFC_SLI4_INTR6 BIT6 780 #define LPFC_SLI4_INTR7 BIT7 781 #define LPFC_SLI4_INTR8 BIT8 782 #define LPFC_SLI4_INTR9 BIT9 783 #define LPFC_SLI4_INTR10 BIT10 784 #define LPFC_SLI4_INTR11 BIT11 785 #define LPFC_SLI4_INTR12 BIT12 786 #define LPFC_SLI4_INTR13 BIT13 787 #define LPFC_SLI4_INTR14 BIT14 788 #define LPFC_SLI4_INTR15 BIT15 789 #define LPFC_SLI4_INTR16 BIT16 790 #define LPFC_SLI4_INTR17 BIT17 791 #define LPFC_SLI4_INTR18 BIT18 792 #define LPFC_SLI4_INTR19 BIT19 793 #define LPFC_SLI4_INTR20 BIT20 794 #define LPFC_SLI4_INTR21 BIT21 795 #define LPFC_SLI4_INTR22 BIT22 796 #define LPFC_SLI4_INTR23 BIT23 797 #define LPFC_SLI4_INTR24 BIT24 798 #define LPFC_SLI4_INTR25 BIT25 799 #define LPFC_SLI4_INTR26 BIT26 800 #define LPFC_SLI4_INTR27 BIT27 801 #define LPFC_SLI4_INTR28 BIT28 802 #define LPFC_SLI4_INTR29 BIT29 803 #define LPFC_SLI4_INTR30 BIT30 804 #define LPFC_SLI4_INTR31 BIT31 805 806 /* 807 * The Doorbell registers defined here exist in different BAR 808 * register sets depending on the UCNA Port's reported if_type 809 * value. For UCNA ports running SLI4 and if_type 0, they reside in 810 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 811 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 812 * BAR2. The offsets and base address are different, so the driver 813 * has to compute the register addresses accordingly 814 */ 815 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 816 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 817 #define LPFC_IF6_RQ_DOORBELL 0x0080 818 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 819 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 820 #define lpfc_rq_db_list_fm_num_posted_WORD word0 821 #define lpfc_rq_db_list_fm_index_SHIFT 16 822 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 823 #define lpfc_rq_db_list_fm_index_WORD word0 824 #define lpfc_rq_db_list_fm_id_SHIFT 0 825 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 826 #define lpfc_rq_db_list_fm_id_WORD word0 827 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 828 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 829 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 830 #define lpfc_rq_db_ring_fm_id_SHIFT 0 831 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 832 #define lpfc_rq_db_ring_fm_id_WORD word0 833 834 #define LPFC_ULP0_WQ_DOORBELL 0x0040 835 #define LPFC_ULP1_WQ_DOORBELL 0x0060 836 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 837 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 838 #define lpfc_wq_db_list_fm_num_posted_WORD word0 839 #define lpfc_wq_db_list_fm_index_SHIFT 16 840 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 841 #define lpfc_wq_db_list_fm_index_WORD word0 842 #define lpfc_wq_db_list_fm_id_SHIFT 0 843 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 844 #define lpfc_wq_db_list_fm_id_WORD word0 845 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 846 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 847 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 848 #define lpfc_wq_db_ring_fm_id_SHIFT 0 849 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 850 #define lpfc_wq_db_ring_fm_id_WORD word0 851 852 #define LPFC_IF6_WQ_DOORBELL 0x0040 853 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 854 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 855 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 856 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 857 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 858 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0 859 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 860 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 861 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 862 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0 863 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 864 #define lpfc_if6_wq_db_list_fm_id_WORD word0 865 866 #define LPFC_EQCQ_DOORBELL 0x0120 867 #define lpfc_eqcq_doorbell_se_SHIFT 31 868 #define lpfc_eqcq_doorbell_se_MASK 0x0001 869 #define lpfc_eqcq_doorbell_se_WORD word0 870 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 871 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 872 #define lpfc_eqcq_doorbell_arm_SHIFT 29 873 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 874 #define lpfc_eqcq_doorbell_arm_WORD word0 875 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 876 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 877 #define lpfc_eqcq_doorbell_num_released_WORD word0 878 #define lpfc_eqcq_doorbell_qt_SHIFT 10 879 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 880 #define lpfc_eqcq_doorbell_qt_WORD word0 881 #define LPFC_QUEUE_TYPE_COMPLETION 0 882 #define LPFC_QUEUE_TYPE_EVENT 1 883 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 884 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 885 #define lpfc_eqcq_doorbell_eqci_WORD word0 886 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 887 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 888 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 889 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 890 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 891 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 892 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 893 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 894 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 895 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 896 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 897 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 898 #define LPFC_CQID_HI_FIELD_SHIFT 10 899 #define LPFC_EQID_HI_FIELD_SHIFT 9 900 901 #define LPFC_IF6_CQ_DOORBELL 0x00C0 902 #define lpfc_if6_cq_doorbell_se_SHIFT 31 903 #define lpfc_if6_cq_doorbell_se_MASK 0x0001 904 #define lpfc_if6_cq_doorbell_se_WORD word0 905 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 906 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 907 #define lpfc_if6_cq_doorbell_arm_SHIFT 29 908 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001 909 #define lpfc_if6_cq_doorbell_arm_WORD word0 910 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16 911 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 912 #define lpfc_if6_cq_doorbell_num_released_WORD word0 913 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0 914 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 915 #define lpfc_if6_cq_doorbell_cqid_WORD word0 916 917 #define LPFC_IF6_EQ_DOORBELL 0x0120 918 #define lpfc_if6_eq_doorbell_io_SHIFT 31 919 #define lpfc_if6_eq_doorbell_io_MASK 0x0001 920 #define lpfc_if6_eq_doorbell_io_WORD word0 921 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 922 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 923 #define lpfc_if6_eq_doorbell_arm_SHIFT 29 924 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001 925 #define lpfc_if6_eq_doorbell_arm_WORD word0 926 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16 927 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 928 #define lpfc_if6_eq_doorbell_num_released_WORD word0 929 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0 930 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 931 #define lpfc_if6_eq_doorbell_eqid_WORD word0 932 933 #define LPFC_BMBX 0x0160 934 #define lpfc_bmbx_addr_SHIFT 2 935 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 936 #define lpfc_bmbx_addr_WORD word0 937 #define lpfc_bmbx_hi_SHIFT 1 938 #define lpfc_bmbx_hi_MASK 0x0001 939 #define lpfc_bmbx_hi_WORD word0 940 #define lpfc_bmbx_rdy_SHIFT 0 941 #define lpfc_bmbx_rdy_MASK 0x0001 942 #define lpfc_bmbx_rdy_WORD word0 943 944 #define LPFC_MQ_DOORBELL 0x0140 945 #define LPFC_IF6_MQ_DOORBELL 0x0160 946 #define lpfc_mq_doorbell_num_posted_SHIFT 16 947 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 948 #define lpfc_mq_doorbell_num_posted_WORD word0 949 #define lpfc_mq_doorbell_id_SHIFT 0 950 #define lpfc_mq_doorbell_id_MASK 0xFFFF 951 #define lpfc_mq_doorbell_id_WORD word0 952 953 struct lpfc_sli4_cfg_mhdr { 954 uint32_t word1; 955 #define lpfc_mbox_hdr_emb_SHIFT 0 956 #define lpfc_mbox_hdr_emb_MASK 0x00000001 957 #define lpfc_mbox_hdr_emb_WORD word1 958 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 959 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 960 #define lpfc_mbox_hdr_sge_cnt_WORD word1 961 uint32_t payload_length; 962 uint32_t tag_lo; 963 uint32_t tag_hi; 964 uint32_t reserved5; 965 }; 966 967 union lpfc_sli4_cfg_shdr { 968 struct { 969 uint32_t word6; 970 #define lpfc_mbox_hdr_opcode_SHIFT 0 971 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 972 #define lpfc_mbox_hdr_opcode_WORD word6 973 #define lpfc_mbox_hdr_subsystem_SHIFT 8 974 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 975 #define lpfc_mbox_hdr_subsystem_WORD word6 976 #define lpfc_mbox_hdr_port_number_SHIFT 16 977 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 978 #define lpfc_mbox_hdr_port_number_WORD word6 979 #define lpfc_mbox_hdr_domain_SHIFT 24 980 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 981 #define lpfc_mbox_hdr_domain_WORD word6 982 uint32_t timeout; 983 uint32_t request_length; 984 uint32_t word9; 985 #define lpfc_mbox_hdr_version_SHIFT 0 986 #define lpfc_mbox_hdr_version_MASK 0x000000FF 987 #define lpfc_mbox_hdr_version_WORD word9 988 #define lpfc_mbox_hdr_pf_num_SHIFT 16 989 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 990 #define lpfc_mbox_hdr_pf_num_WORD word9 991 #define lpfc_mbox_hdr_vh_num_SHIFT 24 992 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 993 #define lpfc_mbox_hdr_vh_num_WORD word9 994 #define LPFC_Q_CREATE_VERSION_2 2 995 #define LPFC_Q_CREATE_VERSION_1 1 996 #define LPFC_Q_CREATE_VERSION_0 0 997 #define LPFC_OPCODE_VERSION_0 0 998 #define LPFC_OPCODE_VERSION_1 1 999 } request; 1000 struct { 1001 uint32_t word6; 1002 #define lpfc_mbox_hdr_opcode_SHIFT 0 1003 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 1004 #define lpfc_mbox_hdr_opcode_WORD word6 1005 #define lpfc_mbox_hdr_subsystem_SHIFT 8 1006 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 1007 #define lpfc_mbox_hdr_subsystem_WORD word6 1008 #define lpfc_mbox_hdr_domain_SHIFT 24 1009 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 1010 #define lpfc_mbox_hdr_domain_WORD word6 1011 uint32_t word7; 1012 #define lpfc_mbox_hdr_status_SHIFT 0 1013 #define lpfc_mbox_hdr_status_MASK 0x000000FF 1014 #define lpfc_mbox_hdr_status_WORD word7 1015 #define lpfc_mbox_hdr_add_status_SHIFT 8 1016 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 1017 #define lpfc_mbox_hdr_add_status_WORD word7 1018 #define LPFC_ADD_STATUS_INCOMPAT_OBJ 0xA2 1019 #define lpfc_mbox_hdr_add_status_2_SHIFT 16 1020 #define lpfc_mbox_hdr_add_status_2_MASK 0x000000FF 1021 #define lpfc_mbox_hdr_add_status_2_WORD word7 1022 #define LPFC_ADD_STATUS_2_INCOMPAT_FLASH 0x01 1023 #define LPFC_ADD_STATUS_2_INCORRECT_ASIC 0x02 1024 uint32_t response_length; 1025 uint32_t actual_response_length; 1026 } response; 1027 }; 1028 1029 /* Mailbox Header structures. 1030 * struct mbox_header is defined for first generation SLI4_CFG mailbox 1031 * calls deployed for BE-based ports. 1032 * 1033 * struct sli4_mbox_header is defined for second generation SLI4 1034 * ports that don't deploy the SLI4_CFG mechanism. 1035 */ 1036 struct mbox_header { 1037 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1038 union lpfc_sli4_cfg_shdr cfg_shdr; 1039 }; 1040 1041 #define LPFC_EXTENT_LOCAL 0 1042 #define LPFC_TIMEOUT_DEFAULT 0 1043 #define LPFC_EXTENT_VERSION_DEFAULT 0 1044 1045 /* Subsystem Definitions */ 1046 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 1047 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 1048 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 1049 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 1050 1051 /* Device Specific Definitions */ 1052 1053 /* The HOST ENDIAN defines are in Big Endian format. */ 1054 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 1055 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 1056 1057 /* Common Opcodes */ 1058 #define LPFC_MBOX_OPCODE_NA 0x00 1059 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 1060 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 1061 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 1062 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 1063 #define LPFC_MBOX_OPCODE_NOP 0x21 1064 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 1065 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 1066 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 1067 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 1068 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 1069 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 1070 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 1071 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 1072 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 1073 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 1074 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 1075 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 1076 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 1077 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 1078 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 1079 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1080 #define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF 0x8E 1081 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1082 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1083 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1084 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1085 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1086 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1087 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1088 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1089 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1090 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1091 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1092 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1093 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1094 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1095 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1096 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1097 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1098 1099 /* FCoE Opcodes */ 1100 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1101 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1102 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1103 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1104 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1105 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1106 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1107 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1108 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1109 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1110 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1111 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1112 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1113 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1114 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1115 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42 1116 1117 /* Low level Opcodes */ 1118 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1119 1120 /* Mailbox command structures */ 1121 struct eq_context { 1122 uint32_t word0; 1123 #define lpfc_eq_context_size_SHIFT 31 1124 #define lpfc_eq_context_size_MASK 0x00000001 1125 #define lpfc_eq_context_size_WORD word0 1126 #define LPFC_EQE_SIZE_4 0x0 1127 #define LPFC_EQE_SIZE_16 0x1 1128 #define lpfc_eq_context_valid_SHIFT 29 1129 #define lpfc_eq_context_valid_MASK 0x00000001 1130 #define lpfc_eq_context_valid_WORD word0 1131 #define lpfc_eq_context_autovalid_SHIFT 28 1132 #define lpfc_eq_context_autovalid_MASK 0x00000001 1133 #define lpfc_eq_context_autovalid_WORD word0 1134 uint32_t word1; 1135 #define lpfc_eq_context_count_SHIFT 26 1136 #define lpfc_eq_context_count_MASK 0x00000003 1137 #define lpfc_eq_context_count_WORD word1 1138 #define LPFC_EQ_CNT_256 0x0 1139 #define LPFC_EQ_CNT_512 0x1 1140 #define LPFC_EQ_CNT_1024 0x2 1141 #define LPFC_EQ_CNT_2048 0x3 1142 #define LPFC_EQ_CNT_4096 0x4 1143 uint32_t word2; 1144 #define lpfc_eq_context_delay_multi_SHIFT 13 1145 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 1146 #define lpfc_eq_context_delay_multi_WORD word2 1147 uint32_t reserved3; 1148 }; 1149 1150 struct eq_delay_info { 1151 uint32_t eq_id; 1152 uint32_t phase; 1153 uint32_t delay_multi; 1154 }; 1155 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1156 1157 struct sgl_page_pairs { 1158 uint32_t sgl_pg0_addr_lo; 1159 uint32_t sgl_pg0_addr_hi; 1160 uint32_t sgl_pg1_addr_lo; 1161 uint32_t sgl_pg1_addr_hi; 1162 }; 1163 1164 struct lpfc_mbx_post_sgl_pages { 1165 struct mbox_header header; 1166 uint32_t word0; 1167 #define lpfc_post_sgl_pages_xri_SHIFT 0 1168 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1169 #define lpfc_post_sgl_pages_xri_WORD word0 1170 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1171 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1172 #define lpfc_post_sgl_pages_xricnt_WORD word0 1173 struct sgl_page_pairs sgl_pg_pairs[1]; 1174 }; 1175 1176 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1177 struct lpfc_mbx_post_uembed_sgl_page1 { 1178 union lpfc_sli4_cfg_shdr cfg_shdr; 1179 uint32_t word0; 1180 struct sgl_page_pairs sgl_pg_pairs; 1181 }; 1182 1183 struct lpfc_mbx_sge { 1184 uint32_t pa_lo; 1185 uint32_t pa_hi; 1186 uint32_t length; 1187 }; 1188 1189 struct lpfc_mbx_host_buf { 1190 uint32_t length; 1191 uint32_t pa_lo; 1192 uint32_t pa_hi; 1193 }; 1194 1195 struct lpfc_mbx_nembed_cmd { 1196 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1197 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1198 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1199 }; 1200 1201 struct lpfc_mbx_nembed_sge_virt { 1202 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1203 }; 1204 1205 #define LPFC_MBX_OBJECT_NAME_LEN_DW 26 1206 struct lpfc_mbx_read_object { /* Version 0 */ 1207 struct mbox_header header; 1208 union { 1209 struct { 1210 uint32_t word0; 1211 #define lpfc_mbx_rd_object_rlen_SHIFT 0 1212 #define lpfc_mbx_rd_object_rlen_MASK 0x00FFFFFF 1213 #define lpfc_mbx_rd_object_rlen_WORD word0 1214 uint32_t rd_object_offset; 1215 __le32 rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW]; 1216 #define LPFC_OBJ_NAME_SZ 104 /* 26 x sizeof(uint32_t) is 104. */ 1217 uint32_t rd_object_cnt; 1218 struct lpfc_mbx_host_buf rd_object_hbuf[4]; 1219 } request; 1220 struct { 1221 uint32_t rd_object_actual_rlen; 1222 uint32_t word1; 1223 #define lpfc_mbx_rd_object_eof_SHIFT 31 1224 #define lpfc_mbx_rd_object_eof_MASK 0x1 1225 #define lpfc_mbx_rd_object_eof_WORD word1 1226 } response; 1227 } u; 1228 }; 1229 1230 struct lpfc_mbx_eq_create { 1231 struct mbox_header header; 1232 union { 1233 struct { 1234 uint32_t word0; 1235 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1236 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1237 #define lpfc_mbx_eq_create_num_pages_WORD word0 1238 struct eq_context context; 1239 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1240 } request; 1241 struct { 1242 uint32_t word0; 1243 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1244 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1245 #define lpfc_mbx_eq_create_q_id_WORD word0 1246 } response; 1247 } u; 1248 }; 1249 1250 struct lpfc_mbx_modify_eq_delay { 1251 struct mbox_header header; 1252 union { 1253 struct { 1254 uint32_t num_eq; 1255 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1256 } request; 1257 struct { 1258 uint32_t word0; 1259 } response; 1260 } u; 1261 }; 1262 1263 struct lpfc_mbx_eq_destroy { 1264 struct mbox_header header; 1265 union { 1266 struct { 1267 uint32_t word0; 1268 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1269 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1270 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1271 } request; 1272 struct { 1273 uint32_t word0; 1274 } response; 1275 } u; 1276 }; 1277 1278 struct lpfc_mbx_nop { 1279 struct mbox_header header; 1280 uint32_t context[2]; 1281 }; 1282 1283 1284 1285 struct lpfc_mbx_set_ras_fwlog { 1286 struct mbox_header header; 1287 union { 1288 struct { 1289 uint32_t word4; 1290 #define lpfc_fwlog_enable_SHIFT 0 1291 #define lpfc_fwlog_enable_MASK 0x00000001 1292 #define lpfc_fwlog_enable_WORD word4 1293 #define lpfc_fwlog_loglvl_SHIFT 8 1294 #define lpfc_fwlog_loglvl_MASK 0x0000000F 1295 #define lpfc_fwlog_loglvl_WORD word4 1296 #define lpfc_fwlog_ra_SHIFT 15 1297 #define lpfc_fwlog_ra_WORD 0x00000008 1298 #define lpfc_fwlog_buffcnt_SHIFT 16 1299 #define lpfc_fwlog_buffcnt_MASK 0x000000FF 1300 #define lpfc_fwlog_buffcnt_WORD word4 1301 #define lpfc_fwlog_buffsz_SHIFT 24 1302 #define lpfc_fwlog_buffsz_MASK 0x000000FF 1303 #define lpfc_fwlog_buffsz_WORD word4 1304 uint32_t word5; 1305 #define lpfc_fwlog_acqe_SHIFT 0 1306 #define lpfc_fwlog_acqe_MASK 0x0000FFFF 1307 #define lpfc_fwlog_acqe_WORD word5 1308 #define lpfc_fwlog_cqid_SHIFT 16 1309 #define lpfc_fwlog_cqid_MASK 0x0000FFFF 1310 #define lpfc_fwlog_cqid_WORD word5 1311 #define LPFC_MAX_FWLOG_PAGE 16 1312 struct dma_address lwpd; 1313 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1314 } request; 1315 struct { 1316 uint32_t word0; 1317 } response; 1318 } u; 1319 }; 1320 1321 1322 struct cq_context { 1323 uint32_t word0; 1324 #define lpfc_cq_context_event_SHIFT 31 1325 #define lpfc_cq_context_event_MASK 0x00000001 1326 #define lpfc_cq_context_event_WORD word0 1327 #define lpfc_cq_context_valid_SHIFT 29 1328 #define lpfc_cq_context_valid_MASK 0x00000001 1329 #define lpfc_cq_context_valid_WORD word0 1330 #define lpfc_cq_context_count_SHIFT 27 1331 #define lpfc_cq_context_count_MASK 0x00000003 1332 #define lpfc_cq_context_count_WORD word0 1333 #define LPFC_CQ_CNT_256 0x0 1334 #define LPFC_CQ_CNT_512 0x1 1335 #define LPFC_CQ_CNT_1024 0x2 1336 #define LPFC_CQ_CNT_WORD7 0x3 1337 #define lpfc_cq_context_cqe_sz_SHIFT 25 1338 #define lpfc_cq_context_cqe_sz_MASK 0x00000003 1339 #define lpfc_cq_context_cqe_sz_WORD word0 1340 #define lpfc_cq_context_autovalid_SHIFT 15 1341 #define lpfc_cq_context_autovalid_MASK 0x00000001 1342 #define lpfc_cq_context_autovalid_WORD word0 1343 uint32_t word1; 1344 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1345 #define lpfc_cq_eq_id_MASK 0x000000FF 1346 #define lpfc_cq_eq_id_WORD word1 1347 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1348 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1349 #define lpfc_cq_eq_id_2_WORD word1 1350 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1351 uint32_t reserved1; 1352 }; 1353 1354 struct lpfc_mbx_cq_create { 1355 struct mbox_header header; 1356 union { 1357 struct { 1358 uint32_t word0; 1359 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1360 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1361 #define lpfc_mbx_cq_create_page_size_WORD word0 1362 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1363 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1364 #define lpfc_mbx_cq_create_num_pages_WORD word0 1365 struct cq_context context; 1366 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1367 } request; 1368 struct { 1369 uint32_t word0; 1370 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1371 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1372 #define lpfc_mbx_cq_create_q_id_WORD word0 1373 } response; 1374 } u; 1375 }; 1376 1377 struct lpfc_mbx_cq_create_set { 1378 union lpfc_sli4_cfg_shdr cfg_shdr; 1379 union { 1380 struct { 1381 uint32_t word0; 1382 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1383 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1384 #define lpfc_mbx_cq_create_set_page_size_WORD word0 1385 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1386 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1387 #define lpfc_mbx_cq_create_set_num_pages_WORD word0 1388 uint32_t word1; 1389 #define lpfc_mbx_cq_create_set_evt_SHIFT 31 1390 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1391 #define lpfc_mbx_cq_create_set_evt_WORD word1 1392 #define lpfc_mbx_cq_create_set_valid_SHIFT 29 1393 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1394 #define lpfc_mbx_cq_create_set_valid_WORD word1 1395 #define lpfc_mbx_cq_create_set_cqecnt_SHIFT 27 1396 #define lpfc_mbx_cq_create_set_cqecnt_MASK 0x00000003 1397 #define lpfc_mbx_cq_create_set_cqecnt_WORD word1 1398 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1399 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1400 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1401 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1402 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1403 #define lpfc_mbx_cq_create_set_autovalid_WORD word1 1404 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1405 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1406 #define lpfc_mbx_cq_create_set_nodelay_WORD word1 1407 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1408 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1409 #define lpfc_mbx_cq_create_set_clswm_WORD word1 1410 #define lpfc_mbx_cq_create_set_cqe_cnt_hi_SHIFT 0 1411 #define lpfc_mbx_cq_create_set_cqe_cnt_hi_MASK 0x0000001F 1412 #define lpfc_mbx_cq_create_set_cqe_cnt_hi_WORD word1 1413 uint32_t word2; 1414 #define lpfc_mbx_cq_create_set_arm_SHIFT 31 1415 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1416 #define lpfc_mbx_cq_create_set_arm_WORD word2 1417 #define lpfc_mbx_cq_create_set_cqe_cnt_lo_SHIFT 16 1418 #define lpfc_mbx_cq_create_set_cqe_cnt_lo_MASK 0x00007FFF 1419 #define lpfc_mbx_cq_create_set_cqe_cnt_lo_WORD word2 1420 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1421 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1422 #define lpfc_mbx_cq_create_set_num_cq_WORD word2 1423 uint32_t word3; 1424 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1425 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1426 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1427 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1428 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1429 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1430 uint32_t word4; 1431 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1432 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1433 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1434 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1435 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1436 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1437 uint32_t word5; 1438 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1439 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1440 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1441 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1442 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1443 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1444 uint32_t word6; 1445 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1446 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1447 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1448 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1449 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1450 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1451 uint32_t word7; 1452 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1453 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1454 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1455 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1456 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1457 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1458 uint32_t word8; 1459 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1460 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1461 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1462 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1463 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1464 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1465 uint32_t word9; 1466 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1467 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1468 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1469 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1470 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1471 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1472 uint32_t word10; 1473 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1474 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1475 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1476 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1477 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1478 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1479 struct dma_address page[1]; 1480 } request; 1481 struct { 1482 uint32_t word0; 1483 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1484 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1485 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1486 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1487 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1488 #define lpfc_mbx_cq_create_set_base_id_WORD word0 1489 } response; 1490 } u; 1491 }; 1492 1493 struct lpfc_mbx_cq_destroy { 1494 struct mbox_header header; 1495 union { 1496 struct { 1497 uint32_t word0; 1498 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1499 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1500 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1501 } request; 1502 struct { 1503 uint32_t word0; 1504 } response; 1505 } u; 1506 }; 1507 1508 struct wq_context { 1509 uint32_t reserved0; 1510 uint32_t reserved1; 1511 uint32_t reserved2; 1512 uint32_t reserved3; 1513 }; 1514 1515 struct lpfc_mbx_wq_create { 1516 struct mbox_header header; 1517 union { 1518 struct { /* Version 0 Request */ 1519 uint32_t word0; 1520 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1521 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1522 #define lpfc_mbx_wq_create_num_pages_WORD word0 1523 #define lpfc_mbx_wq_create_dua_SHIFT 8 1524 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1525 #define lpfc_mbx_wq_create_dua_WORD word0 1526 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1527 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1528 #define lpfc_mbx_wq_create_cq_id_WORD word0 1529 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1530 uint32_t word9; 1531 #define lpfc_mbx_wq_create_bua_SHIFT 0 1532 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1533 #define lpfc_mbx_wq_create_bua_WORD word9 1534 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1535 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1536 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1537 } request; 1538 struct { /* Version 1 Request */ 1539 uint32_t word0; /* Word 0 is the same as in v0 */ 1540 uint32_t word1; 1541 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1542 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1543 #define lpfc_mbx_wq_create_page_size_WORD word1 1544 #define LPFC_WQ_PAGE_SIZE_4096 0x1 1545 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1546 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1547 #define lpfc_mbx_wq_create_dpp_req_WORD word1 1548 #define lpfc_mbx_wq_create_doe_SHIFT 14 1549 #define lpfc_mbx_wq_create_doe_MASK 0x00000001 1550 #define lpfc_mbx_wq_create_doe_WORD word1 1551 #define lpfc_mbx_wq_create_toe_SHIFT 13 1552 #define lpfc_mbx_wq_create_toe_MASK 0x00000001 1553 #define lpfc_mbx_wq_create_toe_WORD word1 1554 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1555 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1556 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1557 #define LPFC_WQ_WQE_SIZE_64 0x5 1558 #define LPFC_WQ_WQE_SIZE_128 0x6 1559 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1560 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1561 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1562 uint32_t word2; 1563 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1564 } request_1; 1565 struct { 1566 uint32_t word0; 1567 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1568 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1569 #define lpfc_mbx_wq_create_q_id_WORD word0 1570 uint32_t doorbell_offset; 1571 uint32_t word2; 1572 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1573 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1574 #define lpfc_mbx_wq_create_bar_set_WORD word2 1575 #define WQ_PCI_BAR_0_AND_1 0x00 1576 #define WQ_PCI_BAR_2_AND_3 0x01 1577 #define WQ_PCI_BAR_4_AND_5 0x02 1578 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1579 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1580 #define lpfc_mbx_wq_create_db_format_WORD word2 1581 } response; 1582 struct { 1583 uint32_t word0; 1584 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1585 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1586 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1587 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1588 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1589 #define lpfc_mbx_wq_create_v1_q_id_WORD word0 1590 uint32_t word1; 1591 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1592 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1593 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1594 uint32_t doorbell_offset; 1595 uint32_t word3; 1596 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1597 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1598 #define lpfc_mbx_wq_create_dpp_id_WORD word3 1599 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1600 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1601 #define lpfc_mbx_wq_create_dpp_bar_WORD word3 1602 uint32_t dpp_offset; 1603 } response_1; 1604 } u; 1605 }; 1606 1607 struct lpfc_mbx_wq_destroy { 1608 struct mbox_header header; 1609 union { 1610 struct { 1611 uint32_t word0; 1612 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1613 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1614 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1615 } request; 1616 struct { 1617 uint32_t word0; 1618 } response; 1619 } u; 1620 }; 1621 1622 #define LPFC_HDR_BUF_SIZE 128 1623 #define LPFC_DATA_BUF_SIZE 2048 1624 #define LPFC_NVMET_DATA_BUF_SIZE 128 1625 struct rq_context { 1626 uint32_t word0; 1627 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1628 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1629 #define lpfc_rq_context_rqe_count_WORD word0 1630 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1631 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1632 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1633 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1634 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1635 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1636 #define lpfc_rq_context_rqe_count_1_WORD word0 1637 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1638 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1639 #define lpfc_rq_context_rqe_size_WORD word0 1640 #define LPFC_RQE_SIZE_8 2 1641 #define LPFC_RQE_SIZE_16 3 1642 #define LPFC_RQE_SIZE_32 4 1643 #define LPFC_RQE_SIZE_64 5 1644 #define LPFC_RQE_SIZE_128 6 1645 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1646 #define lpfc_rq_context_page_size_MASK 0x000000FF 1647 #define lpfc_rq_context_page_size_WORD word0 1648 #define LPFC_RQ_PAGE_SIZE_4096 0x1 1649 uint32_t word1; 1650 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1651 #define lpfc_rq_context_data_size_MASK 0x0000FFFF 1652 #define lpfc_rq_context_data_size_WORD word1 1653 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1654 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1655 #define lpfc_rq_context_hdr_size_WORD word1 1656 uint32_t word2; 1657 #define lpfc_rq_context_cq_id_SHIFT 16 1658 #define lpfc_rq_context_cq_id_MASK 0x0000FFFF 1659 #define lpfc_rq_context_cq_id_WORD word2 1660 #define lpfc_rq_context_buf_size_SHIFT 0 1661 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1662 #define lpfc_rq_context_buf_size_WORD word2 1663 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1664 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1665 #define lpfc_rq_context_base_cq_WORD word2 1666 uint32_t buffer_size; /* Version 1 Only */ 1667 }; 1668 1669 struct lpfc_mbx_rq_create { 1670 struct mbox_header header; 1671 union { 1672 struct { 1673 uint32_t word0; 1674 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1675 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1676 #define lpfc_mbx_rq_create_num_pages_WORD word0 1677 #define lpfc_mbx_rq_create_dua_SHIFT 16 1678 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1679 #define lpfc_mbx_rq_create_dua_WORD word0 1680 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1681 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1682 #define lpfc_mbx_rq_create_bqu_WORD word0 1683 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1684 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1685 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1686 struct rq_context context; 1687 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1688 } request; 1689 struct { 1690 uint32_t word0; 1691 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1692 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1693 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1694 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1695 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1696 #define lpfc_mbx_rq_create_q_id_WORD word0 1697 uint32_t doorbell_offset; 1698 uint32_t word2; 1699 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1700 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1701 #define lpfc_mbx_rq_create_bar_set_WORD word2 1702 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1703 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1704 #define lpfc_mbx_rq_create_db_format_WORD word2 1705 } response; 1706 } u; 1707 }; 1708 1709 struct lpfc_mbx_rq_create_v2 { 1710 union lpfc_sli4_cfg_shdr cfg_shdr; 1711 union { 1712 struct { 1713 uint32_t word0; 1714 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1715 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1716 #define lpfc_mbx_rq_create_num_pages_WORD word0 1717 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1718 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1719 #define lpfc_mbx_rq_create_rq_cnt_WORD word0 1720 #define lpfc_mbx_rq_create_dua_SHIFT 16 1721 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1722 #define lpfc_mbx_rq_create_dua_WORD word0 1723 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1724 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1725 #define lpfc_mbx_rq_create_bqu_WORD word0 1726 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1727 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1728 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1729 #define lpfc_mbx_rq_create_dim_SHIFT 29 1730 #define lpfc_mbx_rq_create_dim_MASK 0x00000001 1731 #define lpfc_mbx_rq_create_dim_WORD word0 1732 #define lpfc_mbx_rq_create_dfd_SHIFT 30 1733 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1734 #define lpfc_mbx_rq_create_dfd_WORD word0 1735 #define lpfc_mbx_rq_create_dnb_SHIFT 31 1736 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1737 #define lpfc_mbx_rq_create_dnb_WORD word0 1738 struct rq_context context; 1739 struct dma_address page[1]; 1740 } request; 1741 struct { 1742 uint32_t word0; 1743 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1744 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1745 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1746 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1747 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1748 #define lpfc_mbx_rq_create_q_id_WORD word0 1749 uint32_t doorbell_offset; 1750 uint32_t word2; 1751 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1752 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1753 #define lpfc_mbx_rq_create_bar_set_WORD word2 1754 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1755 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1756 #define lpfc_mbx_rq_create_db_format_WORD word2 1757 } response; 1758 } u; 1759 }; 1760 1761 struct lpfc_mbx_rq_destroy { 1762 struct mbox_header header; 1763 union { 1764 struct { 1765 uint32_t word0; 1766 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1767 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1768 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1769 } request; 1770 struct { 1771 uint32_t word0; 1772 } response; 1773 } u; 1774 }; 1775 1776 struct mq_context { 1777 uint32_t word0; 1778 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1779 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1780 #define lpfc_mq_context_cq_id_WORD word0 1781 #define lpfc_mq_context_ring_size_SHIFT 16 1782 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1783 #define lpfc_mq_context_ring_size_WORD word0 1784 #define LPFC_MQ_RING_SIZE_16 0x5 1785 #define LPFC_MQ_RING_SIZE_32 0x6 1786 #define LPFC_MQ_RING_SIZE_64 0x7 1787 #define LPFC_MQ_RING_SIZE_128 0x8 1788 uint32_t word1; 1789 #define lpfc_mq_context_valid_SHIFT 31 1790 #define lpfc_mq_context_valid_MASK 0x00000001 1791 #define lpfc_mq_context_valid_WORD word1 1792 uint32_t reserved2; 1793 uint32_t reserved3; 1794 }; 1795 1796 struct lpfc_mbx_mq_create { 1797 struct mbox_header header; 1798 union { 1799 struct { 1800 uint32_t word0; 1801 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1802 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1803 #define lpfc_mbx_mq_create_num_pages_WORD word0 1804 struct mq_context context; 1805 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1806 } request; 1807 struct { 1808 uint32_t word0; 1809 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1810 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1811 #define lpfc_mbx_mq_create_q_id_WORD word0 1812 } response; 1813 } u; 1814 }; 1815 1816 struct lpfc_mbx_mq_create_ext { 1817 struct mbox_header header; 1818 union { 1819 struct { 1820 uint32_t word0; 1821 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1822 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1823 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1824 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1825 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1826 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1827 uint32_t async_evt_bmap; 1828 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1829 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1830 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1831 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1832 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1833 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1834 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1835 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1836 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1837 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1838 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1839 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1840 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1841 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1842 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1843 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1844 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1845 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1846 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1847 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1848 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1849 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1850 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1851 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1852 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1853 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1854 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1855 struct mq_context context; 1856 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1857 } request; 1858 struct { 1859 uint32_t word0; 1860 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1861 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1862 #define lpfc_mbx_mq_create_q_id_WORD word0 1863 } response; 1864 } u; 1865 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1866 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1867 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1868 }; 1869 1870 struct lpfc_mbx_mq_destroy { 1871 struct mbox_header header; 1872 union { 1873 struct { 1874 uint32_t word0; 1875 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1876 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1877 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1878 } request; 1879 struct { 1880 uint32_t word0; 1881 } response; 1882 } u; 1883 }; 1884 1885 /* Start Gen 2 SLI4 Mailbox definitions: */ 1886 1887 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1888 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1889 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1890 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1891 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1892 1893 struct lpfc_mbx_get_rsrc_extent_info { 1894 struct mbox_header header; 1895 union { 1896 struct { 1897 uint32_t word4; 1898 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1899 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1900 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1901 } req; 1902 struct { 1903 uint32_t word4; 1904 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1905 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1906 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1907 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1908 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1909 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1910 } rsp; 1911 } u; 1912 }; 1913 1914 struct lpfc_mbx_query_fw_config { 1915 struct mbox_header header; 1916 struct { 1917 uint32_t config_number; 1918 #define LPFC_FC_FCOE 0x00000007 1919 uint32_t asic_revision; 1920 uint32_t physical_port; 1921 uint32_t function_mode; 1922 #define LPFC_FC_INI_MODE 0x00000040 1923 #define LPFC_FC_TGT_MODE 0x00000080 1924 #define LPFC_DUA_MODE 0x00000800 1925 uint32_t oper_mode; 1926 uint32_t rsvd9[2]; 1927 uint32_t wqid_base; 1928 uint32_t wqid_tot; 1929 uint32_t rqid_base; 1930 uint32_t rqid_tot; 1931 uint32_t rsvd15[19]; 1932 uint32_t function_capabilities; 1933 uint32_t cqid_base; 1934 uint32_t cqid_tot; 1935 uint32_t eqid_base; 1936 uint32_t eqid_tot; 1937 uint32_t rsvd39[4]; 1938 } rsp; 1939 }; 1940 1941 struct lpfc_mbx_set_beacon_config { 1942 struct mbox_header header; 1943 uint32_t word4; 1944 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1945 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1946 #define lpfc_mbx_set_beacon_port_num_WORD word4 1947 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1948 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1949 #define lpfc_mbx_set_beacon_port_type_WORD word4 1950 #define lpfc_mbx_set_beacon_state_SHIFT 8 1951 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1952 #define lpfc_mbx_set_beacon_state_WORD word4 1953 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1954 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1955 #define lpfc_mbx_set_beacon_duration_WORD word4 1956 1957 /* COMMON_SET_BEACON_CONFIG_V1 */ 1958 #define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1959 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1960 #define lpfc_mbx_set_beacon_duration_v1_WORD word4 1961 uint32_t word5; /* RESERVED */ 1962 }; 1963 1964 struct lpfc_id_range { 1965 uint32_t word5; 1966 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1967 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1968 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1969 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1970 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1971 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1972 }; 1973 1974 struct lpfc_mbx_set_link_diag_state { 1975 struct mbox_header header; 1976 union { 1977 struct { 1978 uint32_t word0; 1979 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1980 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1981 #define lpfc_mbx_set_diag_state_diag_WORD word0 1982 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1983 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1984 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1985 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1986 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1987 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1988 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1989 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1990 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1991 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1992 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1993 } req; 1994 struct { 1995 uint32_t word0; 1996 } rsp; 1997 } u; 1998 }; 1999 2000 struct lpfc_mbx_set_link_diag_loopback { 2001 struct mbox_header header; 2002 union { 2003 struct { 2004 uint32_t word0; 2005 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 2006 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 2007 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 2008 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 2009 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 2010 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 2011 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3 2012 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 2013 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 2014 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 2015 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 2016 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 2017 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 2018 } req; 2019 struct { 2020 uint32_t word0; 2021 } rsp; 2022 } u; 2023 }; 2024 2025 struct lpfc_mbx_run_link_diag_test { 2026 struct mbox_header header; 2027 union { 2028 struct { 2029 uint32_t word0; 2030 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 2031 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 2032 #define lpfc_mbx_run_diag_test_link_num_WORD word0 2033 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 2034 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 2035 #define lpfc_mbx_run_diag_test_link_type_WORD word0 2036 uint32_t word1; 2037 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 2038 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 2039 #define lpfc_mbx_run_diag_test_test_id_WORD word1 2040 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 2041 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 2042 #define lpfc_mbx_run_diag_test_loops_WORD word1 2043 uint32_t word2; 2044 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 2045 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 2046 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 2047 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 2048 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 2049 #define lpfc_mbx_run_diag_test_err_act_WORD word2 2050 } req; 2051 struct { 2052 uint32_t word0; 2053 } rsp; 2054 } u; 2055 }; 2056 2057 /* 2058 * struct lpfc_mbx_alloc_rsrc_extents: 2059 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 2060 * 6 words of header + 4 words of shared subcommand header + 2061 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 2062 * 2063 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 2064 * for extents payload. 2065 * 2066 * 212/2 (bytes per extent) = 106 extents. 2067 * 106/2 (extents per word) = 53 words. 2068 * lpfc_id_range id is statically size to 53. 2069 * 2070 * This mailbox definition is used for ALLOC or GET_ALLOCATED 2071 * extent ranges. For ALLOC, the type and cnt are required. 2072 * For GET_ALLOCATED, only the type is required. 2073 */ 2074 struct lpfc_mbx_alloc_rsrc_extents { 2075 struct mbox_header header; 2076 union { 2077 struct { 2078 uint32_t word4; 2079 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 2080 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 2081 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 2082 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 2083 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 2084 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 2085 } req; 2086 struct { 2087 uint32_t word4; 2088 #define lpfc_mbx_rsrc_cnt_SHIFT 0 2089 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 2090 #define lpfc_mbx_rsrc_cnt_WORD word4 2091 struct lpfc_id_range id[53]; 2092 } rsp; 2093 } u; 2094 }; 2095 2096 /* 2097 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 2098 * structure shares the same SHIFT/MASK/WORD defines provided in the 2099 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 2100 * the structures defined above. This non-embedded structure provides for the 2101 * maximum number of extents supported by the port. 2102 */ 2103 struct lpfc_mbx_nembed_rsrc_extent { 2104 union lpfc_sli4_cfg_shdr cfg_shdr; 2105 uint32_t word4; 2106 struct lpfc_id_range id; 2107 }; 2108 2109 struct lpfc_mbx_dealloc_rsrc_extents { 2110 struct mbox_header header; 2111 struct { 2112 uint32_t word4; 2113 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 2114 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 2115 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 2116 } req; 2117 2118 }; 2119 2120 /* Start SLI4 FCoE specific mbox structures. */ 2121 2122 struct lpfc_mbx_post_hdr_tmpl { 2123 struct mbox_header header; 2124 uint32_t word10; 2125 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2126 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2127 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2128 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2129 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2130 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2131 uint32_t rpi_paddr_lo; 2132 uint32_t rpi_paddr_hi; 2133 }; 2134 2135 struct sli4_sge { /* SLI-4 */ 2136 uint32_t addr_hi; 2137 uint32_t addr_lo; 2138 2139 uint32_t word2; 2140 #define lpfc_sli4_sge_offset_SHIFT 0 2141 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2142 #define lpfc_sli4_sge_offset_WORD word2 2143 #define lpfc_sli4_sge_type_SHIFT 27 2144 #define lpfc_sli4_sge_type_MASK 0x0000000F 2145 #define lpfc_sli4_sge_type_WORD word2 2146 #define LPFC_SGE_TYPE_DATA 0x0 2147 #define LPFC_SGE_TYPE_DIF 0x4 2148 #define LPFC_SGE_TYPE_LSP 0x5 2149 #define LPFC_SGE_TYPE_PEDIF 0x6 2150 #define LPFC_SGE_TYPE_PESEED 0x7 2151 #define LPFC_SGE_TYPE_DISEED 0x8 2152 #define LPFC_SGE_TYPE_ENC 0x9 2153 #define LPFC_SGE_TYPE_ATM 0xA 2154 #define LPFC_SGE_TYPE_SKIP 0xC 2155 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2156 #define lpfc_sli4_sge_last_MASK 0x00000001 2157 #define lpfc_sli4_sge_last_WORD word2 2158 uint32_t sge_len; 2159 }; 2160 2161 struct sli4_sge_le { 2162 __le32 addr_hi; 2163 __le32 addr_lo; 2164 2165 __le32 word2; 2166 __le32 sge_len; 2167 }; 2168 2169 struct sli4_hybrid_sgl { 2170 struct list_head list_node; 2171 struct sli4_sge *dma_sgl; 2172 dma_addr_t dma_phys_sgl; 2173 }; 2174 2175 struct fcp_cmd_rsp_buf { 2176 struct list_head list_node; 2177 2178 /* for storing cmd/rsp dma alloc'ed virt_addr */ 2179 struct fcp_cmnd *fcp_cmnd; 2180 struct fcp_rsp *fcp_rsp; 2181 2182 /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */ 2183 dma_addr_t fcp_cmd_rsp_dma_handle; 2184 }; 2185 2186 struct sli4_sge_diseed { /* SLI-4 */ 2187 uint32_t ref_tag; 2188 uint32_t ref_tag_tran; 2189 2190 uint32_t word2; 2191 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 2192 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2193 #define lpfc_sli4_sge_dif_apptran_WORD word2 2194 #define lpfc_sli4_sge_dif_af_SHIFT 24 2195 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 2196 #define lpfc_sli4_sge_dif_af_WORD word2 2197 #define lpfc_sli4_sge_dif_na_SHIFT 25 2198 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 2199 #define lpfc_sli4_sge_dif_na_WORD word2 2200 #define lpfc_sli4_sge_dif_hi_SHIFT 26 2201 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2202 #define lpfc_sli4_sge_dif_hi_WORD word2 2203 #define lpfc_sli4_sge_dif_type_SHIFT 27 2204 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2205 #define lpfc_sli4_sge_dif_type_WORD word2 2206 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2207 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 2208 #define lpfc_sli4_sge_dif_last_WORD word2 2209 uint32_t word3; 2210 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 2211 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2212 #define lpfc_sli4_sge_dif_apptag_WORD word3 2213 #define lpfc_sli4_sge_dif_bs_SHIFT 16 2214 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2215 #define lpfc_sli4_sge_dif_bs_WORD word3 2216 #define lpfc_sli4_sge_dif_ai_SHIFT 19 2217 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2218 #define lpfc_sli4_sge_dif_ai_WORD word3 2219 #define lpfc_sli4_sge_dif_me_SHIFT 20 2220 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 2221 #define lpfc_sli4_sge_dif_me_WORD word3 2222 #define lpfc_sli4_sge_dif_re_SHIFT 21 2223 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 2224 #define lpfc_sli4_sge_dif_re_WORD word3 2225 #define lpfc_sli4_sge_dif_ce_SHIFT 22 2226 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2227 #define lpfc_sli4_sge_dif_ce_WORD word3 2228 #define lpfc_sli4_sge_dif_nr_SHIFT 23 2229 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2230 #define lpfc_sli4_sge_dif_nr_WORD word3 2231 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 2232 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2233 #define lpfc_sli4_sge_dif_oprx_WORD word3 2234 #define lpfc_sli4_sge_dif_optx_SHIFT 28 2235 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2236 #define lpfc_sli4_sge_dif_optx_WORD word3 2237 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2238 }; 2239 2240 struct fcf_record { 2241 uint32_t max_rcv_size; 2242 uint32_t fka_adv_period; 2243 uint32_t fip_priority; 2244 uint32_t word3; 2245 #define lpfc_fcf_record_mac_0_SHIFT 0 2246 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 2247 #define lpfc_fcf_record_mac_0_WORD word3 2248 #define lpfc_fcf_record_mac_1_SHIFT 8 2249 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 2250 #define lpfc_fcf_record_mac_1_WORD word3 2251 #define lpfc_fcf_record_mac_2_SHIFT 16 2252 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 2253 #define lpfc_fcf_record_mac_2_WORD word3 2254 #define lpfc_fcf_record_mac_3_SHIFT 24 2255 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 2256 #define lpfc_fcf_record_mac_3_WORD word3 2257 uint32_t word4; 2258 #define lpfc_fcf_record_mac_4_SHIFT 0 2259 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 2260 #define lpfc_fcf_record_mac_4_WORD word4 2261 #define lpfc_fcf_record_mac_5_SHIFT 8 2262 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 2263 #define lpfc_fcf_record_mac_5_WORD word4 2264 #define lpfc_fcf_record_fcf_avail_SHIFT 16 2265 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2266 #define lpfc_fcf_record_fcf_avail_WORD word4 2267 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2268 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2269 #define lpfc_fcf_record_mac_addr_prov_WORD word4 2270 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2271 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2272 uint32_t word5; 2273 #define lpfc_fcf_record_fab_name_0_SHIFT 0 2274 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2275 #define lpfc_fcf_record_fab_name_0_WORD word5 2276 #define lpfc_fcf_record_fab_name_1_SHIFT 8 2277 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2278 #define lpfc_fcf_record_fab_name_1_WORD word5 2279 #define lpfc_fcf_record_fab_name_2_SHIFT 16 2280 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2281 #define lpfc_fcf_record_fab_name_2_WORD word5 2282 #define lpfc_fcf_record_fab_name_3_SHIFT 24 2283 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2284 #define lpfc_fcf_record_fab_name_3_WORD word5 2285 uint32_t word6; 2286 #define lpfc_fcf_record_fab_name_4_SHIFT 0 2287 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2288 #define lpfc_fcf_record_fab_name_4_WORD word6 2289 #define lpfc_fcf_record_fab_name_5_SHIFT 8 2290 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2291 #define lpfc_fcf_record_fab_name_5_WORD word6 2292 #define lpfc_fcf_record_fab_name_6_SHIFT 16 2293 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2294 #define lpfc_fcf_record_fab_name_6_WORD word6 2295 #define lpfc_fcf_record_fab_name_7_SHIFT 24 2296 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2297 #define lpfc_fcf_record_fab_name_7_WORD word6 2298 uint32_t word7; 2299 #define lpfc_fcf_record_fc_map_0_SHIFT 0 2300 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2301 #define lpfc_fcf_record_fc_map_0_WORD word7 2302 #define lpfc_fcf_record_fc_map_1_SHIFT 8 2303 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2304 #define lpfc_fcf_record_fc_map_1_WORD word7 2305 #define lpfc_fcf_record_fc_map_2_SHIFT 16 2306 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2307 #define lpfc_fcf_record_fc_map_2_WORD word7 2308 #define lpfc_fcf_record_fcf_valid_SHIFT 24 2309 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2310 #define lpfc_fcf_record_fcf_valid_WORD word7 2311 #define lpfc_fcf_record_fcf_fc_SHIFT 25 2312 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2313 #define lpfc_fcf_record_fcf_fc_WORD word7 2314 #define lpfc_fcf_record_fcf_sol_SHIFT 31 2315 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2316 #define lpfc_fcf_record_fcf_sol_WORD word7 2317 uint32_t word8; 2318 #define lpfc_fcf_record_fcf_index_SHIFT 0 2319 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2320 #define lpfc_fcf_record_fcf_index_WORD word8 2321 #define lpfc_fcf_record_fcf_state_SHIFT 16 2322 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2323 #define lpfc_fcf_record_fcf_state_WORD word8 2324 uint8_t vlan_bitmap[512]; 2325 uint32_t word137; 2326 #define lpfc_fcf_record_switch_name_0_SHIFT 0 2327 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2328 #define lpfc_fcf_record_switch_name_0_WORD word137 2329 #define lpfc_fcf_record_switch_name_1_SHIFT 8 2330 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2331 #define lpfc_fcf_record_switch_name_1_WORD word137 2332 #define lpfc_fcf_record_switch_name_2_SHIFT 16 2333 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2334 #define lpfc_fcf_record_switch_name_2_WORD word137 2335 #define lpfc_fcf_record_switch_name_3_SHIFT 24 2336 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2337 #define lpfc_fcf_record_switch_name_3_WORD word137 2338 uint32_t word138; 2339 #define lpfc_fcf_record_switch_name_4_SHIFT 0 2340 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2341 #define lpfc_fcf_record_switch_name_4_WORD word138 2342 #define lpfc_fcf_record_switch_name_5_SHIFT 8 2343 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2344 #define lpfc_fcf_record_switch_name_5_WORD word138 2345 #define lpfc_fcf_record_switch_name_6_SHIFT 16 2346 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2347 #define lpfc_fcf_record_switch_name_6_WORD word138 2348 #define lpfc_fcf_record_switch_name_7_SHIFT 24 2349 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2350 #define lpfc_fcf_record_switch_name_7_WORD word138 2351 }; 2352 2353 struct lpfc_mbx_read_fcf_tbl { 2354 union lpfc_sli4_cfg_shdr cfg_shdr; 2355 union { 2356 struct { 2357 uint32_t word10; 2358 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2359 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2360 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2361 } request; 2362 struct { 2363 uint32_t eventag; 2364 } response; 2365 } u; 2366 uint32_t word11; 2367 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2368 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2369 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2370 }; 2371 2372 struct lpfc_mbx_add_fcf_tbl_entry { 2373 union lpfc_sli4_cfg_shdr cfg_shdr; 2374 uint32_t word10; 2375 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2376 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2377 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2378 struct lpfc_mbx_sge fcf_sge; 2379 }; 2380 2381 struct lpfc_mbx_del_fcf_tbl_entry { 2382 struct mbox_header header; 2383 uint32_t word10; 2384 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2385 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2386 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 2387 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2388 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2389 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 2390 }; 2391 2392 struct lpfc_mbx_redisc_fcf_tbl { 2393 struct mbox_header header; 2394 uint32_t word10; 2395 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 2396 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2397 #define lpfc_mbx_redisc_fcf_count_WORD word10 2398 uint32_t resvd; 2399 uint32_t word12; 2400 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 2401 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2402 #define lpfc_mbx_redisc_fcf_index_WORD word12 2403 }; 2404 2405 /* Status field for embedded SLI_CONFIG mailbox command */ 2406 #define STATUS_SUCCESS 0x0 2407 #define STATUS_FAILED 0x1 2408 #define STATUS_ILLEGAL_REQUEST 0x2 2409 #define STATUS_ILLEGAL_FIELD 0x3 2410 #define STATUS_INSUFFICIENT_BUFFER 0x4 2411 #define STATUS_UNAUTHORIZED_REQUEST 0x5 2412 #define STATUS_FLASHROM_SAVE_FAILED 0x17 2413 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 2414 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2415 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2416 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2417 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2418 #define STATUS_ASSERT_FAILED 0x1e 2419 #define STATUS_INVALID_SESSION 0x1f 2420 #define STATUS_INVALID_CONNECTION 0x20 2421 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2422 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2423 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2424 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2425 #define STATUS_FLASHROM_READ_FAILED 0x27 2426 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 2427 #define STATUS_ERROR_ACITMAIN 0x2a 2428 #define STATUS_REBOOT_REQUIRED 0x2c 2429 #define STATUS_FCF_IN_USE 0x3a 2430 #define STATUS_FCF_TABLE_EMPTY 0x43 2431 2432 /* 2433 * Additional status field for embedded SLI_CONFIG mailbox 2434 * command. 2435 */ 2436 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2437 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2438 #define ADD_STATUS_INVALID_REQUEST 0x4B 2439 #define ADD_STATUS_INVALID_OBJECT_NAME 0xA0 2440 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58 2441 2442 struct lpfc_mbx_sli4_config { 2443 struct mbox_header header; 2444 }; 2445 2446 struct lpfc_mbx_init_vfi { 2447 uint32_t word1; 2448 #define lpfc_init_vfi_vr_SHIFT 31 2449 #define lpfc_init_vfi_vr_MASK 0x00000001 2450 #define lpfc_init_vfi_vr_WORD word1 2451 #define lpfc_init_vfi_vt_SHIFT 30 2452 #define lpfc_init_vfi_vt_MASK 0x00000001 2453 #define lpfc_init_vfi_vt_WORD word1 2454 #define lpfc_init_vfi_vf_SHIFT 29 2455 #define lpfc_init_vfi_vf_MASK 0x00000001 2456 #define lpfc_init_vfi_vf_WORD word1 2457 #define lpfc_init_vfi_vp_SHIFT 28 2458 #define lpfc_init_vfi_vp_MASK 0x00000001 2459 #define lpfc_init_vfi_vp_WORD word1 2460 #define lpfc_init_vfi_vfi_SHIFT 0 2461 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2462 #define lpfc_init_vfi_vfi_WORD word1 2463 uint32_t word2; 2464 #define lpfc_init_vfi_vpi_SHIFT 16 2465 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2466 #define lpfc_init_vfi_vpi_WORD word2 2467 #define lpfc_init_vfi_fcfi_SHIFT 0 2468 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2469 #define lpfc_init_vfi_fcfi_WORD word2 2470 uint32_t word3; 2471 #define lpfc_init_vfi_pri_SHIFT 13 2472 #define lpfc_init_vfi_pri_MASK 0x00000007 2473 #define lpfc_init_vfi_pri_WORD word3 2474 #define lpfc_init_vfi_vf_id_SHIFT 1 2475 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2476 #define lpfc_init_vfi_vf_id_WORD word3 2477 uint32_t word4; 2478 #define lpfc_init_vfi_hop_count_SHIFT 24 2479 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 2480 #define lpfc_init_vfi_hop_count_WORD word4 2481 }; 2482 #define MBX_VFI_IN_USE 0x9F02 2483 2484 2485 struct lpfc_mbx_reg_vfi { 2486 uint32_t word1; 2487 #define lpfc_reg_vfi_upd_SHIFT 29 2488 #define lpfc_reg_vfi_upd_MASK 0x00000001 2489 #define lpfc_reg_vfi_upd_WORD word1 2490 #define lpfc_reg_vfi_vp_SHIFT 28 2491 #define lpfc_reg_vfi_vp_MASK 0x00000001 2492 #define lpfc_reg_vfi_vp_WORD word1 2493 #define lpfc_reg_vfi_vfi_SHIFT 0 2494 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2495 #define lpfc_reg_vfi_vfi_WORD word1 2496 uint32_t word2; 2497 #define lpfc_reg_vfi_vpi_SHIFT 16 2498 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2499 #define lpfc_reg_vfi_vpi_WORD word2 2500 #define lpfc_reg_vfi_fcfi_SHIFT 0 2501 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2502 #define lpfc_reg_vfi_fcfi_WORD word2 2503 uint32_t wwn[2]; 2504 struct ulp_bde64 bde; 2505 uint32_t e_d_tov; 2506 uint32_t r_a_tov; 2507 uint32_t word10; 2508 #define lpfc_reg_vfi_nport_id_SHIFT 0 2509 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2510 #define lpfc_reg_vfi_nport_id_WORD word10 2511 #define lpfc_reg_vfi_bbcr_SHIFT 27 2512 #define lpfc_reg_vfi_bbcr_MASK 0x00000001 2513 #define lpfc_reg_vfi_bbcr_WORD word10 2514 #define lpfc_reg_vfi_bbscn_SHIFT 28 2515 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2516 #define lpfc_reg_vfi_bbscn_WORD word10 2517 }; 2518 2519 struct lpfc_mbx_init_vpi { 2520 uint32_t word1; 2521 #define lpfc_init_vpi_vfi_SHIFT 16 2522 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2523 #define lpfc_init_vpi_vfi_WORD word1 2524 #define lpfc_init_vpi_vpi_SHIFT 0 2525 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2526 #define lpfc_init_vpi_vpi_WORD word1 2527 }; 2528 2529 struct lpfc_mbx_read_vpi { 2530 uint32_t word1_rsvd; 2531 uint32_t word2; 2532 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2533 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2534 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2535 uint32_t word3_rsvd; 2536 uint32_t word4; 2537 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2538 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2539 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2540 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2541 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2542 #define lpfc_mbx_read_vpi_pb_WORD word4 2543 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2544 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2545 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2546 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2547 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2548 #define lpfc_mbx_read_vpi_ns_WORD word4 2549 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2550 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2551 #define lpfc_mbx_read_vpi_hl_WORD word4 2552 uint32_t word5_rsvd; 2553 uint32_t word6; 2554 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2555 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2556 #define lpfc_mbx_read_vpi_vpi_WORD word6 2557 uint32_t word7; 2558 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2559 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2560 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2561 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2562 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2563 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2564 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2565 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2566 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2567 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2568 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2569 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2570 uint32_t word8; 2571 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2572 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2573 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2574 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2575 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2576 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2577 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2578 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2579 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2580 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2581 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2582 #define lpfc_mbx_read_vpi_vv_WORD word8 2583 }; 2584 2585 struct lpfc_mbx_unreg_vfi { 2586 uint32_t word1_rsvd; 2587 uint32_t word2; 2588 #define lpfc_unreg_vfi_vfi_SHIFT 0 2589 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2590 #define lpfc_unreg_vfi_vfi_WORD word2 2591 }; 2592 2593 struct lpfc_mbx_resume_rpi { 2594 uint32_t word1; 2595 #define lpfc_resume_rpi_index_SHIFT 0 2596 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2597 #define lpfc_resume_rpi_index_WORD word1 2598 #define lpfc_resume_rpi_ii_SHIFT 30 2599 #define lpfc_resume_rpi_ii_MASK 0x00000003 2600 #define lpfc_resume_rpi_ii_WORD word1 2601 #define RESUME_INDEX_RPI 0 2602 #define RESUME_INDEX_VPI 1 2603 #define RESUME_INDEX_VFI 2 2604 #define RESUME_INDEX_FCFI 3 2605 uint32_t event_tag; 2606 }; 2607 2608 #define REG_FCF_INVALID_QID 0xFFFF 2609 struct lpfc_mbx_reg_fcfi { 2610 uint32_t word1; 2611 #define lpfc_reg_fcfi_info_index_SHIFT 0 2612 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2613 #define lpfc_reg_fcfi_info_index_WORD word1 2614 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2615 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2616 #define lpfc_reg_fcfi_fcfi_WORD word1 2617 uint32_t word2; 2618 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2619 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2620 #define lpfc_reg_fcfi_rq_id1_WORD word2 2621 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2622 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2623 #define lpfc_reg_fcfi_rq_id0_WORD word2 2624 uint32_t word3; 2625 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2626 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2627 #define lpfc_reg_fcfi_rq_id3_WORD word3 2628 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2629 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2630 #define lpfc_reg_fcfi_rq_id2_WORD word3 2631 uint32_t word4; 2632 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2633 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2634 #define lpfc_reg_fcfi_type_match0_WORD word4 2635 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2636 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2637 #define lpfc_reg_fcfi_type_mask0_WORD word4 2638 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2639 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2640 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2641 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2642 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2643 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2644 uint32_t word5; 2645 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2646 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2647 #define lpfc_reg_fcfi_type_match1_WORD word5 2648 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2649 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2650 #define lpfc_reg_fcfi_type_mask1_WORD word5 2651 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2652 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2653 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2654 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2655 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2656 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2657 uint32_t word6; 2658 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2659 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2660 #define lpfc_reg_fcfi_type_match2_WORD word6 2661 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2662 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2663 #define lpfc_reg_fcfi_type_mask2_WORD word6 2664 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2665 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2666 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2667 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2668 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2669 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2670 uint32_t word7; 2671 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2672 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2673 #define lpfc_reg_fcfi_type_match3_WORD word7 2674 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2675 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2676 #define lpfc_reg_fcfi_type_mask3_WORD word7 2677 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2678 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2679 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2680 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2681 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2682 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2683 uint32_t word8; 2684 #define lpfc_reg_fcfi_mam_SHIFT 13 2685 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2686 #define lpfc_reg_fcfi_mam_WORD word8 2687 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2688 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2689 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2690 #define lpfc_reg_fcfi_vv_SHIFT 12 2691 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2692 #define lpfc_reg_fcfi_vv_WORD word8 2693 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2694 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2695 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2696 }; 2697 2698 struct lpfc_mbx_reg_fcfi_mrq { 2699 uint32_t word1; 2700 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2701 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2702 #define lpfc_reg_fcfi_mrq_info_index_WORD word1 2703 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2704 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2705 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2706 uint32_t word2; 2707 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2708 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2709 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2710 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2711 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2712 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2713 uint32_t word3; 2714 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2715 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2716 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2717 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2718 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2719 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2720 uint32_t word4; 2721 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2722 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2723 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2724 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2725 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2726 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2727 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2728 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2729 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2730 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2731 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2732 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2733 uint32_t word5; 2734 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2735 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2736 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2737 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2738 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2739 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2740 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2741 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2742 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2743 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2744 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2745 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2746 uint32_t word6; 2747 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2748 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2749 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2750 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2751 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2752 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2753 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2754 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2755 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2756 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2757 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2758 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2759 uint32_t word7; 2760 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2761 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2762 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2763 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2764 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2765 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2766 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2767 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2768 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2769 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2770 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2771 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2772 uint32_t word8; 2773 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2774 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2775 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2776 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2777 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2778 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2779 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2780 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2781 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2782 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2783 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2784 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2785 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2786 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2787 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2788 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2789 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2790 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2791 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2792 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2793 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2794 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2795 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2796 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2797 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2798 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2799 #define lpfc_reg_fcfi_mrq_pt7_WORD word8 2800 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2801 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2802 #define lpfc_reg_fcfi_mrq_pt6_WORD word8 2803 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2804 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2805 #define lpfc_reg_fcfi_mrq_pt5_WORD word8 2806 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2807 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2808 #define lpfc_reg_fcfi_mrq_pt4_WORD word8 2809 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2810 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2811 #define lpfc_reg_fcfi_mrq_pt3_WORD word8 2812 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2813 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2814 #define lpfc_reg_fcfi_mrq_pt2_WORD word8 2815 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2816 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2817 #define lpfc_reg_fcfi_mrq_pt1_WORD word8 2818 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2819 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2820 #define lpfc_reg_fcfi_mrq_pt0_WORD word8 2821 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2822 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2823 #define lpfc_reg_fcfi_mrq_xmv_WORD word8 2824 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2825 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2826 #define lpfc_reg_fcfi_mrq_mode_WORD word8 2827 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2828 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2829 #define lpfc_reg_fcfi_mrq_vv_WORD word8 2830 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2831 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2832 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2833 uint32_t word9; 2834 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2835 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2836 #define lpfc_reg_fcfi_mrq_policy_WORD word9 2837 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2838 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2839 #define lpfc_reg_fcfi_mrq_filter_WORD word9 2840 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2841 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2842 #define lpfc_reg_fcfi_mrq_npairs_WORD word9 2843 uint32_t word10; 2844 uint32_t word11; 2845 uint32_t word12; 2846 uint32_t word13; 2847 uint32_t word14; 2848 uint32_t word15; 2849 uint32_t word16; 2850 }; 2851 2852 struct lpfc_mbx_unreg_fcfi { 2853 uint32_t word1_rsv; 2854 uint32_t word2; 2855 #define lpfc_unreg_fcfi_SHIFT 0 2856 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2857 #define lpfc_unreg_fcfi_WORD word2 2858 }; 2859 2860 struct lpfc_mbx_read_rev { 2861 uint32_t word1; 2862 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2863 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2864 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2865 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2866 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2867 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2868 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2869 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2870 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2871 #define LPFC_PREDCBX_CEE_MODE 0 2872 #define LPFC_DCBX_CEE_MODE 1 2873 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2874 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2875 #define lpfc_mbx_rd_rev_vpd_WORD word1 2876 uint32_t first_hw_rev; 2877 #define LPFC_G7_ASIC_1 0xd 2878 uint32_t second_hw_rev; 2879 uint32_t word4_rsvd; 2880 uint32_t third_hw_rev; 2881 uint32_t word6; 2882 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2883 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2884 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2885 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2886 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2887 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2888 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2889 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2890 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2891 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2892 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2893 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2894 uint32_t word7_rsvd; 2895 uint32_t fw_id_rev; 2896 uint8_t fw_name[16]; 2897 uint32_t ulp_fw_id_rev; 2898 uint8_t ulp_fw_name[16]; 2899 uint32_t word18_47_rsvd[30]; 2900 uint32_t word48; 2901 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2902 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2903 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2904 uint32_t vpd_paddr_low; 2905 uint32_t vpd_paddr_high; 2906 uint32_t avail_vpd_len; 2907 uint32_t rsvd_52_63[12]; 2908 }; 2909 2910 struct lpfc_mbx_read_config { 2911 uint32_t word1; 2912 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2913 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2914 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2915 #define lpfc_mbx_rd_conf_fawwpn_SHIFT 30 2916 #define lpfc_mbx_rd_conf_fawwpn_MASK 0x00000001 2917 #define lpfc_mbx_rd_conf_fawwpn_WORD word1 2918 #define lpfc_mbx_rd_conf_wcs_SHIFT 28 /* warning signaling */ 2919 #define lpfc_mbx_rd_conf_wcs_MASK 0x00000001 2920 #define lpfc_mbx_rd_conf_wcs_WORD word1 2921 #define lpfc_mbx_rd_conf_acs_SHIFT 27 /* alarm signaling */ 2922 #define lpfc_mbx_rd_conf_acs_MASK 0x00000001 2923 #define lpfc_mbx_rd_conf_acs_WORD word1 2924 uint32_t word2; 2925 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2926 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2927 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2928 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2929 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2930 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2931 #define LPFC_LNK_TYPE_GE 0 2932 #define LPFC_LNK_TYPE_FC 1 2933 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2934 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2935 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2936 #define lpfc_mbx_rd_conf_trunk_SHIFT 12 2937 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F 2938 #define lpfc_mbx_rd_conf_trunk_WORD word2 2939 #define lpfc_mbx_rd_conf_pt_SHIFT 20 2940 #define lpfc_mbx_rd_conf_pt_MASK 0x00000003 2941 #define lpfc_mbx_rd_conf_pt_WORD word2 2942 #define lpfc_mbx_rd_conf_tf_SHIFT 22 2943 #define lpfc_mbx_rd_conf_tf_MASK 0x00000001 2944 #define lpfc_mbx_rd_conf_tf_WORD word2 2945 #define lpfc_mbx_rd_conf_ptv_SHIFT 23 2946 #define lpfc_mbx_rd_conf_ptv_MASK 0x00000001 2947 #define lpfc_mbx_rd_conf_ptv_WORD word2 2948 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2949 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2950 #define lpfc_mbx_rd_conf_topology_WORD word2 2951 uint32_t word3; 2952 #define lpfc_mbx_rd_conf_fedif_SHIFT 6 2953 #define lpfc_mbx_rd_conf_fedif_MASK 0x00000001 2954 #define lpfc_mbx_rd_conf_fedif_WORD word3 2955 uint32_t word4; 2956 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2957 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2958 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2959 uint32_t rsvd_5; 2960 uint32_t word6; 2961 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2962 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2963 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2964 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2965 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2966 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2967 uint32_t rsvd_7; 2968 uint32_t word8; 2969 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2970 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2971 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2972 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2973 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2974 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2975 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2976 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2977 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2978 uint32_t word9; 2979 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2980 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2981 #define lpfc_mbx_rd_conf_lmt_WORD word9 2982 uint32_t rsvd_10; 2983 uint32_t rsvd_11; 2984 uint32_t word12; 2985 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2986 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2987 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2988 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2989 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2990 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2991 uint32_t word13; 2992 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2993 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2994 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2995 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2996 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2997 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2998 uint32_t word14; 2999 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 3000 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 3001 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 3002 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 3003 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 3004 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 3005 uint32_t word15; 3006 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 3007 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 3008 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 3009 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 3010 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 3011 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 3012 uint32_t word16; 3013 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 3014 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 3015 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 3016 uint32_t word17; 3017 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 3018 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 3019 #define lpfc_mbx_rd_conf_rq_count_WORD word17 3020 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 3021 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 3022 #define lpfc_mbx_rd_conf_eq_count_WORD word17 3023 uint32_t word18; 3024 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 3025 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 3026 #define lpfc_mbx_rd_conf_wq_count_WORD word18 3027 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 3028 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 3029 #define lpfc_mbx_rd_conf_cq_count_WORD word18 3030 }; 3031 3032 struct lpfc_mbx_request_features { 3033 uint32_t word1; 3034 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 3035 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 3036 #define lpfc_mbx_rq_ftr_qry_WORD word1 3037 uint32_t word2; 3038 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 3039 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 3040 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 3041 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 3042 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 3043 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 3044 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 3045 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 3046 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 3047 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 3048 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 3049 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 3050 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 3051 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 3052 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 3053 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 3054 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 3055 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 3056 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 3057 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 3058 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 3059 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 3060 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 3061 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 3062 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 3063 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 3064 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 3065 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 3066 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 3067 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 3068 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 3069 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 3070 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 3071 #define lpfc_mbx_rq_ftr_rq_ashdr_SHIFT 17 3072 #define lpfc_mbx_rq_ftr_rq_ashdr_MASK 0x00000001 3073 #define lpfc_mbx_rq_ftr_rq_ashdr_WORD word2 3074 uint32_t word3; 3075 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 3076 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 3077 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 3078 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 3079 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 3080 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 3081 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 3082 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 3083 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 3084 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 3085 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 3086 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 3087 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 3088 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 3089 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 3090 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 3091 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 3092 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 3093 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 3094 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 3095 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 3096 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 3097 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 3098 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 3099 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 3100 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 3101 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 3102 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 3103 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 3104 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 3105 #define lpfc_mbx_rq_ftr_rsp_ashdr_SHIFT 17 3106 #define lpfc_mbx_rq_ftr_rsp_ashdr_MASK 0x00000001 3107 #define lpfc_mbx_rq_ftr_rsp_ashdr_WORD word3 3108 }; 3109 3110 struct lpfc_mbx_memory_dump_type3 { 3111 uint32_t word1; 3112 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 3113 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 3114 #define lpfc_mbx_memory_dump_type3_type_WORD word1 3115 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 3116 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 3117 #define lpfc_mbx_memory_dump_type3_link_WORD word1 3118 uint32_t word2; 3119 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 3120 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3121 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3122 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3123 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3124 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 3125 uint32_t word3; 3126 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3127 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3128 #define lpfc_mbx_memory_dump_type3_length_WORD word3 3129 uint32_t addr_lo; 3130 uint32_t addr_hi; 3131 uint32_t return_len; 3132 }; 3133 3134 #define DMP_PAGE_A0 0xa0 3135 #define DMP_PAGE_A2 0xa2 3136 #define DMP_SFF_PAGE_A0_SIZE 256 3137 #define DMP_SFF_PAGE_A2_SIZE 256 3138 3139 #define SFP_WAVELENGTH_LC1310 1310 3140 #define SFP_WAVELENGTH_LL1550 1550 3141 3142 3143 /* 3144 * * SFF-8472 TABLE 3.4 3145 * */ 3146 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3147 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3148 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3149 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3150 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3151 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3152 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3153 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3154 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3155 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3156 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3157 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3158 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3159 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3160 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3161 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3162 3163 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3164 3165 #define SSF_IDENTIFIER 0 3166 #define SSF_EXT_IDENTIFIER 1 3167 #define SSF_CONNECTOR 2 3168 #define SSF_TRANSCEIVER_CODE_B0 3 3169 #define SSF_TRANSCEIVER_CODE_B1 4 3170 #define SSF_TRANSCEIVER_CODE_B2 5 3171 #define SSF_TRANSCEIVER_CODE_B3 6 3172 #define SSF_TRANSCEIVER_CODE_B4 7 3173 #define SSF_TRANSCEIVER_CODE_B5 8 3174 #define SSF_TRANSCEIVER_CODE_B6 9 3175 #define SSF_TRANSCEIVER_CODE_B7 10 3176 #define SSF_ENCODING 11 3177 #define SSF_BR_NOMINAL 12 3178 #define SSF_RATE_IDENTIFIER 13 3179 #define SSF_LENGTH_9UM_KM 14 3180 #define SSF_LENGTH_9UM 15 3181 #define SSF_LENGTH_50UM_OM2 16 3182 #define SSF_LENGTH_62UM_OM1 17 3183 #define SFF_LENGTH_COPPER 18 3184 #define SSF_LENGTH_50UM_OM3 19 3185 #define SSF_VENDOR_NAME 20 3186 #define SSF_TRANSCEIVER2 36 3187 #define SSF_VENDOR_OUI 37 3188 #define SSF_VENDOR_PN 40 3189 #define SSF_VENDOR_REV 56 3190 #define SSF_WAVELENGTH_B1 60 3191 #define SSF_WAVELENGTH_B0 61 3192 #define SSF_CC_BASE 63 3193 #define SSF_OPTIONS_B1 64 3194 #define SSF_OPTIONS_B0 65 3195 #define SSF_BR_MAX 66 3196 #define SSF_BR_MIN 67 3197 #define SSF_VENDOR_SN 68 3198 #define SSF_DATE_CODE 84 3199 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 3200 #define SSF_ENHANCED_OPTIONS 93 3201 #define SFF_8472_COMPLIANCE 94 3202 #define SSF_CC_EXT 95 3203 #define SSF_A0_VENDOR_SPECIFIC 96 3204 3205 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3206 3207 #define SSF_TEMP_HIGH_ALARM 0 3208 #define SSF_TEMP_LOW_ALARM 2 3209 #define SSF_TEMP_HIGH_WARNING 4 3210 #define SSF_TEMP_LOW_WARNING 6 3211 #define SSF_VOLTAGE_HIGH_ALARM 8 3212 #define SSF_VOLTAGE_LOW_ALARM 10 3213 #define SSF_VOLTAGE_HIGH_WARNING 12 3214 #define SSF_VOLTAGE_LOW_WARNING 14 3215 #define SSF_BIAS_HIGH_ALARM 16 3216 #define SSF_BIAS_LOW_ALARM 18 3217 #define SSF_BIAS_HIGH_WARNING 20 3218 #define SSF_BIAS_LOW_WARNING 22 3219 #define SSF_TXPOWER_HIGH_ALARM 24 3220 #define SSF_TXPOWER_LOW_ALARM 26 3221 #define SSF_TXPOWER_HIGH_WARNING 28 3222 #define SSF_TXPOWER_LOW_WARNING 30 3223 #define SSF_RXPOWER_HIGH_ALARM 32 3224 #define SSF_RXPOWER_LOW_ALARM 34 3225 #define SSF_RXPOWER_HIGH_WARNING 36 3226 #define SSF_RXPOWER_LOW_WARNING 38 3227 #define SSF_EXT_CAL_CONSTANTS 56 3228 #define SSF_CC_DMI 95 3229 #define SFF_TEMPERATURE_B1 96 3230 #define SFF_TEMPERATURE_B0 97 3231 #define SFF_VCC_B1 98 3232 #define SFF_VCC_B0 99 3233 #define SFF_TX_BIAS_CURRENT_B1 100 3234 #define SFF_TX_BIAS_CURRENT_B0 101 3235 #define SFF_TXPOWER_B1 102 3236 #define SFF_TXPOWER_B0 103 3237 #define SFF_RXPOWER_B1 104 3238 #define SFF_RXPOWER_B0 105 3239 #define SSF_STATUS_CONTROL 110 3240 #define SSF_ALARM_FLAGS 112 3241 #define SSF_WARNING_FLAGS 116 3242 #define SSF_EXT_TATUS_CONTROL_B1 118 3243 #define SSF_EXT_TATUS_CONTROL_B0 119 3244 #define SSF_A2_VENDOR_SPECIFIC 120 3245 #define SSF_USER_EEPROM 128 3246 #define SSF_VENDOR_CONTROL 148 3247 3248 3249 /* 3250 * Tranceiver codes Fibre Channel SFF-8472 3251 * Table 3.5. 3252 */ 3253 3254 struct sff_trasnceiver_codes_byte0 { 3255 uint8_t inifiband:4; 3256 uint8_t teng_ethernet:4; 3257 }; 3258 3259 struct sff_trasnceiver_codes_byte1 { 3260 uint8_t sonet:6; 3261 uint8_t escon:2; 3262 }; 3263 3264 struct sff_trasnceiver_codes_byte2 { 3265 uint8_t soNet:8; 3266 }; 3267 3268 struct sff_trasnceiver_codes_byte3 { 3269 uint8_t ethernet:8; 3270 }; 3271 3272 struct sff_trasnceiver_codes_byte4 { 3273 uint8_t fc_el_lo:1; 3274 uint8_t fc_lw_laser:1; 3275 uint8_t fc_sw_laser:1; 3276 uint8_t fc_md_distance:1; 3277 uint8_t fc_lg_distance:1; 3278 uint8_t fc_int_distance:1; 3279 uint8_t fc_short_distance:1; 3280 uint8_t fc_vld_distance:1; 3281 }; 3282 3283 struct sff_trasnceiver_codes_byte5 { 3284 uint8_t reserved1:1; 3285 uint8_t reserved2:1; 3286 uint8_t fc_sfp_active:1; /* Active cable */ 3287 uint8_t fc_sfp_passive:1; /* Passive cable */ 3288 uint8_t fc_lw_laser:1; /* Longwave laser */ 3289 uint8_t fc_sw_laser_sl:1; 3290 uint8_t fc_sw_laser_sn:1; 3291 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3292 }; 3293 3294 struct sff_trasnceiver_codes_byte6 { 3295 uint8_t fc_tm_sm:1; /* Single Mode */ 3296 uint8_t reserved:1; 3297 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3298 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3299 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3300 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3301 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3302 }; 3303 3304 struct sff_trasnceiver_codes_byte7 { 3305 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3306 uint8_t speed_chk_ecc:1; 3307 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3308 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3309 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3310 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3311 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3312 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3313 }; 3314 3315 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3316 struct user_eeprom { 3317 uint8_t vendor_name[16]; 3318 uint8_t vendor_oui[3]; 3319 uint8_t vendor_pn[816]; 3320 uint8_t vendor_rev[4]; 3321 uint8_t vendor_sn[16]; 3322 uint8_t datecode[6]; 3323 uint8_t lot_code[2]; 3324 uint8_t reserved191[57]; 3325 }; 3326 3327 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3328 &(~((SLI4_PAGE_SIZE)-1))) 3329 3330 struct lpfc_sli4_parameters { 3331 uint32_t word0; 3332 #define cfg_prot_type_SHIFT 0 3333 #define cfg_prot_type_MASK 0x000000FF 3334 #define cfg_prot_type_WORD word0 3335 uint32_t word1; 3336 #define cfg_ft_SHIFT 0 3337 #define cfg_ft_MASK 0x00000001 3338 #define cfg_ft_WORD word1 3339 #define cfg_sli_rev_SHIFT 4 3340 #define cfg_sli_rev_MASK 0x0000000f 3341 #define cfg_sli_rev_WORD word1 3342 #define cfg_sli_family_SHIFT 8 3343 #define cfg_sli_family_MASK 0x0000000f 3344 #define cfg_sli_family_WORD word1 3345 #define cfg_if_type_SHIFT 12 3346 #define cfg_if_type_MASK 0x0000000f 3347 #define cfg_if_type_WORD word1 3348 #define cfg_sli_hint_1_SHIFT 16 3349 #define cfg_sli_hint_1_MASK 0x000000ff 3350 #define cfg_sli_hint_1_WORD word1 3351 #define cfg_sli_hint_2_SHIFT 24 3352 #define cfg_sli_hint_2_MASK 0x0000001f 3353 #define cfg_sli_hint_2_WORD word1 3354 uint32_t word2; 3355 #define cfg_eqav_SHIFT 31 3356 #define cfg_eqav_MASK 0x00000001 3357 #define cfg_eqav_WORD word2 3358 uint32_t word3; 3359 uint32_t word4; 3360 #define cfg_cqv_SHIFT 14 3361 #define cfg_cqv_MASK 0x00000003 3362 #define cfg_cqv_WORD word4 3363 #define cfg_cqpsize_SHIFT 16 3364 #define cfg_cqpsize_MASK 0x000000ff 3365 #define cfg_cqpsize_WORD word4 3366 #define cfg_cqav_SHIFT 31 3367 #define cfg_cqav_MASK 0x00000001 3368 #define cfg_cqav_WORD word4 3369 uint32_t word5; 3370 uint32_t word6; 3371 #define cfg_mqv_SHIFT 14 3372 #define cfg_mqv_MASK 0x00000003 3373 #define cfg_mqv_WORD word6 3374 uint32_t word7; 3375 uint32_t word8; 3376 #define cfg_wqpcnt_SHIFT 0 3377 #define cfg_wqpcnt_MASK 0x0000000f 3378 #define cfg_wqpcnt_WORD word8 3379 #define cfg_wqsize_SHIFT 8 3380 #define cfg_wqsize_MASK 0x0000000f 3381 #define cfg_wqsize_WORD word8 3382 #define cfg_wqv_SHIFT 14 3383 #define cfg_wqv_MASK 0x00000003 3384 #define cfg_wqv_WORD word8 3385 #define cfg_wqpsize_SHIFT 16 3386 #define cfg_wqpsize_MASK 0x000000ff 3387 #define cfg_wqpsize_WORD word8 3388 uint32_t word9; 3389 uint32_t word10; 3390 #define cfg_rqv_SHIFT 14 3391 #define cfg_rqv_MASK 0x00000003 3392 #define cfg_rqv_WORD word10 3393 uint32_t word11; 3394 #define cfg_rq_db_window_SHIFT 28 3395 #define cfg_rq_db_window_MASK 0x0000000f 3396 #define cfg_rq_db_window_WORD word11 3397 uint32_t word12; 3398 #define cfg_fcoe_SHIFT 0 3399 #define cfg_fcoe_MASK 0x00000001 3400 #define cfg_fcoe_WORD word12 3401 #define cfg_ext_SHIFT 1 3402 #define cfg_ext_MASK 0x00000001 3403 #define cfg_ext_WORD word12 3404 #define cfg_hdrr_SHIFT 2 3405 #define cfg_hdrr_MASK 0x00000001 3406 #define cfg_hdrr_WORD word12 3407 #define cfg_phwq_SHIFT 15 3408 #define cfg_phwq_MASK 0x00000001 3409 #define cfg_phwq_WORD word12 3410 #define cfg_oas_SHIFT 25 3411 #define cfg_oas_MASK 0x00000001 3412 #define cfg_oas_WORD word12 3413 #define cfg_loopbk_scope_SHIFT 28 3414 #define cfg_loopbk_scope_MASK 0x0000000f 3415 #define cfg_loopbk_scope_WORD word12 3416 uint32_t sge_supp_len; 3417 uint32_t word14; 3418 #define cfg_sgl_page_cnt_SHIFT 0 3419 #define cfg_sgl_page_cnt_MASK 0x0000000f 3420 #define cfg_sgl_page_cnt_WORD word14 3421 #define cfg_sgl_page_size_SHIFT 8 3422 #define cfg_sgl_page_size_MASK 0x000000ff 3423 #define cfg_sgl_page_size_WORD word14 3424 #define cfg_sgl_pp_align_SHIFT 16 3425 #define cfg_sgl_pp_align_MASK 0x000000ff 3426 #define cfg_sgl_pp_align_WORD word14 3427 uint32_t word15; 3428 uint32_t word16; 3429 uint32_t word17; 3430 uint32_t word18; 3431 uint32_t word19; 3432 #define cfg_ext_embed_cb_SHIFT 0 3433 #define cfg_ext_embed_cb_MASK 0x00000001 3434 #define cfg_ext_embed_cb_WORD word19 3435 #define cfg_mds_diags_SHIFT 1 3436 #define cfg_mds_diags_MASK 0x00000001 3437 #define cfg_mds_diags_WORD word19 3438 #define cfg_nvme_SHIFT 3 3439 #define cfg_nvme_MASK 0x00000001 3440 #define cfg_nvme_WORD word19 3441 #define cfg_xib_SHIFT 4 3442 #define cfg_xib_MASK 0x00000001 3443 #define cfg_xib_WORD word19 3444 #define cfg_xpsgl_SHIFT 6 3445 #define cfg_xpsgl_MASK 0x00000001 3446 #define cfg_xpsgl_WORD word19 3447 #define cfg_eqdr_SHIFT 8 3448 #define cfg_eqdr_MASK 0x00000001 3449 #define cfg_eqdr_WORD word19 3450 #define cfg_nosr_SHIFT 9 3451 #define cfg_nosr_MASK 0x00000001 3452 #define cfg_nosr_WORD word19 3453 #define cfg_bv1s_SHIFT 10 3454 #define cfg_bv1s_MASK 0x00000001 3455 #define cfg_bv1s_WORD word19 3456 3457 #define cfg_nsler_SHIFT 12 3458 #define cfg_nsler_MASK 0x00000001 3459 #define cfg_nsler_WORD word19 3460 #define cfg_pvl_SHIFT 13 3461 #define cfg_pvl_MASK 0x00000001 3462 #define cfg_pvl_WORD word19 3463 3464 #define cfg_pbde_SHIFT 20 3465 #define cfg_pbde_MASK 0x00000001 3466 #define cfg_pbde_WORD word19 3467 3468 uint32_t word20; 3469 #define cfg_max_tow_xri_SHIFT 0 3470 #define cfg_max_tow_xri_MASK 0x0000ffff 3471 #define cfg_max_tow_xri_WORD word20 3472 3473 uint32_t word21; 3474 #define cfg_mi_ver_SHIFT 0 3475 #define cfg_mi_ver_MASK 0x0000ffff 3476 #define cfg_mi_ver_WORD word21 3477 #define cfg_cmf_SHIFT 24 3478 #define cfg_cmf_MASK 0x000000ff 3479 #define cfg_cmf_WORD word21 3480 3481 uint32_t mib_size; 3482 uint32_t word23; /* RESERVED */ 3483 3484 uint32_t word24; 3485 #define cfg_frag_field_offset_SHIFT 0 3486 #define cfg_frag_field_offset_MASK 0x0000ffff 3487 #define cfg_frag_field_offset_WORD word24 3488 3489 #define cfg_frag_field_size_SHIFT 16 3490 #define cfg_frag_field_size_MASK 0x0000ffff 3491 #define cfg_frag_field_size_WORD word24 3492 3493 uint32_t word25; 3494 #define cfg_sgl_field_offset_SHIFT 0 3495 #define cfg_sgl_field_offset_MASK 0x0000ffff 3496 #define cfg_sgl_field_offset_WORD word25 3497 3498 #define cfg_sgl_field_size_SHIFT 16 3499 #define cfg_sgl_field_size_MASK 0x0000ffff 3500 #define cfg_sgl_field_size_WORD word25 3501 3502 uint32_t word26; /* Chain SGE initial value LOW */ 3503 uint32_t word27; /* Chain SGE initial value HIGH */ 3504 #define LPFC_NODELAY_MAX_IO 32 3505 }; 3506 3507 #define LPFC_SET_UE_RECOVERY 0x10 3508 #define LPFC_SET_MDS_DIAGS 0x12 3509 #define LPFC_SET_DUAL_DUMP 0x1e 3510 #define LPFC_SET_CGN_SIGNAL 0x1f 3511 #define LPFC_SET_ENABLE_MI 0x21 3512 #define LPFC_SET_LD_SIGNAL 0x23 3513 #define LPFC_SET_ENABLE_CMF 0x24 3514 struct lpfc_mbx_set_feature { 3515 struct mbox_header header; 3516 uint32_t feature; 3517 uint32_t param_len; 3518 uint32_t word6; 3519 #define lpfc_mbx_set_feature_UER_SHIFT 0 3520 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 3521 #define lpfc_mbx_set_feature_UER_WORD word6 3522 #define lpfc_mbx_set_feature_mds_SHIFT 2 3523 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 3524 #define lpfc_mbx_set_feature_mds_WORD word6 3525 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3526 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3527 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3528 #define lpfc_mbx_set_feature_CGN_warn_freq_SHIFT 0 3529 #define lpfc_mbx_set_feature_CGN_warn_freq_MASK 0x0000ffff 3530 #define lpfc_mbx_set_feature_CGN_warn_freq_WORD word6 3531 #define lpfc_mbx_set_feature_dd_SHIFT 0 3532 #define lpfc_mbx_set_feature_dd_MASK 0x00000001 3533 #define lpfc_mbx_set_feature_dd_WORD word6 3534 #define lpfc_mbx_set_feature_ddquery_SHIFT 1 3535 #define lpfc_mbx_set_feature_ddquery_MASK 0x00000001 3536 #define lpfc_mbx_set_feature_ddquery_WORD word6 3537 #define LPFC_DISABLE_DUAL_DUMP 0 3538 #define LPFC_ENABLE_DUAL_DUMP 1 3539 #define LPFC_QUERY_OP_DUAL_DUMP 2 3540 #define lpfc_mbx_set_feature_cmf_SHIFT 0 3541 #define lpfc_mbx_set_feature_cmf_MASK 0x00000001 3542 #define lpfc_mbx_set_feature_cmf_WORD word6 3543 #define lpfc_mbx_set_feature_lds_qry_SHIFT 0 3544 #define lpfc_mbx_set_feature_lds_qry_MASK 0x00000001 3545 #define lpfc_mbx_set_feature_lds_qry_WORD word6 3546 #define LPFC_QUERY_LDS_OP 1 3547 #define lpfc_mbx_set_feature_mi_SHIFT 0 3548 #define lpfc_mbx_set_feature_mi_MASK 0x0000ffff 3549 #define lpfc_mbx_set_feature_mi_WORD word6 3550 #define lpfc_mbx_set_feature_milunq_SHIFT 16 3551 #define lpfc_mbx_set_feature_milunq_MASK 0x0000ffff 3552 #define lpfc_mbx_set_feature_milunq_WORD word6 3553 u32 word7; 3554 #define lpfc_mbx_set_feature_UERP_SHIFT 0 3555 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3556 #define lpfc_mbx_set_feature_UERP_WORD word7 3557 #define lpfc_mbx_set_feature_UESR_SHIFT 16 3558 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3559 #define lpfc_mbx_set_feature_UESR_WORD word7 3560 #define lpfc_mbx_set_feature_CGN_alarm_freq_SHIFT 0 3561 #define lpfc_mbx_set_feature_CGN_alarm_freq_MASK 0x0000ffff 3562 #define lpfc_mbx_set_feature_CGN_alarm_freq_WORD word7 3563 u32 word8; 3564 #define lpfc_mbx_set_feature_CGN_acqe_freq_SHIFT 0 3565 #define lpfc_mbx_set_feature_CGN_acqe_freq_MASK 0x000000ff 3566 #define lpfc_mbx_set_feature_CGN_acqe_freq_WORD word8 3567 u32 word9; 3568 u32 word10; 3569 }; 3570 3571 3572 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3573 #define LPFC_SET_HOST_DATE_TIME 0x4 3574 3575 struct lpfc_mbx_set_host_date_time { 3576 uint32_t word6; 3577 #define lpfc_mbx_set_host_month_WORD word6 3578 #define lpfc_mbx_set_host_month_SHIFT 16 3579 #define lpfc_mbx_set_host_month_MASK 0xFF 3580 #define lpfc_mbx_set_host_day_WORD word6 3581 #define lpfc_mbx_set_host_day_SHIFT 8 3582 #define lpfc_mbx_set_host_day_MASK 0xFF 3583 #define lpfc_mbx_set_host_year_WORD word6 3584 #define lpfc_mbx_set_host_year_SHIFT 0 3585 #define lpfc_mbx_set_host_year_MASK 0xFF 3586 uint32_t word7; 3587 #define lpfc_mbx_set_host_hour_WORD word7 3588 #define lpfc_mbx_set_host_hour_SHIFT 16 3589 #define lpfc_mbx_set_host_hour_MASK 0xFF 3590 #define lpfc_mbx_set_host_min_WORD word7 3591 #define lpfc_mbx_set_host_min_SHIFT 8 3592 #define lpfc_mbx_set_host_min_MASK 0xFF 3593 #define lpfc_mbx_set_host_sec_WORD word7 3594 #define lpfc_mbx_set_host_sec_SHIFT 0 3595 #define lpfc_mbx_set_host_sec_MASK 0xFF 3596 }; 3597 3598 struct lpfc_mbx_set_host_data { 3599 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3600 struct mbox_header header; 3601 uint32_t param_id; 3602 uint32_t param_len; 3603 union { 3604 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3605 struct lpfc_mbx_set_host_date_time tm; 3606 } un; 3607 }; 3608 3609 struct lpfc_mbx_set_trunk_mode { 3610 struct mbox_header header; 3611 uint32_t word0; 3612 #define lpfc_mbx_set_trunk_mode_WORD word0 3613 #define lpfc_mbx_set_trunk_mode_SHIFT 0 3614 #define lpfc_mbx_set_trunk_mode_MASK 0xFF 3615 uint32_t word1; 3616 uint32_t word2; 3617 }; 3618 3619 struct lpfc_mbx_get_sli4_parameters { 3620 struct mbox_header header; 3621 struct lpfc_sli4_parameters sli4_parameters; 3622 }; 3623 3624 struct lpfc_mbx_reg_congestion_buf { 3625 struct mbox_header header; 3626 uint32_t word0; 3627 #define lpfc_mbx_reg_cgn_buf_type_WORD word0 3628 #define lpfc_mbx_reg_cgn_buf_type_SHIFT 0 3629 #define lpfc_mbx_reg_cgn_buf_type_MASK 0xFF 3630 #define lpfc_mbx_reg_cgn_buf_cnt_WORD word0 3631 #define lpfc_mbx_reg_cgn_buf_cnt_SHIFT 16 3632 #define lpfc_mbx_reg_cgn_buf_cnt_MASK 0xFF 3633 uint32_t word1; 3634 uint32_t length; 3635 uint32_t addr_lo; 3636 uint32_t addr_hi; 3637 }; 3638 3639 struct lpfc_rscr_desc_generic { 3640 #define LPFC_RSRC_DESC_WSIZE 22 3641 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3642 }; 3643 3644 struct lpfc_rsrc_desc_pcie { 3645 uint32_t word0; 3646 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 3647 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3648 #define lpfc_rsrc_desc_pcie_type_WORD word0 3649 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3650 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 3651 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3652 #define lpfc_rsrc_desc_pcie_length_WORD word0 3653 uint32_t word1; 3654 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3655 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3656 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3657 uint32_t reserved; 3658 uint32_t word3; 3659 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3660 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3661 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3662 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3663 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3664 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3665 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3666 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3667 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3668 uint32_t word4; 3669 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3670 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3671 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3672 }; 3673 3674 struct lpfc_rsrc_desc_fcfcoe { 3675 uint32_t word0; 3676 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3677 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3678 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3679 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3680 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3681 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3682 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3683 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3684 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3685 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3686 uint32_t word1; 3687 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3688 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3689 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3690 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3691 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3692 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3693 uint32_t word2; 3694 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3695 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3696 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3697 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3698 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3699 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3700 uint32_t word3; 3701 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3702 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3703 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3704 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3705 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3706 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3707 uint32_t word4; 3708 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3709 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3710 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3711 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3712 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3713 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3714 uint32_t word5; 3715 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3716 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3717 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3718 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3719 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3720 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3721 uint32_t word6; 3722 uint32_t word7; 3723 uint32_t word8; 3724 uint32_t word9; 3725 uint32_t word10; 3726 uint32_t word11; 3727 uint32_t word12; 3728 uint32_t word13; 3729 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3730 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3731 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3732 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3733 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3734 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3735 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3736 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3737 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3738 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3739 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3740 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3741 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3742 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3743 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3744 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3745 uint32_t bw_min; 3746 uint32_t bw_max; 3747 uint32_t iops_min; 3748 uint32_t iops_max; 3749 uint32_t reserved[4]; 3750 }; 3751 3752 struct lpfc_func_cfg { 3753 #define LPFC_RSRC_DESC_MAX_NUM 2 3754 uint32_t rsrc_desc_count; 3755 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3756 }; 3757 3758 struct lpfc_mbx_get_func_cfg { 3759 struct mbox_header header; 3760 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3761 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3762 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3763 struct lpfc_func_cfg func_cfg; 3764 }; 3765 3766 struct lpfc_prof_cfg { 3767 #define LPFC_RSRC_DESC_MAX_NUM 2 3768 uint32_t rsrc_desc_count; 3769 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3770 }; 3771 3772 struct lpfc_mbx_get_prof_cfg { 3773 struct mbox_header header; 3774 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3775 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3776 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3777 union { 3778 struct { 3779 uint32_t word10; 3780 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3781 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3782 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3783 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3784 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3785 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3786 } request; 3787 struct { 3788 struct lpfc_prof_cfg prof_cfg; 3789 } response; 3790 } u; 3791 }; 3792 3793 struct lpfc_controller_attribute { 3794 uint32_t version_string[8]; 3795 uint32_t manufacturer_name[8]; 3796 uint32_t rsvd16; 3797 uint32_t word17; 3798 #define lpfc_cntl_attr_flash_id_SHIFT 16 3799 #define lpfc_cntl_attr_flash_id_MASK 0x000000ff 3800 #define lpfc_cntl_attr_flash_id_WORD word17 3801 #define lpfc_cntl_attr_boot_enable_SHIFT 24 3802 #define lpfc_cntl_attr_boot_enable_MASK 0x00000001 3803 #define lpfc_cntl_attr_boot_enable_WORD word17 3804 uint32_t rsvd18[2]; 3805 uint32_t ncsi_ver_str[3]; 3806 uint32_t rsvd23; 3807 uint32_t model_number[8]; 3808 uint32_t description[16]; 3809 uint32_t serial_number[8]; 3810 uint32_t ipl_name[5]; 3811 uint32_t rsvd61[3]; 3812 uint32_t fw_ver_str[8]; 3813 uint32_t bios_ver_str[8]; 3814 uint32_t redboot_ver_str[8]; 3815 uint32_t driver_ver_str[8]; 3816 uint32_t flash_fw_ver_str[8]; 3817 uint32_t functionality; 3818 uint32_t word105; 3819 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3820 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3821 #define lpfc_cntl_attr_asic_rev_WORD word105 3822 uint32_t rsvd106[3]; 3823 uint32_t word109; 3824 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3825 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3826 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3827 uint32_t rsvd110; 3828 uint32_t word111; 3829 #define lpfc_cntl_attr_hba_status_SHIFT 8 3830 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3831 #define lpfc_cntl_attr_hba_status_WORD word111 3832 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3833 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3834 #define lpfc_cntl_attr_lnk_numb_WORD word111 3835 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3836 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3837 #define lpfc_cntl_attr_lnk_type_WORD word111 3838 uint32_t rsvd112[9]; 3839 uint32_t word121; 3840 #define lpfc_cntl_attr_asic_gen_SHIFT 8 3841 #define lpfc_cntl_attr_asic_gen_MASK 0x000000ff 3842 #define lpfc_cntl_attr_asic_gen_WORD word121 3843 uint32_t rsvd122[3]; 3844 uint32_t word125; 3845 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3846 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3847 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3848 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3849 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3850 #define lpfc_cntl_attr_pci_device_id_WORD word125 3851 uint32_t word126; 3852 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3853 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3854 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3855 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3856 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3857 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3858 uint32_t word127; 3859 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3860 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3861 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3862 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3863 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3864 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3865 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3866 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3867 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3868 uint32_t rsvd128[7]; 3869 }; 3870 3871 struct lpfc_mbx_get_cntl_attributes { 3872 union lpfc_sli4_cfg_shdr cfg_shdr; 3873 struct lpfc_controller_attribute cntl_attr; 3874 }; 3875 3876 struct lpfc_mbx_get_port_name { 3877 struct mbox_header header; 3878 union { 3879 struct { 3880 uint32_t word4; 3881 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3882 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3883 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3884 } request; 3885 struct { 3886 uint32_t word4; 3887 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3888 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3889 #define lpfc_mbx_get_port_name_name0_WORD word4 3890 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3891 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3892 #define lpfc_mbx_get_port_name_name1_WORD word4 3893 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3894 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3895 #define lpfc_mbx_get_port_name_name2_WORD word4 3896 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3897 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3898 #define lpfc_mbx_get_port_name_name3_WORD word4 3899 #define LPFC_LINK_NUMBER_0 0 3900 #define LPFC_LINK_NUMBER_1 1 3901 #define LPFC_LINK_NUMBER_2 2 3902 #define LPFC_LINK_NUMBER_3 3 3903 } response; 3904 } u; 3905 }; 3906 3907 /* Mailbox Completion Queue Error Messages */ 3908 #define MB_CQE_STATUS_SUCCESS 0x0 3909 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3910 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3911 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3912 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3913 #define MB_CQE_STATUS_DMA_FAILED 0x5 3914 3915 3916 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3917 struct lpfc_mbx_wr_object { 3918 struct mbox_header header; 3919 union { 3920 struct { 3921 uint32_t word4; 3922 #define lpfc_wr_object_eof_SHIFT 31 3923 #define lpfc_wr_object_eof_MASK 0x00000001 3924 #define lpfc_wr_object_eof_WORD word4 3925 #define lpfc_wr_object_eas_SHIFT 29 3926 #define lpfc_wr_object_eas_MASK 0x00000001 3927 #define lpfc_wr_object_eas_WORD word4 3928 #define lpfc_wr_object_write_length_SHIFT 0 3929 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3930 #define lpfc_wr_object_write_length_WORD word4 3931 uint32_t write_offset; 3932 uint32_t object_name[LPFC_MBX_OBJECT_NAME_LEN_DW]; 3933 uint32_t bde_count; 3934 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3935 } request; 3936 struct { 3937 uint32_t actual_write_length; 3938 uint32_t word5; 3939 #define lpfc_wr_object_change_status_SHIFT 0 3940 #define lpfc_wr_object_change_status_MASK 0x000000FF 3941 #define lpfc_wr_object_change_status_WORD word5 3942 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00 3943 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01 3944 #define LPFC_CHANGE_STATUS_FW_RESET 0x02 3945 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04 3946 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05 3947 #define lpfc_wr_object_csf_SHIFT 8 3948 #define lpfc_wr_object_csf_MASK 0x00000001 3949 #define lpfc_wr_object_csf_WORD word5 3950 } response; 3951 } u; 3952 }; 3953 3954 /* mailbox queue entry structure */ 3955 struct lpfc_mqe { 3956 uint32_t word0; 3957 #define lpfc_mqe_status_SHIFT 16 3958 #define lpfc_mqe_status_MASK 0x0000FFFF 3959 #define lpfc_mqe_status_WORD word0 3960 #define lpfc_mqe_command_SHIFT 8 3961 #define lpfc_mqe_command_MASK 0x000000FF 3962 #define lpfc_mqe_command_WORD word0 3963 union { 3964 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3965 /* sli4 mailbox commands */ 3966 struct lpfc_mbx_sli4_config sli4_config; 3967 struct lpfc_mbx_init_vfi init_vfi; 3968 struct lpfc_mbx_reg_vfi reg_vfi; 3969 struct lpfc_mbx_reg_vfi unreg_vfi; 3970 struct lpfc_mbx_init_vpi init_vpi; 3971 struct lpfc_mbx_resume_rpi resume_rpi; 3972 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3973 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3974 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3975 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3976 struct lpfc_mbx_reg_fcfi reg_fcfi; 3977 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3978 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3979 struct lpfc_mbx_mq_create mq_create; 3980 struct lpfc_mbx_mq_create_ext mq_create_ext; 3981 struct lpfc_mbx_read_object read_object; 3982 struct lpfc_mbx_eq_create eq_create; 3983 struct lpfc_mbx_modify_eq_delay eq_delay; 3984 struct lpfc_mbx_cq_create cq_create; 3985 struct lpfc_mbx_cq_create_set cq_create_set; 3986 struct lpfc_mbx_wq_create wq_create; 3987 struct lpfc_mbx_rq_create rq_create; 3988 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3989 struct lpfc_mbx_mq_destroy mq_destroy; 3990 struct lpfc_mbx_eq_destroy eq_destroy; 3991 struct lpfc_mbx_cq_destroy cq_destroy; 3992 struct lpfc_mbx_wq_destroy wq_destroy; 3993 struct lpfc_mbx_rq_destroy rq_destroy; 3994 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3995 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3996 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3997 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3998 struct lpfc_mbx_nembed_cmd nembed_cmd; 3999 struct lpfc_mbx_read_rev read_rev; 4000 struct lpfc_mbx_read_vpi read_vpi; 4001 struct lpfc_mbx_read_config rd_config; 4002 struct lpfc_mbx_request_features req_ftrs; 4003 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 4004 struct lpfc_mbx_query_fw_config query_fw_cfg; 4005 struct lpfc_mbx_set_beacon_config beacon_config; 4006 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 4007 struct lpfc_mbx_reg_congestion_buf reg_congestion_buf; 4008 struct lpfc_mbx_set_link_diag_state link_diag_state; 4009 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 4010 struct lpfc_mbx_run_link_diag_test link_diag_test; 4011 struct lpfc_mbx_get_func_cfg get_func_cfg; 4012 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 4013 struct lpfc_mbx_wr_object wr_object; 4014 struct lpfc_mbx_get_port_name get_port_name; 4015 struct lpfc_mbx_set_feature set_feature; 4016 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 4017 struct lpfc_mbx_set_host_data set_host_data; 4018 struct lpfc_mbx_set_trunk_mode set_trunk_mode; 4019 struct lpfc_mbx_nop nop; 4020 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 4021 } un; 4022 }; 4023 4024 struct lpfc_mcqe { 4025 uint32_t word0; 4026 #define lpfc_mcqe_status_SHIFT 0 4027 #define lpfc_mcqe_status_MASK 0x0000FFFF 4028 #define lpfc_mcqe_status_WORD word0 4029 #define lpfc_mcqe_ext_status_SHIFT 16 4030 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 4031 #define lpfc_mcqe_ext_status_WORD word0 4032 uint32_t mcqe_tag0; 4033 uint32_t mcqe_tag1; 4034 uint32_t trailer; 4035 #define lpfc_trailer_valid_SHIFT 31 4036 #define lpfc_trailer_valid_MASK 0x00000001 4037 #define lpfc_trailer_valid_WORD trailer 4038 #define lpfc_trailer_async_SHIFT 30 4039 #define lpfc_trailer_async_MASK 0x00000001 4040 #define lpfc_trailer_async_WORD trailer 4041 #define lpfc_trailer_hpi_SHIFT 29 4042 #define lpfc_trailer_hpi_MASK 0x00000001 4043 #define lpfc_trailer_hpi_WORD trailer 4044 #define lpfc_trailer_completed_SHIFT 28 4045 #define lpfc_trailer_completed_MASK 0x00000001 4046 #define lpfc_trailer_completed_WORD trailer 4047 #define lpfc_trailer_consumed_SHIFT 27 4048 #define lpfc_trailer_consumed_MASK 0x00000001 4049 #define lpfc_trailer_consumed_WORD trailer 4050 #define lpfc_trailer_type_SHIFT 16 4051 #define lpfc_trailer_type_MASK 0x000000FF 4052 #define lpfc_trailer_type_WORD trailer 4053 #define lpfc_trailer_code_SHIFT 8 4054 #define lpfc_trailer_code_MASK 0x000000FF 4055 #define lpfc_trailer_code_WORD trailer 4056 #define LPFC_TRAILER_CODE_LINK 0x1 4057 #define LPFC_TRAILER_CODE_FCOE 0x2 4058 #define LPFC_TRAILER_CODE_DCBX 0x3 4059 #define LPFC_TRAILER_CODE_GRP5 0x5 4060 #define LPFC_TRAILER_CODE_FC 0x10 4061 #define LPFC_TRAILER_CODE_SLI 0x11 4062 }; 4063 4064 struct lpfc_acqe_link { 4065 uint32_t word0; 4066 #define lpfc_acqe_link_speed_SHIFT 24 4067 #define lpfc_acqe_link_speed_MASK 0x000000FF 4068 #define lpfc_acqe_link_speed_WORD word0 4069 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 4070 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 4071 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 4072 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 4073 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 4074 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 4075 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 4076 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 4077 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 4078 #define lpfc_acqe_link_duplex_SHIFT 16 4079 #define lpfc_acqe_link_duplex_MASK 0x000000FF 4080 #define lpfc_acqe_link_duplex_WORD word0 4081 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 4082 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 4083 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 4084 #define lpfc_acqe_link_status_SHIFT 8 4085 #define lpfc_acqe_link_status_MASK 0x000000FF 4086 #define lpfc_acqe_link_status_WORD word0 4087 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 4088 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 4089 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 4090 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 4091 #define lpfc_acqe_link_type_SHIFT 6 4092 #define lpfc_acqe_link_type_MASK 0x00000003 4093 #define lpfc_acqe_link_type_WORD word0 4094 #define lpfc_acqe_link_number_SHIFT 0 4095 #define lpfc_acqe_link_number_MASK 0x0000003F 4096 #define lpfc_acqe_link_number_WORD word0 4097 uint32_t word1; 4098 #define lpfc_acqe_link_fault_SHIFT 0 4099 #define lpfc_acqe_link_fault_MASK 0x000000FF 4100 #define lpfc_acqe_link_fault_WORD word1 4101 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 4102 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 4103 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 4104 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 4105 #define lpfc_acqe_logical_link_speed_SHIFT 16 4106 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 4107 #define lpfc_acqe_logical_link_speed_WORD word1 4108 uint32_t event_tag; 4109 uint32_t trailer; 4110 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 4111 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 4112 }; 4113 4114 struct lpfc_acqe_fip { 4115 uint32_t index; 4116 uint32_t word1; 4117 #define lpfc_acqe_fip_fcf_count_SHIFT 0 4118 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 4119 #define lpfc_acqe_fip_fcf_count_WORD word1 4120 #define lpfc_acqe_fip_event_type_SHIFT 16 4121 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 4122 #define lpfc_acqe_fip_event_type_WORD word1 4123 uint32_t event_tag; 4124 uint32_t trailer; 4125 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 4126 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 4127 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 4128 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 4129 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 4130 }; 4131 4132 struct lpfc_acqe_dcbx { 4133 uint32_t tlv_ttl; 4134 uint32_t reserved; 4135 uint32_t event_tag; 4136 uint32_t trailer; 4137 }; 4138 4139 struct lpfc_acqe_grp5 { 4140 uint32_t word0; 4141 #define lpfc_acqe_grp5_type_SHIFT 6 4142 #define lpfc_acqe_grp5_type_MASK 0x00000003 4143 #define lpfc_acqe_grp5_type_WORD word0 4144 #define lpfc_acqe_grp5_number_SHIFT 0 4145 #define lpfc_acqe_grp5_number_MASK 0x0000003F 4146 #define lpfc_acqe_grp5_number_WORD word0 4147 uint32_t word1; 4148 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 4149 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 4150 #define lpfc_acqe_grp5_llink_spd_WORD word1 4151 uint32_t event_tag; 4152 uint32_t trailer; 4153 }; 4154 4155 extern const char *const trunk_errmsg[]; 4156 4157 struct lpfc_acqe_fc_la { 4158 uint32_t word0; 4159 #define lpfc_acqe_fc_la_speed_SHIFT 24 4160 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4161 #define lpfc_acqe_fc_la_speed_WORD word0 4162 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4163 #define LPFC_FC_LA_SPEED_1G 0x1 4164 #define LPFC_FC_LA_SPEED_2G 0x2 4165 #define LPFC_FC_LA_SPEED_4G 0x4 4166 #define LPFC_FC_LA_SPEED_8G 0x8 4167 #define LPFC_FC_LA_SPEED_10G 0xA 4168 #define LPFC_FC_LA_SPEED_16G 0x10 4169 #define LPFC_FC_LA_SPEED_32G 0x20 4170 #define LPFC_FC_LA_SPEED_64G 0x21 4171 #define LPFC_FC_LA_SPEED_128G 0x22 4172 #define LPFC_FC_LA_SPEED_256G 0x23 4173 #define lpfc_acqe_fc_la_topology_SHIFT 16 4174 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4175 #define lpfc_acqe_fc_la_topology_WORD word0 4176 #define LPFC_FC_LA_TOP_UNKOWN 0x0 4177 #define LPFC_FC_LA_TOP_P2P 0x1 4178 #define LPFC_FC_LA_TOP_FCAL 0x2 4179 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4180 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4181 #define lpfc_acqe_fc_la_att_type_SHIFT 8 4182 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4183 #define lpfc_acqe_fc_la_att_type_WORD word0 4184 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 4185 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4186 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4187 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4188 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4189 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4190 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7 4191 #define LPFC_FC_LA_TYPE_ACTIVATE_FAIL 0x8 4192 #define LPFC_FC_LA_TYPE_LINK_RESET_PRTCL_EVT 0x9 4193 #define lpfc_acqe_fc_la_port_type_SHIFT 6 4194 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4195 #define lpfc_acqe_fc_la_port_type_WORD word0 4196 #define LPFC_LINK_TYPE_ETHERNET 0x0 4197 #define LPFC_LINK_TYPE_FC 0x1 4198 #define lpfc_acqe_fc_la_port_number_SHIFT 0 4199 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4200 #define lpfc_acqe_fc_la_port_number_WORD word0 4201 4202 /* Attention Type is 0x07 (Trunking Event) word0 */ 4203 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16 4204 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001 4205 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0 4206 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17 4207 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001 4208 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0 4209 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18 4210 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001 4211 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0 4212 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19 4213 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001 4214 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0 4215 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20 4216 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001 4217 #define lpfc_acqe_fc_la_trunk_config_port0_WORD word0 4218 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21 4219 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001 4220 #define lpfc_acqe_fc_la_trunk_config_port1_WORD word0 4221 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22 4222 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001 4223 #define lpfc_acqe_fc_la_trunk_config_port2_WORD word0 4224 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23 4225 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001 4226 #define lpfc_acqe_fc_la_trunk_config_port3_WORD word0 4227 uint32_t word1; 4228 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4229 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4230 #define lpfc_acqe_fc_la_llink_spd_WORD word1 4231 #define lpfc_acqe_fc_la_fault_SHIFT 0 4232 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4233 #define lpfc_acqe_fc_la_fault_WORD word1 4234 #define lpfc_acqe_fc_la_link_status_SHIFT 8 4235 #define lpfc_acqe_fc_la_link_status_MASK 0x0000007F 4236 #define lpfc_acqe_fc_la_link_status_WORD word1 4237 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0 4238 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F 4239 #define lpfc_acqe_fc_la_trunk_fault_WORD word1 4240 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4 4241 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F 4242 #define lpfc_acqe_fc_la_trunk_linkmask_WORD word1 4243 #define LPFC_FC_LA_FAULT_NONE 0x0 4244 #define LPFC_FC_LA_FAULT_LOCAL 0x1 4245 #define LPFC_FC_LA_FAULT_REMOTE 0x2 4246 uint32_t event_tag; 4247 uint32_t trailer; 4248 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4249 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4250 }; 4251 4252 struct lpfc_acqe_misconfigured_event { 4253 struct { 4254 uint32_t word0; 4255 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 4256 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4257 #define lpfc_sli_misconfigured_port0_state_WORD word0 4258 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 4259 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4260 #define lpfc_sli_misconfigured_port1_state_WORD word0 4261 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 4262 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4263 #define lpfc_sli_misconfigured_port2_state_WORD word0 4264 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 4265 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4266 #define lpfc_sli_misconfigured_port3_state_WORD word0 4267 uint32_t word1; 4268 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 4269 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4270 #define lpfc_sli_misconfigured_port0_op_WORD word1 4271 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4272 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4273 #define lpfc_sli_misconfigured_port0_severity_WORD word1 4274 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 4275 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4276 #define lpfc_sli_misconfigured_port1_op_WORD word1 4277 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4278 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4279 #define lpfc_sli_misconfigured_port1_severity_WORD word1 4280 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 4281 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4282 #define lpfc_sli_misconfigured_port2_op_WORD word1 4283 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4284 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4285 #define lpfc_sli_misconfigured_port2_severity_WORD word1 4286 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 4287 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4288 #define lpfc_sli_misconfigured_port3_op_WORD word1 4289 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4290 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4291 #define lpfc_sli_misconfigured_port3_severity_WORD word1 4292 } theEvent; 4293 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 4294 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4295 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4296 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4297 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4298 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4299 }; 4300 4301 struct lpfc_acqe_cgn_signal { 4302 u32 word0; 4303 #define lpfc_warn_acqe_SHIFT 0 4304 #define lpfc_warn_acqe_MASK 0x7FFFFFFF 4305 #define lpfc_warn_acqe_WORD word0 4306 #define lpfc_imm_acqe_SHIFT 31 4307 #define lpfc_imm_acqe_MASK 0x1 4308 #define lpfc_imm_acqe_WORD word0 4309 u32 alarm_cnt; 4310 u32 word2; 4311 u32 trailer; 4312 }; 4313 4314 struct lpfc_acqe_sli { 4315 uint32_t event_data1; 4316 uint32_t event_data2; 4317 uint32_t event_data3; 4318 uint32_t trailer; 4319 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4320 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4321 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4322 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4323 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4324 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4325 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4326 #define LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG 0xE 4327 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF 4328 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10 4329 #define LPFC_SLI_EVENT_TYPE_CGN_SIGNAL 0x11 4330 #define LPFC_SLI_EVENT_TYPE_RD_SIGNAL 0x12 4331 #define LPFC_SLI_EVENT_TYPE_RESET_CM_STATS 0x13 4332 }; 4333 4334 /* 4335 * Define the bootstrap mailbox (bmbx) region used to communicate 4336 * mailbox command between the host and port. The mailbox consists 4337 * of a payload area of 256 bytes and a completion queue of length 4338 * 16 bytes. 4339 */ 4340 struct lpfc_bmbx_create { 4341 struct lpfc_mqe mqe; 4342 struct lpfc_mcqe mcqe; 4343 }; 4344 4345 #define SGL_ALIGN_SZ 64 4346 #define SGL_PAGE_SIZE 4096 4347 /* align SGL addr on a size boundary - adjust address up */ 4348 #define NO_XRI 0xffff 4349 4350 struct wqe_common { 4351 uint32_t word6; 4352 #define wqe_xri_tag_SHIFT 0 4353 #define wqe_xri_tag_MASK 0x0000FFFF 4354 #define wqe_xri_tag_WORD word6 4355 #define wqe_ctxt_tag_SHIFT 16 4356 #define wqe_ctxt_tag_MASK 0x0000FFFF 4357 #define wqe_ctxt_tag_WORD word6 4358 uint32_t word7; 4359 #define wqe_dif_SHIFT 0 4360 #define wqe_dif_MASK 0x00000003 4361 #define wqe_dif_WORD word7 4362 #define LPFC_WQE_DIF_PASSTHRU 1 4363 #define LPFC_WQE_DIF_STRIP 2 4364 #define LPFC_WQE_DIF_INSERT 3 4365 #define wqe_ct_SHIFT 2 4366 #define wqe_ct_MASK 0x00000003 4367 #define wqe_ct_WORD word7 4368 #define wqe_status_SHIFT 4 4369 #define wqe_status_MASK 0x0000000f 4370 #define wqe_status_WORD word7 4371 #define wqe_cmnd_SHIFT 8 4372 #define wqe_cmnd_MASK 0x000000ff 4373 #define wqe_cmnd_WORD word7 4374 #define wqe_class_SHIFT 16 4375 #define wqe_class_MASK 0x00000007 4376 #define wqe_class_WORD word7 4377 #define wqe_ar_SHIFT 19 4378 #define wqe_ar_MASK 0x00000001 4379 #define wqe_ar_WORD word7 4380 #define wqe_ag_SHIFT wqe_ar_SHIFT 4381 #define wqe_ag_MASK wqe_ar_MASK 4382 #define wqe_ag_WORD wqe_ar_WORD 4383 #define wqe_pu_SHIFT 20 4384 #define wqe_pu_MASK 0x00000003 4385 #define wqe_pu_WORD word7 4386 #define wqe_erp_SHIFT 22 4387 #define wqe_erp_MASK 0x00000001 4388 #define wqe_erp_WORD word7 4389 #define wqe_conf_SHIFT wqe_erp_SHIFT 4390 #define wqe_conf_MASK wqe_erp_MASK 4391 #define wqe_conf_WORD wqe_erp_WORD 4392 #define wqe_lnk_SHIFT 23 4393 #define wqe_lnk_MASK 0x00000001 4394 #define wqe_lnk_WORD word7 4395 #define wqe_tmo_SHIFT 24 4396 #define wqe_tmo_MASK 0x000000ff 4397 #define wqe_tmo_WORD word7 4398 uint32_t abort_tag; /* word 8 in WQE */ 4399 uint32_t word9; 4400 #define wqe_reqtag_SHIFT 0 4401 #define wqe_reqtag_MASK 0x0000FFFF 4402 #define wqe_reqtag_WORD word9 4403 #define wqe_temp_rpi_SHIFT 16 4404 #define wqe_temp_rpi_MASK 0x0000FFFF 4405 #define wqe_temp_rpi_WORD word9 4406 #define wqe_rcvoxid_SHIFT 16 4407 #define wqe_rcvoxid_MASK 0x0000FFFF 4408 #define wqe_rcvoxid_WORD word9 4409 #define wqe_sof_SHIFT 24 4410 #define wqe_sof_MASK 0x000000FF 4411 #define wqe_sof_WORD word9 4412 #define wqe_eof_SHIFT 16 4413 #define wqe_eof_MASK 0x000000FF 4414 #define wqe_eof_WORD word9 4415 uint32_t word10; 4416 #define wqe_ebde_cnt_SHIFT 0 4417 #define wqe_ebde_cnt_MASK 0x0000000f 4418 #define wqe_ebde_cnt_WORD word10 4419 #define wqe_xchg_SHIFT 4 4420 #define wqe_xchg_MASK 0x00000001 4421 #define wqe_xchg_WORD word10 4422 #define LPFC_SCSI_XCHG 0x0 4423 #define LPFC_NVME_XCHG 0x1 4424 #define wqe_appid_SHIFT 5 4425 #define wqe_appid_MASK 0x00000001 4426 #define wqe_appid_WORD word10 4427 #define wqe_oas_SHIFT 6 4428 #define wqe_oas_MASK 0x00000001 4429 #define wqe_oas_WORD word10 4430 #define wqe_lenloc_SHIFT 7 4431 #define wqe_lenloc_MASK 0x00000003 4432 #define wqe_lenloc_WORD word10 4433 #define LPFC_WQE_LENLOC_NONE 0 4434 #define LPFC_WQE_LENLOC_WORD3 1 4435 #define LPFC_WQE_LENLOC_WORD12 2 4436 #define LPFC_WQE_LENLOC_WORD4 3 4437 #define wqe_qosd_SHIFT 9 4438 #define wqe_qosd_MASK 0x00000001 4439 #define wqe_qosd_WORD word10 4440 #define wqe_xbl_SHIFT 11 4441 #define wqe_xbl_MASK 0x00000001 4442 #define wqe_xbl_WORD word10 4443 #define wqe_iod_SHIFT 13 4444 #define wqe_iod_MASK 0x00000001 4445 #define wqe_iod_WORD word10 4446 #define LPFC_WQE_IOD_NONE 0 4447 #define LPFC_WQE_IOD_WRITE 0 4448 #define LPFC_WQE_IOD_READ 1 4449 #define wqe_dbde_SHIFT 14 4450 #define wqe_dbde_MASK 0x00000001 4451 #define wqe_dbde_WORD word10 4452 #define wqe_wqes_SHIFT 15 4453 #define wqe_wqes_MASK 0x00000001 4454 #define wqe_wqes_WORD word10 4455 /* Note that this field overlaps above fields */ 4456 #define wqe_wqid_SHIFT 1 4457 #define wqe_wqid_MASK 0x00007fff 4458 #define wqe_wqid_WORD word10 4459 #define wqe_pri_SHIFT 16 4460 #define wqe_pri_MASK 0x00000007 4461 #define wqe_pri_WORD word10 4462 #define wqe_pv_SHIFT 19 4463 #define wqe_pv_MASK 0x00000001 4464 #define wqe_pv_WORD word10 4465 #define wqe_xc_SHIFT 21 4466 #define wqe_xc_MASK 0x00000001 4467 #define wqe_xc_WORD word10 4468 #define wqe_sr_SHIFT 22 4469 #define wqe_sr_MASK 0x00000001 4470 #define wqe_sr_WORD word10 4471 #define wqe_ccpe_SHIFT 23 4472 #define wqe_ccpe_MASK 0x00000001 4473 #define wqe_ccpe_WORD word10 4474 #define wqe_ccp_SHIFT 24 4475 #define wqe_ccp_MASK 0x000000ff 4476 #define wqe_ccp_WORD word10 4477 uint32_t word11; 4478 #define wqe_cmd_type_SHIFT 0 4479 #define wqe_cmd_type_MASK 0x0000000f 4480 #define wqe_cmd_type_WORD word11 4481 #define wqe_els_id_SHIFT 4 4482 #define wqe_els_id_MASK 0x00000007 4483 #define wqe_els_id_WORD word11 4484 #define wqe_irsp_SHIFT 4 4485 #define wqe_irsp_MASK 0x00000001 4486 #define wqe_irsp_WORD word11 4487 #define wqe_pbde_SHIFT 5 4488 #define wqe_pbde_MASK 0x00000001 4489 #define wqe_pbde_WORD word11 4490 #define wqe_sup_SHIFT 6 4491 #define wqe_sup_MASK 0x00000001 4492 #define wqe_sup_WORD word11 4493 #define wqe_ffrq_SHIFT 6 4494 #define wqe_ffrq_MASK 0x00000001 4495 #define wqe_ffrq_WORD word11 4496 #define wqe_wqec_SHIFT 7 4497 #define wqe_wqec_MASK 0x00000001 4498 #define wqe_wqec_WORD word11 4499 #define wqe_irsplen_SHIFT 8 4500 #define wqe_irsplen_MASK 0x0000000f 4501 #define wqe_irsplen_WORD word11 4502 #define wqe_cqid_SHIFT 16 4503 #define wqe_cqid_MASK 0x0000ffff 4504 #define wqe_cqid_WORD word11 4505 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4506 }; 4507 4508 struct wqe_did { 4509 uint32_t word5; 4510 #define wqe_els_did_SHIFT 0 4511 #define wqe_els_did_MASK 0x00FFFFFF 4512 #define wqe_els_did_WORD word5 4513 #define wqe_xmit_bls_pt_SHIFT 28 4514 #define wqe_xmit_bls_pt_MASK 0x00000003 4515 #define wqe_xmit_bls_pt_WORD word5 4516 #define wqe_xmit_bls_ar_SHIFT 30 4517 #define wqe_xmit_bls_ar_MASK 0x00000001 4518 #define wqe_xmit_bls_ar_WORD word5 4519 #define wqe_xmit_bls_xo_SHIFT 31 4520 #define wqe_xmit_bls_xo_MASK 0x00000001 4521 #define wqe_xmit_bls_xo_WORD word5 4522 }; 4523 4524 struct lpfc_wqe_generic{ 4525 struct ulp_bde64 bde; 4526 uint32_t word3; 4527 uint32_t word4; 4528 uint32_t word5; 4529 struct wqe_common wqe_com; 4530 uint32_t payload[4]; 4531 }; 4532 4533 enum els_request64_wqe_word11 { 4534 LPFC_ELS_ID_DEFAULT, 4535 LPFC_ELS_ID_LOGO, 4536 LPFC_ELS_ID_FDISC, 4537 LPFC_ELS_ID_FLOGI, 4538 LPFC_ELS_ID_PLOGI, 4539 }; 4540 4541 struct els_request64_wqe { 4542 struct ulp_bde64 bde; 4543 uint32_t payload_len; 4544 uint32_t word4; 4545 #define els_req64_sid_SHIFT 0 4546 #define els_req64_sid_MASK 0x00FFFFFF 4547 #define els_req64_sid_WORD word4 4548 #define els_req64_sp_SHIFT 24 4549 #define els_req64_sp_MASK 0x00000001 4550 #define els_req64_sp_WORD word4 4551 #define els_req64_vf_SHIFT 25 4552 #define els_req64_vf_MASK 0x00000001 4553 #define els_req64_vf_WORD word4 4554 struct wqe_did wqe_dest; 4555 struct wqe_common wqe_com; /* words 6-11 */ 4556 uint32_t word12; 4557 #define els_req64_vfid_SHIFT 1 4558 #define els_req64_vfid_MASK 0x00000FFF 4559 #define els_req64_vfid_WORD word12 4560 #define els_req64_pri_SHIFT 13 4561 #define els_req64_pri_MASK 0x00000007 4562 #define els_req64_pri_WORD word12 4563 uint32_t word13; 4564 #define els_req64_hopcnt_SHIFT 24 4565 #define els_req64_hopcnt_MASK 0x000000ff 4566 #define els_req64_hopcnt_WORD word13 4567 uint32_t word14; 4568 uint32_t max_response_payload_len; 4569 }; 4570 4571 struct xmit_els_rsp64_wqe { 4572 struct ulp_bde64 bde; 4573 uint32_t response_payload_len; 4574 uint32_t word4; 4575 #define els_rsp64_sid_SHIFT 0 4576 #define els_rsp64_sid_MASK 0x00FFFFFF 4577 #define els_rsp64_sid_WORD word4 4578 #define els_rsp64_sp_SHIFT 24 4579 #define els_rsp64_sp_MASK 0x00000001 4580 #define els_rsp64_sp_WORD word4 4581 struct wqe_did wqe_dest; 4582 struct wqe_common wqe_com; /* words 6-11 */ 4583 uint32_t word12; 4584 #define wqe_rsp_temp_rpi_SHIFT 0 4585 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4586 #define wqe_rsp_temp_rpi_WORD word12 4587 uint32_t rsvd_13_15[3]; 4588 }; 4589 4590 struct xmit_bls_rsp64_wqe { 4591 uint32_t payload0; 4592 /* Payload0 for BA_ACC */ 4593 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4594 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4595 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 4596 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4597 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4598 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4599 /* Payload0 for BA_RJT */ 4600 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4601 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4602 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 4603 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 4604 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4605 #define xmit_bls_rsp64_rjt_expc_WORD payload0 4606 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4607 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4608 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4609 uint32_t word1; 4610 #define xmit_bls_rsp64_rxid_SHIFT 0 4611 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4612 #define xmit_bls_rsp64_rxid_WORD word1 4613 #define xmit_bls_rsp64_oxid_SHIFT 16 4614 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4615 #define xmit_bls_rsp64_oxid_WORD word1 4616 uint32_t word2; 4617 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 4618 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4619 #define xmit_bls_rsp64_seqcnthi_WORD word2 4620 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 4621 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4622 #define xmit_bls_rsp64_seqcntlo_WORD word2 4623 uint32_t rsrvd3; 4624 uint32_t rsrvd4; 4625 struct wqe_did wqe_dest; 4626 struct wqe_common wqe_com; /* words 6-11 */ 4627 uint32_t word12; 4628 #define xmit_bls_rsp64_temprpi_SHIFT 0 4629 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4630 #define xmit_bls_rsp64_temprpi_WORD word12 4631 uint32_t rsvd_13_15[3]; 4632 }; 4633 4634 struct wqe_rctl_dfctl { 4635 uint32_t word5; 4636 #define wqe_si_SHIFT 2 4637 #define wqe_si_MASK 0x000000001 4638 #define wqe_si_WORD word5 4639 #define wqe_la_SHIFT 3 4640 #define wqe_la_MASK 0x000000001 4641 #define wqe_la_WORD word5 4642 #define wqe_xo_SHIFT 6 4643 #define wqe_xo_MASK 0x000000001 4644 #define wqe_xo_WORD word5 4645 #define wqe_ls_SHIFT 7 4646 #define wqe_ls_MASK 0x000000001 4647 #define wqe_ls_WORD word5 4648 #define wqe_dfctl_SHIFT 8 4649 #define wqe_dfctl_MASK 0x0000000ff 4650 #define wqe_dfctl_WORD word5 4651 #define wqe_type_SHIFT 16 4652 #define wqe_type_MASK 0x0000000ff 4653 #define wqe_type_WORD word5 4654 #define wqe_rctl_SHIFT 24 4655 #define wqe_rctl_MASK 0x0000000ff 4656 #define wqe_rctl_WORD word5 4657 }; 4658 4659 struct xmit_seq64_wqe { 4660 struct ulp_bde64 bde; 4661 uint32_t rsvd3; 4662 uint32_t relative_offset; 4663 struct wqe_rctl_dfctl wge_ctl; 4664 struct wqe_common wqe_com; /* words 6-11 */ 4665 uint32_t xmit_len; 4666 uint32_t rsvd_12_15[3]; 4667 }; 4668 struct xmit_bcast64_wqe { 4669 struct ulp_bde64 bde; 4670 uint32_t seq_payload_len; 4671 uint32_t rsvd4; 4672 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4673 struct wqe_common wqe_com; /* words 6-11 */ 4674 uint32_t rsvd_12_15[4]; 4675 }; 4676 4677 struct gen_req64_wqe { 4678 struct ulp_bde64 bde; 4679 uint32_t request_payload_len; 4680 uint32_t relative_offset; 4681 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4682 struct wqe_common wqe_com; /* words 6-11 */ 4683 uint32_t rsvd_12_14[3]; 4684 uint32_t max_response_payload_len; 4685 }; 4686 4687 /* Define NVME PRLI request to fabric. NVME is a 4688 * fabric-only protocol. 4689 * Updated to red-lined v1.08 on Sept 16, 2016 4690 */ 4691 struct lpfc_nvme_prli { 4692 uint32_t word1; 4693 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4694 #define prli_acc_rsp_code_SHIFT 8 4695 #define prli_acc_rsp_code_MASK 0x0000000f 4696 #define prli_acc_rsp_code_WORD word1 4697 #define prli_estabImagePair_SHIFT 13 4698 #define prli_estabImagePair_MASK 0x00000001 4699 #define prli_estabImagePair_WORD word1 4700 #define prli_type_code_ext_SHIFT 16 4701 #define prli_type_code_ext_MASK 0x000000ff 4702 #define prli_type_code_ext_WORD word1 4703 #define prli_type_code_SHIFT 24 4704 #define prli_type_code_MASK 0x000000ff 4705 #define prli_type_code_WORD word1 4706 uint32_t word_rsvd2; 4707 uint32_t word_rsvd3; 4708 4709 uint32_t word4; 4710 #define prli_fba_SHIFT 0 4711 #define prli_fba_MASK 0x00000001 4712 #define prli_fba_WORD word4 4713 #define prli_disc_SHIFT 3 4714 #define prli_disc_MASK 0x00000001 4715 #define prli_disc_WORD word4 4716 #define prli_tgt_SHIFT 4 4717 #define prli_tgt_MASK 0x00000001 4718 #define prli_tgt_WORD word4 4719 #define prli_init_SHIFT 5 4720 #define prli_init_MASK 0x00000001 4721 #define prli_init_WORD word4 4722 #define prli_conf_SHIFT 7 4723 #define prli_conf_MASK 0x00000001 4724 #define prli_conf_WORD word4 4725 #define prli_nsler_SHIFT 8 4726 #define prli_nsler_MASK 0x00000001 4727 #define prli_nsler_WORD word4 4728 uint32_t word5; 4729 #define prli_fb_sz_SHIFT 0 4730 #define prli_fb_sz_MASK 0x0000ffff 4731 #define prli_fb_sz_WORD word5 4732 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4733 }; 4734 4735 struct create_xri_wqe { 4736 uint32_t rsrvd[5]; /* words 0-4 */ 4737 struct wqe_did wqe_dest; /* word 5 */ 4738 struct wqe_common wqe_com; /* words 6-11 */ 4739 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4740 }; 4741 4742 #define T_REQUEST_TAG 3 4743 #define T_XRI_TAG 1 4744 4745 struct cmf_sync_wqe { 4746 uint32_t rsrvd[3]; 4747 uint32_t word3; 4748 #define cmf_sync_interval_SHIFT 0 4749 #define cmf_sync_interval_MASK 0x00000ffff 4750 #define cmf_sync_interval_WORD word3 4751 #define cmf_sync_afpin_SHIFT 16 4752 #define cmf_sync_afpin_MASK 0x000000001 4753 #define cmf_sync_afpin_WORD word3 4754 #define cmf_sync_asig_SHIFT 17 4755 #define cmf_sync_asig_MASK 0x000000001 4756 #define cmf_sync_asig_WORD word3 4757 #define cmf_sync_op_SHIFT 20 4758 #define cmf_sync_op_MASK 0x00000000f 4759 #define cmf_sync_op_WORD word3 4760 #define cmf_sync_ver_SHIFT 24 4761 #define cmf_sync_ver_MASK 0x0000000ff 4762 #define cmf_sync_ver_WORD word3 4763 #define LPFC_CMF_SYNC_VER 1 4764 uint32_t event_tag; 4765 uint32_t word5; 4766 #define cmf_sync_wsigmax_SHIFT 0 4767 #define cmf_sync_wsigmax_MASK 0x00000ffff 4768 #define cmf_sync_wsigmax_WORD word5 4769 #define cmf_sync_wsigcnt_SHIFT 16 4770 #define cmf_sync_wsigcnt_MASK 0x00000ffff 4771 #define cmf_sync_wsigcnt_WORD word5 4772 uint32_t word6; 4773 uint32_t word7; 4774 #define cmf_sync_cmnd_SHIFT 8 4775 #define cmf_sync_cmnd_MASK 0x0000000ff 4776 #define cmf_sync_cmnd_WORD word7 4777 uint32_t word8; 4778 uint32_t word9; 4779 #define cmf_sync_reqtag_SHIFT 0 4780 #define cmf_sync_reqtag_MASK 0x00000ffff 4781 #define cmf_sync_reqtag_WORD word9 4782 #define cmf_sync_wfpinmax_SHIFT 16 4783 #define cmf_sync_wfpinmax_MASK 0x0000000ff 4784 #define cmf_sync_wfpinmax_WORD word9 4785 #define cmf_sync_wfpincnt_SHIFT 24 4786 #define cmf_sync_wfpincnt_MASK 0x0000000ff 4787 #define cmf_sync_wfpincnt_WORD word9 4788 uint32_t word10; 4789 #define cmf_sync_qosd_SHIFT 9 4790 #define cmf_sync_qosd_MASK 0x00000001 4791 #define cmf_sync_qosd_WORD word10 4792 uint32_t word11; 4793 #define cmf_sync_cmd_type_SHIFT 0 4794 #define cmf_sync_cmd_type_MASK 0x0000000f 4795 #define cmf_sync_cmd_type_WORD word11 4796 #define cmf_sync_wqec_SHIFT 7 4797 #define cmf_sync_wqec_MASK 0x00000001 4798 #define cmf_sync_wqec_WORD word11 4799 #define cmf_sync_cqid_SHIFT 16 4800 #define cmf_sync_cqid_MASK 0x0000ffff 4801 #define cmf_sync_cqid_WORD word11 4802 uint32_t read_bytes; 4803 uint32_t word13; 4804 #define cmf_sync_period_SHIFT 24 4805 #define cmf_sync_period_MASK 0x000000ff 4806 #define cmf_sync_period_WORD word13 4807 uint32_t word14; 4808 uint32_t word15; 4809 }; 4810 4811 struct abort_cmd_wqe { 4812 uint32_t rsrvd[3]; 4813 uint32_t word3; 4814 #define abort_cmd_ia_SHIFT 0 4815 #define abort_cmd_ia_MASK 0x000000001 4816 #define abort_cmd_ia_WORD word3 4817 #define abort_cmd_criteria_SHIFT 8 4818 #define abort_cmd_criteria_MASK 0x0000000ff 4819 #define abort_cmd_criteria_WORD word3 4820 uint32_t rsrvd4; 4821 uint32_t rsrvd5; 4822 struct wqe_common wqe_com; /* words 6-11 */ 4823 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4824 }; 4825 4826 struct fcp_iwrite64_wqe { 4827 struct ulp_bde64 bde; 4828 uint32_t word3; 4829 #define cmd_buff_len_SHIFT 16 4830 #define cmd_buff_len_MASK 0x00000ffff 4831 #define cmd_buff_len_WORD word3 4832 /* Note: payload_offset_len field depends on ASIC support */ 4833 #define payload_offset_len_SHIFT 0 4834 #define payload_offset_len_MASK 0x0000ffff 4835 #define payload_offset_len_WORD word3 4836 uint32_t total_xfer_len; 4837 uint32_t initial_xfer_len; 4838 struct wqe_common wqe_com; /* words 6-11 */ 4839 uint32_t rsrvd12; 4840 struct ulp_bde64 ph_bde; /* words 13-15 */ 4841 }; 4842 4843 struct fcp_iread64_wqe { 4844 struct ulp_bde64 bde; 4845 uint32_t word3; 4846 #define cmd_buff_len_SHIFT 16 4847 #define cmd_buff_len_MASK 0x00000ffff 4848 #define cmd_buff_len_WORD word3 4849 /* Note: payload_offset_len field depends on ASIC support */ 4850 #define payload_offset_len_SHIFT 0 4851 #define payload_offset_len_MASK 0x0000ffff 4852 #define payload_offset_len_WORD word3 4853 uint32_t total_xfer_len; /* word 4 */ 4854 uint32_t rsrvd5; /* word 5 */ 4855 struct wqe_common wqe_com; /* words 6-11 */ 4856 uint32_t rsrvd12; 4857 struct ulp_bde64 ph_bde; /* words 13-15 */ 4858 }; 4859 4860 struct fcp_icmnd64_wqe { 4861 struct ulp_bde64 bde; /* words 0-2 */ 4862 uint32_t word3; 4863 #define cmd_buff_len_SHIFT 16 4864 #define cmd_buff_len_MASK 0x00000ffff 4865 #define cmd_buff_len_WORD word3 4866 /* Note: payload_offset_len field depends on ASIC support */ 4867 #define payload_offset_len_SHIFT 0 4868 #define payload_offset_len_MASK 0x0000ffff 4869 #define payload_offset_len_WORD word3 4870 uint32_t rsrvd4; /* word 4 */ 4871 uint32_t rsrvd5; /* word 5 */ 4872 struct wqe_common wqe_com; /* words 6-11 */ 4873 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4874 }; 4875 4876 struct fcp_trsp64_wqe { 4877 struct ulp_bde64 bde; 4878 uint32_t response_len; 4879 uint32_t rsvd_4_5[2]; 4880 struct wqe_common wqe_com; /* words 6-11 */ 4881 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4882 }; 4883 4884 struct fcp_tsend64_wqe { 4885 struct ulp_bde64 bde; 4886 uint32_t payload_offset_len; 4887 uint32_t relative_offset; 4888 uint32_t reserved; 4889 struct wqe_common wqe_com; /* words 6-11 */ 4890 uint32_t fcp_data_len; /* word 12 */ 4891 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4892 }; 4893 4894 struct fcp_treceive64_wqe { 4895 struct ulp_bde64 bde; 4896 uint32_t payload_offset_len; 4897 uint32_t relative_offset; 4898 uint32_t reserved; 4899 struct wqe_common wqe_com; /* words 6-11 */ 4900 uint32_t fcp_data_len; /* word 12 */ 4901 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4902 }; 4903 #define TXRDY_PAYLOAD_LEN 12 4904 4905 #define CMD_SEND_FRAME 0xE1 4906 4907 struct send_frame_wqe { 4908 struct ulp_bde64 bde; /* words 0-2 */ 4909 uint32_t frame_len; /* word 3 */ 4910 uint32_t fc_hdr_wd0; /* word 4 */ 4911 uint32_t fc_hdr_wd1; /* word 5 */ 4912 struct wqe_common wqe_com; /* words 6-11 */ 4913 uint32_t fc_hdr_wd2; /* word 12 */ 4914 uint32_t fc_hdr_wd3; /* word 13 */ 4915 uint32_t fc_hdr_wd4; /* word 14 */ 4916 uint32_t fc_hdr_wd5; /* word 15 */ 4917 }; 4918 4919 #define ELS_RDF_REG_TAG_CNT 4 4920 struct lpfc_els_rdf_reg_desc { 4921 struct fc_df_desc_fpin_reg_hdr reg_desc; /* descriptor header */ 4922 __be32 desc_tags[ELS_RDF_REG_TAG_CNT]; 4923 /* tags in reg_desc */ 4924 }; 4925 4926 struct lpfc_els_rdf_req { 4927 struct fc_els_rdf_hdr rdf; /* hdr up to descriptors */ 4928 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4929 }; 4930 4931 struct lpfc_els_rdf_rsp { 4932 struct fc_els_rdf_resp_hdr rdf_resp; /* hdr up to descriptors */ 4933 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4934 }; 4935 4936 union lpfc_wqe { 4937 uint32_t words[16]; 4938 struct lpfc_wqe_generic generic; 4939 struct fcp_icmnd64_wqe fcp_icmd; 4940 struct fcp_iread64_wqe fcp_iread; 4941 struct fcp_iwrite64_wqe fcp_iwrite; 4942 struct abort_cmd_wqe abort_cmd; 4943 struct cmf_sync_wqe cmf_sync; 4944 struct create_xri_wqe create_xri; 4945 struct xmit_bcast64_wqe xmit_bcast64; 4946 struct xmit_seq64_wqe xmit_sequence; 4947 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4948 struct xmit_els_rsp64_wqe xmit_els_rsp; 4949 struct els_request64_wqe els_req; 4950 struct gen_req64_wqe gen_req; 4951 struct fcp_trsp64_wqe fcp_trsp; 4952 struct fcp_tsend64_wqe fcp_tsend; 4953 struct fcp_treceive64_wqe fcp_treceive; 4954 struct send_frame_wqe send_frame; 4955 }; 4956 4957 union lpfc_wqe128 { 4958 uint32_t words[32]; 4959 struct lpfc_wqe_generic generic; 4960 struct fcp_icmnd64_wqe fcp_icmd; 4961 struct fcp_iread64_wqe fcp_iread; 4962 struct fcp_iwrite64_wqe fcp_iwrite; 4963 struct abort_cmd_wqe abort_cmd; 4964 struct cmf_sync_wqe cmf_sync; 4965 struct create_xri_wqe create_xri; 4966 struct xmit_bcast64_wqe xmit_bcast64; 4967 struct xmit_seq64_wqe xmit_sequence; 4968 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4969 struct xmit_els_rsp64_wqe xmit_els_rsp; 4970 struct els_request64_wqe els_req; 4971 struct gen_req64_wqe gen_req; 4972 struct fcp_trsp64_wqe fcp_trsp; 4973 struct fcp_tsend64_wqe fcp_tsend; 4974 struct fcp_treceive64_wqe fcp_treceive; 4975 struct send_frame_wqe send_frame; 4976 }; 4977 4978 #define MAGIC_NUMBER_G6 0xFEAA0003 4979 #define MAGIC_NUMBER_G7 0xFEAA0005 4980 #define MAGIC_NUMBER_G7P 0xFEAA0020 4981 4982 struct lpfc_grp_hdr { 4983 uint32_t size; 4984 uint32_t magic_number; 4985 uint32_t word2; 4986 #define lpfc_grp_hdr_file_type_SHIFT 24 4987 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4988 #define lpfc_grp_hdr_file_type_WORD word2 4989 #define lpfc_grp_hdr_id_SHIFT 16 4990 #define lpfc_grp_hdr_id_MASK 0x000000FF 4991 #define lpfc_grp_hdr_id_WORD word2 4992 uint8_t rev_name[128]; 4993 uint8_t date[12]; 4994 uint8_t revision[32]; 4995 }; 4996 4997 /* Defines for WQE command type */ 4998 #define FCP_COMMAND 0x0 4999 #define NVME_READ_CMD 0x0 5000 #define FCP_COMMAND_DATA_OUT 0x1 5001 #define NVME_WRITE_CMD 0x1 5002 #define COMMAND_DATA_IN 0x0 5003 #define COMMAND_DATA_OUT 0x1 5004 #define FCP_COMMAND_TRECEIVE 0x2 5005 #define FCP_COMMAND_TRSP 0x3 5006 #define FCP_COMMAND_TSEND 0x7 5007 #define OTHER_COMMAND 0x8 5008 #define CMF_SYNC_COMMAND 0xA 5009 #define ELS_COMMAND_NON_FIP 0xC 5010 #define ELS_COMMAND_FIP 0xD 5011 5012 #define LPFC_NVME_EMBED_CMD 0x0 5013 #define LPFC_NVME_EMBED_WRITE 0x1 5014 #define LPFC_NVME_EMBED_READ 0x2 5015 5016 /* WQE Commands */ 5017 #define CMD_ABORT_XRI_WQE 0x0F 5018 #define CMD_XMIT_SEQUENCE64_WQE 0x82 5019 #define CMD_XMIT_BCAST64_WQE 0x84 5020 #define CMD_ELS_REQUEST64_WQE 0x8A 5021 #define CMD_XMIT_ELS_RSP64_WQE 0x95 5022 #define CMD_XMIT_BLS_RSP64_WQE 0x97 5023 #define CMD_FCP_IWRITE64_WQE 0x98 5024 #define CMD_FCP_IREAD64_WQE 0x9A 5025 #define CMD_FCP_ICMND64_WQE 0x9C 5026 #define CMD_FCP_TSEND64_WQE 0x9F 5027 #define CMD_FCP_TRECEIVE64_WQE 0xA1 5028 #define CMD_FCP_TRSP64_WQE 0xA3 5029 #define CMD_GEN_REQUEST64_WQE 0xC2 5030 #define CMD_CMF_SYNC_WQE 0xE8 5031 5032 #define CMD_WQE_MASK 0xff 5033 5034 5035 #define LPFC_FW_DUMP 1 5036 #define LPFC_FW_RESET 2 5037 #define LPFC_DV_RESET 3 5038 5039 /* On some kernels, enum fc_ls_tlv_dtag does not have 5040 * these 2 enums defined, on other kernels it does. 5041 * To get aound this we need to add these 2 defines here. 5042 */ 5043 #ifndef ELS_DTAG_LNK_FAULT_CAP 5044 #define ELS_DTAG_LNK_FAULT_CAP 0x0001000D 5045 #endif 5046 #ifndef ELS_DTAG_CG_SIGNAL_CAP 5047 #define ELS_DTAG_CG_SIGNAL_CAP 0x0001000F 5048 #endif 5049 5050 /* 5051 * Initializer useful for decoding FPIN string table. 5052 */ 5053 #define FC_FPIN_CONGN_SEVERITY_INIT { \ 5054 { FPIN_CONGN_SEVERITY_WARNING, "Warning" }, \ 5055 { FPIN_CONGN_SEVERITY_ERROR, "Alarm" }, \ 5056 } 5057 5058 /* Used for logging FPIN messages */ 5059 #define LPFC_FPIN_WWPN_LINE_SZ 128 5060 #define LPFC_FPIN_WWPN_LINE_CNT 6 5061 #define LPFC_FPIN_WWPN_NUM_LINE 6 5062