1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2024 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #define FDMI_DID 0xfffffaU 24 #define NameServer_DID 0xfffffcU 25 #define Fabric_Cntl_DID 0xfffffdU 26 #define Fabric_DID 0xfffffeU 27 #define Bcast_DID 0xffffffU 28 #define Mask_DID 0xffffffU 29 #define CT_DID_MASK 0xffff00U 30 #define Fabric_DID_MASK 0xfff000U 31 #define WELL_KNOWN_DID_MASK 0xfffff0U 32 33 #define PT2PT_LocalID 1 34 #define PT2PT_RemoteID 2 35 36 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 37 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 38 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */ 39 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 40 41 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 42 0 */ 43 44 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 45 46 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 47 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 48 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 49 50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 58 #define SLI2_IOCB_CMD_R3_ENTRIES 0 59 #define SLI2_IOCB_RSP_R3_ENTRIES 0 60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 62 63 #define SLI2_IOCB_CMD_SIZE 32 64 #define SLI2_IOCB_RSP_SIZE 32 65 #define SLI3_IOCB_CMD_SIZE 128 66 #define SLI3_IOCB_RSP_SIZE 64 67 68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 70 71 /* vendor ID used in SCSI netlink calls */ 72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 73 74 #define FW_REV_STR_SIZE 32 75 /* Common Transport structures and definitions */ 76 77 union CtRevisionId { 78 /* Structure is in Big Endian format */ 79 struct { 80 uint32_t Revision:8; 81 uint32_t InId:24; 82 } bits; 83 uint32_t word; 84 }; 85 86 union CtCommandResponse { 87 /* Structure is in Big Endian format */ 88 struct { 89 __be16 CmdRsp; 90 __be16 Size; 91 } bits; 92 uint32_t word; 93 }; 94 95 /* FC4 Feature bits for RFF_ID */ 96 #define FC4_FEATURE_TARGET 0x1 97 #define FC4_FEATURE_INIT 0x2 98 #define FC4_FEATURE_NVME_DISC 0x4 99 100 enum rft_word0 { 101 RFT_FCP_REG = (0x1 << 8), 102 }; 103 104 enum rft_word1 { 105 RFT_NVME_REG = (0x1 << 8), 106 }; 107 108 enum rft_word3 { 109 RFT_APP_SERV_REG = (0x1 << 0), 110 }; 111 112 struct lpfc_sli_ct_request { 113 /* Structure is in Big Endian format */ 114 union CtRevisionId RevisionId; 115 uint8_t FsType; 116 uint8_t FsSubType; 117 uint8_t Options; 118 uint8_t Rsrvd1; 119 union CtCommandResponse CommandResponse; 120 uint8_t Rsrvd2; 121 uint8_t ReasonCode; 122 uint8_t Explanation; 123 uint8_t VendorUnique; 124 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */ 125 126 union { 127 __be32 PortID; 128 struct gid { 129 uint8_t PortType; /* for GID_PT requests */ 130 #define GID_PT_N_PORT 1 131 uint8_t DomainScope; 132 uint8_t AreaScope; 133 uint8_t Fc4Type; /* for GID_FT requests */ 134 } gid; 135 struct gid_ff { 136 uint8_t Flags; 137 uint8_t DomainScope; 138 uint8_t AreaScope; 139 uint8_t rsvd1; 140 uint8_t rsvd2; 141 uint8_t rsvd3; 142 uint8_t Fc4FBits; 143 uint8_t Fc4Type; 144 } gid_ff; 145 struct rft { 146 __be32 port_id; /* For RFT_ID requests */ 147 148 __be32 fcp_reg; /* rsvd 31:9, fcp_reg 8, rsvd 7:0 */ 149 __be32 nvme_reg; /* rsvd 31:9, nvme_reg 8, rsvd 7:0 */ 150 __be32 word2; 151 __be32 app_serv_reg; /* rsvd 31:1, app_serv_reg 0 */ 152 __be32 word[4]; 153 } rft; 154 struct rnn { 155 uint32_t PortId; /* For RNN_ID requests */ 156 uint8_t wwnn[8]; 157 } rnn; 158 struct rsnn { /* For RSNN_ID requests */ 159 uint8_t wwnn[8]; 160 uint8_t len; 161 uint8_t symbname[255]; 162 } rsnn; 163 struct da_id { /* For DA_ID requests */ 164 uint32_t port_id; 165 } da_id; 166 struct rspn { /* For RSPN_ID requests */ 167 uint32_t PortId; 168 uint8_t len; 169 uint8_t symbname[255]; 170 } rspn; 171 struct gff { 172 uint32_t PortId; 173 } gff; 174 struct gff_acc { 175 uint8_t fbits[128]; 176 } gff_acc; 177 struct gft { 178 uint32_t PortId; 179 } gft; 180 struct gft_acc { 181 uint32_t fc4_types[8]; 182 } gft_acc; 183 #define FCP_TYPE_FEATURE_OFFSET 7 184 struct rff { 185 uint32_t PortId; 186 uint8_t reserved[2]; 187 uint8_t fbits; 188 uint8_t type_code; /* type=8 for FCP */ 189 } rff; 190 } un; 191 }; 192 193 #define LPFC_MAX_CT_SIZE (60 * 4096) 194 195 #define SLI_CT_REVISION 1 196 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 197 sizeof(struct gid)) 198 #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 199 sizeof(struct gid_ff)) 200 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 201 sizeof(struct gff)) 202 #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 203 sizeof(struct gft)) 204 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 205 sizeof(struct rft)) 206 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 207 sizeof(struct rff)) 208 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 209 sizeof(struct rnn)) 210 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 211 sizeof(struct rsnn)) 212 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 213 sizeof(struct da_id)) 214 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 215 sizeof(struct rspn)) 216 217 /* 218 * FsType Definitions 219 */ 220 221 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 222 #define SLI_CT_TIME_SERVICE 0xFB 223 #define SLI_CT_DIRECTORY_SERVICE 0xFC 224 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 225 226 /* 227 * Directory Service Subtypes 228 */ 229 230 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 231 232 /* 233 * Response Codes 234 */ 235 236 #define SLI_CT_RESPONSE_FS_RJT 0x8001 237 #define SLI_CT_RESPONSE_FS_ACC 0x8002 238 239 /* 240 * Reason Codes 241 */ 242 243 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 244 #define SLI_CT_INVALID_COMMAND 0x01 245 #define SLI_CT_INVALID_VERSION 0x02 246 #define SLI_CT_LOGICAL_ERROR 0x03 247 #define SLI_CT_INVALID_IU_SIZE 0x04 248 #define SLI_CT_LOGICAL_BUSY 0x05 249 #define SLI_CT_PROTOCOL_ERROR 0x07 250 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 251 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 252 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 253 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 254 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 255 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 256 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 257 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 258 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 259 #define SLI_CT_VENDOR_UNIQUE 0xff 260 261 /* 262 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 263 */ 264 265 #define SLI_CT_NO_PORT_ID 0x01 266 #define SLI_CT_NO_PORT_NAME 0x02 267 #define SLI_CT_NO_NODE_NAME 0x03 268 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 269 #define SLI_CT_NO_IP_ADDRESS 0x05 270 #define SLI_CT_NO_IPA 0x06 271 #define SLI_CT_NO_FC4_TYPES 0x07 272 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 273 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 274 #define SLI_CT_NO_PORT_TYPE 0x0A 275 #define SLI_CT_ACCESS_DENIED 0x10 276 #define SLI_CT_INVALID_PORT_ID 0x11 277 #define SLI_CT_DATABASE_EMPTY 0x12 278 #define SLI_CT_APP_ID_NOT_AVAILABLE 0x40 279 280 /* 281 * Name Server Command Codes 282 */ 283 284 #define SLI_CTNS_GA_NXT 0x0100 285 #define SLI_CTNS_GPN_ID 0x0112 286 #define SLI_CTNS_GNN_ID 0x0113 287 #define SLI_CTNS_GCS_ID 0x0114 288 #define SLI_CTNS_GFT_ID 0x0117 289 #define SLI_CTNS_GSPN_ID 0x0118 290 #define SLI_CTNS_GPT_ID 0x011A 291 #define SLI_CTNS_GFF_ID 0x011F 292 #define SLI_CTNS_GID_PN 0x0121 293 #define SLI_CTNS_GID_NN 0x0131 294 #define SLI_CTNS_GIP_NN 0x0135 295 #define SLI_CTNS_GIPA_NN 0x0136 296 #define SLI_CTNS_GSNN_NN 0x0139 297 #define SLI_CTNS_GNN_IP 0x0153 298 #define SLI_CTNS_GIPA_IP 0x0156 299 #define SLI_CTNS_GID_FT 0x0171 300 #define SLI_CTNS_GID_FF 0x01F1 301 #define SLI_CTNS_GID_PT 0x01A1 302 #define SLI_CTNS_RPN_ID 0x0212 303 #define SLI_CTNS_RNN_ID 0x0213 304 #define SLI_CTNS_RCS_ID 0x0214 305 #define SLI_CTNS_RFT_ID 0x0217 306 #define SLI_CTNS_RSPN_ID 0x0218 307 #define SLI_CTNS_RPT_ID 0x021A 308 #define SLI_CTNS_RFF_ID 0x021F 309 #define SLI_CTNS_RIP_NN 0x0235 310 #define SLI_CTNS_RIPA_NN 0x0236 311 #define SLI_CTNS_RSNN_NN 0x0239 312 #define SLI_CTNS_DA_ID 0x0300 313 314 /* 315 * Port Types 316 */ 317 318 #define SLI_CTPT_N_PORT 0x01 319 #define SLI_CTPT_NL_PORT 0x02 320 #define SLI_CTPT_FNL_PORT 0x03 321 #define SLI_CTPT_IP 0x04 322 #define SLI_CTPT_FCP 0x08 323 #define SLI_CTPT_NVME 0x28 324 #define SLI_CTPT_NX_PORT 0x7F 325 #define SLI_CTPT_F_PORT 0x81 326 #define SLI_CTPT_FL_PORT 0x82 327 #define SLI_CTPT_E_PORT 0x84 328 329 #define SLI_CT_LAST_ENTRY 0x80000000 330 331 /* Fibre Channel Service Parameter definitions */ 332 333 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 334 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 335 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 336 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 337 338 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 339 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 340 #define FC_PH3 0x20 /* FC-PH-3 version */ 341 342 #define FF_FRAME_SIZE 2048 343 344 struct lpfc_name { 345 union { 346 struct { 347 #ifdef __BIG_ENDIAN_BITFIELD 348 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 349 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 350 8:11 of IEEE ext */ 351 #else /* __LITTLE_ENDIAN_BITFIELD */ 352 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 353 8:11 of IEEE ext */ 354 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 355 #endif 356 357 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 358 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 359 #define NAME_FC_TYPE 0x3 /* FC native name type */ 360 #define NAME_IP_TYPE 0x4 /* IP address */ 361 #define NAME_CCITT_TYPE 0xC 362 #define NAME_CCITT_GR_TYPE 0xE 363 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 364 extended Lsb */ 365 uint8_t IEEE[6]; /* FC IEEE address */ 366 } s; 367 uint8_t wwn[8]; 368 uint64_t name __packed __aligned(4); 369 } u; 370 }; 371 372 struct csp { 373 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 374 uint8_t fcphLow; 375 uint8_t bbCreditMsb; 376 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */ 377 378 /* 379 * Word 1 Bit 31 in common service parameter is overloaded. 380 * Word 1 Bit 31 in FLOGI request is multiple NPort request 381 * Word 1 Bit 31 in FLOGI response is clean address bit 382 */ 383 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 384 /* 385 * Word 1 Bit 30 in common service parameter is overloaded. 386 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 387 * Word 1 Bit 30 in PLOGI request is random offset 388 */ 389 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 390 /* 391 * Word 1 Bit 29 in common service parameter is overloaded. 392 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment 393 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level 394 */ 395 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */ 396 #ifdef __BIG_ENDIAN_BITFIELD 397 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 398 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 399 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 400 uint16_t fPort:1; /* FC Word 1, bit 28 */ 401 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 402 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 403 uint16_t multicast:1; /* FC Word 1, bit 25 */ 404 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ 405 406 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ 407 uint16_t simplex:1; /* FC Word 1, bit 22 */ 408 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 409 uint16_t dhd:1; /* FC Word 1, bit 18 */ 410 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 411 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 412 #else /* __LITTLE_ENDIAN_BITFIELD */ 413 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ 414 uint16_t multicast:1; /* FC Word 1, bit 25 */ 415 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 416 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 417 uint16_t fPort:1; /* FC Word 1, bit 28 */ 418 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 419 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 420 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 421 422 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 423 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 424 uint16_t dhd:1; /* FC Word 1, bit 18 */ 425 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 426 uint16_t simplex:1; /* FC Word 1, bit 22 */ 427 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ 428 #endif 429 430 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 431 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 432 union { 433 struct { 434 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 435 436 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 437 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 438 439 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 440 } nPort; 441 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 442 } w2; 443 444 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 445 }; 446 447 struct class_parms { 448 #ifdef __BIG_ENDIAN_BITFIELD 449 uint8_t classValid:1; /* FC Word 0, bit 31 */ 450 uint8_t intermix:1; /* FC Word 0, bit 30 */ 451 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 452 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 453 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 454 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 455 #else /* __LITTLE_ENDIAN_BITFIELD */ 456 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 457 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 458 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 459 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 460 uint8_t intermix:1; /* FC Word 0, bit 30 */ 461 uint8_t classValid:1; /* FC Word 0, bit 31 */ 462 463 #endif 464 465 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 466 467 #ifdef __BIG_ENDIAN_BITFIELD 468 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 469 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 470 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 471 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 472 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 473 #else /* __LITTLE_ENDIAN_BITFIELD */ 474 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 475 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 476 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 477 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 478 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 479 #endif 480 481 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 482 483 #ifdef __BIG_ENDIAN_BITFIELD 484 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 485 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 486 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 487 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 488 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 489 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 490 #else /* __LITTLE_ENDIAN_BITFIELD */ 491 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 492 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 493 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 494 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 495 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 496 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 497 #endif 498 499 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 500 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 501 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 502 503 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 504 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 505 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 506 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 507 508 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 509 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 510 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 511 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 512 }; 513 514 struct serv_parm { /* Structure is in Big Endian format */ 515 struct csp cmn; 516 struct lpfc_name portName; 517 struct lpfc_name nodeName; 518 struct class_parms cls1; 519 struct class_parms cls2; 520 struct class_parms cls3; 521 struct class_parms cls4; 522 union { 523 uint8_t vendorVersion[16]; 524 struct { 525 uint32_t vid; 526 #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */ 527 uint32_t flags; 528 #define LPFC_VV_SUPPRESS_RSP 1 529 } vv; 530 } un; 531 }; 532 533 /* 534 * Virtual Fabric Tagging Header 535 */ 536 struct fc_vft_header { 537 uint32_t word0; 538 #define fc_vft_hdr_r_ctl_SHIFT 24 539 #define fc_vft_hdr_r_ctl_MASK 0xFF 540 #define fc_vft_hdr_r_ctl_WORD word0 541 #define fc_vft_hdr_ver_SHIFT 22 542 #define fc_vft_hdr_ver_MASK 0x3 543 #define fc_vft_hdr_ver_WORD word0 544 #define fc_vft_hdr_type_SHIFT 18 545 #define fc_vft_hdr_type_MASK 0xF 546 #define fc_vft_hdr_type_WORD word0 547 #define fc_vft_hdr_e_SHIFT 16 548 #define fc_vft_hdr_e_MASK 0x1 549 #define fc_vft_hdr_e_WORD word0 550 #define fc_vft_hdr_priority_SHIFT 13 551 #define fc_vft_hdr_priority_MASK 0x7 552 #define fc_vft_hdr_priority_WORD word0 553 #define fc_vft_hdr_vf_id_SHIFT 1 554 #define fc_vft_hdr_vf_id_MASK 0xFFF 555 #define fc_vft_hdr_vf_id_WORD word0 556 uint32_t word1; 557 #define fc_vft_hdr_hopct_SHIFT 24 558 #define fc_vft_hdr_hopct_MASK 0xFF 559 #define fc_vft_hdr_hopct_WORD word1 560 }; 561 562 #include <uapi/scsi/fc/fc_els.h> 563 564 /* 565 * Application Header 566 */ 567 struct fc_app_header { 568 uint32_t dst_app_id; 569 uint32_t src_app_id; 570 #define LOOPBACK_SRC_APPID 0x4321 571 uint32_t word2; 572 uint32_t word3; 573 }; 574 575 /* 576 * dfctl optional header definition 577 */ 578 enum lpfc_fc_dfctl { 579 LPFC_FC_NO_DEVICE_HEADER, 580 LPFC_FC_16B_DEVICE_HEADER, 581 LPFC_FC_32B_DEVICE_HEADER, 582 LPFC_FC_64B_DEVICE_HEADER, 583 }; 584 585 /* 586 * Extended Link Service LS_COMMAND codes (Payload Word 0) 587 */ 588 #ifdef __BIG_ENDIAN_BITFIELD 589 #define ELS_CMD_MASK 0xffff0000 590 #define ELS_RSP_MASK 0xff000000 591 #define ELS_CMD_LS_RJT 0x01000000 592 #define ELS_CMD_ACC 0x02000000 593 #define ELS_CMD_PLOGI 0x03000000 594 #define ELS_CMD_FLOGI 0x04000000 595 #define ELS_CMD_LOGO 0x05000000 596 #define ELS_CMD_ABTX 0x06000000 597 #define ELS_CMD_RCS 0x07000000 598 #define ELS_CMD_RES 0x08000000 599 #define ELS_CMD_RSS 0x09000000 600 #define ELS_CMD_RSI 0x0A000000 601 #define ELS_CMD_ESTS 0x0B000000 602 #define ELS_CMD_ESTC 0x0C000000 603 #define ELS_CMD_ADVC 0x0D000000 604 #define ELS_CMD_RTV 0x0E000000 605 #define ELS_CMD_RLS 0x0F000000 606 #define ELS_CMD_ECHO 0x10000000 607 #define ELS_CMD_TEST 0x11000000 608 #define ELS_CMD_RRQ 0x12000000 609 #define ELS_CMD_REC 0x13000000 610 #define ELS_CMD_RDP 0x18000000 611 #define ELS_CMD_RDF 0x19000000 612 #define ELS_CMD_PRLI 0x20100014 613 #define ELS_CMD_NVMEPRLI 0x20140018 614 #define ELS_CMD_PRLO 0x21100014 615 #define ELS_CMD_PRLO_ACC 0x02100014 616 #define ELS_CMD_PDISC 0x50000000 617 #define ELS_CMD_FDISC 0x51000000 618 #define ELS_CMD_ADISC 0x52000000 619 #define ELS_CMD_FARP 0x54000000 620 #define ELS_CMD_FARPR 0x55000000 621 #define ELS_CMD_RPL 0x57000000 622 #define ELS_CMD_FAN 0x60000000 623 #define ELS_CMD_RSCN 0x61040000 624 #define ELS_CMD_RSCN_XMT 0x61040008 625 #define ELS_CMD_SCR 0x62000000 626 #define ELS_CMD_RNID 0x78000000 627 #define ELS_CMD_LIRR 0x7A000000 628 #define ELS_CMD_LCB 0x81000000 629 #define ELS_CMD_FPIN 0x16000000 630 #define ELS_CMD_EDC 0x17000000 631 #define ELS_CMD_QFPA 0xB0000000 632 #define ELS_CMD_UVEM 0xB1000000 633 #else /* __LITTLE_ENDIAN_BITFIELD */ 634 #define ELS_CMD_MASK 0xffff 635 #define ELS_RSP_MASK 0xff 636 #define ELS_CMD_LS_RJT 0x01 637 #define ELS_CMD_ACC 0x02 638 #define ELS_CMD_PLOGI 0x03 639 #define ELS_CMD_FLOGI 0x04 640 #define ELS_CMD_LOGO 0x05 641 #define ELS_CMD_ABTX 0x06 642 #define ELS_CMD_RCS 0x07 643 #define ELS_CMD_RES 0x08 644 #define ELS_CMD_RSS 0x09 645 #define ELS_CMD_RSI 0x0A 646 #define ELS_CMD_ESTS 0x0B 647 #define ELS_CMD_ESTC 0x0C 648 #define ELS_CMD_ADVC 0x0D 649 #define ELS_CMD_RTV 0x0E 650 #define ELS_CMD_RLS 0x0F 651 #define ELS_CMD_ECHO 0x10 652 #define ELS_CMD_TEST 0x11 653 #define ELS_CMD_RRQ 0x12 654 #define ELS_CMD_REC 0x13 655 #define ELS_CMD_RDP 0x18 656 #define ELS_CMD_RDF 0x19 657 #define ELS_CMD_PRLI 0x14001020 658 #define ELS_CMD_NVMEPRLI 0x18001420 659 #define ELS_CMD_PRLO 0x14001021 660 #define ELS_CMD_PRLO_ACC 0x14001002 661 #define ELS_CMD_PDISC 0x50 662 #define ELS_CMD_FDISC 0x51 663 #define ELS_CMD_ADISC 0x52 664 #define ELS_CMD_FARP 0x54 665 #define ELS_CMD_FARPR 0x55 666 #define ELS_CMD_RPL 0x57 667 #define ELS_CMD_FAN 0x60 668 #define ELS_CMD_RSCN 0x0461 669 #define ELS_CMD_RSCN_XMT 0x08000461 670 #define ELS_CMD_SCR 0x62 671 #define ELS_CMD_RNID 0x78 672 #define ELS_CMD_LIRR 0x7A 673 #define ELS_CMD_LCB 0x81 674 #define ELS_CMD_FPIN ELS_FPIN 675 #define ELS_CMD_EDC ELS_EDC 676 #define ELS_CMD_QFPA 0xB0 677 #define ELS_CMD_UVEM 0xB1 678 #endif 679 680 /* 681 * LS_RJT Payload Definition 682 */ 683 684 struct ls_rjt { /* Structure is in Big Endian format */ 685 union { 686 __be32 ls_rjt_error_be; 687 uint32_t lsRjtError; 688 struct { 689 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 690 691 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 692 /* LS_RJT reason codes */ 693 #define LSRJT_INVALID_CMD 0x01 694 #define LSRJT_LOGICAL_ERR 0x03 695 #define LSRJT_LOGICAL_BSY 0x05 696 #define LSRJT_PROTOCOL_ERR 0x07 697 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 698 #define LSRJT_CMD_UNSUPPORTED 0x0B 699 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 700 701 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 702 /* LS_RJT reason explanation */ 703 #define LSEXP_NOTHING_MORE 0x00 704 #define LSEXP_SPARM_OPTIONS 0x01 705 #define LSEXP_SPARM_ICTL 0x03 706 #define LSEXP_SPARM_RCTL 0x05 707 #define LSEXP_SPARM_RCV_SIZE 0x07 708 #define LSEXP_SPARM_CONCUR_SEQ 0x09 709 #define LSEXP_SPARM_CREDIT 0x0B 710 #define LSEXP_INVALID_PNAME 0x0D 711 #define LSEXP_INVALID_NNAME 0x0E 712 #define LSEXP_INVALID_CSP 0x0F 713 #define LSEXP_INVALID_ASSOC_HDR 0x11 714 #define LSEXP_ASSOC_HDR_REQ 0x13 715 #define LSEXP_INVALID_O_SID 0x15 716 #define LSEXP_INVALID_OX_RX 0x17 717 #define LSEXP_CMD_IN_PROGRESS 0x19 718 #define LSEXP_PORT_LOGIN_REQ 0x1E 719 #define LSEXP_INVALID_NPORT_ID 0x1F 720 #define LSEXP_INVALID_SEQ_ID 0x21 721 #define LSEXP_INVALID_XCHG 0x23 722 #define LSEXP_INACTIVE_XCHG 0x25 723 #define LSEXP_RQ_REQUIRED 0x27 724 #define LSEXP_OUT_OF_RESOURCE 0x29 725 #define LSEXP_CANT_GIVE_DATA 0x2A 726 #define LSEXP_REQ_UNSUPPORTED 0x2C 727 #define LSEXP_AUTH_REQ 0x48 728 #define LSEXP_NO_RSRC_ASSIGN 0x52 729 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 730 } b; 731 } un; 732 }; 733 734 /* 735 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 736 */ 737 738 typedef struct _LOGO { /* Structure is in Big Endian format */ 739 union { 740 uint32_t nPortId32; /* Access nPortId as a word */ 741 struct { 742 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 743 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 744 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 745 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 746 } b; 747 } un; 748 struct lpfc_name portName; /* N_port name field */ 749 } LOGO; 750 751 /* 752 * FCP Login (PRLI Request / ACC) Payload Definition 753 */ 754 755 #define PRLX_PAGE_LEN 0x10 756 #define TPRLO_PAGE_LEN 0x14 757 758 typedef struct _PRLI { /* Structure is in Big Endian format */ 759 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 760 761 #define PRLI_FCP_TYPE 0x08 762 #define PRLI_NVME_TYPE 0x28 763 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 764 765 #ifdef __BIG_ENDIAN_BITFIELD 766 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 767 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 768 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 769 770 /* ACC = imagePairEstablished */ 771 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 772 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 773 #else /* __LITTLE_ENDIAN_BITFIELD */ 774 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 775 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 776 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 777 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 778 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 779 /* ACC = imagePairEstablished */ 780 #endif 781 782 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 783 #define PRLI_NO_RESOURCES 0x2 784 #define PRLI_INIT_INCOMPLETE 0x3 785 #define PRLI_NO_SUCH_PA 0x4 786 #define PRLI_PREDEF_CONFIG 0x5 787 #define PRLI_PARTIAL_SUCCESS 0x6 788 #define PRLI_INVALID_PAGE_CNT 0x7 789 #define PRLI_INV_SRV_PARM 0x8 790 791 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 792 793 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 794 795 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 796 797 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 798 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 799 800 #ifdef __BIG_ENDIAN_BITFIELD 801 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 802 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 803 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 804 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 805 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 806 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 807 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 808 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 809 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 810 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 811 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 812 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 813 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 814 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 815 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 816 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 817 #else /* __LITTLE_ENDIAN_BITFIELD */ 818 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 819 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 820 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 821 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 822 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 823 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 824 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 825 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 826 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 827 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 828 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 829 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 830 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 831 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 832 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 833 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 834 #endif 835 } PRLI; 836 837 /* 838 * FCP Logout (PRLO Request / ACC) Payload Definition 839 */ 840 841 typedef struct _PRLO { /* Structure is in Big Endian format */ 842 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 843 844 #define PRLO_FCP_TYPE 0x08 845 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 846 847 #ifdef __BIG_ENDIAN_BITFIELD 848 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 849 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 850 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 851 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 852 #else /* __LITTLE_ENDIAN_BITFIELD */ 853 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 854 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 855 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 856 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 857 #endif 858 859 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 860 #define PRLO_NO_SUCH_IMAGE 0x4 861 #define PRLO_INVALID_PAGE_CNT 0x7 862 863 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 864 865 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 866 867 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 868 869 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 870 } PRLO; 871 872 typedef struct _ADISC { /* Structure is in Big Endian format */ 873 uint32_t hardAL_PA; 874 struct lpfc_name portName; 875 struct lpfc_name nodeName; 876 uint32_t DID; 877 } ADISC; 878 879 typedef struct _FARP { /* Structure is in Big Endian format */ 880 uint32_t Mflags:8; 881 uint32_t Odid:24; 882 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 883 action */ 884 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 885 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 886 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 887 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 888 supported */ 889 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 890 supported */ 891 uint32_t Rflags:8; 892 uint32_t Rdid:24; 893 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 894 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 895 struct lpfc_name OportName; 896 struct lpfc_name OnodeName; 897 struct lpfc_name RportName; 898 struct lpfc_name RnodeName; 899 uint8_t Oipaddr[16]; 900 uint8_t Ripaddr[16]; 901 } FARP; 902 903 typedef struct _FAN { /* Structure is in Big Endian format */ 904 uint32_t Fdid; 905 struct lpfc_name FportName; 906 struct lpfc_name FnodeName; 907 } FAN; 908 909 typedef struct _SCR { /* Structure is in Big Endian format */ 910 uint8_t resvd1; 911 uint8_t resvd2; 912 uint8_t resvd3; 913 uint8_t Function; 914 #define SCR_FUNC_FABRIC 0x01 915 #define SCR_FUNC_NPORT 0x02 916 #define SCR_FUNC_FULL 0x03 917 #define SCR_CLEAR 0xff 918 } SCR; 919 920 typedef struct _RNID_TOP_DISC { 921 struct lpfc_name portName; 922 uint8_t resvd[8]; 923 uint32_t unitType; 924 #define RNID_HBA 0x7 925 #define RNID_HOST 0xa 926 #define RNID_DRIVER 0xd 927 uint32_t physPort; 928 uint32_t attachedNodes; 929 uint16_t ipVersion; 930 #define RNID_IPV4 0x1 931 #define RNID_IPV6 0x2 932 uint16_t UDPport; 933 uint8_t ipAddr[16]; 934 uint16_t resvd1; 935 uint16_t flags; 936 #define RNID_TD_SUPPORT 0x1 937 #define RNID_LP_VALID 0x2 938 } RNID_TOP_DISC; 939 940 typedef struct _RNID { /* Structure is in Big Endian format */ 941 uint8_t Format; 942 #define RNID_TOPOLOGY_DISC 0xdf 943 uint8_t CommonLen; 944 uint8_t resvd1; 945 uint8_t SpecificLen; 946 struct lpfc_name portName; 947 struct lpfc_name nodeName; 948 union { 949 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 950 } un; 951 } RNID; 952 953 struct RLS { /* Structure is in Big Endian format */ 954 uint32_t rls; 955 #define rls_rsvd_SHIFT 24 956 #define rls_rsvd_MASK 0x000000ff 957 #define rls_rsvd_WORD rls 958 #define rls_did_SHIFT 0 959 #define rls_did_MASK 0x00ffffff 960 #define rls_did_WORD rls 961 }; 962 963 struct RLS_RSP { /* Structure is in Big Endian format */ 964 uint32_t linkFailureCnt; 965 uint32_t lossSyncCnt; 966 uint32_t lossSignalCnt; 967 uint32_t primSeqErrCnt; 968 uint32_t invalidXmitWord; 969 uint32_t crcCnt; 970 }; 971 972 struct RRQ { /* Structure is in Big Endian format */ 973 uint32_t rrq; 974 #define rrq_rsvd_SHIFT 24 975 #define rrq_rsvd_MASK 0x000000ff 976 #define rrq_rsvd_WORD rrq 977 #define rrq_did_SHIFT 0 978 #define rrq_did_MASK 0x00ffffff 979 #define rrq_did_WORD rrq 980 uint32_t rrq_exchg; 981 #define rrq_oxid_SHIFT 16 982 #define rrq_oxid_MASK 0xffff 983 #define rrq_oxid_WORD rrq_exchg 984 #define rrq_rxid_SHIFT 0 985 #define rrq_rxid_MASK 0xffff 986 #define rrq_rxid_WORD rrq_exchg 987 }; 988 989 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 990 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 991 992 struct RTV_RSP { /* Structure is in Big Endian format */ 993 uint32_t ratov; 994 uint32_t edtov; 995 uint32_t qtov; 996 #define qtov_rsvd0_SHIFT 28 997 #define qtov_rsvd0_MASK 0x0000000f 998 #define qtov_rsvd0_WORD qtov /* reserved */ 999 #define qtov_edtovres_SHIFT 27 1000 #define qtov_edtovres_MASK 0x00000001 1001 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 1002 #define qtov__rsvd1_SHIFT 19 1003 #define qtov_rsvd1_MASK 0x0000003f 1004 #define qtov_rsvd1_WORD qtov /* reserved */ 1005 #define qtov_rttov_SHIFT 18 1006 #define qtov_rttov_MASK 0x00000001 1007 #define qtov_rttov_WORD qtov /* R_T_TOV value */ 1008 #define qtov_rsvd2_SHIFT 0 1009 #define qtov_rsvd2_MASK 0x0003ffff 1010 #define qtov_rsvd2_WORD qtov /* reserved */ 1011 }; 1012 1013 1014 typedef struct _RPL { /* Structure is in Big Endian format */ 1015 uint32_t maxsize; 1016 uint32_t index; 1017 } RPL; 1018 1019 typedef struct _PORT_NUM_BLK { 1020 uint32_t portNum; 1021 uint32_t portID; 1022 struct lpfc_name portName; 1023 } PORT_NUM_BLK; 1024 1025 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 1026 uint32_t listLen; 1027 uint32_t index; 1028 PORT_NUM_BLK port_num_blk; 1029 } RPL_RSP; 1030 1031 /* This is used for RSCN command */ 1032 typedef struct _D_ID { /* Structure is in Big Endian format */ 1033 union { 1034 uint32_t word; 1035 struct { 1036 #ifdef __BIG_ENDIAN_BITFIELD 1037 uint8_t resv; 1038 uint8_t domain; 1039 uint8_t area; 1040 uint8_t id; 1041 #else /* __LITTLE_ENDIAN_BITFIELD */ 1042 uint8_t id; 1043 uint8_t area; 1044 uint8_t domain; 1045 uint8_t resv; 1046 #endif 1047 } b; 1048 } un; 1049 } D_ID; 1050 1051 #define RSCN_ADDRESS_FORMAT_PORT 0x0 1052 #define RSCN_ADDRESS_FORMAT_AREA 0x1 1053 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 1054 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 1055 #define RSCN_ADDRESS_FORMAT_MASK 0x3 1056 1057 /* 1058 * Structure to define all ELS Payload types 1059 */ 1060 1061 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 1062 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1063 uint8_t elsByte1; 1064 uint8_t elsByte2; 1065 uint8_t elsByte3; 1066 union { 1067 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 1068 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 1069 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 1070 PRLI prli; /* Payload for PRLI/ACC */ 1071 PRLO prlo; /* Payload for PRLO/ACC */ 1072 ADISC adisc; /* Payload for ADISC/ACC */ 1073 FARP farp; /* Payload for FARP/ACC */ 1074 FAN fan; /* Payload for FAN */ 1075 SCR scr; /* Payload for SCR/ACC */ 1076 RNID rnid; /* Payload for RNID */ 1077 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1078 } un; 1079 } ELS_PKT; 1080 1081 /* 1082 * Link Cable Beacon (LCB) ELS Frame 1083 */ 1084 1085 struct fc_lcb_request_frame { 1086 uint32_t lcb_command; /* ELS command opcode (0x81) */ 1087 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1088 #define LPFC_LCB_ON 0x1 1089 #define LPFC_LCB_OFF 0x2 1090 uint8_t reserved[2]; 1091 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ 1092 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1093 #define LPFC_LCB_GREEN 0x1 1094 #define LPFC_LCB_AMBER 0x2 1095 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1096 #define LCB_CAPABILITY_DURATION 1 1097 #define BEACON_VERSION_V1 1 1098 #define BEACON_VERSION_V0 0 1099 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1100 }; 1101 1102 /* 1103 * Link Cable Beacon (LCB) ELS Response Frame 1104 */ 1105 struct fc_lcb_res_frame { 1106 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */ 1107 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1108 uint8_t reserved[2]; 1109 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ 1110 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1111 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1112 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1113 }; 1114 1115 /* 1116 * Read Diagnostic Parameters (RDP) ELS frame. 1117 */ 1118 #define SFF_PG0_IDENT_SFP 0x3 1119 1120 #define SFP_FLAG_PT_OPTICAL 0x0 1121 #define SFP_FLAG_PT_SWLASER 0x01 1122 #define SFP_FLAG_PT_LWLASER_LC1310 0x02 1123 #define SFP_FLAG_PT_LWLASER_LL1550 0x03 1124 #define SFP_FLAG_PT_MASK 0x0F 1125 #define SFP_FLAG_PT_SHIFT 0 1126 1127 #define SFP_FLAG_IS_OPTICAL_PORT 0x01 1128 #define SFP_FLAG_IS_OPTICAL_MASK 0x010 1129 #define SFP_FLAG_IS_OPTICAL_SHIFT 4 1130 1131 #define SFP_FLAG_IS_DESC_VALID 0x01 1132 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020 1133 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5 1134 1135 #define SFP_FLAG_CT_UNKNOWN 0x0 1136 #define SFP_FLAG_CT_SFP_PLUS 0x01 1137 #define SFP_FLAG_CT_MASK 0x3C 1138 #define SFP_FLAG_CT_SHIFT 6 1139 1140 struct fc_rdp_port_name_info { 1141 uint8_t wwnn[8]; 1142 uint8_t wwpn[8]; 1143 }; 1144 1145 1146 /* 1147 * Link Error Status Block Structure (FC-FS-3) for RDP 1148 * This similar to RPS ELS 1149 */ 1150 struct fc_link_status { 1151 uint32_t link_failure_cnt; 1152 uint32_t loss_of_synch_cnt; 1153 uint32_t loss_of_signal_cnt; 1154 uint32_t primitive_seq_proto_err; 1155 uint32_t invalid_trans_word; 1156 uint32_t invalid_crc_cnt; 1157 1158 }; 1159 1160 #define RDP_PORT_NAMES_DESC_TAG 0x00010003 1161 struct fc_rdp_port_name_desc { 1162 uint32_t tag; /* 0001 0003h */ 1163 uint32_t length; /* set to size of payload struct */ 1164 struct fc_rdp_port_name_info port_names; 1165 }; 1166 1167 1168 struct fc_rdp_fec_info { 1169 uint32_t CorrectedBlocks; 1170 uint32_t UncorrectableBlocks; 1171 }; 1172 1173 #define RDP_FEC_DESC_TAG 0x00010005 1174 struct fc_fec_rdp_desc { 1175 uint32_t tag; 1176 uint32_t length; 1177 struct fc_rdp_fec_info info; 1178 }; 1179 1180 struct fc_rdp_link_error_status_payload_info { 1181 struct fc_link_status link_status; /* 24 bytes */ 1182 uint32_t port_type; /* bits 31-30 only */ 1183 }; 1184 1185 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002 1186 struct fc_rdp_link_error_status_desc { 1187 uint32_t tag; /* 0001 0002h */ 1188 uint32_t length; /* set to size of payload struct */ 1189 struct fc_rdp_link_error_status_payload_info info; 1190 }; 1191 1192 #define VN_PT_PHY_UNKNOWN 0x00 1193 #define VN_PT_PHY_PF_PORT 0x01 1194 #define VN_PT_PHY_ETH_MAC 0x10 1195 #define VN_PT_PHY_SHIFT 30 1196 1197 #define RDP_PS_1GB 0x8000 1198 #define RDP_PS_2GB 0x4000 1199 #define RDP_PS_4GB 0x2000 1200 #define RDP_PS_10GB 0x1000 1201 #define RDP_PS_8GB 0x0800 1202 #define RDP_PS_16GB 0x0400 1203 #define RDP_PS_32GB 0x0200 1204 #define RDP_PS_64GB 0x0100 1205 #define RDP_PS_128GB 0x0080 1206 #define RDP_PS_256GB 0x0040 1207 1208 #define RDP_CAP_USER_CONFIGURED 0x0002 1209 #define RDP_CAP_UNKNOWN 0x0001 1210 #define RDP_PS_UNKNOWN 0x0002 1211 #define RDP_PS_NOT_ESTABLISHED 0x0001 1212 1213 struct fc_rdp_port_speed { 1214 uint16_t capabilities; 1215 uint16_t speed; 1216 }; 1217 1218 struct fc_rdp_port_speed_info { 1219 struct fc_rdp_port_speed port_speed; 1220 }; 1221 1222 #define RDP_PORT_SPEED_DESC_TAG 0x00010001 1223 struct fc_rdp_port_speed_desc { 1224 uint32_t tag; /* 00010001h */ 1225 uint32_t length; /* set to size of payload struct */ 1226 struct fc_rdp_port_speed_info info; 1227 }; 1228 1229 #define RDP_NPORT_ID_SIZE 4 1230 #define RDP_N_PORT_DESC_TAG 0x00000003 1231 struct fc_rdp_nport_desc { 1232 uint32_t tag; /* 0000 0003h, big endian */ 1233 uint32_t length; /* size of RDP_N_PORT_ID struct */ 1234 uint32_t nport_id : 12; 1235 uint32_t reserved : 8; 1236 }; 1237 1238 1239 struct fc_rdp_link_service_info { 1240 uint32_t els_req; /* Request payload word 0 value.*/ 1241 }; 1242 1243 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001 1244 struct fc_rdp_link_service_desc { 1245 uint32_t tag; /* Descriptor tag 1 */ 1246 uint32_t length; /* set to size of payload struct. */ 1247 struct fc_rdp_link_service_info payload; 1248 /* must be ELS req Word 0(0x18) */ 1249 }; 1250 1251 struct fc_rdp_sfp_info { 1252 uint16_t temperature; 1253 uint16_t vcc; 1254 uint16_t tx_bias; 1255 uint16_t tx_power; 1256 uint16_t rx_power; 1257 uint16_t flags; 1258 }; 1259 1260 #define RDP_SFP_DESC_TAG 0x00010000 1261 struct fc_rdp_sfp_desc { 1262 uint32_t tag; 1263 uint32_t length; /* set to size of sfp_info struct */ 1264 struct fc_rdp_sfp_info sfp_info; 1265 }; 1266 1267 /* Buffer Credit Descriptor */ 1268 struct fc_rdp_bbc_info { 1269 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */ 1270 uint32_t attached_port_bbc; 1271 uint32_t rtt; /* Round trip time */ 1272 }; 1273 #define RDP_BBC_DESC_TAG 0x00010006 1274 struct fc_rdp_bbc_desc { 1275 uint32_t tag; 1276 uint32_t length; 1277 struct fc_rdp_bbc_info bbc_info; 1278 }; 1279 1280 /* Optical Element Type Transgression Flags */ 1281 #define RDP_OET_LOW_WARNING 0x1 1282 #define RDP_OET_HIGH_WARNING 0x2 1283 #define RDP_OET_LOW_ALARM 0x4 1284 #define RDP_OET_HIGH_ALARM 0x8 1285 1286 #define RDP_OED_TEMPERATURE 0x1 1287 #define RDP_OED_VOLTAGE 0x2 1288 #define RDP_OED_TXBIAS 0x3 1289 #define RDP_OED_TXPOWER 0x4 1290 #define RDP_OED_RXPOWER 0x5 1291 1292 #define RDP_OED_TYPE_SHIFT 28 1293 /* Optical Element Data descriptor */ 1294 struct fc_rdp_oed_info { 1295 uint16_t hi_alarm; 1296 uint16_t lo_alarm; 1297 uint16_t hi_warning; 1298 uint16_t lo_warning; 1299 uint32_t function_flags; 1300 }; 1301 #define RDP_OED_DESC_TAG 0x00010007 1302 struct fc_rdp_oed_sfp_desc { 1303 uint32_t tag; 1304 uint32_t length; 1305 struct fc_rdp_oed_info oed_info; 1306 }; 1307 1308 /* Optical Product Data descriptor */ 1309 struct fc_rdp_opd_sfp_info { 1310 uint8_t vendor_name[16]; 1311 uint8_t model_number[16]; 1312 uint8_t serial_number[16]; 1313 uint8_t revision[4]; 1314 uint8_t date[8]; 1315 }; 1316 1317 #define RDP_OPD_DESC_TAG 0x00010008 1318 struct fc_rdp_opd_sfp_desc { 1319 uint32_t tag; 1320 uint32_t length; 1321 struct fc_rdp_opd_sfp_info opd_info; 1322 }; 1323 1324 struct fc_rdp_req_frame { 1325 uint32_t rdp_command; /* ELS command opcode (0x18)*/ 1326 uint32_t rdp_des_length; /* RDP Payload Word 1 */ 1327 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */ 1328 }; 1329 1330 1331 struct fc_rdp_res_frame { 1332 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */ 1333 uint32_t length; /* FC Word 1 */ 1334 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */ 1335 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */ 1336 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */ 1337 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */ 1338 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */ 1339 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */ 1340 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/ 1341 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/ 1342 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/ 1343 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/ 1344 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/ 1345 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/ 1346 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/ 1347 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/ 1348 }; 1349 1350 1351 /* UVEM */ 1352 1353 #define LPFC_UVEM_SIZE 60 1354 #define LPFC_UVEM_VEM_ID_DESC_SIZE 16 1355 #define LPFC_UVEM_VE_MAP_DESC_SIZE 20 1356 1357 #define VEM_ID_DESC_TAG 0x0001000A 1358 struct lpfc_vem_id_desc { 1359 uint32_t tag; 1360 uint32_t length; 1361 uint8_t vem_id[16]; 1362 }; 1363 1364 #define LPFC_QFPA_SIZE 4 1365 1366 #define INSTANTIATED_VE_DESC_TAG 0x0001000B 1367 struct instantiated_ve_desc { 1368 uint32_t tag; 1369 uint32_t length; 1370 uint8_t global_vem_id[16]; 1371 uint32_t word6; 1372 #define lpfc_instantiated_local_id_SHIFT 0 1373 #define lpfc_instantiated_local_id_MASK 0x000000ff 1374 #define lpfc_instantiated_local_id_WORD word6 1375 #define lpfc_instantiated_nport_id_SHIFT 8 1376 #define lpfc_instantiated_nport_id_MASK 0x00ffffff 1377 #define lpfc_instantiated_nport_id_WORD word6 1378 }; 1379 1380 #define DEINSTANTIATED_VE_DESC_TAG 0x0001000C 1381 struct deinstantiated_ve_desc { 1382 uint32_t tag; 1383 uint32_t length; 1384 uint8_t global_vem_id[16]; 1385 uint32_t word6; 1386 #define lpfc_deinstantiated_nport_id_SHIFT 0 1387 #define lpfc_deinstantiated_nport_id_MASK 0x000000ff 1388 #define lpfc_deinstantiated_nport_id_WORD word6 1389 #define lpfc_deinstantiated_local_id_SHIFT 24 1390 #define lpfc_deinstantiated_local_id_MASK 0x00ffffff 1391 #define lpfc_deinstantiated_local_id_WORD word6 1392 }; 1393 1394 /* Query Fabric Priority Allocation Response */ 1395 #define LPFC_PRIORITY_RANGE_DESC_SIZE 12 1396 1397 struct priority_range_desc { 1398 uint32_t tag; 1399 uint32_t length; 1400 uint8_t lo_range; 1401 uint8_t hi_range; 1402 uint8_t qos_priority; 1403 uint8_t local_ve_id; 1404 }; 1405 1406 struct fc_qfpa_res { 1407 uint32_t reply_sequence; /* LS_ACC or LS_RJT */ 1408 uint32_t length; /* FC Word 1 */ 1409 struct priority_range_desc desc[1]; 1410 }; 1411 1412 /* Application Server command code */ 1413 /* VMID */ 1414 1415 #define SLI_CT_APP_SEV_Subtypes 0x20 /* Application Server subtype */ 1416 1417 #define SLI_CTAS_GAPPIA_ENT 0x0100 /* Get Application Identifier */ 1418 #define SLI_CTAS_GALLAPPIA 0x0101 /* Get All Application Identifier */ 1419 #define SLI_CTAS_GALLAPPIA_ID 0x0102 /* Get All Application Identifier */ 1420 /* for Nport */ 1421 #define SLI_CTAS_GAPPIA_IDAPP 0x0103 /* Get Application Identifier */ 1422 /* for Nport */ 1423 #define SLI_CTAS_RAPP_IDENT 0x0200 /* Register Application Identifier */ 1424 #define SLI_CTAS_DAPP_IDENT 0x0300 /* Deregister Application */ 1425 /* Identifier */ 1426 #define SLI_CTAS_DALLAPP_ID 0x0301 /* Deregister All Application */ 1427 /* Identifier */ 1428 1429 struct entity_id_object { 1430 uint8_t entity_id_len; 1431 uint8_t entity_id[255]; /* VM UUID */ 1432 }; 1433 1434 struct app_id_object { 1435 __be32 port_id; 1436 __be32 app_id; 1437 struct entity_id_object obj; 1438 }; 1439 1440 struct lpfc_vmid_rapp_ident_list { 1441 __be32 no_of_objects; 1442 struct entity_id_object obj[]; 1443 }; 1444 1445 struct lpfc_vmid_dapp_ident_list { 1446 __be32 no_of_objects; 1447 struct entity_id_object obj[]; 1448 }; 1449 1450 #define GALLAPPIA_ID_LAST 0x80 1451 struct lpfc_vmid_gallapp_ident_list { 1452 uint8_t control; 1453 uint8_t reserved[3]; 1454 struct app_id_object app_id; 1455 }; 1456 1457 #define RAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) 1458 #define DAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) 1459 #define GALLAPPIA_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) 1460 #define DALLAPP_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) 1461 1462 /******** FDMI ********/ 1463 1464 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */ 1465 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */ 1466 1467 /* Definitions for HBA / Port attribute entries */ 1468 1469 /* Attribute Entry Structures */ 1470 1471 struct lpfc_fdmi_attr_u32 { 1472 __be16 type; 1473 __be16 len; 1474 __be32 value_u32; 1475 }; 1476 1477 struct lpfc_fdmi_attr_wwn { 1478 __be16 type; 1479 __be16 len; 1480 1481 /* Keep as u8[8] instead of __be64 to avoid accidental zero padding 1482 * by compiler 1483 */ 1484 u8 name[8]; 1485 }; 1486 1487 struct lpfc_fdmi_attr_fullwwn { 1488 __be16 type; 1489 __be16 len; 1490 1491 /* Keep as u8[8] instead of __be64 to avoid accidental zero padding 1492 * by compiler 1493 */ 1494 u8 nname[8]; 1495 u8 pname[8]; 1496 }; 1497 1498 struct lpfc_fdmi_attr_fc4types { 1499 __be16 type; 1500 __be16 len; 1501 u8 value_types[32]; 1502 }; 1503 1504 struct lpfc_fdmi_attr_string { 1505 __be16 type; 1506 __be16 len; 1507 char value_string[256]; 1508 }; 1509 1510 /* Maximum FDMI attribute length is Type+Len (4 bytes) + 256 byte string */ 1511 #define FDMI_MAX_ATTRLEN sizeof(struct lpfc_fdmi_attr_string) 1512 1513 /* 1514 * HBA Attribute Block 1515 */ 1516 struct lpfc_fdmi_attr_block { 1517 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1518 /* Variable Length Attribute Entry TLV's follow */ 1519 }; 1520 1521 /* 1522 * Port Entry 1523 */ 1524 struct lpfc_fdmi_port_entry { 1525 struct lpfc_name PortName; 1526 }; 1527 1528 /* 1529 * HBA Identifier 1530 */ 1531 struct lpfc_fdmi_hba_ident { 1532 struct lpfc_name PortName; 1533 }; 1534 1535 /* 1536 * Registered Port List Format 1537 */ 1538 struct lpfc_fdmi_reg_port_list { 1539 __be32 EntryCnt; 1540 struct lpfc_fdmi_port_entry pe; 1541 }; 1542 1543 /* 1544 * Register HBA(RHBA) 1545 */ 1546 struct lpfc_fdmi_reg_hba { 1547 struct lpfc_fdmi_hba_ident hi; 1548 struct lpfc_fdmi_reg_port_list rpl; 1549 }; 1550 1551 /******** MI MIB ********/ 1552 #define SLI_CT_MIB_Subtypes 0x11 1553 1554 /* 1555 * Register HBA Attributes (RHAT) 1556 */ 1557 struct lpfc_fdmi_reg_hbaattr { 1558 struct lpfc_name HBA_PortName; 1559 struct lpfc_fdmi_attr_block ab; 1560 }; 1561 1562 /* 1563 * Register Port Attributes (RPA) 1564 */ 1565 struct lpfc_fdmi_reg_portattr { 1566 struct lpfc_name PortName; 1567 struct lpfc_fdmi_attr_block ab; 1568 }; 1569 1570 /* 1571 * HBA MAnagement Operations Command Codes 1572 */ 1573 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1574 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1575 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1576 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1577 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */ 1578 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1579 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1580 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1581 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1582 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1583 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */ 1584 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1585 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */ 1586 1587 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */ 1588 1589 /* 1590 * HBA Attribute Types 1591 */ 1592 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */ 1593 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */ 1594 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */ 1595 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */ 1596 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */ 1597 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */ 1598 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */ 1599 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */ 1600 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */ 1601 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */ 1602 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */ 1603 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */ 1604 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */ 1605 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */ 1606 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */ 1607 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */ 1608 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */ 1609 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */ 1610 1611 /* Bit mask for all individual HBA attributes */ 1612 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001 1613 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002 1614 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004 1615 #define LPFC_FDMI_HBA_ATTR_model 0x00000008 1616 #define LPFC_FDMI_HBA_ATTR_description 0x00000010 1617 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020 1618 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040 1619 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080 1620 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100 1621 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200 1622 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400 1623 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800 1624 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */ 1625 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000 1626 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000 1627 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000 1628 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */ 1629 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000 1630 1631 /* Bit mask for FDMI-1 defined HBA attributes */ 1632 #define LPFC_FDMI1_HBA_ATTR 0x000007ff 1633 1634 /* Bit mask for FDMI-2 defined HBA attributes */ 1635 /* Skip vendor_info and bios_state */ 1636 #define LPFC_FDMI2_HBA_ATTR 0x0002efff 1637 1638 /* 1639 * Port Attribute Types 1640 */ 1641 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */ 1642 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */ 1643 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */ 1644 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */ 1645 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */ 1646 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */ 1647 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */ 1648 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */ 1649 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */ 1650 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */ 1651 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */ 1652 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */ 1653 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */ 1654 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */ 1655 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */ 1656 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */ 1657 #define RPRT_VENDOR_MI 0xf047 /* vendor ascii string */ 1658 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */ 1659 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */ 1660 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */ 1661 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */ 1662 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */ 1663 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */ 1664 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */ 1665 1666 /* Bit mask for all individual PORT attributes */ 1667 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001 1668 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002 1669 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004 1670 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008 1671 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010 1672 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020 1673 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040 1674 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080 1675 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100 1676 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200 1677 #define LPFC_FDMI_PORT_ATTR_class 0x00000400 1678 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800 1679 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000 1680 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000 1681 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000 1682 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000 1683 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */ 1684 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */ 1685 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */ 1686 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */ 1687 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */ 1688 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */ 1689 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */ 1690 #define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000 /* Vendor specific */ 1691 1692 /* Bit mask for FDMI-1 defined PORT attributes */ 1693 #define LPFC_FDMI1_PORT_ATTR 0x0000003f 1694 1695 /* Bit mask for FDMI-2 defined PORT attributes */ 1696 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff 1697 1698 /* Bit mask for Smart SAN defined PORT attributes */ 1699 #define LPFC_FDMI2_SMART_ATTR 0x007fffff 1700 1701 /* Defines for PORT port state attribute */ 1702 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1 1703 #define LPFC_FDMI_PORTSTATE_ONLINE 2 1704 1705 /* Defines for PORT port type attribute */ 1706 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0 1707 #define LPFC_FDMI_PORTTYPE_NPORT 1 1708 #define LPFC_FDMI_PORTTYPE_NLPORT 2 1709 1710 /* 1711 * Begin HBA configuration parameters. 1712 * The PCI configuration register BAR assignments are: 1713 * BAR0, offset 0x10 - SLIM base memory address 1714 * BAR1, offset 0x14 - SLIM base memory high address 1715 * BAR2, offset 0x18 - REGISTER base memory address 1716 * BAR3, offset 0x1c - REGISTER base memory high address 1717 * BAR4, offset 0x20 - BIU I/O registers 1718 * BAR5, offset 0x24 - REGISTER base io high address 1719 */ 1720 1721 /* Number of rings currently used and available. */ 1722 #define MAX_SLI3_CONFIGURED_RINGS 3 1723 #define MAX_SLI3_RINGS 4 1724 1725 /* IOCB / Mailbox is owned by FireFly */ 1726 #define OWN_CHIP 1 1727 1728 /* IOCB / Mailbox is owned by Host */ 1729 #define OWN_HOST 0 1730 1731 /* Number of 4-byte words in an IOCB. */ 1732 #define IOCB_WORD_SZ 8 1733 1734 /* network headers for Dfctl field */ 1735 #define FC_NET_HDR 0x20 1736 1737 /* Start FireFly Register definitions */ 1738 #define PCI_VENDOR_ID_EMULEX 0x10df 1739 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1740 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1741 #define PCI_DEVICE_ID_BALIUS 0xe131 1742 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1743 #define PCI_DEVICE_ID_LANCER_FC 0xe200 1744 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1745 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1746 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1747 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300 1748 #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400 1749 #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500 1750 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1751 #define PCI_DEVICE_ID_SAT_MID 0xf015 1752 #define PCI_DEVICE_ID_RFLY 0xf095 1753 #define PCI_DEVICE_ID_PFLY 0xf098 1754 #define PCI_DEVICE_ID_LP101 0xf0a1 1755 #define PCI_DEVICE_ID_TFLY 0xf0a5 1756 #define PCI_DEVICE_ID_BSMB 0xf0d1 1757 #define PCI_DEVICE_ID_BMID 0xf0d5 1758 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1759 #define PCI_DEVICE_ID_ZMID 0xf0e5 1760 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1761 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1762 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1763 #define PCI_DEVICE_ID_SAT 0xf100 1764 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1765 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1766 #define PCI_DEVICE_ID_FALCON 0xf180 1767 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1768 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1769 #define PCI_DEVICE_ID_CENTAUR 0xf900 1770 #define PCI_DEVICE_ID_PEGASUS 0xf980 1771 #define PCI_DEVICE_ID_THOR 0xfa00 1772 #define PCI_DEVICE_ID_VIPER 0xfb00 1773 #define PCI_DEVICE_ID_LP10000S 0xfc00 1774 #define PCI_DEVICE_ID_LP11000S 0xfc10 1775 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1776 #define PCI_DEVICE_ID_SAT_S 0xfc40 1777 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1778 #define PCI_DEVICE_ID_HELIOS 0xfd00 1779 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1780 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1781 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1782 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1783 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1784 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1785 #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1786 #define PCI_DEVICE_ID_TOMCAT 0x0714 1787 #define PCI_DEVICE_ID_SKYHAWK 0x0724 1788 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c 1789 #define PCI_VENDOR_ID_ATTO 0x117c 1790 #define PCI_DEVICE_ID_CLRY_16XE 0x0064 1791 #define PCI_DEVICE_ID_CLRY_161E 0x0063 1792 #define PCI_DEVICE_ID_CLRY_162E 0x0064 1793 #define PCI_DEVICE_ID_CLRY_164E 0x0065 1794 #define PCI_DEVICE_ID_CLRY_16XP 0x0094 1795 #define PCI_DEVICE_ID_CLRY_161P 0x00a0 1796 #define PCI_DEVICE_ID_CLRY_162P 0x0094 1797 #define PCI_DEVICE_ID_CLRY_164P 0x00a1 1798 #define PCI_DEVICE_ID_CLRY_32XE 0x0094 1799 #define PCI_DEVICE_ID_CLRY_321E 0x00a2 1800 #define PCI_DEVICE_ID_CLRY_322E 0x00a3 1801 #define PCI_DEVICE_ID_CLRY_324E 0x00ac 1802 #define PCI_DEVICE_ID_CLRY_32XP 0x00bb 1803 #define PCI_DEVICE_ID_CLRY_321P 0x00bc 1804 #define PCI_DEVICE_ID_CLRY_322P 0x00bd 1805 #define PCI_DEVICE_ID_CLRY_324P 0x00be 1806 #define PCI_DEVICE_ID_TLFC_2 0x0064 1807 #define PCI_DEVICE_ID_TLFC_2XX2 0x4064 1808 #define PCI_DEVICE_ID_TLFC_3 0x0094 1809 #define PCI_DEVICE_ID_TLFC_3162 0x40a6 1810 #define PCI_DEVICE_ID_TLFC_3322 0x40a7 1811 1812 #define JEDEC_ID_ADDRESS 0x0080001c 1813 #define FIREFLY_JEDEC_ID 0x1ACC 1814 #define SUPERFLY_JEDEC_ID 0x0020 1815 #define DRAGONFLY_JEDEC_ID 0x0021 1816 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1817 #define CENTAUR_2G_JEDEC_ID 0x0026 1818 #define CENTAUR_1G_JEDEC_ID 0x0028 1819 #define PEGASUS_ORION_JEDEC_ID 0x0036 1820 #define PEGASUS_JEDEC_ID 0x0038 1821 #define THOR_JEDEC_ID 0x0012 1822 #define HELIOS_JEDEC_ID 0x0364 1823 #define ZEPHYR_JEDEC_ID 0x0577 1824 #define VIPER_JEDEC_ID 0x4838 1825 #define SATURN_JEDEC_ID 0x1004 1826 1827 #define JEDEC_ID_MASK 0x0FFFF000 1828 #define JEDEC_ID_SHIFT 12 1829 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1830 1831 typedef struct { /* FireFly BIU registers */ 1832 uint32_t hostAtt; /* See definitions for Host Attention 1833 register */ 1834 uint32_t chipAtt; /* See definitions for Chip Attention 1835 register */ 1836 uint32_t hostStatus; /* See definitions for Host Status register */ 1837 uint32_t hostControl; /* See definitions for Host Control register */ 1838 uint32_t buiConfig; /* See definitions for BIU configuration 1839 register */ 1840 } FF_REGS; 1841 1842 /* IO Register size in bytes */ 1843 #define FF_REG_AREA_SIZE 256 1844 1845 /* Host Attention Register */ 1846 1847 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1848 1849 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1850 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1851 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1852 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1853 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1854 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1855 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1856 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1857 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1858 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1859 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1860 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1861 #define HA_LATT 0x20000000 /* Bit 29 */ 1862 #define HA_MBATT 0x40000000 /* Bit 30 */ 1863 #define HA_ERATT 0x80000000 /* Bit 31 */ 1864 1865 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1866 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1867 #define HA_RXATT 0x00000008 /* Bit 3 */ 1868 #define HA_RXMASK 0x0000000f 1869 1870 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1871 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1872 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1873 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1874 1875 #define HA_R0_POS 3 1876 #define HA_R1_POS 7 1877 #define HA_R2_POS 11 1878 #define HA_R3_POS 15 1879 #define HA_LE_POS 29 1880 #define HA_MB_POS 30 1881 #define HA_ER_POS 31 1882 /* Chip Attention Register */ 1883 1884 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1885 1886 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1887 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1888 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1889 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1890 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1891 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1892 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1893 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1894 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1895 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1896 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1897 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1898 #define CA_MBATT 0x40000000 /* Bit 30 */ 1899 1900 /* Host Status Register */ 1901 1902 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1903 1904 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1905 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1906 #define HS_FFER8 0x01000000 /* Bit 24 */ 1907 #define HS_FFER7 0x02000000 /* Bit 25 */ 1908 #define HS_FFER6 0x04000000 /* Bit 26 */ 1909 #define HS_FFER5 0x08000000 /* Bit 27 */ 1910 #define HS_FFER4 0x10000000 /* Bit 28 */ 1911 #define HS_FFER3 0x20000000 /* Bit 29 */ 1912 #define HS_FFER2 0x40000000 /* Bit 30 */ 1913 #define HS_FFER1 0x80000000 /* Bit 31 */ 1914 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1915 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1916 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1917 /* Host Control Register */ 1918 1919 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1920 1921 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1922 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1923 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1924 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1925 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1926 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1927 #define HC_INITMB 0x04000000 /* Bit 26 */ 1928 #define HC_INITFF 0x08000000 /* Bit 27 */ 1929 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1930 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1931 1932 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1933 #define MSIX_DFLT_ID 0 1934 #define MSIX_RNG0_ID 0 1935 #define MSIX_RNG1_ID 1 1936 #define MSIX_RNG2_ID 2 1937 #define MSIX_RNG3_ID 3 1938 1939 #define MSIX_LINK_ID 4 1940 #define MSIX_MBOX_ID 5 1941 1942 #define MSIX_SPARE0_ID 6 1943 #define MSIX_SPARE1_ID 7 1944 1945 /* Mailbox Commands */ 1946 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1947 #define MBX_LOAD_SM 0x01 1948 #define MBX_READ_NV 0x02 1949 #define MBX_WRITE_NV 0x03 1950 #define MBX_RUN_BIU_DIAG 0x04 1951 #define MBX_INIT_LINK 0x05 1952 #define MBX_DOWN_LINK 0x06 1953 #define MBX_CONFIG_LINK 0x07 1954 #define MBX_CONFIG_RING 0x09 1955 #define MBX_RESET_RING 0x0A 1956 #define MBX_READ_CONFIG 0x0B 1957 #define MBX_READ_RCONFIG 0x0C 1958 #define MBX_READ_SPARM 0x0D 1959 #define MBX_READ_STATUS 0x0E 1960 #define MBX_READ_RPI 0x0F 1961 #define MBX_READ_XRI 0x10 1962 #define MBX_READ_REV 0x11 1963 #define MBX_READ_LNK_STAT 0x12 1964 #define MBX_REG_LOGIN 0x13 1965 #define MBX_UNREG_LOGIN 0x14 1966 #define MBX_CLEAR_LA 0x16 1967 #define MBX_DUMP_MEMORY 0x17 1968 #define MBX_DUMP_CONTEXT 0x18 1969 #define MBX_RUN_DIAGS 0x19 1970 #define MBX_RESTART 0x1A 1971 #define MBX_UPDATE_CFG 0x1B 1972 #define MBX_DOWN_LOAD 0x1C 1973 #define MBX_DEL_LD_ENTRY 0x1D 1974 #define MBX_RUN_PROGRAM 0x1E 1975 #define MBX_SET_MASK 0x20 1976 #define MBX_SET_VARIABLE 0x21 1977 #define MBX_UNREG_D_ID 0x23 1978 #define MBX_KILL_BOARD 0x24 1979 #define MBX_CONFIG_FARP 0x25 1980 #define MBX_BEACON 0x2A 1981 #define MBX_CONFIG_MSI 0x30 1982 #define MBX_HEARTBEAT 0x31 1983 #define MBX_WRITE_VPARMS 0x32 1984 #define MBX_ASYNCEVT_ENABLE 0x33 1985 #define MBX_READ_EVENT_LOG_STATUS 0x37 1986 #define MBX_READ_EVENT_LOG 0x38 1987 #define MBX_WRITE_EVENT_LOG 0x39 1988 1989 #define MBX_PORT_CAPABILITIES 0x3B 1990 #define MBX_PORT_IOV_CONTROL 0x3C 1991 1992 #define MBX_CONFIG_HBQ 0x7C 1993 #define MBX_LOAD_AREA 0x81 1994 #define MBX_RUN_BIU_DIAG64 0x84 1995 #define MBX_CONFIG_PORT 0x88 1996 #define MBX_READ_SPARM64 0x8D 1997 #define MBX_READ_RPI64 0x8F 1998 #define MBX_REG_LOGIN64 0x93 1999 #define MBX_READ_TOPOLOGY 0x95 2000 #define MBX_REG_VPI 0x96 2001 #define MBX_UNREG_VPI 0x97 2002 2003 #define MBX_WRITE_WWN 0x98 2004 #define MBX_SET_DEBUG 0x99 2005 #define MBX_LOAD_EXP_ROM 0x9C 2006 #define MBX_SLI4_CONFIG 0x9B 2007 #define MBX_SLI4_REQ_FTRS 0x9D 2008 #define MBX_MAX_CMDS 0x9E 2009 #define MBX_RESUME_RPI 0x9E 2010 #define MBX_SLI2_CMD_MASK 0x80 2011 #define MBX_REG_VFI 0x9F 2012 #define MBX_REG_FCFI 0xA0 2013 #define MBX_UNREG_VFI 0xA1 2014 #define MBX_UNREG_FCFI 0xA2 2015 #define MBX_INIT_VFI 0xA3 2016 #define MBX_INIT_VPI 0xA4 2017 #define MBX_ACCESS_VDATA 0xA5 2018 #define MBX_REG_FCFI_MRQ 0xAF 2019 2020 #define MBX_AUTH_PORT 0xF8 2021 #define MBX_SECURITY_MGMT 0xF9 2022 2023 /* IOCB Commands */ 2024 2025 #define CMD_RCV_SEQUENCE_CX 0x01 2026 #define CMD_XMIT_SEQUENCE_CR 0x02 2027 #define CMD_XMIT_SEQUENCE_CX 0x03 2028 #define CMD_XMIT_BCAST_CN 0x04 2029 #define CMD_XMIT_BCAST_CX 0x05 2030 #define CMD_QUE_RING_BUF_CN 0x06 2031 #define CMD_QUE_XRI_BUF_CX 0x07 2032 #define CMD_IOCB_CONTINUE_CN 0x08 2033 #define CMD_RET_XRI_BUF_CX 0x09 2034 #define CMD_ELS_REQUEST_CR 0x0A 2035 #define CMD_ELS_REQUEST_CX 0x0B 2036 #define CMD_RCV_ELS_REQ_CX 0x0D 2037 #define CMD_ABORT_XRI_CN 0x0E 2038 #define CMD_ABORT_XRI_CX 0x0F 2039 #define CMD_CLOSE_XRI_CN 0x10 2040 #define CMD_CLOSE_XRI_CX 0x11 2041 #define CMD_CREATE_XRI_CR 0x12 2042 #define CMD_CREATE_XRI_CX 0x13 2043 #define CMD_GET_RPI_CN 0x14 2044 #define CMD_XMIT_ELS_RSP_CX 0x15 2045 #define CMD_GET_RPI_CR 0x16 2046 #define CMD_XRI_ABORTED_CX 0x17 2047 #define CMD_FCP_IWRITE_CR 0x18 2048 #define CMD_FCP_IWRITE_CX 0x19 2049 #define CMD_FCP_IREAD_CR 0x1A 2050 #define CMD_FCP_IREAD_CX 0x1B 2051 #define CMD_FCP_ICMND_CR 0x1C 2052 #define CMD_FCP_ICMND_CX 0x1D 2053 #define CMD_FCP_TSEND_CX 0x1F 2054 #define CMD_FCP_TRECEIVE_CX 0x21 2055 #define CMD_FCP_TRSP_CX 0x23 2056 #define CMD_FCP_AUTO_TRSP_CX 0x29 2057 2058 #define CMD_ADAPTER_MSG 0x20 2059 #define CMD_ADAPTER_DUMP 0x22 2060 2061 /* SLI_2 IOCB Command Set */ 2062 2063 #define CMD_ASYNC_STATUS 0x7C 2064 #define CMD_RCV_SEQUENCE64_CX 0x81 2065 #define CMD_XMIT_SEQUENCE64_CR 0x82 2066 #define CMD_XMIT_SEQUENCE64_CX 0x83 2067 #define CMD_XMIT_BCAST64_CN 0x84 2068 #define CMD_XMIT_BCAST64_CX 0x85 2069 #define CMD_QUE_RING_BUF64_CN 0x86 2070 #define CMD_QUE_XRI_BUF64_CX 0x87 2071 #define CMD_IOCB_CONTINUE64_CN 0x88 2072 #define CMD_RET_XRI_BUF64_CX 0x89 2073 #define CMD_ELS_REQUEST64_CR 0x8A 2074 #define CMD_ELS_REQUEST64_CX 0x8B 2075 #define CMD_ABORT_MXRI64_CN 0x8C 2076 #define CMD_RCV_ELS_REQ64_CX 0x8D 2077 #define CMD_XMIT_ELS_RSP64_CX 0x95 2078 #define CMD_XMIT_BLS_RSP64_CX 0x97 2079 #define CMD_FCP_IWRITE64_CR 0x98 2080 #define CMD_FCP_IWRITE64_CX 0x99 2081 #define CMD_FCP_IREAD64_CR 0x9A 2082 #define CMD_FCP_IREAD64_CX 0x9B 2083 #define CMD_FCP_ICMND64_CR 0x9C 2084 #define CMD_FCP_ICMND64_CX 0x9D 2085 #define CMD_FCP_TSEND64_CX 0x9F 2086 #define CMD_FCP_TRECEIVE64_CX 0xA1 2087 #define CMD_FCP_TRSP64_CX 0xA3 2088 2089 #define CMD_QUE_XRI64_CX 0xB3 2090 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 2091 #define CMD_IOCB_RCV_ELS64_CX 0xB7 2092 #define CMD_IOCB_RET_XRI64_CX 0xB9 2093 #define CMD_IOCB_RCV_CONT64_CX 0xBB 2094 2095 #define CMD_GEN_REQUEST64_CR 0xC2 2096 #define CMD_GEN_REQUEST64_CX 0xC3 2097 2098 /* Unhandled SLI-3 Commands */ 2099 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 2100 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 2101 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 2102 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 2103 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 2104 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 2105 #define CMD_IOCB_RET_HBQE64_CN 0xCA 2106 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 2107 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 2108 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 2109 #define CMD_IOCB_LOGENTRY_CN 0x94 2110 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 2111 2112 /* Data Security SLI Commands */ 2113 #define DSSCMD_IWRITE64_CR 0xF8 2114 #define DSSCMD_IWRITE64_CX 0xF9 2115 #define DSSCMD_IREAD64_CR 0xFA 2116 #define DSSCMD_IREAD64_CX 0xFB 2117 2118 #define CMD_MAX_IOCB_CMD 0xFB 2119 #define CMD_IOCB_MASK 0xff 2120 2121 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 2122 iocb */ 2123 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 2124 /* 2125 * Define Status 2126 */ 2127 #define MBX_SUCCESS 0 2128 #define MBXERR_NUM_RINGS 1 2129 #define MBXERR_NUM_IOCBS 2 2130 #define MBXERR_IOCBS_EXCEEDED 3 2131 #define MBXERR_BAD_RING_NUMBER 4 2132 #define MBXERR_MASK_ENTRIES_RANGE 5 2133 #define MBXERR_MASKS_EXCEEDED 6 2134 #define MBXERR_BAD_PROFILE 7 2135 #define MBXERR_BAD_DEF_CLASS 8 2136 #define MBXERR_BAD_MAX_RESPONDER 9 2137 #define MBXERR_BAD_MAX_ORIGINATOR 10 2138 #define MBXERR_RPI_REGISTERED 11 2139 #define MBXERR_RPI_FULL 12 2140 #define MBXERR_NO_RESOURCES 13 2141 #define MBXERR_BAD_RCV_LENGTH 14 2142 #define MBXERR_DMA_ERROR 15 2143 #define MBXERR_ERROR 16 2144 #define MBXERR_LINK_DOWN 0x33 2145 #define MBXERR_SEC_NO_PERMISSION 0xF02 2146 #define MBX_NOT_FINISHED 255 2147 2148 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 2149 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 2150 2151 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 2152 2153 /* 2154 * return code Fail 2155 */ 2156 #define FAILURE 1 2157 2158 /* 2159 * Begin Structure Definitions for Mailbox Commands 2160 */ 2161 2162 typedef struct { 2163 #ifdef __BIG_ENDIAN_BITFIELD 2164 uint8_t tval; 2165 uint8_t tmask; 2166 uint8_t rval; 2167 uint8_t rmask; 2168 #else /* __LITTLE_ENDIAN_BITFIELD */ 2169 uint8_t rmask; 2170 uint8_t rval; 2171 uint8_t tmask; 2172 uint8_t tval; 2173 #endif 2174 } RR_REG; 2175 2176 struct ulp_bde { 2177 uint32_t bdeAddress; 2178 #ifdef __BIG_ENDIAN_BITFIELD 2179 uint32_t bdeReserved:4; 2180 uint32_t bdeAddrHigh:4; 2181 uint32_t bdeSize:24; 2182 #else /* __LITTLE_ENDIAN_BITFIELD */ 2183 uint32_t bdeSize:24; 2184 uint32_t bdeAddrHigh:4; 2185 uint32_t bdeReserved:4; 2186 #endif 2187 }; 2188 2189 typedef struct ULP_BDL { /* SLI-2 */ 2190 #ifdef __BIG_ENDIAN_BITFIELD 2191 uint32_t bdeFlags:8; /* BDL Flags */ 2192 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 2193 #else /* __LITTLE_ENDIAN_BITFIELD */ 2194 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 2195 uint32_t bdeFlags:8; /* BDL Flags */ 2196 #endif 2197 2198 uint32_t addrLow; /* Address 0:31 */ 2199 uint32_t addrHigh; /* Address 32:63 */ 2200 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 2201 } ULP_BDL; 2202 2203 /* 2204 * BlockGuard Definitions 2205 */ 2206 2207 enum lpfc_protgrp_type { 2208 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 2209 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 2210 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 2211 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 2212 }; 2213 2214 /* PDE Descriptors */ 2215 #define LPFC_PDE5_DESCRIPTOR 0x85 2216 #define LPFC_PDE6_DESCRIPTOR 0x86 2217 #define LPFC_PDE7_DESCRIPTOR 0x87 2218 2219 /* BlockGuard Opcodes */ 2220 #define BG_OP_IN_NODIF_OUT_CRC 0x0 2221 #define BG_OP_IN_CRC_OUT_NODIF 0x1 2222 #define BG_OP_IN_NODIF_OUT_CSUM 0x2 2223 #define BG_OP_IN_CSUM_OUT_NODIF 0x3 2224 #define BG_OP_IN_CRC_OUT_CRC 0x4 2225 #define BG_OP_IN_CSUM_OUT_CSUM 0x5 2226 #define BG_OP_IN_CRC_OUT_CSUM 0x6 2227 #define BG_OP_IN_CSUM_OUT_CRC 0x7 2228 #define BG_OP_RAW_MODE 0x8 2229 2230 struct lpfc_pde5 { 2231 uint32_t word0; 2232 #define pde5_type_SHIFT 24 2233 #define pde5_type_MASK 0x000000ff 2234 #define pde5_type_WORD word0 2235 #define pde5_rsvd0_SHIFT 0 2236 #define pde5_rsvd0_MASK 0x00ffffff 2237 #define pde5_rsvd0_WORD word0 2238 uint32_t reftag; /* Reference Tag Value */ 2239 uint32_t reftagtr; /* Reference Tag Translation Value */ 2240 }; 2241 2242 struct lpfc_pde6 { 2243 uint32_t word0; 2244 #define pde6_type_SHIFT 24 2245 #define pde6_type_MASK 0x000000ff 2246 #define pde6_type_WORD word0 2247 #define pde6_rsvd0_SHIFT 0 2248 #define pde6_rsvd0_MASK 0x00ffffff 2249 #define pde6_rsvd0_WORD word0 2250 uint32_t word1; 2251 #define pde6_rsvd1_SHIFT 26 2252 #define pde6_rsvd1_MASK 0x0000003f 2253 #define pde6_rsvd1_WORD word1 2254 #define pde6_na_SHIFT 25 2255 #define pde6_na_MASK 0x00000001 2256 #define pde6_na_WORD word1 2257 #define pde6_rsvd2_SHIFT 16 2258 #define pde6_rsvd2_MASK 0x000001FF 2259 #define pde6_rsvd2_WORD word1 2260 #define pde6_apptagtr_SHIFT 0 2261 #define pde6_apptagtr_MASK 0x0000ffff 2262 #define pde6_apptagtr_WORD word1 2263 uint32_t word2; 2264 #define pde6_optx_SHIFT 28 2265 #define pde6_optx_MASK 0x0000000f 2266 #define pde6_optx_WORD word2 2267 #define pde6_oprx_SHIFT 24 2268 #define pde6_oprx_MASK 0x0000000f 2269 #define pde6_oprx_WORD word2 2270 #define pde6_nr_SHIFT 23 2271 #define pde6_nr_MASK 0x00000001 2272 #define pde6_nr_WORD word2 2273 #define pde6_ce_SHIFT 22 2274 #define pde6_ce_MASK 0x00000001 2275 #define pde6_ce_WORD word2 2276 #define pde6_re_SHIFT 21 2277 #define pde6_re_MASK 0x00000001 2278 #define pde6_re_WORD word2 2279 #define pde6_ae_SHIFT 20 2280 #define pde6_ae_MASK 0x00000001 2281 #define pde6_ae_WORD word2 2282 #define pde6_ai_SHIFT 19 2283 #define pde6_ai_MASK 0x00000001 2284 #define pde6_ai_WORD word2 2285 #define pde6_bs_SHIFT 16 2286 #define pde6_bs_MASK 0x00000007 2287 #define pde6_bs_WORD word2 2288 #define pde6_apptagval_SHIFT 0 2289 #define pde6_apptagval_MASK 0x0000ffff 2290 #define pde6_apptagval_WORD word2 2291 }; 2292 2293 struct lpfc_pde7 { 2294 uint32_t word0; 2295 #define pde7_type_SHIFT 24 2296 #define pde7_type_MASK 0x000000ff 2297 #define pde7_type_WORD word0 2298 #define pde7_rsvd0_SHIFT 0 2299 #define pde7_rsvd0_MASK 0x00ffffff 2300 #define pde7_rsvd0_WORD word0 2301 uint32_t addrHigh; 2302 uint32_t addrLow; 2303 }; 2304 2305 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 2306 2307 typedef struct { 2308 #ifdef __BIG_ENDIAN_BITFIELD 2309 uint32_t rsvd2:25; 2310 uint32_t acknowledgment:1; 2311 uint32_t version:1; 2312 uint32_t erase_or_prog:1; 2313 uint32_t update_flash:1; 2314 uint32_t update_ram:1; 2315 uint32_t method:1; 2316 uint32_t load_cmplt:1; 2317 #else /* __LITTLE_ENDIAN_BITFIELD */ 2318 uint32_t load_cmplt:1; 2319 uint32_t method:1; 2320 uint32_t update_ram:1; 2321 uint32_t update_flash:1; 2322 uint32_t erase_or_prog:1; 2323 uint32_t version:1; 2324 uint32_t acknowledgment:1; 2325 uint32_t rsvd2:25; 2326 #endif 2327 2328 uint32_t dl_to_adr_low; 2329 uint32_t dl_to_adr_high; 2330 uint32_t dl_len; 2331 union { 2332 uint32_t dl_from_mbx_offset; 2333 struct ulp_bde dl_from_bde; 2334 struct ulp_bde64 dl_from_bde64; 2335 } un; 2336 2337 } LOAD_SM_VAR; 2338 2339 /* Structure for MB Command READ_NVPARM (02) */ 2340 2341 typedef struct { 2342 uint32_t rsvd1[3]; /* Read as all one's */ 2343 uint32_t rsvd2; /* Read as all zero's */ 2344 uint32_t portname[2]; /* N_PORT name */ 2345 uint32_t nodename[2]; /* NODE name */ 2346 2347 #ifdef __BIG_ENDIAN_BITFIELD 2348 uint32_t pref_DID:24; 2349 uint32_t hardAL_PA:8; 2350 #else /* __LITTLE_ENDIAN_BITFIELD */ 2351 uint32_t hardAL_PA:8; 2352 uint32_t pref_DID:24; 2353 #endif 2354 2355 uint32_t rsvd3[21]; /* Read as all one's */ 2356 } READ_NV_VAR; 2357 2358 /* Structure for MB Command WRITE_NVPARMS (03) */ 2359 2360 typedef struct { 2361 uint32_t rsvd1[3]; /* Must be all one's */ 2362 uint32_t rsvd2; /* Must be all zero's */ 2363 uint32_t portname[2]; /* N_PORT name */ 2364 uint32_t nodename[2]; /* NODE name */ 2365 2366 #ifdef __BIG_ENDIAN_BITFIELD 2367 uint32_t pref_DID:24; 2368 uint32_t hardAL_PA:8; 2369 #else /* __LITTLE_ENDIAN_BITFIELD */ 2370 uint32_t hardAL_PA:8; 2371 uint32_t pref_DID:24; 2372 #endif 2373 2374 uint32_t rsvd3[21]; /* Must be all one's */ 2375 } WRITE_NV_VAR; 2376 2377 /* Structure for MB Command RUN_BIU_DIAG (04) */ 2378 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 2379 2380 typedef struct { 2381 uint32_t rsvd1; 2382 union { 2383 struct { 2384 struct ulp_bde xmit_bde; 2385 struct ulp_bde rcv_bde; 2386 } s1; 2387 struct { 2388 struct ulp_bde64 xmit_bde64; 2389 struct ulp_bde64 rcv_bde64; 2390 } s2; 2391 } un; 2392 } BIU_DIAG_VAR; 2393 2394 /* Structure for MB command READ_EVENT_LOG (0x38) */ 2395 struct READ_EVENT_LOG_VAR { 2396 uint32_t word1; 2397 #define lpfc_event_log_SHIFT 29 2398 #define lpfc_event_log_MASK 0x00000001 2399 #define lpfc_event_log_WORD word1 2400 #define USE_MAILBOX_RESPONSE 1 2401 uint32_t offset; 2402 struct ulp_bde64 rcv_bde64; 2403 }; 2404 2405 /* Structure for MB Command INIT_LINK (05) */ 2406 2407 typedef struct { 2408 #ifdef __BIG_ENDIAN_BITFIELD 2409 uint32_t rsvd1:24; 2410 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2411 #else /* __LITTLE_ENDIAN_BITFIELD */ 2412 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2413 uint32_t rsvd1:24; 2414 #endif 2415 2416 #ifdef __BIG_ENDIAN_BITFIELD 2417 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2418 uint8_t rsvd2; 2419 uint16_t link_flags; 2420 #else /* __LITTLE_ENDIAN_BITFIELD */ 2421 uint16_t link_flags; 2422 uint8_t rsvd2; 2423 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2424 #endif 2425 2426 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 2427 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 2428 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 2429 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 2430 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 2431 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 2432 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 2433 2434 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 2435 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 2436 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 2437 2438 uint32_t link_speed; 2439 #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 2440 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 2441 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 2442 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 2443 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 2444 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 2445 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 2446 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ 2447 #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */ 2448 #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */ 2449 #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */ 2450 2451 } INIT_LINK_VAR; 2452 2453 /* Structure for MB Command DOWN_LINK (06) */ 2454 2455 typedef struct { 2456 uint32_t rsvd1; 2457 } DOWN_LINK_VAR; 2458 2459 /* Structure for MB Command CONFIG_LINK (07) */ 2460 2461 typedef struct { 2462 #ifdef __BIG_ENDIAN_BITFIELD 2463 uint32_t cr:1; 2464 uint32_t ci:1; 2465 uint32_t cr_delay:6; 2466 uint32_t cr_count:8; 2467 uint32_t rsvd1:8; 2468 uint32_t MaxBBC:8; 2469 #else /* __LITTLE_ENDIAN_BITFIELD */ 2470 uint32_t MaxBBC:8; 2471 uint32_t rsvd1:8; 2472 uint32_t cr_count:8; 2473 uint32_t cr_delay:6; 2474 uint32_t ci:1; 2475 uint32_t cr:1; 2476 #endif 2477 2478 uint32_t myId; 2479 uint32_t rsvd2; 2480 uint32_t edtov; 2481 uint32_t arbtov; 2482 uint32_t ratov; 2483 uint32_t rttov; 2484 uint32_t altov; 2485 uint32_t crtov; 2486 2487 #ifdef __BIG_ENDIAN_BITFIELD 2488 uint32_t rsvd4:19; 2489 uint32_t cscn:1; 2490 uint32_t bbscn:4; 2491 uint32_t rsvd3:8; 2492 #else /* __LITTLE_ENDIAN_BITFIELD */ 2493 uint32_t rsvd3:8; 2494 uint32_t bbscn:4; 2495 uint32_t cscn:1; 2496 uint32_t rsvd4:19; 2497 #endif 2498 2499 #ifdef __BIG_ENDIAN_BITFIELD 2500 uint32_t rrq_enable:1; 2501 uint32_t rrq_immed:1; 2502 uint32_t rsvd5:29; 2503 uint32_t ack0_enable:1; 2504 #else /* __LITTLE_ENDIAN_BITFIELD */ 2505 uint32_t ack0_enable:1; 2506 uint32_t rsvd5:29; 2507 uint32_t rrq_immed:1; 2508 uint32_t rrq_enable:1; 2509 #endif 2510 } CONFIG_LINK; 2511 2512 /* Structure for MB Command PART_SLIM (08) 2513 * will be removed since SLI1 is no longer supported! 2514 */ 2515 typedef struct { 2516 #ifdef __BIG_ENDIAN_BITFIELD 2517 uint16_t offCiocb; 2518 uint16_t numCiocb; 2519 uint16_t offRiocb; 2520 uint16_t numRiocb; 2521 #else /* __LITTLE_ENDIAN_BITFIELD */ 2522 uint16_t numCiocb; 2523 uint16_t offCiocb; 2524 uint16_t numRiocb; 2525 uint16_t offRiocb; 2526 #endif 2527 } RING_DEF; 2528 2529 typedef struct { 2530 #ifdef __BIG_ENDIAN_BITFIELD 2531 uint32_t unused1:24; 2532 uint32_t numRing:8; 2533 #else /* __LITTLE_ENDIAN_BITFIELD */ 2534 uint32_t numRing:8; 2535 uint32_t unused1:24; 2536 #endif 2537 2538 RING_DEF ringdef[4]; 2539 uint32_t hbainit; 2540 } PART_SLIM_VAR; 2541 2542 /* Structure for MB Command CONFIG_RING (09) */ 2543 2544 typedef struct { 2545 #ifdef __BIG_ENDIAN_BITFIELD 2546 uint32_t unused2:6; 2547 uint32_t recvSeq:1; 2548 uint32_t recvNotify:1; 2549 uint32_t numMask:8; 2550 uint32_t profile:8; 2551 uint32_t unused1:4; 2552 uint32_t ring:4; 2553 #else /* __LITTLE_ENDIAN_BITFIELD */ 2554 uint32_t ring:4; 2555 uint32_t unused1:4; 2556 uint32_t profile:8; 2557 uint32_t numMask:8; 2558 uint32_t recvNotify:1; 2559 uint32_t recvSeq:1; 2560 uint32_t unused2:6; 2561 #endif 2562 2563 #ifdef __BIG_ENDIAN_BITFIELD 2564 uint16_t maxRespXchg; 2565 uint16_t maxOrigXchg; 2566 #else /* __LITTLE_ENDIAN_BITFIELD */ 2567 uint16_t maxOrigXchg; 2568 uint16_t maxRespXchg; 2569 #endif 2570 2571 RR_REG rrRegs[6]; 2572 } CONFIG_RING_VAR; 2573 2574 /* Structure for MB Command RESET_RING (10) */ 2575 2576 typedef struct { 2577 uint32_t ring_no; 2578 } RESET_RING_VAR; 2579 2580 /* Structure for MB Command READ_CONFIG (11) */ 2581 2582 typedef struct { 2583 #ifdef __BIG_ENDIAN_BITFIELD 2584 uint32_t cr:1; 2585 uint32_t ci:1; 2586 uint32_t cr_delay:6; 2587 uint32_t cr_count:8; 2588 uint32_t InitBBC:8; 2589 uint32_t MaxBBC:8; 2590 #else /* __LITTLE_ENDIAN_BITFIELD */ 2591 uint32_t MaxBBC:8; 2592 uint32_t InitBBC:8; 2593 uint32_t cr_count:8; 2594 uint32_t cr_delay:6; 2595 uint32_t ci:1; 2596 uint32_t cr:1; 2597 #endif 2598 2599 #ifdef __BIG_ENDIAN_BITFIELD 2600 uint32_t topology:8; 2601 uint32_t myDid:24; 2602 #else /* __LITTLE_ENDIAN_BITFIELD */ 2603 uint32_t myDid:24; 2604 uint32_t topology:8; 2605 #endif 2606 2607 /* Defines for topology (defined previously) */ 2608 #ifdef __BIG_ENDIAN_BITFIELD 2609 uint32_t AR:1; 2610 uint32_t IR:1; 2611 uint32_t rsvd1:29; 2612 uint32_t ack0:1; 2613 #else /* __LITTLE_ENDIAN_BITFIELD */ 2614 uint32_t ack0:1; 2615 uint32_t rsvd1:29; 2616 uint32_t IR:1; 2617 uint32_t AR:1; 2618 #endif 2619 2620 uint32_t edtov; 2621 uint32_t arbtov; 2622 uint32_t ratov; 2623 uint32_t rttov; 2624 uint32_t altov; 2625 uint32_t lmt; 2626 #define LMT_RESERVED 0x000 /* Not used */ 2627 #define LMT_1Gb 0x004 2628 #define LMT_2Gb 0x008 2629 #define LMT_4Gb 0x040 2630 #define LMT_8Gb 0x080 2631 #define LMT_10Gb 0x100 2632 #define LMT_16Gb 0x200 2633 #define LMT_32Gb 0x400 2634 #define LMT_64Gb 0x800 2635 #define LMT_128Gb 0x1000 2636 #define LMT_256Gb 0x2000 2637 uint32_t rsvd2; 2638 uint32_t rsvd3; 2639 uint32_t max_xri; 2640 uint32_t max_iocb; 2641 uint32_t max_rpi; 2642 uint32_t avail_xri; 2643 uint32_t avail_iocb; 2644 uint32_t avail_rpi; 2645 uint32_t max_vpi; 2646 uint32_t rsvd4; 2647 uint32_t rsvd5; 2648 uint32_t avail_vpi; 2649 } READ_CONFIG_VAR; 2650 2651 /* Structure for MB Command READ_RCONFIG (12) */ 2652 2653 typedef struct { 2654 #ifdef __BIG_ENDIAN_BITFIELD 2655 uint32_t rsvd2:7; 2656 uint32_t recvNotify:1; 2657 uint32_t numMask:8; 2658 uint32_t profile:8; 2659 uint32_t rsvd1:4; 2660 uint32_t ring:4; 2661 #else /* __LITTLE_ENDIAN_BITFIELD */ 2662 uint32_t ring:4; 2663 uint32_t rsvd1:4; 2664 uint32_t profile:8; 2665 uint32_t numMask:8; 2666 uint32_t recvNotify:1; 2667 uint32_t rsvd2:7; 2668 #endif 2669 2670 #ifdef __BIG_ENDIAN_BITFIELD 2671 uint16_t maxResp; 2672 uint16_t maxOrig; 2673 #else /* __LITTLE_ENDIAN_BITFIELD */ 2674 uint16_t maxOrig; 2675 uint16_t maxResp; 2676 #endif 2677 2678 RR_REG rrRegs[6]; 2679 2680 #ifdef __BIG_ENDIAN_BITFIELD 2681 uint16_t cmdRingOffset; 2682 uint16_t cmdEntryCnt; 2683 uint16_t rspRingOffset; 2684 uint16_t rspEntryCnt; 2685 uint16_t nextCmdOffset; 2686 uint16_t rsvd3; 2687 uint16_t nextRspOffset; 2688 uint16_t rsvd4; 2689 #else /* __LITTLE_ENDIAN_BITFIELD */ 2690 uint16_t cmdEntryCnt; 2691 uint16_t cmdRingOffset; 2692 uint16_t rspEntryCnt; 2693 uint16_t rspRingOffset; 2694 uint16_t rsvd3; 2695 uint16_t nextCmdOffset; 2696 uint16_t rsvd4; 2697 uint16_t nextRspOffset; 2698 #endif 2699 } READ_RCONF_VAR; 2700 2701 /* Structure for MB Command READ_SPARM (13) */ 2702 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2703 2704 typedef struct { 2705 uint32_t rsvd1; 2706 uint32_t rsvd2; 2707 union { 2708 struct ulp_bde sp; /* This BDE points to struct serv_parm 2709 structure */ 2710 struct ulp_bde64 sp64; 2711 } un; 2712 #ifdef __BIG_ENDIAN_BITFIELD 2713 uint16_t rsvd3; 2714 uint16_t vpi; 2715 #else /* __LITTLE_ENDIAN_BITFIELD */ 2716 uint16_t vpi; 2717 uint16_t rsvd3; 2718 #endif 2719 } READ_SPARM_VAR; 2720 2721 /* Structure for MB Command READ_STATUS (14) */ 2722 enum read_status_word1 { 2723 RD_ST_CC = 0x01, 2724 RD_ST_XKB = 0x80, 2725 }; 2726 2727 enum read_status_word17 { 2728 RD_ST_XMIT_XKB_MASK = 0x3fffff, 2729 }; 2730 2731 enum read_status_word18 { 2732 RD_ST_RCV_XKB_MASK = 0x3fffff, 2733 }; 2734 2735 typedef struct { 2736 u8 clear_counters; /* rsvd 7:1, cc 0 */ 2737 u8 rsvd5; 2738 u8 rsvd6; 2739 u8 xkb; /* xkb 7, rsvd 6:0 */ 2740 2741 u32 rsvd8; 2742 2743 uint32_t xmitByteCnt; 2744 uint32_t rcvByteCnt; 2745 uint32_t xmitFrameCnt; 2746 uint32_t rcvFrameCnt; 2747 uint32_t xmitSeqCnt; 2748 uint32_t rcvSeqCnt; 2749 uint32_t totalOrigExchanges; 2750 uint32_t totalRespExchanges; 2751 uint32_t rcvPbsyCnt; 2752 uint32_t rcvFbsyCnt; 2753 2754 u32 drop_frame_no_rq; 2755 u32 empty_rq; 2756 u32 drop_frame_no_xri; 2757 u32 empty_xri; 2758 2759 u32 xmit_xkb; /* rsvd 31:22, xmit_xkb 21:0 */ 2760 u32 rcv_xkb; /* rsvd 31:22, rcv_xkb 21:0 */ 2761 } READ_STATUS_VAR; 2762 2763 /* Structure for MB Command READ_RPI (15) */ 2764 /* Structure for MB Command READ_RPI64 (0x8F) */ 2765 2766 typedef struct { 2767 #ifdef __BIG_ENDIAN_BITFIELD 2768 uint16_t nextRpi; 2769 uint16_t reqRpi; 2770 uint32_t rsvd2:8; 2771 uint32_t DID:24; 2772 #else /* __LITTLE_ENDIAN_BITFIELD */ 2773 uint16_t reqRpi; 2774 uint16_t nextRpi; 2775 uint32_t DID:24; 2776 uint32_t rsvd2:8; 2777 #endif 2778 2779 union { 2780 struct ulp_bde sp; 2781 struct ulp_bde64 sp64; 2782 } un; 2783 2784 } READ_RPI_VAR; 2785 2786 /* Structure for MB Command READ_XRI (16) */ 2787 2788 typedef struct { 2789 #ifdef __BIG_ENDIAN_BITFIELD 2790 uint16_t nextXri; 2791 uint16_t reqXri; 2792 uint16_t rsvd1; 2793 uint16_t rpi; 2794 uint32_t rsvd2:8; 2795 uint32_t DID:24; 2796 uint32_t rsvd3:8; 2797 uint32_t SID:24; 2798 uint32_t rsvd4; 2799 uint8_t seqId; 2800 uint8_t rsvd5; 2801 uint16_t seqCount; 2802 uint16_t oxId; 2803 uint16_t rxId; 2804 uint32_t rsvd6:30; 2805 uint32_t si:1; 2806 uint32_t exchOrig:1; 2807 #else /* __LITTLE_ENDIAN_BITFIELD */ 2808 uint16_t reqXri; 2809 uint16_t nextXri; 2810 uint16_t rpi; 2811 uint16_t rsvd1; 2812 uint32_t DID:24; 2813 uint32_t rsvd2:8; 2814 uint32_t SID:24; 2815 uint32_t rsvd3:8; 2816 uint32_t rsvd4; 2817 uint16_t seqCount; 2818 uint8_t rsvd5; 2819 uint8_t seqId; 2820 uint16_t rxId; 2821 uint16_t oxId; 2822 uint32_t exchOrig:1; 2823 uint32_t si:1; 2824 uint32_t rsvd6:30; 2825 #endif 2826 } READ_XRI_VAR; 2827 2828 /* Structure for MB Command READ_REV (17) */ 2829 2830 typedef struct { 2831 #ifdef __BIG_ENDIAN_BITFIELD 2832 uint32_t cv:1; 2833 uint32_t rr:1; 2834 uint32_t rsvd2:2; 2835 uint32_t v3req:1; 2836 uint32_t v3rsp:1; 2837 uint32_t rsvd1:25; 2838 uint32_t rv:1; 2839 #else /* __LITTLE_ENDIAN_BITFIELD */ 2840 uint32_t rv:1; 2841 uint32_t rsvd1:25; 2842 uint32_t v3rsp:1; 2843 uint32_t v3req:1; 2844 uint32_t rsvd2:2; 2845 uint32_t rr:1; 2846 uint32_t cv:1; 2847 #endif 2848 2849 uint32_t biuRev; 2850 uint32_t smRev; 2851 union { 2852 uint32_t smFwRev; 2853 struct { 2854 #ifdef __BIG_ENDIAN_BITFIELD 2855 uint8_t ProgType; 2856 uint8_t ProgId; 2857 uint16_t ProgVer:4; 2858 uint16_t ProgRev:4; 2859 uint16_t ProgFixLvl:2; 2860 uint16_t ProgDistType:2; 2861 uint16_t DistCnt:4; 2862 #else /* __LITTLE_ENDIAN_BITFIELD */ 2863 uint16_t DistCnt:4; 2864 uint16_t ProgDistType:2; 2865 uint16_t ProgFixLvl:2; 2866 uint16_t ProgRev:4; 2867 uint16_t ProgVer:4; 2868 uint8_t ProgId; 2869 uint8_t ProgType; 2870 #endif 2871 2872 } b; 2873 } un; 2874 uint32_t endecRev; 2875 #ifdef __BIG_ENDIAN_BITFIELD 2876 uint8_t feaLevelHigh; 2877 uint8_t feaLevelLow; 2878 uint8_t fcphHigh; 2879 uint8_t fcphLow; 2880 #else /* __LITTLE_ENDIAN_BITFIELD */ 2881 uint8_t fcphLow; 2882 uint8_t fcphHigh; 2883 uint8_t feaLevelLow; 2884 uint8_t feaLevelHigh; 2885 #endif 2886 2887 uint32_t postKernRev; 2888 uint32_t opFwRev; 2889 uint8_t opFwName[16]; 2890 uint32_t sli1FwRev; 2891 uint8_t sli1FwName[16]; 2892 uint32_t sli2FwRev; 2893 uint8_t sli2FwName[16]; 2894 uint32_t sli3Feat; 2895 uint32_t RandomData[6]; 2896 } READ_REV_VAR; 2897 2898 /* Structure for MB Command READ_LINK_STAT (18) */ 2899 2900 typedef struct { 2901 uint32_t word0; 2902 2903 #define lpfc_read_link_stat_rec_SHIFT 0 2904 #define lpfc_read_link_stat_rec_MASK 0x1 2905 #define lpfc_read_link_stat_rec_WORD word0 2906 2907 #define lpfc_read_link_stat_gec_SHIFT 1 2908 #define lpfc_read_link_stat_gec_MASK 0x1 2909 #define lpfc_read_link_stat_gec_WORD word0 2910 2911 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2 2912 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF 2913 #define lpfc_read_link_stat_w02oftow23of_WORD word0 2914 2915 #define lpfc_read_link_stat_rsvd_SHIFT 24 2916 #define lpfc_read_link_stat_rsvd_MASK 0x1F 2917 #define lpfc_read_link_stat_rsvd_WORD word0 2918 2919 #define lpfc_read_link_stat_gec2_SHIFT 29 2920 #define lpfc_read_link_stat_gec2_MASK 0x1 2921 #define lpfc_read_link_stat_gec2_WORD word0 2922 2923 #define lpfc_read_link_stat_clrc_SHIFT 30 2924 #define lpfc_read_link_stat_clrc_MASK 0x1 2925 #define lpfc_read_link_stat_clrc_WORD word0 2926 2927 #define lpfc_read_link_stat_clof_SHIFT 31 2928 #define lpfc_read_link_stat_clof_MASK 0x1 2929 #define lpfc_read_link_stat_clof_WORD word0 2930 2931 uint32_t linkFailureCnt; 2932 uint32_t lossSyncCnt; 2933 uint32_t lossSignalCnt; 2934 uint32_t primSeqErrCnt; 2935 uint32_t invalidXmitWord; 2936 uint32_t crcCnt; 2937 uint32_t primSeqTimeout; 2938 uint32_t elasticOverrun; 2939 uint32_t arbTimeout; 2940 uint32_t advRecBufCredit; 2941 uint32_t curRecBufCredit; 2942 uint32_t advTransBufCredit; 2943 uint32_t curTransBufCredit; 2944 uint32_t recEofCount; 2945 uint32_t recEofdtiCount; 2946 uint32_t recEofniCount; 2947 uint32_t recSofcount; 2948 uint32_t rsvd1; 2949 uint32_t rsvd2; 2950 uint32_t recDrpXriCount; 2951 uint32_t fecCorrBlkCount; 2952 uint32_t fecUncorrBlkCount; 2953 } READ_LNK_VAR; 2954 2955 /* Structure for MB Command REG_LOGIN (19) */ 2956 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2957 2958 typedef struct { 2959 #ifdef __BIG_ENDIAN_BITFIELD 2960 uint16_t rsvd1; 2961 uint16_t rpi; 2962 uint32_t rsvd2:8; 2963 uint32_t did:24; 2964 #else /* __LITTLE_ENDIAN_BITFIELD */ 2965 uint16_t rpi; 2966 uint16_t rsvd1; 2967 uint32_t did:24; 2968 uint32_t rsvd2:8; 2969 #endif 2970 2971 union { 2972 struct ulp_bde sp; 2973 struct ulp_bde64 sp64; 2974 } un; 2975 2976 #ifdef __BIG_ENDIAN_BITFIELD 2977 uint16_t rsvd6; 2978 uint16_t vpi; 2979 #else /* __LITTLE_ENDIAN_BITFIELD */ 2980 uint16_t vpi; 2981 uint16_t rsvd6; 2982 #endif 2983 2984 } REG_LOGIN_VAR; 2985 2986 /* Word 30 contents for REG_LOGIN */ 2987 typedef union { 2988 struct { 2989 #ifdef __BIG_ENDIAN_BITFIELD 2990 uint16_t rsvd1:12; 2991 uint16_t wd30_class:4; 2992 uint16_t xri; 2993 #else /* __LITTLE_ENDIAN_BITFIELD */ 2994 uint16_t xri; 2995 uint16_t wd30_class:4; 2996 uint16_t rsvd1:12; 2997 #endif 2998 } f; 2999 uint32_t word; 3000 } REG_WD30; 3001 3002 /* Structure for MB Command UNREG_LOGIN (20) */ 3003 3004 typedef struct { 3005 #ifdef __BIG_ENDIAN_BITFIELD 3006 uint16_t rsvd1; 3007 uint16_t rpi; 3008 uint32_t rsvd2; 3009 uint32_t rsvd3; 3010 uint32_t rsvd4; 3011 uint32_t rsvd5; 3012 uint16_t rsvd6; 3013 uint16_t vpi; 3014 #else /* __LITTLE_ENDIAN_BITFIELD */ 3015 uint16_t rpi; 3016 uint16_t rsvd1; 3017 uint32_t rsvd2; 3018 uint32_t rsvd3; 3019 uint32_t rsvd4; 3020 uint32_t rsvd5; 3021 uint16_t vpi; 3022 uint16_t rsvd6; 3023 #endif 3024 } UNREG_LOGIN_VAR; 3025 3026 /* Structure for MB Command REG_VPI (0x96) */ 3027 typedef struct { 3028 #ifdef __BIG_ENDIAN_BITFIELD 3029 uint32_t rsvd1; 3030 uint32_t rsvd2:7; 3031 uint32_t upd:1; 3032 uint32_t sid:24; 3033 uint32_t wwn[2]; 3034 uint32_t rsvd5; 3035 uint16_t vfi; 3036 uint16_t vpi; 3037 #else /* __LITTLE_ENDIAN */ 3038 uint32_t rsvd1; 3039 uint32_t sid:24; 3040 uint32_t upd:1; 3041 uint32_t rsvd2:7; 3042 uint32_t wwn[2]; 3043 uint32_t rsvd5; 3044 uint16_t vpi; 3045 uint16_t vfi; 3046 #endif 3047 } REG_VPI_VAR; 3048 3049 /* Structure for MB Command UNREG_VPI (0x97) */ 3050 typedef struct { 3051 uint32_t rsvd1; 3052 #ifdef __BIG_ENDIAN_BITFIELD 3053 uint16_t rsvd2; 3054 uint16_t sli4_vpi; 3055 #else /* __LITTLE_ENDIAN */ 3056 uint16_t sli4_vpi; 3057 uint16_t rsvd2; 3058 #endif 3059 uint32_t rsvd3; 3060 uint32_t rsvd4; 3061 uint32_t rsvd5; 3062 #ifdef __BIG_ENDIAN_BITFIELD 3063 uint16_t rsvd6; 3064 uint16_t vpi; 3065 #else /* __LITTLE_ENDIAN */ 3066 uint16_t vpi; 3067 uint16_t rsvd6; 3068 #endif 3069 } UNREG_VPI_VAR; 3070 3071 /* Structure for MB Command UNREG_D_ID (0x23) */ 3072 3073 typedef struct { 3074 uint32_t did; 3075 uint32_t rsvd2; 3076 uint32_t rsvd3; 3077 uint32_t rsvd4; 3078 uint32_t rsvd5; 3079 #ifdef __BIG_ENDIAN_BITFIELD 3080 uint16_t rsvd6; 3081 uint16_t vpi; 3082 #else 3083 uint16_t vpi; 3084 uint16_t rsvd6; 3085 #endif 3086 } UNREG_D_ID_VAR; 3087 3088 /* Structure for MB Command READ_TOPOLOGY (0x95) */ 3089 struct lpfc_mbx_read_top { 3090 uint32_t eventTag; /* Event tag */ 3091 uint32_t word2; 3092 #define lpfc_mbx_read_top_fa_SHIFT 12 3093 #define lpfc_mbx_read_top_fa_MASK 0x00000001 3094 #define lpfc_mbx_read_top_fa_WORD word2 3095 #define lpfc_mbx_read_top_mm_SHIFT 11 3096 #define lpfc_mbx_read_top_mm_MASK 0x00000001 3097 #define lpfc_mbx_read_top_mm_WORD word2 3098 #define lpfc_mbx_read_top_pb_SHIFT 9 3099 #define lpfc_mbx_read_top_pb_MASK 0X00000001 3100 #define lpfc_mbx_read_top_pb_WORD word2 3101 #define lpfc_mbx_read_top_il_SHIFT 8 3102 #define lpfc_mbx_read_top_il_MASK 0x00000001 3103 #define lpfc_mbx_read_top_il_WORD word2 3104 #define lpfc_mbx_read_top_att_type_SHIFT 0 3105 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 3106 #define lpfc_mbx_read_top_att_type_WORD word2 3107 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 3108 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 3109 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 3110 #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */ 3111 uint32_t word3; 3112 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 3113 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 3114 #define lpfc_mbx_read_top_alpa_granted_WORD word3 3115 #define lpfc_mbx_read_top_lip_alps_SHIFT 16 3116 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 3117 #define lpfc_mbx_read_top_lip_alps_WORD word3 3118 #define lpfc_mbx_read_top_lip_type_SHIFT 8 3119 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 3120 #define lpfc_mbx_read_top_lip_type_WORD word3 3121 #define lpfc_mbx_read_top_topology_SHIFT 0 3122 #define lpfc_mbx_read_top_topology_MASK 0x000000FF 3123 #define lpfc_mbx_read_top_topology_WORD word3 3124 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 3125 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 3126 /* store the LILP AL_PA position map into */ 3127 struct ulp_bde64 lilpBde64; 3128 #define LPFC_ALPA_MAP_SIZE 128 3129 uint32_t word7; 3130 #define lpfc_mbx_read_top_ld_lu_SHIFT 31 3131 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 3132 #define lpfc_mbx_read_top_ld_lu_WORD word7 3133 #define lpfc_mbx_read_top_ld_tf_SHIFT 30 3134 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 3135 #define lpfc_mbx_read_top_ld_tf_WORD word7 3136 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 3137 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 3138 #define lpfc_mbx_read_top_ld_link_spd_WORD word7 3139 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 3140 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 3141 #define lpfc_mbx_read_top_ld_nl_port_WORD word7 3142 #define lpfc_mbx_read_top_ld_tx_SHIFT 2 3143 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 3144 #define lpfc_mbx_read_top_ld_tx_WORD word7 3145 #define lpfc_mbx_read_top_ld_rx_SHIFT 0 3146 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 3147 #define lpfc_mbx_read_top_ld_rx_WORD word7 3148 uint32_t word8; 3149 #define lpfc_mbx_read_top_lu_SHIFT 31 3150 #define lpfc_mbx_read_top_lu_MASK 0x00000001 3151 #define lpfc_mbx_read_top_lu_WORD word8 3152 #define lpfc_mbx_read_top_tf_SHIFT 30 3153 #define lpfc_mbx_read_top_tf_MASK 0x00000001 3154 #define lpfc_mbx_read_top_tf_WORD word8 3155 #define lpfc_mbx_read_top_link_spd_SHIFT 8 3156 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 3157 #define lpfc_mbx_read_top_link_spd_WORD word8 3158 #define lpfc_mbx_read_top_nl_port_SHIFT 4 3159 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 3160 #define lpfc_mbx_read_top_nl_port_WORD word8 3161 #define lpfc_mbx_read_top_tx_SHIFT 2 3162 #define lpfc_mbx_read_top_tx_MASK 0x00000003 3163 #define lpfc_mbx_read_top_tx_WORD word8 3164 #define lpfc_mbx_read_top_rx_SHIFT 0 3165 #define lpfc_mbx_read_top_rx_MASK 0x00000003 3166 #define lpfc_mbx_read_top_rx_WORD word8 3167 #define LPFC_LINK_SPEED_UNKNOWN 0x0 3168 #define LPFC_LINK_SPEED_1GHZ 0x04 3169 #define LPFC_LINK_SPEED_2GHZ 0x08 3170 #define LPFC_LINK_SPEED_4GHZ 0x10 3171 #define LPFC_LINK_SPEED_8GHZ 0x20 3172 #define LPFC_LINK_SPEED_10GHZ 0x40 3173 #define LPFC_LINK_SPEED_16GHZ 0x80 3174 #define LPFC_LINK_SPEED_32GHZ 0x90 3175 #define LPFC_LINK_SPEED_64GHZ 0xA0 3176 #define LPFC_LINK_SPEED_128GHZ 0xB0 3177 #define LPFC_LINK_SPEED_256GHZ 0xC0 3178 }; 3179 3180 /* Structure for MB Command CLEAR_LA (22) */ 3181 3182 typedef struct { 3183 uint32_t eventTag; /* Event tag */ 3184 uint32_t rsvd1; 3185 } CLEAR_LA_VAR; 3186 3187 /* Structure for MB Command DUMP */ 3188 3189 typedef struct { 3190 #ifdef __BIG_ENDIAN_BITFIELD 3191 uint32_t rsvd:25; 3192 uint32_t ra:1; 3193 uint32_t co:1; 3194 uint32_t cv:1; 3195 uint32_t type:4; 3196 uint32_t entry_index:16; 3197 uint32_t region_id:16; 3198 #else /* __LITTLE_ENDIAN_BITFIELD */ 3199 uint32_t type:4; 3200 uint32_t cv:1; 3201 uint32_t co:1; 3202 uint32_t ra:1; 3203 uint32_t rsvd:25; 3204 uint32_t region_id:16; 3205 uint32_t entry_index:16; 3206 #endif 3207 3208 uint32_t sli4_length; 3209 uint32_t word_cnt; 3210 uint32_t resp_offset; 3211 } DUMP_VAR; 3212 3213 #define DMP_MEM_REG 0x1 3214 #define DMP_NV_PARAMS 0x2 3215 #define DMP_LMSD 0x3 /* Link Module Serial Data */ 3216 #define DMP_WELL_KNOWN 0x4 3217 3218 #define DMP_REGION_VPD 0xe 3219 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 3220 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 3221 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 3222 3223 #define DMP_REGION_VPORT 0x16 /* VPort info region */ 3224 #define DMP_VPORT_REGION_SIZE 0x200 3225 #define DMP_MBOX_OFFSET_WORD 0x5 3226 3227 #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 3228 #define DMP_RGN23_SIZE 0x400 3229 3230 #define WAKE_UP_PARMS_REGION_ID 4 3231 #define WAKE_UP_PARMS_WORD_SIZE 15 3232 3233 struct vport_rec { 3234 uint8_t wwpn[8]; 3235 uint8_t wwnn[8]; 3236 }; 3237 3238 #define VPORT_INFO_SIG 0x32324752 3239 #define VPORT_INFO_REV_MASK 0xff 3240 #define VPORT_INFO_REV 0x1 3241 #define MAX_STATIC_VPORT_COUNT 16 3242 struct static_vport_info { 3243 uint32_t signature; 3244 uint32_t rev; 3245 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 3246 uint32_t resvd[66]; 3247 }; 3248 3249 /* Option rom version structure */ 3250 struct prog_id { 3251 #ifdef __BIG_ENDIAN_BITFIELD 3252 uint8_t type; 3253 uint8_t id; 3254 uint32_t ver:4; /* Major Version */ 3255 uint32_t rev:4; /* Revision */ 3256 uint32_t lev:2; /* Level */ 3257 uint32_t dist:2; /* Dist Type */ 3258 uint32_t num:4; /* number after dist type */ 3259 #else /* __LITTLE_ENDIAN_BITFIELD */ 3260 uint32_t num:4; /* number after dist type */ 3261 uint32_t dist:2; /* Dist Type */ 3262 uint32_t lev:2; /* Level */ 3263 uint32_t rev:4; /* Revision */ 3264 uint32_t ver:4; /* Major Version */ 3265 uint8_t id; 3266 uint8_t type; 3267 #endif 3268 }; 3269 3270 /* Structure for MB Command UPDATE_CFG (0x1B) */ 3271 3272 struct update_cfg_var { 3273 #ifdef __BIG_ENDIAN_BITFIELD 3274 uint32_t rsvd2:16; 3275 uint32_t type:8; 3276 uint32_t rsvd:1; 3277 uint32_t ra:1; 3278 uint32_t co:1; 3279 uint32_t cv:1; 3280 uint32_t req:4; 3281 uint32_t entry_length:16; 3282 uint32_t region_id:16; 3283 #else /* __LITTLE_ENDIAN_BITFIELD */ 3284 uint32_t req:4; 3285 uint32_t cv:1; 3286 uint32_t co:1; 3287 uint32_t ra:1; 3288 uint32_t rsvd:1; 3289 uint32_t type:8; 3290 uint32_t rsvd2:16; 3291 uint32_t region_id:16; 3292 uint32_t entry_length:16; 3293 #endif 3294 3295 uint32_t resp_info; 3296 uint32_t byte_cnt; 3297 uint32_t data_offset; 3298 }; 3299 3300 struct hbq_mask { 3301 #ifdef __BIG_ENDIAN_BITFIELD 3302 uint8_t tmatch; 3303 uint8_t tmask; 3304 uint8_t rctlmatch; 3305 uint8_t rctlmask; 3306 #else /* __LITTLE_ENDIAN */ 3307 uint8_t rctlmask; 3308 uint8_t rctlmatch; 3309 uint8_t tmask; 3310 uint8_t tmatch; 3311 #endif 3312 }; 3313 3314 3315 /* Structure for MB Command CONFIG_HBQ (7c) */ 3316 3317 struct config_hbq_var { 3318 #ifdef __BIG_ENDIAN_BITFIELD 3319 uint32_t rsvd1 :7; 3320 uint32_t recvNotify :1; /* Receive Notification */ 3321 uint32_t numMask :8; /* # Mask Entries */ 3322 uint32_t profile :8; /* Selection Profile */ 3323 uint32_t rsvd2 :8; 3324 #else /* __LITTLE_ENDIAN */ 3325 uint32_t rsvd2 :8; 3326 uint32_t profile :8; /* Selection Profile */ 3327 uint32_t numMask :8; /* # Mask Entries */ 3328 uint32_t recvNotify :1; /* Receive Notification */ 3329 uint32_t rsvd1 :7; 3330 #endif 3331 3332 #ifdef __BIG_ENDIAN_BITFIELD 3333 uint32_t hbqId :16; 3334 uint32_t rsvd3 :12; 3335 uint32_t ringMask :4; 3336 #else /* __LITTLE_ENDIAN */ 3337 uint32_t ringMask :4; 3338 uint32_t rsvd3 :12; 3339 uint32_t hbqId :16; 3340 #endif 3341 3342 #ifdef __BIG_ENDIAN_BITFIELD 3343 uint32_t entry_count :16; 3344 uint32_t rsvd4 :8; 3345 uint32_t headerLen :8; 3346 #else /* __LITTLE_ENDIAN */ 3347 uint32_t headerLen :8; 3348 uint32_t rsvd4 :8; 3349 uint32_t entry_count :16; 3350 #endif 3351 3352 uint32_t hbqaddrLow; 3353 uint32_t hbqaddrHigh; 3354 3355 #ifdef __BIG_ENDIAN_BITFIELD 3356 uint32_t rsvd5 :31; 3357 uint32_t logEntry :1; 3358 #else /* __LITTLE_ENDIAN */ 3359 uint32_t logEntry :1; 3360 uint32_t rsvd5 :31; 3361 #endif 3362 3363 uint32_t rsvd6; /* w7 */ 3364 uint32_t rsvd7; /* w8 */ 3365 uint32_t rsvd8; /* w9 */ 3366 3367 struct hbq_mask hbqMasks[6]; 3368 3369 3370 union { 3371 uint32_t allprofiles[12]; 3372 3373 struct { 3374 #ifdef __BIG_ENDIAN_BITFIELD 3375 uint32_t seqlenoff :16; 3376 uint32_t maxlen :16; 3377 #else /* __LITTLE_ENDIAN */ 3378 uint32_t maxlen :16; 3379 uint32_t seqlenoff :16; 3380 #endif 3381 #ifdef __BIG_ENDIAN_BITFIELD 3382 uint32_t rsvd1 :28; 3383 uint32_t seqlenbcnt :4; 3384 #else /* __LITTLE_ENDIAN */ 3385 uint32_t seqlenbcnt :4; 3386 uint32_t rsvd1 :28; 3387 #endif 3388 uint32_t rsvd[10]; 3389 } profile2; 3390 3391 struct { 3392 #ifdef __BIG_ENDIAN_BITFIELD 3393 uint32_t seqlenoff :16; 3394 uint32_t maxlen :16; 3395 #else /* __LITTLE_ENDIAN */ 3396 uint32_t maxlen :16; 3397 uint32_t seqlenoff :16; 3398 #endif 3399 #ifdef __BIG_ENDIAN_BITFIELD 3400 uint32_t cmdcodeoff :28; 3401 uint32_t rsvd1 :12; 3402 uint32_t seqlenbcnt :4; 3403 #else /* __LITTLE_ENDIAN */ 3404 uint32_t seqlenbcnt :4; 3405 uint32_t rsvd1 :12; 3406 uint32_t cmdcodeoff :28; 3407 #endif 3408 uint32_t cmdmatch[8]; 3409 3410 uint32_t rsvd[2]; 3411 } profile3; 3412 3413 struct { 3414 #ifdef __BIG_ENDIAN_BITFIELD 3415 uint32_t seqlenoff :16; 3416 uint32_t maxlen :16; 3417 #else /* __LITTLE_ENDIAN */ 3418 uint32_t maxlen :16; 3419 uint32_t seqlenoff :16; 3420 #endif 3421 #ifdef __BIG_ENDIAN_BITFIELD 3422 uint32_t cmdcodeoff :28; 3423 uint32_t rsvd1 :12; 3424 uint32_t seqlenbcnt :4; 3425 #else /* __LITTLE_ENDIAN */ 3426 uint32_t seqlenbcnt :4; 3427 uint32_t rsvd1 :12; 3428 uint32_t cmdcodeoff :28; 3429 #endif 3430 uint32_t cmdmatch[8]; 3431 3432 uint32_t rsvd[2]; 3433 } profile5; 3434 3435 } profiles; 3436 3437 }; 3438 3439 3440 3441 /* Structure for MB Command CONFIG_PORT (0x88) */ 3442 typedef struct { 3443 #ifdef __BIG_ENDIAN_BITFIELD 3444 uint32_t cBE : 1; 3445 uint32_t cET : 1; 3446 uint32_t cHpcb : 1; 3447 uint32_t cMA : 1; 3448 uint32_t sli_mode : 4; 3449 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3450 * config block */ 3451 #else /* __LITTLE_ENDIAN */ 3452 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3453 * config block */ 3454 uint32_t sli_mode : 4; 3455 uint32_t cMA : 1; 3456 uint32_t cHpcb : 1; 3457 uint32_t cET : 1; 3458 uint32_t cBE : 1; 3459 #endif 3460 3461 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 3462 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 3463 uint32_t hbainit[5]; 3464 #ifdef __BIG_ENDIAN_BITFIELD 3465 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3466 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3467 #else /* __LITTLE_ENDIAN */ 3468 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3469 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3470 #endif 3471 3472 #ifdef __BIG_ENDIAN_BITFIELD 3473 uint32_t rsvd1 : 20; /* Reserved */ 3474 uint32_t casabt : 1; /* Configure async abts status notice */ 3475 uint32_t rsvd2 : 2; /* Reserved */ 3476 uint32_t cbg : 1; /* Configure BlockGuard */ 3477 uint32_t cmv : 1; /* Configure Max VPIs */ 3478 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3479 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3480 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3481 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3482 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3483 uint32_t cmx : 1; /* Configure Max XRIs */ 3484 uint32_t cmr : 1; /* Configure Max RPIs */ 3485 #else /* __LITTLE_ENDIAN */ 3486 uint32_t cmr : 1; /* Configure Max RPIs */ 3487 uint32_t cmx : 1; /* Configure Max XRIs */ 3488 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3489 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3490 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3491 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3492 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3493 uint32_t cmv : 1; /* Configure Max VPIs */ 3494 uint32_t cbg : 1; /* Configure BlockGuard */ 3495 uint32_t rsvd2 : 2; /* Reserved */ 3496 uint32_t casabt : 1; /* Configure async abts status notice */ 3497 uint32_t rsvd1 : 20; /* Reserved */ 3498 #endif 3499 #ifdef __BIG_ENDIAN_BITFIELD 3500 uint32_t rsvd3 : 20; /* Reserved */ 3501 uint32_t gasabt : 1; /* Grant async abts status notice */ 3502 uint32_t rsvd4 : 2; /* Reserved */ 3503 uint32_t gbg : 1; /* Grant BlockGuard */ 3504 uint32_t gmv : 1; /* Grant Max VPIs */ 3505 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3506 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3507 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3508 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3509 uint32_t gerbm : 1; /* Grant ERBM Request */ 3510 uint32_t gmx : 1; /* Grant Max XRIs */ 3511 uint32_t gmr : 1; /* Grant Max RPIs */ 3512 #else /* __LITTLE_ENDIAN */ 3513 uint32_t gmr : 1; /* Grant Max RPIs */ 3514 uint32_t gmx : 1; /* Grant Max XRIs */ 3515 uint32_t gerbm : 1; /* Grant ERBM Request */ 3516 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3517 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3518 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3519 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3520 uint32_t gmv : 1; /* Grant Max VPIs */ 3521 uint32_t gbg : 1; /* Grant BlockGuard */ 3522 uint32_t rsvd4 : 2; /* Reserved */ 3523 uint32_t gasabt : 1; /* Grant async abts status notice */ 3524 uint32_t rsvd3 : 20; /* Reserved */ 3525 #endif 3526 3527 #ifdef __BIG_ENDIAN_BITFIELD 3528 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3529 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3530 #else /* __LITTLE_ENDIAN */ 3531 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3532 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3533 #endif 3534 3535 #ifdef __BIG_ENDIAN_BITFIELD 3536 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3537 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3538 #else /* __LITTLE_ENDIAN */ 3539 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3540 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3541 #endif 3542 3543 uint32_t rsvd6; /* Reserved */ 3544 3545 #ifdef __BIG_ENDIAN_BITFIELD 3546 uint32_t rsvd7 : 16; 3547 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3548 #else /* __LITTLE_ENDIAN */ 3549 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3550 uint32_t rsvd7 : 16; 3551 #endif 3552 3553 } CONFIG_PORT_VAR; 3554 3555 /* Structure for MB Command CONFIG_MSI (0x30) */ 3556 struct config_msi_var { 3557 #ifdef __BIG_ENDIAN_BITFIELD 3558 uint32_t dfltMsgNum:8; /* Default message number */ 3559 uint32_t rsvd1:11; /* Reserved */ 3560 uint32_t NID:5; /* Number of secondary attention IDs */ 3561 uint32_t rsvd2:5; /* Reserved */ 3562 uint32_t dfltPresent:1; /* Default message number present */ 3563 uint32_t addFlag:1; /* Add association flag */ 3564 uint32_t reportFlag:1; /* Report association flag */ 3565 #else /* __LITTLE_ENDIAN_BITFIELD */ 3566 uint32_t reportFlag:1; /* Report association flag */ 3567 uint32_t addFlag:1; /* Add association flag */ 3568 uint32_t dfltPresent:1; /* Default message number present */ 3569 uint32_t rsvd2:5; /* Reserved */ 3570 uint32_t NID:5; /* Number of secondary attention IDs */ 3571 uint32_t rsvd1:11; /* Reserved */ 3572 uint32_t dfltMsgNum:8; /* Default message number */ 3573 #endif 3574 uint32_t attentionConditions[2]; 3575 uint8_t attentionId[16]; 3576 uint8_t messageNumberByHA[64]; 3577 uint8_t messageNumberByID[16]; 3578 uint32_t autoClearHA[2]; 3579 #ifdef __BIG_ENDIAN_BITFIELD 3580 uint32_t rsvd3:16; 3581 uint32_t autoClearID:16; 3582 #else /* __LITTLE_ENDIAN_BITFIELD */ 3583 uint32_t autoClearID:16; 3584 uint32_t rsvd3:16; 3585 #endif 3586 uint32_t rsvd4; 3587 }; 3588 3589 /* SLI-2 Port Control Block */ 3590 3591 /* SLIM POINTER */ 3592 #define SLIMOFF 0x30 /* WORD */ 3593 3594 typedef struct _SLI2_RDSC { 3595 uint32_t cmdEntries; 3596 uint32_t cmdAddrLow; 3597 uint32_t cmdAddrHigh; 3598 3599 uint32_t rspEntries; 3600 uint32_t rspAddrLow; 3601 uint32_t rspAddrHigh; 3602 } SLI2_RDSC; 3603 3604 typedef struct _PCB { 3605 #ifdef __BIG_ENDIAN_BITFIELD 3606 uint32_t type:8; 3607 #define TYPE_NATIVE_SLI2 0x01 3608 uint32_t feature:8; 3609 #define FEATURE_INITIAL_SLI2 0x01 3610 uint32_t rsvd:12; 3611 uint32_t maxRing:4; 3612 #else /* __LITTLE_ENDIAN_BITFIELD */ 3613 uint32_t maxRing:4; 3614 uint32_t rsvd:12; 3615 uint32_t feature:8; 3616 #define FEATURE_INITIAL_SLI2 0x01 3617 uint32_t type:8; 3618 #define TYPE_NATIVE_SLI2 0x01 3619 #endif 3620 3621 uint32_t mailBoxSize; 3622 uint32_t mbAddrLow; 3623 uint32_t mbAddrHigh; 3624 3625 uint32_t hgpAddrLow; 3626 uint32_t hgpAddrHigh; 3627 3628 uint32_t pgpAddrLow; 3629 uint32_t pgpAddrHigh; 3630 SLI2_RDSC rdsc[MAX_SLI3_RINGS]; 3631 } PCB_t; 3632 3633 /* NEW_FEATURE */ 3634 typedef struct { 3635 #ifdef __BIG_ENDIAN_BITFIELD 3636 uint32_t rsvd0:27; 3637 uint32_t discardFarp:1; 3638 uint32_t IPEnable:1; 3639 uint32_t nodeName:1; 3640 uint32_t portName:1; 3641 uint32_t filterEnable:1; 3642 #else /* __LITTLE_ENDIAN_BITFIELD */ 3643 uint32_t filterEnable:1; 3644 uint32_t portName:1; 3645 uint32_t nodeName:1; 3646 uint32_t IPEnable:1; 3647 uint32_t discardFarp:1; 3648 uint32_t rsvd:27; 3649 #endif 3650 3651 uint8_t portname[8]; /* Used to be struct lpfc_name */ 3652 uint8_t nodename[8]; 3653 uint32_t rsvd1; 3654 uint32_t rsvd2; 3655 uint32_t rsvd3; 3656 uint32_t IPAddress; 3657 } CONFIG_FARP_VAR; 3658 3659 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 3660 3661 typedef struct { 3662 #ifdef __BIG_ENDIAN_BITFIELD 3663 uint32_t rsvd:30; 3664 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3665 #else /* __LITTLE_ENDIAN */ 3666 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3667 uint32_t rsvd:30; 3668 #endif 3669 } ASYNCEVT_ENABLE_VAR; 3670 3671 /* Union of all Mailbox Command types */ 3672 #define MAILBOX_CMD_WSIZE 32 3673 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 3674 /* ext_wsize times 4 bytes should not be greater than max xmit size */ 3675 #define MAILBOX_EXT_WSIZE 512 3676 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 3677 #define MAILBOX_HBA_EXT_OFFSET 0x100 3678 /* max mbox xmit size is a page size for sysfs IO operations */ 3679 #define MAILBOX_SYSFS_MAX 4096 3680 3681 typedef union { 3682 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3683 * feature/max ring number 3684 */ 3685 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3686 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3687 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3688 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3689 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3690 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3691 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3692 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3693 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3694 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3695 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3696 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3697 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3698 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3699 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3700 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3701 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3702 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3703 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3704 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3705 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3706 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3707 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3708 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3709 * NEW_FEATURE 3710 */ 3711 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3712 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3713 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3714 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 3715 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3716 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3717 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3718 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3719 * (READ_EVENT_LOG) 3720 */ 3721 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3722 } MAILVARIANTS; 3723 3724 /* 3725 * SLI-2 specific structures 3726 */ 3727 3728 struct lpfc_hgp { 3729 __le32 cmdPutInx; 3730 __le32 rspGetInx; 3731 }; 3732 3733 struct lpfc_pgp { 3734 __le32 cmdGetInx; 3735 __le32 rspPutInx; 3736 }; 3737 3738 struct sli2_desc { 3739 uint32_t unused1[16]; 3740 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3741 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3742 }; 3743 3744 struct sli3_desc { 3745 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3746 uint32_t reserved[8]; 3747 uint32_t hbq_put[16]; 3748 }; 3749 3750 struct sli3_pgp { 3751 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3752 uint32_t hbq_get[16]; 3753 }; 3754 3755 union sli_var { 3756 struct sli2_desc s2; 3757 struct sli3_desc s3; 3758 struct sli3_pgp s3_pgp; 3759 }; 3760 3761 typedef struct { 3762 struct_group_tagged(MAILBOX_word0, bits, 3763 union { 3764 struct { 3765 #ifdef __BIG_ENDIAN_BITFIELD 3766 uint16_t mbxStatus; 3767 uint8_t mbxCommand; 3768 uint8_t mbxReserved:6; 3769 uint8_t mbxHc:1; 3770 uint8_t mbxOwner:1; /* Low order bit first word */ 3771 #else /* __LITTLE_ENDIAN_BITFIELD */ 3772 uint8_t mbxOwner:1; /* Low order bit first word */ 3773 uint8_t mbxHc:1; 3774 uint8_t mbxReserved:6; 3775 uint8_t mbxCommand; 3776 uint16_t mbxStatus; 3777 #endif 3778 }; 3779 u32 word0; 3780 }; 3781 ); 3782 3783 MAILVARIANTS un; 3784 union sli_var us; 3785 } MAILBOX_t; 3786 3787 /* 3788 * Begin Structure Definitions for IOCB Commands 3789 */ 3790 3791 typedef struct { 3792 #ifdef __BIG_ENDIAN_BITFIELD 3793 uint8_t statAction; 3794 uint8_t statRsn; 3795 uint8_t statBaExp; 3796 uint8_t statLocalError; 3797 #else /* __LITTLE_ENDIAN_BITFIELD */ 3798 uint8_t statLocalError; 3799 uint8_t statBaExp; 3800 uint8_t statRsn; 3801 uint8_t statAction; 3802 #endif 3803 /* statRsn P/F_RJT reason codes */ 3804 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3805 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3806 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3807 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3808 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3809 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3810 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3811 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3812 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3813 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3814 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3815 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3816 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3817 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3818 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3819 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3820 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3821 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3822 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3823 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3824 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3825 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3826 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3827 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3828 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3829 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3830 3831 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3832 #define IOERR_MISSING_CONTINUE 0x01 3833 #define IOERR_SEQUENCE_TIMEOUT 0x02 3834 #define IOERR_INTERNAL_ERROR 0x03 3835 #define IOERR_INVALID_RPI 0x04 3836 #define IOERR_NO_XRI 0x05 3837 #define IOERR_ILLEGAL_COMMAND 0x06 3838 #define IOERR_XCHG_DROPPED 0x07 3839 #define IOERR_ILLEGAL_FIELD 0x08 3840 #define IOERR_RPI_SUSPENDED 0x09 3841 #define IOERR_TOO_MANY_BUFFERS 0x0A 3842 #define IOERR_RCV_BUFFER_WAITING 0x0B 3843 #define IOERR_NO_CONNECTION 0x0C 3844 #define IOERR_TX_DMA_FAILED 0x0D 3845 #define IOERR_RX_DMA_FAILED 0x0E 3846 #define IOERR_ILLEGAL_FRAME 0x0F 3847 #define IOERR_EXTRA_DATA 0x10 3848 #define IOERR_NO_RESOURCES 0x11 3849 #define IOERR_RESERVED 0x12 3850 #define IOERR_ILLEGAL_LENGTH 0x13 3851 #define IOERR_UNSUPPORTED_FEATURE 0x14 3852 #define IOERR_ABORT_IN_PROGRESS 0x15 3853 #define IOERR_ABORT_REQUESTED 0x16 3854 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3855 #define IOERR_LOOP_OPEN_FAILURE 0x18 3856 #define IOERR_RING_RESET 0x19 3857 #define IOERR_LINK_DOWN 0x1A 3858 #define IOERR_CORRUPTED_DATA 0x1B 3859 #define IOERR_CORRUPTED_RPI 0x1C 3860 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3861 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3862 #define IOERR_DUP_FRAME 0x1F 3863 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3864 #define IOERR_BAD_HOST_ADDRESS 0x21 3865 #define IOERR_RCV_HDRBUF_WAITING 0x22 3866 #define IOERR_MISSING_HDR_BUFFER 0x23 3867 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3868 #define IOERR_ABORTMULT_REQUESTED 0x25 3869 #define IOERR_BUFFER_SHORTAGE 0x28 3870 #define IOERR_DEFAULT 0x29 3871 #define IOERR_CNT 0x2A 3872 #define IOERR_SLER_FAILURE 0x46 3873 #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3874 #define IOERR_SLER_REC_RJT_ERR 0x48 3875 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3876 #define IOERR_SLER_SRR_RJT_ERR 0x4A 3877 #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3878 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3879 #define IOERR_SLER_ABTS_ERR 0x4E 3880 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3881 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3882 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3883 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3884 #define IOERR_DRVR_MASK 0x100 3885 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3886 #define IOERR_SLI_BRESET 0x102 3887 #define IOERR_SLI_ABORTED 0x103 3888 #define IOERR_PARAM_MASK 0x1ff 3889 } PARM_ERR; 3890 3891 typedef union { 3892 struct { 3893 #ifdef __BIG_ENDIAN_BITFIELD 3894 uint8_t Rctl; /* R_CTL field */ 3895 uint8_t Type; /* TYPE field */ 3896 uint8_t Dfctl; /* DF_CTL field */ 3897 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3898 #else /* __LITTLE_ENDIAN_BITFIELD */ 3899 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3900 uint8_t Dfctl; /* DF_CTL field */ 3901 uint8_t Type; /* TYPE field */ 3902 uint8_t Rctl; /* R_CTL field */ 3903 #endif 3904 3905 #define BC 0x02 /* Broadcast Received - Fctl */ 3906 #define SI 0x04 /* Sequence Initiative */ 3907 #define LA 0x08 /* Ignore Link Attention state */ 3908 #define LS 0x80 /* Last Sequence */ 3909 } hcsw; 3910 uint32_t reserved; 3911 } WORD5; 3912 3913 /* IOCB Command template for a generic response */ 3914 typedef struct { 3915 uint32_t reserved[4]; 3916 PARM_ERR perr; 3917 } GENERIC_RSP; 3918 3919 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3920 typedef struct { 3921 struct ulp_bde xrsqbde[2]; 3922 uint32_t xrsqRo; /* Starting Relative Offset */ 3923 WORD5 w5; /* Header control/status word */ 3924 } XR_SEQ_FIELDS; 3925 3926 /* IOCB Command template for ELS_REQUEST */ 3927 typedef struct { 3928 struct ulp_bde elsReq; 3929 struct ulp_bde elsRsp; 3930 3931 #ifdef __BIG_ENDIAN_BITFIELD 3932 uint32_t word4Rsvd:7; 3933 uint32_t fl:1; 3934 uint32_t myID:24; 3935 uint32_t word5Rsvd:8; 3936 uint32_t remoteID:24; 3937 #else /* __LITTLE_ENDIAN_BITFIELD */ 3938 uint32_t myID:24; 3939 uint32_t fl:1; 3940 uint32_t word4Rsvd:7; 3941 uint32_t remoteID:24; 3942 uint32_t word5Rsvd:8; 3943 #endif 3944 } ELS_REQUEST; 3945 3946 /* IOCB Command template for RCV_ELS_REQ */ 3947 typedef struct { 3948 struct ulp_bde elsReq[2]; 3949 uint32_t parmRo; 3950 3951 #ifdef __BIG_ENDIAN_BITFIELD 3952 uint32_t word5Rsvd:8; 3953 uint32_t remoteID:24; 3954 #else /* __LITTLE_ENDIAN_BITFIELD */ 3955 uint32_t remoteID:24; 3956 uint32_t word5Rsvd:8; 3957 #endif 3958 } RCV_ELS_REQ; 3959 3960 /* IOCB Command template for ABORT / CLOSE_XRI */ 3961 typedef struct { 3962 uint32_t rsvd[3]; 3963 uint32_t abortType; 3964 #define ABORT_TYPE_ABTX 0x00000000 3965 #define ABORT_TYPE_ABTS 0x00000001 3966 uint32_t parm; 3967 #ifdef __BIG_ENDIAN_BITFIELD 3968 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3969 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3970 #else /* __LITTLE_ENDIAN_BITFIELD */ 3971 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3972 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3973 #endif 3974 } AC_XRI; 3975 3976 /* IOCB Command template for ABORT_MXRI64 */ 3977 typedef struct { 3978 uint32_t rsvd[3]; 3979 uint32_t abortType; 3980 uint32_t parm; 3981 uint32_t iotag32; 3982 } A_MXRI64; 3983 3984 /* IOCB Command template for GET_RPI */ 3985 typedef struct { 3986 uint32_t rsvd[4]; 3987 uint32_t parmRo; 3988 #ifdef __BIG_ENDIAN_BITFIELD 3989 uint32_t word5Rsvd:8; 3990 uint32_t remoteID:24; 3991 #else /* __LITTLE_ENDIAN_BITFIELD */ 3992 uint32_t remoteID:24; 3993 uint32_t word5Rsvd:8; 3994 #endif 3995 } GET_RPI; 3996 3997 /* IOCB Command template for all FCP Initiator commands */ 3998 typedef struct { 3999 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 4000 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 4001 uint32_t fcpi_parm; 4002 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 4003 } FCPI_FIELDS; 4004 4005 /* IOCB Command template for all FCP Target commands */ 4006 typedef struct { 4007 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 4008 uint32_t fcpt_Offset; 4009 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 4010 } FCPT_FIELDS; 4011 4012 /* SLI-2 IOCB structure definitions */ 4013 4014 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 4015 typedef struct { 4016 ULP_BDL bdl; 4017 uint32_t xrsqRo; /* Starting Relative Offset */ 4018 WORD5 w5; /* Header control/status word */ 4019 } XMT_SEQ_FIELDS64; 4020 4021 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */ 4022 #define xmit_els_remoteID xrsqRo 4023 4024 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 4025 typedef struct { 4026 struct ulp_bde64 rcvBde; 4027 uint32_t rsvd1; 4028 uint32_t xrsqRo; /* Starting Relative Offset */ 4029 WORD5 w5; /* Header control/status word */ 4030 } RCV_SEQ_FIELDS64; 4031 4032 /* IOCB Command template for ELS_REQUEST64 */ 4033 typedef struct { 4034 ULP_BDL bdl; 4035 #ifdef __BIG_ENDIAN_BITFIELD 4036 uint32_t word4Rsvd:7; 4037 uint32_t fl:1; 4038 uint32_t myID:24; 4039 uint32_t word5Rsvd:8; 4040 uint32_t remoteID:24; 4041 #else /* __LITTLE_ENDIAN_BITFIELD */ 4042 uint32_t myID:24; 4043 uint32_t fl:1; 4044 uint32_t word4Rsvd:7; 4045 uint32_t remoteID:24; 4046 uint32_t word5Rsvd:8; 4047 #endif 4048 } ELS_REQUEST64; 4049 4050 /* IOCB Command template for GEN_REQUEST64 */ 4051 typedef struct { 4052 ULP_BDL bdl; 4053 uint32_t xrsqRo; /* Starting Relative Offset */ 4054 WORD5 w5; /* Header control/status word */ 4055 } GEN_REQUEST64; 4056 4057 /* IOCB Command template for RCV_ELS_REQ64 */ 4058 typedef struct { 4059 struct ulp_bde64 elsReq; 4060 uint32_t rcvd1; 4061 uint32_t parmRo; 4062 4063 #ifdef __BIG_ENDIAN_BITFIELD 4064 uint32_t word5Rsvd:8; 4065 uint32_t remoteID:24; 4066 #else /* __LITTLE_ENDIAN_BITFIELD */ 4067 uint32_t remoteID:24; 4068 uint32_t word5Rsvd:8; 4069 #endif 4070 } RCV_ELS_REQ64; 4071 4072 /* IOCB Command template for RCV_SEQ64 */ 4073 struct rcv_seq64 { 4074 struct ulp_bde64 elsReq; 4075 uint32_t hbq_1; 4076 uint32_t parmRo; 4077 #ifdef __BIG_ENDIAN_BITFIELD 4078 uint32_t rctl:8; 4079 uint32_t type:8; 4080 uint32_t dfctl:8; 4081 uint32_t ls:1; 4082 uint32_t fs:1; 4083 uint32_t rsvd2:3; 4084 uint32_t si:1; 4085 uint32_t bc:1; 4086 uint32_t rsvd3:1; 4087 #else /* __LITTLE_ENDIAN_BITFIELD */ 4088 uint32_t rsvd3:1; 4089 uint32_t bc:1; 4090 uint32_t si:1; 4091 uint32_t rsvd2:3; 4092 uint32_t fs:1; 4093 uint32_t ls:1; 4094 uint32_t dfctl:8; 4095 uint32_t type:8; 4096 uint32_t rctl:8; 4097 #endif 4098 }; 4099 4100 /* IOCB Command template for all 64 bit FCP Initiator commands */ 4101 typedef struct { 4102 ULP_BDL bdl; 4103 uint32_t fcpi_parm; 4104 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 4105 } FCPI_FIELDS64; 4106 4107 /* IOCB Command template for all 64 bit FCP Target commands */ 4108 typedef struct { 4109 ULP_BDL bdl; 4110 uint32_t fcpt_Offset; 4111 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 4112 } FCPT_FIELDS64; 4113 4114 /* IOCB Command template for Async Status iocb commands */ 4115 typedef struct { 4116 uint32_t rsvd[4]; 4117 uint32_t param; 4118 #ifdef __BIG_ENDIAN_BITFIELD 4119 uint16_t evt_code; /* High order bits word 5 */ 4120 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 4121 #else /* __LITTLE_ENDIAN_BITFIELD */ 4122 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 4123 uint16_t evt_code; /* Low order bits word 5 */ 4124 #endif 4125 } ASYNCSTAT_FIELDS; 4126 #define ASYNC_TEMP_WARN 0x100 4127 #define ASYNC_TEMP_SAFE 0x101 4128 #define ASYNC_STATUS_CN 0x102 4129 4130 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 4131 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 4132 4133 struct rcv_sli3 { 4134 #ifdef __BIG_ENDIAN_BITFIELD 4135 uint16_t ox_id; 4136 uint16_t seq_cnt; 4137 4138 uint16_t vpi; 4139 uint16_t word9Rsvd; 4140 #else /* __LITTLE_ENDIAN */ 4141 uint16_t seq_cnt; 4142 uint16_t ox_id; 4143 4144 uint16_t word9Rsvd; 4145 uint16_t vpi; 4146 #endif 4147 uint32_t word10Rsvd; 4148 uint32_t acc_len; /* accumulated length */ 4149 struct ulp_bde64 bde2; 4150 }; 4151 4152 /* Structure used for a single HBQ entry */ 4153 struct lpfc_hbq_entry { 4154 struct ulp_bde64 bde; 4155 uint32_t buffer_tag; 4156 }; 4157 4158 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 4159 typedef struct { 4160 struct lpfc_hbq_entry buff; 4161 uint32_t rsvd; 4162 uint32_t rsvd1; 4163 } QUE_XRI64_CX_FIELDS; 4164 4165 struct que_xri64cx_ext_fields { 4166 uint32_t iotag64_low; 4167 uint32_t iotag64_high; 4168 uint32_t ebde_count; 4169 uint32_t rsvd; 4170 struct lpfc_hbq_entry buff[5]; 4171 }; 4172 4173 struct sli3_bg_fields { 4174 uint32_t filler[6]; /* word 8-13 in IOCB */ 4175 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 4176 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 4177 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 4178 #define BGS_BIDIR_BG_PROF_SHIFT 24 4179 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 4180 #define BGS_BIDIR_ERR_COND_SHIFT 16 4181 #define BGS_BG_PROFILE_MASK 0x0000ff00 4182 #define BGS_BG_PROFILE_SHIFT 8 4183 #define BGS_INVALID_PROF_MASK 0x00000020 4184 #define BGS_INVALID_PROF_SHIFT 5 4185 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 4186 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 4187 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 4188 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 4189 #define BGS_REFTAG_ERR_MASK 0x00000004 4190 #define BGS_REFTAG_ERR_SHIFT 2 4191 #define BGS_APPTAG_ERR_MASK 0x00000002 4192 #define BGS_APPTAG_ERR_SHIFT 1 4193 #define BGS_GUARD_ERR_MASK 0x00000001 4194 #define BGS_GUARD_ERR_SHIFT 0 4195 uint32_t bgstat; /* word 15 - BlockGuard Status */ 4196 }; 4197 4198 static inline uint32_t 4199 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 4200 { 4201 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 4202 BGS_BIDIR_BG_PROF_SHIFT; 4203 } 4204 4205 static inline uint32_t 4206 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 4207 { 4208 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 4209 BGS_BIDIR_ERR_COND_SHIFT; 4210 } 4211 4212 static inline uint32_t 4213 lpfc_bgs_get_bg_prof(uint32_t bgstat) 4214 { 4215 return (bgstat & BGS_BG_PROFILE_MASK) >> 4216 BGS_BG_PROFILE_SHIFT; 4217 } 4218 4219 static inline uint32_t 4220 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 4221 { 4222 return (bgstat & BGS_INVALID_PROF_MASK) >> 4223 BGS_INVALID_PROF_SHIFT; 4224 } 4225 4226 static inline uint32_t 4227 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 4228 { 4229 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 4230 BGS_UNINIT_DIF_BLOCK_SHIFT; 4231 } 4232 4233 static inline uint32_t 4234 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 4235 { 4236 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 4237 BGS_HI_WATER_MARK_PRESENT_SHIFT; 4238 } 4239 4240 static inline uint32_t 4241 lpfc_bgs_get_reftag_err(uint32_t bgstat) 4242 { 4243 return (bgstat & BGS_REFTAG_ERR_MASK) >> 4244 BGS_REFTAG_ERR_SHIFT; 4245 } 4246 4247 static inline uint32_t 4248 lpfc_bgs_get_apptag_err(uint32_t bgstat) 4249 { 4250 return (bgstat & BGS_APPTAG_ERR_MASK) >> 4251 BGS_APPTAG_ERR_SHIFT; 4252 } 4253 4254 static inline uint32_t 4255 lpfc_bgs_get_guard_err(uint32_t bgstat) 4256 { 4257 return (bgstat & BGS_GUARD_ERR_MASK) >> 4258 BGS_GUARD_ERR_SHIFT; 4259 } 4260 4261 #define LPFC_EXT_DATA_BDE_COUNT 3 4262 struct fcp_irw_ext { 4263 uint32_t io_tag64_low; 4264 uint32_t io_tag64_high; 4265 #ifdef __BIG_ENDIAN_BITFIELD 4266 uint8_t reserved1; 4267 uint8_t reserved2; 4268 uint8_t reserved3; 4269 uint8_t ebde_count; 4270 #else /* __LITTLE_ENDIAN */ 4271 uint8_t ebde_count; 4272 uint8_t reserved3; 4273 uint8_t reserved2; 4274 uint8_t reserved1; 4275 #endif 4276 uint32_t reserved4; 4277 struct ulp_bde64 rbde; /* response bde */ 4278 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 4279 uint8_t icd[32]; /* immediate command data (32 bytes) */ 4280 }; 4281 4282 typedef struct _IOCB { /* IOCB structure */ 4283 union { 4284 GENERIC_RSP grsp; /* Generic response */ 4285 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 4286 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 4287 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 4288 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 4289 A_MXRI64 amxri; /* abort multiple xri command overlay */ 4290 GET_RPI getrpi; /* GET_RPI template */ 4291 FCPI_FIELDS fcpi; /* FCP Initiator template */ 4292 FCPT_FIELDS fcpt; /* FCP target template */ 4293 4294 /* SLI-2 structures */ 4295 4296 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 4297 * bde_64s */ 4298 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 4299 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 4300 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 4301 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 4302 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 4303 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 4304 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 4305 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 4306 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 4307 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 4308 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 4309 } un; 4310 union { 4311 struct { 4312 #ifdef __BIG_ENDIAN_BITFIELD 4313 uint16_t ulpContext; /* High order bits word 6 */ 4314 uint16_t ulpIoTag; /* Low order bits word 6 */ 4315 #else /* __LITTLE_ENDIAN_BITFIELD */ 4316 uint16_t ulpIoTag; /* Low order bits word 6 */ 4317 uint16_t ulpContext; /* High order bits word 6 */ 4318 #endif 4319 } t1; 4320 struct { 4321 #ifdef __BIG_ENDIAN_BITFIELD 4322 uint16_t ulpContext; /* High order bits word 6 */ 4323 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4324 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4325 #else /* __LITTLE_ENDIAN_BITFIELD */ 4326 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4327 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4328 uint16_t ulpContext; /* High order bits word 6 */ 4329 #endif 4330 } t2; 4331 } un1; 4332 #define ulpContext un1.t1.ulpContext 4333 #define ulpIoTag un1.t1.ulpIoTag 4334 #define ulpIoTag0 un1.t2.ulpIoTag0 4335 4336 #ifdef __BIG_ENDIAN_BITFIELD 4337 uint32_t ulpTimeout:8; 4338 uint32_t ulpXS:1; 4339 uint32_t ulpFCP2Rcvy:1; 4340 uint32_t ulpPU:2; 4341 uint32_t ulpIr:1; 4342 uint32_t ulpClass:3; 4343 uint32_t ulpCommand:8; 4344 uint32_t ulpStatus:4; 4345 uint32_t ulpBdeCount:2; 4346 uint32_t ulpLe:1; 4347 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4348 #else /* __LITTLE_ENDIAN_BITFIELD */ 4349 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4350 uint32_t ulpLe:1; 4351 uint32_t ulpBdeCount:2; 4352 uint32_t ulpStatus:4; 4353 uint32_t ulpCommand:8; 4354 uint32_t ulpClass:3; 4355 uint32_t ulpIr:1; 4356 uint32_t ulpPU:2; 4357 uint32_t ulpFCP2Rcvy:1; 4358 uint32_t ulpXS:1; 4359 uint32_t ulpTimeout:8; 4360 #endif 4361 4362 union { 4363 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 4364 4365 /* words 8-31 used for que_xri_cx iocb */ 4366 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 4367 struct fcp_irw_ext fcp_ext; 4368 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 4369 4370 /* words 8-15 for BlockGuard */ 4371 struct sli3_bg_fields sli3_bg; 4372 } unsli3; 4373 4374 #define ulpCt_h ulpXS 4375 #define ulpCt_l ulpFCP2Rcvy 4376 4377 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 4378 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 4379 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 4380 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 4381 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 4382 #define PARM_NPIV_DID 3 4383 #define CLASS1 0 /* Class 1 */ 4384 #define CLASS2 1 /* Class 2 */ 4385 #define CLASS3 2 /* Class 3 */ 4386 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 4387 4388 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 4389 #define IOSTAT_FCP_RSP_ERROR 0x1 4390 #define IOSTAT_REMOTE_STOP 0x2 4391 #define IOSTAT_LOCAL_REJECT 0x3 4392 #define IOSTAT_NPORT_RJT 0x4 4393 #define IOSTAT_FABRIC_RJT 0x5 4394 #define IOSTAT_NPORT_BSY 0x6 4395 #define IOSTAT_FABRIC_BSY 0x7 4396 #define IOSTAT_INTERMED_RSP 0x8 4397 #define IOSTAT_LS_RJT 0x9 4398 #define IOSTAT_BA_RJT 0xA 4399 #define IOSTAT_RSVD1 0xB 4400 #define IOSTAT_RSVD2 0xC 4401 #define IOSTAT_RSVD3 0xD 4402 #define IOSTAT_RSVD4 0xE 4403 #define IOSTAT_NEED_BUFFER 0xF 4404 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 4405 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 4406 #define IOSTAT_CNT 0x11 4407 4408 } IOCB_t; 4409 4410 4411 #define SLI1_SLIM_SIZE (4 * 1024) 4412 4413 /* Up to 498 IOCBs will fit into 16k 4414 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 4415 */ 4416 #define SLI2_SLIM_SIZE (64 * 1024) 4417 4418 /* Maximum IOCBs that will fit in SLI2 slim */ 4419 #define MAX_SLI2_IOCB 498 4420 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 4421 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 4422 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 4423 4424 /* HBQ entries are 4 words each = 4k */ 4425 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 4426 lpfc_sli_hbq_count()) 4427 4428 struct lpfc_sli2_slim { 4429 MAILBOX_t mbx; 4430 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 4431 PCB_t pcb; 4432 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 4433 }; 4434 4435 /* 4436 * This function checks PCI device to allow special handling for LC HBAs. 4437 * 4438 * Parameters: 4439 * device : struct pci_dev 's device field 4440 * 4441 * return 1 => TRUE 4442 * 0 => FALSE 4443 */ 4444 static inline int 4445 lpfc_is_LC_HBA(unsigned short device) 4446 { 4447 if ((device == PCI_DEVICE_ID_TFLY) || 4448 (device == PCI_DEVICE_ID_PFLY) || 4449 (device == PCI_DEVICE_ID_LP101) || 4450 (device == PCI_DEVICE_ID_BMID) || 4451 (device == PCI_DEVICE_ID_BSMB) || 4452 (device == PCI_DEVICE_ID_ZMID) || 4453 (device == PCI_DEVICE_ID_ZSMB) || 4454 (device == PCI_DEVICE_ID_SAT_MID) || 4455 (device == PCI_DEVICE_ID_SAT_SMB) || 4456 (device == PCI_DEVICE_ID_RFLY)) 4457 return 1; 4458 else 4459 return 0; 4460 } 4461 4462 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 4463