1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #define FDMI_DID 0xfffffaU 24 #define NameServer_DID 0xfffffcU 25 #define Fabric_Cntl_DID 0xfffffdU 26 #define Fabric_DID 0xfffffeU 27 #define Bcast_DID 0xffffffU 28 #define Mask_DID 0xffffffU 29 #define CT_DID_MASK 0xffff00U 30 #define Fabric_DID_MASK 0xfff000U 31 #define WELL_KNOWN_DID_MASK 0xfffff0U 32 33 #define PT2PT_LocalID 1 34 #define PT2PT_RemoteID 2 35 36 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 37 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 38 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */ 39 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 40 41 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 42 0 */ 43 44 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 45 46 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 47 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 48 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 49 50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 58 #define SLI2_IOCB_CMD_R3_ENTRIES 0 59 #define SLI2_IOCB_RSP_R3_ENTRIES 0 60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 62 63 #define SLI2_IOCB_CMD_SIZE 32 64 #define SLI2_IOCB_RSP_SIZE 32 65 #define SLI3_IOCB_CMD_SIZE 128 66 #define SLI3_IOCB_RSP_SIZE 64 67 68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 70 71 /* vendor ID used in SCSI netlink calls */ 72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 73 74 #define FW_REV_STR_SIZE 32 75 /* Common Transport structures and definitions */ 76 77 union CtRevisionId { 78 /* Structure is in Big Endian format */ 79 struct { 80 uint32_t Revision:8; 81 uint32_t InId:24; 82 } bits; 83 uint32_t word; 84 }; 85 86 union CtCommandResponse { 87 /* Structure is in Big Endian format */ 88 struct { 89 uint32_t CmdRsp:16; 90 uint32_t Size:16; 91 } bits; 92 uint32_t word; 93 }; 94 95 /* FC4 Feature bits for RFF_ID */ 96 #define FC4_FEATURE_TARGET 0x1 97 #define FC4_FEATURE_INIT 0x2 98 #define FC4_FEATURE_NVME_DISC 0x4 99 100 struct lpfc_sli_ct_request { 101 /* Structure is in Big Endian format */ 102 union CtRevisionId RevisionId; 103 uint8_t FsType; 104 uint8_t FsSubType; 105 uint8_t Options; 106 uint8_t Rsrvd1; 107 union CtCommandResponse CommandResponse; 108 uint8_t Rsrvd2; 109 uint8_t ReasonCode; 110 uint8_t Explanation; 111 uint8_t VendorUnique; 112 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */ 113 114 union { 115 uint32_t PortID; 116 struct gid { 117 uint8_t PortType; /* for GID_PT requests */ 118 #define GID_PT_N_PORT 1 119 uint8_t DomainScope; 120 uint8_t AreaScope; 121 uint8_t Fc4Type; /* for GID_FT requests */ 122 } gid; 123 struct gid_ff { 124 uint8_t Flags; 125 uint8_t DomainScope; 126 uint8_t AreaScope; 127 uint8_t rsvd1; 128 uint8_t rsvd2; 129 uint8_t rsvd3; 130 uint8_t Fc4FBits; 131 uint8_t Fc4Type; 132 } gid_ff; 133 struct rft { 134 uint32_t PortId; /* For RFT_ID requests */ 135 136 #ifdef __BIG_ENDIAN_BITFIELD 137 uint32_t rsvd0:16; 138 uint32_t rsvd1:7; 139 uint32_t fcpReg:1; /* Type 8 */ 140 uint32_t rsvd2:2; 141 uint32_t ipReg:1; /* Type 5 */ 142 uint32_t rsvd3:5; 143 #else /* __LITTLE_ENDIAN_BITFIELD */ 144 uint32_t rsvd0:16; 145 uint32_t fcpReg:1; /* Type 8 */ 146 uint32_t rsvd1:7; 147 uint32_t rsvd3:5; 148 uint32_t ipReg:1; /* Type 5 */ 149 uint32_t rsvd2:2; 150 #endif 151 152 uint32_t rsvd[7]; 153 } rft; 154 struct rnn { 155 uint32_t PortId; /* For RNN_ID requests */ 156 uint8_t wwnn[8]; 157 } rnn; 158 struct rsnn { /* For RSNN_ID requests */ 159 uint8_t wwnn[8]; 160 uint8_t len; 161 uint8_t symbname[255]; 162 } rsnn; 163 struct da_id { /* For DA_ID requests */ 164 uint32_t port_id; 165 } da_id; 166 struct rspn { /* For RSPN_ID requests */ 167 uint32_t PortId; 168 uint8_t len; 169 uint8_t symbname[255]; 170 } rspn; 171 struct gff { 172 uint32_t PortId; 173 } gff; 174 struct gff_acc { 175 uint8_t fbits[128]; 176 } gff_acc; 177 struct gft { 178 uint32_t PortId; 179 } gft; 180 struct gft_acc { 181 uint32_t fc4_types[8]; 182 } gft_acc; 183 #define FCP_TYPE_FEATURE_OFFSET 7 184 struct rff { 185 uint32_t PortId; 186 uint8_t reserved[2]; 187 uint8_t fbits; 188 uint8_t type_code; /* type=8 for FCP */ 189 } rff; 190 } un; 191 }; 192 193 #define LPFC_MAX_CT_SIZE (60 * 4096) 194 195 #define SLI_CT_REVISION 1 196 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 197 sizeof(struct gid)) 198 #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 199 sizeof(struct gid_ff)) 200 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 201 sizeof(struct gff)) 202 #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 203 sizeof(struct gft)) 204 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 205 sizeof(struct rft)) 206 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 207 sizeof(struct rff)) 208 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 209 sizeof(struct rnn)) 210 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 211 sizeof(struct rsnn)) 212 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 213 sizeof(struct da_id)) 214 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 215 sizeof(struct rspn)) 216 217 /* 218 * FsType Definitions 219 */ 220 221 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 222 #define SLI_CT_TIME_SERVICE 0xFB 223 #define SLI_CT_DIRECTORY_SERVICE 0xFC 224 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 225 226 /* 227 * Directory Service Subtypes 228 */ 229 230 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 231 232 /* 233 * Response Codes 234 */ 235 236 #define SLI_CT_RESPONSE_FS_RJT 0x8001 237 #define SLI_CT_RESPONSE_FS_ACC 0x8002 238 239 /* 240 * Reason Codes 241 */ 242 243 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 244 #define SLI_CT_INVALID_COMMAND 0x01 245 #define SLI_CT_INVALID_VERSION 0x02 246 #define SLI_CT_LOGICAL_ERROR 0x03 247 #define SLI_CT_INVALID_IU_SIZE 0x04 248 #define SLI_CT_LOGICAL_BUSY 0x05 249 #define SLI_CT_PROTOCOL_ERROR 0x07 250 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 251 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 252 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 253 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 254 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 255 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 256 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 257 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 258 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 259 #define SLI_CT_VENDOR_UNIQUE 0xff 260 261 /* 262 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 263 */ 264 265 #define SLI_CT_NO_PORT_ID 0x01 266 #define SLI_CT_NO_PORT_NAME 0x02 267 #define SLI_CT_NO_NODE_NAME 0x03 268 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 269 #define SLI_CT_NO_IP_ADDRESS 0x05 270 #define SLI_CT_NO_IPA 0x06 271 #define SLI_CT_NO_FC4_TYPES 0x07 272 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 273 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 274 #define SLI_CT_NO_PORT_TYPE 0x0A 275 #define SLI_CT_ACCESS_DENIED 0x10 276 #define SLI_CT_INVALID_PORT_ID 0x11 277 #define SLI_CT_DATABASE_EMPTY 0x12 278 #define SLI_CT_APP_ID_NOT_AVAILABLE 0x40 279 280 /* 281 * Name Server Command Codes 282 */ 283 284 #define SLI_CTNS_GA_NXT 0x0100 285 #define SLI_CTNS_GPN_ID 0x0112 286 #define SLI_CTNS_GNN_ID 0x0113 287 #define SLI_CTNS_GCS_ID 0x0114 288 #define SLI_CTNS_GFT_ID 0x0117 289 #define SLI_CTNS_GSPN_ID 0x0118 290 #define SLI_CTNS_GPT_ID 0x011A 291 #define SLI_CTNS_GFF_ID 0x011F 292 #define SLI_CTNS_GID_PN 0x0121 293 #define SLI_CTNS_GID_NN 0x0131 294 #define SLI_CTNS_GIP_NN 0x0135 295 #define SLI_CTNS_GIPA_NN 0x0136 296 #define SLI_CTNS_GSNN_NN 0x0139 297 #define SLI_CTNS_GNN_IP 0x0153 298 #define SLI_CTNS_GIPA_IP 0x0156 299 #define SLI_CTNS_GID_FT 0x0171 300 #define SLI_CTNS_GID_FF 0x01F1 301 #define SLI_CTNS_GID_PT 0x01A1 302 #define SLI_CTNS_RPN_ID 0x0212 303 #define SLI_CTNS_RNN_ID 0x0213 304 #define SLI_CTNS_RCS_ID 0x0214 305 #define SLI_CTNS_RFT_ID 0x0217 306 #define SLI_CTNS_RSPN_ID 0x0218 307 #define SLI_CTNS_RPT_ID 0x021A 308 #define SLI_CTNS_RFF_ID 0x021F 309 #define SLI_CTNS_RIP_NN 0x0235 310 #define SLI_CTNS_RIPA_NN 0x0236 311 #define SLI_CTNS_RSNN_NN 0x0239 312 #define SLI_CTNS_DA_ID 0x0300 313 314 /* 315 * Port Types 316 */ 317 318 #define SLI_CTPT_N_PORT 0x01 319 #define SLI_CTPT_NL_PORT 0x02 320 #define SLI_CTPT_FNL_PORT 0x03 321 #define SLI_CTPT_IP 0x04 322 #define SLI_CTPT_FCP 0x08 323 #define SLI_CTPT_NVME 0x28 324 #define SLI_CTPT_NX_PORT 0x7F 325 #define SLI_CTPT_F_PORT 0x81 326 #define SLI_CTPT_FL_PORT 0x82 327 #define SLI_CTPT_E_PORT 0x84 328 329 #define SLI_CT_LAST_ENTRY 0x80000000 330 331 /* Fibre Channel Service Parameter definitions */ 332 333 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 334 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 335 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 336 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 337 338 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 339 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 340 #define FC_PH3 0x20 /* FC-PH-3 version */ 341 342 #define FF_FRAME_SIZE 2048 343 344 struct lpfc_name { 345 union { 346 struct { 347 #ifdef __BIG_ENDIAN_BITFIELD 348 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 349 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 350 8:11 of IEEE ext */ 351 #else /* __LITTLE_ENDIAN_BITFIELD */ 352 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 353 8:11 of IEEE ext */ 354 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 355 #endif 356 357 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 358 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 359 #define NAME_FC_TYPE 0x3 /* FC native name type */ 360 #define NAME_IP_TYPE 0x4 /* IP address */ 361 #define NAME_CCITT_TYPE 0xC 362 #define NAME_CCITT_GR_TYPE 0xE 363 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 364 extended Lsb */ 365 uint8_t IEEE[6]; /* FC IEEE address */ 366 } s; 367 uint8_t wwn[8]; 368 uint64_t name; 369 } u; 370 }; 371 372 struct csp { 373 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 374 uint8_t fcphLow; 375 uint8_t bbCreditMsb; 376 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */ 377 378 /* 379 * Word 1 Bit 31 in common service parameter is overloaded. 380 * Word 1 Bit 31 in FLOGI request is multiple NPort request 381 * Word 1 Bit 31 in FLOGI response is clean address bit 382 */ 383 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 384 /* 385 * Word 1 Bit 30 in common service parameter is overloaded. 386 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 387 * Word 1 Bit 30 in PLOGI request is random offset 388 */ 389 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 390 /* 391 * Word 1 Bit 29 in common service parameter is overloaded. 392 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment 393 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level 394 */ 395 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */ 396 #ifdef __BIG_ENDIAN_BITFIELD 397 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 398 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 399 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 400 uint16_t fPort:1; /* FC Word 1, bit 28 */ 401 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 402 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 403 uint16_t multicast:1; /* FC Word 1, bit 25 */ 404 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ 405 406 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ 407 uint16_t simplex:1; /* FC Word 1, bit 22 */ 408 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 409 uint16_t dhd:1; /* FC Word 1, bit 18 */ 410 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 411 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 412 #else /* __LITTLE_ENDIAN_BITFIELD */ 413 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ 414 uint16_t multicast:1; /* FC Word 1, bit 25 */ 415 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 416 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 417 uint16_t fPort:1; /* FC Word 1, bit 28 */ 418 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 419 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 420 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 421 422 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 423 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 424 uint16_t dhd:1; /* FC Word 1, bit 18 */ 425 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 426 uint16_t simplex:1; /* FC Word 1, bit 22 */ 427 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ 428 #endif 429 430 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 431 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 432 union { 433 struct { 434 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 435 436 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 437 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 438 439 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 440 } nPort; 441 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 442 } w2; 443 444 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 445 }; 446 447 struct class_parms { 448 #ifdef __BIG_ENDIAN_BITFIELD 449 uint8_t classValid:1; /* FC Word 0, bit 31 */ 450 uint8_t intermix:1; /* FC Word 0, bit 30 */ 451 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 452 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 453 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 454 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 455 #else /* __LITTLE_ENDIAN_BITFIELD */ 456 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 457 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 458 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 459 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 460 uint8_t intermix:1; /* FC Word 0, bit 30 */ 461 uint8_t classValid:1; /* FC Word 0, bit 31 */ 462 463 #endif 464 465 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 466 467 #ifdef __BIG_ENDIAN_BITFIELD 468 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 469 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 470 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 471 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 472 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 473 #else /* __LITTLE_ENDIAN_BITFIELD */ 474 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 475 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 476 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 477 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 478 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 479 #endif 480 481 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 482 483 #ifdef __BIG_ENDIAN_BITFIELD 484 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 485 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 486 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 487 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 488 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 489 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 490 #else /* __LITTLE_ENDIAN_BITFIELD */ 491 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 492 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 493 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 494 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 495 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 496 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 497 #endif 498 499 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 500 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 501 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 502 503 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 504 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 505 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 506 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 507 508 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 509 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 510 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 511 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 512 }; 513 514 #define FAPWWN_KEY_VENDOR 0x42524344 /*valid vendor version fawwpn key*/ 515 516 struct serv_parm { /* Structure is in Big Endian format */ 517 struct csp cmn; 518 struct lpfc_name portName; 519 struct lpfc_name nodeName; 520 struct class_parms cls1; 521 struct class_parms cls2; 522 struct class_parms cls3; 523 struct class_parms cls4; 524 union { 525 uint8_t vendorVersion[16]; 526 struct { 527 uint32_t vid; 528 #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */ 529 uint32_t flags; 530 #define LPFC_VV_SUPPRESS_RSP 1 531 } vv; 532 } un; 533 }; 534 535 /* 536 * Virtual Fabric Tagging Header 537 */ 538 struct fc_vft_header { 539 uint32_t word0; 540 #define fc_vft_hdr_r_ctl_SHIFT 24 541 #define fc_vft_hdr_r_ctl_MASK 0xFF 542 #define fc_vft_hdr_r_ctl_WORD word0 543 #define fc_vft_hdr_ver_SHIFT 22 544 #define fc_vft_hdr_ver_MASK 0x3 545 #define fc_vft_hdr_ver_WORD word0 546 #define fc_vft_hdr_type_SHIFT 18 547 #define fc_vft_hdr_type_MASK 0xF 548 #define fc_vft_hdr_type_WORD word0 549 #define fc_vft_hdr_e_SHIFT 16 550 #define fc_vft_hdr_e_MASK 0x1 551 #define fc_vft_hdr_e_WORD word0 552 #define fc_vft_hdr_priority_SHIFT 13 553 #define fc_vft_hdr_priority_MASK 0x7 554 #define fc_vft_hdr_priority_WORD word0 555 #define fc_vft_hdr_vf_id_SHIFT 1 556 #define fc_vft_hdr_vf_id_MASK 0xFFF 557 #define fc_vft_hdr_vf_id_WORD word0 558 uint32_t word1; 559 #define fc_vft_hdr_hopct_SHIFT 24 560 #define fc_vft_hdr_hopct_MASK 0xFF 561 #define fc_vft_hdr_hopct_WORD word1 562 }; 563 564 #include <uapi/scsi/fc/fc_els.h> 565 566 /* 567 * Extended Link Service LS_COMMAND codes (Payload Word 0) 568 */ 569 #ifdef __BIG_ENDIAN_BITFIELD 570 #define ELS_CMD_MASK 0xffff0000 571 #define ELS_RSP_MASK 0xff000000 572 #define ELS_CMD_LS_RJT 0x01000000 573 #define ELS_CMD_ACC 0x02000000 574 #define ELS_CMD_PLOGI 0x03000000 575 #define ELS_CMD_FLOGI 0x04000000 576 #define ELS_CMD_LOGO 0x05000000 577 #define ELS_CMD_ABTX 0x06000000 578 #define ELS_CMD_RCS 0x07000000 579 #define ELS_CMD_RES 0x08000000 580 #define ELS_CMD_RSS 0x09000000 581 #define ELS_CMD_RSI 0x0A000000 582 #define ELS_CMD_ESTS 0x0B000000 583 #define ELS_CMD_ESTC 0x0C000000 584 #define ELS_CMD_ADVC 0x0D000000 585 #define ELS_CMD_RTV 0x0E000000 586 #define ELS_CMD_RLS 0x0F000000 587 #define ELS_CMD_ECHO 0x10000000 588 #define ELS_CMD_TEST 0x11000000 589 #define ELS_CMD_RRQ 0x12000000 590 #define ELS_CMD_REC 0x13000000 591 #define ELS_CMD_RDP 0x18000000 592 #define ELS_CMD_RDF 0x19000000 593 #define ELS_CMD_PRLI 0x20100014 594 #define ELS_CMD_NVMEPRLI 0x20140018 595 #define ELS_CMD_PRLO 0x21100014 596 #define ELS_CMD_PRLO_ACC 0x02100014 597 #define ELS_CMD_PDISC 0x50000000 598 #define ELS_CMD_FDISC 0x51000000 599 #define ELS_CMD_ADISC 0x52000000 600 #define ELS_CMD_FARP 0x54000000 601 #define ELS_CMD_FARPR 0x55000000 602 #define ELS_CMD_RPL 0x57000000 603 #define ELS_CMD_FAN 0x60000000 604 #define ELS_CMD_RSCN 0x61040000 605 #define ELS_CMD_RSCN_XMT 0x61040008 606 #define ELS_CMD_SCR 0x62000000 607 #define ELS_CMD_RNID 0x78000000 608 #define ELS_CMD_LIRR 0x7A000000 609 #define ELS_CMD_LCB 0x81000000 610 #define ELS_CMD_FPIN 0x16000000 611 #define ELS_CMD_EDC 0x17000000 612 #define ELS_CMD_QFPA 0xB0000000 613 #define ELS_CMD_UVEM 0xB1000000 614 #else /* __LITTLE_ENDIAN_BITFIELD */ 615 #define ELS_CMD_MASK 0xffff 616 #define ELS_RSP_MASK 0xff 617 #define ELS_CMD_LS_RJT 0x01 618 #define ELS_CMD_ACC 0x02 619 #define ELS_CMD_PLOGI 0x03 620 #define ELS_CMD_FLOGI 0x04 621 #define ELS_CMD_LOGO 0x05 622 #define ELS_CMD_ABTX 0x06 623 #define ELS_CMD_RCS 0x07 624 #define ELS_CMD_RES 0x08 625 #define ELS_CMD_RSS 0x09 626 #define ELS_CMD_RSI 0x0A 627 #define ELS_CMD_ESTS 0x0B 628 #define ELS_CMD_ESTC 0x0C 629 #define ELS_CMD_ADVC 0x0D 630 #define ELS_CMD_RTV 0x0E 631 #define ELS_CMD_RLS 0x0F 632 #define ELS_CMD_ECHO 0x10 633 #define ELS_CMD_TEST 0x11 634 #define ELS_CMD_RRQ 0x12 635 #define ELS_CMD_REC 0x13 636 #define ELS_CMD_RDP 0x18 637 #define ELS_CMD_RDF 0x19 638 #define ELS_CMD_PRLI 0x14001020 639 #define ELS_CMD_NVMEPRLI 0x18001420 640 #define ELS_CMD_PRLO 0x14001021 641 #define ELS_CMD_PRLO_ACC 0x14001002 642 #define ELS_CMD_PDISC 0x50 643 #define ELS_CMD_FDISC 0x51 644 #define ELS_CMD_ADISC 0x52 645 #define ELS_CMD_FARP 0x54 646 #define ELS_CMD_FARPR 0x55 647 #define ELS_CMD_RPL 0x57 648 #define ELS_CMD_FAN 0x60 649 #define ELS_CMD_RSCN 0x0461 650 #define ELS_CMD_RSCN_XMT 0x08000461 651 #define ELS_CMD_SCR 0x62 652 #define ELS_CMD_RNID 0x78 653 #define ELS_CMD_LIRR 0x7A 654 #define ELS_CMD_LCB 0x81 655 #define ELS_CMD_FPIN ELS_FPIN 656 #define ELS_CMD_EDC ELS_EDC 657 #define ELS_CMD_QFPA 0xB0 658 #define ELS_CMD_UVEM 0xB1 659 #endif 660 661 /* 662 * LS_RJT Payload Definition 663 */ 664 665 struct ls_rjt { /* Structure is in Big Endian format */ 666 union { 667 __be32 ls_rjt_error_be; 668 uint32_t lsRjtError; 669 struct { 670 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 671 672 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 673 /* LS_RJT reason codes */ 674 #define LSRJT_INVALID_CMD 0x01 675 #define LSRJT_LOGICAL_ERR 0x03 676 #define LSRJT_LOGICAL_BSY 0x05 677 #define LSRJT_PROTOCOL_ERR 0x07 678 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 679 #define LSRJT_CMD_UNSUPPORTED 0x0B 680 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 681 682 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 683 /* LS_RJT reason explanation */ 684 #define LSEXP_NOTHING_MORE 0x00 685 #define LSEXP_SPARM_OPTIONS 0x01 686 #define LSEXP_SPARM_ICTL 0x03 687 #define LSEXP_SPARM_RCTL 0x05 688 #define LSEXP_SPARM_RCV_SIZE 0x07 689 #define LSEXP_SPARM_CONCUR_SEQ 0x09 690 #define LSEXP_SPARM_CREDIT 0x0B 691 #define LSEXP_INVALID_PNAME 0x0D 692 #define LSEXP_INVALID_NNAME 0x0E 693 #define LSEXP_INVALID_CSP 0x0F 694 #define LSEXP_INVALID_ASSOC_HDR 0x11 695 #define LSEXP_ASSOC_HDR_REQ 0x13 696 #define LSEXP_INVALID_O_SID 0x15 697 #define LSEXP_INVALID_OX_RX 0x17 698 #define LSEXP_CMD_IN_PROGRESS 0x19 699 #define LSEXP_PORT_LOGIN_REQ 0x1E 700 #define LSEXP_INVALID_NPORT_ID 0x1F 701 #define LSEXP_INVALID_SEQ_ID 0x21 702 #define LSEXP_INVALID_XCHG 0x23 703 #define LSEXP_INACTIVE_XCHG 0x25 704 #define LSEXP_RQ_REQUIRED 0x27 705 #define LSEXP_OUT_OF_RESOURCE 0x29 706 #define LSEXP_CANT_GIVE_DATA 0x2A 707 #define LSEXP_REQ_UNSUPPORTED 0x2C 708 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 709 } b; 710 } un; 711 }; 712 713 /* 714 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 715 */ 716 717 typedef struct _LOGO { /* Structure is in Big Endian format */ 718 union { 719 uint32_t nPortId32; /* Access nPortId as a word */ 720 struct { 721 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 722 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 723 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 724 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 725 } b; 726 } un; 727 struct lpfc_name portName; /* N_port name field */ 728 } LOGO; 729 730 /* 731 * FCP Login (PRLI Request / ACC) Payload Definition 732 */ 733 734 #define PRLX_PAGE_LEN 0x10 735 #define TPRLO_PAGE_LEN 0x14 736 737 typedef struct _PRLI { /* Structure is in Big Endian format */ 738 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 739 740 #define PRLI_FCP_TYPE 0x08 741 #define PRLI_NVME_TYPE 0x28 742 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 743 744 #ifdef __BIG_ENDIAN_BITFIELD 745 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 746 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 747 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 748 749 /* ACC = imagePairEstablished */ 750 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 751 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 752 #else /* __LITTLE_ENDIAN_BITFIELD */ 753 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 754 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 755 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 756 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 757 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 758 /* ACC = imagePairEstablished */ 759 #endif 760 761 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 762 #define PRLI_NO_RESOURCES 0x2 763 #define PRLI_INIT_INCOMPLETE 0x3 764 #define PRLI_NO_SUCH_PA 0x4 765 #define PRLI_PREDEF_CONFIG 0x5 766 #define PRLI_PARTIAL_SUCCESS 0x6 767 #define PRLI_INVALID_PAGE_CNT 0x7 768 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 769 770 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 771 772 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 773 774 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 775 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 776 777 #ifdef __BIG_ENDIAN_BITFIELD 778 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 779 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 780 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 781 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 782 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 783 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 784 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 785 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 786 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 787 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 788 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 789 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 790 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 791 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 792 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 793 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 794 #else /* __LITTLE_ENDIAN_BITFIELD */ 795 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 796 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 797 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 798 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 799 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 800 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 801 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 802 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 803 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 804 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 805 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 806 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 807 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 808 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 809 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 810 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 811 #endif 812 } PRLI; 813 814 /* 815 * FCP Logout (PRLO Request / ACC) Payload Definition 816 */ 817 818 typedef struct _PRLO { /* Structure is in Big Endian format */ 819 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 820 821 #define PRLO_FCP_TYPE 0x08 822 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 823 824 #ifdef __BIG_ENDIAN_BITFIELD 825 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 826 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 827 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 828 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 829 #else /* __LITTLE_ENDIAN_BITFIELD */ 830 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 831 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 832 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 833 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 834 #endif 835 836 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 837 #define PRLO_NO_SUCH_IMAGE 0x4 838 #define PRLO_INVALID_PAGE_CNT 0x7 839 840 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 841 842 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 843 844 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 845 846 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 847 } PRLO; 848 849 typedef struct _ADISC { /* Structure is in Big Endian format */ 850 uint32_t hardAL_PA; 851 struct lpfc_name portName; 852 struct lpfc_name nodeName; 853 uint32_t DID; 854 } __packed ADISC; 855 856 typedef struct _FARP { /* Structure is in Big Endian format */ 857 uint32_t Mflags:8; 858 uint32_t Odid:24; 859 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 860 action */ 861 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 862 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 863 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 864 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 865 supported */ 866 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 867 supported */ 868 uint32_t Rflags:8; 869 uint32_t Rdid:24; 870 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 871 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 872 struct lpfc_name OportName; 873 struct lpfc_name OnodeName; 874 struct lpfc_name RportName; 875 struct lpfc_name RnodeName; 876 uint8_t Oipaddr[16]; 877 uint8_t Ripaddr[16]; 878 } FARP; 879 880 typedef struct _FAN { /* Structure is in Big Endian format */ 881 uint32_t Fdid; 882 struct lpfc_name FportName; 883 struct lpfc_name FnodeName; 884 } __packed FAN; 885 886 typedef struct _SCR { /* Structure is in Big Endian format */ 887 uint8_t resvd1; 888 uint8_t resvd2; 889 uint8_t resvd3; 890 uint8_t Function; 891 #define SCR_FUNC_FABRIC 0x01 892 #define SCR_FUNC_NPORT 0x02 893 #define SCR_FUNC_FULL 0x03 894 #define SCR_CLEAR 0xff 895 } SCR; 896 897 typedef struct _RNID_TOP_DISC { 898 struct lpfc_name portName; 899 uint8_t resvd[8]; 900 uint32_t unitType; 901 #define RNID_HBA 0x7 902 #define RNID_HOST 0xa 903 #define RNID_DRIVER 0xd 904 uint32_t physPort; 905 uint32_t attachedNodes; 906 uint16_t ipVersion; 907 #define RNID_IPV4 0x1 908 #define RNID_IPV6 0x2 909 uint16_t UDPport; 910 uint8_t ipAddr[16]; 911 uint16_t resvd1; 912 uint16_t flags; 913 #define RNID_TD_SUPPORT 0x1 914 #define RNID_LP_VALID 0x2 915 } RNID_TOP_DISC; 916 917 typedef struct _RNID { /* Structure is in Big Endian format */ 918 uint8_t Format; 919 #define RNID_TOPOLOGY_DISC 0xdf 920 uint8_t CommonLen; 921 uint8_t resvd1; 922 uint8_t SpecificLen; 923 struct lpfc_name portName; 924 struct lpfc_name nodeName; 925 union { 926 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 927 } un; 928 } __packed RNID; 929 930 struct RLS { /* Structure is in Big Endian format */ 931 uint32_t rls; 932 #define rls_rsvd_SHIFT 24 933 #define rls_rsvd_MASK 0x000000ff 934 #define rls_rsvd_WORD rls 935 #define rls_did_SHIFT 0 936 #define rls_did_MASK 0x00ffffff 937 #define rls_did_WORD rls 938 }; 939 940 struct RLS_RSP { /* Structure is in Big Endian format */ 941 uint32_t linkFailureCnt; 942 uint32_t lossSyncCnt; 943 uint32_t lossSignalCnt; 944 uint32_t primSeqErrCnt; 945 uint32_t invalidXmitWord; 946 uint32_t crcCnt; 947 }; 948 949 struct RRQ { /* Structure is in Big Endian format */ 950 uint32_t rrq; 951 #define rrq_rsvd_SHIFT 24 952 #define rrq_rsvd_MASK 0x000000ff 953 #define rrq_rsvd_WORD rrq 954 #define rrq_did_SHIFT 0 955 #define rrq_did_MASK 0x00ffffff 956 #define rrq_did_WORD rrq 957 uint32_t rrq_exchg; 958 #define rrq_oxid_SHIFT 16 959 #define rrq_oxid_MASK 0xffff 960 #define rrq_oxid_WORD rrq_exchg 961 #define rrq_rxid_SHIFT 0 962 #define rrq_rxid_MASK 0xffff 963 #define rrq_rxid_WORD rrq_exchg 964 }; 965 966 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 967 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 968 969 struct RTV_RSP { /* Structure is in Big Endian format */ 970 uint32_t ratov; 971 uint32_t edtov; 972 uint32_t qtov; 973 #define qtov_rsvd0_SHIFT 28 974 #define qtov_rsvd0_MASK 0x0000000f 975 #define qtov_rsvd0_WORD qtov /* reserved */ 976 #define qtov_edtovres_SHIFT 27 977 #define qtov_edtovres_MASK 0x00000001 978 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 979 #define qtov__rsvd1_SHIFT 19 980 #define qtov_rsvd1_MASK 0x0000003f 981 #define qtov_rsvd1_WORD qtov /* reserved */ 982 #define qtov_rttov_SHIFT 18 983 #define qtov_rttov_MASK 0x00000001 984 #define qtov_rttov_WORD qtov /* R_T_TOV value */ 985 #define qtov_rsvd2_SHIFT 0 986 #define qtov_rsvd2_MASK 0x0003ffff 987 #define qtov_rsvd2_WORD qtov /* reserved */ 988 }; 989 990 991 typedef struct _RPL { /* Structure is in Big Endian format */ 992 uint32_t maxsize; 993 uint32_t index; 994 } RPL; 995 996 typedef struct _PORT_NUM_BLK { 997 uint32_t portNum; 998 uint32_t portID; 999 struct lpfc_name portName; 1000 } PORT_NUM_BLK; 1001 1002 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 1003 uint32_t listLen; 1004 uint32_t index; 1005 PORT_NUM_BLK port_num_blk; 1006 } RPL_RSP; 1007 1008 /* This is used for RSCN command */ 1009 typedef struct _D_ID { /* Structure is in Big Endian format */ 1010 union { 1011 uint32_t word; 1012 struct { 1013 #ifdef __BIG_ENDIAN_BITFIELD 1014 uint8_t resv; 1015 uint8_t domain; 1016 uint8_t area; 1017 uint8_t id; 1018 #else /* __LITTLE_ENDIAN_BITFIELD */ 1019 uint8_t id; 1020 uint8_t area; 1021 uint8_t domain; 1022 uint8_t resv; 1023 #endif 1024 } b; 1025 } un; 1026 } D_ID; 1027 1028 #define RSCN_ADDRESS_FORMAT_PORT 0x0 1029 #define RSCN_ADDRESS_FORMAT_AREA 0x1 1030 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 1031 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 1032 #define RSCN_ADDRESS_FORMAT_MASK 0x3 1033 1034 /* 1035 * Structure to define all ELS Payload types 1036 */ 1037 1038 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 1039 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1040 uint8_t elsByte1; 1041 uint8_t elsByte2; 1042 uint8_t elsByte3; 1043 union { 1044 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 1045 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 1046 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 1047 PRLI prli; /* Payload for PRLI/ACC */ 1048 PRLO prlo; /* Payload for PRLO/ACC */ 1049 ADISC adisc; /* Payload for ADISC/ACC */ 1050 FARP farp; /* Payload for FARP/ACC */ 1051 FAN fan; /* Payload for FAN */ 1052 SCR scr; /* Payload for SCR/ACC */ 1053 RNID rnid; /* Payload for RNID */ 1054 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1055 } un; 1056 } ELS_PKT; 1057 1058 /* 1059 * Link Cable Beacon (LCB) ELS Frame 1060 */ 1061 1062 struct fc_lcb_request_frame { 1063 uint32_t lcb_command; /* ELS command opcode (0x81) */ 1064 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1065 #define LPFC_LCB_ON 0x1 1066 #define LPFC_LCB_OFF 0x2 1067 uint8_t reserved[2]; 1068 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ 1069 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1070 #define LPFC_LCB_GREEN 0x1 1071 #define LPFC_LCB_AMBER 0x2 1072 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1073 #define LCB_CAPABILITY_DURATION 1 1074 #define BEACON_VERSION_V1 1 1075 #define BEACON_VERSION_V0 0 1076 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1077 }; 1078 1079 /* 1080 * Link Cable Beacon (LCB) ELS Response Frame 1081 */ 1082 struct fc_lcb_res_frame { 1083 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */ 1084 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1085 uint8_t reserved[2]; 1086 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ 1087 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1088 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1089 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1090 }; 1091 1092 /* 1093 * Read Diagnostic Parameters (RDP) ELS frame. 1094 */ 1095 #define SFF_PG0_IDENT_SFP 0x3 1096 1097 #define SFP_FLAG_PT_OPTICAL 0x0 1098 #define SFP_FLAG_PT_SWLASER 0x01 1099 #define SFP_FLAG_PT_LWLASER_LC1310 0x02 1100 #define SFP_FLAG_PT_LWLASER_LL1550 0x03 1101 #define SFP_FLAG_PT_MASK 0x0F 1102 #define SFP_FLAG_PT_SHIFT 0 1103 1104 #define SFP_FLAG_IS_OPTICAL_PORT 0x01 1105 #define SFP_FLAG_IS_OPTICAL_MASK 0x010 1106 #define SFP_FLAG_IS_OPTICAL_SHIFT 4 1107 1108 #define SFP_FLAG_IS_DESC_VALID 0x01 1109 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020 1110 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5 1111 1112 #define SFP_FLAG_CT_UNKNOWN 0x0 1113 #define SFP_FLAG_CT_SFP_PLUS 0x01 1114 #define SFP_FLAG_CT_MASK 0x3C 1115 #define SFP_FLAG_CT_SHIFT 6 1116 1117 struct fc_rdp_port_name_info { 1118 uint8_t wwnn[8]; 1119 uint8_t wwpn[8]; 1120 }; 1121 1122 1123 /* 1124 * Link Error Status Block Structure (FC-FS-3) for RDP 1125 * This similar to RPS ELS 1126 */ 1127 struct fc_link_status { 1128 uint32_t link_failure_cnt; 1129 uint32_t loss_of_synch_cnt; 1130 uint32_t loss_of_signal_cnt; 1131 uint32_t primitive_seq_proto_err; 1132 uint32_t invalid_trans_word; 1133 uint32_t invalid_crc_cnt; 1134 1135 }; 1136 1137 #define RDP_PORT_NAMES_DESC_TAG 0x00010003 1138 struct fc_rdp_port_name_desc { 1139 uint32_t tag; /* 0001 0003h */ 1140 uint32_t length; /* set to size of payload struct */ 1141 struct fc_rdp_port_name_info port_names; 1142 }; 1143 1144 1145 struct fc_rdp_fec_info { 1146 uint32_t CorrectedBlocks; 1147 uint32_t UncorrectableBlocks; 1148 }; 1149 1150 #define RDP_FEC_DESC_TAG 0x00010005 1151 struct fc_fec_rdp_desc { 1152 uint32_t tag; 1153 uint32_t length; 1154 struct fc_rdp_fec_info info; 1155 }; 1156 1157 struct fc_rdp_link_error_status_payload_info { 1158 struct fc_link_status link_status; /* 24 bytes */ 1159 uint32_t port_type; /* bits 31-30 only */ 1160 }; 1161 1162 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002 1163 struct fc_rdp_link_error_status_desc { 1164 uint32_t tag; /* 0001 0002h */ 1165 uint32_t length; /* set to size of payload struct */ 1166 struct fc_rdp_link_error_status_payload_info info; 1167 }; 1168 1169 #define VN_PT_PHY_UNKNOWN 0x00 1170 #define VN_PT_PHY_PF_PORT 0x01 1171 #define VN_PT_PHY_ETH_MAC 0x10 1172 #define VN_PT_PHY_SHIFT 30 1173 1174 #define RDP_PS_1GB 0x8000 1175 #define RDP_PS_2GB 0x4000 1176 #define RDP_PS_4GB 0x2000 1177 #define RDP_PS_10GB 0x1000 1178 #define RDP_PS_8GB 0x0800 1179 #define RDP_PS_16GB 0x0400 1180 #define RDP_PS_32GB 0x0200 1181 #define RDP_PS_64GB 0x0100 1182 #define RDP_PS_128GB 0x0080 1183 #define RDP_PS_256GB 0x0040 1184 1185 #define RDP_CAP_USER_CONFIGURED 0x0002 1186 #define RDP_CAP_UNKNOWN 0x0001 1187 #define RDP_PS_UNKNOWN 0x0002 1188 #define RDP_PS_NOT_ESTABLISHED 0x0001 1189 1190 struct fc_rdp_port_speed { 1191 uint16_t capabilities; 1192 uint16_t speed; 1193 }; 1194 1195 struct fc_rdp_port_speed_info { 1196 struct fc_rdp_port_speed port_speed; 1197 }; 1198 1199 #define RDP_PORT_SPEED_DESC_TAG 0x00010001 1200 struct fc_rdp_port_speed_desc { 1201 uint32_t tag; /* 00010001h */ 1202 uint32_t length; /* set to size of payload struct */ 1203 struct fc_rdp_port_speed_info info; 1204 }; 1205 1206 #define RDP_NPORT_ID_SIZE 4 1207 #define RDP_N_PORT_DESC_TAG 0x00000003 1208 struct fc_rdp_nport_desc { 1209 uint32_t tag; /* 0000 0003h, big endian */ 1210 uint32_t length; /* size of RDP_N_PORT_ID struct */ 1211 uint32_t nport_id : 12; 1212 uint32_t reserved : 8; 1213 }; 1214 1215 1216 struct fc_rdp_link_service_info { 1217 uint32_t els_req; /* Request payload word 0 value.*/ 1218 }; 1219 1220 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001 1221 struct fc_rdp_link_service_desc { 1222 uint32_t tag; /* Descriptor tag 1 */ 1223 uint32_t length; /* set to size of payload struct. */ 1224 struct fc_rdp_link_service_info payload; 1225 /* must be ELS req Word 0(0x18) */ 1226 }; 1227 1228 struct fc_rdp_sfp_info { 1229 uint16_t temperature; 1230 uint16_t vcc; 1231 uint16_t tx_bias; 1232 uint16_t tx_power; 1233 uint16_t rx_power; 1234 uint16_t flags; 1235 }; 1236 1237 #define RDP_SFP_DESC_TAG 0x00010000 1238 struct fc_rdp_sfp_desc { 1239 uint32_t tag; 1240 uint32_t length; /* set to size of sfp_info struct */ 1241 struct fc_rdp_sfp_info sfp_info; 1242 }; 1243 1244 /* Buffer Credit Descriptor */ 1245 struct fc_rdp_bbc_info { 1246 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */ 1247 uint32_t attached_port_bbc; 1248 uint32_t rtt; /* Round trip time */ 1249 }; 1250 #define RDP_BBC_DESC_TAG 0x00010006 1251 struct fc_rdp_bbc_desc { 1252 uint32_t tag; 1253 uint32_t length; 1254 struct fc_rdp_bbc_info bbc_info; 1255 }; 1256 1257 /* Optical Element Type Transgression Flags */ 1258 #define RDP_OET_LOW_WARNING 0x1 1259 #define RDP_OET_HIGH_WARNING 0x2 1260 #define RDP_OET_LOW_ALARM 0x4 1261 #define RDP_OET_HIGH_ALARM 0x8 1262 1263 #define RDP_OED_TEMPERATURE 0x1 1264 #define RDP_OED_VOLTAGE 0x2 1265 #define RDP_OED_TXBIAS 0x3 1266 #define RDP_OED_TXPOWER 0x4 1267 #define RDP_OED_RXPOWER 0x5 1268 1269 #define RDP_OED_TYPE_SHIFT 28 1270 /* Optical Element Data descriptor */ 1271 struct fc_rdp_oed_info { 1272 uint16_t hi_alarm; 1273 uint16_t lo_alarm; 1274 uint16_t hi_warning; 1275 uint16_t lo_warning; 1276 uint32_t function_flags; 1277 }; 1278 #define RDP_OED_DESC_TAG 0x00010007 1279 struct fc_rdp_oed_sfp_desc { 1280 uint32_t tag; 1281 uint32_t length; 1282 struct fc_rdp_oed_info oed_info; 1283 }; 1284 1285 /* Optical Product Data descriptor */ 1286 struct fc_rdp_opd_sfp_info { 1287 uint8_t vendor_name[16]; 1288 uint8_t model_number[16]; 1289 uint8_t serial_number[16]; 1290 uint8_t revision[4]; 1291 uint8_t date[8]; 1292 }; 1293 1294 #define RDP_OPD_DESC_TAG 0x00010008 1295 struct fc_rdp_opd_sfp_desc { 1296 uint32_t tag; 1297 uint32_t length; 1298 struct fc_rdp_opd_sfp_info opd_info; 1299 }; 1300 1301 struct fc_rdp_req_frame { 1302 uint32_t rdp_command; /* ELS command opcode (0x18)*/ 1303 uint32_t rdp_des_length; /* RDP Payload Word 1 */ 1304 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */ 1305 }; 1306 1307 1308 struct fc_rdp_res_frame { 1309 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */ 1310 uint32_t length; /* FC Word 1 */ 1311 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */ 1312 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */ 1313 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */ 1314 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */ 1315 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */ 1316 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */ 1317 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/ 1318 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/ 1319 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/ 1320 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/ 1321 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/ 1322 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/ 1323 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/ 1324 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/ 1325 }; 1326 1327 1328 /* UVEM */ 1329 1330 #define LPFC_UVEM_SIZE 60 1331 #define LPFC_UVEM_VEM_ID_DESC_SIZE 16 1332 #define LPFC_UVEM_VE_MAP_DESC_SIZE 20 1333 1334 #define VEM_ID_DESC_TAG 0x0001000A 1335 struct lpfc_vem_id_desc { 1336 uint32_t tag; 1337 uint32_t length; 1338 uint8_t vem_id[16]; 1339 }; 1340 1341 #define LPFC_QFPA_SIZE 4 1342 1343 #define INSTANTIATED_VE_DESC_TAG 0x0001000B 1344 struct instantiated_ve_desc { 1345 uint32_t tag; 1346 uint32_t length; 1347 uint8_t global_vem_id[16]; 1348 uint32_t word6; 1349 #define lpfc_instantiated_local_id_SHIFT 0 1350 #define lpfc_instantiated_local_id_MASK 0x000000ff 1351 #define lpfc_instantiated_local_id_WORD word6 1352 #define lpfc_instantiated_nport_id_SHIFT 8 1353 #define lpfc_instantiated_nport_id_MASK 0x00ffffff 1354 #define lpfc_instantiated_nport_id_WORD word6 1355 }; 1356 1357 #define DEINSTANTIATED_VE_DESC_TAG 0x0001000C 1358 struct deinstantiated_ve_desc { 1359 uint32_t tag; 1360 uint32_t length; 1361 uint8_t global_vem_id[16]; 1362 uint32_t word6; 1363 #define lpfc_deinstantiated_nport_id_SHIFT 0 1364 #define lpfc_deinstantiated_nport_id_MASK 0x000000ff 1365 #define lpfc_deinstantiated_nport_id_WORD word6 1366 #define lpfc_deinstantiated_local_id_SHIFT 24 1367 #define lpfc_deinstantiated_local_id_MASK 0x00ffffff 1368 #define lpfc_deinstantiated_local_id_WORD word6 1369 }; 1370 1371 /* Query Fabric Priority Allocation Response */ 1372 #define LPFC_PRIORITY_RANGE_DESC_SIZE 12 1373 1374 struct priority_range_desc { 1375 uint32_t tag; 1376 uint32_t length; 1377 uint8_t lo_range; 1378 uint8_t hi_range; 1379 uint8_t qos_priority; 1380 uint8_t local_ve_id; 1381 }; 1382 1383 struct fc_qfpa_res { 1384 uint32_t reply_sequence; /* LS_ACC or LS_RJT */ 1385 uint32_t length; /* FC Word 1 */ 1386 struct priority_range_desc desc[1]; 1387 }; 1388 1389 /* Application Server command code */ 1390 /* VMID */ 1391 1392 #define SLI_CT_APP_SEV_Subtypes 0x20 /* Application Server subtype */ 1393 1394 #define SLI_CTAS_GAPPIA_ENT 0x0100 /* Get Application Identifier */ 1395 #define SLI_CTAS_GALLAPPIA 0x0101 /* Get All Application Identifier */ 1396 #define SLI_CTAS_GALLAPPIA_ID 0x0102 /* Get All Application Identifier */ 1397 /* for Nport */ 1398 #define SLI_CTAS_GAPPIA_IDAPP 0x0103 /* Get Application Identifier */ 1399 /* for Nport */ 1400 #define SLI_CTAS_RAPP_IDENT 0x0200 /* Register Application Identifier */ 1401 #define SLI_CTAS_DAPP_IDENT 0x0300 /* Deregister Application */ 1402 /* Identifier */ 1403 #define SLI_CTAS_DALLAPP_ID 0x0301 /* Deregister All Application */ 1404 /* Identifier */ 1405 1406 struct entity_id_object { 1407 uint8_t entity_id_len; 1408 uint8_t entity_id[255]; /* VM UUID */ 1409 }; 1410 1411 struct app_id_object { 1412 uint32_t port_id; 1413 uint32_t app_id; 1414 struct entity_id_object obj; 1415 }; 1416 1417 struct lpfc_vmid_rapp_ident_list { 1418 uint32_t no_of_objects; 1419 struct entity_id_object obj[1]; 1420 }; 1421 1422 struct lpfc_vmid_dapp_ident_list { 1423 uint32_t no_of_objects; 1424 struct entity_id_object obj[1]; 1425 }; 1426 1427 #define GALLAPPIA_ID_LAST 0x80 1428 struct lpfc_vmid_gallapp_ident_list { 1429 uint8_t control; 1430 uint8_t reserved[3]; 1431 struct app_id_object app_id; 1432 }; 1433 1434 #define RAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) 1435 #define DAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) 1436 #define GALLAPPIA_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) 1437 #define DALLAPP_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) 1438 1439 /******** FDMI ********/ 1440 1441 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */ 1442 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */ 1443 1444 /* Definitions for HBA / Port attribute entries */ 1445 1446 /* Attribute Entry */ 1447 struct lpfc_fdmi_attr_entry { 1448 union { 1449 uint32_t AttrInt; 1450 uint8_t AttrTypes[32]; 1451 uint8_t AttrString[256]; 1452 struct lpfc_name AttrWWN; 1453 } un; 1454 }; 1455 1456 struct lpfc_fdmi_attr_def { /* Defined in TLV format */ 1457 /* Structure is in Big Endian format */ 1458 uint32_t AttrType:16; 1459 uint32_t AttrLen:16; 1460 /* Marks start of Value (ATTRIBUTE_ENTRY) */ 1461 struct lpfc_fdmi_attr_entry AttrValue; 1462 } __packed; 1463 1464 /* 1465 * HBA Attribute Block 1466 */ 1467 struct lpfc_fdmi_attr_block { 1468 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1469 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */ 1470 }; 1471 1472 /* 1473 * Port Entry 1474 */ 1475 struct lpfc_fdmi_port_entry { 1476 struct lpfc_name PortName; 1477 }; 1478 1479 /* 1480 * HBA Identifier 1481 */ 1482 struct lpfc_fdmi_hba_ident { 1483 struct lpfc_name PortName; 1484 }; 1485 1486 /* 1487 * Registered Port List Format 1488 */ 1489 struct lpfc_fdmi_reg_port_list { 1490 uint32_t EntryCnt; 1491 struct lpfc_fdmi_port_entry pe; 1492 } __packed; 1493 1494 /* 1495 * Register HBA(RHBA) 1496 */ 1497 struct lpfc_fdmi_reg_hba { 1498 struct lpfc_fdmi_hba_ident hi; 1499 struct lpfc_fdmi_reg_port_list rpl; 1500 }; 1501 1502 /******** MI MIB ********/ 1503 #define SLI_CT_MIB_Subtypes 0x11 1504 1505 /* 1506 * Register HBA Attributes (RHAT) 1507 */ 1508 struct lpfc_fdmi_reg_hbaattr { 1509 struct lpfc_name HBA_PortName; 1510 struct lpfc_fdmi_attr_block ab; 1511 }; 1512 1513 /* 1514 * Register Port Attributes (RPA) 1515 */ 1516 struct lpfc_fdmi_reg_portattr { 1517 struct lpfc_name PortName; 1518 struct lpfc_fdmi_attr_block ab; 1519 }; 1520 1521 /* 1522 * HBA MAnagement Operations Command Codes 1523 */ 1524 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1525 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1526 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1527 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1528 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */ 1529 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1530 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1531 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1532 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1533 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1534 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */ 1535 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1536 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */ 1537 1538 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */ 1539 1540 /* 1541 * HBA Attribute Types 1542 */ 1543 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */ 1544 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */ 1545 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */ 1546 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */ 1547 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */ 1548 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */ 1549 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */ 1550 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */ 1551 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */ 1552 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */ 1553 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */ 1554 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */ 1555 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */ 1556 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */ 1557 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */ 1558 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */ 1559 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */ 1560 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */ 1561 1562 /* Bit mask for all individual HBA attributes */ 1563 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001 1564 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002 1565 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004 1566 #define LPFC_FDMI_HBA_ATTR_model 0x00000008 1567 #define LPFC_FDMI_HBA_ATTR_description 0x00000010 1568 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020 1569 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040 1570 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080 1571 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100 1572 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200 1573 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400 1574 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800 1575 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */ 1576 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000 1577 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000 1578 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000 1579 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */ 1580 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000 1581 1582 /* Bit mask for FDMI-1 defined HBA attributes */ 1583 #define LPFC_FDMI1_HBA_ATTR 0x000007ff 1584 1585 /* Bit mask for FDMI-2 defined HBA attributes */ 1586 /* Skip vendor_info and bios_state */ 1587 #define LPFC_FDMI2_HBA_ATTR 0x0002efff 1588 1589 /* 1590 * Port Attribute Types 1591 */ 1592 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */ 1593 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */ 1594 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */ 1595 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */ 1596 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */ 1597 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */ 1598 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */ 1599 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */ 1600 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */ 1601 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */ 1602 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */ 1603 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */ 1604 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */ 1605 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */ 1606 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */ 1607 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */ 1608 #define RPRT_VENDOR_MI 0xf047 /* vendor ascii string */ 1609 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */ 1610 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */ 1611 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */ 1612 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */ 1613 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */ 1614 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */ 1615 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */ 1616 1617 /* Bit mask for all individual PORT attributes */ 1618 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001 1619 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002 1620 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004 1621 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008 1622 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010 1623 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020 1624 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040 1625 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080 1626 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100 1627 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200 1628 #define LPFC_FDMI_PORT_ATTR_class 0x00000400 1629 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800 1630 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000 1631 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000 1632 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000 1633 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000 1634 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */ 1635 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */ 1636 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */ 1637 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */ 1638 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */ 1639 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */ 1640 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */ 1641 #define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000 /* Vendor specific */ 1642 1643 /* Bit mask for FDMI-1 defined PORT attributes */ 1644 #define LPFC_FDMI1_PORT_ATTR 0x0000003f 1645 1646 /* Bit mask for FDMI-2 defined PORT attributes */ 1647 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff 1648 1649 /* Bit mask for Smart SAN defined PORT attributes */ 1650 #define LPFC_FDMI2_SMART_ATTR 0x007fffff 1651 1652 /* Defines for PORT port state attribute */ 1653 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1 1654 #define LPFC_FDMI_PORTSTATE_ONLINE 2 1655 1656 /* Defines for PORT port type attribute */ 1657 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0 1658 #define LPFC_FDMI_PORTTYPE_NPORT 1 1659 #define LPFC_FDMI_PORTTYPE_NLPORT 2 1660 1661 /* 1662 * Begin HBA configuration parameters. 1663 * The PCI configuration register BAR assignments are: 1664 * BAR0, offset 0x10 - SLIM base memory address 1665 * BAR1, offset 0x14 - SLIM base memory high address 1666 * BAR2, offset 0x18 - REGISTER base memory address 1667 * BAR3, offset 0x1c - REGISTER base memory high address 1668 * BAR4, offset 0x20 - BIU I/O registers 1669 * BAR5, offset 0x24 - REGISTER base io high address 1670 */ 1671 1672 /* Number of rings currently used and available. */ 1673 #define MAX_SLI3_CONFIGURED_RINGS 3 1674 #define MAX_SLI3_RINGS 4 1675 1676 /* IOCB / Mailbox is owned by FireFly */ 1677 #define OWN_CHIP 1 1678 1679 /* IOCB / Mailbox is owned by Host */ 1680 #define OWN_HOST 0 1681 1682 /* Number of 4-byte words in an IOCB. */ 1683 #define IOCB_WORD_SZ 8 1684 1685 /* network headers for Dfctl field */ 1686 #define FC_NET_HDR 0x20 1687 1688 /* Start FireFly Register definitions */ 1689 #define PCI_VENDOR_ID_EMULEX 0x10df 1690 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1691 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1692 #define PCI_DEVICE_ID_BALIUS 0xe131 1693 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1694 #define PCI_DEVICE_ID_LANCER_FC 0xe200 1695 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1696 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1697 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1698 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300 1699 #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400 1700 #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500 1701 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1702 #define PCI_DEVICE_ID_SAT_MID 0xf015 1703 #define PCI_DEVICE_ID_RFLY 0xf095 1704 #define PCI_DEVICE_ID_PFLY 0xf098 1705 #define PCI_DEVICE_ID_LP101 0xf0a1 1706 #define PCI_DEVICE_ID_TFLY 0xf0a5 1707 #define PCI_DEVICE_ID_BSMB 0xf0d1 1708 #define PCI_DEVICE_ID_BMID 0xf0d5 1709 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1710 #define PCI_DEVICE_ID_ZMID 0xf0e5 1711 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1712 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1713 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1714 #define PCI_DEVICE_ID_SAT 0xf100 1715 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1716 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1717 #define PCI_DEVICE_ID_FALCON 0xf180 1718 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1719 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1720 #define PCI_DEVICE_ID_CENTAUR 0xf900 1721 #define PCI_DEVICE_ID_PEGASUS 0xf980 1722 #define PCI_DEVICE_ID_THOR 0xfa00 1723 #define PCI_DEVICE_ID_VIPER 0xfb00 1724 #define PCI_DEVICE_ID_LP10000S 0xfc00 1725 #define PCI_DEVICE_ID_LP11000S 0xfc10 1726 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1727 #define PCI_DEVICE_ID_SAT_S 0xfc40 1728 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1729 #define PCI_DEVICE_ID_HELIOS 0xfd00 1730 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1731 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1732 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1733 #define PCI_DEVICE_ID_HORNET 0xfe05 1734 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1735 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1736 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1737 #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1738 #define PCI_DEVICE_ID_TOMCAT 0x0714 1739 #define PCI_DEVICE_ID_SKYHAWK 0x0724 1740 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c 1741 1742 #define JEDEC_ID_ADDRESS 0x0080001c 1743 #define FIREFLY_JEDEC_ID 0x1ACC 1744 #define SUPERFLY_JEDEC_ID 0x0020 1745 #define DRAGONFLY_JEDEC_ID 0x0021 1746 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1747 #define CENTAUR_2G_JEDEC_ID 0x0026 1748 #define CENTAUR_1G_JEDEC_ID 0x0028 1749 #define PEGASUS_ORION_JEDEC_ID 0x0036 1750 #define PEGASUS_JEDEC_ID 0x0038 1751 #define THOR_JEDEC_ID 0x0012 1752 #define HELIOS_JEDEC_ID 0x0364 1753 #define ZEPHYR_JEDEC_ID 0x0577 1754 #define VIPER_JEDEC_ID 0x4838 1755 #define SATURN_JEDEC_ID 0x1004 1756 #define HORNET_JDEC_ID 0x2057706D 1757 1758 #define JEDEC_ID_MASK 0x0FFFF000 1759 #define JEDEC_ID_SHIFT 12 1760 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1761 1762 typedef struct { /* FireFly BIU registers */ 1763 uint32_t hostAtt; /* See definitions for Host Attention 1764 register */ 1765 uint32_t chipAtt; /* See definitions for Chip Attention 1766 register */ 1767 uint32_t hostStatus; /* See definitions for Host Status register */ 1768 uint32_t hostControl; /* See definitions for Host Control register */ 1769 uint32_t buiConfig; /* See definitions for BIU configuration 1770 register */ 1771 } FF_REGS; 1772 1773 /* IO Register size in bytes */ 1774 #define FF_REG_AREA_SIZE 256 1775 1776 /* Host Attention Register */ 1777 1778 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1779 1780 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1781 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1782 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1783 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1784 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1785 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1786 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1787 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1788 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1789 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1790 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1791 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1792 #define HA_LATT 0x20000000 /* Bit 29 */ 1793 #define HA_MBATT 0x40000000 /* Bit 30 */ 1794 #define HA_ERATT 0x80000000 /* Bit 31 */ 1795 1796 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1797 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1798 #define HA_RXATT 0x00000008 /* Bit 3 */ 1799 #define HA_RXMASK 0x0000000f 1800 1801 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1802 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1803 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1804 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1805 1806 #define HA_R0_POS 3 1807 #define HA_R1_POS 7 1808 #define HA_R2_POS 11 1809 #define HA_R3_POS 15 1810 #define HA_LE_POS 29 1811 #define HA_MB_POS 30 1812 #define HA_ER_POS 31 1813 /* Chip Attention Register */ 1814 1815 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1816 1817 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1818 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1819 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1820 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1821 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1822 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1823 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1824 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1825 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1826 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1827 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1828 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1829 #define CA_MBATT 0x40000000 /* Bit 30 */ 1830 1831 /* Host Status Register */ 1832 1833 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1834 1835 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1836 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1837 #define HS_FFER8 0x01000000 /* Bit 24 */ 1838 #define HS_FFER7 0x02000000 /* Bit 25 */ 1839 #define HS_FFER6 0x04000000 /* Bit 26 */ 1840 #define HS_FFER5 0x08000000 /* Bit 27 */ 1841 #define HS_FFER4 0x10000000 /* Bit 28 */ 1842 #define HS_FFER3 0x20000000 /* Bit 29 */ 1843 #define HS_FFER2 0x40000000 /* Bit 30 */ 1844 #define HS_FFER1 0x80000000 /* Bit 31 */ 1845 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1846 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1847 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1848 /* Host Control Register */ 1849 1850 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1851 1852 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1853 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1854 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1855 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1856 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1857 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1858 #define HC_INITMB 0x04000000 /* Bit 26 */ 1859 #define HC_INITFF 0x08000000 /* Bit 27 */ 1860 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1861 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1862 1863 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1864 #define MSIX_DFLT_ID 0 1865 #define MSIX_RNG0_ID 0 1866 #define MSIX_RNG1_ID 1 1867 #define MSIX_RNG2_ID 2 1868 #define MSIX_RNG3_ID 3 1869 1870 #define MSIX_LINK_ID 4 1871 #define MSIX_MBOX_ID 5 1872 1873 #define MSIX_SPARE0_ID 6 1874 #define MSIX_SPARE1_ID 7 1875 1876 /* Mailbox Commands */ 1877 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1878 #define MBX_LOAD_SM 0x01 1879 #define MBX_READ_NV 0x02 1880 #define MBX_WRITE_NV 0x03 1881 #define MBX_RUN_BIU_DIAG 0x04 1882 #define MBX_INIT_LINK 0x05 1883 #define MBX_DOWN_LINK 0x06 1884 #define MBX_CONFIG_LINK 0x07 1885 #define MBX_CONFIG_RING 0x09 1886 #define MBX_RESET_RING 0x0A 1887 #define MBX_READ_CONFIG 0x0B 1888 #define MBX_READ_RCONFIG 0x0C 1889 #define MBX_READ_SPARM 0x0D 1890 #define MBX_READ_STATUS 0x0E 1891 #define MBX_READ_RPI 0x0F 1892 #define MBX_READ_XRI 0x10 1893 #define MBX_READ_REV 0x11 1894 #define MBX_READ_LNK_STAT 0x12 1895 #define MBX_REG_LOGIN 0x13 1896 #define MBX_UNREG_LOGIN 0x14 1897 #define MBX_CLEAR_LA 0x16 1898 #define MBX_DUMP_MEMORY 0x17 1899 #define MBX_DUMP_CONTEXT 0x18 1900 #define MBX_RUN_DIAGS 0x19 1901 #define MBX_RESTART 0x1A 1902 #define MBX_UPDATE_CFG 0x1B 1903 #define MBX_DOWN_LOAD 0x1C 1904 #define MBX_DEL_LD_ENTRY 0x1D 1905 #define MBX_RUN_PROGRAM 0x1E 1906 #define MBX_SET_MASK 0x20 1907 #define MBX_SET_VARIABLE 0x21 1908 #define MBX_UNREG_D_ID 0x23 1909 #define MBX_KILL_BOARD 0x24 1910 #define MBX_CONFIG_FARP 0x25 1911 #define MBX_BEACON 0x2A 1912 #define MBX_CONFIG_MSI 0x30 1913 #define MBX_HEARTBEAT 0x31 1914 #define MBX_WRITE_VPARMS 0x32 1915 #define MBX_ASYNCEVT_ENABLE 0x33 1916 #define MBX_READ_EVENT_LOG_STATUS 0x37 1917 #define MBX_READ_EVENT_LOG 0x38 1918 #define MBX_WRITE_EVENT_LOG 0x39 1919 1920 #define MBX_PORT_CAPABILITIES 0x3B 1921 #define MBX_PORT_IOV_CONTROL 0x3C 1922 1923 #define MBX_CONFIG_HBQ 0x7C 1924 #define MBX_LOAD_AREA 0x81 1925 #define MBX_RUN_BIU_DIAG64 0x84 1926 #define MBX_CONFIG_PORT 0x88 1927 #define MBX_READ_SPARM64 0x8D 1928 #define MBX_READ_RPI64 0x8F 1929 #define MBX_REG_LOGIN64 0x93 1930 #define MBX_READ_TOPOLOGY 0x95 1931 #define MBX_REG_VPI 0x96 1932 #define MBX_UNREG_VPI 0x97 1933 1934 #define MBX_WRITE_WWN 0x98 1935 #define MBX_SET_DEBUG 0x99 1936 #define MBX_LOAD_EXP_ROM 0x9C 1937 #define MBX_SLI4_CONFIG 0x9B 1938 #define MBX_SLI4_REQ_FTRS 0x9D 1939 #define MBX_MAX_CMDS 0x9E 1940 #define MBX_RESUME_RPI 0x9E 1941 #define MBX_SLI2_CMD_MASK 0x80 1942 #define MBX_REG_VFI 0x9F 1943 #define MBX_REG_FCFI 0xA0 1944 #define MBX_UNREG_VFI 0xA1 1945 #define MBX_UNREG_FCFI 0xA2 1946 #define MBX_INIT_VFI 0xA3 1947 #define MBX_INIT_VPI 0xA4 1948 #define MBX_ACCESS_VDATA 0xA5 1949 #define MBX_REG_FCFI_MRQ 0xAF 1950 1951 #define MBX_AUTH_PORT 0xF8 1952 #define MBX_SECURITY_MGMT 0xF9 1953 1954 /* IOCB Commands */ 1955 1956 #define CMD_RCV_SEQUENCE_CX 0x01 1957 #define CMD_XMIT_SEQUENCE_CR 0x02 1958 #define CMD_XMIT_SEQUENCE_CX 0x03 1959 #define CMD_XMIT_BCAST_CN 0x04 1960 #define CMD_XMIT_BCAST_CX 0x05 1961 #define CMD_QUE_RING_BUF_CN 0x06 1962 #define CMD_QUE_XRI_BUF_CX 0x07 1963 #define CMD_IOCB_CONTINUE_CN 0x08 1964 #define CMD_RET_XRI_BUF_CX 0x09 1965 #define CMD_ELS_REQUEST_CR 0x0A 1966 #define CMD_ELS_REQUEST_CX 0x0B 1967 #define CMD_RCV_ELS_REQ_CX 0x0D 1968 #define CMD_ABORT_XRI_CN 0x0E 1969 #define CMD_ABORT_XRI_CX 0x0F 1970 #define CMD_CLOSE_XRI_CN 0x10 1971 #define CMD_CLOSE_XRI_CX 0x11 1972 #define CMD_CREATE_XRI_CR 0x12 1973 #define CMD_CREATE_XRI_CX 0x13 1974 #define CMD_GET_RPI_CN 0x14 1975 #define CMD_XMIT_ELS_RSP_CX 0x15 1976 #define CMD_GET_RPI_CR 0x16 1977 #define CMD_XRI_ABORTED_CX 0x17 1978 #define CMD_FCP_IWRITE_CR 0x18 1979 #define CMD_FCP_IWRITE_CX 0x19 1980 #define CMD_FCP_IREAD_CR 0x1A 1981 #define CMD_FCP_IREAD_CX 0x1B 1982 #define CMD_FCP_ICMND_CR 0x1C 1983 #define CMD_FCP_ICMND_CX 0x1D 1984 #define CMD_FCP_TSEND_CX 0x1F 1985 #define CMD_FCP_TRECEIVE_CX 0x21 1986 #define CMD_FCP_TRSP_CX 0x23 1987 #define CMD_FCP_AUTO_TRSP_CX 0x29 1988 1989 #define CMD_ADAPTER_MSG 0x20 1990 #define CMD_ADAPTER_DUMP 0x22 1991 1992 /* SLI_2 IOCB Command Set */ 1993 1994 #define CMD_ASYNC_STATUS 0x7C 1995 #define CMD_RCV_SEQUENCE64_CX 0x81 1996 #define CMD_XMIT_SEQUENCE64_CR 0x82 1997 #define CMD_XMIT_SEQUENCE64_CX 0x83 1998 #define CMD_XMIT_BCAST64_CN 0x84 1999 #define CMD_XMIT_BCAST64_CX 0x85 2000 #define CMD_QUE_RING_BUF64_CN 0x86 2001 #define CMD_QUE_XRI_BUF64_CX 0x87 2002 #define CMD_IOCB_CONTINUE64_CN 0x88 2003 #define CMD_RET_XRI_BUF64_CX 0x89 2004 #define CMD_ELS_REQUEST64_CR 0x8A 2005 #define CMD_ELS_REQUEST64_CX 0x8B 2006 #define CMD_ABORT_MXRI64_CN 0x8C 2007 #define CMD_RCV_ELS_REQ64_CX 0x8D 2008 #define CMD_XMIT_ELS_RSP64_CX 0x95 2009 #define CMD_XMIT_BLS_RSP64_CX 0x97 2010 #define CMD_FCP_IWRITE64_CR 0x98 2011 #define CMD_FCP_IWRITE64_CX 0x99 2012 #define CMD_FCP_IREAD64_CR 0x9A 2013 #define CMD_FCP_IREAD64_CX 0x9B 2014 #define CMD_FCP_ICMND64_CR 0x9C 2015 #define CMD_FCP_ICMND64_CX 0x9D 2016 #define CMD_FCP_TSEND64_CX 0x9F 2017 #define CMD_FCP_TRECEIVE64_CX 0xA1 2018 #define CMD_FCP_TRSP64_CX 0xA3 2019 2020 #define CMD_QUE_XRI64_CX 0xB3 2021 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 2022 #define CMD_IOCB_RCV_ELS64_CX 0xB7 2023 #define CMD_IOCB_RET_XRI64_CX 0xB9 2024 #define CMD_IOCB_RCV_CONT64_CX 0xBB 2025 2026 #define CMD_GEN_REQUEST64_CR 0xC2 2027 #define CMD_GEN_REQUEST64_CX 0xC3 2028 2029 /* Unhandled SLI-3 Commands */ 2030 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 2031 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 2032 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 2033 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 2034 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 2035 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 2036 #define CMD_IOCB_RET_HBQE64_CN 0xCA 2037 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 2038 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 2039 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 2040 #define CMD_IOCB_LOGENTRY_CN 0x94 2041 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 2042 2043 /* Data Security SLI Commands */ 2044 #define DSSCMD_IWRITE64_CR 0xF8 2045 #define DSSCMD_IWRITE64_CX 0xF9 2046 #define DSSCMD_IREAD64_CR 0xFA 2047 #define DSSCMD_IREAD64_CX 0xFB 2048 2049 #define CMD_MAX_IOCB_CMD 0xFB 2050 #define CMD_IOCB_MASK 0xff 2051 2052 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 2053 iocb */ 2054 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 2055 /* 2056 * Define Status 2057 */ 2058 #define MBX_SUCCESS 0 2059 #define MBXERR_NUM_RINGS 1 2060 #define MBXERR_NUM_IOCBS 2 2061 #define MBXERR_IOCBS_EXCEEDED 3 2062 #define MBXERR_BAD_RING_NUMBER 4 2063 #define MBXERR_MASK_ENTRIES_RANGE 5 2064 #define MBXERR_MASKS_EXCEEDED 6 2065 #define MBXERR_BAD_PROFILE 7 2066 #define MBXERR_BAD_DEF_CLASS 8 2067 #define MBXERR_BAD_MAX_RESPONDER 9 2068 #define MBXERR_BAD_MAX_ORIGINATOR 10 2069 #define MBXERR_RPI_REGISTERED 11 2070 #define MBXERR_RPI_FULL 12 2071 #define MBXERR_NO_RESOURCES 13 2072 #define MBXERR_BAD_RCV_LENGTH 14 2073 #define MBXERR_DMA_ERROR 15 2074 #define MBXERR_ERROR 16 2075 #define MBXERR_LINK_DOWN 0x33 2076 #define MBXERR_SEC_NO_PERMISSION 0xF02 2077 #define MBX_NOT_FINISHED 255 2078 2079 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 2080 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 2081 2082 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 2083 2084 /* 2085 * return code Fail 2086 */ 2087 #define FAILURE 1 2088 2089 /* 2090 * Begin Structure Definitions for Mailbox Commands 2091 */ 2092 2093 typedef struct { 2094 #ifdef __BIG_ENDIAN_BITFIELD 2095 uint8_t tval; 2096 uint8_t tmask; 2097 uint8_t rval; 2098 uint8_t rmask; 2099 #else /* __LITTLE_ENDIAN_BITFIELD */ 2100 uint8_t rmask; 2101 uint8_t rval; 2102 uint8_t tmask; 2103 uint8_t tval; 2104 #endif 2105 } RR_REG; 2106 2107 struct ulp_bde { 2108 uint32_t bdeAddress; 2109 #ifdef __BIG_ENDIAN_BITFIELD 2110 uint32_t bdeReserved:4; 2111 uint32_t bdeAddrHigh:4; 2112 uint32_t bdeSize:24; 2113 #else /* __LITTLE_ENDIAN_BITFIELD */ 2114 uint32_t bdeSize:24; 2115 uint32_t bdeAddrHigh:4; 2116 uint32_t bdeReserved:4; 2117 #endif 2118 }; 2119 2120 typedef struct ULP_BDL { /* SLI-2 */ 2121 #ifdef __BIG_ENDIAN_BITFIELD 2122 uint32_t bdeFlags:8; /* BDL Flags */ 2123 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 2124 #else /* __LITTLE_ENDIAN_BITFIELD */ 2125 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 2126 uint32_t bdeFlags:8; /* BDL Flags */ 2127 #endif 2128 2129 uint32_t addrLow; /* Address 0:31 */ 2130 uint32_t addrHigh; /* Address 32:63 */ 2131 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 2132 } ULP_BDL; 2133 2134 /* 2135 * BlockGuard Definitions 2136 */ 2137 2138 enum lpfc_protgrp_type { 2139 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 2140 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 2141 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 2142 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 2143 }; 2144 2145 /* PDE Descriptors */ 2146 #define LPFC_PDE5_DESCRIPTOR 0x85 2147 #define LPFC_PDE6_DESCRIPTOR 0x86 2148 #define LPFC_PDE7_DESCRIPTOR 0x87 2149 2150 /* BlockGuard Opcodes */ 2151 #define BG_OP_IN_NODIF_OUT_CRC 0x0 2152 #define BG_OP_IN_CRC_OUT_NODIF 0x1 2153 #define BG_OP_IN_NODIF_OUT_CSUM 0x2 2154 #define BG_OP_IN_CSUM_OUT_NODIF 0x3 2155 #define BG_OP_IN_CRC_OUT_CRC 0x4 2156 #define BG_OP_IN_CSUM_OUT_CSUM 0x5 2157 #define BG_OP_IN_CRC_OUT_CSUM 0x6 2158 #define BG_OP_IN_CSUM_OUT_CRC 0x7 2159 #define BG_OP_RAW_MODE 0x8 2160 2161 struct lpfc_pde5 { 2162 uint32_t word0; 2163 #define pde5_type_SHIFT 24 2164 #define pde5_type_MASK 0x000000ff 2165 #define pde5_type_WORD word0 2166 #define pde5_rsvd0_SHIFT 0 2167 #define pde5_rsvd0_MASK 0x00ffffff 2168 #define pde5_rsvd0_WORD word0 2169 uint32_t reftag; /* Reference Tag Value */ 2170 uint32_t reftagtr; /* Reference Tag Translation Value */ 2171 }; 2172 2173 struct lpfc_pde6 { 2174 uint32_t word0; 2175 #define pde6_type_SHIFT 24 2176 #define pde6_type_MASK 0x000000ff 2177 #define pde6_type_WORD word0 2178 #define pde6_rsvd0_SHIFT 0 2179 #define pde6_rsvd0_MASK 0x00ffffff 2180 #define pde6_rsvd0_WORD word0 2181 uint32_t word1; 2182 #define pde6_rsvd1_SHIFT 26 2183 #define pde6_rsvd1_MASK 0x0000003f 2184 #define pde6_rsvd1_WORD word1 2185 #define pde6_na_SHIFT 25 2186 #define pde6_na_MASK 0x00000001 2187 #define pde6_na_WORD word1 2188 #define pde6_rsvd2_SHIFT 16 2189 #define pde6_rsvd2_MASK 0x000001FF 2190 #define pde6_rsvd2_WORD word1 2191 #define pde6_apptagtr_SHIFT 0 2192 #define pde6_apptagtr_MASK 0x0000ffff 2193 #define pde6_apptagtr_WORD word1 2194 uint32_t word2; 2195 #define pde6_optx_SHIFT 28 2196 #define pde6_optx_MASK 0x0000000f 2197 #define pde6_optx_WORD word2 2198 #define pde6_oprx_SHIFT 24 2199 #define pde6_oprx_MASK 0x0000000f 2200 #define pde6_oprx_WORD word2 2201 #define pde6_nr_SHIFT 23 2202 #define pde6_nr_MASK 0x00000001 2203 #define pde6_nr_WORD word2 2204 #define pde6_ce_SHIFT 22 2205 #define pde6_ce_MASK 0x00000001 2206 #define pde6_ce_WORD word2 2207 #define pde6_re_SHIFT 21 2208 #define pde6_re_MASK 0x00000001 2209 #define pde6_re_WORD word2 2210 #define pde6_ae_SHIFT 20 2211 #define pde6_ae_MASK 0x00000001 2212 #define pde6_ae_WORD word2 2213 #define pde6_ai_SHIFT 19 2214 #define pde6_ai_MASK 0x00000001 2215 #define pde6_ai_WORD word2 2216 #define pde6_bs_SHIFT 16 2217 #define pde6_bs_MASK 0x00000007 2218 #define pde6_bs_WORD word2 2219 #define pde6_apptagval_SHIFT 0 2220 #define pde6_apptagval_MASK 0x0000ffff 2221 #define pde6_apptagval_WORD word2 2222 }; 2223 2224 struct lpfc_pde7 { 2225 uint32_t word0; 2226 #define pde7_type_SHIFT 24 2227 #define pde7_type_MASK 0x000000ff 2228 #define pde7_type_WORD word0 2229 #define pde7_rsvd0_SHIFT 0 2230 #define pde7_rsvd0_MASK 0x00ffffff 2231 #define pde7_rsvd0_WORD word0 2232 uint32_t addrHigh; 2233 uint32_t addrLow; 2234 }; 2235 2236 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 2237 2238 typedef struct { 2239 #ifdef __BIG_ENDIAN_BITFIELD 2240 uint32_t rsvd2:25; 2241 uint32_t acknowledgment:1; 2242 uint32_t version:1; 2243 uint32_t erase_or_prog:1; 2244 uint32_t update_flash:1; 2245 uint32_t update_ram:1; 2246 uint32_t method:1; 2247 uint32_t load_cmplt:1; 2248 #else /* __LITTLE_ENDIAN_BITFIELD */ 2249 uint32_t load_cmplt:1; 2250 uint32_t method:1; 2251 uint32_t update_ram:1; 2252 uint32_t update_flash:1; 2253 uint32_t erase_or_prog:1; 2254 uint32_t version:1; 2255 uint32_t acknowledgment:1; 2256 uint32_t rsvd2:25; 2257 #endif 2258 2259 uint32_t dl_to_adr_low; 2260 uint32_t dl_to_adr_high; 2261 uint32_t dl_len; 2262 union { 2263 uint32_t dl_from_mbx_offset; 2264 struct ulp_bde dl_from_bde; 2265 struct ulp_bde64 dl_from_bde64; 2266 } un; 2267 2268 } LOAD_SM_VAR; 2269 2270 /* Structure for MB Command READ_NVPARM (02) */ 2271 2272 typedef struct { 2273 uint32_t rsvd1[3]; /* Read as all one's */ 2274 uint32_t rsvd2; /* Read as all zero's */ 2275 uint32_t portname[2]; /* N_PORT name */ 2276 uint32_t nodename[2]; /* NODE name */ 2277 2278 #ifdef __BIG_ENDIAN_BITFIELD 2279 uint32_t pref_DID:24; 2280 uint32_t hardAL_PA:8; 2281 #else /* __LITTLE_ENDIAN_BITFIELD */ 2282 uint32_t hardAL_PA:8; 2283 uint32_t pref_DID:24; 2284 #endif 2285 2286 uint32_t rsvd3[21]; /* Read as all one's */ 2287 } READ_NV_VAR; 2288 2289 /* Structure for MB Command WRITE_NVPARMS (03) */ 2290 2291 typedef struct { 2292 uint32_t rsvd1[3]; /* Must be all one's */ 2293 uint32_t rsvd2; /* Must be all zero's */ 2294 uint32_t portname[2]; /* N_PORT name */ 2295 uint32_t nodename[2]; /* NODE name */ 2296 2297 #ifdef __BIG_ENDIAN_BITFIELD 2298 uint32_t pref_DID:24; 2299 uint32_t hardAL_PA:8; 2300 #else /* __LITTLE_ENDIAN_BITFIELD */ 2301 uint32_t hardAL_PA:8; 2302 uint32_t pref_DID:24; 2303 #endif 2304 2305 uint32_t rsvd3[21]; /* Must be all one's */ 2306 } WRITE_NV_VAR; 2307 2308 /* Structure for MB Command RUN_BIU_DIAG (04) */ 2309 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 2310 2311 typedef struct { 2312 uint32_t rsvd1; 2313 union { 2314 struct { 2315 struct ulp_bde xmit_bde; 2316 struct ulp_bde rcv_bde; 2317 } s1; 2318 struct { 2319 struct ulp_bde64 xmit_bde64; 2320 struct ulp_bde64 rcv_bde64; 2321 } s2; 2322 } un; 2323 } BIU_DIAG_VAR; 2324 2325 /* Structure for MB command READ_EVENT_LOG (0x38) */ 2326 struct READ_EVENT_LOG_VAR { 2327 uint32_t word1; 2328 #define lpfc_event_log_SHIFT 29 2329 #define lpfc_event_log_MASK 0x00000001 2330 #define lpfc_event_log_WORD word1 2331 #define USE_MAILBOX_RESPONSE 1 2332 uint32_t offset; 2333 struct ulp_bde64 rcv_bde64; 2334 }; 2335 2336 /* Structure for MB Command INIT_LINK (05) */ 2337 2338 typedef struct { 2339 #ifdef __BIG_ENDIAN_BITFIELD 2340 uint32_t rsvd1:24; 2341 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2342 #else /* __LITTLE_ENDIAN_BITFIELD */ 2343 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2344 uint32_t rsvd1:24; 2345 #endif 2346 2347 #ifdef __BIG_ENDIAN_BITFIELD 2348 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2349 uint8_t rsvd2; 2350 uint16_t link_flags; 2351 #else /* __LITTLE_ENDIAN_BITFIELD */ 2352 uint16_t link_flags; 2353 uint8_t rsvd2; 2354 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2355 #endif 2356 2357 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 2358 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 2359 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 2360 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 2361 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 2362 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 2363 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 2364 2365 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 2366 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 2367 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 2368 2369 uint32_t link_speed; 2370 #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 2371 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 2372 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 2373 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 2374 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 2375 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 2376 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 2377 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ 2378 #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */ 2379 #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */ 2380 #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */ 2381 2382 } INIT_LINK_VAR; 2383 2384 /* Structure for MB Command DOWN_LINK (06) */ 2385 2386 typedef struct { 2387 uint32_t rsvd1; 2388 } DOWN_LINK_VAR; 2389 2390 /* Structure for MB Command CONFIG_LINK (07) */ 2391 2392 typedef struct { 2393 #ifdef __BIG_ENDIAN_BITFIELD 2394 uint32_t cr:1; 2395 uint32_t ci:1; 2396 uint32_t cr_delay:6; 2397 uint32_t cr_count:8; 2398 uint32_t rsvd1:8; 2399 uint32_t MaxBBC:8; 2400 #else /* __LITTLE_ENDIAN_BITFIELD */ 2401 uint32_t MaxBBC:8; 2402 uint32_t rsvd1:8; 2403 uint32_t cr_count:8; 2404 uint32_t cr_delay:6; 2405 uint32_t ci:1; 2406 uint32_t cr:1; 2407 #endif 2408 2409 uint32_t myId; 2410 uint32_t rsvd2; 2411 uint32_t edtov; 2412 uint32_t arbtov; 2413 uint32_t ratov; 2414 uint32_t rttov; 2415 uint32_t altov; 2416 uint32_t crtov; 2417 2418 #ifdef __BIG_ENDIAN_BITFIELD 2419 uint32_t rsvd4:19; 2420 uint32_t cscn:1; 2421 uint32_t bbscn:4; 2422 uint32_t rsvd3:8; 2423 #else /* __LITTLE_ENDIAN_BITFIELD */ 2424 uint32_t rsvd3:8; 2425 uint32_t bbscn:4; 2426 uint32_t cscn:1; 2427 uint32_t rsvd4:19; 2428 #endif 2429 2430 #ifdef __BIG_ENDIAN_BITFIELD 2431 uint32_t rrq_enable:1; 2432 uint32_t rrq_immed:1; 2433 uint32_t rsvd5:29; 2434 uint32_t ack0_enable:1; 2435 #else /* __LITTLE_ENDIAN_BITFIELD */ 2436 uint32_t ack0_enable:1; 2437 uint32_t rsvd5:29; 2438 uint32_t rrq_immed:1; 2439 uint32_t rrq_enable:1; 2440 #endif 2441 } CONFIG_LINK; 2442 2443 /* Structure for MB Command PART_SLIM (08) 2444 * will be removed since SLI1 is no longer supported! 2445 */ 2446 typedef struct { 2447 #ifdef __BIG_ENDIAN_BITFIELD 2448 uint16_t offCiocb; 2449 uint16_t numCiocb; 2450 uint16_t offRiocb; 2451 uint16_t numRiocb; 2452 #else /* __LITTLE_ENDIAN_BITFIELD */ 2453 uint16_t numCiocb; 2454 uint16_t offCiocb; 2455 uint16_t numRiocb; 2456 uint16_t offRiocb; 2457 #endif 2458 } RING_DEF; 2459 2460 typedef struct { 2461 #ifdef __BIG_ENDIAN_BITFIELD 2462 uint32_t unused1:24; 2463 uint32_t numRing:8; 2464 #else /* __LITTLE_ENDIAN_BITFIELD */ 2465 uint32_t numRing:8; 2466 uint32_t unused1:24; 2467 #endif 2468 2469 RING_DEF ringdef[4]; 2470 uint32_t hbainit; 2471 } PART_SLIM_VAR; 2472 2473 /* Structure for MB Command CONFIG_RING (09) */ 2474 2475 typedef struct { 2476 #ifdef __BIG_ENDIAN_BITFIELD 2477 uint32_t unused2:6; 2478 uint32_t recvSeq:1; 2479 uint32_t recvNotify:1; 2480 uint32_t numMask:8; 2481 uint32_t profile:8; 2482 uint32_t unused1:4; 2483 uint32_t ring:4; 2484 #else /* __LITTLE_ENDIAN_BITFIELD */ 2485 uint32_t ring:4; 2486 uint32_t unused1:4; 2487 uint32_t profile:8; 2488 uint32_t numMask:8; 2489 uint32_t recvNotify:1; 2490 uint32_t recvSeq:1; 2491 uint32_t unused2:6; 2492 #endif 2493 2494 #ifdef __BIG_ENDIAN_BITFIELD 2495 uint16_t maxRespXchg; 2496 uint16_t maxOrigXchg; 2497 #else /* __LITTLE_ENDIAN_BITFIELD */ 2498 uint16_t maxOrigXchg; 2499 uint16_t maxRespXchg; 2500 #endif 2501 2502 RR_REG rrRegs[6]; 2503 } CONFIG_RING_VAR; 2504 2505 /* Structure for MB Command RESET_RING (10) */ 2506 2507 typedef struct { 2508 uint32_t ring_no; 2509 } RESET_RING_VAR; 2510 2511 /* Structure for MB Command READ_CONFIG (11) */ 2512 2513 typedef struct { 2514 #ifdef __BIG_ENDIAN_BITFIELD 2515 uint32_t cr:1; 2516 uint32_t ci:1; 2517 uint32_t cr_delay:6; 2518 uint32_t cr_count:8; 2519 uint32_t InitBBC:8; 2520 uint32_t MaxBBC:8; 2521 #else /* __LITTLE_ENDIAN_BITFIELD */ 2522 uint32_t MaxBBC:8; 2523 uint32_t InitBBC:8; 2524 uint32_t cr_count:8; 2525 uint32_t cr_delay:6; 2526 uint32_t ci:1; 2527 uint32_t cr:1; 2528 #endif 2529 2530 #ifdef __BIG_ENDIAN_BITFIELD 2531 uint32_t topology:8; 2532 uint32_t myDid:24; 2533 #else /* __LITTLE_ENDIAN_BITFIELD */ 2534 uint32_t myDid:24; 2535 uint32_t topology:8; 2536 #endif 2537 2538 /* Defines for topology (defined previously) */ 2539 #ifdef __BIG_ENDIAN_BITFIELD 2540 uint32_t AR:1; 2541 uint32_t IR:1; 2542 uint32_t rsvd1:29; 2543 uint32_t ack0:1; 2544 #else /* __LITTLE_ENDIAN_BITFIELD */ 2545 uint32_t ack0:1; 2546 uint32_t rsvd1:29; 2547 uint32_t IR:1; 2548 uint32_t AR:1; 2549 #endif 2550 2551 uint32_t edtov; 2552 uint32_t arbtov; 2553 uint32_t ratov; 2554 uint32_t rttov; 2555 uint32_t altov; 2556 uint32_t lmt; 2557 #define LMT_RESERVED 0x000 /* Not used */ 2558 #define LMT_1Gb 0x004 2559 #define LMT_2Gb 0x008 2560 #define LMT_4Gb 0x040 2561 #define LMT_8Gb 0x080 2562 #define LMT_10Gb 0x100 2563 #define LMT_16Gb 0x200 2564 #define LMT_32Gb 0x400 2565 #define LMT_64Gb 0x800 2566 #define LMT_128Gb 0x1000 2567 #define LMT_256Gb 0x2000 2568 uint32_t rsvd2; 2569 uint32_t rsvd3; 2570 uint32_t max_xri; 2571 uint32_t max_iocb; 2572 uint32_t max_rpi; 2573 uint32_t avail_xri; 2574 uint32_t avail_iocb; 2575 uint32_t avail_rpi; 2576 uint32_t max_vpi; 2577 uint32_t rsvd4; 2578 uint32_t rsvd5; 2579 uint32_t avail_vpi; 2580 } READ_CONFIG_VAR; 2581 2582 /* Structure for MB Command READ_RCONFIG (12) */ 2583 2584 typedef struct { 2585 #ifdef __BIG_ENDIAN_BITFIELD 2586 uint32_t rsvd2:7; 2587 uint32_t recvNotify:1; 2588 uint32_t numMask:8; 2589 uint32_t profile:8; 2590 uint32_t rsvd1:4; 2591 uint32_t ring:4; 2592 #else /* __LITTLE_ENDIAN_BITFIELD */ 2593 uint32_t ring:4; 2594 uint32_t rsvd1:4; 2595 uint32_t profile:8; 2596 uint32_t numMask:8; 2597 uint32_t recvNotify:1; 2598 uint32_t rsvd2:7; 2599 #endif 2600 2601 #ifdef __BIG_ENDIAN_BITFIELD 2602 uint16_t maxResp; 2603 uint16_t maxOrig; 2604 #else /* __LITTLE_ENDIAN_BITFIELD */ 2605 uint16_t maxOrig; 2606 uint16_t maxResp; 2607 #endif 2608 2609 RR_REG rrRegs[6]; 2610 2611 #ifdef __BIG_ENDIAN_BITFIELD 2612 uint16_t cmdRingOffset; 2613 uint16_t cmdEntryCnt; 2614 uint16_t rspRingOffset; 2615 uint16_t rspEntryCnt; 2616 uint16_t nextCmdOffset; 2617 uint16_t rsvd3; 2618 uint16_t nextRspOffset; 2619 uint16_t rsvd4; 2620 #else /* __LITTLE_ENDIAN_BITFIELD */ 2621 uint16_t cmdEntryCnt; 2622 uint16_t cmdRingOffset; 2623 uint16_t rspEntryCnt; 2624 uint16_t rspRingOffset; 2625 uint16_t rsvd3; 2626 uint16_t nextCmdOffset; 2627 uint16_t rsvd4; 2628 uint16_t nextRspOffset; 2629 #endif 2630 } READ_RCONF_VAR; 2631 2632 /* Structure for MB Command READ_SPARM (13) */ 2633 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2634 2635 typedef struct { 2636 uint32_t rsvd1; 2637 uint32_t rsvd2; 2638 union { 2639 struct ulp_bde sp; /* This BDE points to struct serv_parm 2640 structure */ 2641 struct ulp_bde64 sp64; 2642 } un; 2643 #ifdef __BIG_ENDIAN_BITFIELD 2644 uint16_t rsvd3; 2645 uint16_t vpi; 2646 #else /* __LITTLE_ENDIAN_BITFIELD */ 2647 uint16_t vpi; 2648 uint16_t rsvd3; 2649 #endif 2650 } READ_SPARM_VAR; 2651 2652 /* Structure for MB Command READ_STATUS (14) */ 2653 2654 typedef struct { 2655 #ifdef __BIG_ENDIAN_BITFIELD 2656 uint32_t rsvd1:31; 2657 uint32_t clrCounters:1; 2658 uint16_t activeXriCnt; 2659 uint16_t activeRpiCnt; 2660 #else /* __LITTLE_ENDIAN_BITFIELD */ 2661 uint32_t clrCounters:1; 2662 uint32_t rsvd1:31; 2663 uint16_t activeRpiCnt; 2664 uint16_t activeXriCnt; 2665 #endif 2666 2667 uint32_t xmitByteCnt; 2668 uint32_t rcvByteCnt; 2669 uint32_t xmitFrameCnt; 2670 uint32_t rcvFrameCnt; 2671 uint32_t xmitSeqCnt; 2672 uint32_t rcvSeqCnt; 2673 uint32_t totalOrigExchanges; 2674 uint32_t totalRespExchanges; 2675 uint32_t rcvPbsyCnt; 2676 uint32_t rcvFbsyCnt; 2677 } READ_STATUS_VAR; 2678 2679 /* Structure for MB Command READ_RPI (15) */ 2680 /* Structure for MB Command READ_RPI64 (0x8F) */ 2681 2682 typedef struct { 2683 #ifdef __BIG_ENDIAN_BITFIELD 2684 uint16_t nextRpi; 2685 uint16_t reqRpi; 2686 uint32_t rsvd2:8; 2687 uint32_t DID:24; 2688 #else /* __LITTLE_ENDIAN_BITFIELD */ 2689 uint16_t reqRpi; 2690 uint16_t nextRpi; 2691 uint32_t DID:24; 2692 uint32_t rsvd2:8; 2693 #endif 2694 2695 union { 2696 struct ulp_bde sp; 2697 struct ulp_bde64 sp64; 2698 } un; 2699 2700 } READ_RPI_VAR; 2701 2702 /* Structure for MB Command READ_XRI (16) */ 2703 2704 typedef struct { 2705 #ifdef __BIG_ENDIAN_BITFIELD 2706 uint16_t nextXri; 2707 uint16_t reqXri; 2708 uint16_t rsvd1; 2709 uint16_t rpi; 2710 uint32_t rsvd2:8; 2711 uint32_t DID:24; 2712 uint32_t rsvd3:8; 2713 uint32_t SID:24; 2714 uint32_t rsvd4; 2715 uint8_t seqId; 2716 uint8_t rsvd5; 2717 uint16_t seqCount; 2718 uint16_t oxId; 2719 uint16_t rxId; 2720 uint32_t rsvd6:30; 2721 uint32_t si:1; 2722 uint32_t exchOrig:1; 2723 #else /* __LITTLE_ENDIAN_BITFIELD */ 2724 uint16_t reqXri; 2725 uint16_t nextXri; 2726 uint16_t rpi; 2727 uint16_t rsvd1; 2728 uint32_t DID:24; 2729 uint32_t rsvd2:8; 2730 uint32_t SID:24; 2731 uint32_t rsvd3:8; 2732 uint32_t rsvd4; 2733 uint16_t seqCount; 2734 uint8_t rsvd5; 2735 uint8_t seqId; 2736 uint16_t rxId; 2737 uint16_t oxId; 2738 uint32_t exchOrig:1; 2739 uint32_t si:1; 2740 uint32_t rsvd6:30; 2741 #endif 2742 } READ_XRI_VAR; 2743 2744 /* Structure for MB Command READ_REV (17) */ 2745 2746 typedef struct { 2747 #ifdef __BIG_ENDIAN_BITFIELD 2748 uint32_t cv:1; 2749 uint32_t rr:1; 2750 uint32_t rsvd2:2; 2751 uint32_t v3req:1; 2752 uint32_t v3rsp:1; 2753 uint32_t rsvd1:25; 2754 uint32_t rv:1; 2755 #else /* __LITTLE_ENDIAN_BITFIELD */ 2756 uint32_t rv:1; 2757 uint32_t rsvd1:25; 2758 uint32_t v3rsp:1; 2759 uint32_t v3req:1; 2760 uint32_t rsvd2:2; 2761 uint32_t rr:1; 2762 uint32_t cv:1; 2763 #endif 2764 2765 uint32_t biuRev; 2766 uint32_t smRev; 2767 union { 2768 uint32_t smFwRev; 2769 struct { 2770 #ifdef __BIG_ENDIAN_BITFIELD 2771 uint8_t ProgType; 2772 uint8_t ProgId; 2773 uint16_t ProgVer:4; 2774 uint16_t ProgRev:4; 2775 uint16_t ProgFixLvl:2; 2776 uint16_t ProgDistType:2; 2777 uint16_t DistCnt:4; 2778 #else /* __LITTLE_ENDIAN_BITFIELD */ 2779 uint16_t DistCnt:4; 2780 uint16_t ProgDistType:2; 2781 uint16_t ProgFixLvl:2; 2782 uint16_t ProgRev:4; 2783 uint16_t ProgVer:4; 2784 uint8_t ProgId; 2785 uint8_t ProgType; 2786 #endif 2787 2788 } b; 2789 } un; 2790 uint32_t endecRev; 2791 #ifdef __BIG_ENDIAN_BITFIELD 2792 uint8_t feaLevelHigh; 2793 uint8_t feaLevelLow; 2794 uint8_t fcphHigh; 2795 uint8_t fcphLow; 2796 #else /* __LITTLE_ENDIAN_BITFIELD */ 2797 uint8_t fcphLow; 2798 uint8_t fcphHigh; 2799 uint8_t feaLevelLow; 2800 uint8_t feaLevelHigh; 2801 #endif 2802 2803 uint32_t postKernRev; 2804 uint32_t opFwRev; 2805 uint8_t opFwName[16]; 2806 uint32_t sli1FwRev; 2807 uint8_t sli1FwName[16]; 2808 uint32_t sli2FwRev; 2809 uint8_t sli2FwName[16]; 2810 uint32_t sli3Feat; 2811 uint32_t RandomData[6]; 2812 } READ_REV_VAR; 2813 2814 /* Structure for MB Command READ_LINK_STAT (18) */ 2815 2816 typedef struct { 2817 uint32_t word0; 2818 2819 #define lpfc_read_link_stat_rec_SHIFT 0 2820 #define lpfc_read_link_stat_rec_MASK 0x1 2821 #define lpfc_read_link_stat_rec_WORD word0 2822 2823 #define lpfc_read_link_stat_gec_SHIFT 1 2824 #define lpfc_read_link_stat_gec_MASK 0x1 2825 #define lpfc_read_link_stat_gec_WORD word0 2826 2827 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2 2828 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF 2829 #define lpfc_read_link_stat_w02oftow23of_WORD word0 2830 2831 #define lpfc_read_link_stat_rsvd_SHIFT 24 2832 #define lpfc_read_link_stat_rsvd_MASK 0x1F 2833 #define lpfc_read_link_stat_rsvd_WORD word0 2834 2835 #define lpfc_read_link_stat_gec2_SHIFT 29 2836 #define lpfc_read_link_stat_gec2_MASK 0x1 2837 #define lpfc_read_link_stat_gec2_WORD word0 2838 2839 #define lpfc_read_link_stat_clrc_SHIFT 30 2840 #define lpfc_read_link_stat_clrc_MASK 0x1 2841 #define lpfc_read_link_stat_clrc_WORD word0 2842 2843 #define lpfc_read_link_stat_clof_SHIFT 31 2844 #define lpfc_read_link_stat_clof_MASK 0x1 2845 #define lpfc_read_link_stat_clof_WORD word0 2846 2847 uint32_t linkFailureCnt; 2848 uint32_t lossSyncCnt; 2849 uint32_t lossSignalCnt; 2850 uint32_t primSeqErrCnt; 2851 uint32_t invalidXmitWord; 2852 uint32_t crcCnt; 2853 uint32_t primSeqTimeout; 2854 uint32_t elasticOverrun; 2855 uint32_t arbTimeout; 2856 uint32_t advRecBufCredit; 2857 uint32_t curRecBufCredit; 2858 uint32_t advTransBufCredit; 2859 uint32_t curTransBufCredit; 2860 uint32_t recEofCount; 2861 uint32_t recEofdtiCount; 2862 uint32_t recEofniCount; 2863 uint32_t recSofcount; 2864 uint32_t rsvd1; 2865 uint32_t rsvd2; 2866 uint32_t recDrpXriCount; 2867 uint32_t fecCorrBlkCount; 2868 uint32_t fecUncorrBlkCount; 2869 } READ_LNK_VAR; 2870 2871 /* Structure for MB Command REG_LOGIN (19) */ 2872 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2873 2874 typedef struct { 2875 #ifdef __BIG_ENDIAN_BITFIELD 2876 uint16_t rsvd1; 2877 uint16_t rpi; 2878 uint32_t rsvd2:8; 2879 uint32_t did:24; 2880 #else /* __LITTLE_ENDIAN_BITFIELD */ 2881 uint16_t rpi; 2882 uint16_t rsvd1; 2883 uint32_t did:24; 2884 uint32_t rsvd2:8; 2885 #endif 2886 2887 union { 2888 struct ulp_bde sp; 2889 struct ulp_bde64 sp64; 2890 } un; 2891 2892 #ifdef __BIG_ENDIAN_BITFIELD 2893 uint16_t rsvd6; 2894 uint16_t vpi; 2895 #else /* __LITTLE_ENDIAN_BITFIELD */ 2896 uint16_t vpi; 2897 uint16_t rsvd6; 2898 #endif 2899 2900 } REG_LOGIN_VAR; 2901 2902 /* Word 30 contents for REG_LOGIN */ 2903 typedef union { 2904 struct { 2905 #ifdef __BIG_ENDIAN_BITFIELD 2906 uint16_t rsvd1:12; 2907 uint16_t wd30_class:4; 2908 uint16_t xri; 2909 #else /* __LITTLE_ENDIAN_BITFIELD */ 2910 uint16_t xri; 2911 uint16_t wd30_class:4; 2912 uint16_t rsvd1:12; 2913 #endif 2914 } f; 2915 uint32_t word; 2916 } REG_WD30; 2917 2918 /* Structure for MB Command UNREG_LOGIN (20) */ 2919 2920 typedef struct { 2921 #ifdef __BIG_ENDIAN_BITFIELD 2922 uint16_t rsvd1; 2923 uint16_t rpi; 2924 uint32_t rsvd2; 2925 uint32_t rsvd3; 2926 uint32_t rsvd4; 2927 uint32_t rsvd5; 2928 uint16_t rsvd6; 2929 uint16_t vpi; 2930 #else /* __LITTLE_ENDIAN_BITFIELD */ 2931 uint16_t rpi; 2932 uint16_t rsvd1; 2933 uint32_t rsvd2; 2934 uint32_t rsvd3; 2935 uint32_t rsvd4; 2936 uint32_t rsvd5; 2937 uint16_t vpi; 2938 uint16_t rsvd6; 2939 #endif 2940 } UNREG_LOGIN_VAR; 2941 2942 /* Structure for MB Command REG_VPI (0x96) */ 2943 typedef struct { 2944 #ifdef __BIG_ENDIAN_BITFIELD 2945 uint32_t rsvd1; 2946 uint32_t rsvd2:7; 2947 uint32_t upd:1; 2948 uint32_t sid:24; 2949 uint32_t wwn[2]; 2950 uint32_t rsvd5; 2951 uint16_t vfi; 2952 uint16_t vpi; 2953 #else /* __LITTLE_ENDIAN */ 2954 uint32_t rsvd1; 2955 uint32_t sid:24; 2956 uint32_t upd:1; 2957 uint32_t rsvd2:7; 2958 uint32_t wwn[2]; 2959 uint32_t rsvd5; 2960 uint16_t vpi; 2961 uint16_t vfi; 2962 #endif 2963 } REG_VPI_VAR; 2964 2965 /* Structure for MB Command UNREG_VPI (0x97) */ 2966 typedef struct { 2967 uint32_t rsvd1; 2968 #ifdef __BIG_ENDIAN_BITFIELD 2969 uint16_t rsvd2; 2970 uint16_t sli4_vpi; 2971 #else /* __LITTLE_ENDIAN */ 2972 uint16_t sli4_vpi; 2973 uint16_t rsvd2; 2974 #endif 2975 uint32_t rsvd3; 2976 uint32_t rsvd4; 2977 uint32_t rsvd5; 2978 #ifdef __BIG_ENDIAN_BITFIELD 2979 uint16_t rsvd6; 2980 uint16_t vpi; 2981 #else /* __LITTLE_ENDIAN */ 2982 uint16_t vpi; 2983 uint16_t rsvd6; 2984 #endif 2985 } UNREG_VPI_VAR; 2986 2987 /* Structure for MB Command UNREG_D_ID (0x23) */ 2988 2989 typedef struct { 2990 uint32_t did; 2991 uint32_t rsvd2; 2992 uint32_t rsvd3; 2993 uint32_t rsvd4; 2994 uint32_t rsvd5; 2995 #ifdef __BIG_ENDIAN_BITFIELD 2996 uint16_t rsvd6; 2997 uint16_t vpi; 2998 #else 2999 uint16_t vpi; 3000 uint16_t rsvd6; 3001 #endif 3002 } UNREG_D_ID_VAR; 3003 3004 /* Structure for MB Command READ_TOPOLOGY (0x95) */ 3005 struct lpfc_mbx_read_top { 3006 uint32_t eventTag; /* Event tag */ 3007 uint32_t word2; 3008 #define lpfc_mbx_read_top_fa_SHIFT 12 3009 #define lpfc_mbx_read_top_fa_MASK 0x00000001 3010 #define lpfc_mbx_read_top_fa_WORD word2 3011 #define lpfc_mbx_read_top_mm_SHIFT 11 3012 #define lpfc_mbx_read_top_mm_MASK 0x00000001 3013 #define lpfc_mbx_read_top_mm_WORD word2 3014 #define lpfc_mbx_read_top_pb_SHIFT 9 3015 #define lpfc_mbx_read_top_pb_MASK 0X00000001 3016 #define lpfc_mbx_read_top_pb_WORD word2 3017 #define lpfc_mbx_read_top_il_SHIFT 8 3018 #define lpfc_mbx_read_top_il_MASK 0x00000001 3019 #define lpfc_mbx_read_top_il_WORD word2 3020 #define lpfc_mbx_read_top_att_type_SHIFT 0 3021 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 3022 #define lpfc_mbx_read_top_att_type_WORD word2 3023 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 3024 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 3025 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 3026 #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */ 3027 uint32_t word3; 3028 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 3029 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 3030 #define lpfc_mbx_read_top_alpa_granted_WORD word3 3031 #define lpfc_mbx_read_top_lip_alps_SHIFT 16 3032 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 3033 #define lpfc_mbx_read_top_lip_alps_WORD word3 3034 #define lpfc_mbx_read_top_lip_type_SHIFT 8 3035 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 3036 #define lpfc_mbx_read_top_lip_type_WORD word3 3037 #define lpfc_mbx_read_top_topology_SHIFT 0 3038 #define lpfc_mbx_read_top_topology_MASK 0x000000FF 3039 #define lpfc_mbx_read_top_topology_WORD word3 3040 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 3041 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 3042 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ 3043 /* store the LILP AL_PA position map into */ 3044 struct ulp_bde64 lilpBde64; 3045 #define LPFC_ALPA_MAP_SIZE 128 3046 uint32_t word7; 3047 #define lpfc_mbx_read_top_ld_lu_SHIFT 31 3048 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 3049 #define lpfc_mbx_read_top_ld_lu_WORD word7 3050 #define lpfc_mbx_read_top_ld_tf_SHIFT 30 3051 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 3052 #define lpfc_mbx_read_top_ld_tf_WORD word7 3053 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 3054 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 3055 #define lpfc_mbx_read_top_ld_link_spd_WORD word7 3056 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 3057 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 3058 #define lpfc_mbx_read_top_ld_nl_port_WORD word7 3059 #define lpfc_mbx_read_top_ld_tx_SHIFT 2 3060 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 3061 #define lpfc_mbx_read_top_ld_tx_WORD word7 3062 #define lpfc_mbx_read_top_ld_rx_SHIFT 0 3063 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 3064 #define lpfc_mbx_read_top_ld_rx_WORD word7 3065 uint32_t word8; 3066 #define lpfc_mbx_read_top_lu_SHIFT 31 3067 #define lpfc_mbx_read_top_lu_MASK 0x00000001 3068 #define lpfc_mbx_read_top_lu_WORD word8 3069 #define lpfc_mbx_read_top_tf_SHIFT 30 3070 #define lpfc_mbx_read_top_tf_MASK 0x00000001 3071 #define lpfc_mbx_read_top_tf_WORD word8 3072 #define lpfc_mbx_read_top_link_spd_SHIFT 8 3073 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 3074 #define lpfc_mbx_read_top_link_spd_WORD word8 3075 #define lpfc_mbx_read_top_nl_port_SHIFT 4 3076 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 3077 #define lpfc_mbx_read_top_nl_port_WORD word8 3078 #define lpfc_mbx_read_top_tx_SHIFT 2 3079 #define lpfc_mbx_read_top_tx_MASK 0x00000003 3080 #define lpfc_mbx_read_top_tx_WORD word8 3081 #define lpfc_mbx_read_top_rx_SHIFT 0 3082 #define lpfc_mbx_read_top_rx_MASK 0x00000003 3083 #define lpfc_mbx_read_top_rx_WORD word8 3084 #define LPFC_LINK_SPEED_UNKNOWN 0x0 3085 #define LPFC_LINK_SPEED_1GHZ 0x04 3086 #define LPFC_LINK_SPEED_2GHZ 0x08 3087 #define LPFC_LINK_SPEED_4GHZ 0x10 3088 #define LPFC_LINK_SPEED_8GHZ 0x20 3089 #define LPFC_LINK_SPEED_10GHZ 0x40 3090 #define LPFC_LINK_SPEED_16GHZ 0x80 3091 #define LPFC_LINK_SPEED_32GHZ 0x90 3092 #define LPFC_LINK_SPEED_64GHZ 0xA0 3093 #define LPFC_LINK_SPEED_128GHZ 0xB0 3094 #define LPFC_LINK_SPEED_256GHZ 0xC0 3095 }; 3096 3097 /* Structure for MB Command CLEAR_LA (22) */ 3098 3099 typedef struct { 3100 uint32_t eventTag; /* Event tag */ 3101 uint32_t rsvd1; 3102 } CLEAR_LA_VAR; 3103 3104 /* Structure for MB Command DUMP */ 3105 3106 typedef struct { 3107 #ifdef __BIG_ENDIAN_BITFIELD 3108 uint32_t rsvd:25; 3109 uint32_t ra:1; 3110 uint32_t co:1; 3111 uint32_t cv:1; 3112 uint32_t type:4; 3113 uint32_t entry_index:16; 3114 uint32_t region_id:16; 3115 #else /* __LITTLE_ENDIAN_BITFIELD */ 3116 uint32_t type:4; 3117 uint32_t cv:1; 3118 uint32_t co:1; 3119 uint32_t ra:1; 3120 uint32_t rsvd:25; 3121 uint32_t region_id:16; 3122 uint32_t entry_index:16; 3123 #endif 3124 3125 uint32_t sli4_length; 3126 uint32_t word_cnt; 3127 uint32_t resp_offset; 3128 } DUMP_VAR; 3129 3130 #define DMP_MEM_REG 0x1 3131 #define DMP_NV_PARAMS 0x2 3132 #define DMP_LMSD 0x3 /* Link Module Serial Data */ 3133 #define DMP_WELL_KNOWN 0x4 3134 3135 #define DMP_REGION_VPD 0xe 3136 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 3137 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 3138 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 3139 3140 #define DMP_REGION_VPORT 0x16 /* VPort info region */ 3141 #define DMP_VPORT_REGION_SIZE 0x200 3142 #define DMP_MBOX_OFFSET_WORD 0x5 3143 3144 #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 3145 #define DMP_RGN23_SIZE 0x400 3146 3147 #define WAKE_UP_PARMS_REGION_ID 4 3148 #define WAKE_UP_PARMS_WORD_SIZE 15 3149 3150 struct vport_rec { 3151 uint8_t wwpn[8]; 3152 uint8_t wwnn[8]; 3153 }; 3154 3155 #define VPORT_INFO_SIG 0x32324752 3156 #define VPORT_INFO_REV_MASK 0xff 3157 #define VPORT_INFO_REV 0x1 3158 #define MAX_STATIC_VPORT_COUNT 16 3159 struct static_vport_info { 3160 uint32_t signature; 3161 uint32_t rev; 3162 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 3163 uint32_t resvd[66]; 3164 }; 3165 3166 /* Option rom version structure */ 3167 struct prog_id { 3168 #ifdef __BIG_ENDIAN_BITFIELD 3169 uint8_t type; 3170 uint8_t id; 3171 uint32_t ver:4; /* Major Version */ 3172 uint32_t rev:4; /* Revision */ 3173 uint32_t lev:2; /* Level */ 3174 uint32_t dist:2; /* Dist Type */ 3175 uint32_t num:4; /* number after dist type */ 3176 #else /* __LITTLE_ENDIAN_BITFIELD */ 3177 uint32_t num:4; /* number after dist type */ 3178 uint32_t dist:2; /* Dist Type */ 3179 uint32_t lev:2; /* Level */ 3180 uint32_t rev:4; /* Revision */ 3181 uint32_t ver:4; /* Major Version */ 3182 uint8_t id; 3183 uint8_t type; 3184 #endif 3185 }; 3186 3187 /* Structure for MB Command UPDATE_CFG (0x1B) */ 3188 3189 struct update_cfg_var { 3190 #ifdef __BIG_ENDIAN_BITFIELD 3191 uint32_t rsvd2:16; 3192 uint32_t type:8; 3193 uint32_t rsvd:1; 3194 uint32_t ra:1; 3195 uint32_t co:1; 3196 uint32_t cv:1; 3197 uint32_t req:4; 3198 uint32_t entry_length:16; 3199 uint32_t region_id:16; 3200 #else /* __LITTLE_ENDIAN_BITFIELD */ 3201 uint32_t req:4; 3202 uint32_t cv:1; 3203 uint32_t co:1; 3204 uint32_t ra:1; 3205 uint32_t rsvd:1; 3206 uint32_t type:8; 3207 uint32_t rsvd2:16; 3208 uint32_t region_id:16; 3209 uint32_t entry_length:16; 3210 #endif 3211 3212 uint32_t resp_info; 3213 uint32_t byte_cnt; 3214 uint32_t data_offset; 3215 }; 3216 3217 struct hbq_mask { 3218 #ifdef __BIG_ENDIAN_BITFIELD 3219 uint8_t tmatch; 3220 uint8_t tmask; 3221 uint8_t rctlmatch; 3222 uint8_t rctlmask; 3223 #else /* __LITTLE_ENDIAN */ 3224 uint8_t rctlmask; 3225 uint8_t rctlmatch; 3226 uint8_t tmask; 3227 uint8_t tmatch; 3228 #endif 3229 }; 3230 3231 3232 /* Structure for MB Command CONFIG_HBQ (7c) */ 3233 3234 struct config_hbq_var { 3235 #ifdef __BIG_ENDIAN_BITFIELD 3236 uint32_t rsvd1 :7; 3237 uint32_t recvNotify :1; /* Receive Notification */ 3238 uint32_t numMask :8; /* # Mask Entries */ 3239 uint32_t profile :8; /* Selection Profile */ 3240 uint32_t rsvd2 :8; 3241 #else /* __LITTLE_ENDIAN */ 3242 uint32_t rsvd2 :8; 3243 uint32_t profile :8; /* Selection Profile */ 3244 uint32_t numMask :8; /* # Mask Entries */ 3245 uint32_t recvNotify :1; /* Receive Notification */ 3246 uint32_t rsvd1 :7; 3247 #endif 3248 3249 #ifdef __BIG_ENDIAN_BITFIELD 3250 uint32_t hbqId :16; 3251 uint32_t rsvd3 :12; 3252 uint32_t ringMask :4; 3253 #else /* __LITTLE_ENDIAN */ 3254 uint32_t ringMask :4; 3255 uint32_t rsvd3 :12; 3256 uint32_t hbqId :16; 3257 #endif 3258 3259 #ifdef __BIG_ENDIAN_BITFIELD 3260 uint32_t entry_count :16; 3261 uint32_t rsvd4 :8; 3262 uint32_t headerLen :8; 3263 #else /* __LITTLE_ENDIAN */ 3264 uint32_t headerLen :8; 3265 uint32_t rsvd4 :8; 3266 uint32_t entry_count :16; 3267 #endif 3268 3269 uint32_t hbqaddrLow; 3270 uint32_t hbqaddrHigh; 3271 3272 #ifdef __BIG_ENDIAN_BITFIELD 3273 uint32_t rsvd5 :31; 3274 uint32_t logEntry :1; 3275 #else /* __LITTLE_ENDIAN */ 3276 uint32_t logEntry :1; 3277 uint32_t rsvd5 :31; 3278 #endif 3279 3280 uint32_t rsvd6; /* w7 */ 3281 uint32_t rsvd7; /* w8 */ 3282 uint32_t rsvd8; /* w9 */ 3283 3284 struct hbq_mask hbqMasks[6]; 3285 3286 3287 union { 3288 uint32_t allprofiles[12]; 3289 3290 struct { 3291 #ifdef __BIG_ENDIAN_BITFIELD 3292 uint32_t seqlenoff :16; 3293 uint32_t maxlen :16; 3294 #else /* __LITTLE_ENDIAN */ 3295 uint32_t maxlen :16; 3296 uint32_t seqlenoff :16; 3297 #endif 3298 #ifdef __BIG_ENDIAN_BITFIELD 3299 uint32_t rsvd1 :28; 3300 uint32_t seqlenbcnt :4; 3301 #else /* __LITTLE_ENDIAN */ 3302 uint32_t seqlenbcnt :4; 3303 uint32_t rsvd1 :28; 3304 #endif 3305 uint32_t rsvd[10]; 3306 } profile2; 3307 3308 struct { 3309 #ifdef __BIG_ENDIAN_BITFIELD 3310 uint32_t seqlenoff :16; 3311 uint32_t maxlen :16; 3312 #else /* __LITTLE_ENDIAN */ 3313 uint32_t maxlen :16; 3314 uint32_t seqlenoff :16; 3315 #endif 3316 #ifdef __BIG_ENDIAN_BITFIELD 3317 uint32_t cmdcodeoff :28; 3318 uint32_t rsvd1 :12; 3319 uint32_t seqlenbcnt :4; 3320 #else /* __LITTLE_ENDIAN */ 3321 uint32_t seqlenbcnt :4; 3322 uint32_t rsvd1 :12; 3323 uint32_t cmdcodeoff :28; 3324 #endif 3325 uint32_t cmdmatch[8]; 3326 3327 uint32_t rsvd[2]; 3328 } profile3; 3329 3330 struct { 3331 #ifdef __BIG_ENDIAN_BITFIELD 3332 uint32_t seqlenoff :16; 3333 uint32_t maxlen :16; 3334 #else /* __LITTLE_ENDIAN */ 3335 uint32_t maxlen :16; 3336 uint32_t seqlenoff :16; 3337 #endif 3338 #ifdef __BIG_ENDIAN_BITFIELD 3339 uint32_t cmdcodeoff :28; 3340 uint32_t rsvd1 :12; 3341 uint32_t seqlenbcnt :4; 3342 #else /* __LITTLE_ENDIAN */ 3343 uint32_t seqlenbcnt :4; 3344 uint32_t rsvd1 :12; 3345 uint32_t cmdcodeoff :28; 3346 #endif 3347 uint32_t cmdmatch[8]; 3348 3349 uint32_t rsvd[2]; 3350 } profile5; 3351 3352 } profiles; 3353 3354 }; 3355 3356 3357 3358 /* Structure for MB Command CONFIG_PORT (0x88) */ 3359 typedef struct { 3360 #ifdef __BIG_ENDIAN_BITFIELD 3361 uint32_t cBE : 1; 3362 uint32_t cET : 1; 3363 uint32_t cHpcb : 1; 3364 uint32_t cMA : 1; 3365 uint32_t sli_mode : 4; 3366 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3367 * config block */ 3368 #else /* __LITTLE_ENDIAN */ 3369 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3370 * config block */ 3371 uint32_t sli_mode : 4; 3372 uint32_t cMA : 1; 3373 uint32_t cHpcb : 1; 3374 uint32_t cET : 1; 3375 uint32_t cBE : 1; 3376 #endif 3377 3378 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 3379 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 3380 uint32_t hbainit[5]; 3381 #ifdef __BIG_ENDIAN_BITFIELD 3382 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3383 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3384 #else /* __LITTLE_ENDIAN */ 3385 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3386 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3387 #endif 3388 3389 #ifdef __BIG_ENDIAN_BITFIELD 3390 uint32_t rsvd1 : 20; /* Reserved */ 3391 uint32_t casabt : 1; /* Configure async abts status notice */ 3392 uint32_t rsvd2 : 2; /* Reserved */ 3393 uint32_t cbg : 1; /* Configure BlockGuard */ 3394 uint32_t cmv : 1; /* Configure Max VPIs */ 3395 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3396 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3397 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3398 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3399 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3400 uint32_t cmx : 1; /* Configure Max XRIs */ 3401 uint32_t cmr : 1; /* Configure Max RPIs */ 3402 #else /* __LITTLE_ENDIAN */ 3403 uint32_t cmr : 1; /* Configure Max RPIs */ 3404 uint32_t cmx : 1; /* Configure Max XRIs */ 3405 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3406 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3407 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3408 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3409 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3410 uint32_t cmv : 1; /* Configure Max VPIs */ 3411 uint32_t cbg : 1; /* Configure BlockGuard */ 3412 uint32_t rsvd2 : 2; /* Reserved */ 3413 uint32_t casabt : 1; /* Configure async abts status notice */ 3414 uint32_t rsvd1 : 20; /* Reserved */ 3415 #endif 3416 #ifdef __BIG_ENDIAN_BITFIELD 3417 uint32_t rsvd3 : 20; /* Reserved */ 3418 uint32_t gasabt : 1; /* Grant async abts status notice */ 3419 uint32_t rsvd4 : 2; /* Reserved */ 3420 uint32_t gbg : 1; /* Grant BlockGuard */ 3421 uint32_t gmv : 1; /* Grant Max VPIs */ 3422 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3423 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3424 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3425 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3426 uint32_t gerbm : 1; /* Grant ERBM Request */ 3427 uint32_t gmx : 1; /* Grant Max XRIs */ 3428 uint32_t gmr : 1; /* Grant Max RPIs */ 3429 #else /* __LITTLE_ENDIAN */ 3430 uint32_t gmr : 1; /* Grant Max RPIs */ 3431 uint32_t gmx : 1; /* Grant Max XRIs */ 3432 uint32_t gerbm : 1; /* Grant ERBM Request */ 3433 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3434 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3435 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3436 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3437 uint32_t gmv : 1; /* Grant Max VPIs */ 3438 uint32_t gbg : 1; /* Grant BlockGuard */ 3439 uint32_t rsvd4 : 2; /* Reserved */ 3440 uint32_t gasabt : 1; /* Grant async abts status notice */ 3441 uint32_t rsvd3 : 20; /* Reserved */ 3442 #endif 3443 3444 #ifdef __BIG_ENDIAN_BITFIELD 3445 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3446 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3447 #else /* __LITTLE_ENDIAN */ 3448 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3449 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3450 #endif 3451 3452 #ifdef __BIG_ENDIAN_BITFIELD 3453 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3454 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3455 #else /* __LITTLE_ENDIAN */ 3456 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3457 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3458 #endif 3459 3460 uint32_t rsvd6; /* Reserved */ 3461 3462 #ifdef __BIG_ENDIAN_BITFIELD 3463 uint32_t rsvd7 : 16; 3464 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3465 #else /* __LITTLE_ENDIAN */ 3466 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3467 uint32_t rsvd7 : 16; 3468 #endif 3469 3470 } CONFIG_PORT_VAR; 3471 3472 /* Structure for MB Command CONFIG_MSI (0x30) */ 3473 struct config_msi_var { 3474 #ifdef __BIG_ENDIAN_BITFIELD 3475 uint32_t dfltMsgNum:8; /* Default message number */ 3476 uint32_t rsvd1:11; /* Reserved */ 3477 uint32_t NID:5; /* Number of secondary attention IDs */ 3478 uint32_t rsvd2:5; /* Reserved */ 3479 uint32_t dfltPresent:1; /* Default message number present */ 3480 uint32_t addFlag:1; /* Add association flag */ 3481 uint32_t reportFlag:1; /* Report association flag */ 3482 #else /* __LITTLE_ENDIAN_BITFIELD */ 3483 uint32_t reportFlag:1; /* Report association flag */ 3484 uint32_t addFlag:1; /* Add association flag */ 3485 uint32_t dfltPresent:1; /* Default message number present */ 3486 uint32_t rsvd2:5; /* Reserved */ 3487 uint32_t NID:5; /* Number of secondary attention IDs */ 3488 uint32_t rsvd1:11; /* Reserved */ 3489 uint32_t dfltMsgNum:8; /* Default message number */ 3490 #endif 3491 uint32_t attentionConditions[2]; 3492 uint8_t attentionId[16]; 3493 uint8_t messageNumberByHA[64]; 3494 uint8_t messageNumberByID[16]; 3495 uint32_t autoClearHA[2]; 3496 #ifdef __BIG_ENDIAN_BITFIELD 3497 uint32_t rsvd3:16; 3498 uint32_t autoClearID:16; 3499 #else /* __LITTLE_ENDIAN_BITFIELD */ 3500 uint32_t autoClearID:16; 3501 uint32_t rsvd3:16; 3502 #endif 3503 uint32_t rsvd4; 3504 }; 3505 3506 /* SLI-2 Port Control Block */ 3507 3508 /* SLIM POINTER */ 3509 #define SLIMOFF 0x30 /* WORD */ 3510 3511 typedef struct _SLI2_RDSC { 3512 uint32_t cmdEntries; 3513 uint32_t cmdAddrLow; 3514 uint32_t cmdAddrHigh; 3515 3516 uint32_t rspEntries; 3517 uint32_t rspAddrLow; 3518 uint32_t rspAddrHigh; 3519 } SLI2_RDSC; 3520 3521 typedef struct _PCB { 3522 #ifdef __BIG_ENDIAN_BITFIELD 3523 uint32_t type:8; 3524 #define TYPE_NATIVE_SLI2 0x01 3525 uint32_t feature:8; 3526 #define FEATURE_INITIAL_SLI2 0x01 3527 uint32_t rsvd:12; 3528 uint32_t maxRing:4; 3529 #else /* __LITTLE_ENDIAN_BITFIELD */ 3530 uint32_t maxRing:4; 3531 uint32_t rsvd:12; 3532 uint32_t feature:8; 3533 #define FEATURE_INITIAL_SLI2 0x01 3534 uint32_t type:8; 3535 #define TYPE_NATIVE_SLI2 0x01 3536 #endif 3537 3538 uint32_t mailBoxSize; 3539 uint32_t mbAddrLow; 3540 uint32_t mbAddrHigh; 3541 3542 uint32_t hgpAddrLow; 3543 uint32_t hgpAddrHigh; 3544 3545 uint32_t pgpAddrLow; 3546 uint32_t pgpAddrHigh; 3547 SLI2_RDSC rdsc[MAX_SLI3_RINGS]; 3548 } PCB_t; 3549 3550 /* NEW_FEATURE */ 3551 typedef struct { 3552 #ifdef __BIG_ENDIAN_BITFIELD 3553 uint32_t rsvd0:27; 3554 uint32_t discardFarp:1; 3555 uint32_t IPEnable:1; 3556 uint32_t nodeName:1; 3557 uint32_t portName:1; 3558 uint32_t filterEnable:1; 3559 #else /* __LITTLE_ENDIAN_BITFIELD */ 3560 uint32_t filterEnable:1; 3561 uint32_t portName:1; 3562 uint32_t nodeName:1; 3563 uint32_t IPEnable:1; 3564 uint32_t discardFarp:1; 3565 uint32_t rsvd:27; 3566 #endif 3567 3568 uint8_t portname[8]; /* Used to be struct lpfc_name */ 3569 uint8_t nodename[8]; 3570 uint32_t rsvd1; 3571 uint32_t rsvd2; 3572 uint32_t rsvd3; 3573 uint32_t IPAddress; 3574 } CONFIG_FARP_VAR; 3575 3576 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 3577 3578 typedef struct { 3579 #ifdef __BIG_ENDIAN_BITFIELD 3580 uint32_t rsvd:30; 3581 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3582 #else /* __LITTLE_ENDIAN */ 3583 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3584 uint32_t rsvd:30; 3585 #endif 3586 } ASYNCEVT_ENABLE_VAR; 3587 3588 /* Union of all Mailbox Command types */ 3589 #define MAILBOX_CMD_WSIZE 32 3590 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 3591 /* ext_wsize times 4 bytes should not be greater than max xmit size */ 3592 #define MAILBOX_EXT_WSIZE 512 3593 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 3594 #define MAILBOX_HBA_EXT_OFFSET 0x100 3595 /* max mbox xmit size is a page size for sysfs IO operations */ 3596 #define MAILBOX_SYSFS_MAX 4096 3597 3598 typedef union { 3599 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3600 * feature/max ring number 3601 */ 3602 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3603 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3604 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3605 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3606 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3607 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3608 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3609 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3610 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3611 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3612 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3613 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3614 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3615 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3616 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3617 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3618 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3619 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3620 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3621 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3622 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3623 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3624 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3625 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3626 * NEW_FEATURE 3627 */ 3628 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3629 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3630 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3631 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 3632 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3633 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3634 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3635 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3636 * (READ_EVENT_LOG) 3637 */ 3638 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3639 } MAILVARIANTS; 3640 3641 /* 3642 * SLI-2 specific structures 3643 */ 3644 3645 struct lpfc_hgp { 3646 __le32 cmdPutInx; 3647 __le32 rspGetInx; 3648 }; 3649 3650 struct lpfc_pgp { 3651 __le32 cmdGetInx; 3652 __le32 rspPutInx; 3653 }; 3654 3655 struct sli2_desc { 3656 uint32_t unused1[16]; 3657 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3658 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3659 }; 3660 3661 struct sli3_desc { 3662 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3663 uint32_t reserved[8]; 3664 uint32_t hbq_put[16]; 3665 }; 3666 3667 struct sli3_pgp { 3668 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3669 uint32_t hbq_get[16]; 3670 }; 3671 3672 union sli_var { 3673 struct sli2_desc s2; 3674 struct sli3_desc s3; 3675 struct sli3_pgp s3_pgp; 3676 }; 3677 3678 typedef struct { 3679 struct_group_tagged(MAILBOX_word0, bits, 3680 union { 3681 struct { 3682 #ifdef __BIG_ENDIAN_BITFIELD 3683 uint16_t mbxStatus; 3684 uint8_t mbxCommand; 3685 uint8_t mbxReserved:6; 3686 uint8_t mbxHc:1; 3687 uint8_t mbxOwner:1; /* Low order bit first word */ 3688 #else /* __LITTLE_ENDIAN_BITFIELD */ 3689 uint8_t mbxOwner:1; /* Low order bit first word */ 3690 uint8_t mbxHc:1; 3691 uint8_t mbxReserved:6; 3692 uint8_t mbxCommand; 3693 uint16_t mbxStatus; 3694 #endif 3695 }; 3696 u32 word0; 3697 }; 3698 ); 3699 3700 MAILVARIANTS un; 3701 union sli_var us; 3702 } MAILBOX_t; 3703 3704 /* 3705 * Begin Structure Definitions for IOCB Commands 3706 */ 3707 3708 typedef struct { 3709 #ifdef __BIG_ENDIAN_BITFIELD 3710 uint8_t statAction; 3711 uint8_t statRsn; 3712 uint8_t statBaExp; 3713 uint8_t statLocalError; 3714 #else /* __LITTLE_ENDIAN_BITFIELD */ 3715 uint8_t statLocalError; 3716 uint8_t statBaExp; 3717 uint8_t statRsn; 3718 uint8_t statAction; 3719 #endif 3720 /* statRsn P/F_RJT reason codes */ 3721 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3722 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3723 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3724 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3725 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3726 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3727 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3728 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3729 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3730 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3731 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3732 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3733 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3734 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3735 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3736 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3737 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3738 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3739 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3740 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3741 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3742 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3743 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3744 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3745 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3746 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3747 3748 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3749 #define IOERR_MISSING_CONTINUE 0x01 3750 #define IOERR_SEQUENCE_TIMEOUT 0x02 3751 #define IOERR_INTERNAL_ERROR 0x03 3752 #define IOERR_INVALID_RPI 0x04 3753 #define IOERR_NO_XRI 0x05 3754 #define IOERR_ILLEGAL_COMMAND 0x06 3755 #define IOERR_XCHG_DROPPED 0x07 3756 #define IOERR_ILLEGAL_FIELD 0x08 3757 #define IOERR_RPI_SUSPENDED 0x09 3758 #define IOERR_TOO_MANY_BUFFERS 0x0A 3759 #define IOERR_RCV_BUFFER_WAITING 0x0B 3760 #define IOERR_NO_CONNECTION 0x0C 3761 #define IOERR_TX_DMA_FAILED 0x0D 3762 #define IOERR_RX_DMA_FAILED 0x0E 3763 #define IOERR_ILLEGAL_FRAME 0x0F 3764 #define IOERR_EXTRA_DATA 0x10 3765 #define IOERR_NO_RESOURCES 0x11 3766 #define IOERR_RESERVED 0x12 3767 #define IOERR_ILLEGAL_LENGTH 0x13 3768 #define IOERR_UNSUPPORTED_FEATURE 0x14 3769 #define IOERR_ABORT_IN_PROGRESS 0x15 3770 #define IOERR_ABORT_REQUESTED 0x16 3771 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3772 #define IOERR_LOOP_OPEN_FAILURE 0x18 3773 #define IOERR_RING_RESET 0x19 3774 #define IOERR_LINK_DOWN 0x1A 3775 #define IOERR_CORRUPTED_DATA 0x1B 3776 #define IOERR_CORRUPTED_RPI 0x1C 3777 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3778 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3779 #define IOERR_DUP_FRAME 0x1F 3780 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3781 #define IOERR_BAD_HOST_ADDRESS 0x21 3782 #define IOERR_RCV_HDRBUF_WAITING 0x22 3783 #define IOERR_MISSING_HDR_BUFFER 0x23 3784 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3785 #define IOERR_ABORTMULT_REQUESTED 0x25 3786 #define IOERR_BUFFER_SHORTAGE 0x28 3787 #define IOERR_DEFAULT 0x29 3788 #define IOERR_CNT 0x2A 3789 #define IOERR_SLER_FAILURE 0x46 3790 #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3791 #define IOERR_SLER_REC_RJT_ERR 0x48 3792 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3793 #define IOERR_SLER_SRR_RJT_ERR 0x4A 3794 #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3795 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3796 #define IOERR_SLER_ABTS_ERR 0x4E 3797 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3798 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3799 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3800 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3801 #define IOERR_DRVR_MASK 0x100 3802 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3803 #define IOERR_SLI_BRESET 0x102 3804 #define IOERR_SLI_ABORTED 0x103 3805 #define IOERR_PARAM_MASK 0x1ff 3806 } PARM_ERR; 3807 3808 typedef union { 3809 struct { 3810 #ifdef __BIG_ENDIAN_BITFIELD 3811 uint8_t Rctl; /* R_CTL field */ 3812 uint8_t Type; /* TYPE field */ 3813 uint8_t Dfctl; /* DF_CTL field */ 3814 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3815 #else /* __LITTLE_ENDIAN_BITFIELD */ 3816 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3817 uint8_t Dfctl; /* DF_CTL field */ 3818 uint8_t Type; /* TYPE field */ 3819 uint8_t Rctl; /* R_CTL field */ 3820 #endif 3821 3822 #define BC 0x02 /* Broadcast Received - Fctl */ 3823 #define SI 0x04 /* Sequence Initiative */ 3824 #define LA 0x08 /* Ignore Link Attention state */ 3825 #define LS 0x80 /* Last Sequence */ 3826 } hcsw; 3827 uint32_t reserved; 3828 } WORD5; 3829 3830 /* IOCB Command template for a generic response */ 3831 typedef struct { 3832 uint32_t reserved[4]; 3833 PARM_ERR perr; 3834 } GENERIC_RSP; 3835 3836 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3837 typedef struct { 3838 struct ulp_bde xrsqbde[2]; 3839 uint32_t xrsqRo; /* Starting Relative Offset */ 3840 WORD5 w5; /* Header control/status word */ 3841 } XR_SEQ_FIELDS; 3842 3843 /* IOCB Command template for ELS_REQUEST */ 3844 typedef struct { 3845 struct ulp_bde elsReq; 3846 struct ulp_bde elsRsp; 3847 3848 #ifdef __BIG_ENDIAN_BITFIELD 3849 uint32_t word4Rsvd:7; 3850 uint32_t fl:1; 3851 uint32_t myID:24; 3852 uint32_t word5Rsvd:8; 3853 uint32_t remoteID:24; 3854 #else /* __LITTLE_ENDIAN_BITFIELD */ 3855 uint32_t myID:24; 3856 uint32_t fl:1; 3857 uint32_t word4Rsvd:7; 3858 uint32_t remoteID:24; 3859 uint32_t word5Rsvd:8; 3860 #endif 3861 } ELS_REQUEST; 3862 3863 /* IOCB Command template for RCV_ELS_REQ */ 3864 typedef struct { 3865 struct ulp_bde elsReq[2]; 3866 uint32_t parmRo; 3867 3868 #ifdef __BIG_ENDIAN_BITFIELD 3869 uint32_t word5Rsvd:8; 3870 uint32_t remoteID:24; 3871 #else /* __LITTLE_ENDIAN_BITFIELD */ 3872 uint32_t remoteID:24; 3873 uint32_t word5Rsvd:8; 3874 #endif 3875 } RCV_ELS_REQ; 3876 3877 /* IOCB Command template for ABORT / CLOSE_XRI */ 3878 typedef struct { 3879 uint32_t rsvd[3]; 3880 uint32_t abortType; 3881 #define ABORT_TYPE_ABTX 0x00000000 3882 #define ABORT_TYPE_ABTS 0x00000001 3883 uint32_t parm; 3884 #ifdef __BIG_ENDIAN_BITFIELD 3885 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3886 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3887 #else /* __LITTLE_ENDIAN_BITFIELD */ 3888 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3889 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3890 #endif 3891 } AC_XRI; 3892 3893 /* IOCB Command template for ABORT_MXRI64 */ 3894 typedef struct { 3895 uint32_t rsvd[3]; 3896 uint32_t abortType; 3897 uint32_t parm; 3898 uint32_t iotag32; 3899 } A_MXRI64; 3900 3901 /* IOCB Command template for GET_RPI */ 3902 typedef struct { 3903 uint32_t rsvd[4]; 3904 uint32_t parmRo; 3905 #ifdef __BIG_ENDIAN_BITFIELD 3906 uint32_t word5Rsvd:8; 3907 uint32_t remoteID:24; 3908 #else /* __LITTLE_ENDIAN_BITFIELD */ 3909 uint32_t remoteID:24; 3910 uint32_t word5Rsvd:8; 3911 #endif 3912 } GET_RPI; 3913 3914 /* IOCB Command template for all FCP Initiator commands */ 3915 typedef struct { 3916 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3917 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3918 uint32_t fcpi_parm; 3919 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3920 } FCPI_FIELDS; 3921 3922 /* IOCB Command template for all FCP Target commands */ 3923 typedef struct { 3924 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3925 uint32_t fcpt_Offset; 3926 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3927 } FCPT_FIELDS; 3928 3929 /* SLI-2 IOCB structure definitions */ 3930 3931 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3932 typedef struct { 3933 ULP_BDL bdl; 3934 uint32_t xrsqRo; /* Starting Relative Offset */ 3935 WORD5 w5; /* Header control/status word */ 3936 } XMT_SEQ_FIELDS64; 3937 3938 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */ 3939 #define xmit_els_remoteID xrsqRo 3940 3941 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3942 typedef struct { 3943 struct ulp_bde64 rcvBde; 3944 uint32_t rsvd1; 3945 uint32_t xrsqRo; /* Starting Relative Offset */ 3946 WORD5 w5; /* Header control/status word */ 3947 } RCV_SEQ_FIELDS64; 3948 3949 /* IOCB Command template for ELS_REQUEST64 */ 3950 typedef struct { 3951 ULP_BDL bdl; 3952 #ifdef __BIG_ENDIAN_BITFIELD 3953 uint32_t word4Rsvd:7; 3954 uint32_t fl:1; 3955 uint32_t myID:24; 3956 uint32_t word5Rsvd:8; 3957 uint32_t remoteID:24; 3958 #else /* __LITTLE_ENDIAN_BITFIELD */ 3959 uint32_t myID:24; 3960 uint32_t fl:1; 3961 uint32_t word4Rsvd:7; 3962 uint32_t remoteID:24; 3963 uint32_t word5Rsvd:8; 3964 #endif 3965 } ELS_REQUEST64; 3966 3967 /* IOCB Command template for GEN_REQUEST64 */ 3968 typedef struct { 3969 ULP_BDL bdl; 3970 uint32_t xrsqRo; /* Starting Relative Offset */ 3971 WORD5 w5; /* Header control/status word */ 3972 } GEN_REQUEST64; 3973 3974 /* IOCB Command template for RCV_ELS_REQ64 */ 3975 typedef struct { 3976 struct ulp_bde64 elsReq; 3977 uint32_t rcvd1; 3978 uint32_t parmRo; 3979 3980 #ifdef __BIG_ENDIAN_BITFIELD 3981 uint32_t word5Rsvd:8; 3982 uint32_t remoteID:24; 3983 #else /* __LITTLE_ENDIAN_BITFIELD */ 3984 uint32_t remoteID:24; 3985 uint32_t word5Rsvd:8; 3986 #endif 3987 } RCV_ELS_REQ64; 3988 3989 /* IOCB Command template for RCV_SEQ64 */ 3990 struct rcv_seq64 { 3991 struct ulp_bde64 elsReq; 3992 uint32_t hbq_1; 3993 uint32_t parmRo; 3994 #ifdef __BIG_ENDIAN_BITFIELD 3995 uint32_t rctl:8; 3996 uint32_t type:8; 3997 uint32_t dfctl:8; 3998 uint32_t ls:1; 3999 uint32_t fs:1; 4000 uint32_t rsvd2:3; 4001 uint32_t si:1; 4002 uint32_t bc:1; 4003 uint32_t rsvd3:1; 4004 #else /* __LITTLE_ENDIAN_BITFIELD */ 4005 uint32_t rsvd3:1; 4006 uint32_t bc:1; 4007 uint32_t si:1; 4008 uint32_t rsvd2:3; 4009 uint32_t fs:1; 4010 uint32_t ls:1; 4011 uint32_t dfctl:8; 4012 uint32_t type:8; 4013 uint32_t rctl:8; 4014 #endif 4015 }; 4016 4017 /* IOCB Command template for all 64 bit FCP Initiator commands */ 4018 typedef struct { 4019 ULP_BDL bdl; 4020 uint32_t fcpi_parm; 4021 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 4022 } FCPI_FIELDS64; 4023 4024 /* IOCB Command template for all 64 bit FCP Target commands */ 4025 typedef struct { 4026 ULP_BDL bdl; 4027 uint32_t fcpt_Offset; 4028 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 4029 } FCPT_FIELDS64; 4030 4031 /* IOCB Command template for Async Status iocb commands */ 4032 typedef struct { 4033 uint32_t rsvd[4]; 4034 uint32_t param; 4035 #ifdef __BIG_ENDIAN_BITFIELD 4036 uint16_t evt_code; /* High order bits word 5 */ 4037 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 4038 #else /* __LITTLE_ENDIAN_BITFIELD */ 4039 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 4040 uint16_t evt_code; /* Low order bits word 5 */ 4041 #endif 4042 } ASYNCSTAT_FIELDS; 4043 #define ASYNC_TEMP_WARN 0x100 4044 #define ASYNC_TEMP_SAFE 0x101 4045 #define ASYNC_STATUS_CN 0x102 4046 4047 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 4048 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 4049 4050 struct rcv_sli3 { 4051 #ifdef __BIG_ENDIAN_BITFIELD 4052 uint16_t ox_id; 4053 uint16_t seq_cnt; 4054 4055 uint16_t vpi; 4056 uint16_t word9Rsvd; 4057 #else /* __LITTLE_ENDIAN */ 4058 uint16_t seq_cnt; 4059 uint16_t ox_id; 4060 4061 uint16_t word9Rsvd; 4062 uint16_t vpi; 4063 #endif 4064 uint32_t word10Rsvd; 4065 uint32_t acc_len; /* accumulated length */ 4066 struct ulp_bde64 bde2; 4067 }; 4068 4069 /* Structure used for a single HBQ entry */ 4070 struct lpfc_hbq_entry { 4071 struct ulp_bde64 bde; 4072 uint32_t buffer_tag; 4073 }; 4074 4075 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 4076 typedef struct { 4077 struct lpfc_hbq_entry buff; 4078 uint32_t rsvd; 4079 uint32_t rsvd1; 4080 } QUE_XRI64_CX_FIELDS; 4081 4082 struct que_xri64cx_ext_fields { 4083 uint32_t iotag64_low; 4084 uint32_t iotag64_high; 4085 uint32_t ebde_count; 4086 uint32_t rsvd; 4087 struct lpfc_hbq_entry buff[5]; 4088 }; 4089 4090 struct sli3_bg_fields { 4091 uint32_t filler[6]; /* word 8-13 in IOCB */ 4092 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 4093 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 4094 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 4095 #define BGS_BIDIR_BG_PROF_SHIFT 24 4096 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 4097 #define BGS_BIDIR_ERR_COND_SHIFT 16 4098 #define BGS_BG_PROFILE_MASK 0x0000ff00 4099 #define BGS_BG_PROFILE_SHIFT 8 4100 #define BGS_INVALID_PROF_MASK 0x00000020 4101 #define BGS_INVALID_PROF_SHIFT 5 4102 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 4103 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 4104 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 4105 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 4106 #define BGS_REFTAG_ERR_MASK 0x00000004 4107 #define BGS_REFTAG_ERR_SHIFT 2 4108 #define BGS_APPTAG_ERR_MASK 0x00000002 4109 #define BGS_APPTAG_ERR_SHIFT 1 4110 #define BGS_GUARD_ERR_MASK 0x00000001 4111 #define BGS_GUARD_ERR_SHIFT 0 4112 uint32_t bgstat; /* word 15 - BlockGuard Status */ 4113 }; 4114 4115 static inline uint32_t 4116 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 4117 { 4118 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 4119 BGS_BIDIR_BG_PROF_SHIFT; 4120 } 4121 4122 static inline uint32_t 4123 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 4124 { 4125 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 4126 BGS_BIDIR_ERR_COND_SHIFT; 4127 } 4128 4129 static inline uint32_t 4130 lpfc_bgs_get_bg_prof(uint32_t bgstat) 4131 { 4132 return (bgstat & BGS_BG_PROFILE_MASK) >> 4133 BGS_BG_PROFILE_SHIFT; 4134 } 4135 4136 static inline uint32_t 4137 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 4138 { 4139 return (bgstat & BGS_INVALID_PROF_MASK) >> 4140 BGS_INVALID_PROF_SHIFT; 4141 } 4142 4143 static inline uint32_t 4144 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 4145 { 4146 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 4147 BGS_UNINIT_DIF_BLOCK_SHIFT; 4148 } 4149 4150 static inline uint32_t 4151 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 4152 { 4153 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 4154 BGS_HI_WATER_MARK_PRESENT_SHIFT; 4155 } 4156 4157 static inline uint32_t 4158 lpfc_bgs_get_reftag_err(uint32_t bgstat) 4159 { 4160 return (bgstat & BGS_REFTAG_ERR_MASK) >> 4161 BGS_REFTAG_ERR_SHIFT; 4162 } 4163 4164 static inline uint32_t 4165 lpfc_bgs_get_apptag_err(uint32_t bgstat) 4166 { 4167 return (bgstat & BGS_APPTAG_ERR_MASK) >> 4168 BGS_APPTAG_ERR_SHIFT; 4169 } 4170 4171 static inline uint32_t 4172 lpfc_bgs_get_guard_err(uint32_t bgstat) 4173 { 4174 return (bgstat & BGS_GUARD_ERR_MASK) >> 4175 BGS_GUARD_ERR_SHIFT; 4176 } 4177 4178 #define LPFC_EXT_DATA_BDE_COUNT 3 4179 struct fcp_irw_ext { 4180 uint32_t io_tag64_low; 4181 uint32_t io_tag64_high; 4182 #ifdef __BIG_ENDIAN_BITFIELD 4183 uint8_t reserved1; 4184 uint8_t reserved2; 4185 uint8_t reserved3; 4186 uint8_t ebde_count; 4187 #else /* __LITTLE_ENDIAN */ 4188 uint8_t ebde_count; 4189 uint8_t reserved3; 4190 uint8_t reserved2; 4191 uint8_t reserved1; 4192 #endif 4193 uint32_t reserved4; 4194 struct ulp_bde64 rbde; /* response bde */ 4195 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 4196 uint8_t icd[32]; /* immediate command data (32 bytes) */ 4197 }; 4198 4199 typedef struct _IOCB { /* IOCB structure */ 4200 union { 4201 GENERIC_RSP grsp; /* Generic response */ 4202 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 4203 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 4204 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 4205 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 4206 A_MXRI64 amxri; /* abort multiple xri command overlay */ 4207 GET_RPI getrpi; /* GET_RPI template */ 4208 FCPI_FIELDS fcpi; /* FCP Initiator template */ 4209 FCPT_FIELDS fcpt; /* FCP target template */ 4210 4211 /* SLI-2 structures */ 4212 4213 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 4214 * bde_64s */ 4215 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 4216 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 4217 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 4218 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 4219 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 4220 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 4221 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 4222 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 4223 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 4224 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 4225 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 4226 } un; 4227 union { 4228 struct { 4229 #ifdef __BIG_ENDIAN_BITFIELD 4230 uint16_t ulpContext; /* High order bits word 6 */ 4231 uint16_t ulpIoTag; /* Low order bits word 6 */ 4232 #else /* __LITTLE_ENDIAN_BITFIELD */ 4233 uint16_t ulpIoTag; /* Low order bits word 6 */ 4234 uint16_t ulpContext; /* High order bits word 6 */ 4235 #endif 4236 } t1; 4237 struct { 4238 #ifdef __BIG_ENDIAN_BITFIELD 4239 uint16_t ulpContext; /* High order bits word 6 */ 4240 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4241 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4242 #else /* __LITTLE_ENDIAN_BITFIELD */ 4243 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4244 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4245 uint16_t ulpContext; /* High order bits word 6 */ 4246 #endif 4247 } t2; 4248 } un1; 4249 #define ulpContext un1.t1.ulpContext 4250 #define ulpIoTag un1.t1.ulpIoTag 4251 #define ulpIoTag0 un1.t2.ulpIoTag0 4252 4253 #ifdef __BIG_ENDIAN_BITFIELD 4254 uint32_t ulpTimeout:8; 4255 uint32_t ulpXS:1; 4256 uint32_t ulpFCP2Rcvy:1; 4257 uint32_t ulpPU:2; 4258 uint32_t ulpIr:1; 4259 uint32_t ulpClass:3; 4260 uint32_t ulpCommand:8; 4261 uint32_t ulpStatus:4; 4262 uint32_t ulpBdeCount:2; 4263 uint32_t ulpLe:1; 4264 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4265 #else /* __LITTLE_ENDIAN_BITFIELD */ 4266 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4267 uint32_t ulpLe:1; 4268 uint32_t ulpBdeCount:2; 4269 uint32_t ulpStatus:4; 4270 uint32_t ulpCommand:8; 4271 uint32_t ulpClass:3; 4272 uint32_t ulpIr:1; 4273 uint32_t ulpPU:2; 4274 uint32_t ulpFCP2Rcvy:1; 4275 uint32_t ulpXS:1; 4276 uint32_t ulpTimeout:8; 4277 #endif 4278 4279 union { 4280 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 4281 4282 /* words 8-31 used for que_xri_cx iocb */ 4283 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 4284 struct fcp_irw_ext fcp_ext; 4285 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 4286 4287 /* words 8-15 for BlockGuard */ 4288 struct sli3_bg_fields sli3_bg; 4289 } unsli3; 4290 4291 #define ulpCt_h ulpXS 4292 #define ulpCt_l ulpFCP2Rcvy 4293 4294 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 4295 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 4296 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 4297 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 4298 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 4299 #define PARM_NPIV_DID 3 4300 #define CLASS1 0 /* Class 1 */ 4301 #define CLASS2 1 /* Class 2 */ 4302 #define CLASS3 2 /* Class 3 */ 4303 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 4304 4305 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 4306 #define IOSTAT_FCP_RSP_ERROR 0x1 4307 #define IOSTAT_REMOTE_STOP 0x2 4308 #define IOSTAT_LOCAL_REJECT 0x3 4309 #define IOSTAT_NPORT_RJT 0x4 4310 #define IOSTAT_FABRIC_RJT 0x5 4311 #define IOSTAT_NPORT_BSY 0x6 4312 #define IOSTAT_FABRIC_BSY 0x7 4313 #define IOSTAT_INTERMED_RSP 0x8 4314 #define IOSTAT_LS_RJT 0x9 4315 #define IOSTAT_BA_RJT 0xA 4316 #define IOSTAT_RSVD1 0xB 4317 #define IOSTAT_RSVD2 0xC 4318 #define IOSTAT_RSVD3 0xD 4319 #define IOSTAT_RSVD4 0xE 4320 #define IOSTAT_NEED_BUFFER 0xF 4321 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 4322 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 4323 #define IOSTAT_CNT 0x11 4324 4325 } IOCB_t; 4326 4327 4328 #define SLI1_SLIM_SIZE (4 * 1024) 4329 4330 /* Up to 498 IOCBs will fit into 16k 4331 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 4332 */ 4333 #define SLI2_SLIM_SIZE (64 * 1024) 4334 4335 /* Maximum IOCBs that will fit in SLI2 slim */ 4336 #define MAX_SLI2_IOCB 498 4337 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 4338 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 4339 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 4340 4341 /* HBQ entries are 4 words each = 4k */ 4342 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 4343 lpfc_sli_hbq_count()) 4344 4345 struct lpfc_sli2_slim { 4346 MAILBOX_t mbx; 4347 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 4348 PCB_t pcb; 4349 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 4350 }; 4351 4352 /* 4353 * This function checks PCI device to allow special handling for LC HBAs. 4354 * 4355 * Parameters: 4356 * device : struct pci_dev 's device field 4357 * 4358 * return 1 => TRUE 4359 * 0 => FALSE 4360 */ 4361 static inline int 4362 lpfc_is_LC_HBA(unsigned short device) 4363 { 4364 if ((device == PCI_DEVICE_ID_TFLY) || 4365 (device == PCI_DEVICE_ID_PFLY) || 4366 (device == PCI_DEVICE_ID_LP101) || 4367 (device == PCI_DEVICE_ID_BMID) || 4368 (device == PCI_DEVICE_ID_BSMB) || 4369 (device == PCI_DEVICE_ID_ZMID) || 4370 (device == PCI_DEVICE_ID_ZSMB) || 4371 (device == PCI_DEVICE_ID_SAT_MID) || 4372 (device == PCI_DEVICE_ID_SAT_SMB) || 4373 (device == PCI_DEVICE_ID_RFLY)) 4374 return 1; 4375 else 4376 return 0; 4377 } 4378 4379 /* 4380 * Determine if failed because of a link event or firmware reset. 4381 */ 4382 static inline int 4383 lpfc_error_lost_link(u32 ulp_status, u32 ulp_word4) 4384 { 4385 return (ulp_status == IOSTAT_LOCAL_REJECT && 4386 (ulp_word4 == IOERR_SLI_ABORTED || 4387 ulp_word4 == IOERR_LINK_DOWN || 4388 ulp_word4 == IOERR_SLI_DOWN)); 4389 } 4390 4391 #define MENLO_TRANSPORT_TYPE 0xfe 4392 #define MENLO_CONTEXT 0 4393 #define MENLO_PU 3 4394 #define MENLO_TIMEOUT 30 4395 #define SETVAR_MLOMNT 0x103107 4396 #define SETVAR_MLORST 0x103007 4397 4398 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 4399