1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2025 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #define FDMI_DID 0xfffffaU 24 #define NameServer_DID 0xfffffcU 25 #define Fabric_Cntl_DID 0xfffffdU 26 #define Fabric_DID 0xfffffeU 27 #define Bcast_DID 0xffffffU 28 #define Mask_DID 0xffffffU 29 #define CT_DID_MASK 0xffff00U 30 #define Fabric_DID_MASK 0xfff000U 31 #define WELL_KNOWN_DID_MASK 0xfffff0U 32 33 #define PT2PT_LocalID 1 34 #define PT2PT_RemoteID 2 35 36 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 37 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 38 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */ 39 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 40 41 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 42 0 */ 43 44 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 45 46 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 47 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 48 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 49 50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 58 #define SLI2_IOCB_CMD_R3_ENTRIES 0 59 #define SLI2_IOCB_RSP_R3_ENTRIES 0 60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 62 63 #define SLI2_IOCB_CMD_SIZE 32 64 #define SLI2_IOCB_RSP_SIZE 32 65 #define SLI3_IOCB_CMD_SIZE 128 66 #define SLI3_IOCB_RSP_SIZE 64 67 68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 70 71 /* vendor ID used in SCSI netlink calls */ 72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 73 74 #define FW_REV_STR_SIZE 32 75 /* Common Transport structures and definitions */ 76 77 union CtRevisionId { 78 /* Structure is in Big Endian format */ 79 struct { 80 uint32_t Revision:8; 81 uint32_t InId:24; 82 } bits; 83 uint32_t word; 84 }; 85 86 union CtCommandResponse { 87 /* Structure is in Big Endian format */ 88 struct { 89 __be16 CmdRsp; 90 __be16 Size; 91 } bits; 92 uint32_t word; 93 }; 94 95 /* FC4 Feature bits for RFF_ID */ 96 #define FC4_FEATURE_TARGET 0x1 97 #define FC4_FEATURE_INIT 0x2 98 #define FC4_FEATURE_NVME_DISC 0x4 99 100 enum rft_word0 { 101 RFT_FCP_REG = (0x1 << 8), 102 }; 103 104 enum rft_word1 { 105 RFT_NVME_REG = (0x1 << 8), 106 }; 107 108 enum rft_word3 { 109 RFT_APP_SERV_REG = (0x1 << 0), 110 }; 111 112 struct lpfc_sli_ct_request { 113 /* Structure is in Big Endian format */ 114 union CtRevisionId RevisionId; 115 uint8_t FsType; 116 uint8_t FsSubType; 117 uint8_t Options; 118 uint8_t Rsrvd1; 119 union CtCommandResponse CommandResponse; 120 uint8_t Rsrvd2; 121 uint8_t ReasonCode; 122 uint8_t Explanation; 123 uint8_t VendorUnique; 124 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */ 125 126 union { 127 __be32 PortID; 128 struct gid { 129 uint8_t PortType; /* for GID_PT requests */ 130 #define GID_PT_N_PORT 1 131 uint8_t DomainScope; 132 uint8_t AreaScope; 133 uint8_t Fc4Type; /* for GID_FT requests */ 134 } gid; 135 struct gid_ff { 136 uint8_t Flags; 137 uint8_t DomainScope; 138 uint8_t AreaScope; 139 uint8_t rsvd1; 140 uint8_t rsvd2; 141 uint8_t rsvd3; 142 uint8_t Fc4FBits; 143 uint8_t Fc4Type; 144 } gid_ff; 145 struct rft { 146 __be32 port_id; /* For RFT_ID requests */ 147 148 __be32 fcp_reg; /* rsvd 31:9, fcp_reg 8, rsvd 7:0 */ 149 __be32 nvme_reg; /* rsvd 31:9, nvme_reg 8, rsvd 7:0 */ 150 __be32 word2; 151 __be32 app_serv_reg; /* rsvd 31:1, app_serv_reg 0 */ 152 __be32 word[4]; 153 } rft; 154 struct rnn { 155 uint32_t PortId; /* For RNN_ID requests */ 156 uint8_t wwnn[8]; 157 } rnn; 158 struct rsnn { /* For RSNN_ID requests */ 159 uint8_t wwnn[8]; 160 uint8_t len; 161 uint8_t symbname[255]; 162 } rsnn; 163 struct da_id { /* For DA_ID requests */ 164 uint32_t port_id; 165 } da_id; 166 struct rspn { /* For RSPN_ID requests */ 167 uint32_t PortId; 168 uint8_t len; 169 uint8_t symbname[255]; 170 } rspn; 171 struct gff { 172 uint32_t PortId; 173 } gff; 174 struct gff_acc { 175 uint8_t fbits[128]; 176 } gff_acc; 177 struct gft { 178 uint32_t PortId; 179 } gft; 180 struct gft_acc { 181 uint32_t fc4_types[8]; 182 } gft_acc; 183 #define FCP_TYPE_FEATURE_OFFSET 7 184 struct rff { 185 uint32_t PortId; 186 uint8_t reserved[2]; 187 uint8_t fbits; 188 uint8_t type_code; /* type=8 for FCP */ 189 } rff; 190 } un; 191 }; 192 193 #define LPFC_MAX_CT_SIZE (60 * 4096) 194 195 #define SLI_CT_REVISION 1 196 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 197 sizeof(struct gid)) 198 #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 199 sizeof(struct gid_ff)) 200 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 201 sizeof(struct gff)) 202 #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 203 sizeof(struct gft)) 204 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 205 sizeof(struct rft)) 206 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 207 sizeof(struct rff)) 208 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 209 sizeof(struct rnn)) 210 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 211 sizeof(struct rsnn)) 212 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 213 sizeof(struct da_id)) 214 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 215 sizeof(struct rspn)) 216 217 /* 218 * FsType Definitions 219 */ 220 221 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 222 #define SLI_CT_TIME_SERVICE 0xFB 223 #define SLI_CT_DIRECTORY_SERVICE 0xFC 224 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 225 226 /* 227 * Directory Service Subtypes 228 */ 229 230 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 231 232 /* 233 * Response Codes 234 */ 235 236 #define SLI_CT_RESPONSE_FS_RJT 0x8001 237 #define SLI_CT_RESPONSE_FS_ACC 0x8002 238 239 /* 240 * Reason Codes 241 */ 242 243 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 244 #define SLI_CT_INVALID_COMMAND 0x01 245 #define SLI_CT_INVALID_VERSION 0x02 246 #define SLI_CT_LOGICAL_ERROR 0x03 247 #define SLI_CT_INVALID_IU_SIZE 0x04 248 #define SLI_CT_LOGICAL_BUSY 0x05 249 #define SLI_CT_PROTOCOL_ERROR 0x07 250 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 251 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 252 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 253 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 254 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 255 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 256 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 257 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 258 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 259 #define SLI_CT_VENDOR_UNIQUE 0xff 260 261 /* 262 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 263 */ 264 265 #define SLI_CT_NO_PORT_ID 0x01 266 #define SLI_CT_NO_PORT_NAME 0x02 267 #define SLI_CT_NO_NODE_NAME 0x03 268 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 269 #define SLI_CT_NO_IP_ADDRESS 0x05 270 #define SLI_CT_NO_IPA 0x06 271 #define SLI_CT_NO_FC4_TYPES 0x07 272 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 273 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 274 #define SLI_CT_NO_PORT_TYPE 0x0A 275 #define SLI_CT_ACCESS_DENIED 0x10 276 #define SLI_CT_INVALID_PORT_ID 0x11 277 #define SLI_CT_DATABASE_EMPTY 0x12 278 #define SLI_CT_APP_ID_NOT_AVAILABLE 0x40 279 280 /* 281 * Name Server Command Codes 282 */ 283 284 #define SLI_CTNS_GA_NXT 0x0100 285 #define SLI_CTNS_GPN_ID 0x0112 286 #define SLI_CTNS_GNN_ID 0x0113 287 #define SLI_CTNS_GCS_ID 0x0114 288 #define SLI_CTNS_GFT_ID 0x0117 289 #define SLI_CTNS_GSPN_ID 0x0118 290 #define SLI_CTNS_GPT_ID 0x011A 291 #define SLI_CTNS_GFF_ID 0x011F 292 #define SLI_CTNS_GID_PN 0x0121 293 #define SLI_CTNS_GID_NN 0x0131 294 #define SLI_CTNS_GIP_NN 0x0135 295 #define SLI_CTNS_GIPA_NN 0x0136 296 #define SLI_CTNS_GSNN_NN 0x0139 297 #define SLI_CTNS_GNN_IP 0x0153 298 #define SLI_CTNS_GIPA_IP 0x0156 299 #define SLI_CTNS_GID_FT 0x0171 300 #define SLI_CTNS_GID_FF 0x01F1 301 #define SLI_CTNS_GID_PT 0x01A1 302 #define SLI_CTNS_RPN_ID 0x0212 303 #define SLI_CTNS_RNN_ID 0x0213 304 #define SLI_CTNS_RCS_ID 0x0214 305 #define SLI_CTNS_RFT_ID 0x0217 306 #define SLI_CTNS_RSPN_ID 0x0218 307 #define SLI_CTNS_RPT_ID 0x021A 308 #define SLI_CTNS_RFF_ID 0x021F 309 #define SLI_CTNS_RIP_NN 0x0235 310 #define SLI_CTNS_RIPA_NN 0x0236 311 #define SLI_CTNS_RSNN_NN 0x0239 312 #define SLI_CTNS_DA_ID 0x0300 313 314 /* 315 * Port Types 316 */ 317 318 #define SLI_CTPT_N_PORT 0x01 319 #define SLI_CTPT_NL_PORT 0x02 320 #define SLI_CTPT_FNL_PORT 0x03 321 #define SLI_CTPT_IP 0x04 322 #define SLI_CTPT_FCP 0x08 323 #define SLI_CTPT_NVME 0x28 324 #define SLI_CTPT_NX_PORT 0x7F 325 #define SLI_CTPT_F_PORT 0x81 326 #define SLI_CTPT_FL_PORT 0x82 327 #define SLI_CTPT_E_PORT 0x84 328 329 #define SLI_CT_LAST_ENTRY 0x80000000 330 331 /* Fibre Channel Service Parameter definitions */ 332 333 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 334 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 335 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 336 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 337 338 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 339 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 340 #define FC_PH3 0x20 /* FC-PH-3 version */ 341 342 #define FF_FRAME_SIZE 2048 343 344 struct lpfc_name { 345 union { 346 struct { 347 #ifdef __BIG_ENDIAN_BITFIELD 348 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 349 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 350 8:11 of IEEE ext */ 351 #else /* __LITTLE_ENDIAN_BITFIELD */ 352 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 353 8:11 of IEEE ext */ 354 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 355 #endif 356 357 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 358 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 359 #define NAME_FC_TYPE 0x3 /* FC native name type */ 360 #define NAME_IP_TYPE 0x4 /* IP address */ 361 #define NAME_CCITT_TYPE 0xC 362 #define NAME_CCITT_GR_TYPE 0xE 363 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 364 extended Lsb */ 365 uint8_t IEEE[6]; /* FC IEEE address */ 366 } s; 367 uint8_t wwn[8]; 368 uint64_t name __packed __aligned(4); 369 __be64 wwn_be __packed __aligned(4); 370 } u; 371 }; 372 373 struct csp { 374 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 375 uint8_t fcphLow; 376 uint8_t bbCreditMsb; 377 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */ 378 379 /* 380 * Word 1 Bit 31 in common service parameter is overloaded. 381 * Word 1 Bit 31 in FLOGI request is multiple NPort request 382 * Word 1 Bit 31 in FLOGI response is clean address bit 383 */ 384 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 385 /* 386 * Word 1 Bit 30 in common service parameter is overloaded. 387 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 388 * Word 1 Bit 30 in PLOGI request is random offset 389 */ 390 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 391 /* 392 * Word 1 Bit 29 in common service parameter is overloaded. 393 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment 394 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level 395 */ 396 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */ 397 #ifdef __BIG_ENDIAN_BITFIELD 398 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 399 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 400 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 401 uint16_t fPort:1; /* FC Word 1, bit 28 */ 402 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 403 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 404 uint16_t multicast:1; /* FC Word 1, bit 25 */ 405 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ 406 407 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ 408 uint16_t simplex:1; /* FC Word 1, bit 22 */ 409 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 410 uint16_t dhd:1; /* FC Word 1, bit 18 */ 411 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 412 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 413 #else /* __LITTLE_ENDIAN_BITFIELD */ 414 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ 415 uint16_t multicast:1; /* FC Word 1, bit 25 */ 416 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 417 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 418 uint16_t fPort:1; /* FC Word 1, bit 28 */ 419 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 420 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 421 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 422 423 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 424 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 425 uint16_t dhd:1; /* FC Word 1, bit 18 */ 426 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 427 uint16_t simplex:1; /* FC Word 1, bit 22 */ 428 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ 429 #endif 430 431 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 432 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 433 union { 434 struct { 435 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 436 437 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 438 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 439 440 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 441 } nPort; 442 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 443 } w2; 444 445 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 446 }; 447 448 struct class_parms { 449 #ifdef __BIG_ENDIAN_BITFIELD 450 uint8_t classValid:1; /* FC Word 0, bit 31 */ 451 uint8_t intermix:1; /* FC Word 0, bit 30 */ 452 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 453 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 454 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 455 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 456 #else /* __LITTLE_ENDIAN_BITFIELD */ 457 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 458 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 459 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 460 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 461 uint8_t intermix:1; /* FC Word 0, bit 30 */ 462 uint8_t classValid:1; /* FC Word 0, bit 31 */ 463 464 #endif 465 466 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 467 468 #ifdef __BIG_ENDIAN_BITFIELD 469 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 470 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 471 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 472 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 473 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 474 #else /* __LITTLE_ENDIAN_BITFIELD */ 475 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 476 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 477 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 478 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 479 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 480 #endif 481 482 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 483 484 #ifdef __BIG_ENDIAN_BITFIELD 485 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 486 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 487 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 488 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 489 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 490 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 491 #else /* __LITTLE_ENDIAN_BITFIELD */ 492 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 493 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 494 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 495 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 496 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 497 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 498 #endif 499 500 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 501 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 502 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 503 504 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 505 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 506 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 507 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 508 509 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 510 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 511 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 512 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 513 }; 514 515 struct serv_parm { /* Structure is in Big Endian format */ 516 struct csp cmn; 517 struct lpfc_name portName; 518 struct lpfc_name nodeName; 519 struct class_parms cls1; 520 struct class_parms cls2; 521 struct class_parms cls3; 522 struct class_parms cls4; 523 union { 524 uint8_t vendorVersion[16]; 525 struct { 526 uint32_t vid; 527 #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */ 528 uint32_t flags; 529 #define LPFC_VV_SUPPRESS_RSP 1 530 } vv; 531 } un; 532 }; 533 534 /* 535 * Virtual Fabric Tagging Header 536 */ 537 struct fc_vft_header { 538 uint32_t word0; 539 #define fc_vft_hdr_r_ctl_SHIFT 24 540 #define fc_vft_hdr_r_ctl_MASK 0xFF 541 #define fc_vft_hdr_r_ctl_WORD word0 542 #define fc_vft_hdr_ver_SHIFT 22 543 #define fc_vft_hdr_ver_MASK 0x3 544 #define fc_vft_hdr_ver_WORD word0 545 #define fc_vft_hdr_type_SHIFT 18 546 #define fc_vft_hdr_type_MASK 0xF 547 #define fc_vft_hdr_type_WORD word0 548 #define fc_vft_hdr_e_SHIFT 16 549 #define fc_vft_hdr_e_MASK 0x1 550 #define fc_vft_hdr_e_WORD word0 551 #define fc_vft_hdr_priority_SHIFT 13 552 #define fc_vft_hdr_priority_MASK 0x7 553 #define fc_vft_hdr_priority_WORD word0 554 #define fc_vft_hdr_vf_id_SHIFT 1 555 #define fc_vft_hdr_vf_id_MASK 0xFFF 556 #define fc_vft_hdr_vf_id_WORD word0 557 uint32_t word1; 558 #define fc_vft_hdr_hopct_SHIFT 24 559 #define fc_vft_hdr_hopct_MASK 0xFF 560 #define fc_vft_hdr_hopct_WORD word1 561 }; 562 563 #include <uapi/scsi/fc/fc_els.h> 564 565 /* 566 * Application Header 567 */ 568 struct fc_app_header { 569 uint32_t dst_app_id; 570 uint32_t src_app_id; 571 #define LOOPBACK_SRC_APPID 0x4321 572 uint32_t word2; 573 uint32_t word3; 574 }; 575 576 /* 577 * dfctl optional header definition 578 */ 579 enum lpfc_fc_dfctl { 580 LPFC_FC_NO_DEVICE_HEADER, 581 LPFC_FC_16B_DEVICE_HEADER, 582 LPFC_FC_32B_DEVICE_HEADER, 583 LPFC_FC_64B_DEVICE_HEADER, 584 }; 585 586 /* 587 * Extended Link Service LS_COMMAND codes (Payload Word 0) 588 */ 589 #ifdef __BIG_ENDIAN_BITFIELD 590 #define ELS_CMD_MASK 0xffff0000 591 #define ELS_RSP_MASK 0xff000000 592 #define ELS_CMD_LS_RJT 0x01000000 593 #define ELS_CMD_ACC 0x02000000 594 #define ELS_CMD_PLOGI 0x03000000 595 #define ELS_CMD_FLOGI 0x04000000 596 #define ELS_CMD_LOGO 0x05000000 597 #define ELS_CMD_ABTX 0x06000000 598 #define ELS_CMD_RCS 0x07000000 599 #define ELS_CMD_RES 0x08000000 600 #define ELS_CMD_RSS 0x09000000 601 #define ELS_CMD_RSI 0x0A000000 602 #define ELS_CMD_ESTS 0x0B000000 603 #define ELS_CMD_ESTC 0x0C000000 604 #define ELS_CMD_ADVC 0x0D000000 605 #define ELS_CMD_RTV 0x0E000000 606 #define ELS_CMD_RLS 0x0F000000 607 #define ELS_CMD_ECHO 0x10000000 608 #define ELS_CMD_TEST 0x11000000 609 #define ELS_CMD_RRQ 0x12000000 610 #define ELS_CMD_REC 0x13000000 611 #define ELS_CMD_RDP 0x18000000 612 #define ELS_CMD_RDF 0x19000000 613 #define ELS_CMD_PRLI 0x20100014 614 #define ELS_CMD_NVMEPRLI 0x20140018 615 #define ELS_CMD_PRLO 0x21100014 616 #define ELS_CMD_PRLO_ACC 0x02100014 617 #define ELS_CMD_PDISC 0x50000000 618 #define ELS_CMD_FDISC 0x51000000 619 #define ELS_CMD_ADISC 0x52000000 620 #define ELS_CMD_FARP 0x54000000 621 #define ELS_CMD_FARPR 0x55000000 622 #define ELS_CMD_RPL 0x57000000 623 #define ELS_CMD_FAN 0x60000000 624 #define ELS_CMD_RSCN 0x61040000 625 #define ELS_CMD_RSCN_XMT 0x61040008 626 #define ELS_CMD_SCR 0x62000000 627 #define ELS_CMD_RNID 0x78000000 628 #define ELS_CMD_LIRR 0x7A000000 629 #define ELS_CMD_LCB 0x81000000 630 #define ELS_CMD_FPIN 0x16000000 631 #define ELS_CMD_EDC 0x17000000 632 #define ELS_CMD_QFPA 0xB0000000 633 #define ELS_CMD_UVEM 0xB1000000 634 #else /* __LITTLE_ENDIAN_BITFIELD */ 635 #define ELS_CMD_MASK 0xffff 636 #define ELS_RSP_MASK 0xff 637 #define ELS_CMD_LS_RJT 0x01 638 #define ELS_CMD_ACC 0x02 639 #define ELS_CMD_PLOGI 0x03 640 #define ELS_CMD_FLOGI 0x04 641 #define ELS_CMD_LOGO 0x05 642 #define ELS_CMD_ABTX 0x06 643 #define ELS_CMD_RCS 0x07 644 #define ELS_CMD_RES 0x08 645 #define ELS_CMD_RSS 0x09 646 #define ELS_CMD_RSI 0x0A 647 #define ELS_CMD_ESTS 0x0B 648 #define ELS_CMD_ESTC 0x0C 649 #define ELS_CMD_ADVC 0x0D 650 #define ELS_CMD_RTV 0x0E 651 #define ELS_CMD_RLS 0x0F 652 #define ELS_CMD_ECHO 0x10 653 #define ELS_CMD_TEST 0x11 654 #define ELS_CMD_RRQ 0x12 655 #define ELS_CMD_REC 0x13 656 #define ELS_CMD_RDP 0x18 657 #define ELS_CMD_RDF 0x19 658 #define ELS_CMD_PRLI 0x14001020 659 #define ELS_CMD_NVMEPRLI 0x18001420 660 #define ELS_CMD_PRLO 0x14001021 661 #define ELS_CMD_PRLO_ACC 0x14001002 662 #define ELS_CMD_PDISC 0x50 663 #define ELS_CMD_FDISC 0x51 664 #define ELS_CMD_ADISC 0x52 665 #define ELS_CMD_FARP 0x54 666 #define ELS_CMD_FARPR 0x55 667 #define ELS_CMD_RPL 0x57 668 #define ELS_CMD_FAN 0x60 669 #define ELS_CMD_RSCN 0x0461 670 #define ELS_CMD_RSCN_XMT 0x08000461 671 #define ELS_CMD_SCR 0x62 672 #define ELS_CMD_RNID 0x78 673 #define ELS_CMD_LIRR 0x7A 674 #define ELS_CMD_LCB 0x81 675 #define ELS_CMD_FPIN ELS_FPIN 676 #define ELS_CMD_EDC ELS_EDC 677 #define ELS_CMD_QFPA 0xB0 678 #define ELS_CMD_UVEM 0xB1 679 #endif 680 681 /* 682 * LS_RJT Payload Definition 683 */ 684 685 struct ls_rjt { /* Structure is in Big Endian format */ 686 union { 687 __be32 ls_rjt_error_be; 688 uint32_t lsRjtError; 689 struct { 690 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 691 692 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 693 /* LS_RJT reason codes */ 694 #define LSRJT_INVALID_CMD 0x01 695 #define LSRJT_LOGICAL_ERR 0x03 696 #define LSRJT_LOGICAL_BSY 0x05 697 #define LSRJT_PROTOCOL_ERR 0x07 698 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 699 #define LSRJT_CMD_UNSUPPORTED 0x0B 700 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 701 702 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 703 /* LS_RJT reason explanation */ 704 #define LSEXP_NOTHING_MORE 0x00 705 #define LSEXP_SPARM_OPTIONS 0x01 706 #define LSEXP_SPARM_ICTL 0x03 707 #define LSEXP_SPARM_RCTL 0x05 708 #define LSEXP_SPARM_RCV_SIZE 0x07 709 #define LSEXP_SPARM_CONCUR_SEQ 0x09 710 #define LSEXP_SPARM_CREDIT 0x0B 711 #define LSEXP_INVALID_PNAME 0x0D 712 #define LSEXP_INVALID_NNAME 0x0E 713 #define LSEXP_INVALID_CSP 0x0F 714 #define LSEXP_INVALID_ASSOC_HDR 0x11 715 #define LSEXP_ASSOC_HDR_REQ 0x13 716 #define LSEXP_INVALID_O_SID 0x15 717 #define LSEXP_INVALID_OX_RX 0x17 718 #define LSEXP_CMD_IN_PROGRESS 0x19 719 #define LSEXP_PORT_LOGIN_REQ 0x1E 720 #define LSEXP_INVALID_NPORT_ID 0x1F 721 #define LSEXP_INVALID_SEQ_ID 0x21 722 #define LSEXP_INVALID_XCHG 0x23 723 #define LSEXP_INACTIVE_XCHG 0x25 724 #define LSEXP_RQ_REQUIRED 0x27 725 #define LSEXP_OUT_OF_RESOURCE 0x29 726 #define LSEXP_CANT_GIVE_DATA 0x2A 727 #define LSEXP_REQ_UNSUPPORTED 0x2C 728 #define LSEXP_AUTH_REQ 0x48 729 #define LSEXP_NO_RSRC_ASSIGN 0x52 730 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 731 } b; 732 } un; 733 }; 734 735 /* 736 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 737 */ 738 739 typedef struct _LOGO { /* Structure is in Big Endian format */ 740 union { 741 uint32_t nPortId32; /* Access nPortId as a word */ 742 struct { 743 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 744 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 745 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 746 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 747 } b; 748 } un; 749 struct lpfc_name portName; /* N_port name field */ 750 } LOGO; 751 752 /* 753 * FCP Login (PRLI Request / ACC) Payload Definition 754 */ 755 756 #define PRLX_PAGE_LEN 0x10 757 #define TPRLO_PAGE_LEN 0x14 758 759 typedef struct _PRLI { /* Structure is in Big Endian format */ 760 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 761 762 #define PRLI_FCP_TYPE 0x08 763 #define PRLI_NVME_TYPE 0x28 764 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 765 766 #ifdef __BIG_ENDIAN_BITFIELD 767 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 768 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 769 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 770 771 /* ACC = imagePairEstablished */ 772 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 773 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 774 #else /* __LITTLE_ENDIAN_BITFIELD */ 775 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 776 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 777 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 778 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 779 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 780 /* ACC = imagePairEstablished */ 781 #endif 782 783 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 784 #define PRLI_NO_RESOURCES 0x2 785 #define PRLI_INIT_INCOMPLETE 0x3 786 #define PRLI_NO_SUCH_PA 0x4 787 #define PRLI_PREDEF_CONFIG 0x5 788 #define PRLI_PARTIAL_SUCCESS 0x6 789 #define PRLI_INVALID_PAGE_CNT 0x7 790 #define PRLI_INV_SRV_PARM 0x8 791 792 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 793 794 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 795 796 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 797 798 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 799 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 800 801 #ifdef __BIG_ENDIAN_BITFIELD 802 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 803 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 804 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 805 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 806 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 807 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 808 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 809 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 810 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 811 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 812 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 813 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 814 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 815 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 816 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 817 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 818 #else /* __LITTLE_ENDIAN_BITFIELD */ 819 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 820 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 821 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 822 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 823 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 824 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 825 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 826 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 827 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 828 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 829 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 830 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 831 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 832 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 833 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 834 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 835 #endif 836 } PRLI; 837 838 /* 839 * FCP Logout (PRLO Request / ACC) Payload Definition 840 */ 841 842 typedef struct _PRLO { /* Structure is in Big Endian format */ 843 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 844 845 #define PRLO_FCP_TYPE 0x08 846 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 847 848 #ifdef __BIG_ENDIAN_BITFIELD 849 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 850 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 851 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 852 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 853 #else /* __LITTLE_ENDIAN_BITFIELD */ 854 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 855 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 856 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 857 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 858 #endif 859 860 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 861 #define PRLO_NO_SUCH_IMAGE 0x4 862 #define PRLO_INVALID_PAGE_CNT 0x7 863 864 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 865 866 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 867 868 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 869 870 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 871 } PRLO; 872 873 typedef struct _ADISC { /* Structure is in Big Endian format */ 874 uint32_t hardAL_PA; 875 struct lpfc_name portName; 876 struct lpfc_name nodeName; 877 uint32_t DID; 878 } ADISC; 879 880 typedef struct _FARP { /* Structure is in Big Endian format */ 881 uint32_t Mflags:8; 882 uint32_t Odid:24; 883 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 884 action */ 885 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 886 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 887 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 888 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 889 supported */ 890 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 891 supported */ 892 uint32_t Rflags:8; 893 uint32_t Rdid:24; 894 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 895 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 896 struct lpfc_name OportName; 897 struct lpfc_name OnodeName; 898 struct lpfc_name RportName; 899 struct lpfc_name RnodeName; 900 uint8_t Oipaddr[16]; 901 uint8_t Ripaddr[16]; 902 } FARP; 903 904 typedef struct _FAN { /* Structure is in Big Endian format */ 905 uint32_t Fdid; 906 struct lpfc_name FportName; 907 struct lpfc_name FnodeName; 908 } FAN; 909 910 typedef struct _SCR { /* Structure is in Big Endian format */ 911 uint8_t resvd1; 912 uint8_t resvd2; 913 uint8_t resvd3; 914 uint8_t Function; 915 #define SCR_FUNC_FABRIC 0x01 916 #define SCR_FUNC_NPORT 0x02 917 #define SCR_FUNC_FULL 0x03 918 #define SCR_CLEAR 0xff 919 } SCR; 920 921 typedef struct _RNID_TOP_DISC { 922 struct lpfc_name portName; 923 uint8_t resvd[8]; 924 uint32_t unitType; 925 #define RNID_HBA 0x7 926 #define RNID_HOST 0xa 927 #define RNID_DRIVER 0xd 928 uint32_t physPort; 929 uint32_t attachedNodes; 930 uint16_t ipVersion; 931 #define RNID_IPV4 0x1 932 #define RNID_IPV6 0x2 933 uint16_t UDPport; 934 uint8_t ipAddr[16]; 935 uint16_t resvd1; 936 uint16_t flags; 937 #define RNID_TD_SUPPORT 0x1 938 #define RNID_LP_VALID 0x2 939 } RNID_TOP_DISC; 940 941 typedef struct _RNID { /* Structure is in Big Endian format */ 942 uint8_t Format; 943 #define RNID_TOPOLOGY_DISC 0xdf 944 uint8_t CommonLen; 945 uint8_t resvd1; 946 uint8_t SpecificLen; 947 struct lpfc_name portName; 948 struct lpfc_name nodeName; 949 union { 950 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 951 } un; 952 } RNID; 953 954 struct RLS { /* Structure is in Big Endian format */ 955 uint32_t rls; 956 #define rls_rsvd_SHIFT 24 957 #define rls_rsvd_MASK 0x000000ff 958 #define rls_rsvd_WORD rls 959 #define rls_did_SHIFT 0 960 #define rls_did_MASK 0x00ffffff 961 #define rls_did_WORD rls 962 }; 963 964 struct RLS_RSP { /* Structure is in Big Endian format */ 965 uint32_t linkFailureCnt; 966 uint32_t lossSyncCnt; 967 uint32_t lossSignalCnt; 968 uint32_t primSeqErrCnt; 969 uint32_t invalidXmitWord; 970 uint32_t crcCnt; 971 }; 972 973 struct RRQ { /* Structure is in Big Endian format */ 974 uint32_t rrq; 975 #define rrq_rsvd_SHIFT 24 976 #define rrq_rsvd_MASK 0x000000ff 977 #define rrq_rsvd_WORD rrq 978 #define rrq_did_SHIFT 0 979 #define rrq_did_MASK 0x00ffffff 980 #define rrq_did_WORD rrq 981 uint32_t rrq_exchg; 982 #define rrq_oxid_SHIFT 16 983 #define rrq_oxid_MASK 0xffff 984 #define rrq_oxid_WORD rrq_exchg 985 #define rrq_rxid_SHIFT 0 986 #define rrq_rxid_MASK 0xffff 987 #define rrq_rxid_WORD rrq_exchg 988 }; 989 990 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 991 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 992 993 struct RTV_RSP { /* Structure is in Big Endian format */ 994 uint32_t ratov; 995 uint32_t edtov; 996 uint32_t qtov; 997 #define qtov_rsvd0_SHIFT 28 998 #define qtov_rsvd0_MASK 0x0000000f 999 #define qtov_rsvd0_WORD qtov /* reserved */ 1000 #define qtov_edtovres_SHIFT 27 1001 #define qtov_edtovres_MASK 0x00000001 1002 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 1003 #define qtov__rsvd1_SHIFT 19 1004 #define qtov_rsvd1_MASK 0x0000003f 1005 #define qtov_rsvd1_WORD qtov /* reserved */ 1006 #define qtov_rttov_SHIFT 18 1007 #define qtov_rttov_MASK 0x00000001 1008 #define qtov_rttov_WORD qtov /* R_T_TOV value */ 1009 #define qtov_rsvd2_SHIFT 0 1010 #define qtov_rsvd2_MASK 0x0003ffff 1011 #define qtov_rsvd2_WORD qtov /* reserved */ 1012 }; 1013 1014 1015 typedef struct _RPL { /* Structure is in Big Endian format */ 1016 uint32_t maxsize; 1017 uint32_t index; 1018 } RPL; 1019 1020 typedef struct _PORT_NUM_BLK { 1021 uint32_t portNum; 1022 uint32_t portID; 1023 struct lpfc_name portName; 1024 } PORT_NUM_BLK; 1025 1026 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 1027 uint32_t listLen; 1028 uint32_t index; 1029 PORT_NUM_BLK port_num_blk; 1030 } RPL_RSP; 1031 1032 /* This is used for RSCN command */ 1033 typedef struct _D_ID { /* Structure is in Big Endian format */ 1034 union { 1035 uint32_t word; 1036 struct { 1037 #ifdef __BIG_ENDIAN_BITFIELD 1038 uint8_t resv; 1039 uint8_t domain; 1040 uint8_t area; 1041 uint8_t id; 1042 #else /* __LITTLE_ENDIAN_BITFIELD */ 1043 uint8_t id; 1044 uint8_t area; 1045 uint8_t domain; 1046 uint8_t resv; 1047 #endif 1048 } b; 1049 } un; 1050 } D_ID; 1051 1052 #define RSCN_ADDRESS_FORMAT_PORT 0x0 1053 #define RSCN_ADDRESS_FORMAT_AREA 0x1 1054 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 1055 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 1056 #define RSCN_ADDRESS_FORMAT_MASK 0x3 1057 1058 /* 1059 * Structure to define all ELS Payload types 1060 */ 1061 1062 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 1063 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1064 uint8_t elsByte1; 1065 uint8_t elsByte2; 1066 uint8_t elsByte3; 1067 union { 1068 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 1069 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 1070 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 1071 PRLI prli; /* Payload for PRLI/ACC */ 1072 PRLO prlo; /* Payload for PRLO/ACC */ 1073 ADISC adisc; /* Payload for ADISC/ACC */ 1074 FARP farp; /* Payload for FARP/ACC */ 1075 FAN fan; /* Payload for FAN */ 1076 SCR scr; /* Payload for SCR/ACC */ 1077 RNID rnid; /* Payload for RNID */ 1078 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1079 } un; 1080 } ELS_PKT; 1081 1082 /* 1083 * Link Cable Beacon (LCB) ELS Frame 1084 */ 1085 1086 struct fc_lcb_request_frame { 1087 uint32_t lcb_command; /* ELS command opcode (0x81) */ 1088 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1089 #define LPFC_LCB_ON 0x1 1090 #define LPFC_LCB_OFF 0x2 1091 uint8_t reserved[2]; 1092 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ 1093 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1094 #define LPFC_LCB_GREEN 0x1 1095 #define LPFC_LCB_AMBER 0x2 1096 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1097 #define LCB_CAPABILITY_DURATION 1 1098 #define BEACON_VERSION_V1 1 1099 #define BEACON_VERSION_V0 0 1100 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1101 }; 1102 1103 /* 1104 * Link Cable Beacon (LCB) ELS Response Frame 1105 */ 1106 struct fc_lcb_res_frame { 1107 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */ 1108 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1109 uint8_t reserved[2]; 1110 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ 1111 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1112 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1113 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1114 }; 1115 1116 /* 1117 * Read Diagnostic Parameters (RDP) ELS frame. 1118 */ 1119 #define SFF_PG0_IDENT_SFP 0x3 1120 1121 #define SFP_FLAG_PT_OPTICAL 0x0 1122 #define SFP_FLAG_PT_SWLASER 0x01 1123 #define SFP_FLAG_PT_LWLASER_LC1310 0x02 1124 #define SFP_FLAG_PT_LWLASER_LL1550 0x03 1125 #define SFP_FLAG_PT_MASK 0x0F 1126 #define SFP_FLAG_PT_SHIFT 0 1127 1128 #define SFP_FLAG_IS_OPTICAL_PORT 0x01 1129 #define SFP_FLAG_IS_OPTICAL_MASK 0x010 1130 #define SFP_FLAG_IS_OPTICAL_SHIFT 4 1131 1132 #define SFP_FLAG_IS_DESC_VALID 0x01 1133 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020 1134 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5 1135 1136 #define SFP_FLAG_CT_UNKNOWN 0x0 1137 #define SFP_FLAG_CT_SFP_PLUS 0x01 1138 #define SFP_FLAG_CT_MASK 0x3C 1139 #define SFP_FLAG_CT_SHIFT 6 1140 1141 struct fc_rdp_port_name_info { 1142 uint8_t wwnn[8]; 1143 uint8_t wwpn[8]; 1144 }; 1145 1146 1147 /* 1148 * Link Error Status Block Structure (FC-FS-3) for RDP 1149 * This similar to RPS ELS 1150 */ 1151 struct fc_link_status { 1152 uint32_t link_failure_cnt; 1153 uint32_t loss_of_synch_cnt; 1154 uint32_t loss_of_signal_cnt; 1155 uint32_t primitive_seq_proto_err; 1156 uint32_t invalid_trans_word; 1157 uint32_t invalid_crc_cnt; 1158 1159 }; 1160 1161 #define RDP_PORT_NAMES_DESC_TAG 0x00010003 1162 struct fc_rdp_port_name_desc { 1163 uint32_t tag; /* 0001 0003h */ 1164 uint32_t length; /* set to size of payload struct */ 1165 struct fc_rdp_port_name_info port_names; 1166 }; 1167 1168 1169 struct fc_rdp_fec_info { 1170 uint32_t CorrectedBlocks; 1171 uint32_t UncorrectableBlocks; 1172 }; 1173 1174 #define RDP_FEC_DESC_TAG 0x00010005 1175 struct fc_fec_rdp_desc { 1176 uint32_t tag; 1177 uint32_t length; 1178 struct fc_rdp_fec_info info; 1179 }; 1180 1181 struct fc_rdp_link_error_status_payload_info { 1182 struct fc_link_status link_status; /* 24 bytes */ 1183 uint32_t port_type; /* bits 31-30 only */ 1184 }; 1185 1186 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002 1187 struct fc_rdp_link_error_status_desc { 1188 uint32_t tag; /* 0001 0002h */ 1189 uint32_t length; /* set to size of payload struct */ 1190 struct fc_rdp_link_error_status_payload_info info; 1191 }; 1192 1193 #define VN_PT_PHY_UNKNOWN 0x00 1194 #define VN_PT_PHY_PF_PORT 0x01 1195 #define VN_PT_PHY_ETH_MAC 0x10 1196 #define VN_PT_PHY_SHIFT 30 1197 1198 #define RDP_PS_1GB 0x8000 1199 #define RDP_PS_2GB 0x4000 1200 #define RDP_PS_4GB 0x2000 1201 #define RDP_PS_10GB 0x1000 1202 #define RDP_PS_8GB 0x0800 1203 #define RDP_PS_16GB 0x0400 1204 #define RDP_PS_32GB 0x0200 1205 #define RDP_PS_64GB 0x0100 1206 #define RDP_PS_128GB 0x0080 1207 #define RDP_PS_256GB 0x0040 1208 1209 #define RDP_CAP_USER_CONFIGURED 0x0002 1210 #define RDP_CAP_UNKNOWN 0x0001 1211 #define RDP_PS_UNKNOWN 0x0002 1212 #define RDP_PS_NOT_ESTABLISHED 0x0001 1213 1214 struct fc_rdp_port_speed { 1215 uint16_t capabilities; 1216 uint16_t speed; 1217 }; 1218 1219 struct fc_rdp_port_speed_info { 1220 struct fc_rdp_port_speed port_speed; 1221 }; 1222 1223 #define RDP_PORT_SPEED_DESC_TAG 0x00010001 1224 struct fc_rdp_port_speed_desc { 1225 uint32_t tag; /* 00010001h */ 1226 uint32_t length; /* set to size of payload struct */ 1227 struct fc_rdp_port_speed_info info; 1228 }; 1229 1230 #define RDP_NPORT_ID_SIZE 4 1231 #define RDP_N_PORT_DESC_TAG 0x00000003 1232 struct fc_rdp_nport_desc { 1233 uint32_t tag; /* 0000 0003h, big endian */ 1234 uint32_t length; /* size of RDP_N_PORT_ID struct */ 1235 uint32_t nport_id : 12; 1236 uint32_t reserved : 8; 1237 }; 1238 1239 1240 struct fc_rdp_link_service_info { 1241 uint32_t els_req; /* Request payload word 0 value.*/ 1242 }; 1243 1244 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001 1245 struct fc_rdp_link_service_desc { 1246 uint32_t tag; /* Descriptor tag 1 */ 1247 uint32_t length; /* set to size of payload struct. */ 1248 struct fc_rdp_link_service_info payload; 1249 /* must be ELS req Word 0(0x18) */ 1250 }; 1251 1252 struct fc_rdp_sfp_info { 1253 uint16_t temperature; 1254 uint16_t vcc; 1255 uint16_t tx_bias; 1256 uint16_t tx_power; 1257 uint16_t rx_power; 1258 uint16_t flags; 1259 }; 1260 1261 #define RDP_SFP_DESC_TAG 0x00010000 1262 struct fc_rdp_sfp_desc { 1263 uint32_t tag; 1264 uint32_t length; /* set to size of sfp_info struct */ 1265 struct fc_rdp_sfp_info sfp_info; 1266 }; 1267 1268 /* Buffer Credit Descriptor */ 1269 struct fc_rdp_bbc_info { 1270 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */ 1271 uint32_t attached_port_bbc; 1272 uint32_t rtt; /* Round trip time */ 1273 }; 1274 #define RDP_BBC_DESC_TAG 0x00010006 1275 struct fc_rdp_bbc_desc { 1276 uint32_t tag; 1277 uint32_t length; 1278 struct fc_rdp_bbc_info bbc_info; 1279 }; 1280 1281 /* Optical Element Type Transgression Flags */ 1282 #define RDP_OET_LOW_WARNING 0x1 1283 #define RDP_OET_HIGH_WARNING 0x2 1284 #define RDP_OET_LOW_ALARM 0x4 1285 #define RDP_OET_HIGH_ALARM 0x8 1286 1287 #define RDP_OED_TEMPERATURE 0x1 1288 #define RDP_OED_VOLTAGE 0x2 1289 #define RDP_OED_TXBIAS 0x3 1290 #define RDP_OED_TXPOWER 0x4 1291 #define RDP_OED_RXPOWER 0x5 1292 1293 #define RDP_OED_TYPE_SHIFT 28 1294 /* Optical Element Data descriptor */ 1295 struct fc_rdp_oed_info { 1296 uint16_t hi_alarm; 1297 uint16_t lo_alarm; 1298 uint16_t hi_warning; 1299 uint16_t lo_warning; 1300 uint32_t function_flags; 1301 }; 1302 #define RDP_OED_DESC_TAG 0x00010007 1303 struct fc_rdp_oed_sfp_desc { 1304 uint32_t tag; 1305 uint32_t length; 1306 struct fc_rdp_oed_info oed_info; 1307 }; 1308 1309 /* Optical Product Data descriptor */ 1310 struct fc_rdp_opd_sfp_info { 1311 uint8_t vendor_name[16]; 1312 uint8_t model_number[16]; 1313 uint8_t serial_number[16]; 1314 uint8_t revision[4]; 1315 uint8_t date[8]; 1316 }; 1317 1318 #define RDP_OPD_DESC_TAG 0x00010008 1319 struct fc_rdp_opd_sfp_desc { 1320 uint32_t tag; 1321 uint32_t length; 1322 struct fc_rdp_opd_sfp_info opd_info; 1323 }; 1324 1325 struct fc_rdp_req_frame { 1326 uint32_t rdp_command; /* ELS command opcode (0x18)*/ 1327 uint32_t rdp_des_length; /* RDP Payload Word 1 */ 1328 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */ 1329 }; 1330 1331 1332 struct fc_rdp_res_frame { 1333 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */ 1334 uint32_t length; /* FC Word 1 */ 1335 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */ 1336 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */ 1337 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */ 1338 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */ 1339 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */ 1340 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */ 1341 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/ 1342 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/ 1343 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/ 1344 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/ 1345 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/ 1346 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/ 1347 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/ 1348 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/ 1349 }; 1350 1351 1352 /* UVEM */ 1353 1354 #define LPFC_UVEM_SIZE 60 1355 #define LPFC_UVEM_VEM_ID_DESC_SIZE 16 1356 #define LPFC_UVEM_VE_MAP_DESC_SIZE 20 1357 1358 #define VEM_ID_DESC_TAG 0x0001000A 1359 struct lpfc_vem_id_desc { 1360 uint32_t tag; 1361 uint32_t length; 1362 uint8_t vem_id[16]; 1363 }; 1364 1365 #define LPFC_QFPA_SIZE 4 1366 1367 #define INSTANTIATED_VE_DESC_TAG 0x0001000B 1368 struct instantiated_ve_desc { 1369 uint32_t tag; 1370 uint32_t length; 1371 uint8_t global_vem_id[16]; 1372 uint32_t word6; 1373 #define lpfc_instantiated_local_id_SHIFT 0 1374 #define lpfc_instantiated_local_id_MASK 0x000000ff 1375 #define lpfc_instantiated_local_id_WORD word6 1376 #define lpfc_instantiated_nport_id_SHIFT 8 1377 #define lpfc_instantiated_nport_id_MASK 0x00ffffff 1378 #define lpfc_instantiated_nport_id_WORD word6 1379 }; 1380 1381 #define DEINSTANTIATED_VE_DESC_TAG 0x0001000C 1382 struct deinstantiated_ve_desc { 1383 uint32_t tag; 1384 uint32_t length; 1385 uint8_t global_vem_id[16]; 1386 uint32_t word6; 1387 #define lpfc_deinstantiated_nport_id_SHIFT 0 1388 #define lpfc_deinstantiated_nport_id_MASK 0x000000ff 1389 #define lpfc_deinstantiated_nport_id_WORD word6 1390 #define lpfc_deinstantiated_local_id_SHIFT 24 1391 #define lpfc_deinstantiated_local_id_MASK 0x00ffffff 1392 #define lpfc_deinstantiated_local_id_WORD word6 1393 }; 1394 1395 /* Query Fabric Priority Allocation Response */ 1396 #define LPFC_PRIORITY_RANGE_DESC_SIZE 12 1397 1398 struct priority_range_desc { 1399 uint32_t tag; 1400 uint32_t length; 1401 uint8_t lo_range; 1402 uint8_t hi_range; 1403 uint8_t qos_priority; 1404 uint8_t local_ve_id; 1405 }; 1406 1407 struct fc_qfpa_res { 1408 uint32_t reply_sequence; /* LS_ACC or LS_RJT */ 1409 uint32_t length; /* FC Word 1 */ 1410 struct priority_range_desc desc[1]; 1411 }; 1412 1413 /* Application Server command code */ 1414 /* VMID */ 1415 1416 #define SLI_CT_APP_SEV_Subtypes 0x20 /* Application Server subtype */ 1417 1418 #define SLI_CTAS_GAPPIA_ENT 0x0100 /* Get Application Identifier */ 1419 #define SLI_CTAS_GALLAPPIA 0x0101 /* Get All Application Identifier */ 1420 #define SLI_CTAS_GALLAPPIA_ID 0x0102 /* Get All Application Identifier */ 1421 /* for Nport */ 1422 #define SLI_CTAS_GAPPIA_IDAPP 0x0103 /* Get Application Identifier */ 1423 /* for Nport */ 1424 #define SLI_CTAS_RAPP_IDENT 0x0200 /* Register Application Identifier */ 1425 #define SLI_CTAS_DAPP_IDENT 0x0300 /* Deregister Application */ 1426 /* Identifier */ 1427 #define SLI_CTAS_DALLAPP_ID 0x0301 /* Deregister All Application */ 1428 /* Identifier */ 1429 1430 struct entity_id_object { 1431 uint8_t entity_id_len; 1432 uint8_t entity_id[255]; /* VM UUID */ 1433 }; 1434 1435 struct app_id_object { 1436 __be32 port_id; 1437 __be32 app_id; 1438 struct entity_id_object obj; 1439 }; 1440 1441 struct lpfc_vmid_rapp_ident_list { 1442 __be32 no_of_objects; 1443 struct entity_id_object obj[]; 1444 }; 1445 1446 struct lpfc_vmid_dapp_ident_list { 1447 __be32 no_of_objects; 1448 struct entity_id_object obj[]; 1449 }; 1450 1451 #define GALLAPPIA_ID_LAST 0x80 1452 struct lpfc_vmid_gallapp_ident_list { 1453 uint8_t control; 1454 uint8_t reserved[3]; 1455 struct app_id_object app_id; 1456 }; 1457 1458 #define RAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) 1459 #define DAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) 1460 #define GALLAPPIA_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) 1461 #define DALLAPP_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) 1462 1463 /******** FDMI ********/ 1464 1465 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */ 1466 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */ 1467 1468 /* Definitions for HBA / Port attribute entries */ 1469 1470 /* Attribute Entry Structures */ 1471 1472 struct lpfc_fdmi_attr_u32 { 1473 __be16 type; 1474 __be16 len; 1475 __be32 value_u32; 1476 }; 1477 1478 struct lpfc_fdmi_attr_wwn { 1479 __be16 type; 1480 __be16 len; 1481 1482 /* Keep as u8[8] instead of __be64 to avoid accidental zero padding 1483 * by compiler 1484 */ 1485 u8 name[8]; 1486 }; 1487 1488 struct lpfc_fdmi_attr_fullwwn { 1489 __be16 type; 1490 __be16 len; 1491 1492 /* Keep as u8[8] instead of __be64 to avoid accidental zero padding 1493 * by compiler 1494 */ 1495 u8 nname[8]; 1496 u8 pname[8]; 1497 }; 1498 1499 struct lpfc_fdmi_attr_fc4types { 1500 __be16 type; 1501 __be16 len; 1502 u8 value_types[32]; 1503 }; 1504 1505 struct lpfc_fdmi_attr_string { 1506 __be16 type; 1507 __be16 len; 1508 char value_string[256]; 1509 }; 1510 1511 /* Maximum FDMI attribute length is Type+Len (4 bytes) + 256 byte string */ 1512 #define FDMI_MAX_ATTRLEN sizeof(struct lpfc_fdmi_attr_string) 1513 1514 /* 1515 * HBA Attribute Block 1516 */ 1517 struct lpfc_fdmi_attr_block { 1518 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1519 /* Variable Length Attribute Entry TLV's follow */ 1520 }; 1521 1522 /* 1523 * Port Entry 1524 */ 1525 struct lpfc_fdmi_port_entry { 1526 struct lpfc_name PortName; 1527 }; 1528 1529 /* 1530 * HBA Identifier 1531 */ 1532 struct lpfc_fdmi_hba_ident { 1533 struct lpfc_name PortName; 1534 }; 1535 1536 /* 1537 * Registered Port List Format 1538 */ 1539 struct lpfc_fdmi_reg_port_list { 1540 __be32 EntryCnt; 1541 struct lpfc_fdmi_port_entry pe; 1542 }; 1543 1544 /* 1545 * Register HBA(RHBA) 1546 */ 1547 struct lpfc_fdmi_reg_hba { 1548 struct lpfc_fdmi_hba_ident hi; 1549 struct lpfc_fdmi_reg_port_list rpl; 1550 }; 1551 1552 /******** MI MIB ********/ 1553 #define SLI_CT_MIB_Subtypes 0x11 1554 1555 /* 1556 * Register HBA Attributes (RHAT) 1557 */ 1558 struct lpfc_fdmi_reg_hbaattr { 1559 struct lpfc_name HBA_PortName; 1560 struct lpfc_fdmi_attr_block ab; 1561 }; 1562 1563 /* 1564 * Register Port Attributes (RPA) 1565 */ 1566 struct lpfc_fdmi_reg_portattr { 1567 struct lpfc_name PortName; 1568 struct lpfc_fdmi_attr_block ab; 1569 }; 1570 1571 /* 1572 * HBA MAnagement Operations Command Codes 1573 */ 1574 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1575 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1576 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1577 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1578 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */ 1579 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1580 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1581 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1582 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1583 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1584 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */ 1585 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1586 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */ 1587 1588 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */ 1589 1590 /* 1591 * HBA Attribute Types 1592 */ 1593 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */ 1594 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */ 1595 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */ 1596 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */ 1597 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */ 1598 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */ 1599 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */ 1600 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */ 1601 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */ 1602 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */ 1603 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */ 1604 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */ 1605 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */ 1606 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */ 1607 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */ 1608 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */ 1609 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */ 1610 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */ 1611 1612 /* Bit mask for all individual HBA attributes */ 1613 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001 1614 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002 1615 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004 1616 #define LPFC_FDMI_HBA_ATTR_model 0x00000008 1617 #define LPFC_FDMI_HBA_ATTR_description 0x00000010 1618 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020 1619 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040 1620 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080 1621 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100 1622 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200 1623 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400 1624 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800 1625 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */ 1626 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000 1627 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000 1628 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000 1629 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */ 1630 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000 1631 1632 /* Bit mask for FDMI-1 defined HBA attributes */ 1633 #define LPFC_FDMI1_HBA_ATTR 0x000007ff 1634 1635 /* Bit mask for FDMI-2 defined HBA attributes */ 1636 /* Skip vendor_info and bios_state */ 1637 #define LPFC_FDMI2_HBA_ATTR 0x0002efff 1638 1639 /* 1640 * Port Attribute Types 1641 */ 1642 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */ 1643 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */ 1644 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */ 1645 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */ 1646 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */ 1647 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */ 1648 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */ 1649 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */ 1650 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */ 1651 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */ 1652 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */ 1653 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */ 1654 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */ 1655 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */ 1656 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */ 1657 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */ 1658 #define RPRT_VENDOR_MI 0xf047 /* vendor ascii string */ 1659 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */ 1660 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */ 1661 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */ 1662 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */ 1663 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */ 1664 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */ 1665 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */ 1666 1667 /* Bit mask for all individual PORT attributes */ 1668 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001 1669 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002 1670 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004 1671 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008 1672 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010 1673 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020 1674 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040 1675 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080 1676 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100 1677 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200 1678 #define LPFC_FDMI_PORT_ATTR_class 0x00000400 1679 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800 1680 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000 1681 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000 1682 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000 1683 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000 1684 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */ 1685 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */ 1686 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */ 1687 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */ 1688 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */ 1689 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */ 1690 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */ 1691 #define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000 /* Vendor specific */ 1692 1693 /* Bit mask for FDMI-1 defined PORT attributes */ 1694 #define LPFC_FDMI1_PORT_ATTR 0x0000003f 1695 1696 /* Bit mask for FDMI-2 defined PORT attributes */ 1697 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff 1698 1699 /* Bit mask for Smart SAN defined PORT attributes */ 1700 #define LPFC_FDMI2_SMART_ATTR 0x007fffff 1701 1702 /* Defines for PORT port state attribute */ 1703 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1 1704 #define LPFC_FDMI_PORTSTATE_ONLINE 2 1705 1706 /* Defines for PORT port type attribute */ 1707 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0 1708 #define LPFC_FDMI_PORTTYPE_NPORT 1 1709 #define LPFC_FDMI_PORTTYPE_NLPORT 2 1710 1711 /* 1712 * Begin HBA configuration parameters. 1713 * The PCI configuration register BAR assignments are: 1714 * BAR0, offset 0x10 - SLIM base memory address 1715 * BAR1, offset 0x14 - SLIM base memory high address 1716 * BAR2, offset 0x18 - REGISTER base memory address 1717 * BAR3, offset 0x1c - REGISTER base memory high address 1718 * BAR4, offset 0x20 - BIU I/O registers 1719 * BAR5, offset 0x24 - REGISTER base io high address 1720 */ 1721 1722 /* Number of rings currently used and available. */ 1723 #define MAX_SLI3_CONFIGURED_RINGS 3 1724 #define MAX_SLI3_RINGS 4 1725 1726 /* IOCB / Mailbox is owned by FireFly */ 1727 #define OWN_CHIP 1 1728 1729 /* IOCB / Mailbox is owned by Host */ 1730 #define OWN_HOST 0 1731 1732 /* Number of 4-byte words in an IOCB. */ 1733 #define IOCB_WORD_SZ 8 1734 1735 /* network headers for Dfctl field */ 1736 #define FC_NET_HDR 0x20 1737 1738 /* Start FireFly Register definitions */ 1739 #define PCI_VENDOR_ID_EMULEX 0x10df 1740 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1741 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1742 #define PCI_DEVICE_ID_BALIUS 0xe131 1743 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1744 #define PCI_DEVICE_ID_LANCER_FC 0xe200 1745 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1746 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1747 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1748 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300 1749 #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400 1750 #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500 1751 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1752 #define PCI_DEVICE_ID_SAT_MID 0xf015 1753 #define PCI_DEVICE_ID_RFLY 0xf095 1754 #define PCI_DEVICE_ID_PFLY 0xf098 1755 #define PCI_DEVICE_ID_LP101 0xf0a1 1756 #define PCI_DEVICE_ID_TFLY 0xf0a5 1757 #define PCI_DEVICE_ID_BSMB 0xf0d1 1758 #define PCI_DEVICE_ID_BMID 0xf0d5 1759 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1760 #define PCI_DEVICE_ID_ZMID 0xf0e5 1761 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1762 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1763 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1764 #define PCI_DEVICE_ID_SAT 0xf100 1765 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1766 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1767 #define PCI_DEVICE_ID_FALCON 0xf180 1768 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1769 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1770 #define PCI_DEVICE_ID_CENTAUR 0xf900 1771 #define PCI_DEVICE_ID_PEGASUS 0xf980 1772 #define PCI_DEVICE_ID_THOR 0xfa00 1773 #define PCI_DEVICE_ID_VIPER 0xfb00 1774 #define PCI_DEVICE_ID_LP10000S 0xfc00 1775 #define PCI_DEVICE_ID_LP11000S 0xfc10 1776 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1777 #define PCI_DEVICE_ID_SAT_S 0xfc40 1778 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1779 #define PCI_DEVICE_ID_HELIOS 0xfd00 1780 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1781 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1782 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1783 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1784 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1785 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1786 #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1787 #define PCI_DEVICE_ID_TOMCAT 0x0714 1788 #define PCI_DEVICE_ID_SKYHAWK 0x0724 1789 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c 1790 #define PCI_VENDOR_ID_ATTO 0x117c 1791 #define PCI_DEVICE_ID_CLRY_16XE 0x0064 1792 #define PCI_DEVICE_ID_CLRY_161E 0x0063 1793 #define PCI_DEVICE_ID_CLRY_162E 0x0064 1794 #define PCI_DEVICE_ID_CLRY_164E 0x0065 1795 #define PCI_DEVICE_ID_CLRY_16XP 0x0094 1796 #define PCI_DEVICE_ID_CLRY_161P 0x00a0 1797 #define PCI_DEVICE_ID_CLRY_162P 0x0094 1798 #define PCI_DEVICE_ID_CLRY_164P 0x00a1 1799 #define PCI_DEVICE_ID_CLRY_32XE 0x0094 1800 #define PCI_DEVICE_ID_CLRY_321E 0x00a2 1801 #define PCI_DEVICE_ID_CLRY_322E 0x00a3 1802 #define PCI_DEVICE_ID_CLRY_324E 0x00ac 1803 #define PCI_DEVICE_ID_CLRY_32XP 0x00bb 1804 #define PCI_DEVICE_ID_CLRY_321P 0x00bc 1805 #define PCI_DEVICE_ID_CLRY_322P 0x00bd 1806 #define PCI_DEVICE_ID_CLRY_324P 0x00be 1807 #define PCI_DEVICE_ID_TLFC_2 0x0064 1808 #define PCI_DEVICE_ID_TLFC_2XX2 0x4064 1809 #define PCI_DEVICE_ID_TLFC_3 0x0094 1810 #define PCI_DEVICE_ID_TLFC_3162 0x40a6 1811 #define PCI_DEVICE_ID_TLFC_3322 0x40a7 1812 1813 #define JEDEC_ID_ADDRESS 0x0080001c 1814 #define FIREFLY_JEDEC_ID 0x1ACC 1815 #define SUPERFLY_JEDEC_ID 0x0020 1816 #define DRAGONFLY_JEDEC_ID 0x0021 1817 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1818 #define CENTAUR_2G_JEDEC_ID 0x0026 1819 #define CENTAUR_1G_JEDEC_ID 0x0028 1820 #define PEGASUS_ORION_JEDEC_ID 0x0036 1821 #define PEGASUS_JEDEC_ID 0x0038 1822 #define THOR_JEDEC_ID 0x0012 1823 #define HELIOS_JEDEC_ID 0x0364 1824 #define ZEPHYR_JEDEC_ID 0x0577 1825 #define VIPER_JEDEC_ID 0x4838 1826 #define SATURN_JEDEC_ID 0x1004 1827 1828 #define JEDEC_ID_MASK 0x0FFFF000 1829 #define JEDEC_ID_SHIFT 12 1830 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1831 1832 typedef struct { /* FireFly BIU registers */ 1833 uint32_t hostAtt; /* See definitions for Host Attention 1834 register */ 1835 uint32_t chipAtt; /* See definitions for Chip Attention 1836 register */ 1837 uint32_t hostStatus; /* See definitions for Host Status register */ 1838 uint32_t hostControl; /* See definitions for Host Control register */ 1839 uint32_t buiConfig; /* See definitions for BIU configuration 1840 register */ 1841 } FF_REGS; 1842 1843 /* IO Register size in bytes */ 1844 #define FF_REG_AREA_SIZE 256 1845 1846 /* Host Attention Register */ 1847 1848 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1849 1850 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1851 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1852 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1853 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1854 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1855 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1856 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1857 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1858 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1859 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1860 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1861 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1862 #define HA_LATT 0x20000000 /* Bit 29 */ 1863 #define HA_MBATT 0x40000000 /* Bit 30 */ 1864 #define HA_ERATT 0x80000000 /* Bit 31 */ 1865 1866 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1867 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1868 #define HA_RXATT 0x00000008 /* Bit 3 */ 1869 #define HA_RXMASK 0x0000000f 1870 1871 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1872 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1873 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1874 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1875 1876 #define HA_R0_POS 3 1877 #define HA_R1_POS 7 1878 #define HA_R2_POS 11 1879 #define HA_R3_POS 15 1880 #define HA_LE_POS 29 1881 #define HA_MB_POS 30 1882 #define HA_ER_POS 31 1883 /* Chip Attention Register */ 1884 1885 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1886 1887 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1888 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1889 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1890 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1891 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1892 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1893 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1894 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1895 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1896 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1897 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1898 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1899 #define CA_MBATT 0x40000000 /* Bit 30 */ 1900 1901 /* Host Status Register */ 1902 1903 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1904 1905 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1906 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1907 #define HS_FFER8 0x01000000 /* Bit 24 */ 1908 #define HS_FFER7 0x02000000 /* Bit 25 */ 1909 #define HS_FFER6 0x04000000 /* Bit 26 */ 1910 #define HS_FFER5 0x08000000 /* Bit 27 */ 1911 #define HS_FFER4 0x10000000 /* Bit 28 */ 1912 #define HS_FFER3 0x20000000 /* Bit 29 */ 1913 #define HS_FFER2 0x40000000 /* Bit 30 */ 1914 #define HS_FFER1 0x80000000 /* Bit 31 */ 1915 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1916 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1917 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1918 /* Host Control Register */ 1919 1920 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1921 1922 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1923 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1924 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1925 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1926 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1927 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1928 #define HC_INITMB 0x04000000 /* Bit 26 */ 1929 #define HC_INITFF 0x08000000 /* Bit 27 */ 1930 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1931 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1932 1933 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1934 #define MSIX_DFLT_ID 0 1935 #define MSIX_RNG0_ID 0 1936 #define MSIX_RNG1_ID 1 1937 #define MSIX_RNG2_ID 2 1938 #define MSIX_RNG3_ID 3 1939 1940 #define MSIX_LINK_ID 4 1941 #define MSIX_MBOX_ID 5 1942 1943 #define MSIX_SPARE0_ID 6 1944 #define MSIX_SPARE1_ID 7 1945 1946 /* Mailbox Commands */ 1947 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1948 #define MBX_LOAD_SM 0x01 1949 #define MBX_READ_NV 0x02 1950 #define MBX_WRITE_NV 0x03 1951 #define MBX_RUN_BIU_DIAG 0x04 1952 #define MBX_INIT_LINK 0x05 1953 #define MBX_DOWN_LINK 0x06 1954 #define MBX_CONFIG_LINK 0x07 1955 #define MBX_CONFIG_RING 0x09 1956 #define MBX_RESET_RING 0x0A 1957 #define MBX_READ_CONFIG 0x0B 1958 #define MBX_READ_RCONFIG 0x0C 1959 #define MBX_READ_SPARM 0x0D 1960 #define MBX_READ_STATUS 0x0E 1961 #define MBX_READ_RPI 0x0F 1962 #define MBX_READ_XRI 0x10 1963 #define MBX_READ_REV 0x11 1964 #define MBX_READ_LNK_STAT 0x12 1965 #define MBX_REG_LOGIN 0x13 1966 #define MBX_UNREG_LOGIN 0x14 1967 #define MBX_CLEAR_LA 0x16 1968 #define MBX_DUMP_MEMORY 0x17 1969 #define MBX_DUMP_CONTEXT 0x18 1970 #define MBX_RUN_DIAGS 0x19 1971 #define MBX_RESTART 0x1A 1972 #define MBX_UPDATE_CFG 0x1B 1973 #define MBX_DOWN_LOAD 0x1C 1974 #define MBX_DEL_LD_ENTRY 0x1D 1975 #define MBX_RUN_PROGRAM 0x1E 1976 #define MBX_SET_MASK 0x20 1977 #define MBX_SET_VARIABLE 0x21 1978 #define MBX_UNREG_D_ID 0x23 1979 #define MBX_KILL_BOARD 0x24 1980 #define MBX_CONFIG_FARP 0x25 1981 #define MBX_BEACON 0x2A 1982 #define MBX_CONFIG_MSI 0x30 1983 #define MBX_HEARTBEAT 0x31 1984 #define MBX_WRITE_VPARMS 0x32 1985 #define MBX_ASYNCEVT_ENABLE 0x33 1986 #define MBX_READ_EVENT_LOG_STATUS 0x37 1987 #define MBX_READ_EVENT_LOG 0x38 1988 #define MBX_WRITE_EVENT_LOG 0x39 1989 1990 #define MBX_PORT_CAPABILITIES 0x3B 1991 #define MBX_PORT_IOV_CONTROL 0x3C 1992 1993 #define MBX_CONFIG_HBQ 0x7C 1994 #define MBX_LOAD_AREA 0x81 1995 #define MBX_RUN_BIU_DIAG64 0x84 1996 #define MBX_CONFIG_PORT 0x88 1997 #define MBX_READ_SPARM64 0x8D 1998 #define MBX_READ_RPI64 0x8F 1999 #define MBX_REG_LOGIN64 0x93 2000 #define MBX_READ_TOPOLOGY 0x95 2001 #define MBX_REG_VPI 0x96 2002 #define MBX_UNREG_VPI 0x97 2003 2004 #define MBX_WRITE_WWN 0x98 2005 #define MBX_SET_DEBUG 0x99 2006 #define MBX_LOAD_EXP_ROM 0x9C 2007 #define MBX_SLI4_CONFIG 0x9B 2008 #define MBX_SLI4_REQ_FTRS 0x9D 2009 #define MBX_MAX_CMDS 0x9E 2010 #define MBX_RESUME_RPI 0x9E 2011 #define MBX_SLI2_CMD_MASK 0x80 2012 #define MBX_REG_VFI 0x9F 2013 #define MBX_REG_FCFI 0xA0 2014 #define MBX_UNREG_VFI 0xA1 2015 #define MBX_UNREG_FCFI 0xA2 2016 #define MBX_INIT_VFI 0xA3 2017 #define MBX_INIT_VPI 0xA4 2018 #define MBX_ACCESS_VDATA 0xA5 2019 #define MBX_REG_FCFI_MRQ 0xAF 2020 2021 #define MBX_AUTH_PORT 0xF8 2022 #define MBX_SECURITY_MGMT 0xF9 2023 2024 /* IOCB Commands */ 2025 2026 #define CMD_RCV_SEQUENCE_CX 0x01 2027 #define CMD_XMIT_SEQUENCE_CR 0x02 2028 #define CMD_XMIT_SEQUENCE_CX 0x03 2029 #define CMD_XMIT_BCAST_CN 0x04 2030 #define CMD_XMIT_BCAST_CX 0x05 2031 #define CMD_QUE_RING_BUF_CN 0x06 2032 #define CMD_QUE_XRI_BUF_CX 0x07 2033 #define CMD_IOCB_CONTINUE_CN 0x08 2034 #define CMD_RET_XRI_BUF_CX 0x09 2035 #define CMD_ELS_REQUEST_CR 0x0A 2036 #define CMD_ELS_REQUEST_CX 0x0B 2037 #define CMD_RCV_ELS_REQ_CX 0x0D 2038 #define CMD_ABORT_XRI_CN 0x0E 2039 #define CMD_ABORT_XRI_CX 0x0F 2040 #define CMD_CLOSE_XRI_CN 0x10 2041 #define CMD_CLOSE_XRI_CX 0x11 2042 #define CMD_CREATE_XRI_CR 0x12 2043 #define CMD_CREATE_XRI_CX 0x13 2044 #define CMD_GET_RPI_CN 0x14 2045 #define CMD_XMIT_ELS_RSP_CX 0x15 2046 #define CMD_GET_RPI_CR 0x16 2047 #define CMD_XRI_ABORTED_CX 0x17 2048 #define CMD_FCP_IWRITE_CR 0x18 2049 #define CMD_FCP_IWRITE_CX 0x19 2050 #define CMD_FCP_IREAD_CR 0x1A 2051 #define CMD_FCP_IREAD_CX 0x1B 2052 #define CMD_FCP_ICMND_CR 0x1C 2053 #define CMD_FCP_ICMND_CX 0x1D 2054 #define CMD_FCP_TSEND_CX 0x1F 2055 #define CMD_FCP_TRECEIVE_CX 0x21 2056 #define CMD_FCP_TRSP_CX 0x23 2057 #define CMD_FCP_AUTO_TRSP_CX 0x29 2058 2059 #define CMD_ADAPTER_MSG 0x20 2060 #define CMD_ADAPTER_DUMP 0x22 2061 2062 /* SLI_2 IOCB Command Set */ 2063 2064 #define CMD_ASYNC_STATUS 0x7C 2065 #define CMD_RCV_SEQUENCE64_CX 0x81 2066 #define CMD_XMIT_SEQUENCE64_CR 0x82 2067 #define CMD_XMIT_SEQUENCE64_CX 0x83 2068 #define CMD_XMIT_BCAST64_CN 0x84 2069 #define CMD_XMIT_BCAST64_CX 0x85 2070 #define CMD_QUE_RING_BUF64_CN 0x86 2071 #define CMD_QUE_XRI_BUF64_CX 0x87 2072 #define CMD_IOCB_CONTINUE64_CN 0x88 2073 #define CMD_RET_XRI_BUF64_CX 0x89 2074 #define CMD_ELS_REQUEST64_CR 0x8A 2075 #define CMD_ELS_REQUEST64_CX 0x8B 2076 #define CMD_ABORT_MXRI64_CN 0x8C 2077 #define CMD_RCV_ELS_REQ64_CX 0x8D 2078 #define CMD_XMIT_ELS_RSP64_CX 0x95 2079 #define CMD_XMIT_BLS_RSP64_CX 0x97 2080 #define CMD_FCP_IWRITE64_CR 0x98 2081 #define CMD_FCP_IWRITE64_CX 0x99 2082 #define CMD_FCP_IREAD64_CR 0x9A 2083 #define CMD_FCP_IREAD64_CX 0x9B 2084 #define CMD_FCP_ICMND64_CR 0x9C 2085 #define CMD_FCP_ICMND64_CX 0x9D 2086 #define CMD_FCP_TSEND64_CX 0x9F 2087 #define CMD_FCP_TRECEIVE64_CX 0xA1 2088 #define CMD_FCP_TRSP64_CX 0xA3 2089 2090 #define CMD_QUE_XRI64_CX 0xB3 2091 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 2092 #define CMD_IOCB_RCV_ELS64_CX 0xB7 2093 #define CMD_IOCB_RET_XRI64_CX 0xB9 2094 #define CMD_IOCB_RCV_CONT64_CX 0xBB 2095 2096 #define CMD_GEN_REQUEST64_CR 0xC2 2097 #define CMD_GEN_REQUEST64_CX 0xC3 2098 2099 /* Unhandled SLI-3 Commands */ 2100 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 2101 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 2102 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 2103 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 2104 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 2105 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 2106 #define CMD_IOCB_RET_HBQE64_CN 0xCA 2107 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 2108 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 2109 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 2110 #define CMD_IOCB_LOGENTRY_CN 0x94 2111 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 2112 2113 /* Data Security SLI Commands */ 2114 #define DSSCMD_IWRITE64_CR 0xF8 2115 #define DSSCMD_IWRITE64_CX 0xF9 2116 #define DSSCMD_IREAD64_CR 0xFA 2117 #define DSSCMD_IREAD64_CX 0xFB 2118 2119 #define CMD_MAX_IOCB_CMD 0xFB 2120 #define CMD_IOCB_MASK 0xff 2121 2122 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 2123 iocb */ 2124 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 2125 /* 2126 * Define Status 2127 */ 2128 #define MBX_SUCCESS 0 2129 #define MBXERR_NUM_RINGS 1 2130 #define MBXERR_NUM_IOCBS 2 2131 #define MBXERR_IOCBS_EXCEEDED 3 2132 #define MBXERR_BAD_RING_NUMBER 4 2133 #define MBXERR_MASK_ENTRIES_RANGE 5 2134 #define MBXERR_MASKS_EXCEEDED 6 2135 #define MBXERR_BAD_PROFILE 7 2136 #define MBXERR_BAD_DEF_CLASS 8 2137 #define MBXERR_BAD_MAX_RESPONDER 9 2138 #define MBXERR_BAD_MAX_ORIGINATOR 10 2139 #define MBXERR_RPI_REGISTERED 11 2140 #define MBXERR_RPI_FULL 12 2141 #define MBXERR_NO_RESOURCES 13 2142 #define MBXERR_BAD_RCV_LENGTH 14 2143 #define MBXERR_DMA_ERROR 15 2144 #define MBXERR_ERROR 16 2145 #define MBXERR_LINK_DOWN 0x33 2146 #define MBXERR_SEC_NO_PERMISSION 0xF02 2147 #define MBX_NOT_FINISHED 255 2148 2149 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 2150 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 2151 2152 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 2153 2154 /* 2155 * return code Fail 2156 */ 2157 #define FAILURE 1 2158 2159 /* 2160 * Begin Structure Definitions for Mailbox Commands 2161 */ 2162 2163 typedef struct { 2164 #ifdef __BIG_ENDIAN_BITFIELD 2165 uint8_t tval; 2166 uint8_t tmask; 2167 uint8_t rval; 2168 uint8_t rmask; 2169 #else /* __LITTLE_ENDIAN_BITFIELD */ 2170 uint8_t rmask; 2171 uint8_t rval; 2172 uint8_t tmask; 2173 uint8_t tval; 2174 #endif 2175 } RR_REG; 2176 2177 struct ulp_bde { 2178 uint32_t bdeAddress; 2179 #ifdef __BIG_ENDIAN_BITFIELD 2180 uint32_t bdeReserved:4; 2181 uint32_t bdeAddrHigh:4; 2182 uint32_t bdeSize:24; 2183 #else /* __LITTLE_ENDIAN_BITFIELD */ 2184 uint32_t bdeSize:24; 2185 uint32_t bdeAddrHigh:4; 2186 uint32_t bdeReserved:4; 2187 #endif 2188 }; 2189 2190 typedef struct ULP_BDL { /* SLI-2 */ 2191 #ifdef __BIG_ENDIAN_BITFIELD 2192 uint32_t bdeFlags:8; /* BDL Flags */ 2193 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 2194 #else /* __LITTLE_ENDIAN_BITFIELD */ 2195 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 2196 uint32_t bdeFlags:8; /* BDL Flags */ 2197 #endif 2198 2199 uint32_t addrLow; /* Address 0:31 */ 2200 uint32_t addrHigh; /* Address 32:63 */ 2201 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 2202 } ULP_BDL; 2203 2204 /* 2205 * BlockGuard Definitions 2206 */ 2207 2208 enum lpfc_protgrp_type { 2209 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 2210 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 2211 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 2212 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 2213 }; 2214 2215 /* PDE Descriptors */ 2216 #define LPFC_PDE5_DESCRIPTOR 0x85 2217 #define LPFC_PDE6_DESCRIPTOR 0x86 2218 #define LPFC_PDE7_DESCRIPTOR 0x87 2219 2220 /* BlockGuard Opcodes */ 2221 #define BG_OP_IN_NODIF_OUT_CRC 0x0 2222 #define BG_OP_IN_CRC_OUT_NODIF 0x1 2223 #define BG_OP_IN_NODIF_OUT_CSUM 0x2 2224 #define BG_OP_IN_CSUM_OUT_NODIF 0x3 2225 #define BG_OP_IN_CRC_OUT_CRC 0x4 2226 #define BG_OP_IN_CSUM_OUT_CSUM 0x5 2227 #define BG_OP_IN_CRC_OUT_CSUM 0x6 2228 #define BG_OP_IN_CSUM_OUT_CRC 0x7 2229 #define BG_OP_RAW_MODE 0x8 2230 2231 struct lpfc_pde5 { 2232 uint32_t word0; 2233 #define pde5_type_SHIFT 24 2234 #define pde5_type_MASK 0x000000ff 2235 #define pde5_type_WORD word0 2236 #define pde5_rsvd0_SHIFT 0 2237 #define pde5_rsvd0_MASK 0x00ffffff 2238 #define pde5_rsvd0_WORD word0 2239 uint32_t reftag; /* Reference Tag Value */ 2240 uint32_t reftagtr; /* Reference Tag Translation Value */ 2241 }; 2242 2243 struct lpfc_pde6 { 2244 uint32_t word0; 2245 #define pde6_type_SHIFT 24 2246 #define pde6_type_MASK 0x000000ff 2247 #define pde6_type_WORD word0 2248 #define pde6_rsvd0_SHIFT 0 2249 #define pde6_rsvd0_MASK 0x00ffffff 2250 #define pde6_rsvd0_WORD word0 2251 uint32_t word1; 2252 #define pde6_rsvd1_SHIFT 26 2253 #define pde6_rsvd1_MASK 0x0000003f 2254 #define pde6_rsvd1_WORD word1 2255 #define pde6_na_SHIFT 25 2256 #define pde6_na_MASK 0x00000001 2257 #define pde6_na_WORD word1 2258 #define pde6_rsvd2_SHIFT 16 2259 #define pde6_rsvd2_MASK 0x000001FF 2260 #define pde6_rsvd2_WORD word1 2261 #define pde6_apptagtr_SHIFT 0 2262 #define pde6_apptagtr_MASK 0x0000ffff 2263 #define pde6_apptagtr_WORD word1 2264 uint32_t word2; 2265 #define pde6_optx_SHIFT 28 2266 #define pde6_optx_MASK 0x0000000f 2267 #define pde6_optx_WORD word2 2268 #define pde6_oprx_SHIFT 24 2269 #define pde6_oprx_MASK 0x0000000f 2270 #define pde6_oprx_WORD word2 2271 #define pde6_nr_SHIFT 23 2272 #define pde6_nr_MASK 0x00000001 2273 #define pde6_nr_WORD word2 2274 #define pde6_ce_SHIFT 22 2275 #define pde6_ce_MASK 0x00000001 2276 #define pde6_ce_WORD word2 2277 #define pde6_re_SHIFT 21 2278 #define pde6_re_MASK 0x00000001 2279 #define pde6_re_WORD word2 2280 #define pde6_ae_SHIFT 20 2281 #define pde6_ae_MASK 0x00000001 2282 #define pde6_ae_WORD word2 2283 #define pde6_ai_SHIFT 19 2284 #define pde6_ai_MASK 0x00000001 2285 #define pde6_ai_WORD word2 2286 #define pde6_bs_SHIFT 16 2287 #define pde6_bs_MASK 0x00000007 2288 #define pde6_bs_WORD word2 2289 #define pde6_apptagval_SHIFT 0 2290 #define pde6_apptagval_MASK 0x0000ffff 2291 #define pde6_apptagval_WORD word2 2292 }; 2293 2294 struct lpfc_pde7 { 2295 uint32_t word0; 2296 #define pde7_type_SHIFT 24 2297 #define pde7_type_MASK 0x000000ff 2298 #define pde7_type_WORD word0 2299 #define pde7_rsvd0_SHIFT 0 2300 #define pde7_rsvd0_MASK 0x00ffffff 2301 #define pde7_rsvd0_WORD word0 2302 uint32_t addrHigh; 2303 uint32_t addrLow; 2304 }; 2305 2306 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 2307 2308 typedef struct { 2309 #ifdef __BIG_ENDIAN_BITFIELD 2310 uint32_t rsvd2:25; 2311 uint32_t acknowledgment:1; 2312 uint32_t version:1; 2313 uint32_t erase_or_prog:1; 2314 uint32_t update_flash:1; 2315 uint32_t update_ram:1; 2316 uint32_t method:1; 2317 uint32_t load_cmplt:1; 2318 #else /* __LITTLE_ENDIAN_BITFIELD */ 2319 uint32_t load_cmplt:1; 2320 uint32_t method:1; 2321 uint32_t update_ram:1; 2322 uint32_t update_flash:1; 2323 uint32_t erase_or_prog:1; 2324 uint32_t version:1; 2325 uint32_t acknowledgment:1; 2326 uint32_t rsvd2:25; 2327 #endif 2328 2329 uint32_t dl_to_adr_low; 2330 uint32_t dl_to_adr_high; 2331 uint32_t dl_len; 2332 union { 2333 uint32_t dl_from_mbx_offset; 2334 struct ulp_bde dl_from_bde; 2335 struct ulp_bde64 dl_from_bde64; 2336 } un; 2337 2338 } LOAD_SM_VAR; 2339 2340 /* Structure for MB Command READ_NVPARM (02) */ 2341 2342 typedef struct { 2343 uint32_t rsvd1[3]; /* Read as all one's */ 2344 uint32_t rsvd2; /* Read as all zero's */ 2345 uint32_t portname[2]; /* N_PORT name */ 2346 uint32_t nodename[2]; /* NODE name */ 2347 2348 #ifdef __BIG_ENDIAN_BITFIELD 2349 uint32_t pref_DID:24; 2350 uint32_t hardAL_PA:8; 2351 #else /* __LITTLE_ENDIAN_BITFIELD */ 2352 uint32_t hardAL_PA:8; 2353 uint32_t pref_DID:24; 2354 #endif 2355 2356 uint32_t rsvd3[21]; /* Read as all one's */ 2357 } READ_NV_VAR; 2358 2359 /* Structure for MB Command WRITE_NVPARMS (03) */ 2360 2361 typedef struct { 2362 uint32_t rsvd1[3]; /* Must be all one's */ 2363 uint32_t rsvd2; /* Must be all zero's */ 2364 uint32_t portname[2]; /* N_PORT name */ 2365 uint32_t nodename[2]; /* NODE name */ 2366 2367 #ifdef __BIG_ENDIAN_BITFIELD 2368 uint32_t pref_DID:24; 2369 uint32_t hardAL_PA:8; 2370 #else /* __LITTLE_ENDIAN_BITFIELD */ 2371 uint32_t hardAL_PA:8; 2372 uint32_t pref_DID:24; 2373 #endif 2374 2375 uint32_t rsvd3[21]; /* Must be all one's */ 2376 } WRITE_NV_VAR; 2377 2378 /* Structure for MB Command RUN_BIU_DIAG (04) */ 2379 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 2380 2381 typedef struct { 2382 uint32_t rsvd1; 2383 union { 2384 struct { 2385 struct ulp_bde xmit_bde; 2386 struct ulp_bde rcv_bde; 2387 } s1; 2388 struct { 2389 struct ulp_bde64 xmit_bde64; 2390 struct ulp_bde64 rcv_bde64; 2391 } s2; 2392 } un; 2393 } BIU_DIAG_VAR; 2394 2395 /* Structure for MB command READ_EVENT_LOG (0x38) */ 2396 struct READ_EVENT_LOG_VAR { 2397 uint32_t word1; 2398 #define lpfc_event_log_SHIFT 29 2399 #define lpfc_event_log_MASK 0x00000001 2400 #define lpfc_event_log_WORD word1 2401 #define USE_MAILBOX_RESPONSE 1 2402 uint32_t offset; 2403 struct ulp_bde64 rcv_bde64; 2404 }; 2405 2406 /* Structure for MB Command INIT_LINK (05) */ 2407 2408 typedef struct { 2409 #ifdef __BIG_ENDIAN_BITFIELD 2410 uint32_t rsvd1:24; 2411 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2412 #else /* __LITTLE_ENDIAN_BITFIELD */ 2413 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2414 uint32_t rsvd1:24; 2415 #endif 2416 2417 #ifdef __BIG_ENDIAN_BITFIELD 2418 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2419 uint8_t rsvd2; 2420 uint16_t link_flags; 2421 #else /* __LITTLE_ENDIAN_BITFIELD */ 2422 uint16_t link_flags; 2423 uint8_t rsvd2; 2424 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2425 #endif 2426 2427 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 2428 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 2429 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 2430 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 2431 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 2432 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 2433 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 2434 2435 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 2436 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 2437 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 2438 2439 uint32_t link_speed; 2440 #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 2441 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 2442 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 2443 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 2444 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 2445 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 2446 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 2447 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ 2448 #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */ 2449 #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */ 2450 #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */ 2451 2452 } INIT_LINK_VAR; 2453 2454 /* Structure for MB Command DOWN_LINK (06) */ 2455 2456 typedef struct { 2457 uint32_t rsvd1; 2458 } DOWN_LINK_VAR; 2459 2460 /* Structure for MB Command CONFIG_LINK (07) */ 2461 2462 typedef struct { 2463 #ifdef __BIG_ENDIAN_BITFIELD 2464 uint32_t cr:1; 2465 uint32_t ci:1; 2466 uint32_t cr_delay:6; 2467 uint32_t cr_count:8; 2468 uint32_t rsvd1:8; 2469 uint32_t MaxBBC:8; 2470 #else /* __LITTLE_ENDIAN_BITFIELD */ 2471 uint32_t MaxBBC:8; 2472 uint32_t rsvd1:8; 2473 uint32_t cr_count:8; 2474 uint32_t cr_delay:6; 2475 uint32_t ci:1; 2476 uint32_t cr:1; 2477 #endif 2478 2479 uint32_t myId; 2480 uint32_t rsvd2; 2481 uint32_t edtov; 2482 uint32_t arbtov; 2483 uint32_t ratov; 2484 uint32_t rttov; 2485 uint32_t altov; 2486 uint32_t crtov; 2487 2488 #ifdef __BIG_ENDIAN_BITFIELD 2489 uint32_t rsvd4:19; 2490 uint32_t cscn:1; 2491 uint32_t bbscn:4; 2492 uint32_t rsvd3:8; 2493 #else /* __LITTLE_ENDIAN_BITFIELD */ 2494 uint32_t rsvd3:8; 2495 uint32_t bbscn:4; 2496 uint32_t cscn:1; 2497 uint32_t rsvd4:19; 2498 #endif 2499 2500 #ifdef __BIG_ENDIAN_BITFIELD 2501 uint32_t rrq_enable:1; 2502 uint32_t rrq_immed:1; 2503 uint32_t rsvd5:29; 2504 uint32_t ack0_enable:1; 2505 #else /* __LITTLE_ENDIAN_BITFIELD */ 2506 uint32_t ack0_enable:1; 2507 uint32_t rsvd5:29; 2508 uint32_t rrq_immed:1; 2509 uint32_t rrq_enable:1; 2510 #endif 2511 } CONFIG_LINK; 2512 2513 /* Structure for MB Command PART_SLIM (08) 2514 * will be removed since SLI1 is no longer supported! 2515 */ 2516 typedef struct { 2517 #ifdef __BIG_ENDIAN_BITFIELD 2518 uint16_t offCiocb; 2519 uint16_t numCiocb; 2520 uint16_t offRiocb; 2521 uint16_t numRiocb; 2522 #else /* __LITTLE_ENDIAN_BITFIELD */ 2523 uint16_t numCiocb; 2524 uint16_t offCiocb; 2525 uint16_t numRiocb; 2526 uint16_t offRiocb; 2527 #endif 2528 } RING_DEF; 2529 2530 typedef struct { 2531 #ifdef __BIG_ENDIAN_BITFIELD 2532 uint32_t unused1:24; 2533 uint32_t numRing:8; 2534 #else /* __LITTLE_ENDIAN_BITFIELD */ 2535 uint32_t numRing:8; 2536 uint32_t unused1:24; 2537 #endif 2538 2539 RING_DEF ringdef[4]; 2540 uint32_t hbainit; 2541 } PART_SLIM_VAR; 2542 2543 /* Structure for MB Command CONFIG_RING (09) */ 2544 2545 typedef struct { 2546 #ifdef __BIG_ENDIAN_BITFIELD 2547 uint32_t unused2:6; 2548 uint32_t recvSeq:1; 2549 uint32_t recvNotify:1; 2550 uint32_t numMask:8; 2551 uint32_t profile:8; 2552 uint32_t unused1:4; 2553 uint32_t ring:4; 2554 #else /* __LITTLE_ENDIAN_BITFIELD */ 2555 uint32_t ring:4; 2556 uint32_t unused1:4; 2557 uint32_t profile:8; 2558 uint32_t numMask:8; 2559 uint32_t recvNotify:1; 2560 uint32_t recvSeq:1; 2561 uint32_t unused2:6; 2562 #endif 2563 2564 #ifdef __BIG_ENDIAN_BITFIELD 2565 uint16_t maxRespXchg; 2566 uint16_t maxOrigXchg; 2567 #else /* __LITTLE_ENDIAN_BITFIELD */ 2568 uint16_t maxOrigXchg; 2569 uint16_t maxRespXchg; 2570 #endif 2571 2572 RR_REG rrRegs[6]; 2573 } CONFIG_RING_VAR; 2574 2575 /* Structure for MB Command RESET_RING (10) */ 2576 2577 typedef struct { 2578 uint32_t ring_no; 2579 } RESET_RING_VAR; 2580 2581 /* Structure for MB Command READ_CONFIG (11) */ 2582 2583 typedef struct { 2584 #ifdef __BIG_ENDIAN_BITFIELD 2585 uint32_t cr:1; 2586 uint32_t ci:1; 2587 uint32_t cr_delay:6; 2588 uint32_t cr_count:8; 2589 uint32_t InitBBC:8; 2590 uint32_t MaxBBC:8; 2591 #else /* __LITTLE_ENDIAN_BITFIELD */ 2592 uint32_t MaxBBC:8; 2593 uint32_t InitBBC:8; 2594 uint32_t cr_count:8; 2595 uint32_t cr_delay:6; 2596 uint32_t ci:1; 2597 uint32_t cr:1; 2598 #endif 2599 2600 #ifdef __BIG_ENDIAN_BITFIELD 2601 uint32_t topology:8; 2602 uint32_t myDid:24; 2603 #else /* __LITTLE_ENDIAN_BITFIELD */ 2604 uint32_t myDid:24; 2605 uint32_t topology:8; 2606 #endif 2607 2608 /* Defines for topology (defined previously) */ 2609 #ifdef __BIG_ENDIAN_BITFIELD 2610 uint32_t AR:1; 2611 uint32_t IR:1; 2612 uint32_t rsvd1:29; 2613 uint32_t ack0:1; 2614 #else /* __LITTLE_ENDIAN_BITFIELD */ 2615 uint32_t ack0:1; 2616 uint32_t rsvd1:29; 2617 uint32_t IR:1; 2618 uint32_t AR:1; 2619 #endif 2620 2621 uint32_t edtov; 2622 uint32_t arbtov; 2623 uint32_t ratov; 2624 uint32_t rttov; 2625 uint32_t altov; 2626 uint32_t lmt; 2627 #define LMT_RESERVED 0x000 /* Not used */ 2628 #define LMT_1Gb 0x004 2629 #define LMT_2Gb 0x008 2630 #define LMT_4Gb 0x040 2631 #define LMT_8Gb 0x080 2632 #define LMT_10Gb 0x100 2633 #define LMT_16Gb 0x200 2634 #define LMT_32Gb 0x400 2635 #define LMT_64Gb 0x800 2636 #define LMT_128Gb 0x1000 2637 #define LMT_256Gb 0x2000 2638 uint32_t rsvd2; 2639 uint32_t rsvd3; 2640 uint32_t max_xri; 2641 uint32_t max_iocb; 2642 uint32_t max_rpi; 2643 uint32_t avail_xri; 2644 uint32_t avail_iocb; 2645 uint32_t avail_rpi; 2646 uint32_t max_vpi; 2647 uint32_t rsvd4; 2648 uint32_t rsvd5; 2649 uint32_t avail_vpi; 2650 } READ_CONFIG_VAR; 2651 2652 /* Structure for MB Command READ_RCONFIG (12) */ 2653 2654 typedef struct { 2655 #ifdef __BIG_ENDIAN_BITFIELD 2656 uint32_t rsvd2:7; 2657 uint32_t recvNotify:1; 2658 uint32_t numMask:8; 2659 uint32_t profile:8; 2660 uint32_t rsvd1:4; 2661 uint32_t ring:4; 2662 #else /* __LITTLE_ENDIAN_BITFIELD */ 2663 uint32_t ring:4; 2664 uint32_t rsvd1:4; 2665 uint32_t profile:8; 2666 uint32_t numMask:8; 2667 uint32_t recvNotify:1; 2668 uint32_t rsvd2:7; 2669 #endif 2670 2671 #ifdef __BIG_ENDIAN_BITFIELD 2672 uint16_t maxResp; 2673 uint16_t maxOrig; 2674 #else /* __LITTLE_ENDIAN_BITFIELD */ 2675 uint16_t maxOrig; 2676 uint16_t maxResp; 2677 #endif 2678 2679 RR_REG rrRegs[6]; 2680 2681 #ifdef __BIG_ENDIAN_BITFIELD 2682 uint16_t cmdRingOffset; 2683 uint16_t cmdEntryCnt; 2684 uint16_t rspRingOffset; 2685 uint16_t rspEntryCnt; 2686 uint16_t nextCmdOffset; 2687 uint16_t rsvd3; 2688 uint16_t nextRspOffset; 2689 uint16_t rsvd4; 2690 #else /* __LITTLE_ENDIAN_BITFIELD */ 2691 uint16_t cmdEntryCnt; 2692 uint16_t cmdRingOffset; 2693 uint16_t rspEntryCnt; 2694 uint16_t rspRingOffset; 2695 uint16_t rsvd3; 2696 uint16_t nextCmdOffset; 2697 uint16_t rsvd4; 2698 uint16_t nextRspOffset; 2699 #endif 2700 } READ_RCONF_VAR; 2701 2702 /* Structure for MB Command READ_SPARM (13) */ 2703 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2704 2705 typedef struct { 2706 uint32_t rsvd1; 2707 uint32_t rsvd2; 2708 union { 2709 struct ulp_bde sp; /* This BDE points to struct serv_parm 2710 structure */ 2711 struct ulp_bde64 sp64; 2712 } un; 2713 #ifdef __BIG_ENDIAN_BITFIELD 2714 uint16_t rsvd3; 2715 uint16_t vpi; 2716 #else /* __LITTLE_ENDIAN_BITFIELD */ 2717 uint16_t vpi; 2718 uint16_t rsvd3; 2719 #endif 2720 } READ_SPARM_VAR; 2721 2722 /* Structure for MB Command READ_STATUS (14) */ 2723 enum read_status_word1 { 2724 RD_ST_CC = 0x01, 2725 RD_ST_XKB = 0x80, 2726 }; 2727 2728 enum read_status_word17 { 2729 RD_ST_XMIT_XKB_MASK = 0x3fffff, 2730 }; 2731 2732 enum read_status_word18 { 2733 RD_ST_RCV_XKB_MASK = 0x3fffff, 2734 }; 2735 2736 typedef struct { 2737 u8 clear_counters; /* rsvd 7:1, cc 0 */ 2738 u8 rsvd5; 2739 u8 rsvd6; 2740 u8 xkb; /* xkb 7, rsvd 6:0 */ 2741 2742 u32 rsvd8; 2743 2744 uint32_t xmitByteCnt; 2745 uint32_t rcvByteCnt; 2746 uint32_t xmitFrameCnt; 2747 uint32_t rcvFrameCnt; 2748 uint32_t xmitSeqCnt; 2749 uint32_t rcvSeqCnt; 2750 uint32_t totalOrigExchanges; 2751 uint32_t totalRespExchanges; 2752 uint32_t rcvPbsyCnt; 2753 uint32_t rcvFbsyCnt; 2754 2755 u32 drop_frame_no_rq; 2756 u32 empty_rq; 2757 u32 drop_frame_no_xri; 2758 u32 empty_xri; 2759 2760 u32 xmit_xkb; /* rsvd 31:22, xmit_xkb 21:0 */ 2761 u32 rcv_xkb; /* rsvd 31:22, rcv_xkb 21:0 */ 2762 } READ_STATUS_VAR; 2763 2764 /* Structure for MB Command READ_RPI (15) */ 2765 /* Structure for MB Command READ_RPI64 (0x8F) */ 2766 2767 typedef struct { 2768 #ifdef __BIG_ENDIAN_BITFIELD 2769 uint16_t nextRpi; 2770 uint16_t reqRpi; 2771 uint32_t rsvd2:8; 2772 uint32_t DID:24; 2773 #else /* __LITTLE_ENDIAN_BITFIELD */ 2774 uint16_t reqRpi; 2775 uint16_t nextRpi; 2776 uint32_t DID:24; 2777 uint32_t rsvd2:8; 2778 #endif 2779 2780 union { 2781 struct ulp_bde sp; 2782 struct ulp_bde64 sp64; 2783 } un; 2784 2785 } READ_RPI_VAR; 2786 2787 /* Structure for MB Command READ_XRI (16) */ 2788 2789 typedef struct { 2790 #ifdef __BIG_ENDIAN_BITFIELD 2791 uint16_t nextXri; 2792 uint16_t reqXri; 2793 uint16_t rsvd1; 2794 uint16_t rpi; 2795 uint32_t rsvd2:8; 2796 uint32_t DID:24; 2797 uint32_t rsvd3:8; 2798 uint32_t SID:24; 2799 uint32_t rsvd4; 2800 uint8_t seqId; 2801 uint8_t rsvd5; 2802 uint16_t seqCount; 2803 uint16_t oxId; 2804 uint16_t rxId; 2805 uint32_t rsvd6:30; 2806 uint32_t si:1; 2807 uint32_t exchOrig:1; 2808 #else /* __LITTLE_ENDIAN_BITFIELD */ 2809 uint16_t reqXri; 2810 uint16_t nextXri; 2811 uint16_t rpi; 2812 uint16_t rsvd1; 2813 uint32_t DID:24; 2814 uint32_t rsvd2:8; 2815 uint32_t SID:24; 2816 uint32_t rsvd3:8; 2817 uint32_t rsvd4; 2818 uint16_t seqCount; 2819 uint8_t rsvd5; 2820 uint8_t seqId; 2821 uint16_t rxId; 2822 uint16_t oxId; 2823 uint32_t exchOrig:1; 2824 uint32_t si:1; 2825 uint32_t rsvd6:30; 2826 #endif 2827 } READ_XRI_VAR; 2828 2829 /* Structure for MB Command READ_REV (17) */ 2830 2831 typedef struct { 2832 #ifdef __BIG_ENDIAN_BITFIELD 2833 uint32_t cv:1; 2834 uint32_t rr:1; 2835 uint32_t rsvd2:2; 2836 uint32_t v3req:1; 2837 uint32_t v3rsp:1; 2838 uint32_t rsvd1:25; 2839 uint32_t rv:1; 2840 #else /* __LITTLE_ENDIAN_BITFIELD */ 2841 uint32_t rv:1; 2842 uint32_t rsvd1:25; 2843 uint32_t v3rsp:1; 2844 uint32_t v3req:1; 2845 uint32_t rsvd2:2; 2846 uint32_t rr:1; 2847 uint32_t cv:1; 2848 #endif 2849 2850 uint32_t biuRev; 2851 uint32_t smRev; 2852 union { 2853 uint32_t smFwRev; 2854 struct { 2855 #ifdef __BIG_ENDIAN_BITFIELD 2856 uint8_t ProgType; 2857 uint8_t ProgId; 2858 uint16_t ProgVer:4; 2859 uint16_t ProgRev:4; 2860 uint16_t ProgFixLvl:2; 2861 uint16_t ProgDistType:2; 2862 uint16_t DistCnt:4; 2863 #else /* __LITTLE_ENDIAN_BITFIELD */ 2864 uint16_t DistCnt:4; 2865 uint16_t ProgDistType:2; 2866 uint16_t ProgFixLvl:2; 2867 uint16_t ProgRev:4; 2868 uint16_t ProgVer:4; 2869 uint8_t ProgId; 2870 uint8_t ProgType; 2871 #endif 2872 2873 } b; 2874 } un; 2875 uint32_t endecRev; 2876 #ifdef __BIG_ENDIAN_BITFIELD 2877 uint8_t feaLevelHigh; 2878 uint8_t feaLevelLow; 2879 uint8_t fcphHigh; 2880 uint8_t fcphLow; 2881 #else /* __LITTLE_ENDIAN_BITFIELD */ 2882 uint8_t fcphLow; 2883 uint8_t fcphHigh; 2884 uint8_t feaLevelLow; 2885 uint8_t feaLevelHigh; 2886 #endif 2887 2888 uint32_t postKernRev; 2889 uint32_t opFwRev; 2890 uint8_t opFwName[16]; 2891 uint32_t sli1FwRev; 2892 uint8_t sli1FwName[16]; 2893 uint32_t sli2FwRev; 2894 uint8_t sli2FwName[16]; 2895 uint32_t sli3Feat; 2896 uint32_t RandomData[6]; 2897 } READ_REV_VAR; 2898 2899 /* Structure for MB Command READ_LINK_STAT (18) */ 2900 2901 typedef struct { 2902 uint32_t word0; 2903 2904 #define lpfc_read_link_stat_rec_SHIFT 0 2905 #define lpfc_read_link_stat_rec_MASK 0x1 2906 #define lpfc_read_link_stat_rec_WORD word0 2907 2908 #define lpfc_read_link_stat_gec_SHIFT 1 2909 #define lpfc_read_link_stat_gec_MASK 0x1 2910 #define lpfc_read_link_stat_gec_WORD word0 2911 2912 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2 2913 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF 2914 #define lpfc_read_link_stat_w02oftow23of_WORD word0 2915 2916 #define lpfc_read_link_stat_rsvd_SHIFT 24 2917 #define lpfc_read_link_stat_rsvd_MASK 0x1F 2918 #define lpfc_read_link_stat_rsvd_WORD word0 2919 2920 #define lpfc_read_link_stat_gec2_SHIFT 29 2921 #define lpfc_read_link_stat_gec2_MASK 0x1 2922 #define lpfc_read_link_stat_gec2_WORD word0 2923 2924 #define lpfc_read_link_stat_clrc_SHIFT 30 2925 #define lpfc_read_link_stat_clrc_MASK 0x1 2926 #define lpfc_read_link_stat_clrc_WORD word0 2927 2928 #define lpfc_read_link_stat_clof_SHIFT 31 2929 #define lpfc_read_link_stat_clof_MASK 0x1 2930 #define lpfc_read_link_stat_clof_WORD word0 2931 2932 uint32_t linkFailureCnt; 2933 uint32_t lossSyncCnt; 2934 uint32_t lossSignalCnt; 2935 uint32_t primSeqErrCnt; 2936 uint32_t invalidXmitWord; 2937 uint32_t crcCnt; 2938 uint32_t primSeqTimeout; 2939 uint32_t elasticOverrun; 2940 uint32_t arbTimeout; 2941 uint32_t advRecBufCredit; 2942 uint32_t curRecBufCredit; 2943 uint32_t advTransBufCredit; 2944 uint32_t curTransBufCredit; 2945 uint32_t recEofCount; 2946 uint32_t recEofdtiCount; 2947 uint32_t recEofniCount; 2948 uint32_t recSofcount; 2949 uint32_t rsvd1; 2950 uint32_t rsvd2; 2951 uint32_t recDrpXriCount; 2952 uint32_t fecCorrBlkCount; 2953 uint32_t fecUncorrBlkCount; 2954 } READ_LNK_VAR; 2955 2956 /* Structure for MB Command REG_LOGIN (19) */ 2957 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2958 2959 typedef struct { 2960 #ifdef __BIG_ENDIAN_BITFIELD 2961 uint16_t rsvd1; 2962 uint16_t rpi; 2963 uint32_t rsvd2:8; 2964 uint32_t did:24; 2965 #else /* __LITTLE_ENDIAN_BITFIELD */ 2966 uint16_t rpi; 2967 uint16_t rsvd1; 2968 uint32_t did:24; 2969 uint32_t rsvd2:8; 2970 #endif 2971 2972 union { 2973 struct ulp_bde sp; 2974 struct ulp_bde64 sp64; 2975 } un; 2976 2977 #ifdef __BIG_ENDIAN_BITFIELD 2978 uint16_t rsvd6; 2979 uint16_t vpi; 2980 #else /* __LITTLE_ENDIAN_BITFIELD */ 2981 uint16_t vpi; 2982 uint16_t rsvd6; 2983 #endif 2984 2985 } REG_LOGIN_VAR; 2986 2987 /* Word 30 contents for REG_LOGIN */ 2988 typedef union { 2989 struct { 2990 #ifdef __BIG_ENDIAN_BITFIELD 2991 uint16_t rsvd1:12; 2992 uint16_t wd30_class:4; 2993 uint16_t xri; 2994 #else /* __LITTLE_ENDIAN_BITFIELD */ 2995 uint16_t xri; 2996 uint16_t wd30_class:4; 2997 uint16_t rsvd1:12; 2998 #endif 2999 } f; 3000 uint32_t word; 3001 } REG_WD30; 3002 3003 /* Structure for MB Command UNREG_LOGIN (20) */ 3004 3005 typedef struct { 3006 #ifdef __BIG_ENDIAN_BITFIELD 3007 uint16_t rsvd1; 3008 uint16_t rpi; 3009 uint32_t rsvd2; 3010 uint32_t rsvd3; 3011 uint32_t rsvd4; 3012 uint32_t rsvd5; 3013 uint16_t rsvd6; 3014 uint16_t vpi; 3015 #else /* __LITTLE_ENDIAN_BITFIELD */ 3016 uint16_t rpi; 3017 uint16_t rsvd1; 3018 uint32_t rsvd2; 3019 uint32_t rsvd3; 3020 uint32_t rsvd4; 3021 uint32_t rsvd5; 3022 uint16_t vpi; 3023 uint16_t rsvd6; 3024 #endif 3025 } UNREG_LOGIN_VAR; 3026 3027 /* Structure for MB Command REG_VPI (0x96) */ 3028 typedef struct { 3029 #ifdef __BIG_ENDIAN_BITFIELD 3030 uint32_t rsvd1; 3031 uint32_t rsvd2:7; 3032 uint32_t upd:1; 3033 uint32_t sid:24; 3034 uint32_t wwn[2]; 3035 uint32_t rsvd5; 3036 uint16_t vfi; 3037 uint16_t vpi; 3038 #else /* __LITTLE_ENDIAN */ 3039 uint32_t rsvd1; 3040 uint32_t sid:24; 3041 uint32_t upd:1; 3042 uint32_t rsvd2:7; 3043 uint32_t wwn[2]; 3044 uint32_t rsvd5; 3045 uint16_t vpi; 3046 uint16_t vfi; 3047 #endif 3048 } REG_VPI_VAR; 3049 3050 /* Structure for MB Command UNREG_VPI (0x97) */ 3051 typedef struct { 3052 uint32_t rsvd1; 3053 #ifdef __BIG_ENDIAN_BITFIELD 3054 uint16_t rsvd2; 3055 uint16_t sli4_vpi; 3056 #else /* __LITTLE_ENDIAN */ 3057 uint16_t sli4_vpi; 3058 uint16_t rsvd2; 3059 #endif 3060 uint32_t rsvd3; 3061 uint32_t rsvd4; 3062 uint32_t rsvd5; 3063 #ifdef __BIG_ENDIAN_BITFIELD 3064 uint16_t rsvd6; 3065 uint16_t vpi; 3066 #else /* __LITTLE_ENDIAN */ 3067 uint16_t vpi; 3068 uint16_t rsvd6; 3069 #endif 3070 } UNREG_VPI_VAR; 3071 3072 /* Structure for MB Command UNREG_D_ID (0x23) */ 3073 3074 typedef struct { 3075 uint32_t did; 3076 uint32_t rsvd2; 3077 uint32_t rsvd3; 3078 uint32_t rsvd4; 3079 uint32_t rsvd5; 3080 #ifdef __BIG_ENDIAN_BITFIELD 3081 uint16_t rsvd6; 3082 uint16_t vpi; 3083 #else 3084 uint16_t vpi; 3085 uint16_t rsvd6; 3086 #endif 3087 } UNREG_D_ID_VAR; 3088 3089 /* Structure for MB Command READ_TOPOLOGY (0x95) */ 3090 struct lpfc_mbx_read_top { 3091 uint32_t eventTag; /* Event tag */ 3092 uint32_t word2; 3093 #define lpfc_mbx_read_top_fa_SHIFT 12 3094 #define lpfc_mbx_read_top_fa_MASK 0x00000001 3095 #define lpfc_mbx_read_top_fa_WORD word2 3096 #define lpfc_mbx_read_top_mm_SHIFT 11 3097 #define lpfc_mbx_read_top_mm_MASK 0x00000001 3098 #define lpfc_mbx_read_top_mm_WORD word2 3099 #define lpfc_mbx_read_top_pb_SHIFT 9 3100 #define lpfc_mbx_read_top_pb_MASK 0X00000001 3101 #define lpfc_mbx_read_top_pb_WORD word2 3102 #define lpfc_mbx_read_top_il_SHIFT 8 3103 #define lpfc_mbx_read_top_il_MASK 0x00000001 3104 #define lpfc_mbx_read_top_il_WORD word2 3105 #define lpfc_mbx_read_top_att_type_SHIFT 0 3106 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 3107 #define lpfc_mbx_read_top_att_type_WORD word2 3108 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 3109 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 3110 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 3111 #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */ 3112 uint32_t word3; 3113 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 3114 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 3115 #define lpfc_mbx_read_top_alpa_granted_WORD word3 3116 #define lpfc_mbx_read_top_lip_alps_SHIFT 16 3117 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 3118 #define lpfc_mbx_read_top_lip_alps_WORD word3 3119 #define lpfc_mbx_read_top_lip_type_SHIFT 8 3120 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 3121 #define lpfc_mbx_read_top_lip_type_WORD word3 3122 #define lpfc_mbx_read_top_topology_SHIFT 0 3123 #define lpfc_mbx_read_top_topology_MASK 0x000000FF 3124 #define lpfc_mbx_read_top_topology_WORD word3 3125 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 3126 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 3127 /* store the LILP AL_PA position map into */ 3128 struct ulp_bde64 lilpBde64; 3129 #define LPFC_ALPA_MAP_SIZE 128 3130 uint32_t word7; 3131 #define lpfc_mbx_read_top_ld_lu_SHIFT 31 3132 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 3133 #define lpfc_mbx_read_top_ld_lu_WORD word7 3134 #define lpfc_mbx_read_top_ld_tf_SHIFT 30 3135 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 3136 #define lpfc_mbx_read_top_ld_tf_WORD word7 3137 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 3138 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 3139 #define lpfc_mbx_read_top_ld_link_spd_WORD word7 3140 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 3141 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 3142 #define lpfc_mbx_read_top_ld_nl_port_WORD word7 3143 #define lpfc_mbx_read_top_ld_tx_SHIFT 2 3144 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 3145 #define lpfc_mbx_read_top_ld_tx_WORD word7 3146 #define lpfc_mbx_read_top_ld_rx_SHIFT 0 3147 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 3148 #define lpfc_mbx_read_top_ld_rx_WORD word7 3149 uint32_t word8; 3150 #define lpfc_mbx_read_top_lu_SHIFT 31 3151 #define lpfc_mbx_read_top_lu_MASK 0x00000001 3152 #define lpfc_mbx_read_top_lu_WORD word8 3153 #define lpfc_mbx_read_top_tf_SHIFT 30 3154 #define lpfc_mbx_read_top_tf_MASK 0x00000001 3155 #define lpfc_mbx_read_top_tf_WORD word8 3156 #define lpfc_mbx_read_top_link_spd_SHIFT 8 3157 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 3158 #define lpfc_mbx_read_top_link_spd_WORD word8 3159 #define lpfc_mbx_read_top_nl_port_SHIFT 4 3160 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 3161 #define lpfc_mbx_read_top_nl_port_WORD word8 3162 #define lpfc_mbx_read_top_tx_SHIFT 2 3163 #define lpfc_mbx_read_top_tx_MASK 0x00000003 3164 #define lpfc_mbx_read_top_tx_WORD word8 3165 #define lpfc_mbx_read_top_rx_SHIFT 0 3166 #define lpfc_mbx_read_top_rx_MASK 0x00000003 3167 #define lpfc_mbx_read_top_rx_WORD word8 3168 #define LPFC_LINK_SPEED_UNKNOWN 0x0 3169 #define LPFC_LINK_SPEED_1GHZ 0x04 3170 #define LPFC_LINK_SPEED_2GHZ 0x08 3171 #define LPFC_LINK_SPEED_4GHZ 0x10 3172 #define LPFC_LINK_SPEED_8GHZ 0x20 3173 #define LPFC_LINK_SPEED_10GHZ 0x40 3174 #define LPFC_LINK_SPEED_16GHZ 0x80 3175 #define LPFC_LINK_SPEED_32GHZ 0x90 3176 #define LPFC_LINK_SPEED_64GHZ 0xA0 3177 #define LPFC_LINK_SPEED_128GHZ 0xB0 3178 #define LPFC_LINK_SPEED_256GHZ 0xC0 3179 }; 3180 3181 /* Structure for MB Command CLEAR_LA (22) */ 3182 3183 typedef struct { 3184 uint32_t eventTag; /* Event tag */ 3185 uint32_t rsvd1; 3186 } CLEAR_LA_VAR; 3187 3188 /* Structure for MB Command DUMP */ 3189 3190 typedef struct { 3191 #ifdef __BIG_ENDIAN_BITFIELD 3192 uint32_t rsvd:25; 3193 uint32_t ra:1; 3194 uint32_t co:1; 3195 uint32_t cv:1; 3196 uint32_t type:4; 3197 uint32_t entry_index:16; 3198 uint32_t region_id:16; 3199 #else /* __LITTLE_ENDIAN_BITFIELD */ 3200 uint32_t type:4; 3201 uint32_t cv:1; 3202 uint32_t co:1; 3203 uint32_t ra:1; 3204 uint32_t rsvd:25; 3205 uint32_t region_id:16; 3206 uint32_t entry_index:16; 3207 #endif 3208 3209 uint32_t sli4_length; 3210 uint32_t word_cnt; 3211 uint32_t resp_offset; 3212 } DUMP_VAR; 3213 3214 #define DMP_MEM_REG 0x1 3215 #define DMP_NV_PARAMS 0x2 3216 #define DMP_LMSD 0x3 /* Link Module Serial Data */ 3217 #define DMP_WELL_KNOWN 0x4 3218 3219 #define DMP_REGION_VPD 0xe 3220 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 3221 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 3222 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 3223 3224 #define DMP_REGION_VPORT 0x16 /* VPort info region */ 3225 #define DMP_VPORT_REGION_SIZE 0x200 3226 #define DMP_MBOX_OFFSET_WORD 0x5 3227 3228 #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 3229 #define DMP_RGN23_SIZE 0x400 3230 3231 #define WAKE_UP_PARMS_REGION_ID 4 3232 #define WAKE_UP_PARMS_WORD_SIZE 15 3233 3234 struct vport_rec { 3235 uint8_t wwpn[8]; 3236 uint8_t wwnn[8]; 3237 }; 3238 3239 #define VPORT_INFO_SIG 0x32324752 3240 #define VPORT_INFO_REV_MASK 0xff 3241 #define VPORT_INFO_REV 0x1 3242 #define MAX_STATIC_VPORT_COUNT 16 3243 struct static_vport_info { 3244 uint32_t signature; 3245 uint32_t rev; 3246 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 3247 uint32_t resvd[66]; 3248 }; 3249 3250 /* Option rom version structure */ 3251 struct prog_id { 3252 #ifdef __BIG_ENDIAN_BITFIELD 3253 uint8_t type; 3254 uint8_t id; 3255 uint32_t ver:4; /* Major Version */ 3256 uint32_t rev:4; /* Revision */ 3257 uint32_t lev:2; /* Level */ 3258 uint32_t dist:2; /* Dist Type */ 3259 uint32_t num:4; /* number after dist type */ 3260 #else /* __LITTLE_ENDIAN_BITFIELD */ 3261 uint32_t num:4; /* number after dist type */ 3262 uint32_t dist:2; /* Dist Type */ 3263 uint32_t lev:2; /* Level */ 3264 uint32_t rev:4; /* Revision */ 3265 uint32_t ver:4; /* Major Version */ 3266 uint8_t id; 3267 uint8_t type; 3268 #endif 3269 }; 3270 3271 /* Structure for MB Command UPDATE_CFG (0x1B) */ 3272 3273 struct update_cfg_var { 3274 #ifdef __BIG_ENDIAN_BITFIELD 3275 uint32_t rsvd2:16; 3276 uint32_t type:8; 3277 uint32_t rsvd:1; 3278 uint32_t ra:1; 3279 uint32_t co:1; 3280 uint32_t cv:1; 3281 uint32_t req:4; 3282 uint32_t entry_length:16; 3283 uint32_t region_id:16; 3284 #else /* __LITTLE_ENDIAN_BITFIELD */ 3285 uint32_t req:4; 3286 uint32_t cv:1; 3287 uint32_t co:1; 3288 uint32_t ra:1; 3289 uint32_t rsvd:1; 3290 uint32_t type:8; 3291 uint32_t rsvd2:16; 3292 uint32_t region_id:16; 3293 uint32_t entry_length:16; 3294 #endif 3295 3296 uint32_t resp_info; 3297 uint32_t byte_cnt; 3298 uint32_t data_offset; 3299 }; 3300 3301 struct hbq_mask { 3302 #ifdef __BIG_ENDIAN_BITFIELD 3303 uint8_t tmatch; 3304 uint8_t tmask; 3305 uint8_t rctlmatch; 3306 uint8_t rctlmask; 3307 #else /* __LITTLE_ENDIAN */ 3308 uint8_t rctlmask; 3309 uint8_t rctlmatch; 3310 uint8_t tmask; 3311 uint8_t tmatch; 3312 #endif 3313 }; 3314 3315 3316 /* Structure for MB Command CONFIG_HBQ (7c) */ 3317 3318 struct config_hbq_var { 3319 #ifdef __BIG_ENDIAN_BITFIELD 3320 uint32_t rsvd1 :7; 3321 uint32_t recvNotify :1; /* Receive Notification */ 3322 uint32_t numMask :8; /* # Mask Entries */ 3323 uint32_t profile :8; /* Selection Profile */ 3324 uint32_t rsvd2 :8; 3325 #else /* __LITTLE_ENDIAN */ 3326 uint32_t rsvd2 :8; 3327 uint32_t profile :8; /* Selection Profile */ 3328 uint32_t numMask :8; /* # Mask Entries */ 3329 uint32_t recvNotify :1; /* Receive Notification */ 3330 uint32_t rsvd1 :7; 3331 #endif 3332 3333 #ifdef __BIG_ENDIAN_BITFIELD 3334 uint32_t hbqId :16; 3335 uint32_t rsvd3 :12; 3336 uint32_t ringMask :4; 3337 #else /* __LITTLE_ENDIAN */ 3338 uint32_t ringMask :4; 3339 uint32_t rsvd3 :12; 3340 uint32_t hbqId :16; 3341 #endif 3342 3343 #ifdef __BIG_ENDIAN_BITFIELD 3344 uint32_t entry_count :16; 3345 uint32_t rsvd4 :8; 3346 uint32_t headerLen :8; 3347 #else /* __LITTLE_ENDIAN */ 3348 uint32_t headerLen :8; 3349 uint32_t rsvd4 :8; 3350 uint32_t entry_count :16; 3351 #endif 3352 3353 uint32_t hbqaddrLow; 3354 uint32_t hbqaddrHigh; 3355 3356 #ifdef __BIG_ENDIAN_BITFIELD 3357 uint32_t rsvd5 :31; 3358 uint32_t logEntry :1; 3359 #else /* __LITTLE_ENDIAN */ 3360 uint32_t logEntry :1; 3361 uint32_t rsvd5 :31; 3362 #endif 3363 3364 uint32_t rsvd6; /* w7 */ 3365 uint32_t rsvd7; /* w8 */ 3366 uint32_t rsvd8; /* w9 */ 3367 3368 struct hbq_mask hbqMasks[6]; 3369 3370 3371 union { 3372 uint32_t allprofiles[12]; 3373 3374 struct { 3375 #ifdef __BIG_ENDIAN_BITFIELD 3376 uint32_t seqlenoff :16; 3377 uint32_t maxlen :16; 3378 #else /* __LITTLE_ENDIAN */ 3379 uint32_t maxlen :16; 3380 uint32_t seqlenoff :16; 3381 #endif 3382 #ifdef __BIG_ENDIAN_BITFIELD 3383 uint32_t rsvd1 :28; 3384 uint32_t seqlenbcnt :4; 3385 #else /* __LITTLE_ENDIAN */ 3386 uint32_t seqlenbcnt :4; 3387 uint32_t rsvd1 :28; 3388 #endif 3389 uint32_t rsvd[10]; 3390 } profile2; 3391 3392 struct { 3393 #ifdef __BIG_ENDIAN_BITFIELD 3394 uint32_t seqlenoff :16; 3395 uint32_t maxlen :16; 3396 #else /* __LITTLE_ENDIAN */ 3397 uint32_t maxlen :16; 3398 uint32_t seqlenoff :16; 3399 #endif 3400 #ifdef __BIG_ENDIAN_BITFIELD 3401 uint32_t cmdcodeoff :28; 3402 uint32_t rsvd1 :12; 3403 uint32_t seqlenbcnt :4; 3404 #else /* __LITTLE_ENDIAN */ 3405 uint32_t seqlenbcnt :4; 3406 uint32_t rsvd1 :12; 3407 uint32_t cmdcodeoff :28; 3408 #endif 3409 uint32_t cmdmatch[8]; 3410 3411 uint32_t rsvd[2]; 3412 } profile3; 3413 3414 struct { 3415 #ifdef __BIG_ENDIAN_BITFIELD 3416 uint32_t seqlenoff :16; 3417 uint32_t maxlen :16; 3418 #else /* __LITTLE_ENDIAN */ 3419 uint32_t maxlen :16; 3420 uint32_t seqlenoff :16; 3421 #endif 3422 #ifdef __BIG_ENDIAN_BITFIELD 3423 uint32_t cmdcodeoff :28; 3424 uint32_t rsvd1 :12; 3425 uint32_t seqlenbcnt :4; 3426 #else /* __LITTLE_ENDIAN */ 3427 uint32_t seqlenbcnt :4; 3428 uint32_t rsvd1 :12; 3429 uint32_t cmdcodeoff :28; 3430 #endif 3431 uint32_t cmdmatch[8]; 3432 3433 uint32_t rsvd[2]; 3434 } profile5; 3435 3436 } profiles; 3437 3438 }; 3439 3440 3441 3442 /* Structure for MB Command CONFIG_PORT (0x88) */ 3443 typedef struct { 3444 #ifdef __BIG_ENDIAN_BITFIELD 3445 uint32_t cBE : 1; 3446 uint32_t cET : 1; 3447 uint32_t cHpcb : 1; 3448 uint32_t cMA : 1; 3449 uint32_t sli_mode : 4; 3450 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3451 * config block */ 3452 #else /* __LITTLE_ENDIAN */ 3453 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3454 * config block */ 3455 uint32_t sli_mode : 4; 3456 uint32_t cMA : 1; 3457 uint32_t cHpcb : 1; 3458 uint32_t cET : 1; 3459 uint32_t cBE : 1; 3460 #endif 3461 3462 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 3463 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 3464 uint32_t hbainit[5]; 3465 #ifdef __BIG_ENDIAN_BITFIELD 3466 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3467 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3468 #else /* __LITTLE_ENDIAN */ 3469 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3470 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3471 #endif 3472 3473 #ifdef __BIG_ENDIAN_BITFIELD 3474 uint32_t rsvd1 : 20; /* Reserved */ 3475 uint32_t casabt : 1; /* Configure async abts status notice */ 3476 uint32_t rsvd2 : 2; /* Reserved */ 3477 uint32_t cbg : 1; /* Configure BlockGuard */ 3478 uint32_t cmv : 1; /* Configure Max VPIs */ 3479 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3480 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3481 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3482 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3483 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3484 uint32_t cmx : 1; /* Configure Max XRIs */ 3485 uint32_t cmr : 1; /* Configure Max RPIs */ 3486 #else /* __LITTLE_ENDIAN */ 3487 uint32_t cmr : 1; /* Configure Max RPIs */ 3488 uint32_t cmx : 1; /* Configure Max XRIs */ 3489 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3490 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3491 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3492 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3493 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3494 uint32_t cmv : 1; /* Configure Max VPIs */ 3495 uint32_t cbg : 1; /* Configure BlockGuard */ 3496 uint32_t rsvd2 : 2; /* Reserved */ 3497 uint32_t casabt : 1; /* Configure async abts status notice */ 3498 uint32_t rsvd1 : 20; /* Reserved */ 3499 #endif 3500 #ifdef __BIG_ENDIAN_BITFIELD 3501 uint32_t rsvd3 : 20; /* Reserved */ 3502 uint32_t gasabt : 1; /* Grant async abts status notice */ 3503 uint32_t rsvd4 : 2; /* Reserved */ 3504 uint32_t gbg : 1; /* Grant BlockGuard */ 3505 uint32_t gmv : 1; /* Grant Max VPIs */ 3506 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3507 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3508 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3509 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3510 uint32_t gerbm : 1; /* Grant ERBM Request */ 3511 uint32_t gmx : 1; /* Grant Max XRIs */ 3512 uint32_t gmr : 1; /* Grant Max RPIs */ 3513 #else /* __LITTLE_ENDIAN */ 3514 uint32_t gmr : 1; /* Grant Max RPIs */ 3515 uint32_t gmx : 1; /* Grant Max XRIs */ 3516 uint32_t gerbm : 1; /* Grant ERBM Request */ 3517 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3518 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3519 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3520 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3521 uint32_t gmv : 1; /* Grant Max VPIs */ 3522 uint32_t gbg : 1; /* Grant BlockGuard */ 3523 uint32_t rsvd4 : 2; /* Reserved */ 3524 uint32_t gasabt : 1; /* Grant async abts status notice */ 3525 uint32_t rsvd3 : 20; /* Reserved */ 3526 #endif 3527 3528 #ifdef __BIG_ENDIAN_BITFIELD 3529 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3530 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3531 #else /* __LITTLE_ENDIAN */ 3532 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3533 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3534 #endif 3535 3536 #ifdef __BIG_ENDIAN_BITFIELD 3537 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3538 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3539 #else /* __LITTLE_ENDIAN */ 3540 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3541 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3542 #endif 3543 3544 uint32_t rsvd6; /* Reserved */ 3545 3546 #ifdef __BIG_ENDIAN_BITFIELD 3547 uint32_t rsvd7 : 16; 3548 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3549 #else /* __LITTLE_ENDIAN */ 3550 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3551 uint32_t rsvd7 : 16; 3552 #endif 3553 3554 } CONFIG_PORT_VAR; 3555 3556 /* Structure for MB Command CONFIG_MSI (0x30) */ 3557 struct config_msi_var { 3558 #ifdef __BIG_ENDIAN_BITFIELD 3559 uint32_t dfltMsgNum:8; /* Default message number */ 3560 uint32_t rsvd1:11; /* Reserved */ 3561 uint32_t NID:5; /* Number of secondary attention IDs */ 3562 uint32_t rsvd2:5; /* Reserved */ 3563 uint32_t dfltPresent:1; /* Default message number present */ 3564 uint32_t addFlag:1; /* Add association flag */ 3565 uint32_t reportFlag:1; /* Report association flag */ 3566 #else /* __LITTLE_ENDIAN_BITFIELD */ 3567 uint32_t reportFlag:1; /* Report association flag */ 3568 uint32_t addFlag:1; /* Add association flag */ 3569 uint32_t dfltPresent:1; /* Default message number present */ 3570 uint32_t rsvd2:5; /* Reserved */ 3571 uint32_t NID:5; /* Number of secondary attention IDs */ 3572 uint32_t rsvd1:11; /* Reserved */ 3573 uint32_t dfltMsgNum:8; /* Default message number */ 3574 #endif 3575 uint32_t attentionConditions[2]; 3576 uint8_t attentionId[16]; 3577 uint8_t messageNumberByHA[64]; 3578 uint8_t messageNumberByID[16]; 3579 uint32_t autoClearHA[2]; 3580 #ifdef __BIG_ENDIAN_BITFIELD 3581 uint32_t rsvd3:16; 3582 uint32_t autoClearID:16; 3583 #else /* __LITTLE_ENDIAN_BITFIELD */ 3584 uint32_t autoClearID:16; 3585 uint32_t rsvd3:16; 3586 #endif 3587 uint32_t rsvd4; 3588 }; 3589 3590 /* SLI-2 Port Control Block */ 3591 3592 /* SLIM POINTER */ 3593 #define SLIMOFF 0x30 /* WORD */ 3594 3595 typedef struct _SLI2_RDSC { 3596 uint32_t cmdEntries; 3597 uint32_t cmdAddrLow; 3598 uint32_t cmdAddrHigh; 3599 3600 uint32_t rspEntries; 3601 uint32_t rspAddrLow; 3602 uint32_t rspAddrHigh; 3603 } SLI2_RDSC; 3604 3605 typedef struct _PCB { 3606 #ifdef __BIG_ENDIAN_BITFIELD 3607 uint32_t type:8; 3608 #define TYPE_NATIVE_SLI2 0x01 3609 uint32_t feature:8; 3610 #define FEATURE_INITIAL_SLI2 0x01 3611 uint32_t rsvd:12; 3612 uint32_t maxRing:4; 3613 #else /* __LITTLE_ENDIAN_BITFIELD */ 3614 uint32_t maxRing:4; 3615 uint32_t rsvd:12; 3616 uint32_t feature:8; 3617 #define FEATURE_INITIAL_SLI2 0x01 3618 uint32_t type:8; 3619 #define TYPE_NATIVE_SLI2 0x01 3620 #endif 3621 3622 uint32_t mailBoxSize; 3623 uint32_t mbAddrLow; 3624 uint32_t mbAddrHigh; 3625 3626 uint32_t hgpAddrLow; 3627 uint32_t hgpAddrHigh; 3628 3629 uint32_t pgpAddrLow; 3630 uint32_t pgpAddrHigh; 3631 SLI2_RDSC rdsc[MAX_SLI3_RINGS]; 3632 } PCB_t; 3633 3634 /* NEW_FEATURE */ 3635 typedef struct { 3636 #ifdef __BIG_ENDIAN_BITFIELD 3637 uint32_t rsvd0:27; 3638 uint32_t discardFarp:1; 3639 uint32_t IPEnable:1; 3640 uint32_t nodeName:1; 3641 uint32_t portName:1; 3642 uint32_t filterEnable:1; 3643 #else /* __LITTLE_ENDIAN_BITFIELD */ 3644 uint32_t filterEnable:1; 3645 uint32_t portName:1; 3646 uint32_t nodeName:1; 3647 uint32_t IPEnable:1; 3648 uint32_t discardFarp:1; 3649 uint32_t rsvd:27; 3650 #endif 3651 3652 uint8_t portname[8]; /* Used to be struct lpfc_name */ 3653 uint8_t nodename[8]; 3654 uint32_t rsvd1; 3655 uint32_t rsvd2; 3656 uint32_t rsvd3; 3657 uint32_t IPAddress; 3658 } CONFIG_FARP_VAR; 3659 3660 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 3661 3662 typedef struct { 3663 #ifdef __BIG_ENDIAN_BITFIELD 3664 uint32_t rsvd:30; 3665 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3666 #else /* __LITTLE_ENDIAN */ 3667 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3668 uint32_t rsvd:30; 3669 #endif 3670 } ASYNCEVT_ENABLE_VAR; 3671 3672 /* Union of all Mailbox Command types */ 3673 #define MAILBOX_CMD_WSIZE 32 3674 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 3675 /* ext_wsize times 4 bytes should not be greater than max xmit size */ 3676 #define MAILBOX_EXT_WSIZE 512 3677 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 3678 #define MAILBOX_HBA_EXT_OFFSET 0x100 3679 /* max mbox xmit size is a page size for sysfs IO operations */ 3680 #define MAILBOX_SYSFS_MAX 4096 3681 3682 typedef union { 3683 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3684 * feature/max ring number 3685 */ 3686 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3687 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3688 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3689 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3690 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3691 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3692 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3693 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3694 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3695 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3696 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3697 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3698 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3699 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3700 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3701 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3702 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3703 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3704 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3705 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3706 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3707 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3708 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3709 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3710 * NEW_FEATURE 3711 */ 3712 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3713 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3714 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3715 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 3716 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3717 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3718 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3719 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3720 * (READ_EVENT_LOG) 3721 */ 3722 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3723 } MAILVARIANTS; 3724 3725 /* 3726 * SLI-2 specific structures 3727 */ 3728 3729 struct lpfc_hgp { 3730 __le32 cmdPutInx; 3731 __le32 rspGetInx; 3732 }; 3733 3734 struct lpfc_pgp { 3735 __le32 cmdGetInx; 3736 __le32 rspPutInx; 3737 }; 3738 3739 struct sli2_desc { 3740 uint32_t unused1[16]; 3741 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3742 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3743 }; 3744 3745 struct sli3_desc { 3746 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3747 uint32_t reserved[8]; 3748 uint32_t hbq_put[16]; 3749 }; 3750 3751 struct sli3_pgp { 3752 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3753 uint32_t hbq_get[16]; 3754 }; 3755 3756 union sli_var { 3757 struct sli2_desc s2; 3758 struct sli3_desc s3; 3759 struct sli3_pgp s3_pgp; 3760 }; 3761 3762 typedef struct { 3763 struct_group_tagged(MAILBOX_word0, bits, 3764 union { 3765 struct { 3766 #ifdef __BIG_ENDIAN_BITFIELD 3767 uint16_t mbxStatus; 3768 uint8_t mbxCommand; 3769 uint8_t mbxReserved:6; 3770 uint8_t mbxHc:1; 3771 uint8_t mbxOwner:1; /* Low order bit first word */ 3772 #else /* __LITTLE_ENDIAN_BITFIELD */ 3773 uint8_t mbxOwner:1; /* Low order bit first word */ 3774 uint8_t mbxHc:1; 3775 uint8_t mbxReserved:6; 3776 uint8_t mbxCommand; 3777 uint16_t mbxStatus; 3778 #endif 3779 }; 3780 u32 word0; 3781 }; 3782 ); 3783 3784 MAILVARIANTS un; 3785 union sli_var us; 3786 } MAILBOX_t; 3787 3788 /* 3789 * Begin Structure Definitions for IOCB Commands 3790 */ 3791 3792 typedef struct { 3793 #ifdef __BIG_ENDIAN_BITFIELD 3794 uint8_t statAction; 3795 uint8_t statRsn; 3796 uint8_t statBaExp; 3797 uint8_t statLocalError; 3798 #else /* __LITTLE_ENDIAN_BITFIELD */ 3799 uint8_t statLocalError; 3800 uint8_t statBaExp; 3801 uint8_t statRsn; 3802 uint8_t statAction; 3803 #endif 3804 /* statRsn P/F_RJT reason codes */ 3805 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3806 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3807 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3808 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3809 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3810 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3811 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3812 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3813 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3814 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3815 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3816 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3817 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3818 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3819 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3820 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3821 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3822 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3823 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3824 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3825 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3826 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3827 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3828 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3829 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3830 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3831 3832 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3833 #define IOERR_MISSING_CONTINUE 0x01 3834 #define IOERR_SEQUENCE_TIMEOUT 0x02 3835 #define IOERR_INTERNAL_ERROR 0x03 3836 #define IOERR_INVALID_RPI 0x04 3837 #define IOERR_NO_XRI 0x05 3838 #define IOERR_ILLEGAL_COMMAND 0x06 3839 #define IOERR_XCHG_DROPPED 0x07 3840 #define IOERR_ILLEGAL_FIELD 0x08 3841 #define IOERR_RPI_SUSPENDED 0x09 3842 #define IOERR_TOO_MANY_BUFFERS 0x0A 3843 #define IOERR_RCV_BUFFER_WAITING 0x0B 3844 #define IOERR_NO_CONNECTION 0x0C 3845 #define IOERR_TX_DMA_FAILED 0x0D 3846 #define IOERR_RX_DMA_FAILED 0x0E 3847 #define IOERR_ILLEGAL_FRAME 0x0F 3848 #define IOERR_EXTRA_DATA 0x10 3849 #define IOERR_NO_RESOURCES 0x11 3850 #define IOERR_RESERVED 0x12 3851 #define IOERR_ILLEGAL_LENGTH 0x13 3852 #define IOERR_UNSUPPORTED_FEATURE 0x14 3853 #define IOERR_ABORT_IN_PROGRESS 0x15 3854 #define IOERR_ABORT_REQUESTED 0x16 3855 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3856 #define IOERR_LOOP_OPEN_FAILURE 0x18 3857 #define IOERR_RING_RESET 0x19 3858 #define IOERR_LINK_DOWN 0x1A 3859 #define IOERR_CORRUPTED_DATA 0x1B 3860 #define IOERR_CORRUPTED_RPI 0x1C 3861 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3862 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3863 #define IOERR_DUP_FRAME 0x1F 3864 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3865 #define IOERR_BAD_HOST_ADDRESS 0x21 3866 #define IOERR_RCV_HDRBUF_WAITING 0x22 3867 #define IOERR_MISSING_HDR_BUFFER 0x23 3868 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3869 #define IOERR_ABORTMULT_REQUESTED 0x25 3870 #define IOERR_BUFFER_SHORTAGE 0x28 3871 #define IOERR_DEFAULT 0x29 3872 #define IOERR_CNT 0x2A 3873 #define IOERR_SLER_FAILURE 0x46 3874 #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3875 #define IOERR_SLER_REC_RJT_ERR 0x48 3876 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3877 #define IOERR_SLER_SRR_RJT_ERR 0x4A 3878 #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3879 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3880 #define IOERR_SLER_ABTS_ERR 0x4E 3881 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3882 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3883 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3884 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3885 #define IOERR_DRVR_MASK 0x100 3886 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3887 #define IOERR_SLI_BRESET 0x102 3888 #define IOERR_SLI_ABORTED 0x103 3889 #define IOERR_PARAM_MASK 0x1ff 3890 } PARM_ERR; 3891 3892 typedef union { 3893 struct { 3894 #ifdef __BIG_ENDIAN_BITFIELD 3895 uint8_t Rctl; /* R_CTL field */ 3896 uint8_t Type; /* TYPE field */ 3897 uint8_t Dfctl; /* DF_CTL field */ 3898 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3899 #else /* __LITTLE_ENDIAN_BITFIELD */ 3900 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3901 uint8_t Dfctl; /* DF_CTL field */ 3902 uint8_t Type; /* TYPE field */ 3903 uint8_t Rctl; /* R_CTL field */ 3904 #endif 3905 3906 #define BC 0x02 /* Broadcast Received - Fctl */ 3907 #define SI 0x04 /* Sequence Initiative */ 3908 #define LA 0x08 /* Ignore Link Attention state */ 3909 #define LS 0x80 /* Last Sequence */ 3910 } hcsw; 3911 uint32_t reserved; 3912 } WORD5; 3913 3914 /* IOCB Command template for a generic response */ 3915 typedef struct { 3916 uint32_t reserved[4]; 3917 PARM_ERR perr; 3918 } GENERIC_RSP; 3919 3920 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3921 typedef struct { 3922 struct ulp_bde xrsqbde[2]; 3923 uint32_t xrsqRo; /* Starting Relative Offset */ 3924 WORD5 w5; /* Header control/status word */ 3925 } XR_SEQ_FIELDS; 3926 3927 /* IOCB Command template for ELS_REQUEST */ 3928 typedef struct { 3929 struct ulp_bde elsReq; 3930 struct ulp_bde elsRsp; 3931 3932 #ifdef __BIG_ENDIAN_BITFIELD 3933 uint32_t word4Rsvd:7; 3934 uint32_t fl:1; 3935 uint32_t myID:24; 3936 uint32_t word5Rsvd:8; 3937 uint32_t remoteID:24; 3938 #else /* __LITTLE_ENDIAN_BITFIELD */ 3939 uint32_t myID:24; 3940 uint32_t fl:1; 3941 uint32_t word4Rsvd:7; 3942 uint32_t remoteID:24; 3943 uint32_t word5Rsvd:8; 3944 #endif 3945 } ELS_REQUEST; 3946 3947 /* IOCB Command template for RCV_ELS_REQ */ 3948 typedef struct { 3949 struct ulp_bde elsReq[2]; 3950 uint32_t parmRo; 3951 3952 #ifdef __BIG_ENDIAN_BITFIELD 3953 uint32_t word5Rsvd:8; 3954 uint32_t remoteID:24; 3955 #else /* __LITTLE_ENDIAN_BITFIELD */ 3956 uint32_t remoteID:24; 3957 uint32_t word5Rsvd:8; 3958 #endif 3959 } RCV_ELS_REQ; 3960 3961 /* IOCB Command template for ABORT / CLOSE_XRI */ 3962 typedef struct { 3963 uint32_t rsvd[3]; 3964 uint32_t abortType; 3965 #define ABORT_TYPE_ABTX 0x00000000 3966 #define ABORT_TYPE_ABTS 0x00000001 3967 uint32_t parm; 3968 #ifdef __BIG_ENDIAN_BITFIELD 3969 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3970 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3971 #else /* __LITTLE_ENDIAN_BITFIELD */ 3972 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3973 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3974 #endif 3975 } AC_XRI; 3976 3977 /* IOCB Command template for ABORT_MXRI64 */ 3978 typedef struct { 3979 uint32_t rsvd[3]; 3980 uint32_t abortType; 3981 uint32_t parm; 3982 uint32_t iotag32; 3983 } A_MXRI64; 3984 3985 /* IOCB Command template for GET_RPI */ 3986 typedef struct { 3987 uint32_t rsvd[4]; 3988 uint32_t parmRo; 3989 #ifdef __BIG_ENDIAN_BITFIELD 3990 uint32_t word5Rsvd:8; 3991 uint32_t remoteID:24; 3992 #else /* __LITTLE_ENDIAN_BITFIELD */ 3993 uint32_t remoteID:24; 3994 uint32_t word5Rsvd:8; 3995 #endif 3996 } GET_RPI; 3997 3998 /* IOCB Command template for all FCP Initiator commands */ 3999 typedef struct { 4000 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 4001 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 4002 uint32_t fcpi_parm; 4003 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 4004 } FCPI_FIELDS; 4005 4006 /* IOCB Command template for all FCP Target commands */ 4007 typedef struct { 4008 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 4009 uint32_t fcpt_Offset; 4010 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 4011 } FCPT_FIELDS; 4012 4013 /* SLI-2 IOCB structure definitions */ 4014 4015 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 4016 typedef struct { 4017 ULP_BDL bdl; 4018 uint32_t xrsqRo; /* Starting Relative Offset */ 4019 WORD5 w5; /* Header control/status word */ 4020 } XMT_SEQ_FIELDS64; 4021 4022 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */ 4023 #define xmit_els_remoteID xrsqRo 4024 4025 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 4026 typedef struct { 4027 struct ulp_bde64 rcvBde; 4028 uint32_t rsvd1; 4029 uint32_t xrsqRo; /* Starting Relative Offset */ 4030 WORD5 w5; /* Header control/status word */ 4031 } RCV_SEQ_FIELDS64; 4032 4033 /* IOCB Command template for ELS_REQUEST64 */ 4034 typedef struct { 4035 ULP_BDL bdl; 4036 #ifdef __BIG_ENDIAN_BITFIELD 4037 uint32_t word4Rsvd:7; 4038 uint32_t fl:1; 4039 uint32_t myID:24; 4040 uint32_t word5Rsvd:8; 4041 uint32_t remoteID:24; 4042 #else /* __LITTLE_ENDIAN_BITFIELD */ 4043 uint32_t myID:24; 4044 uint32_t fl:1; 4045 uint32_t word4Rsvd:7; 4046 uint32_t remoteID:24; 4047 uint32_t word5Rsvd:8; 4048 #endif 4049 } ELS_REQUEST64; 4050 4051 /* IOCB Command template for GEN_REQUEST64 */ 4052 typedef struct { 4053 ULP_BDL bdl; 4054 uint32_t xrsqRo; /* Starting Relative Offset */ 4055 WORD5 w5; /* Header control/status word */ 4056 } GEN_REQUEST64; 4057 4058 /* IOCB Command template for RCV_ELS_REQ64 */ 4059 typedef struct { 4060 struct ulp_bde64 elsReq; 4061 uint32_t rcvd1; 4062 uint32_t parmRo; 4063 4064 #ifdef __BIG_ENDIAN_BITFIELD 4065 uint32_t word5Rsvd:8; 4066 uint32_t remoteID:24; 4067 #else /* __LITTLE_ENDIAN_BITFIELD */ 4068 uint32_t remoteID:24; 4069 uint32_t word5Rsvd:8; 4070 #endif 4071 } RCV_ELS_REQ64; 4072 4073 /* IOCB Command template for RCV_SEQ64 */ 4074 struct rcv_seq64 { 4075 struct ulp_bde64 elsReq; 4076 uint32_t hbq_1; 4077 uint32_t parmRo; 4078 #ifdef __BIG_ENDIAN_BITFIELD 4079 uint32_t rctl:8; 4080 uint32_t type:8; 4081 uint32_t dfctl:8; 4082 uint32_t ls:1; 4083 uint32_t fs:1; 4084 uint32_t rsvd2:3; 4085 uint32_t si:1; 4086 uint32_t bc:1; 4087 uint32_t rsvd3:1; 4088 #else /* __LITTLE_ENDIAN_BITFIELD */ 4089 uint32_t rsvd3:1; 4090 uint32_t bc:1; 4091 uint32_t si:1; 4092 uint32_t rsvd2:3; 4093 uint32_t fs:1; 4094 uint32_t ls:1; 4095 uint32_t dfctl:8; 4096 uint32_t type:8; 4097 uint32_t rctl:8; 4098 #endif 4099 }; 4100 4101 /* IOCB Command template for all 64 bit FCP Initiator commands */ 4102 typedef struct { 4103 ULP_BDL bdl; 4104 uint32_t fcpi_parm; 4105 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 4106 } FCPI_FIELDS64; 4107 4108 /* IOCB Command template for all 64 bit FCP Target commands */ 4109 typedef struct { 4110 ULP_BDL bdl; 4111 uint32_t fcpt_Offset; 4112 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 4113 } FCPT_FIELDS64; 4114 4115 /* IOCB Command template for Async Status iocb commands */ 4116 typedef struct { 4117 uint32_t rsvd[4]; 4118 uint32_t param; 4119 #ifdef __BIG_ENDIAN_BITFIELD 4120 uint16_t evt_code; /* High order bits word 5 */ 4121 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 4122 #else /* __LITTLE_ENDIAN_BITFIELD */ 4123 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 4124 uint16_t evt_code; /* Low order bits word 5 */ 4125 #endif 4126 } ASYNCSTAT_FIELDS; 4127 #define ASYNC_TEMP_WARN 0x100 4128 #define ASYNC_TEMP_SAFE 0x101 4129 #define ASYNC_STATUS_CN 0x102 4130 4131 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 4132 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 4133 4134 struct rcv_sli3 { 4135 #ifdef __BIG_ENDIAN_BITFIELD 4136 uint16_t ox_id; 4137 uint16_t seq_cnt; 4138 4139 uint16_t vpi; 4140 uint16_t word9Rsvd; 4141 #else /* __LITTLE_ENDIAN */ 4142 uint16_t seq_cnt; 4143 uint16_t ox_id; 4144 4145 uint16_t word9Rsvd; 4146 uint16_t vpi; 4147 #endif 4148 uint32_t word10Rsvd; 4149 uint32_t acc_len; /* accumulated length */ 4150 struct ulp_bde64 bde2; 4151 }; 4152 4153 /* Structure used for a single HBQ entry */ 4154 struct lpfc_hbq_entry { 4155 struct ulp_bde64 bde; 4156 uint32_t buffer_tag; 4157 }; 4158 4159 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 4160 typedef struct { 4161 struct lpfc_hbq_entry buff; 4162 uint32_t rsvd; 4163 uint32_t rsvd1; 4164 } QUE_XRI64_CX_FIELDS; 4165 4166 struct que_xri64cx_ext_fields { 4167 uint32_t iotag64_low; 4168 uint32_t iotag64_high; 4169 uint32_t ebde_count; 4170 uint32_t rsvd; 4171 struct lpfc_hbq_entry buff[5]; 4172 }; 4173 4174 struct sli3_bg_fields { 4175 uint32_t filler[6]; /* word 8-13 in IOCB */ 4176 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 4177 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 4178 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 4179 #define BGS_BIDIR_BG_PROF_SHIFT 24 4180 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 4181 #define BGS_BIDIR_ERR_COND_SHIFT 16 4182 #define BGS_BG_PROFILE_MASK 0x0000ff00 4183 #define BGS_BG_PROFILE_SHIFT 8 4184 #define BGS_INVALID_PROF_MASK 0x00000020 4185 #define BGS_INVALID_PROF_SHIFT 5 4186 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 4187 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 4188 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 4189 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 4190 #define BGS_REFTAG_ERR_MASK 0x00000004 4191 #define BGS_REFTAG_ERR_SHIFT 2 4192 #define BGS_APPTAG_ERR_MASK 0x00000002 4193 #define BGS_APPTAG_ERR_SHIFT 1 4194 #define BGS_GUARD_ERR_MASK 0x00000001 4195 #define BGS_GUARD_ERR_SHIFT 0 4196 uint32_t bgstat; /* word 15 - BlockGuard Status */ 4197 }; 4198 4199 static inline uint32_t 4200 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 4201 { 4202 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 4203 BGS_BIDIR_BG_PROF_SHIFT; 4204 } 4205 4206 static inline uint32_t 4207 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 4208 { 4209 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 4210 BGS_BIDIR_ERR_COND_SHIFT; 4211 } 4212 4213 static inline uint32_t 4214 lpfc_bgs_get_bg_prof(uint32_t bgstat) 4215 { 4216 return (bgstat & BGS_BG_PROFILE_MASK) >> 4217 BGS_BG_PROFILE_SHIFT; 4218 } 4219 4220 static inline uint32_t 4221 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 4222 { 4223 return (bgstat & BGS_INVALID_PROF_MASK) >> 4224 BGS_INVALID_PROF_SHIFT; 4225 } 4226 4227 static inline uint32_t 4228 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 4229 { 4230 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 4231 BGS_UNINIT_DIF_BLOCK_SHIFT; 4232 } 4233 4234 static inline uint32_t 4235 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 4236 { 4237 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 4238 BGS_HI_WATER_MARK_PRESENT_SHIFT; 4239 } 4240 4241 static inline uint32_t 4242 lpfc_bgs_get_reftag_err(uint32_t bgstat) 4243 { 4244 return (bgstat & BGS_REFTAG_ERR_MASK) >> 4245 BGS_REFTAG_ERR_SHIFT; 4246 } 4247 4248 static inline uint32_t 4249 lpfc_bgs_get_apptag_err(uint32_t bgstat) 4250 { 4251 return (bgstat & BGS_APPTAG_ERR_MASK) >> 4252 BGS_APPTAG_ERR_SHIFT; 4253 } 4254 4255 static inline uint32_t 4256 lpfc_bgs_get_guard_err(uint32_t bgstat) 4257 { 4258 return (bgstat & BGS_GUARD_ERR_MASK) >> 4259 BGS_GUARD_ERR_SHIFT; 4260 } 4261 4262 #define LPFC_EXT_DATA_BDE_COUNT 3 4263 struct fcp_irw_ext { 4264 uint32_t io_tag64_low; 4265 uint32_t io_tag64_high; 4266 #ifdef __BIG_ENDIAN_BITFIELD 4267 uint8_t reserved1; 4268 uint8_t reserved2; 4269 uint8_t reserved3; 4270 uint8_t ebde_count; 4271 #else /* __LITTLE_ENDIAN */ 4272 uint8_t ebde_count; 4273 uint8_t reserved3; 4274 uint8_t reserved2; 4275 uint8_t reserved1; 4276 #endif 4277 uint32_t reserved4; 4278 struct ulp_bde64 rbde; /* response bde */ 4279 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 4280 uint8_t icd[32]; /* immediate command data (32 bytes) */ 4281 }; 4282 4283 typedef struct _IOCB { /* IOCB structure */ 4284 union { 4285 GENERIC_RSP grsp; /* Generic response */ 4286 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 4287 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 4288 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 4289 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 4290 A_MXRI64 amxri; /* abort multiple xri command overlay */ 4291 GET_RPI getrpi; /* GET_RPI template */ 4292 FCPI_FIELDS fcpi; /* FCP Initiator template */ 4293 FCPT_FIELDS fcpt; /* FCP target template */ 4294 4295 /* SLI-2 structures */ 4296 4297 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 4298 * bde_64s */ 4299 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 4300 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 4301 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 4302 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 4303 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 4304 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 4305 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 4306 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 4307 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 4308 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 4309 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 4310 } un; 4311 union { 4312 struct { 4313 #ifdef __BIG_ENDIAN_BITFIELD 4314 uint16_t ulpContext; /* High order bits word 6 */ 4315 uint16_t ulpIoTag; /* Low order bits word 6 */ 4316 #else /* __LITTLE_ENDIAN_BITFIELD */ 4317 uint16_t ulpIoTag; /* Low order bits word 6 */ 4318 uint16_t ulpContext; /* High order bits word 6 */ 4319 #endif 4320 } t1; 4321 struct { 4322 #ifdef __BIG_ENDIAN_BITFIELD 4323 uint16_t ulpContext; /* High order bits word 6 */ 4324 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4325 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4326 #else /* __LITTLE_ENDIAN_BITFIELD */ 4327 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4328 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4329 uint16_t ulpContext; /* High order bits word 6 */ 4330 #endif 4331 } t2; 4332 } un1; 4333 #define ulpContext un1.t1.ulpContext 4334 #define ulpIoTag un1.t1.ulpIoTag 4335 #define ulpIoTag0 un1.t2.ulpIoTag0 4336 4337 #ifdef __BIG_ENDIAN_BITFIELD 4338 uint32_t ulpTimeout:8; 4339 uint32_t ulpXS:1; 4340 uint32_t ulpFCP2Rcvy:1; 4341 uint32_t ulpPU:2; 4342 uint32_t ulpIr:1; 4343 uint32_t ulpClass:3; 4344 uint32_t ulpCommand:8; 4345 uint32_t ulpStatus:4; 4346 uint32_t ulpBdeCount:2; 4347 uint32_t ulpLe:1; 4348 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4349 #else /* __LITTLE_ENDIAN_BITFIELD */ 4350 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4351 uint32_t ulpLe:1; 4352 uint32_t ulpBdeCount:2; 4353 uint32_t ulpStatus:4; 4354 uint32_t ulpCommand:8; 4355 uint32_t ulpClass:3; 4356 uint32_t ulpIr:1; 4357 uint32_t ulpPU:2; 4358 uint32_t ulpFCP2Rcvy:1; 4359 uint32_t ulpXS:1; 4360 uint32_t ulpTimeout:8; 4361 #endif 4362 4363 union { 4364 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 4365 4366 /* words 8-31 used for que_xri_cx iocb */ 4367 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 4368 struct fcp_irw_ext fcp_ext; 4369 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 4370 4371 /* words 8-15 for BlockGuard */ 4372 struct sli3_bg_fields sli3_bg; 4373 } unsli3; 4374 4375 #define ulpCt_h ulpXS 4376 #define ulpCt_l ulpFCP2Rcvy 4377 4378 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 4379 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 4380 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 4381 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 4382 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 4383 #define PARM_NPIV_DID 3 4384 #define CLASS1 0 /* Class 1 */ 4385 #define CLASS2 1 /* Class 2 */ 4386 #define CLASS3 2 /* Class 3 */ 4387 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 4388 4389 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 4390 #define IOSTAT_FCP_RSP_ERROR 0x1 4391 #define IOSTAT_REMOTE_STOP 0x2 4392 #define IOSTAT_LOCAL_REJECT 0x3 4393 #define IOSTAT_NPORT_RJT 0x4 4394 #define IOSTAT_FABRIC_RJT 0x5 4395 #define IOSTAT_NPORT_BSY 0x6 4396 #define IOSTAT_FABRIC_BSY 0x7 4397 #define IOSTAT_INTERMED_RSP 0x8 4398 #define IOSTAT_LS_RJT 0x9 4399 #define IOSTAT_BA_RJT 0xA 4400 #define IOSTAT_RSVD1 0xB 4401 #define IOSTAT_RSVD2 0xC 4402 #define IOSTAT_RSVD3 0xD 4403 #define IOSTAT_RSVD4 0xE 4404 #define IOSTAT_NEED_BUFFER 0xF 4405 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 4406 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 4407 #define IOSTAT_CNT 0x11 4408 4409 } IOCB_t; 4410 4411 4412 #define SLI1_SLIM_SIZE (4 * 1024) 4413 4414 /* Up to 498 IOCBs will fit into 16k 4415 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 4416 */ 4417 #define SLI2_SLIM_SIZE (64 * 1024) 4418 4419 /* Maximum IOCBs that will fit in SLI2 slim */ 4420 #define MAX_SLI2_IOCB 498 4421 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 4422 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 4423 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 4424 4425 /* HBQ entries are 4 words each = 4k */ 4426 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 4427 lpfc_sli_hbq_count()) 4428 4429 struct lpfc_sli2_slim { 4430 MAILBOX_t mbx; 4431 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 4432 PCB_t pcb; 4433 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 4434 }; 4435 4436 /* 4437 * This function checks PCI device to allow special handling for LC HBAs. 4438 * 4439 * Parameters: 4440 * device : struct pci_dev 's device field 4441 * 4442 * return 1 => TRUE 4443 * 0 => FALSE 4444 */ 4445 static inline int 4446 lpfc_is_LC_HBA(unsigned short device) 4447 { 4448 if ((device == PCI_DEVICE_ID_TFLY) || 4449 (device == PCI_DEVICE_ID_PFLY) || 4450 (device == PCI_DEVICE_ID_LP101) || 4451 (device == PCI_DEVICE_ID_BMID) || 4452 (device == PCI_DEVICE_ID_BSMB) || 4453 (device == PCI_DEVICE_ID_ZMID) || 4454 (device == PCI_DEVICE_ID_ZSMB) || 4455 (device == PCI_DEVICE_ID_SAT_MID) || 4456 (device == PCI_DEVICE_ID_SAT_SMB) || 4457 (device == PCI_DEVICE_ID_RFLY)) 4458 return 1; 4459 else 4460 return 0; 4461 } 4462 4463 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 4464