1dea3101eS /******************************************************************* 2dea3101eS * This file is part of the Emulex Linux Device Driver for * 3c44ce173SJames.Smart@Emulex.Com * Fibre Channel Host Bus Adapters. * 44fede78fSJames Smart * Copyright (C) 2004-2010 Emulex. All rights reserved. * 5c44ce173SJames.Smart@Emulex.Com * EMULEX and SLI are trademarks of Emulex. * 6dea3101eS * www.emulex.com * 7dea3101eS * * 8dea3101eS * This program is free software; you can redistribute it and/or * 9c44ce173SJames.Smart@Emulex.Com * modify it under the terms of version 2 of the GNU General * 10c44ce173SJames.Smart@Emulex.Com * Public License as published by the Free Software Foundation. * 11c44ce173SJames.Smart@Emulex.Com * This program is distributed in the hope that it will be useful. * 12c44ce173SJames.Smart@Emulex.Com * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13c44ce173SJames.Smart@Emulex.Com * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14c44ce173SJames.Smart@Emulex.Com * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15c44ce173SJames.Smart@Emulex.Com * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16c44ce173SJames.Smart@Emulex.Com * TO BE LEGALLY INVALID. See the GNU General Public License for * 17c44ce173SJames.Smart@Emulex.Com * more details, a copy of which can be found in the file COPYING * 18c44ce173SJames.Smart@Emulex.Com * included with this package. * 19dea3101eS *******************************************************************/ 20dea3101eS 21dea3101eS #define FDMI_DID 0xfffffaU 22dea3101eS #define NameServer_DID 0xfffffcU 23dea3101eS #define SCR_DID 0xfffffdU 24dea3101eS #define Fabric_DID 0xfffffeU 25dea3101eS #define Bcast_DID 0xffffffU 26dea3101eS #define Mask_DID 0xffffffU 27dea3101eS #define CT_DID_MASK 0xffff00U 28dea3101eS #define Fabric_DID_MASK 0xfff000U 29dea3101eS #define WELL_KNOWN_DID_MASK 0xfffff0U 30dea3101eS 31dea3101eS #define PT2PT_LocalID 1 32dea3101eS #define PT2PT_RemoteID 2 33dea3101eS 34dea3101eS #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35dea3101eS #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36dea3101eS #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37dea3101eS #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38dea3101eS 39dea3101eS #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40dea3101eS 0 */ 41dea3101eS 42dea3101eS #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43dea3101eS 44dea3101eS #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45a4bc3379SJames Smart #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46dea3101eS #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47dea3101eS #define LPFC_FCP_NEXT_RING 3 48dea3101eS 49dea3101eS #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50dea3101eS #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51a4bc3379SJames Smart #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 52a4bc3379SJames Smart #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 53dea3101eS #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54dea3101eS #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55dea3101eS #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56dea3101eS #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57dea3101eS #define SLI2_IOCB_CMD_R3_ENTRIES 0 58dea3101eS #define SLI2_IOCB_RSP_R3_ENTRIES 0 59dea3101eS #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60dea3101eS #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61dea3101eS 62ed957684SJames Smart #define SLI2_IOCB_CMD_SIZE 32 63ed957684SJames Smart #define SLI2_IOCB_RSP_SIZE 32 64ed957684SJames Smart #define SLI3_IOCB_CMD_SIZE 128 65ed957684SJames Smart #define SLI3_IOCB_RSP_SIZE 64 66ed957684SJames Smart 676d368e53SJames Smart #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 686d368e53SJames Smart #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 6992d7f7b0SJames Smart 70ddcc50f0SJames Smart /* vendor ID used in SCSI netlink calls */ 71ddcc50f0SJames Smart #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 72ddcc50f0SJames Smart 73dea3101eS /* Common Transport structures and definitions */ 74dea3101eS 75dea3101eS union CtRevisionId { 76dea3101eS /* Structure is in Big Endian format */ 77dea3101eS struct { 78dea3101eS uint32_t Revision:8; 79dea3101eS uint32_t InId:24; 80dea3101eS } bits; 81dea3101eS uint32_t word; 82dea3101eS }; 83dea3101eS 84dea3101eS union CtCommandResponse { 85dea3101eS /* Structure is in Big Endian format */ 86dea3101eS struct { 87dea3101eS uint32_t CmdRsp:16; 88dea3101eS uint32_t Size:16; 89dea3101eS } bits; 90dea3101eS uint32_t word; 91dea3101eS }; 92dea3101eS 9392d7f7b0SJames Smart #define FC4_FEATURE_INIT 0x2 9492d7f7b0SJames Smart #define FC4_FEATURE_TARGET 0x1 9592d7f7b0SJames Smart 96dea3101eS struct lpfc_sli_ct_request { 97dea3101eS /* Structure is in Big Endian format */ 98dea3101eS union CtRevisionId RevisionId; 99dea3101eS uint8_t FsType; 100dea3101eS uint8_t FsSubType; 101dea3101eS uint8_t Options; 102dea3101eS uint8_t Rsrvd1; 103dea3101eS union CtCommandResponse CommandResponse; 104dea3101eS uint8_t Rsrvd2; 105dea3101eS uint8_t ReasonCode; 106dea3101eS uint8_t Explanation; 107dea3101eS uint8_t VendorUnique; 108dea3101eS 109dea3101eS union { 110dea3101eS uint32_t PortID; 111dea3101eS struct gid { 112dea3101eS uint8_t PortType; /* for GID_PT requests */ 113dea3101eS uint8_t DomainScope; 114dea3101eS uint8_t AreaScope; 115dea3101eS uint8_t Fc4Type; /* for GID_FT requests */ 116dea3101eS } gid; 117dea3101eS struct rft { 118dea3101eS uint32_t PortId; /* For RFT_ID requests */ 119dea3101eS 120dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 121dea3101eS uint32_t rsvd0:16; 122dea3101eS uint32_t rsvd1:7; 123dea3101eS uint32_t fcpReg:1; /* Type 8 */ 124dea3101eS uint32_t rsvd2:2; 125dea3101eS uint32_t ipReg:1; /* Type 5 */ 126dea3101eS uint32_t rsvd3:5; 127dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 128dea3101eS uint32_t rsvd0:16; 129dea3101eS uint32_t fcpReg:1; /* Type 8 */ 130dea3101eS uint32_t rsvd1:7; 131dea3101eS uint32_t rsvd3:5; 132dea3101eS uint32_t ipReg:1; /* Type 5 */ 133dea3101eS uint32_t rsvd2:2; 134dea3101eS #endif 135dea3101eS 136dea3101eS uint32_t rsvd[7]; 137dea3101eS } rft; 138dea3101eS struct rnn { 139dea3101eS uint32_t PortId; /* For RNN_ID requests */ 140dea3101eS uint8_t wwnn[8]; 141dea3101eS } rnn; 142dea3101eS struct rsnn { /* For RSNN_ID requests */ 143dea3101eS uint8_t wwnn[8]; 144dea3101eS uint8_t len; 145dea3101eS uint8_t symbname[255]; 146dea3101eS } rsnn; 1477ee5d43eSJames Smart struct da_id { /* For DA_ID requests */ 1487ee5d43eSJames Smart uint32_t port_id; 1497ee5d43eSJames Smart } da_id; 15092d7f7b0SJames Smart struct rspn { /* For RSPN_ID requests */ 15192d7f7b0SJames Smart uint32_t PortId; 15292d7f7b0SJames Smart uint8_t len; 15392d7f7b0SJames Smart uint8_t symbname[255]; 15492d7f7b0SJames Smart } rspn; 15592d7f7b0SJames Smart struct gff { 15692d7f7b0SJames Smart uint32_t PortId; 15792d7f7b0SJames Smart } gff; 15892d7f7b0SJames Smart struct gff_acc { 15992d7f7b0SJames Smart uint8_t fbits[128]; 16092d7f7b0SJames Smart } gff_acc; 16151ef4c26SJames Smart #define FCP_TYPE_FEATURE_OFFSET 7 16292d7f7b0SJames Smart struct rff { 16392d7f7b0SJames Smart uint32_t PortId; 16492d7f7b0SJames Smart uint8_t reserved[2]; 16592d7f7b0SJames Smart uint8_t fbits; 16692d7f7b0SJames Smart uint8_t type_code; /* type=8 for FCP */ 16792d7f7b0SJames Smart } rff; 168dea3101eS } un; 169dea3101eS }; 170dea3101eS 171dea3101eS #define SLI_CT_REVISION 1 17292d7f7b0SJames Smart #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17392d7f7b0SJames Smart sizeof(struct gid)) 17492d7f7b0SJames Smart #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17592d7f7b0SJames Smart sizeof(struct gff)) 17692d7f7b0SJames Smart #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17792d7f7b0SJames Smart sizeof(struct rft)) 17892d7f7b0SJames Smart #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17992d7f7b0SJames Smart sizeof(struct rff)) 18092d7f7b0SJames Smart #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 18192d7f7b0SJames Smart sizeof(struct rnn)) 18292d7f7b0SJames Smart #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 18392d7f7b0SJames Smart sizeof(struct rsnn)) 1847ee5d43eSJames Smart #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 1857ee5d43eSJames Smart sizeof(struct da_id)) 18692d7f7b0SJames Smart #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 18792d7f7b0SJames Smart sizeof(struct rspn)) 188dea3101eS 189dea3101eS /* 190dea3101eS * FsType Definitions 191dea3101eS */ 192dea3101eS 193dea3101eS #define SLI_CT_MANAGEMENT_SERVICE 0xFA 194dea3101eS #define SLI_CT_TIME_SERVICE 0xFB 195dea3101eS #define SLI_CT_DIRECTORY_SERVICE 0xFC 196dea3101eS #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 197dea3101eS 198dea3101eS /* 199dea3101eS * Directory Service Subtypes 200dea3101eS */ 201dea3101eS 202dea3101eS #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 203dea3101eS 204dea3101eS /* 205dea3101eS * Response Codes 206dea3101eS */ 207dea3101eS 208dea3101eS #define SLI_CT_RESPONSE_FS_RJT 0x8001 209dea3101eS #define SLI_CT_RESPONSE_FS_ACC 0x8002 210dea3101eS 211dea3101eS /* 212dea3101eS * Reason Codes 213dea3101eS */ 214dea3101eS 215dea3101eS #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 216dea3101eS #define SLI_CT_INVALID_COMMAND 0x01 217dea3101eS #define SLI_CT_INVALID_VERSION 0x02 218dea3101eS #define SLI_CT_LOGICAL_ERROR 0x03 219dea3101eS #define SLI_CT_INVALID_IU_SIZE 0x04 220dea3101eS #define SLI_CT_LOGICAL_BUSY 0x05 221dea3101eS #define SLI_CT_PROTOCOL_ERROR 0x07 222dea3101eS #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 223dea3101eS #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 224dea3101eS #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 225dea3101eS #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 226dea3101eS #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 227dea3101eS #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 228dea3101eS #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 229dea3101eS #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 230dea3101eS #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 231dea3101eS #define SLI_CT_VENDOR_UNIQUE 0xff 232dea3101eS 233dea3101eS /* 234dea3101eS * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 235dea3101eS */ 236dea3101eS 237dea3101eS #define SLI_CT_NO_PORT_ID 0x01 238dea3101eS #define SLI_CT_NO_PORT_NAME 0x02 239dea3101eS #define SLI_CT_NO_NODE_NAME 0x03 240dea3101eS #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 241dea3101eS #define SLI_CT_NO_IP_ADDRESS 0x05 242dea3101eS #define SLI_CT_NO_IPA 0x06 243dea3101eS #define SLI_CT_NO_FC4_TYPES 0x07 244dea3101eS #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 245dea3101eS #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 246dea3101eS #define SLI_CT_NO_PORT_TYPE 0x0A 247dea3101eS #define SLI_CT_ACCESS_DENIED 0x10 248dea3101eS #define SLI_CT_INVALID_PORT_ID 0x11 249dea3101eS #define SLI_CT_DATABASE_EMPTY 0x12 250dea3101eS 251dea3101eS /* 252dea3101eS * Name Server Command Codes 253dea3101eS */ 254dea3101eS 255dea3101eS #define SLI_CTNS_GA_NXT 0x0100 256dea3101eS #define SLI_CTNS_GPN_ID 0x0112 257dea3101eS #define SLI_CTNS_GNN_ID 0x0113 258dea3101eS #define SLI_CTNS_GCS_ID 0x0114 259dea3101eS #define SLI_CTNS_GFT_ID 0x0117 260dea3101eS #define SLI_CTNS_GSPN_ID 0x0118 261dea3101eS #define SLI_CTNS_GPT_ID 0x011A 26292d7f7b0SJames Smart #define SLI_CTNS_GFF_ID 0x011F 263dea3101eS #define SLI_CTNS_GID_PN 0x0121 264dea3101eS #define SLI_CTNS_GID_NN 0x0131 265dea3101eS #define SLI_CTNS_GIP_NN 0x0135 266dea3101eS #define SLI_CTNS_GIPA_NN 0x0136 267dea3101eS #define SLI_CTNS_GSNN_NN 0x0139 268dea3101eS #define SLI_CTNS_GNN_IP 0x0153 269dea3101eS #define SLI_CTNS_GIPA_IP 0x0156 270dea3101eS #define SLI_CTNS_GID_FT 0x0171 271dea3101eS #define SLI_CTNS_GID_PT 0x01A1 272dea3101eS #define SLI_CTNS_RPN_ID 0x0212 273dea3101eS #define SLI_CTNS_RNN_ID 0x0213 274dea3101eS #define SLI_CTNS_RCS_ID 0x0214 275dea3101eS #define SLI_CTNS_RFT_ID 0x0217 276dea3101eS #define SLI_CTNS_RSPN_ID 0x0218 277dea3101eS #define SLI_CTNS_RPT_ID 0x021A 27892d7f7b0SJames Smart #define SLI_CTNS_RFF_ID 0x021F 279dea3101eS #define SLI_CTNS_RIP_NN 0x0235 280dea3101eS #define SLI_CTNS_RIPA_NN 0x0236 281dea3101eS #define SLI_CTNS_RSNN_NN 0x0239 282dea3101eS #define SLI_CTNS_DA_ID 0x0300 283dea3101eS 284dea3101eS /* 285dea3101eS * Port Types 286dea3101eS */ 287dea3101eS 288dea3101eS #define SLI_CTPT_N_PORT 0x01 289dea3101eS #define SLI_CTPT_NL_PORT 0x02 290dea3101eS #define SLI_CTPT_FNL_PORT 0x03 291dea3101eS #define SLI_CTPT_IP 0x04 292dea3101eS #define SLI_CTPT_FCP 0x08 293dea3101eS #define SLI_CTPT_NX_PORT 0x7F 294dea3101eS #define SLI_CTPT_F_PORT 0x81 295dea3101eS #define SLI_CTPT_FL_PORT 0x82 296dea3101eS #define SLI_CTPT_E_PORT 0x84 297dea3101eS 298dea3101eS #define SLI_CT_LAST_ENTRY 0x80000000 299dea3101eS 300dea3101eS /* Fibre Channel Service Parameter definitions */ 301dea3101eS 302dea3101eS #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 303dea3101eS #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 304dea3101eS #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 305dea3101eS #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 306dea3101eS 307dea3101eS #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 308dea3101eS #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 309dea3101eS #define FC_PH3 0x20 /* FC-PH-3 version */ 310dea3101eS 311dea3101eS #define FF_FRAME_SIZE 2048 312dea3101eS 313dea3101eS struct lpfc_name { 314f631b4beSAndrew Vasquez union { 315f631b4beSAndrew Vasquez struct { 316dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 317dea3101eS uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 3181de933f3SJames.Smart@Emulex.Com uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 3191de933f3SJames.Smart@Emulex.Com 8:11 of IEEE ext */ 320dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3211de933f3SJames.Smart@Emulex.Com uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 3221de933f3SJames.Smart@Emulex.Com 8:11 of IEEE ext */ 323dea3101eS uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 324dea3101eS #endif 325dea3101eS 326dea3101eS #define NAME_IEEE 0x1 /* IEEE name - nameType */ 327dea3101eS #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 328dea3101eS #define NAME_FC_TYPE 0x3 /* FC native name type */ 329dea3101eS #define NAME_IP_TYPE 0x4 /* IP address */ 330dea3101eS #define NAME_CCITT_TYPE 0xC 331dea3101eS #define NAME_CCITT_GR_TYPE 0xE 3321de933f3SJames.Smart@Emulex.Com uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 3331de933f3SJames.Smart@Emulex.Com extended Lsb */ 334dea3101eS uint8_t IEEE[6]; /* FC IEEE address */ 33568ce1eb5SAndrew Morton } s; 336f631b4beSAndrew Vasquez uint8_t wwn[8]; 33768ce1eb5SAndrew Morton } u; 338f631b4beSAndrew Vasquez }; 339dea3101eS 340dea3101eS struct csp { 341dea3101eS uint8_t fcphHigh; /* FC Word 0, byte 0 */ 342dea3101eS uint8_t fcphLow; 343dea3101eS uint8_t bbCreditMsb; 344dea3101eS uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 345dea3101eS 34692494144SJames Smart /* 34792494144SJames Smart * Word 1 Bit 31 in common service parameter is overloaded. 34892494144SJames Smart * Word 1 Bit 31 in FLOGI request is multiple NPort request 34992494144SJames Smart * Word 1 Bit 31 in FLOGI response is clean address bit 35092494144SJames Smart */ 35192494144SJames Smart #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 352*df9e1b59SJames Smart /* 353*df9e1b59SJames Smart * Word 1 Bit 30 in common service parameter is overloaded. 354*df9e1b59SJames Smart * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 355*df9e1b59SJames Smart * Word 1 Bit 30 in PLOGI request is random offset 356*df9e1b59SJames Smart */ 357*df9e1b59SJames Smart #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 358dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 35992d7f7b0SJames Smart uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 36092d7f7b0SJames Smart uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 36192d7f7b0SJames Smart uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 362dea3101eS uint16_t fPort:1; /* FC Word 1, bit 28 */ 363dea3101eS uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 364dea3101eS uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 365dea3101eS uint16_t multicast:1; /* FC Word 1, bit 25 */ 366dea3101eS uint16_t broadcast:1; /* FC Word 1, bit 24 */ 367dea3101eS 368dea3101eS uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 369dea3101eS uint16_t simplex:1; /* FC Word 1, bit 22 */ 370dea3101eS uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 371dea3101eS uint16_t dhd:1; /* FC Word 1, bit 18 */ 372dea3101eS uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 373dea3101eS uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 374dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 375dea3101eS uint16_t broadcast:1; /* FC Word 1, bit 24 */ 376dea3101eS uint16_t multicast:1; /* FC Word 1, bit 25 */ 377dea3101eS uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 378dea3101eS uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 379dea3101eS uint16_t fPort:1; /* FC Word 1, bit 28 */ 38092d7f7b0SJames Smart uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 381dea3101eS uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 38292d7f7b0SJames Smart uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 383dea3101eS 384dea3101eS uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 385dea3101eS uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 386dea3101eS uint16_t dhd:1; /* FC Word 1, bit 18 */ 387dea3101eS uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 388dea3101eS uint16_t simplex:1; /* FC Word 1, bit 22 */ 389dea3101eS uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 390dea3101eS #endif 391dea3101eS 392dea3101eS uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 393dea3101eS uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 394dea3101eS union { 395dea3101eS struct { 396dea3101eS uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 397dea3101eS 398dea3101eS uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 399dea3101eS uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 400dea3101eS 401dea3101eS uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 402dea3101eS } nPort; 403dea3101eS uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 404dea3101eS } w2; 405dea3101eS 406dea3101eS uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 407dea3101eS }; 408dea3101eS 409dea3101eS struct class_parms { 410dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 411dea3101eS uint8_t classValid:1; /* FC Word 0, bit 31 */ 412dea3101eS uint8_t intermix:1; /* FC Word 0, bit 30 */ 413dea3101eS uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 414dea3101eS uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 415dea3101eS uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 416dea3101eS uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 417dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 418dea3101eS uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 419dea3101eS uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 420dea3101eS uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 421dea3101eS uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 422dea3101eS uint8_t intermix:1; /* FC Word 0, bit 30 */ 423dea3101eS uint8_t classValid:1; /* FC Word 0, bit 31 */ 424dea3101eS 425dea3101eS #endif 426dea3101eS 427dea3101eS uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 428dea3101eS 429dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 430dea3101eS uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 431dea3101eS uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 432dea3101eS uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 433dea3101eS uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 434dea3101eS uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 435dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 436dea3101eS uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 437dea3101eS uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 438dea3101eS uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 439dea3101eS uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 440dea3101eS uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 441dea3101eS #endif 442dea3101eS 443dea3101eS uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 444dea3101eS 445dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 446dea3101eS uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 447dea3101eS uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 448dea3101eS uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 449dea3101eS uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 450dea3101eS uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 451dea3101eS uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 452dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 453dea3101eS uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 454dea3101eS uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 455dea3101eS uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 456dea3101eS uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 457dea3101eS uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 458dea3101eS uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 459dea3101eS #endif 460dea3101eS 461dea3101eS uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 462dea3101eS uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 463dea3101eS uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 464dea3101eS 465dea3101eS uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 466dea3101eS uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 467dea3101eS uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 468dea3101eS uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 469dea3101eS 470dea3101eS uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 471dea3101eS uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 472dea3101eS uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 473dea3101eS uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 474dea3101eS }; 475dea3101eS 476dea3101eS struct serv_parm { /* Structure is in Big Endian format */ 477dea3101eS struct csp cmn; 478dea3101eS struct lpfc_name portName; 479dea3101eS struct lpfc_name nodeName; 480dea3101eS struct class_parms cls1; 481dea3101eS struct class_parms cls2; 482dea3101eS struct class_parms cls3; 483dea3101eS struct class_parms cls4; 484dea3101eS uint8_t vendorVersion[16]; 485dea3101eS }; 486dea3101eS 487dea3101eS /* 488da0436e9SJames Smart * Virtual Fabric Tagging Header 489da0436e9SJames Smart */ 490da0436e9SJames Smart struct fc_vft_header { 491da0436e9SJames Smart uint32_t word0; 492da0436e9SJames Smart #define fc_vft_hdr_r_ctl_SHIFT 24 493da0436e9SJames Smart #define fc_vft_hdr_r_ctl_MASK 0xFF 494da0436e9SJames Smart #define fc_vft_hdr_r_ctl_WORD word0 495da0436e9SJames Smart #define fc_vft_hdr_ver_SHIFT 22 496da0436e9SJames Smart #define fc_vft_hdr_ver_MASK 0x3 497da0436e9SJames Smart #define fc_vft_hdr_ver_WORD word0 498da0436e9SJames Smart #define fc_vft_hdr_type_SHIFT 18 499da0436e9SJames Smart #define fc_vft_hdr_type_MASK 0xF 500da0436e9SJames Smart #define fc_vft_hdr_type_WORD word0 501da0436e9SJames Smart #define fc_vft_hdr_e_SHIFT 16 502da0436e9SJames Smart #define fc_vft_hdr_e_MASK 0x1 503da0436e9SJames Smart #define fc_vft_hdr_e_WORD word0 504da0436e9SJames Smart #define fc_vft_hdr_priority_SHIFT 13 505da0436e9SJames Smart #define fc_vft_hdr_priority_MASK 0x7 506da0436e9SJames Smart #define fc_vft_hdr_priority_WORD word0 507da0436e9SJames Smart #define fc_vft_hdr_vf_id_SHIFT 1 508da0436e9SJames Smart #define fc_vft_hdr_vf_id_MASK 0xFFF 509da0436e9SJames Smart #define fc_vft_hdr_vf_id_WORD word0 510da0436e9SJames Smart uint32_t word1; 511da0436e9SJames Smart #define fc_vft_hdr_hopct_SHIFT 24 512da0436e9SJames Smart #define fc_vft_hdr_hopct_MASK 0xFF 513da0436e9SJames Smart #define fc_vft_hdr_hopct_WORD word1 514da0436e9SJames Smart }; 515da0436e9SJames Smart 516da0436e9SJames Smart /* 517dea3101eS * Extended Link Service LS_COMMAND codes (Payload Word 0) 518dea3101eS */ 519dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 520dea3101eS #define ELS_CMD_MASK 0xffff0000 521dea3101eS #define ELS_RSP_MASK 0xff000000 522dea3101eS #define ELS_CMD_LS_RJT 0x01000000 523dea3101eS #define ELS_CMD_ACC 0x02000000 524dea3101eS #define ELS_CMD_PLOGI 0x03000000 525dea3101eS #define ELS_CMD_FLOGI 0x04000000 526dea3101eS #define ELS_CMD_LOGO 0x05000000 527dea3101eS #define ELS_CMD_ABTX 0x06000000 528dea3101eS #define ELS_CMD_RCS 0x07000000 529dea3101eS #define ELS_CMD_RES 0x08000000 530dea3101eS #define ELS_CMD_RSS 0x09000000 531dea3101eS #define ELS_CMD_RSI 0x0A000000 532dea3101eS #define ELS_CMD_ESTS 0x0B000000 533dea3101eS #define ELS_CMD_ESTC 0x0C000000 534dea3101eS #define ELS_CMD_ADVC 0x0D000000 535dea3101eS #define ELS_CMD_RTV 0x0E000000 536dea3101eS #define ELS_CMD_RLS 0x0F000000 537dea3101eS #define ELS_CMD_ECHO 0x10000000 538dea3101eS #define ELS_CMD_TEST 0x11000000 539dea3101eS #define ELS_CMD_RRQ 0x12000000 540dea3101eS #define ELS_CMD_PRLI 0x20100014 541dea3101eS #define ELS_CMD_PRLO 0x21100014 54282d9a2a2SJames Smart #define ELS_CMD_PRLO_ACC 0x02100014 543dea3101eS #define ELS_CMD_PDISC 0x50000000 544dea3101eS #define ELS_CMD_FDISC 0x51000000 545dea3101eS #define ELS_CMD_ADISC 0x52000000 546dea3101eS #define ELS_CMD_FARP 0x54000000 547dea3101eS #define ELS_CMD_FARPR 0x55000000 5487bb3b137SJamie Wellnitz #define ELS_CMD_RPS 0x56000000 5497bb3b137SJamie Wellnitz #define ELS_CMD_RPL 0x57000000 550dea3101eS #define ELS_CMD_FAN 0x60000000 551dea3101eS #define ELS_CMD_RSCN 0x61040000 552dea3101eS #define ELS_CMD_SCR 0x62000000 553dea3101eS #define ELS_CMD_RNID 0x78000000 5547bb3b137SJamie Wellnitz #define ELS_CMD_LIRR 0x7A000000 555dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 556dea3101eS #define ELS_CMD_MASK 0xffff 557dea3101eS #define ELS_RSP_MASK 0xff 558dea3101eS #define ELS_CMD_LS_RJT 0x01 559dea3101eS #define ELS_CMD_ACC 0x02 560dea3101eS #define ELS_CMD_PLOGI 0x03 561dea3101eS #define ELS_CMD_FLOGI 0x04 562dea3101eS #define ELS_CMD_LOGO 0x05 563dea3101eS #define ELS_CMD_ABTX 0x06 564dea3101eS #define ELS_CMD_RCS 0x07 565dea3101eS #define ELS_CMD_RES 0x08 566dea3101eS #define ELS_CMD_RSS 0x09 567dea3101eS #define ELS_CMD_RSI 0x0A 568dea3101eS #define ELS_CMD_ESTS 0x0B 569dea3101eS #define ELS_CMD_ESTC 0x0C 570dea3101eS #define ELS_CMD_ADVC 0x0D 571dea3101eS #define ELS_CMD_RTV 0x0E 572dea3101eS #define ELS_CMD_RLS 0x0F 573dea3101eS #define ELS_CMD_ECHO 0x10 574dea3101eS #define ELS_CMD_TEST 0x11 575dea3101eS #define ELS_CMD_RRQ 0x12 576dea3101eS #define ELS_CMD_PRLI 0x14001020 577dea3101eS #define ELS_CMD_PRLO 0x14001021 57882d9a2a2SJames Smart #define ELS_CMD_PRLO_ACC 0x14001002 579dea3101eS #define ELS_CMD_PDISC 0x50 580dea3101eS #define ELS_CMD_FDISC 0x51 581dea3101eS #define ELS_CMD_ADISC 0x52 582dea3101eS #define ELS_CMD_FARP 0x54 583dea3101eS #define ELS_CMD_FARPR 0x55 5847bb3b137SJamie Wellnitz #define ELS_CMD_RPS 0x56 5857bb3b137SJamie Wellnitz #define ELS_CMD_RPL 0x57 586dea3101eS #define ELS_CMD_FAN 0x60 587dea3101eS #define ELS_CMD_RSCN 0x0461 588dea3101eS #define ELS_CMD_SCR 0x62 589dea3101eS #define ELS_CMD_RNID 0x78 5907bb3b137SJamie Wellnitz #define ELS_CMD_LIRR 0x7A 591dea3101eS #endif 592dea3101eS 593dea3101eS /* 594dea3101eS * LS_RJT Payload Definition 595dea3101eS */ 596dea3101eS 597dea3101eS struct ls_rjt { /* Structure is in Big Endian format */ 598dea3101eS union { 599dea3101eS uint32_t lsRjtError; 600dea3101eS struct { 601dea3101eS uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 602dea3101eS 603dea3101eS uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 604dea3101eS /* LS_RJT reason codes */ 605dea3101eS #define LSRJT_INVALID_CMD 0x01 606dea3101eS #define LSRJT_LOGICAL_ERR 0x03 607dea3101eS #define LSRJT_LOGICAL_BSY 0x05 608dea3101eS #define LSRJT_PROTOCOL_ERR 0x07 609dea3101eS #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 610dea3101eS #define LSRJT_CMD_UNSUPPORTED 0x0B 611dea3101eS #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 612dea3101eS 613dea3101eS uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 614dea3101eS /* LS_RJT reason explanation */ 615dea3101eS #define LSEXP_NOTHING_MORE 0x00 616dea3101eS #define LSEXP_SPARM_OPTIONS 0x01 617dea3101eS #define LSEXP_SPARM_ICTL 0x03 618dea3101eS #define LSEXP_SPARM_RCTL 0x05 619dea3101eS #define LSEXP_SPARM_RCV_SIZE 0x07 620dea3101eS #define LSEXP_SPARM_CONCUR_SEQ 0x09 621dea3101eS #define LSEXP_SPARM_CREDIT 0x0B 622dea3101eS #define LSEXP_INVALID_PNAME 0x0D 623dea3101eS #define LSEXP_INVALID_NNAME 0x0E 624dea3101eS #define LSEXP_INVALID_CSP 0x0F 625dea3101eS #define LSEXP_INVALID_ASSOC_HDR 0x11 626dea3101eS #define LSEXP_ASSOC_HDR_REQ 0x13 627dea3101eS #define LSEXP_INVALID_O_SID 0x15 628dea3101eS #define LSEXP_INVALID_OX_RX 0x17 629dea3101eS #define LSEXP_CMD_IN_PROGRESS 0x19 6307f5f3d0dSJames Smart #define LSEXP_PORT_LOGIN_REQ 0x1E 631dea3101eS #define LSEXP_INVALID_NPORT_ID 0x1F 632dea3101eS #define LSEXP_INVALID_SEQ_ID 0x21 633dea3101eS #define LSEXP_INVALID_XCHG 0x23 634dea3101eS #define LSEXP_INACTIVE_XCHG 0x25 635dea3101eS #define LSEXP_RQ_REQUIRED 0x27 636dea3101eS #define LSEXP_OUT_OF_RESOURCE 0x29 637dea3101eS #define LSEXP_CANT_GIVE_DATA 0x2A 638dea3101eS #define LSEXP_REQ_UNSUPPORTED 0x2C 639dea3101eS uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 640dea3101eS } b; 641dea3101eS } un; 642dea3101eS }; 643dea3101eS 644dea3101eS /* 645dea3101eS * N_Port Login (FLOGO/PLOGO Request) Payload Definition 646dea3101eS */ 647dea3101eS 648dea3101eS typedef struct _LOGO { /* Structure is in Big Endian format */ 649dea3101eS union { 650dea3101eS uint32_t nPortId32; /* Access nPortId as a word */ 651dea3101eS struct { 652dea3101eS uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 653dea3101eS uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 654dea3101eS uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 655dea3101eS uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 656dea3101eS } b; 657dea3101eS } un; 658dea3101eS struct lpfc_name portName; /* N_port name field */ 659dea3101eS } LOGO; 660dea3101eS 661dea3101eS /* 662dea3101eS * FCP Login (PRLI Request / ACC) Payload Definition 663dea3101eS */ 664dea3101eS 665dea3101eS #define PRLX_PAGE_LEN 0x10 666dea3101eS #define TPRLO_PAGE_LEN 0x14 667dea3101eS 668dea3101eS typedef struct _PRLI { /* Structure is in Big Endian format */ 669dea3101eS uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 670dea3101eS 671dea3101eS #define PRLI_FCP_TYPE 0x08 672dea3101eS uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 673dea3101eS 674dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 675dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 676dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 677dea3101eS uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 678dea3101eS 679dea3101eS /* ACC = imagePairEstablished */ 680dea3101eS uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 681dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 682dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 683dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 684dea3101eS uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 685dea3101eS uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 686dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 687dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 688dea3101eS /* ACC = imagePairEstablished */ 689dea3101eS #endif 690dea3101eS 691dea3101eS #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 692dea3101eS #define PRLI_NO_RESOURCES 0x2 693dea3101eS #define PRLI_INIT_INCOMPLETE 0x3 694dea3101eS #define PRLI_NO_SUCH_PA 0x4 695dea3101eS #define PRLI_PREDEF_CONFIG 0x5 696dea3101eS #define PRLI_PARTIAL_SUCCESS 0x6 697dea3101eS #define PRLI_INVALID_PAGE_CNT 0x7 698dea3101eS uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 699dea3101eS 700dea3101eS uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 701dea3101eS 702dea3101eS uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 703dea3101eS 704dea3101eS uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 705dea3101eS uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 706dea3101eS 707dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 708dea3101eS uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 709dea3101eS uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 710dea3101eS uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 711dea3101eS uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 712dea3101eS uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 713dea3101eS uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 714dea3101eS uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 715dea3101eS uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 716dea3101eS uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 717dea3101eS uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 718dea3101eS uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 719dea3101eS uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 720dea3101eS uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 721dea3101eS uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 722dea3101eS uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 723dea3101eS uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 724dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 725dea3101eS uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 726dea3101eS uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 727dea3101eS uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 728dea3101eS uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 729dea3101eS uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 730dea3101eS uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 731dea3101eS uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 732dea3101eS uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 733dea3101eS uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 734dea3101eS uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 735dea3101eS uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 736dea3101eS uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 737dea3101eS uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 738dea3101eS uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 739dea3101eS uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 740dea3101eS uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 741dea3101eS #endif 742dea3101eS } PRLI; 743dea3101eS 744dea3101eS /* 745dea3101eS * FCP Logout (PRLO Request / ACC) Payload Definition 746dea3101eS */ 747dea3101eS 748dea3101eS typedef struct _PRLO { /* Structure is in Big Endian format */ 749dea3101eS uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 750dea3101eS 751dea3101eS #define PRLO_FCP_TYPE 0x08 752dea3101eS uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 753dea3101eS 754dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 755dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 756dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 757dea3101eS uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 758dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 759dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 760dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 761dea3101eS uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 762dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 763dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 764dea3101eS #endif 765dea3101eS 766dea3101eS #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 767dea3101eS #define PRLO_NO_SUCH_IMAGE 0x4 768dea3101eS #define PRLO_INVALID_PAGE_CNT 0x7 769dea3101eS 770dea3101eS uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 771dea3101eS 772dea3101eS uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 773dea3101eS 774dea3101eS uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 775dea3101eS 776dea3101eS uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 777dea3101eS } PRLO; 778dea3101eS 779dea3101eS typedef struct _ADISC { /* Structure is in Big Endian format */ 780dea3101eS uint32_t hardAL_PA; 781dea3101eS struct lpfc_name portName; 782dea3101eS struct lpfc_name nodeName; 783dea3101eS uint32_t DID; 784dea3101eS } ADISC; 785dea3101eS 786dea3101eS typedef struct _FARP { /* Structure is in Big Endian format */ 787dea3101eS uint32_t Mflags:8; 788dea3101eS uint32_t Odid:24; 789dea3101eS #define FARP_NO_ACTION 0 /* FARP information enclosed, no 790dea3101eS action */ 791dea3101eS #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 792dea3101eS #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 793dea3101eS #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 794dea3101eS #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 795dea3101eS supported */ 796dea3101eS #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 797dea3101eS supported */ 798dea3101eS uint32_t Rflags:8; 799dea3101eS uint32_t Rdid:24; 800dea3101eS #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 801dea3101eS #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 802dea3101eS struct lpfc_name OportName; 803dea3101eS struct lpfc_name OnodeName; 804dea3101eS struct lpfc_name RportName; 805dea3101eS struct lpfc_name RnodeName; 806dea3101eS uint8_t Oipaddr[16]; 807dea3101eS uint8_t Ripaddr[16]; 808dea3101eS } FARP; 809dea3101eS 810dea3101eS typedef struct _FAN { /* Structure is in Big Endian format */ 811dea3101eS uint32_t Fdid; 812dea3101eS struct lpfc_name FportName; 813dea3101eS struct lpfc_name FnodeName; 814dea3101eS } FAN; 815dea3101eS 816dea3101eS typedef struct _SCR { /* Structure is in Big Endian format */ 817dea3101eS uint8_t resvd1; 818dea3101eS uint8_t resvd2; 819dea3101eS uint8_t resvd3; 820dea3101eS uint8_t Function; 821dea3101eS #define SCR_FUNC_FABRIC 0x01 822dea3101eS #define SCR_FUNC_NPORT 0x02 823dea3101eS #define SCR_FUNC_FULL 0x03 824dea3101eS #define SCR_CLEAR 0xff 825dea3101eS } SCR; 826dea3101eS 827dea3101eS typedef struct _RNID_TOP_DISC { 828dea3101eS struct lpfc_name portName; 829dea3101eS uint8_t resvd[8]; 830dea3101eS uint32_t unitType; 831dea3101eS #define RNID_HBA 0x7 832dea3101eS #define RNID_HOST 0xa 833dea3101eS #define RNID_DRIVER 0xd 834dea3101eS uint32_t physPort; 835dea3101eS uint32_t attachedNodes; 836dea3101eS uint16_t ipVersion; 837dea3101eS #define RNID_IPV4 0x1 838dea3101eS #define RNID_IPV6 0x2 839dea3101eS uint16_t UDPport; 840dea3101eS uint8_t ipAddr[16]; 841dea3101eS uint16_t resvd1; 842dea3101eS uint16_t flags; 843dea3101eS #define RNID_TD_SUPPORT 0x1 844dea3101eS #define RNID_LP_VALID 0x2 845dea3101eS } RNID_TOP_DISC; 846dea3101eS 847dea3101eS typedef struct _RNID { /* Structure is in Big Endian format */ 848dea3101eS uint8_t Format; 849dea3101eS #define RNID_TOPOLOGY_DISC 0xdf 850dea3101eS uint8_t CommonLen; 851dea3101eS uint8_t resvd1; 852dea3101eS uint8_t SpecificLen; 853dea3101eS struct lpfc_name portName; 854dea3101eS struct lpfc_name nodeName; 855dea3101eS union { 856dea3101eS RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 857dea3101eS } un; 858dea3101eS } RNID; 859dea3101eS 8607bb3b137SJamie Wellnitz typedef struct _RPS { /* Structure is in Big Endian format */ 8617bb3b137SJamie Wellnitz union { 8627bb3b137SJamie Wellnitz uint32_t portNum; 8637bb3b137SJamie Wellnitz struct lpfc_name portName; 8647bb3b137SJamie Wellnitz } un; 8657bb3b137SJamie Wellnitz } RPS; 8667bb3b137SJamie Wellnitz 8677bb3b137SJamie Wellnitz typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 8687bb3b137SJamie Wellnitz uint16_t rsvd1; 8697bb3b137SJamie Wellnitz uint16_t portStatus; 8707bb3b137SJamie Wellnitz uint32_t linkFailureCnt; 8717bb3b137SJamie Wellnitz uint32_t lossSyncCnt; 8727bb3b137SJamie Wellnitz uint32_t lossSignalCnt; 8737bb3b137SJamie Wellnitz uint32_t primSeqErrCnt; 8747bb3b137SJamie Wellnitz uint32_t invalidXmitWord; 8757bb3b137SJamie Wellnitz uint32_t crcCnt; 8767bb3b137SJamie Wellnitz } RPS_RSP; 8777bb3b137SJamie Wellnitz 87812265f68SJames Smart struct RLS { /* Structure is in Big Endian format */ 87912265f68SJames Smart uint32_t rls; 88012265f68SJames Smart #define rls_rsvd_SHIFT 24 88112265f68SJames Smart #define rls_rsvd_MASK 0x000000ff 88212265f68SJames Smart #define rls_rsvd_WORD rls 88312265f68SJames Smart #define rls_did_SHIFT 0 88412265f68SJames Smart #define rls_did_MASK 0x00ffffff 88512265f68SJames Smart #define rls_did_WORD rls 88612265f68SJames Smart }; 88712265f68SJames Smart 88812265f68SJames Smart struct RLS_RSP { /* Structure is in Big Endian format */ 88912265f68SJames Smart uint32_t linkFailureCnt; 89012265f68SJames Smart uint32_t lossSyncCnt; 89112265f68SJames Smart uint32_t lossSignalCnt; 89212265f68SJames Smart uint32_t primSeqErrCnt; 89312265f68SJames Smart uint32_t invalidXmitWord; 89412265f68SJames Smart uint32_t crcCnt; 89512265f68SJames Smart }; 89612265f68SJames Smart 89719ca7609SJames Smart struct RRQ { /* Structure is in Big Endian format */ 89819ca7609SJames Smart uint32_t rrq; 89919ca7609SJames Smart #define rrq_rsvd_SHIFT 24 90019ca7609SJames Smart #define rrq_rsvd_MASK 0x000000ff 90119ca7609SJames Smart #define rrq_rsvd_WORD rrq 90219ca7609SJames Smart #define rrq_did_SHIFT 0 90319ca7609SJames Smart #define rrq_did_MASK 0x00ffffff 90419ca7609SJames Smart #define rrq_did_WORD rrq 90519ca7609SJames Smart uint32_t rrq_exchg; 90619ca7609SJames Smart #define rrq_oxid_SHIFT 16 90719ca7609SJames Smart #define rrq_oxid_MASK 0xffff 90819ca7609SJames Smart #define rrq_oxid_WORD rrq_exchg 90919ca7609SJames Smart #define rrq_rxid_SHIFT 0 91019ca7609SJames Smart #define rrq_rxid_MASK 0xffff 91119ca7609SJames Smart #define rrq_rxid_WORD rrq_exchg 91219ca7609SJames Smart }; 91319ca7609SJames Smart 914912e3acdSJames Smart #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 915912e3acdSJames Smart #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 91619ca7609SJames Smart 91712265f68SJames Smart struct RTV_RSP { /* Structure is in Big Endian format */ 91812265f68SJames Smart uint32_t ratov; 91912265f68SJames Smart uint32_t edtov; 92012265f68SJames Smart uint32_t qtov; 92112265f68SJames Smart #define qtov_rsvd0_SHIFT 28 92212265f68SJames Smart #define qtov_rsvd0_MASK 0x0000000f 92312265f68SJames Smart #define qtov_rsvd0_WORD qtov /* reserved */ 92412265f68SJames Smart #define qtov_edtovres_SHIFT 27 92512265f68SJames Smart #define qtov_edtovres_MASK 0x00000001 92612265f68SJames Smart #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 92712265f68SJames Smart #define qtov__rsvd1_SHIFT 19 92812265f68SJames Smart #define qtov_rsvd1_MASK 0x0000003f 92912265f68SJames Smart #define qtov_rsvd1_WORD qtov /* reserved */ 93012265f68SJames Smart #define qtov_rttov_SHIFT 18 93112265f68SJames Smart #define qtov_rttov_MASK 0x00000001 93212265f68SJames Smart #define qtov_rttov_WORD qtov /* R_T_TOV value */ 93312265f68SJames Smart #define qtov_rsvd2_SHIFT 0 93412265f68SJames Smart #define qtov_rsvd2_MASK 0x0003ffff 93512265f68SJames Smart #define qtov_rsvd2_WORD qtov /* reserved */ 93612265f68SJames Smart }; 93712265f68SJames Smart 93812265f68SJames Smart 9397bb3b137SJamie Wellnitz typedef struct _RPL { /* Structure is in Big Endian format */ 9407bb3b137SJamie Wellnitz uint32_t maxsize; 9417bb3b137SJamie Wellnitz uint32_t index; 9427bb3b137SJamie Wellnitz } RPL; 9437bb3b137SJamie Wellnitz 9447bb3b137SJamie Wellnitz typedef struct _PORT_NUM_BLK { 9457bb3b137SJamie Wellnitz uint32_t portNum; 9467bb3b137SJamie Wellnitz uint32_t portID; 9477bb3b137SJamie Wellnitz struct lpfc_name portName; 9487bb3b137SJamie Wellnitz } PORT_NUM_BLK; 9497bb3b137SJamie Wellnitz 9507bb3b137SJamie Wellnitz typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 9517bb3b137SJamie Wellnitz uint32_t listLen; 9527bb3b137SJamie Wellnitz uint32_t index; 9537bb3b137SJamie Wellnitz PORT_NUM_BLK port_num_blk; 9547bb3b137SJamie Wellnitz } RPL_RSP; 955dea3101eS 956dea3101eS /* This is used for RSCN command */ 957dea3101eS typedef struct _D_ID { /* Structure is in Big Endian format */ 958dea3101eS union { 959dea3101eS uint32_t word; 960dea3101eS struct { 961dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 962dea3101eS uint8_t resv; 963dea3101eS uint8_t domain; 964dea3101eS uint8_t area; 965dea3101eS uint8_t id; 966dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 967dea3101eS uint8_t id; 968dea3101eS uint8_t area; 969dea3101eS uint8_t domain; 970dea3101eS uint8_t resv; 971dea3101eS #endif 972dea3101eS } b; 973dea3101eS } un; 974dea3101eS } D_ID; 975dea3101eS 976eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_PORT 0x0 977eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_AREA 0x1 978eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 979eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 980eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_MASK 0x3 981eaf15d5bSJames Smart 982dea3101eS /* 983dea3101eS * Structure to define all ELS Payload types 984dea3101eS */ 985dea3101eS 986dea3101eS typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 987dea3101eS uint8_t elsCode; /* FC Word 0, bit 24:31 */ 988dea3101eS uint8_t elsByte1; 989dea3101eS uint8_t elsByte2; 990dea3101eS uint8_t elsByte3; 991dea3101eS union { 992dea3101eS struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 993dea3101eS struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 994dea3101eS LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 995dea3101eS PRLI prli; /* Payload for PRLI/ACC */ 996dea3101eS PRLO prlo; /* Payload for PRLO/ACC */ 997dea3101eS ADISC adisc; /* Payload for ADISC/ACC */ 998dea3101eS FARP farp; /* Payload for FARP/ACC */ 999dea3101eS FAN fan; /* Payload for FAN */ 1000dea3101eS SCR scr; /* Payload for SCR/ACC */ 1001dea3101eS RNID rnid; /* Payload for RNID */ 1002dea3101eS uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1003dea3101eS } un; 1004dea3101eS } ELS_PKT; 1005dea3101eS 1006dea3101eS /* 1007dea3101eS * FDMI 1008dea3101eS * HBA MAnagement Operations Command Codes 1009dea3101eS */ 1010dea3101eS #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1011dea3101eS #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1012dea3101eS #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1013dea3101eS #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1014dea3101eS #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 101570f23fd6SJustin P. Mattock #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1016dea3101eS #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1017dea3101eS #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1018dea3101eS #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1019dea3101eS #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1020dea3101eS 1021dea3101eS /* 1022dea3101eS * Management Service Subtypes 1023dea3101eS */ 1024dea3101eS #define SLI_CT_FDMI_Subtypes 0x10 1025dea3101eS 1026dea3101eS /* 1027dea3101eS * HBA Management Service Reject Code 1028dea3101eS */ 1029dea3101eS #define REJECT_CODE 0x9 /* Unable to perform command request */ 1030dea3101eS 1031dea3101eS /* 1032dea3101eS * HBA Management Service Reject Reason Code 1033dea3101eS * Please refer to the Reason Codes above 1034dea3101eS */ 1035dea3101eS 1036dea3101eS /* 1037dea3101eS * HBA Attribute Types 1038dea3101eS */ 1039dea3101eS #define NODE_NAME 0x1 1040dea3101eS #define MANUFACTURER 0x2 1041dea3101eS #define SERIAL_NUMBER 0x3 1042dea3101eS #define MODEL 0x4 1043dea3101eS #define MODEL_DESCRIPTION 0x5 1044dea3101eS #define HARDWARE_VERSION 0x6 1045dea3101eS #define DRIVER_VERSION 0x7 1046dea3101eS #define OPTION_ROM_VERSION 0x8 1047dea3101eS #define FIRMWARE_VERSION 0x9 1048dea3101eS #define OS_NAME_VERSION 0xa 1049dea3101eS #define MAX_CT_PAYLOAD_LEN 0xb 1050dea3101eS 1051dea3101eS /* 1052dea3101eS * Port Attrubute Types 1053dea3101eS */ 1054dea3101eS #define SUPPORTED_FC4_TYPES 0x1 1055dea3101eS #define SUPPORTED_SPEED 0x2 1056dea3101eS #define PORT_SPEED 0x3 1057dea3101eS #define MAX_FRAME_SIZE 0x4 1058dea3101eS #define OS_DEVICE_NAME 0x5 1059dea3101eS #define HOST_NAME 0x6 1060dea3101eS 1061dea3101eS union AttributesDef { 1062dea3101eS /* Structure is in Big Endian format */ 1063dea3101eS struct { 1064dea3101eS uint32_t AttrType:16; 1065dea3101eS uint32_t AttrLen:16; 1066dea3101eS } bits; 1067dea3101eS uint32_t word; 1068dea3101eS }; 1069dea3101eS 1070dea3101eS 1071dea3101eS /* 1072dea3101eS * HBA Attribute Entry (8 - 260 bytes) 1073dea3101eS */ 1074dea3101eS typedef struct { 1075dea3101eS union AttributesDef ad; 1076dea3101eS union { 1077dea3101eS uint32_t VendorSpecific; 1078dea3101eS uint8_t Manufacturer[64]; 1079dea3101eS uint8_t SerialNumber[64]; 1080dea3101eS uint8_t Model[256]; 1081dea3101eS uint8_t ModelDescription[256]; 1082dea3101eS uint8_t HardwareVersion[256]; 1083dea3101eS uint8_t DriverVersion[256]; 1084dea3101eS uint8_t OptionROMVersion[256]; 1085dea3101eS uint8_t FirmwareVersion[256]; 1086dea3101eS struct lpfc_name NodeName; 1087dea3101eS uint8_t SupportFC4Types[32]; 1088dea3101eS uint32_t SupportSpeed; 1089dea3101eS uint32_t PortSpeed; 1090dea3101eS uint32_t MaxFrameSize; 1091dea3101eS uint8_t OsDeviceName[256]; 1092dea3101eS uint8_t OsNameVersion[256]; 1093dea3101eS uint32_t MaxCTPayloadLen; 1094dea3101eS uint8_t HostName[256]; 1095dea3101eS } un; 1096dea3101eS } ATTRIBUTE_ENTRY; 1097dea3101eS 1098dea3101eS /* 1099dea3101eS * HBA Attribute Block 1100dea3101eS */ 1101dea3101eS typedef struct { 1102dea3101eS uint32_t EntryCnt; /* Number of HBA attribute entries */ 1103dea3101eS ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 1104dea3101eS } ATTRIBUTE_BLOCK; 1105dea3101eS 1106dea3101eS /* 1107dea3101eS * Port Entry 1108dea3101eS */ 1109dea3101eS typedef struct { 1110dea3101eS struct lpfc_name PortName; 1111dea3101eS } PORT_ENTRY; 1112dea3101eS 1113dea3101eS /* 1114dea3101eS * HBA Identifier 1115dea3101eS */ 1116dea3101eS typedef struct { 1117dea3101eS struct lpfc_name PortName; 1118dea3101eS } HBA_IDENTIFIER; 1119dea3101eS 1120dea3101eS /* 1121dea3101eS * Registered Port List Format 1122dea3101eS */ 1123dea3101eS typedef struct { 1124dea3101eS uint32_t EntryCnt; 1125dea3101eS PORT_ENTRY pe; /* Variable-length array */ 1126dea3101eS } REG_PORT_LIST; 1127dea3101eS 1128dea3101eS /* 1129dea3101eS * Register HBA(RHBA) 1130dea3101eS */ 1131dea3101eS typedef struct { 1132dea3101eS HBA_IDENTIFIER hi; 1133dea3101eS REG_PORT_LIST rpl; /* variable-length array */ 1134dea3101eS /* ATTRIBUTE_BLOCK ab; */ 1135dea3101eS } REG_HBA; 1136dea3101eS 1137dea3101eS /* 1138dea3101eS * Register HBA Attributes (RHAT) 1139dea3101eS */ 1140dea3101eS typedef struct { 1141dea3101eS struct lpfc_name HBA_PortName; 1142dea3101eS ATTRIBUTE_BLOCK ab; 1143dea3101eS } REG_HBA_ATTRIBUTE; 1144dea3101eS 1145dea3101eS /* 1146dea3101eS * Register Port Attributes (RPA) 1147dea3101eS */ 1148dea3101eS typedef struct { 1149dea3101eS struct lpfc_name PortName; 1150dea3101eS ATTRIBUTE_BLOCK ab; 1151dea3101eS } REG_PORT_ATTRIBUTE; 1152dea3101eS 1153dea3101eS /* 1154dea3101eS * Get Registered HBA List (GRHL) Accept Payload Format 1155dea3101eS */ 1156dea3101eS typedef struct { 1157dea3101eS uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 1158dea3101eS struct lpfc_name HBA_PortName; /* Variable-length array */ 1159dea3101eS } GRHL_ACC_PAYLOAD; 1160dea3101eS 1161dea3101eS /* 1162dea3101eS * Get Registered Port List (GRPL) Accept Payload Format 1163dea3101eS */ 1164dea3101eS typedef struct { 1165dea3101eS uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 1166dea3101eS PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 1167dea3101eS } GRPL_ACC_PAYLOAD; 1168dea3101eS 1169dea3101eS /* 1170dea3101eS * Get Port Attributes (GPAT) Accept Payload Format 1171dea3101eS */ 1172dea3101eS 1173dea3101eS typedef struct { 1174dea3101eS ATTRIBUTE_BLOCK pab; 1175dea3101eS } GPAT_ACC_PAYLOAD; 1176dea3101eS 1177dea3101eS 1178dea3101eS /* 1179dea3101eS * Begin HBA configuration parameters. 1180dea3101eS * The PCI configuration register BAR assignments are: 1181dea3101eS * BAR0, offset 0x10 - SLIM base memory address 1182dea3101eS * BAR1, offset 0x14 - SLIM base memory high address 1183dea3101eS * BAR2, offset 0x18 - REGISTER base memory address 1184dea3101eS * BAR3, offset 0x1c - REGISTER base memory high address 1185dea3101eS * BAR4, offset 0x20 - BIU I/O registers 1186dea3101eS * BAR5, offset 0x24 - REGISTER base io high address 1187dea3101eS */ 1188dea3101eS 1189dea3101eS /* Number of rings currently used and available. */ 1190dea3101eS #define MAX_CONFIGURED_RINGS 3 1191dea3101eS #define MAX_RINGS 4 1192dea3101eS 1193dea3101eS /* IOCB / Mailbox is owned by FireFly */ 1194dea3101eS #define OWN_CHIP 1 1195dea3101eS 1196dea3101eS /* IOCB / Mailbox is owned by Host */ 1197dea3101eS #define OWN_HOST 0 1198dea3101eS 1199dea3101eS /* Number of 4-byte words in an IOCB. */ 1200dea3101eS #define IOCB_WORD_SZ 8 1201dea3101eS 1202dea3101eS /* network headers for Dfctl field */ 1203dea3101eS #define FC_NET_HDR 0x20 1204dea3101eS 1205dea3101eS /* Start FireFly Register definitions */ 1206dea3101eS #define PCI_VENDOR_ID_EMULEX 0x10df 1207dea3101eS #define PCI_DEVICE_ID_FIREFLY 0x1ae5 120884774a4dSJames Smart #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1209085c647cSJames Smart #define PCI_DEVICE_ID_BALIUS 0xe131 121084774a4dSJames Smart #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1211085c647cSJames Smart #define PCI_DEVICE_ID_LANCER_FC 0xe200 1212c0c11512SJames Smart #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1213085c647cSJames Smart #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1214c0c11512SJames Smart #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1215b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_SMB 0xf011 1216b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_MID 0xf015 1217dea3101eS #define PCI_DEVICE_ID_RFLY 0xf095 1218dea3101eS #define PCI_DEVICE_ID_PFLY 0xf098 1219e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_LP101 0xf0a1 1220dea3101eS #define PCI_DEVICE_ID_TFLY 0xf0a5 1221e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_BSMB 0xf0d1 1222e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_BMID 0xf0d5 1223e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZSMB 0xf0e1 1224e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZMID 0xf0e5 1225e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1226e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1227e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1228b87eab38SJames Smart #define PCI_DEVICE_ID_SAT 0xf100 1229b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1230b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1231085c647cSJames Smart #define PCI_DEVICE_ID_FALCON 0xf180 1232e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_SUPERFLY 0xf700 1233e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1234dea3101eS #define PCI_DEVICE_ID_CENTAUR 0xf900 1235dea3101eS #define PCI_DEVICE_ID_PEGASUS 0xf980 1236dea3101eS #define PCI_DEVICE_ID_THOR 0xfa00 1237dea3101eS #define PCI_DEVICE_ID_VIPER 0xfb00 1238dea3101eS #define PCI_DEVICE_ID_LP10000S 0xfc00 1239e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_LP11000S 0xfc10 1240e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_LPE11000S 0xfc20 1241b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_S 0xfc40 124284774a4dSJames Smart #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1243e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_HELIOS 0xfd00 1244e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1245e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1246e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZEPHYR 0xfe00 124784774a4dSJames Smart #define PCI_DEVICE_ID_HORNET 0xfe05 1248e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1249e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1250da0436e9SJames Smart #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1251da0436e9SJames Smart #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1252a747c9ceSJames Smart #define PCI_DEVICE_ID_TOMCAT 0x0714 1253dea3101eS 1254dea3101eS #define JEDEC_ID_ADDRESS 0x0080001c 1255dea3101eS #define FIREFLY_JEDEC_ID 0x1ACC 1256dea3101eS #define SUPERFLY_JEDEC_ID 0x0020 1257dea3101eS #define DRAGONFLY_JEDEC_ID 0x0021 1258dea3101eS #define DRAGONFLY_V2_JEDEC_ID 0x0025 1259dea3101eS #define CENTAUR_2G_JEDEC_ID 0x0026 1260dea3101eS #define CENTAUR_1G_JEDEC_ID 0x0028 1261dea3101eS #define PEGASUS_ORION_JEDEC_ID 0x0036 1262dea3101eS #define PEGASUS_JEDEC_ID 0x0038 1263dea3101eS #define THOR_JEDEC_ID 0x0012 1264dea3101eS #define HELIOS_JEDEC_ID 0x0364 1265dea3101eS #define ZEPHYR_JEDEC_ID 0x0577 1266dea3101eS #define VIPER_JEDEC_ID 0x4838 1267b87eab38SJames Smart #define SATURN_JEDEC_ID 0x1004 126884774a4dSJames Smart #define HORNET_JDEC_ID 0x2057706D 1269dea3101eS 1270dea3101eS #define JEDEC_ID_MASK 0x0FFFF000 1271dea3101eS #define JEDEC_ID_SHIFT 12 1272dea3101eS #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1273dea3101eS 1274dea3101eS typedef struct { /* FireFly BIU registers */ 1275dea3101eS uint32_t hostAtt; /* See definitions for Host Attention 1276dea3101eS register */ 1277dea3101eS uint32_t chipAtt; /* See definitions for Chip Attention 1278dea3101eS register */ 1279dea3101eS uint32_t hostStatus; /* See definitions for Host Status register */ 1280dea3101eS uint32_t hostControl; /* See definitions for Host Control register */ 1281dea3101eS uint32_t buiConfig; /* See definitions for BIU configuration 1282dea3101eS register */ 1283dea3101eS } FF_REGS; 1284dea3101eS 1285dea3101eS /* IO Register size in bytes */ 1286dea3101eS #define FF_REG_AREA_SIZE 256 1287dea3101eS 1288dea3101eS /* Host Attention Register */ 1289dea3101eS 1290dea3101eS #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1291dea3101eS 1292dea3101eS #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1293dea3101eS #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1294dea3101eS #define HA_R0ATT 0x00000008 /* Bit 3 */ 1295dea3101eS #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1296dea3101eS #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1297dea3101eS #define HA_R1ATT 0x00000080 /* Bit 7 */ 1298dea3101eS #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1299dea3101eS #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1300dea3101eS #define HA_R2ATT 0x00000800 /* Bit 11 */ 1301dea3101eS #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1302dea3101eS #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1303dea3101eS #define HA_R3ATT 0x00008000 /* Bit 15 */ 1304dea3101eS #define HA_LATT 0x20000000 /* Bit 29 */ 1305dea3101eS #define HA_MBATT 0x40000000 /* Bit 30 */ 1306dea3101eS #define HA_ERATT 0x80000000 /* Bit 31 */ 1307dea3101eS 1308dea3101eS #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1309dea3101eS #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1310dea3101eS #define HA_RXATT 0x00000008 /* Bit 3 */ 1311dea3101eS #define HA_RXMASK 0x0000000f 1312dea3101eS 13139399627fSJames Smart #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 13149399627fSJames Smart #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 13159399627fSJames Smart #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 13169399627fSJames Smart #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 13179399627fSJames Smart 13189399627fSJames Smart #define HA_R0_POS 3 13199399627fSJames Smart #define HA_R1_POS 7 13209399627fSJames Smart #define HA_R2_POS 11 13219399627fSJames Smart #define HA_R3_POS 15 13229399627fSJames Smart #define HA_LE_POS 29 13239399627fSJames Smart #define HA_MB_POS 30 13249399627fSJames Smart #define HA_ER_POS 31 1325dea3101eS /* Chip Attention Register */ 1326dea3101eS 1327dea3101eS #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1328dea3101eS 1329dea3101eS #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1330dea3101eS #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1331dea3101eS #define CA_R0ATT 0x00000008 /* Bit 3 */ 1332dea3101eS #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1333dea3101eS #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1334dea3101eS #define CA_R1ATT 0x00000080 /* Bit 7 */ 1335dea3101eS #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1336dea3101eS #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1337dea3101eS #define CA_R2ATT 0x00000800 /* Bit 11 */ 1338dea3101eS #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1339dea3101eS #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1340dea3101eS #define CA_R3ATT 0x00008000 /* Bit 15 */ 1341dea3101eS #define CA_MBATT 0x40000000 /* Bit 30 */ 1342dea3101eS 1343dea3101eS /* Host Status Register */ 1344dea3101eS 1345dea3101eS #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1346dea3101eS 1347dea3101eS #define HS_MBRDY 0x00400000 /* Bit 22 */ 1348dea3101eS #define HS_FFRDY 0x00800000 /* Bit 23 */ 1349dea3101eS #define HS_FFER8 0x01000000 /* Bit 24 */ 1350dea3101eS #define HS_FFER7 0x02000000 /* Bit 25 */ 1351dea3101eS #define HS_FFER6 0x04000000 /* Bit 26 */ 1352dea3101eS #define HS_FFER5 0x08000000 /* Bit 27 */ 1353dea3101eS #define HS_FFER4 0x10000000 /* Bit 28 */ 1354dea3101eS #define HS_FFER3 0x20000000 /* Bit 29 */ 1355dea3101eS #define HS_FFER2 0x40000000 /* Bit 30 */ 1356dea3101eS #define HS_FFER1 0x80000000 /* Bit 31 */ 135757127f15SJames Smart #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 135857127f15SJames Smart #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 13599940b97bSJames Smart #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1360dea3101eS /* Host Control Register */ 1361dea3101eS 13629399627fSJames Smart #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1363dea3101eS 1364dea3101eS #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1365dea3101eS #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1366dea3101eS #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1367dea3101eS #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1368dea3101eS #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1369dea3101eS #define HC_INITHBI 0x02000000 /* Bit 25 */ 1370dea3101eS #define HC_INITMB 0x04000000 /* Bit 26 */ 1371dea3101eS #define HC_INITFF 0x08000000 /* Bit 27 */ 1372dea3101eS #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1373dea3101eS #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1374dea3101eS 13759399627fSJames Smart /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 13769399627fSJames Smart #define MSIX_DFLT_ID 0 13779399627fSJames Smart #define MSIX_RNG0_ID 0 13789399627fSJames Smart #define MSIX_RNG1_ID 1 13799399627fSJames Smart #define MSIX_RNG2_ID 2 13809399627fSJames Smart #define MSIX_RNG3_ID 3 13819399627fSJames Smart 13829399627fSJames Smart #define MSIX_LINK_ID 4 13839399627fSJames Smart #define MSIX_MBOX_ID 5 13849399627fSJames Smart 13859399627fSJames Smart #define MSIX_SPARE0_ID 6 13869399627fSJames Smart #define MSIX_SPARE1_ID 7 13879399627fSJames Smart 1388dea3101eS /* Mailbox Commands */ 1389dea3101eS #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1390dea3101eS #define MBX_LOAD_SM 0x01 1391dea3101eS #define MBX_READ_NV 0x02 1392dea3101eS #define MBX_WRITE_NV 0x03 1393dea3101eS #define MBX_RUN_BIU_DIAG 0x04 1394dea3101eS #define MBX_INIT_LINK 0x05 1395dea3101eS #define MBX_DOWN_LINK 0x06 1396dea3101eS #define MBX_CONFIG_LINK 0x07 1397dea3101eS #define MBX_CONFIG_RING 0x09 1398dea3101eS #define MBX_RESET_RING 0x0A 1399dea3101eS #define MBX_READ_CONFIG 0x0B 1400dea3101eS #define MBX_READ_RCONFIG 0x0C 1401dea3101eS #define MBX_READ_SPARM 0x0D 1402dea3101eS #define MBX_READ_STATUS 0x0E 1403dea3101eS #define MBX_READ_RPI 0x0F 1404dea3101eS #define MBX_READ_XRI 0x10 1405dea3101eS #define MBX_READ_REV 0x11 1406dea3101eS #define MBX_READ_LNK_STAT 0x12 1407dea3101eS #define MBX_REG_LOGIN 0x13 1408dea3101eS #define MBX_UNREG_LOGIN 0x14 1409dea3101eS #define MBX_CLEAR_LA 0x16 1410dea3101eS #define MBX_DUMP_MEMORY 0x17 1411dea3101eS #define MBX_DUMP_CONTEXT 0x18 1412dea3101eS #define MBX_RUN_DIAGS 0x19 1413dea3101eS #define MBX_RESTART 0x1A 1414dea3101eS #define MBX_UPDATE_CFG 0x1B 1415dea3101eS #define MBX_DOWN_LOAD 0x1C 1416dea3101eS #define MBX_DEL_LD_ENTRY 0x1D 1417dea3101eS #define MBX_RUN_PROGRAM 0x1E 1418dea3101eS #define MBX_SET_MASK 0x20 141909372820SJames Smart #define MBX_SET_VARIABLE 0x21 1420dea3101eS #define MBX_UNREG_D_ID 0x23 142141415862SJamie Wellnitz #define MBX_KILL_BOARD 0x24 1422dea3101eS #define MBX_CONFIG_FARP 0x25 142341415862SJamie Wellnitz #define MBX_BEACON 0x2A 14249399627fSJames Smart #define MBX_CONFIG_MSI 0x30 1425858c9f6cSJames Smart #define MBX_HEARTBEAT 0x31 1426a8adb832SJames Smart #define MBX_WRITE_VPARMS 0x32 1427a8adb832SJames Smart #define MBX_ASYNCEVT_ENABLE 0x33 14284fede78fSJames Smart #define MBX_READ_EVENT_LOG_STATUS 0x37 14294fede78fSJames Smart #define MBX_READ_EVENT_LOG 0x38 14304fede78fSJames Smart #define MBX_WRITE_EVENT_LOG 0x39 1431dea3101eS 143284774a4dSJames Smart #define MBX_PORT_CAPABILITIES 0x3B 143384774a4dSJames Smart #define MBX_PORT_IOV_CONTROL 0x3C 143484774a4dSJames Smart 1435ed957684SJames Smart #define MBX_CONFIG_HBQ 0x7C 1436dea3101eS #define MBX_LOAD_AREA 0x81 1437dea3101eS #define MBX_RUN_BIU_DIAG64 0x84 1438dea3101eS #define MBX_CONFIG_PORT 0x88 1439dea3101eS #define MBX_READ_SPARM64 0x8D 1440dea3101eS #define MBX_READ_RPI64 0x8F 1441dea3101eS #define MBX_REG_LOGIN64 0x93 144276a95d75SJames Smart #define MBX_READ_TOPOLOGY 0x95 144392d7f7b0SJames Smart #define MBX_REG_VPI 0x96 144492d7f7b0SJames Smart #define MBX_UNREG_VPI 0x97 1445dea3101eS 144609372820SJames Smart #define MBX_WRITE_WWN 0x98 1447dea3101eS #define MBX_SET_DEBUG 0x99 1448dea3101eS #define MBX_LOAD_EXP_ROM 0x9C 1449da0436e9SJames Smart #define MBX_SLI4_CONFIG 0x9B 1450da0436e9SJames Smart #define MBX_SLI4_REQ_FTRS 0x9D 1451da0436e9SJames Smart #define MBX_MAX_CMDS 0x9E 1452da0436e9SJames Smart #define MBX_RESUME_RPI 0x9E 1453dea3101eS #define MBX_SLI2_CMD_MASK 0x80 1454da0436e9SJames Smart #define MBX_REG_VFI 0x9F 1455da0436e9SJames Smart #define MBX_REG_FCFI 0xA0 1456da0436e9SJames Smart #define MBX_UNREG_VFI 0xA1 1457da0436e9SJames Smart #define MBX_UNREG_FCFI 0xA2 1458da0436e9SJames Smart #define MBX_INIT_VFI 0xA3 1459da0436e9SJames Smart #define MBX_INIT_VPI 0xA4 1460dea3101eS 1461dcf2a4e0SJames Smart #define MBX_AUTH_PORT 0xF8 1462dcf2a4e0SJames Smart #define MBX_SECURITY_MGMT 0xF9 1463dcf2a4e0SJames Smart 1464dea3101eS /* IOCB Commands */ 1465dea3101eS 1466dea3101eS #define CMD_RCV_SEQUENCE_CX 0x01 1467dea3101eS #define CMD_XMIT_SEQUENCE_CR 0x02 1468dea3101eS #define CMD_XMIT_SEQUENCE_CX 0x03 1469dea3101eS #define CMD_XMIT_BCAST_CN 0x04 1470dea3101eS #define CMD_XMIT_BCAST_CX 0x05 1471dea3101eS #define CMD_QUE_RING_BUF_CN 0x06 1472dea3101eS #define CMD_QUE_XRI_BUF_CX 0x07 1473dea3101eS #define CMD_IOCB_CONTINUE_CN 0x08 1474dea3101eS #define CMD_RET_XRI_BUF_CX 0x09 1475dea3101eS #define CMD_ELS_REQUEST_CR 0x0A 1476dea3101eS #define CMD_ELS_REQUEST_CX 0x0B 1477dea3101eS #define CMD_RCV_ELS_REQ_CX 0x0D 1478dea3101eS #define CMD_ABORT_XRI_CN 0x0E 1479dea3101eS #define CMD_ABORT_XRI_CX 0x0F 1480dea3101eS #define CMD_CLOSE_XRI_CN 0x10 1481dea3101eS #define CMD_CLOSE_XRI_CX 0x11 1482dea3101eS #define CMD_CREATE_XRI_CR 0x12 1483dea3101eS #define CMD_CREATE_XRI_CX 0x13 1484dea3101eS #define CMD_GET_RPI_CN 0x14 1485dea3101eS #define CMD_XMIT_ELS_RSP_CX 0x15 1486dea3101eS #define CMD_GET_RPI_CR 0x16 1487dea3101eS #define CMD_XRI_ABORTED_CX 0x17 1488dea3101eS #define CMD_FCP_IWRITE_CR 0x18 1489dea3101eS #define CMD_FCP_IWRITE_CX 0x19 1490dea3101eS #define CMD_FCP_IREAD_CR 0x1A 1491dea3101eS #define CMD_FCP_IREAD_CX 0x1B 1492dea3101eS #define CMD_FCP_ICMND_CR 0x1C 1493dea3101eS #define CMD_FCP_ICMND_CX 0x1D 1494f5603511SJames Smart #define CMD_FCP_TSEND_CX 0x1F 1495f5603511SJames Smart #define CMD_FCP_TRECEIVE_CX 0x21 1496f5603511SJames Smart #define CMD_FCP_TRSP_CX 0x23 1497f5603511SJames Smart #define CMD_FCP_AUTO_TRSP_CX 0x29 1498dea3101eS 1499dea3101eS #define CMD_ADAPTER_MSG 0x20 1500dea3101eS #define CMD_ADAPTER_DUMP 0x22 1501dea3101eS 1502dea3101eS /* SLI_2 IOCB Command Set */ 1503dea3101eS 150457127f15SJames Smart #define CMD_ASYNC_STATUS 0x7C 1505dea3101eS #define CMD_RCV_SEQUENCE64_CX 0x81 1506dea3101eS #define CMD_XMIT_SEQUENCE64_CR 0x82 1507dea3101eS #define CMD_XMIT_SEQUENCE64_CX 0x83 1508dea3101eS #define CMD_XMIT_BCAST64_CN 0x84 1509dea3101eS #define CMD_XMIT_BCAST64_CX 0x85 1510dea3101eS #define CMD_QUE_RING_BUF64_CN 0x86 1511dea3101eS #define CMD_QUE_XRI_BUF64_CX 0x87 1512dea3101eS #define CMD_IOCB_CONTINUE64_CN 0x88 1513dea3101eS #define CMD_RET_XRI_BUF64_CX 0x89 1514dea3101eS #define CMD_ELS_REQUEST64_CR 0x8A 1515dea3101eS #define CMD_ELS_REQUEST64_CX 0x8B 1516dea3101eS #define CMD_ABORT_MXRI64_CN 0x8C 1517dea3101eS #define CMD_RCV_ELS_REQ64_CX 0x8D 1518dea3101eS #define CMD_XMIT_ELS_RSP64_CX 0x95 15196669f9bbSJames Smart #define CMD_XMIT_BLS_RSP64_CX 0x97 1520dea3101eS #define CMD_FCP_IWRITE64_CR 0x98 1521dea3101eS #define CMD_FCP_IWRITE64_CX 0x99 1522dea3101eS #define CMD_FCP_IREAD64_CR 0x9A 1523dea3101eS #define CMD_FCP_IREAD64_CX 0x9B 1524dea3101eS #define CMD_FCP_ICMND64_CR 0x9C 1525dea3101eS #define CMD_FCP_ICMND64_CX 0x9D 1526f5603511SJames Smart #define CMD_FCP_TSEND64_CX 0x9F 1527f5603511SJames Smart #define CMD_FCP_TRECEIVE64_CX 0xA1 1528f5603511SJames Smart #define CMD_FCP_TRSP64_CX 0xA3 1529dea3101eS 153076bb24efSJames Smart #define CMD_QUE_XRI64_CX 0xB3 1531ed957684SJames Smart #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1532ed957684SJames Smart #define CMD_IOCB_RCV_ELS64_CX 0xB7 15333163f725SJames Smart #define CMD_IOCB_RET_XRI64_CX 0xB9 1534ed957684SJames Smart #define CMD_IOCB_RCV_CONT64_CX 0xBB 1535ed957684SJames Smart 1536dea3101eS #define CMD_GEN_REQUEST64_CR 0xC2 1537dea3101eS #define CMD_GEN_REQUEST64_CX 0xC3 1538dea3101eS 15393163f725SJames Smart /* Unhandled SLI-3 Commands */ 15403163f725SJames Smart #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 15413163f725SJames Smart #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 15423163f725SJames Smart #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 15433163f725SJames Smart #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 15443163f725SJames Smart #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 15453163f725SJames Smart #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 15463163f725SJames Smart #define CMD_IOCB_RET_HBQE64_CN 0xCA 15473163f725SJames Smart #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 15483163f725SJames Smart #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 15493163f725SJames Smart #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 15503163f725SJames Smart #define CMD_IOCB_LOGENTRY_CN 0x94 15513163f725SJames Smart #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 15523163f725SJames Smart 1553341af102SJames Smart /* Data Security SLI Commands */ 1554341af102SJames Smart #define DSSCMD_IWRITE64_CR 0xF8 1555341af102SJames Smart #define DSSCMD_IWRITE64_CX 0xF9 1556341af102SJames Smart #define DSSCMD_IREAD64_CR 0xFA 1557341af102SJames Smart #define DSSCMD_IREAD64_CX 0xFB 1558da0436e9SJames Smart 1559341af102SJames Smart #define CMD_MAX_IOCB_CMD 0xFB 1560dea3101eS #define CMD_IOCB_MASK 0xff 1561dea3101eS 1562dea3101eS #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1563dea3101eS iocb */ 1564dea3101eS #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1565dea3101eS /* 1566dea3101eS * Define Status 1567dea3101eS */ 1568dea3101eS #define MBX_SUCCESS 0 1569dea3101eS #define MBXERR_NUM_RINGS 1 1570dea3101eS #define MBXERR_NUM_IOCBS 2 1571dea3101eS #define MBXERR_IOCBS_EXCEEDED 3 1572dea3101eS #define MBXERR_BAD_RING_NUMBER 4 1573dea3101eS #define MBXERR_MASK_ENTRIES_RANGE 5 1574dea3101eS #define MBXERR_MASKS_EXCEEDED 6 1575dea3101eS #define MBXERR_BAD_PROFILE 7 1576dea3101eS #define MBXERR_BAD_DEF_CLASS 8 1577dea3101eS #define MBXERR_BAD_MAX_RESPONDER 9 1578dea3101eS #define MBXERR_BAD_MAX_ORIGINATOR 10 1579dea3101eS #define MBXERR_RPI_REGISTERED 11 1580dea3101eS #define MBXERR_RPI_FULL 12 1581dea3101eS #define MBXERR_NO_RESOURCES 13 1582dea3101eS #define MBXERR_BAD_RCV_LENGTH 14 1583dea3101eS #define MBXERR_DMA_ERROR 15 1584dea3101eS #define MBXERR_ERROR 16 1585da0436e9SJames Smart #define MBXERR_LINK_DOWN 0x33 1586dcf2a4e0SJames Smart #define MBXERR_SEC_NO_PERMISSION 0xF02 1587dea3101eS #define MBX_NOT_FINISHED 255 1588dea3101eS 1589dea3101eS #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1590dea3101eS #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1591dea3101eS 159257127f15SJames Smart #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 159357127f15SJames Smart 1594dea3101eS /* 1595dea3101eS * Begin Structure Definitions for Mailbox Commands 1596dea3101eS */ 1597dea3101eS 1598dea3101eS typedef struct { 1599dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1600dea3101eS uint8_t tval; 1601dea3101eS uint8_t tmask; 1602dea3101eS uint8_t rval; 1603dea3101eS uint8_t rmask; 1604dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1605dea3101eS uint8_t rmask; 1606dea3101eS uint8_t rval; 1607dea3101eS uint8_t tmask; 1608dea3101eS uint8_t tval; 1609dea3101eS #endif 1610dea3101eS } RR_REG; 1611dea3101eS 1612dea3101eS struct ulp_bde { 1613dea3101eS uint32_t bdeAddress; 1614dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1615dea3101eS uint32_t bdeReserved:4; 1616dea3101eS uint32_t bdeAddrHigh:4; 1617dea3101eS uint32_t bdeSize:24; 1618dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1619dea3101eS uint32_t bdeSize:24; 1620dea3101eS uint32_t bdeAddrHigh:4; 1621dea3101eS uint32_t bdeReserved:4; 1622dea3101eS #endif 1623dea3101eS }; 1624dea3101eS 1625dea3101eS typedef struct ULP_BDL { /* SLI-2 */ 1626dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1627dea3101eS uint32_t bdeFlags:8; /* BDL Flags */ 1628dea3101eS uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1629dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1630dea3101eS uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1631dea3101eS uint32_t bdeFlags:8; /* BDL Flags */ 1632dea3101eS #endif 1633dea3101eS 1634dea3101eS uint32_t addrLow; /* Address 0:31 */ 1635dea3101eS uint32_t addrHigh; /* Address 32:63 */ 1636dea3101eS uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1637dea3101eS } ULP_BDL; 1638dea3101eS 163981301a9bSJames Smart /* 164081301a9bSJames Smart * BlockGuard Definitions 164181301a9bSJames Smart */ 164281301a9bSJames Smart 164381301a9bSJames Smart enum lpfc_protgrp_type { 164481301a9bSJames Smart LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 164581301a9bSJames Smart LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 164681301a9bSJames Smart LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 164781301a9bSJames Smart LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 164881301a9bSJames Smart }; 164981301a9bSJames Smart 165081301a9bSJames Smart /* PDE Descriptors */ 16516c8eea54SJames Smart #define LPFC_PDE5_DESCRIPTOR 0x85 16526c8eea54SJames Smart #define LPFC_PDE6_DESCRIPTOR 0x86 16536c8eea54SJames Smart #define LPFC_PDE7_DESCRIPTOR 0x87 165481301a9bSJames Smart 16556c8eea54SJames Smart /* BlockGuard Opcodes */ 16566c8eea54SJames Smart #define BG_OP_IN_NODIF_OUT_CRC 0x0 16576c8eea54SJames Smart #define BG_OP_IN_CRC_OUT_NODIF 0x1 16586c8eea54SJames Smart #define BG_OP_IN_NODIF_OUT_CSUM 0x2 16596c8eea54SJames Smart #define BG_OP_IN_CSUM_OUT_NODIF 0x3 16606c8eea54SJames Smart #define BG_OP_IN_CRC_OUT_CRC 0x4 16616c8eea54SJames Smart #define BG_OP_IN_CSUM_OUT_CSUM 0x5 16626c8eea54SJames Smart #define BG_OP_IN_CRC_OUT_CSUM 0x6 16636c8eea54SJames Smart #define BG_OP_IN_CSUM_OUT_CRC 0x7 16646c8eea54SJames Smart 16656c8eea54SJames Smart struct lpfc_pde5 { 16666c8eea54SJames Smart uint32_t word0; 16676c8eea54SJames Smart #define pde5_type_SHIFT 24 16686c8eea54SJames Smart #define pde5_type_MASK 0x000000ff 16696c8eea54SJames Smart #define pde5_type_WORD word0 16706c8eea54SJames Smart #define pde5_rsvd0_SHIFT 0 16716c8eea54SJames Smart #define pde5_rsvd0_MASK 0x00ffffff 16726c8eea54SJames Smart #define pde5_rsvd0_WORD word0 16736c8eea54SJames Smart uint32_t reftag; /* Reference Tag Value */ 16746c8eea54SJames Smart uint32_t reftagtr; /* Reference Tag Translation Value */ 167581301a9bSJames Smart }; 167681301a9bSJames Smart 16776c8eea54SJames Smart struct lpfc_pde6 { 16786c8eea54SJames Smart uint32_t word0; 16796c8eea54SJames Smart #define pde6_type_SHIFT 24 16806c8eea54SJames Smart #define pde6_type_MASK 0x000000ff 16816c8eea54SJames Smart #define pde6_type_WORD word0 16826c8eea54SJames Smart #define pde6_rsvd0_SHIFT 0 16836c8eea54SJames Smart #define pde6_rsvd0_MASK 0x00ffffff 16846c8eea54SJames Smart #define pde6_rsvd0_WORD word0 16856c8eea54SJames Smart uint32_t word1; 16866c8eea54SJames Smart #define pde6_rsvd1_SHIFT 26 16876c8eea54SJames Smart #define pde6_rsvd1_MASK 0x0000003f 16886c8eea54SJames Smart #define pde6_rsvd1_WORD word1 16896c8eea54SJames Smart #define pde6_na_SHIFT 25 16906c8eea54SJames Smart #define pde6_na_MASK 0x00000001 16916c8eea54SJames Smart #define pde6_na_WORD word1 16926c8eea54SJames Smart #define pde6_rsvd2_SHIFT 16 16936c8eea54SJames Smart #define pde6_rsvd2_MASK 0x000001FF 16946c8eea54SJames Smart #define pde6_rsvd2_WORD word1 16956c8eea54SJames Smart #define pde6_apptagtr_SHIFT 0 16966c8eea54SJames Smart #define pde6_apptagtr_MASK 0x0000ffff 16976c8eea54SJames Smart #define pde6_apptagtr_WORD word1 16986c8eea54SJames Smart uint32_t word2; 16996c8eea54SJames Smart #define pde6_optx_SHIFT 28 17006c8eea54SJames Smart #define pde6_optx_MASK 0x0000000f 17016c8eea54SJames Smart #define pde6_optx_WORD word2 17026c8eea54SJames Smart #define pde6_oprx_SHIFT 24 17036c8eea54SJames Smart #define pde6_oprx_MASK 0x0000000f 17046c8eea54SJames Smart #define pde6_oprx_WORD word2 17056c8eea54SJames Smart #define pde6_nr_SHIFT 23 17066c8eea54SJames Smart #define pde6_nr_MASK 0x00000001 17076c8eea54SJames Smart #define pde6_nr_WORD word2 17086c8eea54SJames Smart #define pde6_ce_SHIFT 22 17096c8eea54SJames Smart #define pde6_ce_MASK 0x00000001 17106c8eea54SJames Smart #define pde6_ce_WORD word2 17116c8eea54SJames Smart #define pde6_re_SHIFT 21 17126c8eea54SJames Smart #define pde6_re_MASK 0x00000001 17136c8eea54SJames Smart #define pde6_re_WORD word2 17146c8eea54SJames Smart #define pde6_ae_SHIFT 20 17156c8eea54SJames Smart #define pde6_ae_MASK 0x00000001 17166c8eea54SJames Smart #define pde6_ae_WORD word2 17176c8eea54SJames Smart #define pde6_ai_SHIFT 19 17186c8eea54SJames Smart #define pde6_ai_MASK 0x00000001 17196c8eea54SJames Smart #define pde6_ai_WORD word2 17206c8eea54SJames Smart #define pde6_bs_SHIFT 16 17216c8eea54SJames Smart #define pde6_bs_MASK 0x00000007 17226c8eea54SJames Smart #define pde6_bs_WORD word2 17236c8eea54SJames Smart #define pde6_apptagval_SHIFT 0 17246c8eea54SJames Smart #define pde6_apptagval_MASK 0x0000ffff 17256c8eea54SJames Smart #define pde6_apptagval_WORD word2 172681301a9bSJames Smart }; 172781301a9bSJames Smart 17287f86059aSJames Smart struct lpfc_pde7 { 17297f86059aSJames Smart uint32_t word0; 17307f86059aSJames Smart #define pde7_type_SHIFT 24 17317f86059aSJames Smart #define pde7_type_MASK 0x000000ff 17327f86059aSJames Smart #define pde7_type_WORD word0 17337f86059aSJames Smart #define pde7_rsvd0_SHIFT 0 17347f86059aSJames Smart #define pde7_rsvd0_MASK 0x00ffffff 17357f86059aSJames Smart #define pde7_rsvd0_WORD word0 17367f86059aSJames Smart uint32_t addrHigh; 17377f86059aSJames Smart uint32_t addrLow; 17387f86059aSJames Smart }; 173981301a9bSJames Smart 1740dea3101eS /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1741dea3101eS 1742dea3101eS typedef struct { 1743dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1744dea3101eS uint32_t rsvd2:25; 1745dea3101eS uint32_t acknowledgment:1; 1746dea3101eS uint32_t version:1; 1747dea3101eS uint32_t erase_or_prog:1; 1748dea3101eS uint32_t update_flash:1; 1749dea3101eS uint32_t update_ram:1; 1750dea3101eS uint32_t method:1; 1751dea3101eS uint32_t load_cmplt:1; 1752dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1753dea3101eS uint32_t load_cmplt:1; 1754dea3101eS uint32_t method:1; 1755dea3101eS uint32_t update_ram:1; 1756dea3101eS uint32_t update_flash:1; 1757dea3101eS uint32_t erase_or_prog:1; 1758dea3101eS uint32_t version:1; 1759dea3101eS uint32_t acknowledgment:1; 1760dea3101eS uint32_t rsvd2:25; 1761dea3101eS #endif 1762dea3101eS 1763dea3101eS uint32_t dl_to_adr_low; 1764dea3101eS uint32_t dl_to_adr_high; 1765dea3101eS uint32_t dl_len; 1766dea3101eS union { 1767dea3101eS uint32_t dl_from_mbx_offset; 1768dea3101eS struct ulp_bde dl_from_bde; 1769dea3101eS struct ulp_bde64 dl_from_bde64; 1770dea3101eS } un; 1771dea3101eS 1772dea3101eS } LOAD_SM_VAR; 1773dea3101eS 1774dea3101eS /* Structure for MB Command READ_NVPARM (02) */ 1775dea3101eS 1776dea3101eS typedef struct { 1777dea3101eS uint32_t rsvd1[3]; /* Read as all one's */ 1778dea3101eS uint32_t rsvd2; /* Read as all zero's */ 1779dea3101eS uint32_t portname[2]; /* N_PORT name */ 1780dea3101eS uint32_t nodename[2]; /* NODE name */ 1781dea3101eS 1782dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1783dea3101eS uint32_t pref_DID:24; 1784dea3101eS uint32_t hardAL_PA:8; 1785dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1786dea3101eS uint32_t hardAL_PA:8; 1787dea3101eS uint32_t pref_DID:24; 1788dea3101eS #endif 1789dea3101eS 1790dea3101eS uint32_t rsvd3[21]; /* Read as all one's */ 1791dea3101eS } READ_NV_VAR; 1792dea3101eS 1793dea3101eS /* Structure for MB Command WRITE_NVPARMS (03) */ 1794dea3101eS 1795dea3101eS typedef struct { 1796dea3101eS uint32_t rsvd1[3]; /* Must be all one's */ 1797dea3101eS uint32_t rsvd2; /* Must be all zero's */ 1798dea3101eS uint32_t portname[2]; /* N_PORT name */ 1799dea3101eS uint32_t nodename[2]; /* NODE name */ 1800dea3101eS 1801dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1802dea3101eS uint32_t pref_DID:24; 1803dea3101eS uint32_t hardAL_PA:8; 1804dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1805dea3101eS uint32_t hardAL_PA:8; 1806dea3101eS uint32_t pref_DID:24; 1807dea3101eS #endif 1808dea3101eS 1809dea3101eS uint32_t rsvd3[21]; /* Must be all one's */ 1810dea3101eS } WRITE_NV_VAR; 1811dea3101eS 1812dea3101eS /* Structure for MB Command RUN_BIU_DIAG (04) */ 1813dea3101eS /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1814dea3101eS 1815dea3101eS typedef struct { 1816dea3101eS uint32_t rsvd1; 1817dea3101eS union { 1818dea3101eS struct { 1819dea3101eS struct ulp_bde xmit_bde; 1820dea3101eS struct ulp_bde rcv_bde; 1821dea3101eS } s1; 1822dea3101eS struct { 1823dea3101eS struct ulp_bde64 xmit_bde64; 1824dea3101eS struct ulp_bde64 rcv_bde64; 1825dea3101eS } s2; 1826dea3101eS } un; 1827dea3101eS } BIU_DIAG_VAR; 1828dea3101eS 1829c7495937SJames Smart /* Structure for MB command READ_EVENT_LOG (0x38) */ 1830c7495937SJames Smart struct READ_EVENT_LOG_VAR { 1831c7495937SJames Smart uint32_t word1; 1832c7495937SJames Smart #define lpfc_event_log_SHIFT 29 1833c7495937SJames Smart #define lpfc_event_log_MASK 0x00000001 1834c7495937SJames Smart #define lpfc_event_log_WORD word1 1835c7495937SJames Smart #define USE_MAILBOX_RESPONSE 1 1836c7495937SJames Smart uint32_t offset; 1837c7495937SJames Smart struct ulp_bde64 rcv_bde64; 1838c7495937SJames Smart }; 1839c7495937SJames Smart 1840dea3101eS /* Structure for MB Command INIT_LINK (05) */ 1841dea3101eS 1842dea3101eS typedef struct { 1843dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1844dea3101eS uint32_t rsvd1:24; 1845dea3101eS uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1846dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1847dea3101eS uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1848dea3101eS uint32_t rsvd1:24; 1849dea3101eS #endif 1850dea3101eS 1851dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1852dea3101eS uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1853dea3101eS uint8_t rsvd2; 1854dea3101eS uint16_t link_flags; 1855dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1856dea3101eS uint16_t link_flags; 1857dea3101eS uint8_t rsvd2; 1858dea3101eS uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1859dea3101eS #endif 1860dea3101eS 1861dea3101eS #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1862dea3101eS #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1863dea3101eS #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1864dea3101eS #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1865dea3101eS #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1866ed957684SJames Smart #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 1867dea3101eS #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1868dea3101eS 1869dea3101eS #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1870dea3101eS #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 18714b0b91d4SJames Smart #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 1872dea3101eS 1873dea3101eS uint32_t link_speed; 187476a95d75SJames Smart #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 187576a95d75SJames Smart #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 187676a95d75SJames Smart #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 187776a95d75SJames Smart #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 187876a95d75SJames Smart #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 187976a95d75SJames Smart #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 188076a95d75SJames Smart #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 1881dea3101eS 1882dea3101eS } INIT_LINK_VAR; 1883dea3101eS 1884dea3101eS /* Structure for MB Command DOWN_LINK (06) */ 1885dea3101eS 1886dea3101eS typedef struct { 1887dea3101eS uint32_t rsvd1; 1888dea3101eS } DOWN_LINK_VAR; 1889dea3101eS 1890dea3101eS /* Structure for MB Command CONFIG_LINK (07) */ 1891dea3101eS 1892dea3101eS typedef struct { 1893dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1894dea3101eS uint32_t cr:1; 1895dea3101eS uint32_t ci:1; 1896dea3101eS uint32_t cr_delay:6; 1897dea3101eS uint32_t cr_count:8; 1898dea3101eS uint32_t rsvd1:8; 1899dea3101eS uint32_t MaxBBC:8; 1900dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1901dea3101eS uint32_t MaxBBC:8; 1902dea3101eS uint32_t rsvd1:8; 1903dea3101eS uint32_t cr_count:8; 1904dea3101eS uint32_t cr_delay:6; 1905dea3101eS uint32_t ci:1; 1906dea3101eS uint32_t cr:1; 1907dea3101eS #endif 1908dea3101eS 1909dea3101eS uint32_t myId; 1910dea3101eS uint32_t rsvd2; 1911dea3101eS uint32_t edtov; 1912dea3101eS uint32_t arbtov; 1913dea3101eS uint32_t ratov; 1914dea3101eS uint32_t rttov; 1915dea3101eS uint32_t altov; 1916dea3101eS uint32_t crtov; 1917dea3101eS uint32_t citov; 1918dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1919dea3101eS uint32_t rrq_enable:1; 1920dea3101eS uint32_t rrq_immed:1; 1921dea3101eS uint32_t rsvd4:29; 1922dea3101eS uint32_t ack0_enable:1; 1923dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1924dea3101eS uint32_t ack0_enable:1; 1925dea3101eS uint32_t rsvd4:29; 1926dea3101eS uint32_t rrq_immed:1; 1927dea3101eS uint32_t rrq_enable:1; 1928dea3101eS #endif 1929dea3101eS } CONFIG_LINK; 1930dea3101eS 1931dea3101eS /* Structure for MB Command PART_SLIM (08) 1932dea3101eS * will be removed since SLI1 is no longer supported! 1933dea3101eS */ 1934dea3101eS typedef struct { 1935dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1936dea3101eS uint16_t offCiocb; 1937dea3101eS uint16_t numCiocb; 1938dea3101eS uint16_t offRiocb; 1939dea3101eS uint16_t numRiocb; 1940dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1941dea3101eS uint16_t numCiocb; 1942dea3101eS uint16_t offCiocb; 1943dea3101eS uint16_t numRiocb; 1944dea3101eS uint16_t offRiocb; 1945dea3101eS #endif 1946dea3101eS } RING_DEF; 1947dea3101eS 1948dea3101eS typedef struct { 1949dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1950dea3101eS uint32_t unused1:24; 1951dea3101eS uint32_t numRing:8; 1952dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1953dea3101eS uint32_t numRing:8; 1954dea3101eS uint32_t unused1:24; 1955dea3101eS #endif 1956dea3101eS 1957dea3101eS RING_DEF ringdef[4]; 1958dea3101eS uint32_t hbainit; 1959dea3101eS } PART_SLIM_VAR; 1960dea3101eS 1961dea3101eS /* Structure for MB Command CONFIG_RING (09) */ 1962dea3101eS 1963dea3101eS typedef struct { 1964dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1965dea3101eS uint32_t unused2:6; 1966dea3101eS uint32_t recvSeq:1; 1967dea3101eS uint32_t recvNotify:1; 1968dea3101eS uint32_t numMask:8; 1969dea3101eS uint32_t profile:8; 1970dea3101eS uint32_t unused1:4; 1971dea3101eS uint32_t ring:4; 1972dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1973dea3101eS uint32_t ring:4; 1974dea3101eS uint32_t unused1:4; 1975dea3101eS uint32_t profile:8; 1976dea3101eS uint32_t numMask:8; 1977dea3101eS uint32_t recvNotify:1; 1978dea3101eS uint32_t recvSeq:1; 1979dea3101eS uint32_t unused2:6; 1980dea3101eS #endif 1981dea3101eS 1982dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1983dea3101eS uint16_t maxRespXchg; 1984dea3101eS uint16_t maxOrigXchg; 1985dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1986dea3101eS uint16_t maxOrigXchg; 1987dea3101eS uint16_t maxRespXchg; 1988dea3101eS #endif 1989dea3101eS 1990dea3101eS RR_REG rrRegs[6]; 1991dea3101eS } CONFIG_RING_VAR; 1992dea3101eS 1993dea3101eS /* Structure for MB Command RESET_RING (10) */ 1994dea3101eS 1995dea3101eS typedef struct { 1996dea3101eS uint32_t ring_no; 1997dea3101eS } RESET_RING_VAR; 1998dea3101eS 1999dea3101eS /* Structure for MB Command READ_CONFIG (11) */ 2000dea3101eS 2001dea3101eS typedef struct { 2002dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2003dea3101eS uint32_t cr:1; 2004dea3101eS uint32_t ci:1; 2005dea3101eS uint32_t cr_delay:6; 2006dea3101eS uint32_t cr_count:8; 2007dea3101eS uint32_t InitBBC:8; 2008dea3101eS uint32_t MaxBBC:8; 2009dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2010dea3101eS uint32_t MaxBBC:8; 2011dea3101eS uint32_t InitBBC:8; 2012dea3101eS uint32_t cr_count:8; 2013dea3101eS uint32_t cr_delay:6; 2014dea3101eS uint32_t ci:1; 2015dea3101eS uint32_t cr:1; 2016dea3101eS #endif 2017dea3101eS 2018dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2019dea3101eS uint32_t topology:8; 2020dea3101eS uint32_t myDid:24; 2021dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2022dea3101eS uint32_t myDid:24; 2023dea3101eS uint32_t topology:8; 2024dea3101eS #endif 2025dea3101eS 2026dea3101eS /* Defines for topology (defined previously) */ 2027dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2028dea3101eS uint32_t AR:1; 2029dea3101eS uint32_t IR:1; 2030dea3101eS uint32_t rsvd1:29; 2031dea3101eS uint32_t ack0:1; 2032dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2033dea3101eS uint32_t ack0:1; 2034dea3101eS uint32_t rsvd1:29; 2035dea3101eS uint32_t IR:1; 2036dea3101eS uint32_t AR:1; 2037dea3101eS #endif 2038dea3101eS 2039dea3101eS uint32_t edtov; 2040dea3101eS uint32_t arbtov; 2041dea3101eS uint32_t ratov; 2042dea3101eS uint32_t rttov; 2043dea3101eS uint32_t altov; 2044dea3101eS uint32_t lmt; 204574b72a59SJamie Wellnitz #define LMT_RESERVED 0x000 /* Not used */ 204674b72a59SJamie Wellnitz #define LMT_1Gb 0x004 204774b72a59SJamie Wellnitz #define LMT_2Gb 0x008 204874b72a59SJamie Wellnitz #define LMT_4Gb 0x040 204974b72a59SJamie Wellnitz #define LMT_8Gb 0x080 205074b72a59SJamie Wellnitz #define LMT_10Gb 0x100 205176a95d75SJames Smart #define LMT_16Gb 0x200 2052dea3101eS uint32_t rsvd2; 2053dea3101eS uint32_t rsvd3; 2054dea3101eS uint32_t max_xri; 2055dea3101eS uint32_t max_iocb; 2056dea3101eS uint32_t max_rpi; 2057dea3101eS uint32_t avail_xri; 2058dea3101eS uint32_t avail_iocb; 2059dea3101eS uint32_t avail_rpi; 2060858c9f6cSJames Smart uint32_t max_vpi; 2061858c9f6cSJames Smart uint32_t rsvd4; 2062858c9f6cSJames Smart uint32_t rsvd5; 2063858c9f6cSJames Smart uint32_t avail_vpi; 2064dea3101eS } READ_CONFIG_VAR; 2065dea3101eS 2066dea3101eS /* Structure for MB Command READ_RCONFIG (12) */ 2067dea3101eS 2068dea3101eS typedef struct { 2069dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2070dea3101eS uint32_t rsvd2:7; 2071dea3101eS uint32_t recvNotify:1; 2072dea3101eS uint32_t numMask:8; 2073dea3101eS uint32_t profile:8; 2074dea3101eS uint32_t rsvd1:4; 2075dea3101eS uint32_t ring:4; 2076dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2077dea3101eS uint32_t ring:4; 2078dea3101eS uint32_t rsvd1:4; 2079dea3101eS uint32_t profile:8; 2080dea3101eS uint32_t numMask:8; 2081dea3101eS uint32_t recvNotify:1; 2082dea3101eS uint32_t rsvd2:7; 2083dea3101eS #endif 2084dea3101eS 2085dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2086dea3101eS uint16_t maxResp; 2087dea3101eS uint16_t maxOrig; 2088dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2089dea3101eS uint16_t maxOrig; 2090dea3101eS uint16_t maxResp; 2091dea3101eS #endif 2092dea3101eS 2093dea3101eS RR_REG rrRegs[6]; 2094dea3101eS 2095dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2096dea3101eS uint16_t cmdRingOffset; 2097dea3101eS uint16_t cmdEntryCnt; 2098dea3101eS uint16_t rspRingOffset; 2099dea3101eS uint16_t rspEntryCnt; 2100dea3101eS uint16_t nextCmdOffset; 2101dea3101eS uint16_t rsvd3; 2102dea3101eS uint16_t nextRspOffset; 2103dea3101eS uint16_t rsvd4; 2104dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2105dea3101eS uint16_t cmdEntryCnt; 2106dea3101eS uint16_t cmdRingOffset; 2107dea3101eS uint16_t rspEntryCnt; 2108dea3101eS uint16_t rspRingOffset; 2109dea3101eS uint16_t rsvd3; 2110dea3101eS uint16_t nextCmdOffset; 2111dea3101eS uint16_t rsvd4; 2112dea3101eS uint16_t nextRspOffset; 2113dea3101eS #endif 2114dea3101eS } READ_RCONF_VAR; 2115dea3101eS 2116dea3101eS /* Structure for MB Command READ_SPARM (13) */ 2117dea3101eS /* Structure for MB Command READ_SPARM64 (0x8D) */ 2118dea3101eS 2119dea3101eS typedef struct { 2120dea3101eS uint32_t rsvd1; 2121dea3101eS uint32_t rsvd2; 2122dea3101eS union { 2123dea3101eS struct ulp_bde sp; /* This BDE points to struct serv_parm 2124dea3101eS structure */ 2125dea3101eS struct ulp_bde64 sp64; 2126dea3101eS } un; 2127ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2128ed957684SJames Smart uint16_t rsvd3; 2129ed957684SJames Smart uint16_t vpi; 2130ed957684SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 2131ed957684SJames Smart uint16_t vpi; 2132ed957684SJames Smart uint16_t rsvd3; 2133ed957684SJames Smart #endif 2134dea3101eS } READ_SPARM_VAR; 2135dea3101eS 2136dea3101eS /* Structure for MB Command READ_STATUS (14) */ 2137dea3101eS 2138dea3101eS typedef struct { 2139dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2140dea3101eS uint32_t rsvd1:31; 2141dea3101eS uint32_t clrCounters:1; 2142dea3101eS uint16_t activeXriCnt; 2143dea3101eS uint16_t activeRpiCnt; 2144dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2145dea3101eS uint32_t clrCounters:1; 2146dea3101eS uint32_t rsvd1:31; 2147dea3101eS uint16_t activeRpiCnt; 2148dea3101eS uint16_t activeXriCnt; 2149dea3101eS #endif 2150dea3101eS 2151dea3101eS uint32_t xmitByteCnt; 2152dea3101eS uint32_t rcvByteCnt; 2153dea3101eS uint32_t xmitFrameCnt; 2154dea3101eS uint32_t rcvFrameCnt; 2155dea3101eS uint32_t xmitSeqCnt; 2156dea3101eS uint32_t rcvSeqCnt; 2157dea3101eS uint32_t totalOrigExchanges; 2158dea3101eS uint32_t totalRespExchanges; 2159dea3101eS uint32_t rcvPbsyCnt; 2160dea3101eS uint32_t rcvFbsyCnt; 2161dea3101eS } READ_STATUS_VAR; 2162dea3101eS 2163dea3101eS /* Structure for MB Command READ_RPI (15) */ 2164dea3101eS /* Structure for MB Command READ_RPI64 (0x8F) */ 2165dea3101eS 2166dea3101eS typedef struct { 2167dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2168dea3101eS uint16_t nextRpi; 2169dea3101eS uint16_t reqRpi; 2170dea3101eS uint32_t rsvd2:8; 2171dea3101eS uint32_t DID:24; 2172dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2173dea3101eS uint16_t reqRpi; 2174dea3101eS uint16_t nextRpi; 2175dea3101eS uint32_t DID:24; 2176dea3101eS uint32_t rsvd2:8; 2177dea3101eS #endif 2178dea3101eS 2179dea3101eS union { 2180dea3101eS struct ulp_bde sp; 2181dea3101eS struct ulp_bde64 sp64; 2182dea3101eS } un; 2183dea3101eS 2184dea3101eS } READ_RPI_VAR; 2185dea3101eS 2186dea3101eS /* Structure for MB Command READ_XRI (16) */ 2187dea3101eS 2188dea3101eS typedef struct { 2189dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2190dea3101eS uint16_t nextXri; 2191dea3101eS uint16_t reqXri; 2192dea3101eS uint16_t rsvd1; 2193dea3101eS uint16_t rpi; 2194dea3101eS uint32_t rsvd2:8; 2195dea3101eS uint32_t DID:24; 2196dea3101eS uint32_t rsvd3:8; 2197dea3101eS uint32_t SID:24; 2198dea3101eS uint32_t rsvd4; 2199dea3101eS uint8_t seqId; 2200dea3101eS uint8_t rsvd5; 2201dea3101eS uint16_t seqCount; 2202dea3101eS uint16_t oxId; 2203dea3101eS uint16_t rxId; 2204dea3101eS uint32_t rsvd6:30; 2205dea3101eS uint32_t si:1; 2206dea3101eS uint32_t exchOrig:1; 2207dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2208dea3101eS uint16_t reqXri; 2209dea3101eS uint16_t nextXri; 2210dea3101eS uint16_t rpi; 2211dea3101eS uint16_t rsvd1; 2212dea3101eS uint32_t DID:24; 2213dea3101eS uint32_t rsvd2:8; 2214dea3101eS uint32_t SID:24; 2215dea3101eS uint32_t rsvd3:8; 2216dea3101eS uint32_t rsvd4; 2217dea3101eS uint16_t seqCount; 2218dea3101eS uint8_t rsvd5; 2219dea3101eS uint8_t seqId; 2220dea3101eS uint16_t rxId; 2221dea3101eS uint16_t oxId; 2222dea3101eS uint32_t exchOrig:1; 2223dea3101eS uint32_t si:1; 2224dea3101eS uint32_t rsvd6:30; 2225dea3101eS #endif 2226dea3101eS } READ_XRI_VAR; 2227dea3101eS 2228dea3101eS /* Structure for MB Command READ_REV (17) */ 2229dea3101eS 2230dea3101eS typedef struct { 2231dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2232dea3101eS uint32_t cv:1; 2233dea3101eS uint32_t rr:1; 2234ed957684SJames Smart uint32_t rsvd2:2; 2235ed957684SJames Smart uint32_t v3req:1; 2236ed957684SJames Smart uint32_t v3rsp:1; 2237ed957684SJames Smart uint32_t rsvd1:25; 2238dea3101eS uint32_t rv:1; 2239dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2240dea3101eS uint32_t rv:1; 2241ed957684SJames Smart uint32_t rsvd1:25; 2242ed957684SJames Smart uint32_t v3rsp:1; 2243ed957684SJames Smart uint32_t v3req:1; 2244ed957684SJames Smart uint32_t rsvd2:2; 2245dea3101eS uint32_t rr:1; 2246dea3101eS uint32_t cv:1; 2247dea3101eS #endif 2248dea3101eS 2249dea3101eS uint32_t biuRev; 2250dea3101eS uint32_t smRev; 2251dea3101eS union { 2252dea3101eS uint32_t smFwRev; 2253dea3101eS struct { 2254dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2255dea3101eS uint8_t ProgType; 2256dea3101eS uint8_t ProgId; 2257dea3101eS uint16_t ProgVer:4; 2258dea3101eS uint16_t ProgRev:4; 2259dea3101eS uint16_t ProgFixLvl:2; 2260dea3101eS uint16_t ProgDistType:2; 2261dea3101eS uint16_t DistCnt:4; 2262dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2263dea3101eS uint16_t DistCnt:4; 2264dea3101eS uint16_t ProgDistType:2; 2265dea3101eS uint16_t ProgFixLvl:2; 2266dea3101eS uint16_t ProgRev:4; 2267dea3101eS uint16_t ProgVer:4; 2268dea3101eS uint8_t ProgId; 2269dea3101eS uint8_t ProgType; 2270dea3101eS #endif 2271dea3101eS 2272dea3101eS } b; 2273dea3101eS } un; 2274dea3101eS uint32_t endecRev; 2275dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2276dea3101eS uint8_t feaLevelHigh; 2277dea3101eS uint8_t feaLevelLow; 2278dea3101eS uint8_t fcphHigh; 2279dea3101eS uint8_t fcphLow; 2280dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2281dea3101eS uint8_t fcphLow; 2282dea3101eS uint8_t fcphHigh; 2283dea3101eS uint8_t feaLevelLow; 2284dea3101eS uint8_t feaLevelHigh; 2285dea3101eS #endif 2286dea3101eS 2287dea3101eS uint32_t postKernRev; 2288dea3101eS uint32_t opFwRev; 2289dea3101eS uint8_t opFwName[16]; 2290dea3101eS uint32_t sli1FwRev; 2291dea3101eS uint8_t sli1FwName[16]; 2292dea3101eS uint32_t sli2FwRev; 2293dea3101eS uint8_t sli2FwName[16]; 2294ed957684SJames Smart uint32_t sli3Feat; 2295ed957684SJames Smart uint32_t RandomData[6]; 2296dea3101eS } READ_REV_VAR; 2297dea3101eS 2298dea3101eS /* Structure for MB Command READ_LINK_STAT (18) */ 2299dea3101eS 2300dea3101eS typedef struct { 2301dea3101eS uint32_t rsvd1; 2302dea3101eS uint32_t linkFailureCnt; 2303dea3101eS uint32_t lossSyncCnt; 2304dea3101eS 2305dea3101eS uint32_t lossSignalCnt; 2306dea3101eS uint32_t primSeqErrCnt; 2307dea3101eS uint32_t invalidXmitWord; 2308dea3101eS uint32_t crcCnt; 2309dea3101eS uint32_t primSeqTimeout; 2310dea3101eS uint32_t elasticOverrun; 2311dea3101eS uint32_t arbTimeout; 2312dea3101eS } READ_LNK_VAR; 2313dea3101eS 2314dea3101eS /* Structure for MB Command REG_LOGIN (19) */ 2315dea3101eS /* Structure for MB Command REG_LOGIN64 (0x93) */ 2316dea3101eS 2317dea3101eS typedef struct { 2318dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2319dea3101eS uint16_t rsvd1; 2320dea3101eS uint16_t rpi; 2321dea3101eS uint32_t rsvd2:8; 2322dea3101eS uint32_t did:24; 2323dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2324dea3101eS uint16_t rpi; 2325dea3101eS uint16_t rsvd1; 2326dea3101eS uint32_t did:24; 2327dea3101eS uint32_t rsvd2:8; 2328dea3101eS #endif 2329dea3101eS 2330dea3101eS union { 2331dea3101eS struct ulp_bde sp; 2332dea3101eS struct ulp_bde64 sp64; 2333dea3101eS } un; 2334dea3101eS 2335ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2336ed957684SJames Smart uint16_t rsvd6; 2337ed957684SJames Smart uint16_t vpi; 2338ed957684SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 2339ed957684SJames Smart uint16_t vpi; 2340ed957684SJames Smart uint16_t rsvd6; 2341ed957684SJames Smart #endif 2342ed957684SJames Smart 2343dea3101eS } REG_LOGIN_VAR; 2344dea3101eS 2345dea3101eS /* Word 30 contents for REG_LOGIN */ 2346dea3101eS typedef union { 2347dea3101eS struct { 2348dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2349dea3101eS uint16_t rsvd1:12; 2350dea3101eS uint16_t wd30_class:4; 2351dea3101eS uint16_t xri; 2352dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2353dea3101eS uint16_t xri; 2354dea3101eS uint16_t wd30_class:4; 2355dea3101eS uint16_t rsvd1:12; 2356dea3101eS #endif 2357dea3101eS } f; 2358dea3101eS uint32_t word; 2359dea3101eS } REG_WD30; 2360dea3101eS 2361dea3101eS /* Structure for MB Command UNREG_LOGIN (20) */ 2362dea3101eS 2363dea3101eS typedef struct { 2364dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2365dea3101eS uint16_t rsvd1; 2366dea3101eS uint16_t rpi; 2367ed957684SJames Smart uint32_t rsvd2; 2368ed957684SJames Smart uint32_t rsvd3; 2369ed957684SJames Smart uint32_t rsvd4; 2370ed957684SJames Smart uint32_t rsvd5; 2371ed957684SJames Smart uint16_t rsvd6; 2372ed957684SJames Smart uint16_t vpi; 2373dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2374dea3101eS uint16_t rpi; 2375dea3101eS uint16_t rsvd1; 2376ed957684SJames Smart uint32_t rsvd2; 2377ed957684SJames Smart uint32_t rsvd3; 2378ed957684SJames Smart uint32_t rsvd4; 2379ed957684SJames Smart uint32_t rsvd5; 2380ed957684SJames Smart uint16_t vpi; 2381ed957684SJames Smart uint16_t rsvd6; 2382dea3101eS #endif 2383dea3101eS } UNREG_LOGIN_VAR; 2384dea3101eS 238592d7f7b0SJames Smart /* Structure for MB Command REG_VPI (0x96) */ 238692d7f7b0SJames Smart typedef struct { 238792d7f7b0SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 238892d7f7b0SJames Smart uint32_t rsvd1; 238938b92ef8SJames Smart uint32_t rsvd2:7; 239038b92ef8SJames Smart uint32_t upd:1; 239192d7f7b0SJames Smart uint32_t sid:24; 2392c868595dSJames Smart uint32_t wwn[2]; 239392d7f7b0SJames Smart uint32_t rsvd5; 2394da0436e9SJames Smart uint16_t vfi; 239592d7f7b0SJames Smart uint16_t vpi; 239692d7f7b0SJames Smart #else /* __LITTLE_ENDIAN */ 239792d7f7b0SJames Smart uint32_t rsvd1; 239892d7f7b0SJames Smart uint32_t sid:24; 239938b92ef8SJames Smart uint32_t upd:1; 240038b92ef8SJames Smart uint32_t rsvd2:7; 2401c868595dSJames Smart uint32_t wwn[2]; 240292d7f7b0SJames Smart uint32_t rsvd5; 240392d7f7b0SJames Smart uint16_t vpi; 2404da0436e9SJames Smart uint16_t vfi; 240592d7f7b0SJames Smart #endif 240692d7f7b0SJames Smart } REG_VPI_VAR; 240792d7f7b0SJames Smart 240892d7f7b0SJames Smart /* Structure for MB Command UNREG_VPI (0x97) */ 240992d7f7b0SJames Smart typedef struct { 241092d7f7b0SJames Smart uint32_t rsvd1; 24116669f9bbSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 24126669f9bbSJames Smart uint16_t rsvd2; 24136669f9bbSJames Smart uint16_t sli4_vpi; 24146669f9bbSJames Smart #else /* __LITTLE_ENDIAN */ 24156669f9bbSJames Smart uint16_t sli4_vpi; 24166669f9bbSJames Smart uint16_t rsvd2; 24176669f9bbSJames Smart #endif 241892d7f7b0SJames Smart uint32_t rsvd3; 241992d7f7b0SJames Smart uint32_t rsvd4; 242092d7f7b0SJames Smart uint32_t rsvd5; 242192d7f7b0SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 242292d7f7b0SJames Smart uint16_t rsvd6; 242392d7f7b0SJames Smart uint16_t vpi; 242492d7f7b0SJames Smart #else /* __LITTLE_ENDIAN */ 242592d7f7b0SJames Smart uint16_t vpi; 242692d7f7b0SJames Smart uint16_t rsvd6; 242792d7f7b0SJames Smart #endif 242892d7f7b0SJames Smart } UNREG_VPI_VAR; 242992d7f7b0SJames Smart 2430dea3101eS /* Structure for MB Command UNREG_D_ID (0x23) */ 2431dea3101eS 2432dea3101eS typedef struct { 2433dea3101eS uint32_t did; 2434ed957684SJames Smart uint32_t rsvd2; 2435ed957684SJames Smart uint32_t rsvd3; 2436ed957684SJames Smart uint32_t rsvd4; 2437ed957684SJames Smart uint32_t rsvd5; 2438ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2439ed957684SJames Smart uint16_t rsvd6; 2440ed957684SJames Smart uint16_t vpi; 2441ed957684SJames Smart #else 2442ed957684SJames Smart uint16_t vpi; 2443ed957684SJames Smart uint16_t rsvd6; 2444ed957684SJames Smart #endif 2445dea3101eS } UNREG_D_ID_VAR; 2446dea3101eS 244776a95d75SJames Smart /* Structure for MB Command READ_TOPOLOGY (0x95) */ 244876a95d75SJames Smart struct lpfc_mbx_read_top { 2449dea3101eS uint32_t eventTag; /* Event tag */ 245076a95d75SJames Smart uint32_t word2; 245176a95d75SJames Smart #define lpfc_mbx_read_top_fa_SHIFT 12 245276a95d75SJames Smart #define lpfc_mbx_read_top_fa_MASK 0x00000001 245376a95d75SJames Smart #define lpfc_mbx_read_top_fa_WORD word2 245476a95d75SJames Smart #define lpfc_mbx_read_top_mm_SHIFT 11 245576a95d75SJames Smart #define lpfc_mbx_read_top_mm_MASK 0x00000001 245676a95d75SJames Smart #define lpfc_mbx_read_top_mm_WORD word2 245776a95d75SJames Smart #define lpfc_mbx_read_top_pb_SHIFT 9 245876a95d75SJames Smart #define lpfc_mbx_read_top_pb_MASK 0X00000001 245976a95d75SJames Smart #define lpfc_mbx_read_top_pb_WORD word2 246076a95d75SJames Smart #define lpfc_mbx_read_top_il_SHIFT 8 246176a95d75SJames Smart #define lpfc_mbx_read_top_il_MASK 0x00000001 246276a95d75SJames Smart #define lpfc_mbx_read_top_il_WORD word2 246376a95d75SJames Smart #define lpfc_mbx_read_top_att_type_SHIFT 0 246476a95d75SJames Smart #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 246576a95d75SJames Smart #define lpfc_mbx_read_top_att_type_WORD word2 246676a95d75SJames Smart #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 246776a95d75SJames Smart #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 246876a95d75SJames Smart #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 246976a95d75SJames Smart uint32_t word3; 247076a95d75SJames Smart #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 247176a95d75SJames Smart #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 247276a95d75SJames Smart #define lpfc_mbx_read_top_alpa_granted_WORD word3 247376a95d75SJames Smart #define lpfc_mbx_read_top_lip_alps_SHIFT 16 247476a95d75SJames Smart #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 247576a95d75SJames Smart #define lpfc_mbx_read_top_lip_alps_WORD word3 247676a95d75SJames Smart #define lpfc_mbx_read_top_lip_type_SHIFT 8 247776a95d75SJames Smart #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 247876a95d75SJames Smart #define lpfc_mbx_read_top_lip_type_WORD word3 247976a95d75SJames Smart #define lpfc_mbx_read_top_topology_SHIFT 0 248076a95d75SJames Smart #define lpfc_mbx_read_top_topology_MASK 0x000000FF 248176a95d75SJames Smart #define lpfc_mbx_read_top_topology_WORD word3 248276a95d75SJames Smart #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 248376a95d75SJames Smart #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 248476a95d75SJames Smart #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ 2485dea3101eS /* store the LILP AL_PA position map into */ 2486dea3101eS struct ulp_bde64 lilpBde64; 248776a95d75SJames Smart #define LPFC_ALPA_MAP_SIZE 128 248876a95d75SJames Smart uint32_t word7; 248976a95d75SJames Smart #define lpfc_mbx_read_top_ld_lu_SHIFT 31 249076a95d75SJames Smart #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 249176a95d75SJames Smart #define lpfc_mbx_read_top_ld_lu_WORD word7 249276a95d75SJames Smart #define lpfc_mbx_read_top_ld_tf_SHIFT 30 249376a95d75SJames Smart #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 249476a95d75SJames Smart #define lpfc_mbx_read_top_ld_tf_WORD word7 249576a95d75SJames Smart #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 249676a95d75SJames Smart #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 249776a95d75SJames Smart #define lpfc_mbx_read_top_ld_link_spd_WORD word7 249876a95d75SJames Smart #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 249976a95d75SJames Smart #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 250076a95d75SJames Smart #define lpfc_mbx_read_top_ld_nl_port_WORD word7 250176a95d75SJames Smart #define lpfc_mbx_read_top_ld_tx_SHIFT 2 250276a95d75SJames Smart #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 250376a95d75SJames Smart #define lpfc_mbx_read_top_ld_tx_WORD word7 250476a95d75SJames Smart #define lpfc_mbx_read_top_ld_rx_SHIFT 0 250576a95d75SJames Smart #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 250676a95d75SJames Smart #define lpfc_mbx_read_top_ld_rx_WORD word7 250776a95d75SJames Smart uint32_t word8; 250876a95d75SJames Smart #define lpfc_mbx_read_top_lu_SHIFT 31 250976a95d75SJames Smart #define lpfc_mbx_read_top_lu_MASK 0x00000001 251076a95d75SJames Smart #define lpfc_mbx_read_top_lu_WORD word8 251176a95d75SJames Smart #define lpfc_mbx_read_top_tf_SHIFT 30 251276a95d75SJames Smart #define lpfc_mbx_read_top_tf_MASK 0x00000001 251376a95d75SJames Smart #define lpfc_mbx_read_top_tf_WORD word8 251476a95d75SJames Smart #define lpfc_mbx_read_top_link_spd_SHIFT 8 251576a95d75SJames Smart #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 251676a95d75SJames Smart #define lpfc_mbx_read_top_link_spd_WORD word8 251776a95d75SJames Smart #define lpfc_mbx_read_top_nl_port_SHIFT 4 251876a95d75SJames Smart #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 251976a95d75SJames Smart #define lpfc_mbx_read_top_nl_port_WORD word8 252076a95d75SJames Smart #define lpfc_mbx_read_top_tx_SHIFT 2 252176a95d75SJames Smart #define lpfc_mbx_read_top_tx_MASK 0x00000003 252276a95d75SJames Smart #define lpfc_mbx_read_top_tx_WORD word8 252376a95d75SJames Smart #define lpfc_mbx_read_top_rx_SHIFT 0 252476a95d75SJames Smart #define lpfc_mbx_read_top_rx_MASK 0x00000003 252576a95d75SJames Smart #define lpfc_mbx_read_top_rx_WORD word8 252676a95d75SJames Smart #define LPFC_LINK_SPEED_UNKNOWN 0x0 252776a95d75SJames Smart #define LPFC_LINK_SPEED_1GHZ 0x04 252876a95d75SJames Smart #define LPFC_LINK_SPEED_2GHZ 0x08 252976a95d75SJames Smart #define LPFC_LINK_SPEED_4GHZ 0x10 253076a95d75SJames Smart #define LPFC_LINK_SPEED_8GHZ 0x20 253176a95d75SJames Smart #define LPFC_LINK_SPEED_10GHZ 0x40 253276a95d75SJames Smart #define LPFC_LINK_SPEED_16GHZ 0x80 253376a95d75SJames Smart }; 2534dea3101eS 2535dea3101eS /* Structure for MB Command CLEAR_LA (22) */ 2536dea3101eS 2537dea3101eS typedef struct { 2538dea3101eS uint32_t eventTag; /* Event tag */ 2539dea3101eS uint32_t rsvd1; 2540dea3101eS } CLEAR_LA_VAR; 2541dea3101eS 2542dea3101eS /* Structure for MB Command DUMP */ 2543dea3101eS 2544dea3101eS typedef struct { 2545dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2546dea3101eS uint32_t rsvd:25; 2547dea3101eS uint32_t ra:1; 2548dea3101eS uint32_t co:1; 2549dea3101eS uint32_t cv:1; 2550dea3101eS uint32_t type:4; 2551dea3101eS uint32_t entry_index:16; 2552dea3101eS uint32_t region_id:16; 2553dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2554dea3101eS uint32_t type:4; 2555dea3101eS uint32_t cv:1; 2556dea3101eS uint32_t co:1; 2557dea3101eS uint32_t ra:1; 2558dea3101eS uint32_t rsvd:25; 2559dea3101eS uint32_t region_id:16; 2560dea3101eS uint32_t entry_index:16; 2561dea3101eS #endif 2562dea3101eS 2563da0436e9SJames Smart uint32_t sli4_length; 2564dea3101eS uint32_t word_cnt; 2565dea3101eS uint32_t resp_offset; 2566dea3101eS } DUMP_VAR; 2567dea3101eS 2568dea3101eS #define DMP_MEM_REG 0x1 2569dea3101eS #define DMP_NV_PARAMS 0x2 2570dea3101eS 2571dea3101eS #define DMP_REGION_VPD 0xe 2572dea3101eS #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2573dea3101eS #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2574dea3101eS #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2575dea3101eS 2576da0436e9SJames Smart #define DMP_REGION_VPORT 0x16 /* VPort info region */ 2577da0436e9SJames Smart #define DMP_VPORT_REGION_SIZE 0x200 2578da0436e9SJames Smart #define DMP_MBOX_OFFSET_WORD 0x5 2579da0436e9SJames Smart 2580a0c87cbdSJames Smart #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 2581a0c87cbdSJames Smart #define DMP_RGN23_SIZE 0x400 2582da0436e9SJames Smart 258397207482SJames Smart #define WAKE_UP_PARMS_REGION_ID 4 258497207482SJames Smart #define WAKE_UP_PARMS_WORD_SIZE 15 258597207482SJames Smart 2586da0436e9SJames Smart struct vport_rec { 2587da0436e9SJames Smart uint8_t wwpn[8]; 2588da0436e9SJames Smart uint8_t wwnn[8]; 2589da0436e9SJames Smart }; 2590da0436e9SJames Smart 2591da0436e9SJames Smart #define VPORT_INFO_SIG 0x32324752 2592da0436e9SJames Smart #define VPORT_INFO_REV_MASK 0xff 2593da0436e9SJames Smart #define VPORT_INFO_REV 0x1 2594da0436e9SJames Smart #define MAX_STATIC_VPORT_COUNT 16 2595da0436e9SJames Smart struct static_vport_info { 2596da0436e9SJames Smart uint32_t signature; 2597da0436e9SJames Smart uint32_t rev; 2598da0436e9SJames Smart struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 2599da0436e9SJames Smart uint32_t resvd[66]; 2600da0436e9SJames Smart }; 2601da0436e9SJames Smart 260297207482SJames Smart /* Option rom version structure */ 260397207482SJames Smart struct prog_id { 260497207482SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 260597207482SJames Smart uint8_t type; 260697207482SJames Smart uint8_t id; 260797207482SJames Smart uint32_t ver:4; /* Major Version */ 260897207482SJames Smart uint32_t rev:4; /* Revision */ 260997207482SJames Smart uint32_t lev:2; /* Level */ 261097207482SJames Smart uint32_t dist:2; /* Dist Type */ 261197207482SJames Smart uint32_t num:4; /* number after dist type */ 261297207482SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 261397207482SJames Smart uint32_t num:4; /* number after dist type */ 261497207482SJames Smart uint32_t dist:2; /* Dist Type */ 261597207482SJames Smart uint32_t lev:2; /* Level */ 261697207482SJames Smart uint32_t rev:4; /* Revision */ 261797207482SJames Smart uint32_t ver:4; /* Major Version */ 261897207482SJames Smart uint8_t id; 261997207482SJames Smart uint8_t type; 262097207482SJames Smart #endif 262197207482SJames Smart }; 262297207482SJames Smart 2623d7c255b2SJames Smart /* Structure for MB Command UPDATE_CFG (0x1B) */ 2624d7c255b2SJames Smart 2625d7c255b2SJames Smart struct update_cfg_var { 2626d7c255b2SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2627d7c255b2SJames Smart uint32_t rsvd2:16; 2628d7c255b2SJames Smart uint32_t type:8; 2629d7c255b2SJames Smart uint32_t rsvd:1; 2630d7c255b2SJames Smart uint32_t ra:1; 2631d7c255b2SJames Smart uint32_t co:1; 2632d7c255b2SJames Smart uint32_t cv:1; 2633d7c255b2SJames Smart uint32_t req:4; 2634d7c255b2SJames Smart uint32_t entry_length:16; 2635d7c255b2SJames Smart uint32_t region_id:16; 2636d7c255b2SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 2637d7c255b2SJames Smart uint32_t req:4; 2638d7c255b2SJames Smart uint32_t cv:1; 2639d7c255b2SJames Smart uint32_t co:1; 2640d7c255b2SJames Smart uint32_t ra:1; 2641d7c255b2SJames Smart uint32_t rsvd:1; 2642d7c255b2SJames Smart uint32_t type:8; 2643d7c255b2SJames Smart uint32_t rsvd2:16; 2644d7c255b2SJames Smart uint32_t region_id:16; 2645d7c255b2SJames Smart uint32_t entry_length:16; 2646d7c255b2SJames Smart #endif 2647d7c255b2SJames Smart 2648d7c255b2SJames Smart uint32_t resp_info; 2649d7c255b2SJames Smart uint32_t byte_cnt; 2650d7c255b2SJames Smart uint32_t data_offset; 2651d7c255b2SJames Smart }; 2652d7c255b2SJames Smart 2653ed957684SJames Smart struct hbq_mask { 2654ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2655ed957684SJames Smart uint8_t tmatch; 2656ed957684SJames Smart uint8_t tmask; 2657ed957684SJames Smart uint8_t rctlmatch; 2658ed957684SJames Smart uint8_t rctlmask; 2659ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2660ed957684SJames Smart uint8_t rctlmask; 2661ed957684SJames Smart uint8_t rctlmatch; 2662ed957684SJames Smart uint8_t tmask; 2663ed957684SJames Smart uint8_t tmatch; 2664ed957684SJames Smart #endif 2665ed957684SJames Smart }; 2666ed957684SJames Smart 2667ed957684SJames Smart 2668ed957684SJames Smart /* Structure for MB Command CONFIG_HBQ (7c) */ 2669ed957684SJames Smart 2670ed957684SJames Smart struct config_hbq_var { 2671ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2672ed957684SJames Smart uint32_t rsvd1 :7; 2673ed957684SJames Smart uint32_t recvNotify :1; /* Receive Notification */ 2674ed957684SJames Smart uint32_t numMask :8; /* # Mask Entries */ 2675ed957684SJames Smart uint32_t profile :8; /* Selection Profile */ 2676ed957684SJames Smart uint32_t rsvd2 :8; 2677ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2678ed957684SJames Smart uint32_t rsvd2 :8; 2679ed957684SJames Smart uint32_t profile :8; /* Selection Profile */ 2680ed957684SJames Smart uint32_t numMask :8; /* # Mask Entries */ 2681ed957684SJames Smart uint32_t recvNotify :1; /* Receive Notification */ 2682ed957684SJames Smart uint32_t rsvd1 :7; 2683ed957684SJames Smart #endif 2684ed957684SJames Smart 2685ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2686ed957684SJames Smart uint32_t hbqId :16; 2687ed957684SJames Smart uint32_t rsvd3 :12; 2688ed957684SJames Smart uint32_t ringMask :4; 2689ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2690ed957684SJames Smart uint32_t ringMask :4; 2691ed957684SJames Smart uint32_t rsvd3 :12; 2692ed957684SJames Smart uint32_t hbqId :16; 2693ed957684SJames Smart #endif 2694ed957684SJames Smart 2695ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2696ed957684SJames Smart uint32_t entry_count :16; 2697ed957684SJames Smart uint32_t rsvd4 :8; 2698ed957684SJames Smart uint32_t headerLen :8; 2699ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2700ed957684SJames Smart uint32_t headerLen :8; 2701ed957684SJames Smart uint32_t rsvd4 :8; 2702ed957684SJames Smart uint32_t entry_count :16; 2703ed957684SJames Smart #endif 2704ed957684SJames Smart 2705ed957684SJames Smart uint32_t hbqaddrLow; 2706ed957684SJames Smart uint32_t hbqaddrHigh; 2707ed957684SJames Smart 2708ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2709ed957684SJames Smart uint32_t rsvd5 :31; 2710ed957684SJames Smart uint32_t logEntry :1; 2711ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2712ed957684SJames Smart uint32_t logEntry :1; 2713ed957684SJames Smart uint32_t rsvd5 :31; 2714ed957684SJames Smart #endif 2715ed957684SJames Smart 2716ed957684SJames Smart uint32_t rsvd6; /* w7 */ 2717ed957684SJames Smart uint32_t rsvd7; /* w8 */ 2718ed957684SJames Smart uint32_t rsvd8; /* w9 */ 2719ed957684SJames Smart 2720ed957684SJames Smart struct hbq_mask hbqMasks[6]; 2721ed957684SJames Smart 2722ed957684SJames Smart 2723ed957684SJames Smart union { 2724ed957684SJames Smart uint32_t allprofiles[12]; 2725ed957684SJames Smart 2726ed957684SJames Smart struct { 2727ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2728ed957684SJames Smart uint32_t seqlenoff :16; 2729ed957684SJames Smart uint32_t maxlen :16; 2730ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2731ed957684SJames Smart uint32_t maxlen :16; 2732ed957684SJames Smart uint32_t seqlenoff :16; 2733ed957684SJames Smart #endif 2734ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2735ed957684SJames Smart uint32_t rsvd1 :28; 2736ed957684SJames Smart uint32_t seqlenbcnt :4; 2737ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2738ed957684SJames Smart uint32_t seqlenbcnt :4; 2739ed957684SJames Smart uint32_t rsvd1 :28; 2740ed957684SJames Smart #endif 2741ed957684SJames Smart uint32_t rsvd[10]; 2742ed957684SJames Smart } profile2; 2743ed957684SJames Smart 2744ed957684SJames Smart struct { 2745ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2746ed957684SJames Smart uint32_t seqlenoff :16; 2747ed957684SJames Smart uint32_t maxlen :16; 2748ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2749ed957684SJames Smart uint32_t maxlen :16; 2750ed957684SJames Smart uint32_t seqlenoff :16; 2751ed957684SJames Smart #endif 2752ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2753ed957684SJames Smart uint32_t cmdcodeoff :28; 2754ed957684SJames Smart uint32_t rsvd1 :12; 2755ed957684SJames Smart uint32_t seqlenbcnt :4; 2756ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2757ed957684SJames Smart uint32_t seqlenbcnt :4; 2758ed957684SJames Smart uint32_t rsvd1 :12; 2759ed957684SJames Smart uint32_t cmdcodeoff :28; 2760ed957684SJames Smart #endif 2761ed957684SJames Smart uint32_t cmdmatch[8]; 2762ed957684SJames Smart 2763ed957684SJames Smart uint32_t rsvd[2]; 2764ed957684SJames Smart } profile3; 2765ed957684SJames Smart 2766ed957684SJames Smart struct { 2767ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2768ed957684SJames Smart uint32_t seqlenoff :16; 2769ed957684SJames Smart uint32_t maxlen :16; 2770ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2771ed957684SJames Smart uint32_t maxlen :16; 2772ed957684SJames Smart uint32_t seqlenoff :16; 2773ed957684SJames Smart #endif 2774ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2775ed957684SJames Smart uint32_t cmdcodeoff :28; 2776ed957684SJames Smart uint32_t rsvd1 :12; 2777ed957684SJames Smart uint32_t seqlenbcnt :4; 2778ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2779ed957684SJames Smart uint32_t seqlenbcnt :4; 2780ed957684SJames Smart uint32_t rsvd1 :12; 2781ed957684SJames Smart uint32_t cmdcodeoff :28; 2782ed957684SJames Smart #endif 2783ed957684SJames Smart uint32_t cmdmatch[8]; 2784ed957684SJames Smart 2785ed957684SJames Smart uint32_t rsvd[2]; 2786ed957684SJames Smart } profile5; 2787ed957684SJames Smart 2788ed957684SJames Smart } profiles; 2789ed957684SJames Smart 2790ed957684SJames Smart }; 2791ed957684SJames Smart 2792ed957684SJames Smart 2793dea3101eS 27942e0fef85SJames Smart /* Structure for MB Command CONFIG_PORT (0x88) */ 2795dea3101eS typedef struct { 2796ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2797ed957684SJames Smart uint32_t cBE : 1; 2798ed957684SJames Smart uint32_t cET : 1; 2799ed957684SJames Smart uint32_t cHpcb : 1; 2800ed957684SJames Smart uint32_t cMA : 1; 2801ed957684SJames Smart uint32_t sli_mode : 4; 2802ed957684SJames Smart uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2803ed957684SJames Smart * config block */ 2804ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2805ed957684SJames Smart uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2806ed957684SJames Smart * config block */ 2807ed957684SJames Smart uint32_t sli_mode : 4; 2808ed957684SJames Smart uint32_t cMA : 1; 2809ed957684SJames Smart uint32_t cHpcb : 1; 2810ed957684SJames Smart uint32_t cET : 1; 2811ed957684SJames Smart uint32_t cBE : 1; 2812ed957684SJames Smart #endif 2813ed957684SJames Smart 2814dea3101eS uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2815dea3101eS uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 281697207482SJames Smart uint32_t hbainit[5]; 281797207482SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 281897207482SJames Smart uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 281997207482SJames Smart uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 282097207482SJames Smart #else /* __LITTLE_ENDIAN */ 282197207482SJames Smart uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 282297207482SJames Smart uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 282397207482SJames Smart #endif 2824ed957684SJames Smart 2825ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2826da0436e9SJames Smart uint32_t rsvd1 : 19; /* Reserved */ 2827da0436e9SJames Smart uint32_t cdss : 1; /* Configure Data Security SLI */ 2828cb69f7deSJames Smart uint32_t casabt : 1; /* Configure async abts status notice */ 2829cb69f7deSJames Smart uint32_t rsvd2 : 2; /* Reserved */ 283081301a9bSJames Smart uint32_t cbg : 1; /* Configure BlockGuard */ 2831ed957684SJames Smart uint32_t cmv : 1; /* Configure Max VPIs */ 2832ed957684SJames Smart uint32_t ccrp : 1; /* Config Command Ring Polling */ 2833ed957684SJames Smart uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2834ed957684SJames Smart uint32_t chbs : 1; /* Cofigure Host Backing store */ 2835ed957684SJames Smart uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2836ed957684SJames Smart uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2837ed957684SJames Smart uint32_t cmx : 1; /* Configure Max XRIs */ 2838ed957684SJames Smart uint32_t cmr : 1; /* Configure Max RPIs */ 2839ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2840ed957684SJames Smart uint32_t cmr : 1; /* Configure Max RPIs */ 2841ed957684SJames Smart uint32_t cmx : 1; /* Configure Max XRIs */ 2842ed957684SJames Smart uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2843ed957684SJames Smart uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2844ed957684SJames Smart uint32_t chbs : 1; /* Cofigure Host Backing store */ 2845ed957684SJames Smart uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2846ed957684SJames Smart uint32_t ccrp : 1; /* Config Command Ring Polling */ 2847ed957684SJames Smart uint32_t cmv : 1; /* Configure Max VPIs */ 284881301a9bSJames Smart uint32_t cbg : 1; /* Configure BlockGuard */ 2849cb69f7deSJames Smart uint32_t rsvd2 : 2; /* Reserved */ 2850cb69f7deSJames Smart uint32_t casabt : 1; /* Configure async abts status notice */ 2851da0436e9SJames Smart uint32_t cdss : 1; /* Configure Data Security SLI */ 2852da0436e9SJames Smart uint32_t rsvd1 : 19; /* Reserved */ 2853ed957684SJames Smart #endif 2854ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2855da0436e9SJames Smart uint32_t rsvd3 : 19; /* Reserved */ 2856da0436e9SJames Smart uint32_t gdss : 1; /* Configure Data Security SLI */ 2857cb69f7deSJames Smart uint32_t gasabt : 1; /* Grant async abts status notice */ 2858cb69f7deSJames Smart uint32_t rsvd4 : 2; /* Reserved */ 285981301a9bSJames Smart uint32_t gbg : 1; /* Grant BlockGuard */ 2860ed957684SJames Smart uint32_t gmv : 1; /* Grant Max VPIs */ 2861ed957684SJames Smart uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2862ed957684SJames Smart uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2863ed957684SJames Smart uint32_t ghbs : 1; /* Grant Host Backing Store */ 2864ed957684SJames Smart uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2865ed957684SJames Smart uint32_t gerbm : 1; /* Grant ERBM Request */ 2866ed957684SJames Smart uint32_t gmx : 1; /* Grant Max XRIs */ 2867ed957684SJames Smart uint32_t gmr : 1; /* Grant Max RPIs */ 2868ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2869ed957684SJames Smart uint32_t gmr : 1; /* Grant Max RPIs */ 2870ed957684SJames Smart uint32_t gmx : 1; /* Grant Max XRIs */ 2871ed957684SJames Smart uint32_t gerbm : 1; /* Grant ERBM Request */ 2872ed957684SJames Smart uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2873ed957684SJames Smart uint32_t ghbs : 1; /* Grant Host Backing Store */ 2874ed957684SJames Smart uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2875ed957684SJames Smart uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2876ed957684SJames Smart uint32_t gmv : 1; /* Grant Max VPIs */ 287781301a9bSJames Smart uint32_t gbg : 1; /* Grant BlockGuard */ 2878cb69f7deSJames Smart uint32_t rsvd4 : 2; /* Reserved */ 2879cb69f7deSJames Smart uint32_t gasabt : 1; /* Grant async abts status notice */ 2880da0436e9SJames Smart uint32_t gdss : 1; /* Configure Data Security SLI */ 2881da0436e9SJames Smart uint32_t rsvd3 : 19; /* Reserved */ 2882ed957684SJames Smart #endif 2883ed957684SJames Smart 2884ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2885ed957684SJames Smart uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2886ed957684SJames Smart uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2887ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2888ed957684SJames Smart uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2889ed957684SJames Smart uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2890ed957684SJames Smart #endif 2891ed957684SJames Smart 2892ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2893ed957684SJames Smart uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2894da0436e9SJames Smart uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2895ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2896da0436e9SJames Smart uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2897ed957684SJames Smart uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2898ed957684SJames Smart #endif 2899ed957684SJames Smart 2900da0436e9SJames Smart uint32_t rsvd6; /* Reserved */ 2901ed957684SJames Smart 2902ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2903bc73905aSJames Smart uint32_t fips_rev : 3; /* FIPS Spec Revision */ 2904bc73905aSJames Smart uint32_t fips_level : 4; /* FIPS Level */ 2905bc73905aSJames Smart uint32_t sec_err : 9; /* security crypto error */ 2906ed957684SJames Smart uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2907ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2908ed957684SJames Smart uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2909bc73905aSJames Smart uint32_t sec_err : 9; /* security crypto error */ 2910bc73905aSJames Smart uint32_t fips_level : 4; /* FIPS Level */ 2911bc73905aSJames Smart uint32_t fips_rev : 3; /* FIPS Spec Revision */ 2912ed957684SJames Smart #endif 2913ed957684SJames Smart 2914dea3101eS } CONFIG_PORT_VAR; 2915dea3101eS 29169399627fSJames Smart /* Structure for MB Command CONFIG_MSI (0x30) */ 29179399627fSJames Smart struct config_msi_var { 29189399627fSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 29199399627fSJames Smart uint32_t dfltMsgNum:8; /* Default message number */ 29209399627fSJames Smart uint32_t rsvd1:11; /* Reserved */ 29219399627fSJames Smart uint32_t NID:5; /* Number of secondary attention IDs */ 29229399627fSJames Smart uint32_t rsvd2:5; /* Reserved */ 29239399627fSJames Smart uint32_t dfltPresent:1; /* Default message number present */ 29249399627fSJames Smart uint32_t addFlag:1; /* Add association flag */ 29259399627fSJames Smart uint32_t reportFlag:1; /* Report association flag */ 29269399627fSJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 29279399627fSJames Smart uint32_t reportFlag:1; /* Report association flag */ 29289399627fSJames Smart uint32_t addFlag:1; /* Add association flag */ 29299399627fSJames Smart uint32_t dfltPresent:1; /* Default message number present */ 29309399627fSJames Smart uint32_t rsvd2:5; /* Reserved */ 29319399627fSJames Smart uint32_t NID:5; /* Number of secondary attention IDs */ 29329399627fSJames Smart uint32_t rsvd1:11; /* Reserved */ 29339399627fSJames Smart uint32_t dfltMsgNum:8; /* Default message number */ 29349399627fSJames Smart #endif 29359399627fSJames Smart uint32_t attentionConditions[2]; 29369399627fSJames Smart uint8_t attentionId[16]; 29379399627fSJames Smart uint8_t messageNumberByHA[64]; 29389399627fSJames Smart uint8_t messageNumberByID[16]; 29399399627fSJames Smart uint32_t autoClearHA[2]; 29409399627fSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 29419399627fSJames Smart uint32_t rsvd3:16; 29429399627fSJames Smart uint32_t autoClearID:16; 29439399627fSJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 29449399627fSJames Smart uint32_t autoClearID:16; 29459399627fSJames Smart uint32_t rsvd3:16; 29469399627fSJames Smart #endif 29479399627fSJames Smart uint32_t rsvd4; 29489399627fSJames Smart }; 29499399627fSJames Smart 2950dea3101eS /* SLI-2 Port Control Block */ 2951dea3101eS 2952dea3101eS /* SLIM POINTER */ 2953dea3101eS #define SLIMOFF 0x30 /* WORD */ 2954dea3101eS 2955dea3101eS typedef struct _SLI2_RDSC { 2956dea3101eS uint32_t cmdEntries; 2957dea3101eS uint32_t cmdAddrLow; 2958dea3101eS uint32_t cmdAddrHigh; 2959dea3101eS 2960dea3101eS uint32_t rspEntries; 2961dea3101eS uint32_t rspAddrLow; 2962dea3101eS uint32_t rspAddrHigh; 2963dea3101eS } SLI2_RDSC; 2964dea3101eS 2965dea3101eS typedef struct _PCB { 2966dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2967dea3101eS uint32_t type:8; 2968497888cfSPhil Carmody #define TYPE_NATIVE_SLI2 0x01 2969dea3101eS uint32_t feature:8; 2970497888cfSPhil Carmody #define FEATURE_INITIAL_SLI2 0x01 2971dea3101eS uint32_t rsvd:12; 2972dea3101eS uint32_t maxRing:4; 2973dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2974dea3101eS uint32_t maxRing:4; 2975dea3101eS uint32_t rsvd:12; 2976dea3101eS uint32_t feature:8; 2977497888cfSPhil Carmody #define FEATURE_INITIAL_SLI2 0x01 2978dea3101eS uint32_t type:8; 2979497888cfSPhil Carmody #define TYPE_NATIVE_SLI2 0x01 2980dea3101eS #endif 2981dea3101eS 2982dea3101eS uint32_t mailBoxSize; 2983dea3101eS uint32_t mbAddrLow; 2984dea3101eS uint32_t mbAddrHigh; 2985dea3101eS 2986dea3101eS uint32_t hgpAddrLow; 2987dea3101eS uint32_t hgpAddrHigh; 2988dea3101eS 2989dea3101eS uint32_t pgpAddrLow; 2990dea3101eS uint32_t pgpAddrHigh; 2991dea3101eS SLI2_RDSC rdsc[MAX_RINGS]; 2992dea3101eS } PCB_t; 2993dea3101eS 2994dea3101eS /* NEW_FEATURE */ 2995dea3101eS typedef struct { 2996dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2997dea3101eS uint32_t rsvd0:27; 2998dea3101eS uint32_t discardFarp:1; 2999dea3101eS uint32_t IPEnable:1; 3000dea3101eS uint32_t nodeName:1; 3001dea3101eS uint32_t portName:1; 3002dea3101eS uint32_t filterEnable:1; 3003dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3004dea3101eS uint32_t filterEnable:1; 3005dea3101eS uint32_t portName:1; 3006dea3101eS uint32_t nodeName:1; 3007dea3101eS uint32_t IPEnable:1; 3008dea3101eS uint32_t discardFarp:1; 3009dea3101eS uint32_t rsvd:27; 3010dea3101eS #endif 3011dea3101eS 3012dea3101eS uint8_t portname[8]; /* Used to be struct lpfc_name */ 3013dea3101eS uint8_t nodename[8]; 3014dea3101eS uint32_t rsvd1; 3015dea3101eS uint32_t rsvd2; 3016dea3101eS uint32_t rsvd3; 3017dea3101eS uint32_t IPAddress; 3018dea3101eS } CONFIG_FARP_VAR; 3019dea3101eS 302057127f15SJames Smart /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 302157127f15SJames Smart 302257127f15SJames Smart typedef struct { 302357127f15SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 302457127f15SJames Smart uint32_t rsvd:30; 302557127f15SJames Smart uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 302657127f15SJames Smart #else /* __LITTLE_ENDIAN */ 302757127f15SJames Smart uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 302857127f15SJames Smart uint32_t rsvd:30; 302957127f15SJames Smart #endif 303057127f15SJames Smart } ASYNCEVT_ENABLE_VAR; 303157127f15SJames Smart 3032dea3101eS /* Union of all Mailbox Command types */ 3033dea3101eS #define MAILBOX_CMD_WSIZE 32 3034dea3101eS #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 30357a470277SJames Smart /* ext_wsize times 4 bytes should not be greater than max xmit size */ 30367a470277SJames Smart #define MAILBOX_EXT_WSIZE 512 30377a470277SJames Smart #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 30387a470277SJames Smart #define MAILBOX_HBA_EXT_OFFSET 0x100 30397a470277SJames Smart /* max mbox xmit size is a page size for sysfs IO operations */ 3040c0c11512SJames Smart #define MAILBOX_SYSFS_MAX 4096 3041dea3101eS 3042dea3101eS typedef union { 3043ed957684SJames Smart uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3044ed957684SJames Smart * feature/max ring number 3045ed957684SJames Smart */ 3046dea3101eS LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3047dea3101eS READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3048dea3101eS WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3049dea3101eS BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3050dea3101eS INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3051dea3101eS DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3052dea3101eS CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3053dea3101eS PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3054dea3101eS CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3055dea3101eS RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3056dea3101eS READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3057dea3101eS READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3058dea3101eS READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3059dea3101eS READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3060dea3101eS READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3061dea3101eS READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3062dea3101eS READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3063dea3101eS READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3064dea3101eS REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3065dea3101eS UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3066dea3101eS CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3067dea3101eS DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3068dea3101eS UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3069ed957684SJames Smart CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3070ed957684SJames Smart * NEW_FEATURE 3071ed957684SJames Smart */ 3072ed957684SJames Smart struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3073d7c255b2SJames Smart struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3074dea3101eS CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 307576a95d75SJames Smart struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 307692d7f7b0SJames Smart REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 307792d7f7b0SJames Smart UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 307857127f15SJames Smart ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3079c7495937SJames Smart struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3080c7495937SJames Smart * (READ_EVENT_LOG) 3081c7495937SJames Smart */ 30829399627fSJames Smart struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3083dea3101eS } MAILVARIANTS; 3084dea3101eS 3085dea3101eS /* 3086dea3101eS * SLI-2 specific structures 3087dea3101eS */ 3088dea3101eS 30894cc2da1dSJames.Smart@Emulex.Com struct lpfc_hgp { 30904cc2da1dSJames.Smart@Emulex.Com __le32 cmdPutInx; 30914cc2da1dSJames.Smart@Emulex.Com __le32 rspGetInx; 30924cc2da1dSJames.Smart@Emulex.Com }; 3093dea3101eS 30944cc2da1dSJames.Smart@Emulex.Com struct lpfc_pgp { 30954cc2da1dSJames.Smart@Emulex.Com __le32 cmdGetInx; 30964cc2da1dSJames.Smart@Emulex.Com __le32 rspPutInx; 30974cc2da1dSJames.Smart@Emulex.Com }; 3098dea3101eS 3099ed957684SJames Smart struct sli2_desc { 3100dea3101eS uint32_t unused1[16]; 3101ed957684SJames Smart struct lpfc_hgp host[MAX_RINGS]; 31024cc2da1dSJames.Smart@Emulex.Com struct lpfc_pgp port[MAX_RINGS]; 3103ed957684SJames Smart }; 3104ed957684SJames Smart 3105ed957684SJames Smart struct sli3_desc { 3106ed957684SJames Smart struct lpfc_hgp host[MAX_RINGS]; 3107ed957684SJames Smart uint32_t reserved[8]; 3108ed957684SJames Smart uint32_t hbq_put[16]; 3109ed957684SJames Smart }; 3110ed957684SJames Smart 3111ed957684SJames Smart struct sli3_pgp { 3112ed957684SJames Smart struct lpfc_pgp port[MAX_RINGS]; 3113ed957684SJames Smart uint32_t hbq_get[16]; 3114ed957684SJames Smart }; 3115dea3101eS 311634b02dcdSJames Smart union sli_var { 3117ed957684SJames Smart struct sli2_desc s2; 3118ed957684SJames Smart struct sli3_desc s3; 3119ed957684SJames Smart struct sli3_pgp s3_pgp; 312034b02dcdSJames Smart }; 3121dea3101eS 3122dea3101eS typedef struct { 3123dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3124dea3101eS uint16_t mbxStatus; 3125dea3101eS uint8_t mbxCommand; 3126dea3101eS uint8_t mbxReserved:6; 3127dea3101eS uint8_t mbxHc:1; 3128dea3101eS uint8_t mbxOwner:1; /* Low order bit first word */ 3129dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3130dea3101eS uint8_t mbxOwner:1; /* Low order bit first word */ 3131dea3101eS uint8_t mbxHc:1; 3132dea3101eS uint8_t mbxReserved:6; 3133dea3101eS uint8_t mbxCommand; 3134dea3101eS uint16_t mbxStatus; 3135dea3101eS #endif 3136dea3101eS 3137dea3101eS MAILVARIANTS un; 313834b02dcdSJames Smart union sli_var us; 3139dea3101eS } MAILBOX_t; 3140dea3101eS 3141dea3101eS /* 3142dea3101eS * Begin Structure Definitions for IOCB Commands 3143dea3101eS */ 3144dea3101eS 3145dea3101eS typedef struct { 3146dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3147dea3101eS uint8_t statAction; 3148dea3101eS uint8_t statRsn; 3149dea3101eS uint8_t statBaExp; 3150dea3101eS uint8_t statLocalError; 3151dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3152dea3101eS uint8_t statLocalError; 3153dea3101eS uint8_t statBaExp; 3154dea3101eS uint8_t statRsn; 3155dea3101eS uint8_t statAction; 3156dea3101eS #endif 3157dea3101eS /* statRsn P/F_RJT reason codes */ 3158dea3101eS #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3159dea3101eS #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3160dea3101eS #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3161dea3101eS #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3162dea3101eS #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3163dea3101eS #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3164dea3101eS #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3165dea3101eS #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3166dea3101eS #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3167dea3101eS #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3168dea3101eS #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3169dea3101eS #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3170dea3101eS #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3171dea3101eS #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3172dea3101eS #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3173dea3101eS #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3174dea3101eS #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3175dea3101eS #define RJT_PROT_ERR 0x12 /* Protocol error */ 3176dea3101eS #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3177dea3101eS #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3178dea3101eS #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3179dea3101eS #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3180dea3101eS #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3181dea3101eS #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3182dea3101eS #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3183dea3101eS #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3184dea3101eS 3185dea3101eS #define IOERR_SUCCESS 0x00 /* statLocalError */ 3186dea3101eS #define IOERR_MISSING_CONTINUE 0x01 3187dea3101eS #define IOERR_SEQUENCE_TIMEOUT 0x02 3188dea3101eS #define IOERR_INTERNAL_ERROR 0x03 3189dea3101eS #define IOERR_INVALID_RPI 0x04 3190dea3101eS #define IOERR_NO_XRI 0x05 3191dea3101eS #define IOERR_ILLEGAL_COMMAND 0x06 3192dea3101eS #define IOERR_XCHG_DROPPED 0x07 3193dea3101eS #define IOERR_ILLEGAL_FIELD 0x08 3194dea3101eS #define IOERR_BAD_CONTINUE 0x09 3195dea3101eS #define IOERR_TOO_MANY_BUFFERS 0x0A 3196dea3101eS #define IOERR_RCV_BUFFER_WAITING 0x0B 3197dea3101eS #define IOERR_NO_CONNECTION 0x0C 3198dea3101eS #define IOERR_TX_DMA_FAILED 0x0D 3199dea3101eS #define IOERR_RX_DMA_FAILED 0x0E 3200dea3101eS #define IOERR_ILLEGAL_FRAME 0x0F 3201dea3101eS #define IOERR_EXTRA_DATA 0x10 3202dea3101eS #define IOERR_NO_RESOURCES 0x11 3203dea3101eS #define IOERR_RESERVED 0x12 3204dea3101eS #define IOERR_ILLEGAL_LENGTH 0x13 3205dea3101eS #define IOERR_UNSUPPORTED_FEATURE 0x14 3206dea3101eS #define IOERR_ABORT_IN_PROGRESS 0x15 3207dea3101eS #define IOERR_ABORT_REQUESTED 0x16 3208dea3101eS #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3209dea3101eS #define IOERR_LOOP_OPEN_FAILURE 0x18 3210dea3101eS #define IOERR_RING_RESET 0x19 3211dea3101eS #define IOERR_LINK_DOWN 0x1A 3212dea3101eS #define IOERR_CORRUPTED_DATA 0x1B 3213dea3101eS #define IOERR_CORRUPTED_RPI 0x1C 3214dea3101eS #define IOERR_OUT_OF_ORDER_DATA 0x1D 3215dea3101eS #define IOERR_OUT_OF_ORDER_ACK 0x1E 3216dea3101eS #define IOERR_DUP_FRAME 0x1F 3217dea3101eS #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3218dea3101eS #define IOERR_BAD_HOST_ADDRESS 0x21 3219dea3101eS #define IOERR_RCV_HDRBUF_WAITING 0x22 3220dea3101eS #define IOERR_MISSING_HDR_BUFFER 0x23 3221dea3101eS #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3222dea3101eS #define IOERR_ABORTMULT_REQUESTED 0x25 3223dea3101eS #define IOERR_BUFFER_SHORTAGE 0x28 3224dea3101eS #define IOERR_DEFAULT 0x29 3225dea3101eS #define IOERR_CNT 0x2A 3226b92938b4SJames Smart #define IOERR_SLER_FAILURE 0x46 3227b92938b4SJames Smart #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3228b92938b4SJames Smart #define IOERR_SLER_REC_RJT_ERR 0x48 3229b92938b4SJames Smart #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3230b92938b4SJames Smart #define IOERR_SLER_SRR_RJT_ERR 0x4A 3231b92938b4SJames Smart #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3232b92938b4SJames Smart #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3233b92938b4SJames Smart #define IOERR_SLER_ABTS_ERR 0x4E 3234ab56dc2eSJames Smart #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3235ab56dc2eSJames Smart #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3236ab56dc2eSJames Smart #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3237ab56dc2eSJames Smart #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3238dea3101eS #define IOERR_DRVR_MASK 0x100 3239dea3101eS #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3240dea3101eS #define IOERR_SLI_BRESET 0x102 3241dea3101eS #define IOERR_SLI_ABORTED 0x103 3242dea3101eS } PARM_ERR; 3243dea3101eS 3244dea3101eS typedef union { 3245dea3101eS struct { 3246dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3247dea3101eS uint8_t Rctl; /* R_CTL field */ 3248dea3101eS uint8_t Type; /* TYPE field */ 3249dea3101eS uint8_t Dfctl; /* DF_CTL field */ 3250dea3101eS uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3251dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3252dea3101eS uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3253dea3101eS uint8_t Dfctl; /* DF_CTL field */ 3254dea3101eS uint8_t Type; /* TYPE field */ 3255dea3101eS uint8_t Rctl; /* R_CTL field */ 3256dea3101eS #endif 3257dea3101eS 3258dea3101eS #define BC 0x02 /* Broadcast Received - Fctl */ 3259dea3101eS #define SI 0x04 /* Sequence Initiative */ 3260dea3101eS #define LA 0x08 /* Ignore Link Attention state */ 3261dea3101eS #define LS 0x80 /* Last Sequence */ 3262dea3101eS } hcsw; 3263dea3101eS uint32_t reserved; 3264dea3101eS } WORD5; 3265dea3101eS 3266dea3101eS /* IOCB Command template for a generic response */ 3267dea3101eS typedef struct { 3268dea3101eS uint32_t reserved[4]; 3269dea3101eS PARM_ERR perr; 3270dea3101eS } GENERIC_RSP; 3271dea3101eS 3272dea3101eS /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3273dea3101eS typedef struct { 3274dea3101eS struct ulp_bde xrsqbde[2]; 3275dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3276dea3101eS WORD5 w5; /* Header control/status word */ 3277dea3101eS } XR_SEQ_FIELDS; 3278dea3101eS 3279dea3101eS /* IOCB Command template for ELS_REQUEST */ 3280dea3101eS typedef struct { 3281dea3101eS struct ulp_bde elsReq; 3282dea3101eS struct ulp_bde elsRsp; 3283dea3101eS 3284dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3285dea3101eS uint32_t word4Rsvd:7; 3286dea3101eS uint32_t fl:1; 3287dea3101eS uint32_t myID:24; 3288dea3101eS uint32_t word5Rsvd:8; 3289dea3101eS uint32_t remoteID:24; 3290dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3291dea3101eS uint32_t myID:24; 3292dea3101eS uint32_t fl:1; 3293dea3101eS uint32_t word4Rsvd:7; 3294dea3101eS uint32_t remoteID:24; 3295dea3101eS uint32_t word5Rsvd:8; 3296dea3101eS #endif 3297dea3101eS } ELS_REQUEST; 3298dea3101eS 3299dea3101eS /* IOCB Command template for RCV_ELS_REQ */ 3300dea3101eS typedef struct { 3301dea3101eS struct ulp_bde elsReq[2]; 3302dea3101eS uint32_t parmRo; 3303dea3101eS 3304dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3305dea3101eS uint32_t word5Rsvd:8; 3306dea3101eS uint32_t remoteID:24; 3307dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3308dea3101eS uint32_t remoteID:24; 3309dea3101eS uint32_t word5Rsvd:8; 3310dea3101eS #endif 3311dea3101eS } RCV_ELS_REQ; 3312dea3101eS 3313dea3101eS /* IOCB Command template for ABORT / CLOSE_XRI */ 3314dea3101eS typedef struct { 3315dea3101eS uint32_t rsvd[3]; 3316dea3101eS uint32_t abortType; 3317dea3101eS #define ABORT_TYPE_ABTX 0x00000000 3318dea3101eS #define ABORT_TYPE_ABTS 0x00000001 3319dea3101eS uint32_t parm; 3320dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3321dea3101eS uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3322dea3101eS uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3323dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3324dea3101eS uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3325dea3101eS uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3326dea3101eS #endif 3327dea3101eS } AC_XRI; 3328dea3101eS 3329dea3101eS /* IOCB Command template for ABORT_MXRI64 */ 3330dea3101eS typedef struct { 3331dea3101eS uint32_t rsvd[3]; 3332dea3101eS uint32_t abortType; 3333dea3101eS uint32_t parm; 3334dea3101eS uint32_t iotag32; 3335dea3101eS } A_MXRI64; 3336dea3101eS 3337dea3101eS /* IOCB Command template for GET_RPI */ 3338dea3101eS typedef struct { 3339dea3101eS uint32_t rsvd[4]; 3340dea3101eS uint32_t parmRo; 3341dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3342dea3101eS uint32_t word5Rsvd:8; 3343dea3101eS uint32_t remoteID:24; 3344dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3345dea3101eS uint32_t remoteID:24; 3346dea3101eS uint32_t word5Rsvd:8; 3347dea3101eS #endif 3348dea3101eS } GET_RPI; 3349dea3101eS 3350dea3101eS /* IOCB Command template for all FCP Initiator commands */ 3351dea3101eS typedef struct { 3352dea3101eS struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3353dea3101eS struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3354dea3101eS uint32_t fcpi_parm; 3355dea3101eS uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3356dea3101eS } FCPI_FIELDS; 3357dea3101eS 3358dea3101eS /* IOCB Command template for all FCP Target commands */ 3359dea3101eS typedef struct { 3360dea3101eS struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3361dea3101eS uint32_t fcpt_Offset; 3362dea3101eS uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3363dea3101eS } FCPT_FIELDS; 3364dea3101eS 3365dea3101eS /* SLI-2 IOCB structure definitions */ 3366dea3101eS 3367dea3101eS /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3368dea3101eS typedef struct { 3369dea3101eS ULP_BDL bdl; 3370dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3371dea3101eS WORD5 w5; /* Header control/status word */ 3372dea3101eS } XMT_SEQ_FIELDS64; 3373dea3101eS 3374dea3101eS /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3375dea3101eS typedef struct { 3376dea3101eS struct ulp_bde64 rcvBde; 3377dea3101eS uint32_t rsvd1; 3378dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3379dea3101eS WORD5 w5; /* Header control/status word */ 3380dea3101eS } RCV_SEQ_FIELDS64; 3381dea3101eS 3382dea3101eS /* IOCB Command template for ELS_REQUEST64 */ 3383dea3101eS typedef struct { 3384dea3101eS ULP_BDL bdl; 3385dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3386dea3101eS uint32_t word4Rsvd:7; 3387dea3101eS uint32_t fl:1; 3388dea3101eS uint32_t myID:24; 3389dea3101eS uint32_t word5Rsvd:8; 3390dea3101eS uint32_t remoteID:24; 3391dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3392dea3101eS uint32_t myID:24; 3393dea3101eS uint32_t fl:1; 3394dea3101eS uint32_t word4Rsvd:7; 3395dea3101eS uint32_t remoteID:24; 3396dea3101eS uint32_t word5Rsvd:8; 3397dea3101eS #endif 3398dea3101eS } ELS_REQUEST64; 3399dea3101eS 3400dea3101eS /* IOCB Command template for GEN_REQUEST64 */ 3401dea3101eS typedef struct { 3402dea3101eS ULP_BDL bdl; 3403dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3404dea3101eS WORD5 w5; /* Header control/status word */ 3405dea3101eS } GEN_REQUEST64; 3406dea3101eS 3407dea3101eS /* IOCB Command template for RCV_ELS_REQ64 */ 3408dea3101eS typedef struct { 3409dea3101eS struct ulp_bde64 elsReq; 3410dea3101eS uint32_t rcvd1; 3411dea3101eS uint32_t parmRo; 3412dea3101eS 3413dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3414dea3101eS uint32_t word5Rsvd:8; 3415dea3101eS uint32_t remoteID:24; 3416dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3417dea3101eS uint32_t remoteID:24; 3418dea3101eS uint32_t word5Rsvd:8; 3419dea3101eS #endif 3420dea3101eS } RCV_ELS_REQ64; 3421dea3101eS 34229c2face6SJames Smart /* IOCB Command template for RCV_SEQ64 */ 34239c2face6SJames Smart struct rcv_seq64 { 34249c2face6SJames Smart struct ulp_bde64 elsReq; 34259c2face6SJames Smart uint32_t hbq_1; 34269c2face6SJames Smart uint32_t parmRo; 34279c2face6SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 34289c2face6SJames Smart uint32_t rctl:8; 34299c2face6SJames Smart uint32_t type:8; 34309c2face6SJames Smart uint32_t dfctl:8; 34319c2face6SJames Smart uint32_t ls:1; 34329c2face6SJames Smart uint32_t fs:1; 34339c2face6SJames Smart uint32_t rsvd2:3; 34349c2face6SJames Smart uint32_t si:1; 34359c2face6SJames Smart uint32_t bc:1; 34369c2face6SJames Smart uint32_t rsvd3:1; 34379c2face6SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 34389c2face6SJames Smart uint32_t rsvd3:1; 34399c2face6SJames Smart uint32_t bc:1; 34409c2face6SJames Smart uint32_t si:1; 34419c2face6SJames Smart uint32_t rsvd2:3; 34429c2face6SJames Smart uint32_t fs:1; 34439c2face6SJames Smart uint32_t ls:1; 34449c2face6SJames Smart uint32_t dfctl:8; 34459c2face6SJames Smart uint32_t type:8; 34469c2face6SJames Smart uint32_t rctl:8; 34479c2face6SJames Smart #endif 34489c2face6SJames Smart }; 34499c2face6SJames Smart 3450dea3101eS /* IOCB Command template for all 64 bit FCP Initiator commands */ 3451dea3101eS typedef struct { 3452dea3101eS ULP_BDL bdl; 3453dea3101eS uint32_t fcpi_parm; 3454dea3101eS uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3455dea3101eS } FCPI_FIELDS64; 3456dea3101eS 3457dea3101eS /* IOCB Command template for all 64 bit FCP Target commands */ 3458dea3101eS typedef struct { 3459dea3101eS ULP_BDL bdl; 3460dea3101eS uint32_t fcpt_Offset; 3461dea3101eS uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3462dea3101eS } FCPT_FIELDS64; 3463dea3101eS 346457127f15SJames Smart /* IOCB Command template for Async Status iocb commands */ 346557127f15SJames Smart typedef struct { 346657127f15SJames Smart uint32_t rsvd[4]; 346757127f15SJames Smart uint32_t param; 346857127f15SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 346957127f15SJames Smart uint16_t evt_code; /* High order bits word 5 */ 347057127f15SJames Smart uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 347157127f15SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 347257127f15SJames Smart uint16_t sub_ctxt_tag; /* High order bits word 5 */ 347357127f15SJames Smart uint16_t evt_code; /* Low order bits word 5 */ 347457127f15SJames Smart #endif 347557127f15SJames Smart } ASYNCSTAT_FIELDS; 347657127f15SJames Smart #define ASYNC_TEMP_WARN 0x100 347757127f15SJames Smart #define ASYNC_TEMP_SAFE 0x101 3478cb69f7deSJames Smart #define ASYNC_STATUS_CN 0x102 347957127f15SJames Smart 3480ed957684SJames Smart /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3481ed957684SJames Smart or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3482ed957684SJames Smart 3483ed957684SJames Smart struct rcv_sli3 { 3484ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 34857851fe2cSJames Smart uint16_t ox_id; 34867851fe2cSJames Smart uint16_t seq_cnt; 34877851fe2cSJames Smart 3488ed957684SJames Smart uint16_t vpi; 3489ed957684SJames Smart uint16_t word9Rsvd; 3490ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 34917851fe2cSJames Smart uint16_t seq_cnt; 34927851fe2cSJames Smart uint16_t ox_id; 34937851fe2cSJames Smart 3494ed957684SJames Smart uint16_t word9Rsvd; 3495ed957684SJames Smart uint16_t vpi; 3496ed957684SJames Smart #endif 3497ed957684SJames Smart uint32_t word10Rsvd; 3498ed957684SJames Smart uint32_t acc_len; /* accumulated length */ 3499ed957684SJames Smart struct ulp_bde64 bde2; 3500ed957684SJames Smart }; 3501ed957684SJames Smart 350276bb24efSJames Smart /* Structure used for a single HBQ entry */ 350376bb24efSJames Smart struct lpfc_hbq_entry { 350476bb24efSJames Smart struct ulp_bde64 bde; 350576bb24efSJames Smart uint32_t buffer_tag; 350676bb24efSJames Smart }; 350792d7f7b0SJames Smart 350876bb24efSJames Smart /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 350976bb24efSJames Smart typedef struct { 351076bb24efSJames Smart struct lpfc_hbq_entry buff; 351176bb24efSJames Smart uint32_t rsvd; 351276bb24efSJames Smart uint32_t rsvd1; 351376bb24efSJames Smart } QUE_XRI64_CX_FIELDS; 351476bb24efSJames Smart 351576bb24efSJames Smart struct que_xri64cx_ext_fields { 351676bb24efSJames Smart uint32_t iotag64_low; 351776bb24efSJames Smart uint32_t iotag64_high; 351876bb24efSJames Smart uint32_t ebde_count; 351976bb24efSJames Smart uint32_t rsvd; 352076bb24efSJames Smart struct lpfc_hbq_entry buff[5]; 352176bb24efSJames Smart }; 352292d7f7b0SJames Smart 352381301a9bSJames Smart struct sli3_bg_fields { 352481301a9bSJames Smart uint32_t filler[6]; /* word 8-13 in IOCB */ 352581301a9bSJames Smart uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 352681301a9bSJames Smart /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 352781301a9bSJames Smart #define BGS_BIDIR_BG_PROF_MASK 0xff000000 352881301a9bSJames Smart #define BGS_BIDIR_BG_PROF_SHIFT 24 352981301a9bSJames Smart #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 353081301a9bSJames Smart #define BGS_BIDIR_ERR_COND_SHIFT 16 353181301a9bSJames Smart #define BGS_BG_PROFILE_MASK 0x0000ff00 353281301a9bSJames Smart #define BGS_BG_PROFILE_SHIFT 8 353381301a9bSJames Smart #define BGS_INVALID_PROF_MASK 0x00000020 353481301a9bSJames Smart #define BGS_INVALID_PROF_SHIFT 5 353581301a9bSJames Smart #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 353681301a9bSJames Smart #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 353781301a9bSJames Smart #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 353881301a9bSJames Smart #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 353981301a9bSJames Smart #define BGS_REFTAG_ERR_MASK 0x00000004 354081301a9bSJames Smart #define BGS_REFTAG_ERR_SHIFT 2 354181301a9bSJames Smart #define BGS_APPTAG_ERR_MASK 0x00000002 354281301a9bSJames Smart #define BGS_APPTAG_ERR_SHIFT 1 354381301a9bSJames Smart #define BGS_GUARD_ERR_MASK 0x00000001 354481301a9bSJames Smart #define BGS_GUARD_ERR_SHIFT 0 354581301a9bSJames Smart uint32_t bgstat; /* word 15 - BlockGuard Status */ 354681301a9bSJames Smart }; 354781301a9bSJames Smart 354881301a9bSJames Smart static inline uint32_t 354981301a9bSJames Smart lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 355081301a9bSJames Smart { 3551bc73905aSJames Smart return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 355281301a9bSJames Smart BGS_BIDIR_BG_PROF_SHIFT; 355381301a9bSJames Smart } 355481301a9bSJames Smart 355581301a9bSJames Smart static inline uint32_t 355681301a9bSJames Smart lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 355781301a9bSJames Smart { 3558bc73905aSJames Smart return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 355981301a9bSJames Smart BGS_BIDIR_ERR_COND_SHIFT; 356081301a9bSJames Smart } 356181301a9bSJames Smart 356281301a9bSJames Smart static inline uint32_t 356381301a9bSJames Smart lpfc_bgs_get_bg_prof(uint32_t bgstat) 356481301a9bSJames Smart { 3565bc73905aSJames Smart return (bgstat & BGS_BG_PROFILE_MASK) >> 356681301a9bSJames Smart BGS_BG_PROFILE_SHIFT; 356781301a9bSJames Smart } 356881301a9bSJames Smart 356981301a9bSJames Smart static inline uint32_t 357081301a9bSJames Smart lpfc_bgs_get_invalid_prof(uint32_t bgstat) 357181301a9bSJames Smart { 3572bc73905aSJames Smart return (bgstat & BGS_INVALID_PROF_MASK) >> 357381301a9bSJames Smart BGS_INVALID_PROF_SHIFT; 357481301a9bSJames Smart } 357581301a9bSJames Smart 357681301a9bSJames Smart static inline uint32_t 357781301a9bSJames Smart lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 357881301a9bSJames Smart { 3579bc73905aSJames Smart return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 358081301a9bSJames Smart BGS_UNINIT_DIF_BLOCK_SHIFT; 358181301a9bSJames Smart } 358281301a9bSJames Smart 358381301a9bSJames Smart static inline uint32_t 358481301a9bSJames Smart lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 358581301a9bSJames Smart { 3586bc73905aSJames Smart return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 358781301a9bSJames Smart BGS_HI_WATER_MARK_PRESENT_SHIFT; 358881301a9bSJames Smart } 358981301a9bSJames Smart 359081301a9bSJames Smart static inline uint32_t 359181301a9bSJames Smart lpfc_bgs_get_reftag_err(uint32_t bgstat) 359281301a9bSJames Smart { 3593bc73905aSJames Smart return (bgstat & BGS_REFTAG_ERR_MASK) >> 359481301a9bSJames Smart BGS_REFTAG_ERR_SHIFT; 359581301a9bSJames Smart } 359681301a9bSJames Smart 359781301a9bSJames Smart static inline uint32_t 359881301a9bSJames Smart lpfc_bgs_get_apptag_err(uint32_t bgstat) 359981301a9bSJames Smart { 3600bc73905aSJames Smart return (bgstat & BGS_APPTAG_ERR_MASK) >> 360181301a9bSJames Smart BGS_APPTAG_ERR_SHIFT; 360281301a9bSJames Smart } 360381301a9bSJames Smart 360481301a9bSJames Smart static inline uint32_t 360581301a9bSJames Smart lpfc_bgs_get_guard_err(uint32_t bgstat) 360681301a9bSJames Smart { 3607bc73905aSJames Smart return (bgstat & BGS_GUARD_ERR_MASK) >> 360881301a9bSJames Smart BGS_GUARD_ERR_SHIFT; 360981301a9bSJames Smart } 361081301a9bSJames Smart 361134b02dcdSJames Smart #define LPFC_EXT_DATA_BDE_COUNT 3 361234b02dcdSJames Smart struct fcp_irw_ext { 361334b02dcdSJames Smart uint32_t io_tag64_low; 361434b02dcdSJames Smart uint32_t io_tag64_high; 361534b02dcdSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 361634b02dcdSJames Smart uint8_t reserved1; 361734b02dcdSJames Smart uint8_t reserved2; 361834b02dcdSJames Smart uint8_t reserved3; 361934b02dcdSJames Smart uint8_t ebde_count; 362034b02dcdSJames Smart #else /* __LITTLE_ENDIAN */ 362134b02dcdSJames Smart uint8_t ebde_count; 362234b02dcdSJames Smart uint8_t reserved3; 362334b02dcdSJames Smart uint8_t reserved2; 362434b02dcdSJames Smart uint8_t reserved1; 362534b02dcdSJames Smart #endif 362634b02dcdSJames Smart uint32_t reserved4; 362734b02dcdSJames Smart struct ulp_bde64 rbde; /* response bde */ 362834b02dcdSJames Smart struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 362934b02dcdSJames Smart uint8_t icd[32]; /* immediate command data (32 bytes) */ 363034b02dcdSJames Smart }; 363134b02dcdSJames Smart 3632dea3101eS typedef struct _IOCB { /* IOCB structure */ 3633dea3101eS union { 3634dea3101eS GENERIC_RSP grsp; /* Generic response */ 3635dea3101eS XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 3636dea3101eS struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 3637dea3101eS RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 3638dea3101eS AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 3639dea3101eS A_MXRI64 amxri; /* abort multiple xri command overlay */ 3640dea3101eS GET_RPI getrpi; /* GET_RPI template */ 3641dea3101eS FCPI_FIELDS fcpi; /* FCP Initiator template */ 3642dea3101eS FCPT_FIELDS fcpt; /* FCP target template */ 3643dea3101eS 3644dea3101eS /* SLI-2 structures */ 3645dea3101eS 3646dea3101eS struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 3647ed957684SJames Smart * bde_64s */ 3648dea3101eS ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 3649dea3101eS GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 3650dea3101eS RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 3651dea3101eS XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 3652dea3101eS FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 3653dea3101eS FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 365457127f15SJames Smart ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 365576bb24efSJames Smart QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 36569c2face6SJames Smart struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 3657546fc854SJames Smart struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 3658dea3101eS uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 3659dea3101eS } un; 3660dea3101eS union { 3661dea3101eS struct { 3662dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3663dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3664dea3101eS uint16_t ulpIoTag; /* Low order bits word 6 */ 3665dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3666dea3101eS uint16_t ulpIoTag; /* Low order bits word 6 */ 3667dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3668dea3101eS #endif 3669dea3101eS } t1; 3670dea3101eS struct { 3671dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3672dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3673dea3101eS uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3674dea3101eS uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3675dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3676dea3101eS uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3677dea3101eS uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3678dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3679dea3101eS #endif 3680dea3101eS } t2; 3681dea3101eS } un1; 3682dea3101eS #define ulpContext un1.t1.ulpContext 3683dea3101eS #define ulpIoTag un1.t1.ulpIoTag 3684dea3101eS #define ulpIoTag0 un1.t2.ulpIoTag0 3685dea3101eS 3686dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3687dea3101eS uint32_t ulpTimeout:8; 3688dea3101eS uint32_t ulpXS:1; 3689dea3101eS uint32_t ulpFCP2Rcvy:1; 3690dea3101eS uint32_t ulpPU:2; 3691dea3101eS uint32_t ulpIr:1; 3692dea3101eS uint32_t ulpClass:3; 3693dea3101eS uint32_t ulpCommand:8; 3694dea3101eS uint32_t ulpStatus:4; 3695dea3101eS uint32_t ulpBdeCount:2; 3696dea3101eS uint32_t ulpLe:1; 3697dea3101eS uint32_t ulpOwner:1; /* Low order bit word 7 */ 3698dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3699dea3101eS uint32_t ulpOwner:1; /* Low order bit word 7 */ 3700dea3101eS uint32_t ulpLe:1; 3701dea3101eS uint32_t ulpBdeCount:2; 3702dea3101eS uint32_t ulpStatus:4; 3703dea3101eS uint32_t ulpCommand:8; 3704dea3101eS uint32_t ulpClass:3; 3705dea3101eS uint32_t ulpIr:1; 3706dea3101eS uint32_t ulpPU:2; 3707dea3101eS uint32_t ulpFCP2Rcvy:1; 3708dea3101eS uint32_t ulpXS:1; 3709dea3101eS uint32_t ulpTimeout:8; 3710dea3101eS #endif 371192d7f7b0SJames Smart 3712ed957684SJames Smart union { 3713ed957684SJames Smart struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 371476bb24efSJames Smart 371576bb24efSJames Smart /* words 8-31 used for que_xri_cx iocb */ 371676bb24efSJames Smart struct que_xri64cx_ext_fields que_xri64cx_ext_words; 371734b02dcdSJames Smart struct fcp_irw_ext fcp_ext; 3718ed957684SJames Smart uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 371981301a9bSJames Smart 372081301a9bSJames Smart /* words 8-15 for BlockGuard */ 372181301a9bSJames Smart struct sli3_bg_fields sli3_bg; 3722ed957684SJames Smart } unsli3; 3723dea3101eS 3724ed957684SJames Smart #define ulpCt_h ulpXS 3725ed957684SJames Smart #define ulpCt_l ulpFCP2Rcvy 3726ed957684SJames Smart 3727ed957684SJames Smart #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 3728ed957684SJames Smart #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 3729dea3101eS #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 3730dea3101eS #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 3731dea3101eS #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 373292d7f7b0SJames Smart #define PARM_NPIV_DID 3 3733dea3101eS #define CLASS1 0 /* Class 1 */ 3734dea3101eS #define CLASS2 1 /* Class 2 */ 3735dea3101eS #define CLASS3 2 /* Class 3 */ 3736dea3101eS #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 3737dea3101eS 3738dea3101eS #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 3739dea3101eS #define IOSTAT_FCP_RSP_ERROR 0x1 3740dea3101eS #define IOSTAT_REMOTE_STOP 0x2 3741dea3101eS #define IOSTAT_LOCAL_REJECT 0x3 3742dea3101eS #define IOSTAT_NPORT_RJT 0x4 3743dea3101eS #define IOSTAT_FABRIC_RJT 0x5 3744dea3101eS #define IOSTAT_NPORT_BSY 0x6 3745dea3101eS #define IOSTAT_FABRIC_BSY 0x7 3746dea3101eS #define IOSTAT_INTERMED_RSP 0x8 3747dea3101eS #define IOSTAT_LS_RJT 0x9 3748dea3101eS #define IOSTAT_BA_RJT 0xA 3749dea3101eS #define IOSTAT_RSVD1 0xB 3750dea3101eS #define IOSTAT_RSVD2 0xC 3751dea3101eS #define IOSTAT_RSVD3 0xD 3752dea3101eS #define IOSTAT_RSVD4 0xE 375392d7f7b0SJames Smart #define IOSTAT_NEED_BUFFER 0xF 3754dea3101eS #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 3755dea3101eS #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 3756dea3101eS #define IOSTAT_CNT 0x11 3757dea3101eS 3758dea3101eS } IOCB_t; 3759dea3101eS 3760dea3101eS 3761dea3101eS #define SLI1_SLIM_SIZE (4 * 1024) 3762dea3101eS 3763dea3101eS /* Up to 498 IOCBs will fit into 16k 3764dea3101eS * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 3765dea3101eS */ 3766ed957684SJames Smart #define SLI2_SLIM_SIZE (64 * 1024) 3767dea3101eS 3768dea3101eS /* Maximum IOCBs that will fit in SLI2 slim */ 3769dea3101eS #define MAX_SLI2_IOCB 498 3770ed957684SJames Smart #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 37717a470277SJames Smart (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 37727a470277SJames Smart sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 3773ed957684SJames Smart 3774ed957684SJames Smart /* HBQ entries are 4 words each = 4k */ 3775ed957684SJames Smart #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 3776ed957684SJames Smart lpfc_sli_hbq_count()) 3777dea3101eS 3778dea3101eS struct lpfc_sli2_slim { 3779dea3101eS MAILBOX_t mbx; 37807a470277SJames Smart uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 3781dea3101eS PCB_t pcb; 3782ed957684SJames Smart IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 3783dea3101eS }; 3784dea3101eS 37852e0fef85SJames Smart /* 37862e0fef85SJames Smart * This function checks PCI device to allow special handling for LC HBAs. 37872e0fef85SJames Smart * 37882e0fef85SJames Smart * Parameters: 37892e0fef85SJames Smart * device : struct pci_dev 's device field 37902e0fef85SJames Smart * 37912e0fef85SJames Smart * return 1 => TRUE 37922e0fef85SJames Smart * 0 => FALSE 37932e0fef85SJames Smart */ 3794dea3101eS static inline int 3795dea3101eS lpfc_is_LC_HBA(unsigned short device) 3796dea3101eS { 3797dea3101eS if ((device == PCI_DEVICE_ID_TFLY) || 3798dea3101eS (device == PCI_DEVICE_ID_PFLY) || 3799dea3101eS (device == PCI_DEVICE_ID_LP101) || 3800dea3101eS (device == PCI_DEVICE_ID_BMID) || 3801dea3101eS (device == PCI_DEVICE_ID_BSMB) || 3802dea3101eS (device == PCI_DEVICE_ID_ZMID) || 3803dea3101eS (device == PCI_DEVICE_ID_ZSMB) || 380409372820SJames Smart (device == PCI_DEVICE_ID_SAT_MID) || 380509372820SJames Smart (device == PCI_DEVICE_ID_SAT_SMB) || 3806dea3101eS (device == PCI_DEVICE_ID_RFLY)) 3807dea3101eS return 1; 3808dea3101eS else 3809dea3101eS return 0; 3810dea3101eS } 3811858c9f6cSJames Smart 3812858c9f6cSJames Smart /* 3813858c9f6cSJames Smart * Determine if an IOCB failed because of a link event or firmware reset. 3814858c9f6cSJames Smart */ 3815858c9f6cSJames Smart 3816858c9f6cSJames Smart static inline int 3817858c9f6cSJames Smart lpfc_error_lost_link(IOCB_t *iocbp) 3818858c9f6cSJames Smart { 3819858c9f6cSJames Smart return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 3820858c9f6cSJames Smart (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 3821858c9f6cSJames Smart iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 3822858c9f6cSJames Smart iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 3823858c9f6cSJames Smart } 382484774a4dSJames Smart 382584774a4dSJames Smart #define MENLO_TRANSPORT_TYPE 0xfe 382684774a4dSJames Smart #define MENLO_CONTEXT 0 382784774a4dSJames Smart #define MENLO_PU 3 382884774a4dSJames Smart #define MENLO_TIMEOUT 30 382984774a4dSJames Smart #define SETVAR_MLOMNT 0x103107 383084774a4dSJames Smart #define SETVAR_MLORST 0x103007 3831da0436e9SJames Smart 3832da0436e9SJames Smart #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 3833