1dea3101eS /******************************************************************* 2dea3101eS * This file is part of the Emulex Linux Device Driver for * 3c44ce173SJames.Smart@Emulex.Com * Fibre Channel Host Bus Adapters. * 4*d8e93df1SJames Smart * Copyright (C) 2004-2009 Emulex. All rights reserved. * 5c44ce173SJames.Smart@Emulex.Com * EMULEX and SLI are trademarks of Emulex. * 6dea3101eS * www.emulex.com * 7dea3101eS * * 8dea3101eS * This program is free software; you can redistribute it and/or * 9c44ce173SJames.Smart@Emulex.Com * modify it under the terms of version 2 of the GNU General * 10c44ce173SJames.Smart@Emulex.Com * Public License as published by the Free Software Foundation. * 11c44ce173SJames.Smart@Emulex.Com * This program is distributed in the hope that it will be useful. * 12c44ce173SJames.Smart@Emulex.Com * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13c44ce173SJames.Smart@Emulex.Com * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14c44ce173SJames.Smart@Emulex.Com * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15c44ce173SJames.Smart@Emulex.Com * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16c44ce173SJames.Smart@Emulex.Com * TO BE LEGALLY INVALID. See the GNU General Public License for * 17c44ce173SJames.Smart@Emulex.Com * more details, a copy of which can be found in the file COPYING * 18c44ce173SJames.Smart@Emulex.Com * included with this package. * 19dea3101eS *******************************************************************/ 20dea3101eS 21dea3101eS #define FDMI_DID 0xfffffaU 22dea3101eS #define NameServer_DID 0xfffffcU 23dea3101eS #define SCR_DID 0xfffffdU 24dea3101eS #define Fabric_DID 0xfffffeU 25dea3101eS #define Bcast_DID 0xffffffU 26dea3101eS #define Mask_DID 0xffffffU 27dea3101eS #define CT_DID_MASK 0xffff00U 28dea3101eS #define Fabric_DID_MASK 0xfff000U 29dea3101eS #define WELL_KNOWN_DID_MASK 0xfffff0U 30dea3101eS 31dea3101eS #define PT2PT_LocalID 1 32dea3101eS #define PT2PT_RemoteID 2 33dea3101eS 34dea3101eS #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35dea3101eS #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36dea3101eS #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37dea3101eS #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38dea3101eS 39dea3101eS #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40dea3101eS 0 */ 41dea3101eS 42dea3101eS #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43dea3101eS 44dea3101eS #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45a4bc3379SJames Smart #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46dea3101eS #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47dea3101eS #define LPFC_FCP_NEXT_RING 3 48dea3101eS 49dea3101eS #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50dea3101eS #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51a4bc3379SJames Smart #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 52a4bc3379SJames Smart #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 53dea3101eS #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54dea3101eS #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55dea3101eS #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56dea3101eS #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57dea3101eS #define SLI2_IOCB_CMD_R3_ENTRIES 0 58dea3101eS #define SLI2_IOCB_RSP_R3_ENTRIES 0 59dea3101eS #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60dea3101eS #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61dea3101eS 62ed957684SJames Smart #define SLI2_IOCB_CMD_SIZE 32 63ed957684SJames Smart #define SLI2_IOCB_RSP_SIZE 32 64ed957684SJames Smart #define SLI3_IOCB_CMD_SIZE 128 65ed957684SJames Smart #define SLI3_IOCB_RSP_SIZE 64 66ed957684SJames Smart 6792d7f7b0SJames Smart 68ddcc50f0SJames Smart /* vendor ID used in SCSI netlink calls */ 69ddcc50f0SJames Smart #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 70ddcc50f0SJames Smart 71dea3101eS /* Common Transport structures and definitions */ 72dea3101eS 73dea3101eS union CtRevisionId { 74dea3101eS /* Structure is in Big Endian format */ 75dea3101eS struct { 76dea3101eS uint32_t Revision:8; 77dea3101eS uint32_t InId:24; 78dea3101eS } bits; 79dea3101eS uint32_t word; 80dea3101eS }; 81dea3101eS 82dea3101eS union CtCommandResponse { 83dea3101eS /* Structure is in Big Endian format */ 84dea3101eS struct { 85dea3101eS uint32_t CmdRsp:16; 86dea3101eS uint32_t Size:16; 87dea3101eS } bits; 88dea3101eS uint32_t word; 89dea3101eS }; 90dea3101eS 9192d7f7b0SJames Smart #define FC4_FEATURE_INIT 0x2 9292d7f7b0SJames Smart #define FC4_FEATURE_TARGET 0x1 9392d7f7b0SJames Smart 94dea3101eS struct lpfc_sli_ct_request { 95dea3101eS /* Structure is in Big Endian format */ 96dea3101eS union CtRevisionId RevisionId; 97dea3101eS uint8_t FsType; 98dea3101eS uint8_t FsSubType; 99dea3101eS uint8_t Options; 100dea3101eS uint8_t Rsrvd1; 101dea3101eS union CtCommandResponse CommandResponse; 102dea3101eS uint8_t Rsrvd2; 103dea3101eS uint8_t ReasonCode; 104dea3101eS uint8_t Explanation; 105dea3101eS uint8_t VendorUnique; 106dea3101eS 107dea3101eS union { 108dea3101eS uint32_t PortID; 109dea3101eS struct gid { 110dea3101eS uint8_t PortType; /* for GID_PT requests */ 111dea3101eS uint8_t DomainScope; 112dea3101eS uint8_t AreaScope; 113dea3101eS uint8_t Fc4Type; /* for GID_FT requests */ 114dea3101eS } gid; 115dea3101eS struct rft { 116dea3101eS uint32_t PortId; /* For RFT_ID requests */ 117dea3101eS 118dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 119dea3101eS uint32_t rsvd0:16; 120dea3101eS uint32_t rsvd1:7; 121dea3101eS uint32_t fcpReg:1; /* Type 8 */ 122dea3101eS uint32_t rsvd2:2; 123dea3101eS uint32_t ipReg:1; /* Type 5 */ 124dea3101eS uint32_t rsvd3:5; 125dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 126dea3101eS uint32_t rsvd0:16; 127dea3101eS uint32_t fcpReg:1; /* Type 8 */ 128dea3101eS uint32_t rsvd1:7; 129dea3101eS uint32_t rsvd3:5; 130dea3101eS uint32_t ipReg:1; /* Type 5 */ 131dea3101eS uint32_t rsvd2:2; 132dea3101eS #endif 133dea3101eS 134dea3101eS uint32_t rsvd[7]; 135dea3101eS } rft; 136dea3101eS struct rnn { 137dea3101eS uint32_t PortId; /* For RNN_ID requests */ 138dea3101eS uint8_t wwnn[8]; 139dea3101eS } rnn; 140dea3101eS struct rsnn { /* For RSNN_ID requests */ 141dea3101eS uint8_t wwnn[8]; 142dea3101eS uint8_t len; 143dea3101eS uint8_t symbname[255]; 144dea3101eS } rsnn; 1457ee5d43eSJames Smart struct da_id { /* For DA_ID requests */ 1467ee5d43eSJames Smart uint32_t port_id; 1477ee5d43eSJames Smart } da_id; 14892d7f7b0SJames Smart struct rspn { /* For RSPN_ID requests */ 14992d7f7b0SJames Smart uint32_t PortId; 15092d7f7b0SJames Smart uint8_t len; 15192d7f7b0SJames Smart uint8_t symbname[255]; 15292d7f7b0SJames Smart } rspn; 15392d7f7b0SJames Smart struct gff { 15492d7f7b0SJames Smart uint32_t PortId; 15592d7f7b0SJames Smart } gff; 15692d7f7b0SJames Smart struct gff_acc { 15792d7f7b0SJames Smart uint8_t fbits[128]; 15892d7f7b0SJames Smart } gff_acc; 15951ef4c26SJames Smart #define FCP_TYPE_FEATURE_OFFSET 7 16092d7f7b0SJames Smart struct rff { 16192d7f7b0SJames Smart uint32_t PortId; 16292d7f7b0SJames Smart uint8_t reserved[2]; 16392d7f7b0SJames Smart uint8_t fbits; 16492d7f7b0SJames Smart uint8_t type_code; /* type=8 for FCP */ 16592d7f7b0SJames Smart } rff; 166dea3101eS } un; 167dea3101eS }; 168dea3101eS 169dea3101eS #define SLI_CT_REVISION 1 17092d7f7b0SJames Smart #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17192d7f7b0SJames Smart sizeof(struct gid)) 17292d7f7b0SJames Smart #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17392d7f7b0SJames Smart sizeof(struct gff)) 17492d7f7b0SJames Smart #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17592d7f7b0SJames Smart sizeof(struct rft)) 17692d7f7b0SJames Smart #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17792d7f7b0SJames Smart sizeof(struct rff)) 17892d7f7b0SJames Smart #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17992d7f7b0SJames Smart sizeof(struct rnn)) 18092d7f7b0SJames Smart #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 18192d7f7b0SJames Smart sizeof(struct rsnn)) 1827ee5d43eSJames Smart #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 1837ee5d43eSJames Smart sizeof(struct da_id)) 18492d7f7b0SJames Smart #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 18592d7f7b0SJames Smart sizeof(struct rspn)) 186dea3101eS 187dea3101eS /* 188dea3101eS * FsType Definitions 189dea3101eS */ 190dea3101eS 191dea3101eS #define SLI_CT_MANAGEMENT_SERVICE 0xFA 192dea3101eS #define SLI_CT_TIME_SERVICE 0xFB 193dea3101eS #define SLI_CT_DIRECTORY_SERVICE 0xFC 194dea3101eS #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 195dea3101eS 196dea3101eS /* 197dea3101eS * Directory Service Subtypes 198dea3101eS */ 199dea3101eS 200dea3101eS #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 201dea3101eS 202dea3101eS /* 203dea3101eS * Response Codes 204dea3101eS */ 205dea3101eS 206dea3101eS #define SLI_CT_RESPONSE_FS_RJT 0x8001 207dea3101eS #define SLI_CT_RESPONSE_FS_ACC 0x8002 208dea3101eS 209dea3101eS /* 210dea3101eS * Reason Codes 211dea3101eS */ 212dea3101eS 213dea3101eS #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 214dea3101eS #define SLI_CT_INVALID_COMMAND 0x01 215dea3101eS #define SLI_CT_INVALID_VERSION 0x02 216dea3101eS #define SLI_CT_LOGICAL_ERROR 0x03 217dea3101eS #define SLI_CT_INVALID_IU_SIZE 0x04 218dea3101eS #define SLI_CT_LOGICAL_BUSY 0x05 219dea3101eS #define SLI_CT_PROTOCOL_ERROR 0x07 220dea3101eS #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 221dea3101eS #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 222dea3101eS #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 223dea3101eS #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 224dea3101eS #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 225dea3101eS #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 226dea3101eS #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 227dea3101eS #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 228dea3101eS #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 229dea3101eS #define SLI_CT_VENDOR_UNIQUE 0xff 230dea3101eS 231dea3101eS /* 232dea3101eS * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 233dea3101eS */ 234dea3101eS 235dea3101eS #define SLI_CT_NO_PORT_ID 0x01 236dea3101eS #define SLI_CT_NO_PORT_NAME 0x02 237dea3101eS #define SLI_CT_NO_NODE_NAME 0x03 238dea3101eS #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 239dea3101eS #define SLI_CT_NO_IP_ADDRESS 0x05 240dea3101eS #define SLI_CT_NO_IPA 0x06 241dea3101eS #define SLI_CT_NO_FC4_TYPES 0x07 242dea3101eS #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 243dea3101eS #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 244dea3101eS #define SLI_CT_NO_PORT_TYPE 0x0A 245dea3101eS #define SLI_CT_ACCESS_DENIED 0x10 246dea3101eS #define SLI_CT_INVALID_PORT_ID 0x11 247dea3101eS #define SLI_CT_DATABASE_EMPTY 0x12 248dea3101eS 249dea3101eS /* 250dea3101eS * Name Server Command Codes 251dea3101eS */ 252dea3101eS 253dea3101eS #define SLI_CTNS_GA_NXT 0x0100 254dea3101eS #define SLI_CTNS_GPN_ID 0x0112 255dea3101eS #define SLI_CTNS_GNN_ID 0x0113 256dea3101eS #define SLI_CTNS_GCS_ID 0x0114 257dea3101eS #define SLI_CTNS_GFT_ID 0x0117 258dea3101eS #define SLI_CTNS_GSPN_ID 0x0118 259dea3101eS #define SLI_CTNS_GPT_ID 0x011A 26092d7f7b0SJames Smart #define SLI_CTNS_GFF_ID 0x011F 261dea3101eS #define SLI_CTNS_GID_PN 0x0121 262dea3101eS #define SLI_CTNS_GID_NN 0x0131 263dea3101eS #define SLI_CTNS_GIP_NN 0x0135 264dea3101eS #define SLI_CTNS_GIPA_NN 0x0136 265dea3101eS #define SLI_CTNS_GSNN_NN 0x0139 266dea3101eS #define SLI_CTNS_GNN_IP 0x0153 267dea3101eS #define SLI_CTNS_GIPA_IP 0x0156 268dea3101eS #define SLI_CTNS_GID_FT 0x0171 269dea3101eS #define SLI_CTNS_GID_PT 0x01A1 270dea3101eS #define SLI_CTNS_RPN_ID 0x0212 271dea3101eS #define SLI_CTNS_RNN_ID 0x0213 272dea3101eS #define SLI_CTNS_RCS_ID 0x0214 273dea3101eS #define SLI_CTNS_RFT_ID 0x0217 274dea3101eS #define SLI_CTNS_RSPN_ID 0x0218 275dea3101eS #define SLI_CTNS_RPT_ID 0x021A 27692d7f7b0SJames Smart #define SLI_CTNS_RFF_ID 0x021F 277dea3101eS #define SLI_CTNS_RIP_NN 0x0235 278dea3101eS #define SLI_CTNS_RIPA_NN 0x0236 279dea3101eS #define SLI_CTNS_RSNN_NN 0x0239 280dea3101eS #define SLI_CTNS_DA_ID 0x0300 281dea3101eS 282dea3101eS /* 283dea3101eS * Port Types 284dea3101eS */ 285dea3101eS 286dea3101eS #define SLI_CTPT_N_PORT 0x01 287dea3101eS #define SLI_CTPT_NL_PORT 0x02 288dea3101eS #define SLI_CTPT_FNL_PORT 0x03 289dea3101eS #define SLI_CTPT_IP 0x04 290dea3101eS #define SLI_CTPT_FCP 0x08 291dea3101eS #define SLI_CTPT_NX_PORT 0x7F 292dea3101eS #define SLI_CTPT_F_PORT 0x81 293dea3101eS #define SLI_CTPT_FL_PORT 0x82 294dea3101eS #define SLI_CTPT_E_PORT 0x84 295dea3101eS 296dea3101eS #define SLI_CT_LAST_ENTRY 0x80000000 297dea3101eS 298dea3101eS /* Fibre Channel Service Parameter definitions */ 299dea3101eS 300dea3101eS #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 301dea3101eS #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 302dea3101eS #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 303dea3101eS #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 304dea3101eS 305dea3101eS #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 306dea3101eS #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 307dea3101eS #define FC_PH3 0x20 /* FC-PH-3 version */ 308dea3101eS 309dea3101eS #define FF_FRAME_SIZE 2048 310dea3101eS 311dea3101eS struct lpfc_name { 312f631b4beSAndrew Vasquez union { 313f631b4beSAndrew Vasquez struct { 314dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 315dea3101eS uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 3161de933f3SJames.Smart@Emulex.Com uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 3171de933f3SJames.Smart@Emulex.Com 8:11 of IEEE ext */ 318dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3191de933f3SJames.Smart@Emulex.Com uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 3201de933f3SJames.Smart@Emulex.Com 8:11 of IEEE ext */ 321dea3101eS uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 322dea3101eS #endif 323dea3101eS 324dea3101eS #define NAME_IEEE 0x1 /* IEEE name - nameType */ 325dea3101eS #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 326dea3101eS #define NAME_FC_TYPE 0x3 /* FC native name type */ 327dea3101eS #define NAME_IP_TYPE 0x4 /* IP address */ 328dea3101eS #define NAME_CCITT_TYPE 0xC 329dea3101eS #define NAME_CCITT_GR_TYPE 0xE 3301de933f3SJames.Smart@Emulex.Com uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 3311de933f3SJames.Smart@Emulex.Com extended Lsb */ 332dea3101eS uint8_t IEEE[6]; /* FC IEEE address */ 33368ce1eb5SAndrew Morton } s; 334f631b4beSAndrew Vasquez uint8_t wwn[8]; 33568ce1eb5SAndrew Morton } u; 336f631b4beSAndrew Vasquez }; 337dea3101eS 338dea3101eS struct csp { 339dea3101eS uint8_t fcphHigh; /* FC Word 0, byte 0 */ 340dea3101eS uint8_t fcphLow; 341dea3101eS uint8_t bbCreditMsb; 342dea3101eS uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 343dea3101eS 344dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 34592d7f7b0SJames Smart uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 34692d7f7b0SJames Smart uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 34792d7f7b0SJames Smart uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 348dea3101eS uint16_t fPort:1; /* FC Word 1, bit 28 */ 349dea3101eS uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 350dea3101eS uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 351dea3101eS uint16_t multicast:1; /* FC Word 1, bit 25 */ 352dea3101eS uint16_t broadcast:1; /* FC Word 1, bit 24 */ 353dea3101eS 354dea3101eS uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 355dea3101eS uint16_t simplex:1; /* FC Word 1, bit 22 */ 356dea3101eS uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 357dea3101eS uint16_t dhd:1; /* FC Word 1, bit 18 */ 358dea3101eS uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 359dea3101eS uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 360dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 361dea3101eS uint16_t broadcast:1; /* FC Word 1, bit 24 */ 362dea3101eS uint16_t multicast:1; /* FC Word 1, bit 25 */ 363dea3101eS uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 364dea3101eS uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 365dea3101eS uint16_t fPort:1; /* FC Word 1, bit 28 */ 36692d7f7b0SJames Smart uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 367dea3101eS uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 36892d7f7b0SJames Smart uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 369dea3101eS 370dea3101eS uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 371dea3101eS uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 372dea3101eS uint16_t dhd:1; /* FC Word 1, bit 18 */ 373dea3101eS uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 374dea3101eS uint16_t simplex:1; /* FC Word 1, bit 22 */ 375dea3101eS uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 376dea3101eS #endif 377dea3101eS 378dea3101eS uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 379dea3101eS uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 380dea3101eS union { 381dea3101eS struct { 382dea3101eS uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 383dea3101eS 384dea3101eS uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 385dea3101eS uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 386dea3101eS 387dea3101eS uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 388dea3101eS } nPort; 389dea3101eS uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 390dea3101eS } w2; 391dea3101eS 392dea3101eS uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 393dea3101eS }; 394dea3101eS 395dea3101eS struct class_parms { 396dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 397dea3101eS uint8_t classValid:1; /* FC Word 0, bit 31 */ 398dea3101eS uint8_t intermix:1; /* FC Word 0, bit 30 */ 399dea3101eS uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 400dea3101eS uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 401dea3101eS uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 402dea3101eS uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 403dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 404dea3101eS uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 405dea3101eS uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 406dea3101eS uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 407dea3101eS uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 408dea3101eS uint8_t intermix:1; /* FC Word 0, bit 30 */ 409dea3101eS uint8_t classValid:1; /* FC Word 0, bit 31 */ 410dea3101eS 411dea3101eS #endif 412dea3101eS 413dea3101eS uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 414dea3101eS 415dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 416dea3101eS uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 417dea3101eS uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 418dea3101eS uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 419dea3101eS uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 420dea3101eS uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 421dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 422dea3101eS uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 423dea3101eS uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 424dea3101eS uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 425dea3101eS uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 426dea3101eS uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 427dea3101eS #endif 428dea3101eS 429dea3101eS uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 430dea3101eS 431dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 432dea3101eS uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 433dea3101eS uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 434dea3101eS uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 435dea3101eS uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 436dea3101eS uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 437dea3101eS uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 438dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 439dea3101eS uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 440dea3101eS uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 441dea3101eS uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 442dea3101eS uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 443dea3101eS uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 444dea3101eS uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 445dea3101eS #endif 446dea3101eS 447dea3101eS uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 448dea3101eS uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 449dea3101eS uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 450dea3101eS 451dea3101eS uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 452dea3101eS uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 453dea3101eS uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 454dea3101eS uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 455dea3101eS 456dea3101eS uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 457dea3101eS uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 458dea3101eS uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 459dea3101eS uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 460dea3101eS }; 461dea3101eS 462dea3101eS struct serv_parm { /* Structure is in Big Endian format */ 463dea3101eS struct csp cmn; 464dea3101eS struct lpfc_name portName; 465dea3101eS struct lpfc_name nodeName; 466dea3101eS struct class_parms cls1; 467dea3101eS struct class_parms cls2; 468dea3101eS struct class_parms cls3; 469dea3101eS struct class_parms cls4; 470dea3101eS uint8_t vendorVersion[16]; 471dea3101eS }; 472dea3101eS 473dea3101eS /* 474da0436e9SJames Smart * Virtual Fabric Tagging Header 475da0436e9SJames Smart */ 476da0436e9SJames Smart struct fc_vft_header { 477da0436e9SJames Smart uint32_t word0; 478da0436e9SJames Smart #define fc_vft_hdr_r_ctl_SHIFT 24 479da0436e9SJames Smart #define fc_vft_hdr_r_ctl_MASK 0xFF 480da0436e9SJames Smart #define fc_vft_hdr_r_ctl_WORD word0 481da0436e9SJames Smart #define fc_vft_hdr_ver_SHIFT 22 482da0436e9SJames Smart #define fc_vft_hdr_ver_MASK 0x3 483da0436e9SJames Smart #define fc_vft_hdr_ver_WORD word0 484da0436e9SJames Smart #define fc_vft_hdr_type_SHIFT 18 485da0436e9SJames Smart #define fc_vft_hdr_type_MASK 0xF 486da0436e9SJames Smart #define fc_vft_hdr_type_WORD word0 487da0436e9SJames Smart #define fc_vft_hdr_e_SHIFT 16 488da0436e9SJames Smart #define fc_vft_hdr_e_MASK 0x1 489da0436e9SJames Smart #define fc_vft_hdr_e_WORD word0 490da0436e9SJames Smart #define fc_vft_hdr_priority_SHIFT 13 491da0436e9SJames Smart #define fc_vft_hdr_priority_MASK 0x7 492da0436e9SJames Smart #define fc_vft_hdr_priority_WORD word0 493da0436e9SJames Smart #define fc_vft_hdr_vf_id_SHIFT 1 494da0436e9SJames Smart #define fc_vft_hdr_vf_id_MASK 0xFFF 495da0436e9SJames Smart #define fc_vft_hdr_vf_id_WORD word0 496da0436e9SJames Smart uint32_t word1; 497da0436e9SJames Smart #define fc_vft_hdr_hopct_SHIFT 24 498da0436e9SJames Smart #define fc_vft_hdr_hopct_MASK 0xFF 499da0436e9SJames Smart #define fc_vft_hdr_hopct_WORD word1 500da0436e9SJames Smart }; 501da0436e9SJames Smart 502da0436e9SJames Smart /* 503dea3101eS * Extended Link Service LS_COMMAND codes (Payload Word 0) 504dea3101eS */ 505dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 506dea3101eS #define ELS_CMD_MASK 0xffff0000 507dea3101eS #define ELS_RSP_MASK 0xff000000 508dea3101eS #define ELS_CMD_LS_RJT 0x01000000 509dea3101eS #define ELS_CMD_ACC 0x02000000 510dea3101eS #define ELS_CMD_PLOGI 0x03000000 511dea3101eS #define ELS_CMD_FLOGI 0x04000000 512dea3101eS #define ELS_CMD_LOGO 0x05000000 513dea3101eS #define ELS_CMD_ABTX 0x06000000 514dea3101eS #define ELS_CMD_RCS 0x07000000 515dea3101eS #define ELS_CMD_RES 0x08000000 516dea3101eS #define ELS_CMD_RSS 0x09000000 517dea3101eS #define ELS_CMD_RSI 0x0A000000 518dea3101eS #define ELS_CMD_ESTS 0x0B000000 519dea3101eS #define ELS_CMD_ESTC 0x0C000000 520dea3101eS #define ELS_CMD_ADVC 0x0D000000 521dea3101eS #define ELS_CMD_RTV 0x0E000000 522dea3101eS #define ELS_CMD_RLS 0x0F000000 523dea3101eS #define ELS_CMD_ECHO 0x10000000 524dea3101eS #define ELS_CMD_TEST 0x11000000 525dea3101eS #define ELS_CMD_RRQ 0x12000000 526dea3101eS #define ELS_CMD_PRLI 0x20100014 527dea3101eS #define ELS_CMD_PRLO 0x21100014 52882d9a2a2SJames Smart #define ELS_CMD_PRLO_ACC 0x02100014 529dea3101eS #define ELS_CMD_PDISC 0x50000000 530dea3101eS #define ELS_CMD_FDISC 0x51000000 531dea3101eS #define ELS_CMD_ADISC 0x52000000 532dea3101eS #define ELS_CMD_FARP 0x54000000 533dea3101eS #define ELS_CMD_FARPR 0x55000000 5347bb3b137SJamie Wellnitz #define ELS_CMD_RPS 0x56000000 5357bb3b137SJamie Wellnitz #define ELS_CMD_RPL 0x57000000 536dea3101eS #define ELS_CMD_FAN 0x60000000 537dea3101eS #define ELS_CMD_RSCN 0x61040000 538dea3101eS #define ELS_CMD_SCR 0x62000000 539dea3101eS #define ELS_CMD_RNID 0x78000000 5407bb3b137SJamie Wellnitz #define ELS_CMD_LIRR 0x7A000000 541dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 542dea3101eS #define ELS_CMD_MASK 0xffff 543dea3101eS #define ELS_RSP_MASK 0xff 544dea3101eS #define ELS_CMD_LS_RJT 0x01 545dea3101eS #define ELS_CMD_ACC 0x02 546dea3101eS #define ELS_CMD_PLOGI 0x03 547dea3101eS #define ELS_CMD_FLOGI 0x04 548dea3101eS #define ELS_CMD_LOGO 0x05 549dea3101eS #define ELS_CMD_ABTX 0x06 550dea3101eS #define ELS_CMD_RCS 0x07 551dea3101eS #define ELS_CMD_RES 0x08 552dea3101eS #define ELS_CMD_RSS 0x09 553dea3101eS #define ELS_CMD_RSI 0x0A 554dea3101eS #define ELS_CMD_ESTS 0x0B 555dea3101eS #define ELS_CMD_ESTC 0x0C 556dea3101eS #define ELS_CMD_ADVC 0x0D 557dea3101eS #define ELS_CMD_RTV 0x0E 558dea3101eS #define ELS_CMD_RLS 0x0F 559dea3101eS #define ELS_CMD_ECHO 0x10 560dea3101eS #define ELS_CMD_TEST 0x11 561dea3101eS #define ELS_CMD_RRQ 0x12 562dea3101eS #define ELS_CMD_PRLI 0x14001020 563dea3101eS #define ELS_CMD_PRLO 0x14001021 56482d9a2a2SJames Smart #define ELS_CMD_PRLO_ACC 0x14001002 565dea3101eS #define ELS_CMD_PDISC 0x50 566dea3101eS #define ELS_CMD_FDISC 0x51 567dea3101eS #define ELS_CMD_ADISC 0x52 568dea3101eS #define ELS_CMD_FARP 0x54 569dea3101eS #define ELS_CMD_FARPR 0x55 5707bb3b137SJamie Wellnitz #define ELS_CMD_RPS 0x56 5717bb3b137SJamie Wellnitz #define ELS_CMD_RPL 0x57 572dea3101eS #define ELS_CMD_FAN 0x60 573dea3101eS #define ELS_CMD_RSCN 0x0461 574dea3101eS #define ELS_CMD_SCR 0x62 575dea3101eS #define ELS_CMD_RNID 0x78 5767bb3b137SJamie Wellnitz #define ELS_CMD_LIRR 0x7A 577dea3101eS #endif 578dea3101eS 579dea3101eS /* 580dea3101eS * LS_RJT Payload Definition 581dea3101eS */ 582dea3101eS 583dea3101eS struct ls_rjt { /* Structure is in Big Endian format */ 584dea3101eS union { 585dea3101eS uint32_t lsRjtError; 586dea3101eS struct { 587dea3101eS uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 588dea3101eS 589dea3101eS uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 590dea3101eS /* LS_RJT reason codes */ 591dea3101eS #define LSRJT_INVALID_CMD 0x01 592dea3101eS #define LSRJT_LOGICAL_ERR 0x03 593dea3101eS #define LSRJT_LOGICAL_BSY 0x05 594dea3101eS #define LSRJT_PROTOCOL_ERR 0x07 595dea3101eS #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 596dea3101eS #define LSRJT_CMD_UNSUPPORTED 0x0B 597dea3101eS #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 598dea3101eS 599dea3101eS uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 600dea3101eS /* LS_RJT reason explanation */ 601dea3101eS #define LSEXP_NOTHING_MORE 0x00 602dea3101eS #define LSEXP_SPARM_OPTIONS 0x01 603dea3101eS #define LSEXP_SPARM_ICTL 0x03 604dea3101eS #define LSEXP_SPARM_RCTL 0x05 605dea3101eS #define LSEXP_SPARM_RCV_SIZE 0x07 606dea3101eS #define LSEXP_SPARM_CONCUR_SEQ 0x09 607dea3101eS #define LSEXP_SPARM_CREDIT 0x0B 608dea3101eS #define LSEXP_INVALID_PNAME 0x0D 609dea3101eS #define LSEXP_INVALID_NNAME 0x0E 610dea3101eS #define LSEXP_INVALID_CSP 0x0F 611dea3101eS #define LSEXP_INVALID_ASSOC_HDR 0x11 612dea3101eS #define LSEXP_ASSOC_HDR_REQ 0x13 613dea3101eS #define LSEXP_INVALID_O_SID 0x15 614dea3101eS #define LSEXP_INVALID_OX_RX 0x17 615dea3101eS #define LSEXP_CMD_IN_PROGRESS 0x19 6167f5f3d0dSJames Smart #define LSEXP_PORT_LOGIN_REQ 0x1E 617dea3101eS #define LSEXP_INVALID_NPORT_ID 0x1F 618dea3101eS #define LSEXP_INVALID_SEQ_ID 0x21 619dea3101eS #define LSEXP_INVALID_XCHG 0x23 620dea3101eS #define LSEXP_INACTIVE_XCHG 0x25 621dea3101eS #define LSEXP_RQ_REQUIRED 0x27 622dea3101eS #define LSEXP_OUT_OF_RESOURCE 0x29 623dea3101eS #define LSEXP_CANT_GIVE_DATA 0x2A 624dea3101eS #define LSEXP_REQ_UNSUPPORTED 0x2C 625dea3101eS uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 626dea3101eS } b; 627dea3101eS } un; 628dea3101eS }; 629dea3101eS 630dea3101eS /* 631dea3101eS * N_Port Login (FLOGO/PLOGO Request) Payload Definition 632dea3101eS */ 633dea3101eS 634dea3101eS typedef struct _LOGO { /* Structure is in Big Endian format */ 635dea3101eS union { 636dea3101eS uint32_t nPortId32; /* Access nPortId as a word */ 637dea3101eS struct { 638dea3101eS uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 639dea3101eS uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 640dea3101eS uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 641dea3101eS uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 642dea3101eS } b; 643dea3101eS } un; 644dea3101eS struct lpfc_name portName; /* N_port name field */ 645dea3101eS } LOGO; 646dea3101eS 647dea3101eS /* 648dea3101eS * FCP Login (PRLI Request / ACC) Payload Definition 649dea3101eS */ 650dea3101eS 651dea3101eS #define PRLX_PAGE_LEN 0x10 652dea3101eS #define TPRLO_PAGE_LEN 0x14 653dea3101eS 654dea3101eS typedef struct _PRLI { /* Structure is in Big Endian format */ 655dea3101eS uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 656dea3101eS 657dea3101eS #define PRLI_FCP_TYPE 0x08 658dea3101eS uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 659dea3101eS 660dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 661dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 662dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 663dea3101eS uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 664dea3101eS 665dea3101eS /* ACC = imagePairEstablished */ 666dea3101eS uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 667dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 668dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 669dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 670dea3101eS uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 671dea3101eS uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 672dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 673dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 674dea3101eS /* ACC = imagePairEstablished */ 675dea3101eS #endif 676dea3101eS 677dea3101eS #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 678dea3101eS #define PRLI_NO_RESOURCES 0x2 679dea3101eS #define PRLI_INIT_INCOMPLETE 0x3 680dea3101eS #define PRLI_NO_SUCH_PA 0x4 681dea3101eS #define PRLI_PREDEF_CONFIG 0x5 682dea3101eS #define PRLI_PARTIAL_SUCCESS 0x6 683dea3101eS #define PRLI_INVALID_PAGE_CNT 0x7 684dea3101eS uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 685dea3101eS 686dea3101eS uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 687dea3101eS 688dea3101eS uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 689dea3101eS 690dea3101eS uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 691dea3101eS uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 692dea3101eS 693dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 694dea3101eS uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 695dea3101eS uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 696dea3101eS uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 697dea3101eS uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 698dea3101eS uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 699dea3101eS uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 700dea3101eS uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 701dea3101eS uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 702dea3101eS uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 703dea3101eS uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 704dea3101eS uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 705dea3101eS uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 706dea3101eS uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 707dea3101eS uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 708dea3101eS uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 709dea3101eS uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 710dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 711dea3101eS uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 712dea3101eS uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 713dea3101eS uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 714dea3101eS uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 715dea3101eS uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 716dea3101eS uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 717dea3101eS uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 718dea3101eS uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 719dea3101eS uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 720dea3101eS uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 721dea3101eS uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 722dea3101eS uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 723dea3101eS uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 724dea3101eS uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 725dea3101eS uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 726dea3101eS uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 727dea3101eS #endif 728dea3101eS } PRLI; 729dea3101eS 730dea3101eS /* 731dea3101eS * FCP Logout (PRLO Request / ACC) Payload Definition 732dea3101eS */ 733dea3101eS 734dea3101eS typedef struct _PRLO { /* Structure is in Big Endian format */ 735dea3101eS uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 736dea3101eS 737dea3101eS #define PRLO_FCP_TYPE 0x08 738dea3101eS uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 739dea3101eS 740dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 741dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 742dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 743dea3101eS uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 744dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 745dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 746dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 747dea3101eS uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 748dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 749dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 750dea3101eS #endif 751dea3101eS 752dea3101eS #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 753dea3101eS #define PRLO_NO_SUCH_IMAGE 0x4 754dea3101eS #define PRLO_INVALID_PAGE_CNT 0x7 755dea3101eS 756dea3101eS uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 757dea3101eS 758dea3101eS uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 759dea3101eS 760dea3101eS uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 761dea3101eS 762dea3101eS uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 763dea3101eS } PRLO; 764dea3101eS 765dea3101eS typedef struct _ADISC { /* Structure is in Big Endian format */ 766dea3101eS uint32_t hardAL_PA; 767dea3101eS struct lpfc_name portName; 768dea3101eS struct lpfc_name nodeName; 769dea3101eS uint32_t DID; 770dea3101eS } ADISC; 771dea3101eS 772dea3101eS typedef struct _FARP { /* Structure is in Big Endian format */ 773dea3101eS uint32_t Mflags:8; 774dea3101eS uint32_t Odid:24; 775dea3101eS #define FARP_NO_ACTION 0 /* FARP information enclosed, no 776dea3101eS action */ 777dea3101eS #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 778dea3101eS #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 779dea3101eS #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 780dea3101eS #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 781dea3101eS supported */ 782dea3101eS #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 783dea3101eS supported */ 784dea3101eS uint32_t Rflags:8; 785dea3101eS uint32_t Rdid:24; 786dea3101eS #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 787dea3101eS #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 788dea3101eS struct lpfc_name OportName; 789dea3101eS struct lpfc_name OnodeName; 790dea3101eS struct lpfc_name RportName; 791dea3101eS struct lpfc_name RnodeName; 792dea3101eS uint8_t Oipaddr[16]; 793dea3101eS uint8_t Ripaddr[16]; 794dea3101eS } FARP; 795dea3101eS 796dea3101eS typedef struct _FAN { /* Structure is in Big Endian format */ 797dea3101eS uint32_t Fdid; 798dea3101eS struct lpfc_name FportName; 799dea3101eS struct lpfc_name FnodeName; 800dea3101eS } FAN; 801dea3101eS 802dea3101eS typedef struct _SCR { /* Structure is in Big Endian format */ 803dea3101eS uint8_t resvd1; 804dea3101eS uint8_t resvd2; 805dea3101eS uint8_t resvd3; 806dea3101eS uint8_t Function; 807dea3101eS #define SCR_FUNC_FABRIC 0x01 808dea3101eS #define SCR_FUNC_NPORT 0x02 809dea3101eS #define SCR_FUNC_FULL 0x03 810dea3101eS #define SCR_CLEAR 0xff 811dea3101eS } SCR; 812dea3101eS 813dea3101eS typedef struct _RNID_TOP_DISC { 814dea3101eS struct lpfc_name portName; 815dea3101eS uint8_t resvd[8]; 816dea3101eS uint32_t unitType; 817dea3101eS #define RNID_HBA 0x7 818dea3101eS #define RNID_HOST 0xa 819dea3101eS #define RNID_DRIVER 0xd 820dea3101eS uint32_t physPort; 821dea3101eS uint32_t attachedNodes; 822dea3101eS uint16_t ipVersion; 823dea3101eS #define RNID_IPV4 0x1 824dea3101eS #define RNID_IPV6 0x2 825dea3101eS uint16_t UDPport; 826dea3101eS uint8_t ipAddr[16]; 827dea3101eS uint16_t resvd1; 828dea3101eS uint16_t flags; 829dea3101eS #define RNID_TD_SUPPORT 0x1 830dea3101eS #define RNID_LP_VALID 0x2 831dea3101eS } RNID_TOP_DISC; 832dea3101eS 833dea3101eS typedef struct _RNID { /* Structure is in Big Endian format */ 834dea3101eS uint8_t Format; 835dea3101eS #define RNID_TOPOLOGY_DISC 0xdf 836dea3101eS uint8_t CommonLen; 837dea3101eS uint8_t resvd1; 838dea3101eS uint8_t SpecificLen; 839dea3101eS struct lpfc_name portName; 840dea3101eS struct lpfc_name nodeName; 841dea3101eS union { 842dea3101eS RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 843dea3101eS } un; 844dea3101eS } RNID; 845dea3101eS 8467bb3b137SJamie Wellnitz typedef struct _RPS { /* Structure is in Big Endian format */ 8477bb3b137SJamie Wellnitz union { 8487bb3b137SJamie Wellnitz uint32_t portNum; 8497bb3b137SJamie Wellnitz struct lpfc_name portName; 8507bb3b137SJamie Wellnitz } un; 8517bb3b137SJamie Wellnitz } RPS; 8527bb3b137SJamie Wellnitz 8537bb3b137SJamie Wellnitz typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 8547bb3b137SJamie Wellnitz uint16_t rsvd1; 8557bb3b137SJamie Wellnitz uint16_t portStatus; 8567bb3b137SJamie Wellnitz uint32_t linkFailureCnt; 8577bb3b137SJamie Wellnitz uint32_t lossSyncCnt; 8587bb3b137SJamie Wellnitz uint32_t lossSignalCnt; 8597bb3b137SJamie Wellnitz uint32_t primSeqErrCnt; 8607bb3b137SJamie Wellnitz uint32_t invalidXmitWord; 8617bb3b137SJamie Wellnitz uint32_t crcCnt; 8627bb3b137SJamie Wellnitz } RPS_RSP; 8637bb3b137SJamie Wellnitz 8647bb3b137SJamie Wellnitz typedef struct _RPL { /* Structure is in Big Endian format */ 8657bb3b137SJamie Wellnitz uint32_t maxsize; 8667bb3b137SJamie Wellnitz uint32_t index; 8677bb3b137SJamie Wellnitz } RPL; 8687bb3b137SJamie Wellnitz 8697bb3b137SJamie Wellnitz typedef struct _PORT_NUM_BLK { 8707bb3b137SJamie Wellnitz uint32_t portNum; 8717bb3b137SJamie Wellnitz uint32_t portID; 8727bb3b137SJamie Wellnitz struct lpfc_name portName; 8737bb3b137SJamie Wellnitz } PORT_NUM_BLK; 8747bb3b137SJamie Wellnitz 8757bb3b137SJamie Wellnitz typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 8767bb3b137SJamie Wellnitz uint32_t listLen; 8777bb3b137SJamie Wellnitz uint32_t index; 8787bb3b137SJamie Wellnitz PORT_NUM_BLK port_num_blk; 8797bb3b137SJamie Wellnitz } RPL_RSP; 880dea3101eS 881dea3101eS /* This is used for RSCN command */ 882dea3101eS typedef struct _D_ID { /* Structure is in Big Endian format */ 883dea3101eS union { 884dea3101eS uint32_t word; 885dea3101eS struct { 886dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 887dea3101eS uint8_t resv; 888dea3101eS uint8_t domain; 889dea3101eS uint8_t area; 890dea3101eS uint8_t id; 891dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 892dea3101eS uint8_t id; 893dea3101eS uint8_t area; 894dea3101eS uint8_t domain; 895dea3101eS uint8_t resv; 896dea3101eS #endif 897dea3101eS } b; 898dea3101eS } un; 899dea3101eS } D_ID; 900dea3101eS 901eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_PORT 0x0 902eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_AREA 0x1 903eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 904eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 905eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_MASK 0x3 906eaf15d5bSJames Smart 907dea3101eS /* 908dea3101eS * Structure to define all ELS Payload types 909dea3101eS */ 910dea3101eS 911dea3101eS typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 912dea3101eS uint8_t elsCode; /* FC Word 0, bit 24:31 */ 913dea3101eS uint8_t elsByte1; 914dea3101eS uint8_t elsByte2; 915dea3101eS uint8_t elsByte3; 916dea3101eS union { 917dea3101eS struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 918dea3101eS struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 919dea3101eS LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 920dea3101eS PRLI prli; /* Payload for PRLI/ACC */ 921dea3101eS PRLO prlo; /* Payload for PRLO/ACC */ 922dea3101eS ADISC adisc; /* Payload for ADISC/ACC */ 923dea3101eS FARP farp; /* Payload for FARP/ACC */ 924dea3101eS FAN fan; /* Payload for FAN */ 925dea3101eS SCR scr; /* Payload for SCR/ACC */ 926dea3101eS RNID rnid; /* Payload for RNID */ 927dea3101eS uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 928dea3101eS } un; 929dea3101eS } ELS_PKT; 930dea3101eS 931dea3101eS /* 932dea3101eS * FDMI 933dea3101eS * HBA MAnagement Operations Command Codes 934dea3101eS */ 935dea3101eS #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 936dea3101eS #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 937dea3101eS #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 938dea3101eS #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 939dea3101eS #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 940dea3101eS #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 941dea3101eS #define SLI_MGMT_RPRT 0x210 /* Register Port */ 942dea3101eS #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 943dea3101eS #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 944dea3101eS #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 945dea3101eS 946dea3101eS /* 947dea3101eS * Management Service Subtypes 948dea3101eS */ 949dea3101eS #define SLI_CT_FDMI_Subtypes 0x10 950dea3101eS 951dea3101eS /* 952dea3101eS * HBA Management Service Reject Code 953dea3101eS */ 954dea3101eS #define REJECT_CODE 0x9 /* Unable to perform command request */ 955dea3101eS 956dea3101eS /* 957dea3101eS * HBA Management Service Reject Reason Code 958dea3101eS * Please refer to the Reason Codes above 959dea3101eS */ 960dea3101eS 961dea3101eS /* 962dea3101eS * HBA Attribute Types 963dea3101eS */ 964dea3101eS #define NODE_NAME 0x1 965dea3101eS #define MANUFACTURER 0x2 966dea3101eS #define SERIAL_NUMBER 0x3 967dea3101eS #define MODEL 0x4 968dea3101eS #define MODEL_DESCRIPTION 0x5 969dea3101eS #define HARDWARE_VERSION 0x6 970dea3101eS #define DRIVER_VERSION 0x7 971dea3101eS #define OPTION_ROM_VERSION 0x8 972dea3101eS #define FIRMWARE_VERSION 0x9 973dea3101eS #define OS_NAME_VERSION 0xa 974dea3101eS #define MAX_CT_PAYLOAD_LEN 0xb 975dea3101eS 976dea3101eS /* 977dea3101eS * Port Attrubute Types 978dea3101eS */ 979dea3101eS #define SUPPORTED_FC4_TYPES 0x1 980dea3101eS #define SUPPORTED_SPEED 0x2 981dea3101eS #define PORT_SPEED 0x3 982dea3101eS #define MAX_FRAME_SIZE 0x4 983dea3101eS #define OS_DEVICE_NAME 0x5 984dea3101eS #define HOST_NAME 0x6 985dea3101eS 986dea3101eS union AttributesDef { 987dea3101eS /* Structure is in Big Endian format */ 988dea3101eS struct { 989dea3101eS uint32_t AttrType:16; 990dea3101eS uint32_t AttrLen:16; 991dea3101eS } bits; 992dea3101eS uint32_t word; 993dea3101eS }; 994dea3101eS 995dea3101eS 996dea3101eS /* 997dea3101eS * HBA Attribute Entry (8 - 260 bytes) 998dea3101eS */ 999dea3101eS typedef struct { 1000dea3101eS union AttributesDef ad; 1001dea3101eS union { 1002dea3101eS uint32_t VendorSpecific; 1003dea3101eS uint8_t Manufacturer[64]; 1004dea3101eS uint8_t SerialNumber[64]; 1005dea3101eS uint8_t Model[256]; 1006dea3101eS uint8_t ModelDescription[256]; 1007dea3101eS uint8_t HardwareVersion[256]; 1008dea3101eS uint8_t DriverVersion[256]; 1009dea3101eS uint8_t OptionROMVersion[256]; 1010dea3101eS uint8_t FirmwareVersion[256]; 1011dea3101eS struct lpfc_name NodeName; 1012dea3101eS uint8_t SupportFC4Types[32]; 1013dea3101eS uint32_t SupportSpeed; 1014dea3101eS uint32_t PortSpeed; 1015dea3101eS uint32_t MaxFrameSize; 1016dea3101eS uint8_t OsDeviceName[256]; 1017dea3101eS uint8_t OsNameVersion[256]; 1018dea3101eS uint32_t MaxCTPayloadLen; 1019dea3101eS uint8_t HostName[256]; 1020dea3101eS } un; 1021dea3101eS } ATTRIBUTE_ENTRY; 1022dea3101eS 1023dea3101eS /* 1024dea3101eS * HBA Attribute Block 1025dea3101eS */ 1026dea3101eS typedef struct { 1027dea3101eS uint32_t EntryCnt; /* Number of HBA attribute entries */ 1028dea3101eS ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 1029dea3101eS } ATTRIBUTE_BLOCK; 1030dea3101eS 1031dea3101eS /* 1032dea3101eS * Port Entry 1033dea3101eS */ 1034dea3101eS typedef struct { 1035dea3101eS struct lpfc_name PortName; 1036dea3101eS } PORT_ENTRY; 1037dea3101eS 1038dea3101eS /* 1039dea3101eS * HBA Identifier 1040dea3101eS */ 1041dea3101eS typedef struct { 1042dea3101eS struct lpfc_name PortName; 1043dea3101eS } HBA_IDENTIFIER; 1044dea3101eS 1045dea3101eS /* 1046dea3101eS * Registered Port List Format 1047dea3101eS */ 1048dea3101eS typedef struct { 1049dea3101eS uint32_t EntryCnt; 1050dea3101eS PORT_ENTRY pe; /* Variable-length array */ 1051dea3101eS } REG_PORT_LIST; 1052dea3101eS 1053dea3101eS /* 1054dea3101eS * Register HBA(RHBA) 1055dea3101eS */ 1056dea3101eS typedef struct { 1057dea3101eS HBA_IDENTIFIER hi; 1058dea3101eS REG_PORT_LIST rpl; /* variable-length array */ 1059dea3101eS /* ATTRIBUTE_BLOCK ab; */ 1060dea3101eS } REG_HBA; 1061dea3101eS 1062dea3101eS /* 1063dea3101eS * Register HBA Attributes (RHAT) 1064dea3101eS */ 1065dea3101eS typedef struct { 1066dea3101eS struct lpfc_name HBA_PortName; 1067dea3101eS ATTRIBUTE_BLOCK ab; 1068dea3101eS } REG_HBA_ATTRIBUTE; 1069dea3101eS 1070dea3101eS /* 1071dea3101eS * Register Port Attributes (RPA) 1072dea3101eS */ 1073dea3101eS typedef struct { 1074dea3101eS struct lpfc_name PortName; 1075dea3101eS ATTRIBUTE_BLOCK ab; 1076dea3101eS } REG_PORT_ATTRIBUTE; 1077dea3101eS 1078dea3101eS /* 1079dea3101eS * Get Registered HBA List (GRHL) Accept Payload Format 1080dea3101eS */ 1081dea3101eS typedef struct { 1082dea3101eS uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 1083dea3101eS struct lpfc_name HBA_PortName; /* Variable-length array */ 1084dea3101eS } GRHL_ACC_PAYLOAD; 1085dea3101eS 1086dea3101eS /* 1087dea3101eS * Get Registered Port List (GRPL) Accept Payload Format 1088dea3101eS */ 1089dea3101eS typedef struct { 1090dea3101eS uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 1091dea3101eS PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 1092dea3101eS } GRPL_ACC_PAYLOAD; 1093dea3101eS 1094dea3101eS /* 1095dea3101eS * Get Port Attributes (GPAT) Accept Payload Format 1096dea3101eS */ 1097dea3101eS 1098dea3101eS typedef struct { 1099dea3101eS ATTRIBUTE_BLOCK pab; 1100dea3101eS } GPAT_ACC_PAYLOAD; 1101dea3101eS 1102dea3101eS 1103dea3101eS /* 1104dea3101eS * Begin HBA configuration parameters. 1105dea3101eS * The PCI configuration register BAR assignments are: 1106dea3101eS * BAR0, offset 0x10 - SLIM base memory address 1107dea3101eS * BAR1, offset 0x14 - SLIM base memory high address 1108dea3101eS * BAR2, offset 0x18 - REGISTER base memory address 1109dea3101eS * BAR3, offset 0x1c - REGISTER base memory high address 1110dea3101eS * BAR4, offset 0x20 - BIU I/O registers 1111dea3101eS * BAR5, offset 0x24 - REGISTER base io high address 1112dea3101eS */ 1113dea3101eS 1114dea3101eS /* Number of rings currently used and available. */ 1115dea3101eS #define MAX_CONFIGURED_RINGS 3 1116dea3101eS #define MAX_RINGS 4 1117dea3101eS 1118dea3101eS /* IOCB / Mailbox is owned by FireFly */ 1119dea3101eS #define OWN_CHIP 1 1120dea3101eS 1121dea3101eS /* IOCB / Mailbox is owned by Host */ 1122dea3101eS #define OWN_HOST 0 1123dea3101eS 1124dea3101eS /* Number of 4-byte words in an IOCB. */ 1125dea3101eS #define IOCB_WORD_SZ 8 1126dea3101eS 1127dea3101eS /* defines for type field in fc header */ 1128dea3101eS #define FC_ELS_DATA 0x1 1129dea3101eS #define FC_LLC_SNAP 0x5 1130dea3101eS #define FC_FCP_DATA 0x8 1131dea3101eS #define FC_COMMON_TRANSPORT_ULP 0x20 1132dea3101eS 1133dea3101eS /* defines for rctl field in fc header */ 1134dea3101eS #define FC_DEV_DATA 0x0 1135dea3101eS #define FC_UNSOL_CTL 0x2 1136dea3101eS #define FC_SOL_CTL 0x3 1137dea3101eS #define FC_UNSOL_DATA 0x4 1138dea3101eS #define FC_FCP_CMND 0x6 1139dea3101eS #define FC_ELS_REQ 0x22 1140dea3101eS #define FC_ELS_RSP 0x23 1141dea3101eS 1142dea3101eS /* network headers for Dfctl field */ 1143dea3101eS #define FC_NET_HDR 0x20 1144dea3101eS 1145dea3101eS /* Start FireFly Register definitions */ 1146dea3101eS #define PCI_VENDOR_ID_EMULEX 0x10df 1147dea3101eS #define PCI_DEVICE_ID_FIREFLY 0x1ae5 114884774a4dSJames Smart #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 114984774a4dSJames Smart #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1150b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_SMB 0xf011 1151b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_MID 0xf015 1152dea3101eS #define PCI_DEVICE_ID_RFLY 0xf095 1153dea3101eS #define PCI_DEVICE_ID_PFLY 0xf098 1154e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_LP101 0xf0a1 1155dea3101eS #define PCI_DEVICE_ID_TFLY 0xf0a5 1156e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_BSMB 0xf0d1 1157e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_BMID 0xf0d5 1158e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZSMB 0xf0e1 1159e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZMID 0xf0e5 1160e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1161e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1162e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1163b87eab38SJames Smart #define PCI_DEVICE_ID_SAT 0xf100 1164b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1165b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1166e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_SUPERFLY 0xf700 1167e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1168dea3101eS #define PCI_DEVICE_ID_CENTAUR 0xf900 1169dea3101eS #define PCI_DEVICE_ID_PEGASUS 0xf980 1170dea3101eS #define PCI_DEVICE_ID_THOR 0xfa00 1171dea3101eS #define PCI_DEVICE_ID_VIPER 0xfb00 1172dea3101eS #define PCI_DEVICE_ID_LP10000S 0xfc00 1173e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_LP11000S 0xfc10 1174e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_LPE11000S 0xfc20 1175b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_S 0xfc40 117684774a4dSJames Smart #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1177e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_HELIOS 0xfd00 1178e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1179e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1180e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZEPHYR 0xfe00 118184774a4dSJames Smart #define PCI_DEVICE_ID_HORNET 0xfe05 1182e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1183e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1184da0436e9SJames Smart #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1185da0436e9SJames Smart #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1186da0436e9SJames Smart #define PCI_DEVICE_ID_TIGERSHARK_S 0x0705 1187dea3101eS 1188dea3101eS #define JEDEC_ID_ADDRESS 0x0080001c 1189dea3101eS #define FIREFLY_JEDEC_ID 0x1ACC 1190dea3101eS #define SUPERFLY_JEDEC_ID 0x0020 1191dea3101eS #define DRAGONFLY_JEDEC_ID 0x0021 1192dea3101eS #define DRAGONFLY_V2_JEDEC_ID 0x0025 1193dea3101eS #define CENTAUR_2G_JEDEC_ID 0x0026 1194dea3101eS #define CENTAUR_1G_JEDEC_ID 0x0028 1195dea3101eS #define PEGASUS_ORION_JEDEC_ID 0x0036 1196dea3101eS #define PEGASUS_JEDEC_ID 0x0038 1197dea3101eS #define THOR_JEDEC_ID 0x0012 1198dea3101eS #define HELIOS_JEDEC_ID 0x0364 1199dea3101eS #define ZEPHYR_JEDEC_ID 0x0577 1200dea3101eS #define VIPER_JEDEC_ID 0x4838 1201b87eab38SJames Smart #define SATURN_JEDEC_ID 0x1004 120284774a4dSJames Smart #define HORNET_JDEC_ID 0x2057706D 1203dea3101eS 1204dea3101eS #define JEDEC_ID_MASK 0x0FFFF000 1205dea3101eS #define JEDEC_ID_SHIFT 12 1206dea3101eS #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1207dea3101eS 1208dea3101eS typedef struct { /* FireFly BIU registers */ 1209dea3101eS uint32_t hostAtt; /* See definitions for Host Attention 1210dea3101eS register */ 1211dea3101eS uint32_t chipAtt; /* See definitions for Chip Attention 1212dea3101eS register */ 1213dea3101eS uint32_t hostStatus; /* See definitions for Host Status register */ 1214dea3101eS uint32_t hostControl; /* See definitions for Host Control register */ 1215dea3101eS uint32_t buiConfig; /* See definitions for BIU configuration 1216dea3101eS register */ 1217dea3101eS } FF_REGS; 1218dea3101eS 1219dea3101eS /* IO Register size in bytes */ 1220dea3101eS #define FF_REG_AREA_SIZE 256 1221dea3101eS 1222dea3101eS /* Host Attention Register */ 1223dea3101eS 1224dea3101eS #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1225dea3101eS 1226dea3101eS #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1227dea3101eS #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1228dea3101eS #define HA_R0ATT 0x00000008 /* Bit 3 */ 1229dea3101eS #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1230dea3101eS #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1231dea3101eS #define HA_R1ATT 0x00000080 /* Bit 7 */ 1232dea3101eS #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1233dea3101eS #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1234dea3101eS #define HA_R2ATT 0x00000800 /* Bit 11 */ 1235dea3101eS #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1236dea3101eS #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1237dea3101eS #define HA_R3ATT 0x00008000 /* Bit 15 */ 1238dea3101eS #define HA_LATT 0x20000000 /* Bit 29 */ 1239dea3101eS #define HA_MBATT 0x40000000 /* Bit 30 */ 1240dea3101eS #define HA_ERATT 0x80000000 /* Bit 31 */ 1241dea3101eS 1242dea3101eS #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1243dea3101eS #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1244dea3101eS #define HA_RXATT 0x00000008 /* Bit 3 */ 1245dea3101eS #define HA_RXMASK 0x0000000f 1246dea3101eS 12479399627fSJames Smart #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 12489399627fSJames Smart #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 12499399627fSJames Smart #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 12509399627fSJames Smart #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 12519399627fSJames Smart 12529399627fSJames Smart #define HA_R0_POS 3 12539399627fSJames Smart #define HA_R1_POS 7 12549399627fSJames Smart #define HA_R2_POS 11 12559399627fSJames Smart #define HA_R3_POS 15 12569399627fSJames Smart #define HA_LE_POS 29 12579399627fSJames Smart #define HA_MB_POS 30 12589399627fSJames Smart #define HA_ER_POS 31 1259dea3101eS /* Chip Attention Register */ 1260dea3101eS 1261dea3101eS #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1262dea3101eS 1263dea3101eS #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1264dea3101eS #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1265dea3101eS #define CA_R0ATT 0x00000008 /* Bit 3 */ 1266dea3101eS #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1267dea3101eS #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1268dea3101eS #define CA_R1ATT 0x00000080 /* Bit 7 */ 1269dea3101eS #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1270dea3101eS #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1271dea3101eS #define CA_R2ATT 0x00000800 /* Bit 11 */ 1272dea3101eS #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1273dea3101eS #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1274dea3101eS #define CA_R3ATT 0x00008000 /* Bit 15 */ 1275dea3101eS #define CA_MBATT 0x40000000 /* Bit 30 */ 1276dea3101eS 1277dea3101eS /* Host Status Register */ 1278dea3101eS 1279dea3101eS #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1280dea3101eS 1281dea3101eS #define HS_MBRDY 0x00400000 /* Bit 22 */ 1282dea3101eS #define HS_FFRDY 0x00800000 /* Bit 23 */ 1283dea3101eS #define HS_FFER8 0x01000000 /* Bit 24 */ 1284dea3101eS #define HS_FFER7 0x02000000 /* Bit 25 */ 1285dea3101eS #define HS_FFER6 0x04000000 /* Bit 26 */ 1286dea3101eS #define HS_FFER5 0x08000000 /* Bit 27 */ 1287dea3101eS #define HS_FFER4 0x10000000 /* Bit 28 */ 1288dea3101eS #define HS_FFER3 0x20000000 /* Bit 29 */ 1289dea3101eS #define HS_FFER2 0x40000000 /* Bit 30 */ 1290dea3101eS #define HS_FFER1 0x80000000 /* Bit 31 */ 129157127f15SJames Smart #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 129257127f15SJames Smart #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1293dea3101eS 1294dea3101eS /* Host Control Register */ 1295dea3101eS 12969399627fSJames Smart #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1297dea3101eS 1298dea3101eS #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1299dea3101eS #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1300dea3101eS #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1301dea3101eS #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1302dea3101eS #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1303dea3101eS #define HC_INITHBI 0x02000000 /* Bit 25 */ 1304dea3101eS #define HC_INITMB 0x04000000 /* Bit 26 */ 1305dea3101eS #define HC_INITFF 0x08000000 /* Bit 27 */ 1306dea3101eS #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1307dea3101eS #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1308dea3101eS 13099399627fSJames Smart /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 13109399627fSJames Smart #define MSIX_DFLT_ID 0 13119399627fSJames Smart #define MSIX_RNG0_ID 0 13129399627fSJames Smart #define MSIX_RNG1_ID 1 13139399627fSJames Smart #define MSIX_RNG2_ID 2 13149399627fSJames Smart #define MSIX_RNG3_ID 3 13159399627fSJames Smart 13169399627fSJames Smart #define MSIX_LINK_ID 4 13179399627fSJames Smart #define MSIX_MBOX_ID 5 13189399627fSJames Smart 13199399627fSJames Smart #define MSIX_SPARE0_ID 6 13209399627fSJames Smart #define MSIX_SPARE1_ID 7 13219399627fSJames Smart 1322dea3101eS /* Mailbox Commands */ 1323dea3101eS #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1324dea3101eS #define MBX_LOAD_SM 0x01 1325dea3101eS #define MBX_READ_NV 0x02 1326dea3101eS #define MBX_WRITE_NV 0x03 1327dea3101eS #define MBX_RUN_BIU_DIAG 0x04 1328dea3101eS #define MBX_INIT_LINK 0x05 1329dea3101eS #define MBX_DOWN_LINK 0x06 1330dea3101eS #define MBX_CONFIG_LINK 0x07 1331dea3101eS #define MBX_CONFIG_RING 0x09 1332dea3101eS #define MBX_RESET_RING 0x0A 1333dea3101eS #define MBX_READ_CONFIG 0x0B 1334dea3101eS #define MBX_READ_RCONFIG 0x0C 1335dea3101eS #define MBX_READ_SPARM 0x0D 1336dea3101eS #define MBX_READ_STATUS 0x0E 1337dea3101eS #define MBX_READ_RPI 0x0F 1338dea3101eS #define MBX_READ_XRI 0x10 1339dea3101eS #define MBX_READ_REV 0x11 1340dea3101eS #define MBX_READ_LNK_STAT 0x12 1341dea3101eS #define MBX_REG_LOGIN 0x13 1342dea3101eS #define MBX_UNREG_LOGIN 0x14 1343dea3101eS #define MBX_READ_LA 0x15 1344dea3101eS #define MBX_CLEAR_LA 0x16 1345dea3101eS #define MBX_DUMP_MEMORY 0x17 1346dea3101eS #define MBX_DUMP_CONTEXT 0x18 1347dea3101eS #define MBX_RUN_DIAGS 0x19 1348dea3101eS #define MBX_RESTART 0x1A 1349dea3101eS #define MBX_UPDATE_CFG 0x1B 1350dea3101eS #define MBX_DOWN_LOAD 0x1C 1351dea3101eS #define MBX_DEL_LD_ENTRY 0x1D 1352dea3101eS #define MBX_RUN_PROGRAM 0x1E 1353dea3101eS #define MBX_SET_MASK 0x20 135409372820SJames Smart #define MBX_SET_VARIABLE 0x21 1355dea3101eS #define MBX_UNREG_D_ID 0x23 135641415862SJamie Wellnitz #define MBX_KILL_BOARD 0x24 1357dea3101eS #define MBX_CONFIG_FARP 0x25 135841415862SJamie Wellnitz #define MBX_BEACON 0x2A 13599399627fSJames Smart #define MBX_CONFIG_MSI 0x30 1360858c9f6cSJames Smart #define MBX_HEARTBEAT 0x31 1361a8adb832SJames Smart #define MBX_WRITE_VPARMS 0x32 1362a8adb832SJames Smart #define MBX_ASYNCEVT_ENABLE 0x33 1363dea3101eS 136484774a4dSJames Smart #define MBX_PORT_CAPABILITIES 0x3B 136584774a4dSJames Smart #define MBX_PORT_IOV_CONTROL 0x3C 136684774a4dSJames Smart 1367ed957684SJames Smart #define MBX_CONFIG_HBQ 0x7C 1368dea3101eS #define MBX_LOAD_AREA 0x81 1369dea3101eS #define MBX_RUN_BIU_DIAG64 0x84 1370dea3101eS #define MBX_CONFIG_PORT 0x88 1371dea3101eS #define MBX_READ_SPARM64 0x8D 1372dea3101eS #define MBX_READ_RPI64 0x8F 1373dea3101eS #define MBX_REG_LOGIN64 0x93 1374dea3101eS #define MBX_READ_LA64 0x95 137592d7f7b0SJames Smart #define MBX_REG_VPI 0x96 137692d7f7b0SJames Smart #define MBX_UNREG_VPI 0x97 1377dea3101eS 137809372820SJames Smart #define MBX_WRITE_WWN 0x98 1379dea3101eS #define MBX_SET_DEBUG 0x99 1380dea3101eS #define MBX_LOAD_EXP_ROM 0x9C 1381da0436e9SJames Smart #define MBX_SLI4_CONFIG 0x9B 1382da0436e9SJames Smart #define MBX_SLI4_REQ_FTRS 0x9D 1383da0436e9SJames Smart #define MBX_MAX_CMDS 0x9E 1384da0436e9SJames Smart #define MBX_RESUME_RPI 0x9E 1385dea3101eS #define MBX_SLI2_CMD_MASK 0x80 1386da0436e9SJames Smart #define MBX_REG_VFI 0x9F 1387da0436e9SJames Smart #define MBX_REG_FCFI 0xA0 1388da0436e9SJames Smart #define MBX_UNREG_VFI 0xA1 1389da0436e9SJames Smart #define MBX_UNREG_FCFI 0xA2 1390da0436e9SJames Smart #define MBX_INIT_VFI 0xA3 1391da0436e9SJames Smart #define MBX_INIT_VPI 0xA4 1392dea3101eS 1393dea3101eS /* IOCB Commands */ 1394dea3101eS 1395dea3101eS #define CMD_RCV_SEQUENCE_CX 0x01 1396dea3101eS #define CMD_XMIT_SEQUENCE_CR 0x02 1397dea3101eS #define CMD_XMIT_SEQUENCE_CX 0x03 1398dea3101eS #define CMD_XMIT_BCAST_CN 0x04 1399dea3101eS #define CMD_XMIT_BCAST_CX 0x05 1400dea3101eS #define CMD_QUE_RING_BUF_CN 0x06 1401dea3101eS #define CMD_QUE_XRI_BUF_CX 0x07 1402dea3101eS #define CMD_IOCB_CONTINUE_CN 0x08 1403dea3101eS #define CMD_RET_XRI_BUF_CX 0x09 1404dea3101eS #define CMD_ELS_REQUEST_CR 0x0A 1405dea3101eS #define CMD_ELS_REQUEST_CX 0x0B 1406dea3101eS #define CMD_RCV_ELS_REQ_CX 0x0D 1407dea3101eS #define CMD_ABORT_XRI_CN 0x0E 1408dea3101eS #define CMD_ABORT_XRI_CX 0x0F 1409dea3101eS #define CMD_CLOSE_XRI_CN 0x10 1410dea3101eS #define CMD_CLOSE_XRI_CX 0x11 1411dea3101eS #define CMD_CREATE_XRI_CR 0x12 1412dea3101eS #define CMD_CREATE_XRI_CX 0x13 1413dea3101eS #define CMD_GET_RPI_CN 0x14 1414dea3101eS #define CMD_XMIT_ELS_RSP_CX 0x15 1415dea3101eS #define CMD_GET_RPI_CR 0x16 1416dea3101eS #define CMD_XRI_ABORTED_CX 0x17 1417dea3101eS #define CMD_FCP_IWRITE_CR 0x18 1418dea3101eS #define CMD_FCP_IWRITE_CX 0x19 1419dea3101eS #define CMD_FCP_IREAD_CR 0x1A 1420dea3101eS #define CMD_FCP_IREAD_CX 0x1B 1421dea3101eS #define CMD_FCP_ICMND_CR 0x1C 1422dea3101eS #define CMD_FCP_ICMND_CX 0x1D 1423f5603511SJames Smart #define CMD_FCP_TSEND_CX 0x1F 1424f5603511SJames Smart #define CMD_FCP_TRECEIVE_CX 0x21 1425f5603511SJames Smart #define CMD_FCP_TRSP_CX 0x23 1426f5603511SJames Smart #define CMD_FCP_AUTO_TRSP_CX 0x29 1427dea3101eS 1428dea3101eS #define CMD_ADAPTER_MSG 0x20 1429dea3101eS #define CMD_ADAPTER_DUMP 0x22 1430dea3101eS 1431dea3101eS /* SLI_2 IOCB Command Set */ 1432dea3101eS 143357127f15SJames Smart #define CMD_ASYNC_STATUS 0x7C 1434dea3101eS #define CMD_RCV_SEQUENCE64_CX 0x81 1435dea3101eS #define CMD_XMIT_SEQUENCE64_CR 0x82 1436dea3101eS #define CMD_XMIT_SEQUENCE64_CX 0x83 1437dea3101eS #define CMD_XMIT_BCAST64_CN 0x84 1438dea3101eS #define CMD_XMIT_BCAST64_CX 0x85 1439dea3101eS #define CMD_QUE_RING_BUF64_CN 0x86 1440dea3101eS #define CMD_QUE_XRI_BUF64_CX 0x87 1441dea3101eS #define CMD_IOCB_CONTINUE64_CN 0x88 1442dea3101eS #define CMD_RET_XRI_BUF64_CX 0x89 1443dea3101eS #define CMD_ELS_REQUEST64_CR 0x8A 1444dea3101eS #define CMD_ELS_REQUEST64_CX 0x8B 1445dea3101eS #define CMD_ABORT_MXRI64_CN 0x8C 1446dea3101eS #define CMD_RCV_ELS_REQ64_CX 0x8D 1447dea3101eS #define CMD_XMIT_ELS_RSP64_CX 0x95 1448dea3101eS #define CMD_FCP_IWRITE64_CR 0x98 1449dea3101eS #define CMD_FCP_IWRITE64_CX 0x99 1450dea3101eS #define CMD_FCP_IREAD64_CR 0x9A 1451dea3101eS #define CMD_FCP_IREAD64_CX 0x9B 1452dea3101eS #define CMD_FCP_ICMND64_CR 0x9C 1453dea3101eS #define CMD_FCP_ICMND64_CX 0x9D 1454f5603511SJames Smart #define CMD_FCP_TSEND64_CX 0x9F 1455f5603511SJames Smart #define CMD_FCP_TRECEIVE64_CX 0xA1 1456f5603511SJames Smart #define CMD_FCP_TRSP64_CX 0xA3 1457dea3101eS 145876bb24efSJames Smart #define CMD_QUE_XRI64_CX 0xB3 1459ed957684SJames Smart #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1460ed957684SJames Smart #define CMD_IOCB_RCV_ELS64_CX 0xB7 14613163f725SJames Smart #define CMD_IOCB_RET_XRI64_CX 0xB9 1462ed957684SJames Smart #define CMD_IOCB_RCV_CONT64_CX 0xBB 1463ed957684SJames Smart 1464dea3101eS #define CMD_GEN_REQUEST64_CR 0xC2 1465dea3101eS #define CMD_GEN_REQUEST64_CX 0xC3 1466dea3101eS 14673163f725SJames Smart /* Unhandled SLI-3 Commands */ 14683163f725SJames Smart #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 14693163f725SJames Smart #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 14703163f725SJames Smart #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 14713163f725SJames Smart #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 14723163f725SJames Smart #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 14733163f725SJames Smart #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 14743163f725SJames Smart #define CMD_IOCB_RET_HBQE64_CN 0xCA 14753163f725SJames Smart #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 14763163f725SJames Smart #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 14773163f725SJames Smart #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 14783163f725SJames Smart #define CMD_IOCB_LOGENTRY_CN 0x94 14793163f725SJames Smart #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 14803163f725SJames Smart 1481da0436e9SJames Smart /* Unhandled Data Security SLI Commands */ 1482da0436e9SJames Smart #define DSSCMD_IWRITE64_CR 0xD8 1483da0436e9SJames Smart #define DSSCMD_IWRITE64_CX 0xD9 1484da0436e9SJames Smart #define DSSCMD_IREAD64_CR 0xDA 1485da0436e9SJames Smart #define DSSCMD_IREAD64_CX 0xDB 1486da0436e9SJames Smart #define DSSCMD_INVALIDATE_DEK 0xDC 1487da0436e9SJames Smart #define DSSCMD_SET_KEK 0xDD 1488da0436e9SJames Smart #define DSSCMD_GET_KEK_ID 0xDE 1489da0436e9SJames Smart #define DSSCMD_GEN_XFER 0xDF 1490da0436e9SJames Smart 1491dea3101eS #define CMD_MAX_IOCB_CMD 0xE6 1492dea3101eS #define CMD_IOCB_MASK 0xff 1493dea3101eS 1494dea3101eS #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1495dea3101eS iocb */ 1496dea3101eS #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1497dea3101eS /* 1498dea3101eS * Define Status 1499dea3101eS */ 1500dea3101eS #define MBX_SUCCESS 0 1501dea3101eS #define MBXERR_NUM_RINGS 1 1502dea3101eS #define MBXERR_NUM_IOCBS 2 1503dea3101eS #define MBXERR_IOCBS_EXCEEDED 3 1504dea3101eS #define MBXERR_BAD_RING_NUMBER 4 1505dea3101eS #define MBXERR_MASK_ENTRIES_RANGE 5 1506dea3101eS #define MBXERR_MASKS_EXCEEDED 6 1507dea3101eS #define MBXERR_BAD_PROFILE 7 1508dea3101eS #define MBXERR_BAD_DEF_CLASS 8 1509dea3101eS #define MBXERR_BAD_MAX_RESPONDER 9 1510dea3101eS #define MBXERR_BAD_MAX_ORIGINATOR 10 1511dea3101eS #define MBXERR_RPI_REGISTERED 11 1512dea3101eS #define MBXERR_RPI_FULL 12 1513dea3101eS #define MBXERR_NO_RESOURCES 13 1514dea3101eS #define MBXERR_BAD_RCV_LENGTH 14 1515dea3101eS #define MBXERR_DMA_ERROR 15 1516dea3101eS #define MBXERR_ERROR 16 1517da0436e9SJames Smart #define MBXERR_LINK_DOWN 0x33 1518dea3101eS #define MBX_NOT_FINISHED 255 1519dea3101eS 1520dea3101eS #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1521dea3101eS #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1522dea3101eS 152357127f15SJames Smart #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 152457127f15SJames Smart 1525dea3101eS /* 1526dea3101eS * Begin Structure Definitions for Mailbox Commands 1527dea3101eS */ 1528dea3101eS 1529dea3101eS typedef struct { 1530dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1531dea3101eS uint8_t tval; 1532dea3101eS uint8_t tmask; 1533dea3101eS uint8_t rval; 1534dea3101eS uint8_t rmask; 1535dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1536dea3101eS uint8_t rmask; 1537dea3101eS uint8_t rval; 1538dea3101eS uint8_t tmask; 1539dea3101eS uint8_t tval; 1540dea3101eS #endif 1541dea3101eS } RR_REG; 1542dea3101eS 1543dea3101eS struct ulp_bde { 1544dea3101eS uint32_t bdeAddress; 1545dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1546dea3101eS uint32_t bdeReserved:4; 1547dea3101eS uint32_t bdeAddrHigh:4; 1548dea3101eS uint32_t bdeSize:24; 1549dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1550dea3101eS uint32_t bdeSize:24; 1551dea3101eS uint32_t bdeAddrHigh:4; 1552dea3101eS uint32_t bdeReserved:4; 1553dea3101eS #endif 1554dea3101eS }; 1555dea3101eS 1556dea3101eS typedef struct ULP_BDL { /* SLI-2 */ 1557dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1558dea3101eS uint32_t bdeFlags:8; /* BDL Flags */ 1559dea3101eS uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1560dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1561dea3101eS uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1562dea3101eS uint32_t bdeFlags:8; /* BDL Flags */ 1563dea3101eS #endif 1564dea3101eS 1565dea3101eS uint32_t addrLow; /* Address 0:31 */ 1566dea3101eS uint32_t addrHigh; /* Address 32:63 */ 1567dea3101eS uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1568dea3101eS } ULP_BDL; 1569dea3101eS 157081301a9bSJames Smart /* 157181301a9bSJames Smart * BlockGuard Definitions 157281301a9bSJames Smart */ 157381301a9bSJames Smart 157481301a9bSJames Smart enum lpfc_protgrp_type { 157581301a9bSJames Smart LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 157681301a9bSJames Smart LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 157781301a9bSJames Smart LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 157881301a9bSJames Smart LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 157981301a9bSJames Smart }; 158081301a9bSJames Smart 158181301a9bSJames Smart /* PDE Descriptors */ 158281301a9bSJames Smart #define LPFC_PDE1_DESCRIPTOR 0x81 158381301a9bSJames Smart #define LPFC_PDE2_DESCRIPTOR 0x82 158481301a9bSJames Smart #define LPFC_PDE3_DESCRIPTOR 0x83 158581301a9bSJames Smart 158681301a9bSJames Smart /* BlockGuard Profiles */ 158781301a9bSJames Smart enum lpfc_bg_prof_codes { 158881301a9bSJames Smart LPFC_PROF_INVALID, 158981301a9bSJames Smart LPFC_PROF_A1 = 128, /* Full Protection */ 159081301a9bSJames Smart LPFC_PROF_A2, /* Disabled Protection Checks:A2~A4 */ 159181301a9bSJames Smart LPFC_PROF_A3, 159281301a9bSJames Smart LPFC_PROF_A4, 159381301a9bSJames Smart LPFC_PROF_B1, /* Embedded DIFs: B1~B3 */ 159481301a9bSJames Smart LPFC_PROF_B2, 159581301a9bSJames Smart LPFC_PROF_B3, 159681301a9bSJames Smart LPFC_PROF_C1, /* Separate DIFs: C1~C3 */ 159781301a9bSJames Smart LPFC_PROF_C2, 159881301a9bSJames Smart LPFC_PROF_C3, 159981301a9bSJames Smart LPFC_PROF_D1, /* Full Protection */ 160081301a9bSJames Smart LPFC_PROF_D2, /* Partial Protection & Check Disabling */ 160181301a9bSJames Smart LPFC_PROF_D3, 160281301a9bSJames Smart LPFC_PROF_E1, /* E1~E4:out - check-only, in - update apptag */ 160381301a9bSJames Smart LPFC_PROF_E2, 160481301a9bSJames Smart LPFC_PROF_E3, 160581301a9bSJames Smart LPFC_PROF_E4, 160681301a9bSJames Smart LPFC_PROF_F1, /* Full Translation - F1 Prot Descriptor */ 160781301a9bSJames Smart /* F1 Translation BDE */ 160881301a9bSJames Smart LPFC_PROF_ANT1, /* TCP checksum, DIF inline with data buffers */ 160981301a9bSJames Smart LPFC_PROF_AST1, /* TCP checksum, DIF split from data buffer */ 161081301a9bSJames Smart LPFC_PROF_ANT2, 161181301a9bSJames Smart LPFC_PROF_AST2 161281301a9bSJames Smart }; 161381301a9bSJames Smart 161481301a9bSJames Smart /* BlockGuard error-control defines */ 161581301a9bSJames Smart #define BG_EC_STOP_ERR 0x00 161681301a9bSJames Smart #define BG_EC_CONT_ERR 0x01 161781301a9bSJames Smart #define BG_EC_IGN_UNINIT_STOP_ERR 0x10 161881301a9bSJames Smart #define BG_EC_IGN_UNINIT_CONT_ERR 0x11 161981301a9bSJames Smart 162081301a9bSJames Smart /* PDE (Protection Descriptor Entry) word 0 bit masks and shifts */ 162181301a9bSJames Smart #define PDE_DESC_TYPE_MASK 0xff000000 162281301a9bSJames Smart #define PDE_DESC_TYPE_SHIFT 24 162381301a9bSJames Smart #define PDE_BG_PROFILE_MASK 0x00ff0000 162481301a9bSJames Smart #define PDE_BG_PROFILE_SHIFT 16 162581301a9bSJames Smart #define PDE_BLOCK_LEN_MASK 0x0000fffc 162681301a9bSJames Smart #define PDE_BLOCK_LEN_SHIFT 2 162781301a9bSJames Smart #define PDE_ERR_CTRL_MASK 0x00000003 162881301a9bSJames Smart #define PDE_ERR_CTRL_SHIFT 0 162981301a9bSJames Smart /* PDE word 1 bit masks and shifts */ 163081301a9bSJames Smart #define PDE_APPTAG_MASK_MASK 0xffff0000 163181301a9bSJames Smart #define PDE_APPTAG_MASK_SHIFT 16 163281301a9bSJames Smart #define PDE_APPTAG_VAL_MASK 0x0000ffff 163381301a9bSJames Smart #define PDE_APPTAG_VAL_SHIFT 0 163481301a9bSJames Smart struct lpfc_pde { 163581301a9bSJames Smart uint32_t parms; /* bitfields of descriptor, prof, len, and ec */ 163681301a9bSJames Smart uint32_t apptag; /* bitfields of app tag maskand app tag value */ 163781301a9bSJames Smart uint32_t reftag; /* reference tag occupying all 32 bits */ 163881301a9bSJames Smart }; 163981301a9bSJames Smart 164081301a9bSJames Smart /* inline function to set fields in parms of PDE */ 164181301a9bSJames Smart static inline void 164281301a9bSJames Smart lpfc_pde_set_bg_parms(struct lpfc_pde *p, u8 desc, u8 prof, u16 len, u8 ec) 164381301a9bSJames Smart { 164481301a9bSJames Smart uint32_t *wp = &p->parms; 164581301a9bSJames Smart 164681301a9bSJames Smart /* spec indicates that adapter appends two 0's to length field */ 164781301a9bSJames Smart len = len >> 2; 164881301a9bSJames Smart 164981301a9bSJames Smart *wp &= 0; 165081301a9bSJames Smart *wp |= ((desc << PDE_DESC_TYPE_SHIFT) & PDE_DESC_TYPE_MASK); 165181301a9bSJames Smart *wp |= ((prof << PDE_BG_PROFILE_SHIFT) & PDE_BG_PROFILE_MASK); 165281301a9bSJames Smart *wp |= ((len << PDE_BLOCK_LEN_SHIFT) & PDE_BLOCK_LEN_MASK); 165381301a9bSJames Smart *wp |= ((ec << PDE_ERR_CTRL_SHIFT) & PDE_ERR_CTRL_MASK); 165481301a9bSJames Smart *wp = le32_to_cpu(*wp); 165581301a9bSJames Smart } 165681301a9bSJames Smart 165781301a9bSJames Smart /* inline function to set apptag and reftag fields of PDE */ 165881301a9bSJames Smart static inline void 165981301a9bSJames Smart lpfc_pde_set_dif_parms(struct lpfc_pde *p, u16 apptagmask, u16 apptagval, 166081301a9bSJames Smart u32 reftag) 166181301a9bSJames Smart { 166281301a9bSJames Smart uint32_t *wp = &p->apptag; 166381301a9bSJames Smart *wp &= 0; 166481301a9bSJames Smart *wp |= ((apptagmask << PDE_APPTAG_MASK_SHIFT) & PDE_APPTAG_MASK_MASK); 166581301a9bSJames Smart *wp |= ((apptagval << PDE_APPTAG_VAL_SHIFT) & PDE_APPTAG_VAL_MASK); 166681301a9bSJames Smart *wp = le32_to_cpu(*wp); 166781301a9bSJames Smart wp = &p->reftag; 166881301a9bSJames Smart *wp = le32_to_cpu(reftag); 166981301a9bSJames Smart } 167081301a9bSJames Smart 167181301a9bSJames Smart 1672dea3101eS /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1673dea3101eS 1674dea3101eS typedef struct { 1675dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1676dea3101eS uint32_t rsvd2:25; 1677dea3101eS uint32_t acknowledgment:1; 1678dea3101eS uint32_t version:1; 1679dea3101eS uint32_t erase_or_prog:1; 1680dea3101eS uint32_t update_flash:1; 1681dea3101eS uint32_t update_ram:1; 1682dea3101eS uint32_t method:1; 1683dea3101eS uint32_t load_cmplt:1; 1684dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1685dea3101eS uint32_t load_cmplt:1; 1686dea3101eS uint32_t method:1; 1687dea3101eS uint32_t update_ram:1; 1688dea3101eS uint32_t update_flash:1; 1689dea3101eS uint32_t erase_or_prog:1; 1690dea3101eS uint32_t version:1; 1691dea3101eS uint32_t acknowledgment:1; 1692dea3101eS uint32_t rsvd2:25; 1693dea3101eS #endif 1694dea3101eS 1695dea3101eS uint32_t dl_to_adr_low; 1696dea3101eS uint32_t dl_to_adr_high; 1697dea3101eS uint32_t dl_len; 1698dea3101eS union { 1699dea3101eS uint32_t dl_from_mbx_offset; 1700dea3101eS struct ulp_bde dl_from_bde; 1701dea3101eS struct ulp_bde64 dl_from_bde64; 1702dea3101eS } un; 1703dea3101eS 1704dea3101eS } LOAD_SM_VAR; 1705dea3101eS 1706dea3101eS /* Structure for MB Command READ_NVPARM (02) */ 1707dea3101eS 1708dea3101eS typedef struct { 1709dea3101eS uint32_t rsvd1[3]; /* Read as all one's */ 1710dea3101eS uint32_t rsvd2; /* Read as all zero's */ 1711dea3101eS uint32_t portname[2]; /* N_PORT name */ 1712dea3101eS uint32_t nodename[2]; /* NODE name */ 1713dea3101eS 1714dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1715dea3101eS uint32_t pref_DID:24; 1716dea3101eS uint32_t hardAL_PA:8; 1717dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1718dea3101eS uint32_t hardAL_PA:8; 1719dea3101eS uint32_t pref_DID:24; 1720dea3101eS #endif 1721dea3101eS 1722dea3101eS uint32_t rsvd3[21]; /* Read as all one's */ 1723dea3101eS } READ_NV_VAR; 1724dea3101eS 1725dea3101eS /* Structure for MB Command WRITE_NVPARMS (03) */ 1726dea3101eS 1727dea3101eS typedef struct { 1728dea3101eS uint32_t rsvd1[3]; /* Must be all one's */ 1729dea3101eS uint32_t rsvd2; /* Must be all zero's */ 1730dea3101eS uint32_t portname[2]; /* N_PORT name */ 1731dea3101eS uint32_t nodename[2]; /* NODE name */ 1732dea3101eS 1733dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1734dea3101eS uint32_t pref_DID:24; 1735dea3101eS uint32_t hardAL_PA:8; 1736dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1737dea3101eS uint32_t hardAL_PA:8; 1738dea3101eS uint32_t pref_DID:24; 1739dea3101eS #endif 1740dea3101eS 1741dea3101eS uint32_t rsvd3[21]; /* Must be all one's */ 1742dea3101eS } WRITE_NV_VAR; 1743dea3101eS 1744dea3101eS /* Structure for MB Command RUN_BIU_DIAG (04) */ 1745dea3101eS /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1746dea3101eS 1747dea3101eS typedef struct { 1748dea3101eS uint32_t rsvd1; 1749dea3101eS union { 1750dea3101eS struct { 1751dea3101eS struct ulp_bde xmit_bde; 1752dea3101eS struct ulp_bde rcv_bde; 1753dea3101eS } s1; 1754dea3101eS struct { 1755dea3101eS struct ulp_bde64 xmit_bde64; 1756dea3101eS struct ulp_bde64 rcv_bde64; 1757dea3101eS } s2; 1758dea3101eS } un; 1759dea3101eS } BIU_DIAG_VAR; 1760dea3101eS 1761dea3101eS /* Structure for MB Command INIT_LINK (05) */ 1762dea3101eS 1763dea3101eS typedef struct { 1764dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1765dea3101eS uint32_t rsvd1:24; 1766dea3101eS uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1767dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1768dea3101eS uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1769dea3101eS uint32_t rsvd1:24; 1770dea3101eS #endif 1771dea3101eS 1772dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1773dea3101eS uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1774dea3101eS uint8_t rsvd2; 1775dea3101eS uint16_t link_flags; 1776dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1777dea3101eS uint16_t link_flags; 1778dea3101eS uint8_t rsvd2; 1779dea3101eS uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1780dea3101eS #endif 1781dea3101eS 1782dea3101eS #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1783dea3101eS #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1784dea3101eS #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1785dea3101eS #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1786dea3101eS #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1787ed957684SJames Smart #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 1788dea3101eS #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1789dea3101eS 1790dea3101eS #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1791dea3101eS #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 17924b0b91d4SJames Smart #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 1793dea3101eS 1794dea3101eS uint32_t link_speed; 1795dea3101eS #define LINK_SPEED_AUTO 0 /* Auto selection */ 1796dea3101eS #define LINK_SPEED_1G 1 /* 1 Gigabaud */ 1797dea3101eS #define LINK_SPEED_2G 2 /* 2 Gigabaud */ 1798dea3101eS #define LINK_SPEED_4G 4 /* 4 Gigabaud */ 1799b87eab38SJames Smart #define LINK_SPEED_8G 8 /* 8 Gigabaud */ 1800dea3101eS #define LINK_SPEED_10G 16 /* 10 Gigabaud */ 1801dea3101eS 1802dea3101eS } INIT_LINK_VAR; 1803dea3101eS 1804dea3101eS /* Structure for MB Command DOWN_LINK (06) */ 1805dea3101eS 1806dea3101eS typedef struct { 1807dea3101eS uint32_t rsvd1; 1808dea3101eS } DOWN_LINK_VAR; 1809dea3101eS 1810dea3101eS /* Structure for MB Command CONFIG_LINK (07) */ 1811dea3101eS 1812dea3101eS typedef struct { 1813dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1814dea3101eS uint32_t cr:1; 1815dea3101eS uint32_t ci:1; 1816dea3101eS uint32_t cr_delay:6; 1817dea3101eS uint32_t cr_count:8; 1818dea3101eS uint32_t rsvd1:8; 1819dea3101eS uint32_t MaxBBC:8; 1820dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1821dea3101eS uint32_t MaxBBC:8; 1822dea3101eS uint32_t rsvd1:8; 1823dea3101eS uint32_t cr_count:8; 1824dea3101eS uint32_t cr_delay:6; 1825dea3101eS uint32_t ci:1; 1826dea3101eS uint32_t cr:1; 1827dea3101eS #endif 1828dea3101eS 1829dea3101eS uint32_t myId; 1830dea3101eS uint32_t rsvd2; 1831dea3101eS uint32_t edtov; 1832dea3101eS uint32_t arbtov; 1833dea3101eS uint32_t ratov; 1834dea3101eS uint32_t rttov; 1835dea3101eS uint32_t altov; 1836dea3101eS uint32_t crtov; 1837dea3101eS uint32_t citov; 1838dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1839dea3101eS uint32_t rrq_enable:1; 1840dea3101eS uint32_t rrq_immed:1; 1841dea3101eS uint32_t rsvd4:29; 1842dea3101eS uint32_t ack0_enable:1; 1843dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1844dea3101eS uint32_t ack0_enable:1; 1845dea3101eS uint32_t rsvd4:29; 1846dea3101eS uint32_t rrq_immed:1; 1847dea3101eS uint32_t rrq_enable:1; 1848dea3101eS #endif 1849dea3101eS } CONFIG_LINK; 1850dea3101eS 1851dea3101eS /* Structure for MB Command PART_SLIM (08) 1852dea3101eS * will be removed since SLI1 is no longer supported! 1853dea3101eS */ 1854dea3101eS typedef struct { 1855dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1856dea3101eS uint16_t offCiocb; 1857dea3101eS uint16_t numCiocb; 1858dea3101eS uint16_t offRiocb; 1859dea3101eS uint16_t numRiocb; 1860dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1861dea3101eS uint16_t numCiocb; 1862dea3101eS uint16_t offCiocb; 1863dea3101eS uint16_t numRiocb; 1864dea3101eS uint16_t offRiocb; 1865dea3101eS #endif 1866dea3101eS } RING_DEF; 1867dea3101eS 1868dea3101eS typedef struct { 1869dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1870dea3101eS uint32_t unused1:24; 1871dea3101eS uint32_t numRing:8; 1872dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1873dea3101eS uint32_t numRing:8; 1874dea3101eS uint32_t unused1:24; 1875dea3101eS #endif 1876dea3101eS 1877dea3101eS RING_DEF ringdef[4]; 1878dea3101eS uint32_t hbainit; 1879dea3101eS } PART_SLIM_VAR; 1880dea3101eS 1881dea3101eS /* Structure for MB Command CONFIG_RING (09) */ 1882dea3101eS 1883dea3101eS typedef struct { 1884dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1885dea3101eS uint32_t unused2:6; 1886dea3101eS uint32_t recvSeq:1; 1887dea3101eS uint32_t recvNotify:1; 1888dea3101eS uint32_t numMask:8; 1889dea3101eS uint32_t profile:8; 1890dea3101eS uint32_t unused1:4; 1891dea3101eS uint32_t ring:4; 1892dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1893dea3101eS uint32_t ring:4; 1894dea3101eS uint32_t unused1:4; 1895dea3101eS uint32_t profile:8; 1896dea3101eS uint32_t numMask:8; 1897dea3101eS uint32_t recvNotify:1; 1898dea3101eS uint32_t recvSeq:1; 1899dea3101eS uint32_t unused2:6; 1900dea3101eS #endif 1901dea3101eS 1902dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1903dea3101eS uint16_t maxRespXchg; 1904dea3101eS uint16_t maxOrigXchg; 1905dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1906dea3101eS uint16_t maxOrigXchg; 1907dea3101eS uint16_t maxRespXchg; 1908dea3101eS #endif 1909dea3101eS 1910dea3101eS RR_REG rrRegs[6]; 1911dea3101eS } CONFIG_RING_VAR; 1912dea3101eS 1913dea3101eS /* Structure for MB Command RESET_RING (10) */ 1914dea3101eS 1915dea3101eS typedef struct { 1916dea3101eS uint32_t ring_no; 1917dea3101eS } RESET_RING_VAR; 1918dea3101eS 1919dea3101eS /* Structure for MB Command READ_CONFIG (11) */ 1920dea3101eS 1921dea3101eS typedef struct { 1922dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1923dea3101eS uint32_t cr:1; 1924dea3101eS uint32_t ci:1; 1925dea3101eS uint32_t cr_delay:6; 1926dea3101eS uint32_t cr_count:8; 1927dea3101eS uint32_t InitBBC:8; 1928dea3101eS uint32_t MaxBBC:8; 1929dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1930dea3101eS uint32_t MaxBBC:8; 1931dea3101eS uint32_t InitBBC:8; 1932dea3101eS uint32_t cr_count:8; 1933dea3101eS uint32_t cr_delay:6; 1934dea3101eS uint32_t ci:1; 1935dea3101eS uint32_t cr:1; 1936dea3101eS #endif 1937dea3101eS 1938dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1939dea3101eS uint32_t topology:8; 1940dea3101eS uint32_t myDid:24; 1941dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1942dea3101eS uint32_t myDid:24; 1943dea3101eS uint32_t topology:8; 1944dea3101eS #endif 1945dea3101eS 1946dea3101eS /* Defines for topology (defined previously) */ 1947dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1948dea3101eS uint32_t AR:1; 1949dea3101eS uint32_t IR:1; 1950dea3101eS uint32_t rsvd1:29; 1951dea3101eS uint32_t ack0:1; 1952dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1953dea3101eS uint32_t ack0:1; 1954dea3101eS uint32_t rsvd1:29; 1955dea3101eS uint32_t IR:1; 1956dea3101eS uint32_t AR:1; 1957dea3101eS #endif 1958dea3101eS 1959dea3101eS uint32_t edtov; 1960dea3101eS uint32_t arbtov; 1961dea3101eS uint32_t ratov; 1962dea3101eS uint32_t rttov; 1963dea3101eS uint32_t altov; 1964dea3101eS uint32_t lmt; 196574b72a59SJamie Wellnitz #define LMT_RESERVED 0x000 /* Not used */ 196674b72a59SJamie Wellnitz #define LMT_1Gb 0x004 196774b72a59SJamie Wellnitz #define LMT_2Gb 0x008 196874b72a59SJamie Wellnitz #define LMT_4Gb 0x040 196974b72a59SJamie Wellnitz #define LMT_8Gb 0x080 197074b72a59SJamie Wellnitz #define LMT_10Gb 0x100 1971dea3101eS uint32_t rsvd2; 1972dea3101eS uint32_t rsvd3; 1973dea3101eS uint32_t max_xri; 1974dea3101eS uint32_t max_iocb; 1975dea3101eS uint32_t max_rpi; 1976dea3101eS uint32_t avail_xri; 1977dea3101eS uint32_t avail_iocb; 1978dea3101eS uint32_t avail_rpi; 1979858c9f6cSJames Smart uint32_t max_vpi; 1980858c9f6cSJames Smart uint32_t rsvd4; 1981858c9f6cSJames Smart uint32_t rsvd5; 1982858c9f6cSJames Smart uint32_t avail_vpi; 1983dea3101eS } READ_CONFIG_VAR; 1984dea3101eS 1985dea3101eS /* Structure for MB Command READ_RCONFIG (12) */ 1986dea3101eS 1987dea3101eS typedef struct { 1988dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1989dea3101eS uint32_t rsvd2:7; 1990dea3101eS uint32_t recvNotify:1; 1991dea3101eS uint32_t numMask:8; 1992dea3101eS uint32_t profile:8; 1993dea3101eS uint32_t rsvd1:4; 1994dea3101eS uint32_t ring:4; 1995dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1996dea3101eS uint32_t ring:4; 1997dea3101eS uint32_t rsvd1:4; 1998dea3101eS uint32_t profile:8; 1999dea3101eS uint32_t numMask:8; 2000dea3101eS uint32_t recvNotify:1; 2001dea3101eS uint32_t rsvd2:7; 2002dea3101eS #endif 2003dea3101eS 2004dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2005dea3101eS uint16_t maxResp; 2006dea3101eS uint16_t maxOrig; 2007dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2008dea3101eS uint16_t maxOrig; 2009dea3101eS uint16_t maxResp; 2010dea3101eS #endif 2011dea3101eS 2012dea3101eS RR_REG rrRegs[6]; 2013dea3101eS 2014dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2015dea3101eS uint16_t cmdRingOffset; 2016dea3101eS uint16_t cmdEntryCnt; 2017dea3101eS uint16_t rspRingOffset; 2018dea3101eS uint16_t rspEntryCnt; 2019dea3101eS uint16_t nextCmdOffset; 2020dea3101eS uint16_t rsvd3; 2021dea3101eS uint16_t nextRspOffset; 2022dea3101eS uint16_t rsvd4; 2023dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2024dea3101eS uint16_t cmdEntryCnt; 2025dea3101eS uint16_t cmdRingOffset; 2026dea3101eS uint16_t rspEntryCnt; 2027dea3101eS uint16_t rspRingOffset; 2028dea3101eS uint16_t rsvd3; 2029dea3101eS uint16_t nextCmdOffset; 2030dea3101eS uint16_t rsvd4; 2031dea3101eS uint16_t nextRspOffset; 2032dea3101eS #endif 2033dea3101eS } READ_RCONF_VAR; 2034dea3101eS 2035dea3101eS /* Structure for MB Command READ_SPARM (13) */ 2036dea3101eS /* Structure for MB Command READ_SPARM64 (0x8D) */ 2037dea3101eS 2038dea3101eS typedef struct { 2039dea3101eS uint32_t rsvd1; 2040dea3101eS uint32_t rsvd2; 2041dea3101eS union { 2042dea3101eS struct ulp_bde sp; /* This BDE points to struct serv_parm 2043dea3101eS structure */ 2044dea3101eS struct ulp_bde64 sp64; 2045dea3101eS } un; 2046ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2047ed957684SJames Smart uint16_t rsvd3; 2048ed957684SJames Smart uint16_t vpi; 2049ed957684SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 2050ed957684SJames Smart uint16_t vpi; 2051ed957684SJames Smart uint16_t rsvd3; 2052ed957684SJames Smart #endif 2053dea3101eS } READ_SPARM_VAR; 2054dea3101eS 2055dea3101eS /* Structure for MB Command READ_STATUS (14) */ 2056dea3101eS 2057dea3101eS typedef struct { 2058dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2059dea3101eS uint32_t rsvd1:31; 2060dea3101eS uint32_t clrCounters:1; 2061dea3101eS uint16_t activeXriCnt; 2062dea3101eS uint16_t activeRpiCnt; 2063dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2064dea3101eS uint32_t clrCounters:1; 2065dea3101eS uint32_t rsvd1:31; 2066dea3101eS uint16_t activeRpiCnt; 2067dea3101eS uint16_t activeXriCnt; 2068dea3101eS #endif 2069dea3101eS 2070dea3101eS uint32_t xmitByteCnt; 2071dea3101eS uint32_t rcvByteCnt; 2072dea3101eS uint32_t xmitFrameCnt; 2073dea3101eS uint32_t rcvFrameCnt; 2074dea3101eS uint32_t xmitSeqCnt; 2075dea3101eS uint32_t rcvSeqCnt; 2076dea3101eS uint32_t totalOrigExchanges; 2077dea3101eS uint32_t totalRespExchanges; 2078dea3101eS uint32_t rcvPbsyCnt; 2079dea3101eS uint32_t rcvFbsyCnt; 2080dea3101eS } READ_STATUS_VAR; 2081dea3101eS 2082dea3101eS /* Structure for MB Command READ_RPI (15) */ 2083dea3101eS /* Structure for MB Command READ_RPI64 (0x8F) */ 2084dea3101eS 2085dea3101eS typedef struct { 2086dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2087dea3101eS uint16_t nextRpi; 2088dea3101eS uint16_t reqRpi; 2089dea3101eS uint32_t rsvd2:8; 2090dea3101eS uint32_t DID:24; 2091dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2092dea3101eS uint16_t reqRpi; 2093dea3101eS uint16_t nextRpi; 2094dea3101eS uint32_t DID:24; 2095dea3101eS uint32_t rsvd2:8; 2096dea3101eS #endif 2097dea3101eS 2098dea3101eS union { 2099dea3101eS struct ulp_bde sp; 2100dea3101eS struct ulp_bde64 sp64; 2101dea3101eS } un; 2102dea3101eS 2103dea3101eS } READ_RPI_VAR; 2104dea3101eS 2105dea3101eS /* Structure for MB Command READ_XRI (16) */ 2106dea3101eS 2107dea3101eS typedef struct { 2108dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2109dea3101eS uint16_t nextXri; 2110dea3101eS uint16_t reqXri; 2111dea3101eS uint16_t rsvd1; 2112dea3101eS uint16_t rpi; 2113dea3101eS uint32_t rsvd2:8; 2114dea3101eS uint32_t DID:24; 2115dea3101eS uint32_t rsvd3:8; 2116dea3101eS uint32_t SID:24; 2117dea3101eS uint32_t rsvd4; 2118dea3101eS uint8_t seqId; 2119dea3101eS uint8_t rsvd5; 2120dea3101eS uint16_t seqCount; 2121dea3101eS uint16_t oxId; 2122dea3101eS uint16_t rxId; 2123dea3101eS uint32_t rsvd6:30; 2124dea3101eS uint32_t si:1; 2125dea3101eS uint32_t exchOrig:1; 2126dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2127dea3101eS uint16_t reqXri; 2128dea3101eS uint16_t nextXri; 2129dea3101eS uint16_t rpi; 2130dea3101eS uint16_t rsvd1; 2131dea3101eS uint32_t DID:24; 2132dea3101eS uint32_t rsvd2:8; 2133dea3101eS uint32_t SID:24; 2134dea3101eS uint32_t rsvd3:8; 2135dea3101eS uint32_t rsvd4; 2136dea3101eS uint16_t seqCount; 2137dea3101eS uint8_t rsvd5; 2138dea3101eS uint8_t seqId; 2139dea3101eS uint16_t rxId; 2140dea3101eS uint16_t oxId; 2141dea3101eS uint32_t exchOrig:1; 2142dea3101eS uint32_t si:1; 2143dea3101eS uint32_t rsvd6:30; 2144dea3101eS #endif 2145dea3101eS } READ_XRI_VAR; 2146dea3101eS 2147dea3101eS /* Structure for MB Command READ_REV (17) */ 2148dea3101eS 2149dea3101eS typedef struct { 2150dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2151dea3101eS uint32_t cv:1; 2152dea3101eS uint32_t rr:1; 2153ed957684SJames Smart uint32_t rsvd2:2; 2154ed957684SJames Smart uint32_t v3req:1; 2155ed957684SJames Smart uint32_t v3rsp:1; 2156ed957684SJames Smart uint32_t rsvd1:25; 2157dea3101eS uint32_t rv:1; 2158dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2159dea3101eS uint32_t rv:1; 2160ed957684SJames Smart uint32_t rsvd1:25; 2161ed957684SJames Smart uint32_t v3rsp:1; 2162ed957684SJames Smart uint32_t v3req:1; 2163ed957684SJames Smart uint32_t rsvd2:2; 2164dea3101eS uint32_t rr:1; 2165dea3101eS uint32_t cv:1; 2166dea3101eS #endif 2167dea3101eS 2168dea3101eS uint32_t biuRev; 2169dea3101eS uint32_t smRev; 2170dea3101eS union { 2171dea3101eS uint32_t smFwRev; 2172dea3101eS struct { 2173dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2174dea3101eS uint8_t ProgType; 2175dea3101eS uint8_t ProgId; 2176dea3101eS uint16_t ProgVer:4; 2177dea3101eS uint16_t ProgRev:4; 2178dea3101eS uint16_t ProgFixLvl:2; 2179dea3101eS uint16_t ProgDistType:2; 2180dea3101eS uint16_t DistCnt:4; 2181dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2182dea3101eS uint16_t DistCnt:4; 2183dea3101eS uint16_t ProgDistType:2; 2184dea3101eS uint16_t ProgFixLvl:2; 2185dea3101eS uint16_t ProgRev:4; 2186dea3101eS uint16_t ProgVer:4; 2187dea3101eS uint8_t ProgId; 2188dea3101eS uint8_t ProgType; 2189dea3101eS #endif 2190dea3101eS 2191dea3101eS } b; 2192dea3101eS } un; 2193dea3101eS uint32_t endecRev; 2194dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2195dea3101eS uint8_t feaLevelHigh; 2196dea3101eS uint8_t feaLevelLow; 2197dea3101eS uint8_t fcphHigh; 2198dea3101eS uint8_t fcphLow; 2199dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2200dea3101eS uint8_t fcphLow; 2201dea3101eS uint8_t fcphHigh; 2202dea3101eS uint8_t feaLevelLow; 2203dea3101eS uint8_t feaLevelHigh; 2204dea3101eS #endif 2205dea3101eS 2206dea3101eS uint32_t postKernRev; 2207dea3101eS uint32_t opFwRev; 2208dea3101eS uint8_t opFwName[16]; 2209dea3101eS uint32_t sli1FwRev; 2210dea3101eS uint8_t sli1FwName[16]; 2211dea3101eS uint32_t sli2FwRev; 2212dea3101eS uint8_t sli2FwName[16]; 2213ed957684SJames Smart uint32_t sli3Feat; 2214ed957684SJames Smart uint32_t RandomData[6]; 2215dea3101eS } READ_REV_VAR; 2216dea3101eS 2217dea3101eS /* Structure for MB Command READ_LINK_STAT (18) */ 2218dea3101eS 2219dea3101eS typedef struct { 2220dea3101eS uint32_t rsvd1; 2221dea3101eS uint32_t linkFailureCnt; 2222dea3101eS uint32_t lossSyncCnt; 2223dea3101eS 2224dea3101eS uint32_t lossSignalCnt; 2225dea3101eS uint32_t primSeqErrCnt; 2226dea3101eS uint32_t invalidXmitWord; 2227dea3101eS uint32_t crcCnt; 2228dea3101eS uint32_t primSeqTimeout; 2229dea3101eS uint32_t elasticOverrun; 2230dea3101eS uint32_t arbTimeout; 2231dea3101eS } READ_LNK_VAR; 2232dea3101eS 2233dea3101eS /* Structure for MB Command REG_LOGIN (19) */ 2234dea3101eS /* Structure for MB Command REG_LOGIN64 (0x93) */ 2235dea3101eS 2236dea3101eS typedef struct { 2237dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2238dea3101eS uint16_t rsvd1; 2239dea3101eS uint16_t rpi; 2240dea3101eS uint32_t rsvd2:8; 2241dea3101eS uint32_t did:24; 2242dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2243dea3101eS uint16_t rpi; 2244dea3101eS uint16_t rsvd1; 2245dea3101eS uint32_t did:24; 2246dea3101eS uint32_t rsvd2:8; 2247dea3101eS #endif 2248dea3101eS 2249dea3101eS union { 2250dea3101eS struct ulp_bde sp; 2251dea3101eS struct ulp_bde64 sp64; 2252dea3101eS } un; 2253dea3101eS 2254ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2255ed957684SJames Smart uint16_t rsvd6; 2256ed957684SJames Smart uint16_t vpi; 2257ed957684SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 2258ed957684SJames Smart uint16_t vpi; 2259ed957684SJames Smart uint16_t rsvd6; 2260ed957684SJames Smart #endif 2261ed957684SJames Smart 2262dea3101eS } REG_LOGIN_VAR; 2263dea3101eS 2264dea3101eS /* Word 30 contents for REG_LOGIN */ 2265dea3101eS typedef union { 2266dea3101eS struct { 2267dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2268dea3101eS uint16_t rsvd1:12; 2269dea3101eS uint16_t wd30_class:4; 2270dea3101eS uint16_t xri; 2271dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2272dea3101eS uint16_t xri; 2273dea3101eS uint16_t wd30_class:4; 2274dea3101eS uint16_t rsvd1:12; 2275dea3101eS #endif 2276dea3101eS } f; 2277dea3101eS uint32_t word; 2278dea3101eS } REG_WD30; 2279dea3101eS 2280dea3101eS /* Structure for MB Command UNREG_LOGIN (20) */ 2281dea3101eS 2282dea3101eS typedef struct { 2283dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2284dea3101eS uint16_t rsvd1; 2285dea3101eS uint16_t rpi; 2286ed957684SJames Smart uint32_t rsvd2; 2287ed957684SJames Smart uint32_t rsvd3; 2288ed957684SJames Smart uint32_t rsvd4; 2289ed957684SJames Smart uint32_t rsvd5; 2290ed957684SJames Smart uint16_t rsvd6; 2291ed957684SJames Smart uint16_t vpi; 2292dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2293dea3101eS uint16_t rpi; 2294dea3101eS uint16_t rsvd1; 2295ed957684SJames Smart uint32_t rsvd2; 2296ed957684SJames Smart uint32_t rsvd3; 2297ed957684SJames Smart uint32_t rsvd4; 2298ed957684SJames Smart uint32_t rsvd5; 2299ed957684SJames Smart uint16_t vpi; 2300ed957684SJames Smart uint16_t rsvd6; 2301dea3101eS #endif 2302dea3101eS } UNREG_LOGIN_VAR; 2303dea3101eS 230492d7f7b0SJames Smart /* Structure for MB Command REG_VPI (0x96) */ 230592d7f7b0SJames Smart typedef struct { 230692d7f7b0SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 230792d7f7b0SJames Smart uint32_t rsvd1; 230892d7f7b0SJames Smart uint32_t rsvd2:8; 230992d7f7b0SJames Smart uint32_t sid:24; 231092d7f7b0SJames Smart uint32_t rsvd3; 231192d7f7b0SJames Smart uint32_t rsvd4; 231292d7f7b0SJames Smart uint32_t rsvd5; 2313da0436e9SJames Smart uint16_t vfi; 231492d7f7b0SJames Smart uint16_t vpi; 231592d7f7b0SJames Smart #else /* __LITTLE_ENDIAN */ 231692d7f7b0SJames Smart uint32_t rsvd1; 231792d7f7b0SJames Smart uint32_t sid:24; 231892d7f7b0SJames Smart uint32_t rsvd2:8; 231992d7f7b0SJames Smart uint32_t rsvd3; 232092d7f7b0SJames Smart uint32_t rsvd4; 232192d7f7b0SJames Smart uint32_t rsvd5; 232292d7f7b0SJames Smart uint16_t vpi; 2323da0436e9SJames Smart uint16_t vfi; 232492d7f7b0SJames Smart #endif 232592d7f7b0SJames Smart } REG_VPI_VAR; 232692d7f7b0SJames Smart 232792d7f7b0SJames Smart /* Structure for MB Command UNREG_VPI (0x97) */ 232892d7f7b0SJames Smart typedef struct { 232992d7f7b0SJames Smart uint32_t rsvd1; 233092d7f7b0SJames Smart uint32_t rsvd2; 233192d7f7b0SJames Smart uint32_t rsvd3; 233292d7f7b0SJames Smart uint32_t rsvd4; 233392d7f7b0SJames Smart uint32_t rsvd5; 233492d7f7b0SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 233592d7f7b0SJames Smart uint16_t rsvd6; 233692d7f7b0SJames Smart uint16_t vpi; 233792d7f7b0SJames Smart #else /* __LITTLE_ENDIAN */ 233892d7f7b0SJames Smart uint16_t vpi; 233992d7f7b0SJames Smart uint16_t rsvd6; 234092d7f7b0SJames Smart #endif 234192d7f7b0SJames Smart } UNREG_VPI_VAR; 234292d7f7b0SJames Smart 2343dea3101eS /* Structure for MB Command UNREG_D_ID (0x23) */ 2344dea3101eS 2345dea3101eS typedef struct { 2346dea3101eS uint32_t did; 2347ed957684SJames Smart uint32_t rsvd2; 2348ed957684SJames Smart uint32_t rsvd3; 2349ed957684SJames Smart uint32_t rsvd4; 2350ed957684SJames Smart uint32_t rsvd5; 2351ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2352ed957684SJames Smart uint16_t rsvd6; 2353ed957684SJames Smart uint16_t vpi; 2354ed957684SJames Smart #else 2355ed957684SJames Smart uint16_t vpi; 2356ed957684SJames Smart uint16_t rsvd6; 2357ed957684SJames Smart #endif 2358dea3101eS } UNREG_D_ID_VAR; 2359dea3101eS 2360dea3101eS /* Structure for MB Command READ_LA (21) */ 2361dea3101eS /* Structure for MB Command READ_LA64 (0x95) */ 2362dea3101eS 2363dea3101eS typedef struct { 2364dea3101eS uint32_t eventTag; /* Event tag */ 2365dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 236684774a4dSJames Smart uint32_t rsvd1:19; 236784774a4dSJames Smart uint32_t fa:1; 236884774a4dSJames Smart uint32_t mm:1; /* Menlo Maintenance mode enabled */ 236984774a4dSJames Smart uint32_t rx:1; 2370dea3101eS uint32_t pb:1; 2371dea3101eS uint32_t il:1; 2372dea3101eS uint32_t attType:8; 2373dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2374dea3101eS uint32_t attType:8; 2375dea3101eS uint32_t il:1; 2376dea3101eS uint32_t pb:1; 237784774a4dSJames Smart uint32_t rx:1; 237884774a4dSJames Smart uint32_t mm:1; 237984774a4dSJames Smart uint32_t fa:1; 238084774a4dSJames Smart uint32_t rsvd1:19; 2381dea3101eS #endif 2382dea3101eS 2383dea3101eS #define AT_RESERVED 0x00 /* Reserved - attType */ 2384dea3101eS #define AT_LINK_UP 0x01 /* Link is up */ 2385dea3101eS #define AT_LINK_DOWN 0x02 /* Link is down */ 2386dea3101eS 2387dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2388dea3101eS uint8_t granted_AL_PA; 2389dea3101eS uint8_t lipAlPs; 2390dea3101eS uint8_t lipType; 2391dea3101eS uint8_t topology; 2392dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2393dea3101eS uint8_t topology; 2394dea3101eS uint8_t lipType; 2395dea3101eS uint8_t lipAlPs; 2396dea3101eS uint8_t granted_AL_PA; 2397dea3101eS #endif 2398dea3101eS 2399dea3101eS #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2400dea3101eS #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 240184774a4dSJames Smart #define TOPOLOGY_LNK_MENLO_MAINTENANCE 0x05 /* maint mode zephtr to menlo */ 2402dea3101eS 2403dea3101eS union { 2404dea3101eS struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer 2405dea3101eS to */ 2406dea3101eS /* store the LILP AL_PA position map into */ 2407dea3101eS struct ulp_bde64 lilpBde64; 2408dea3101eS } un; 2409dea3101eS 2410dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2411dea3101eS uint32_t Dlu:1; 2412dea3101eS uint32_t Dtf:1; 2413dea3101eS uint32_t Drsvd2:14; 2414dea3101eS uint32_t DlnkSpeed:8; 2415dea3101eS uint32_t DnlPort:4; 2416dea3101eS uint32_t Dtx:2; 2417dea3101eS uint32_t Drx:2; 2418dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2419dea3101eS uint32_t Drx:2; 2420dea3101eS uint32_t Dtx:2; 2421dea3101eS uint32_t DnlPort:4; 2422dea3101eS uint32_t DlnkSpeed:8; 2423dea3101eS uint32_t Drsvd2:14; 2424dea3101eS uint32_t Dtf:1; 2425dea3101eS uint32_t Dlu:1; 2426dea3101eS #endif 2427dea3101eS 2428dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2429dea3101eS uint32_t Ulu:1; 2430dea3101eS uint32_t Utf:1; 2431dea3101eS uint32_t Ursvd2:14; 2432dea3101eS uint32_t UlnkSpeed:8; 2433dea3101eS uint32_t UnlPort:4; 2434dea3101eS uint32_t Utx:2; 2435dea3101eS uint32_t Urx:2; 2436dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2437dea3101eS uint32_t Urx:2; 2438dea3101eS uint32_t Utx:2; 2439dea3101eS uint32_t UnlPort:4; 2440dea3101eS uint32_t UlnkSpeed:8; 2441dea3101eS uint32_t Ursvd2:14; 2442dea3101eS uint32_t Utf:1; 2443dea3101eS uint32_t Ulu:1; 2444dea3101eS #endif 2445dea3101eS 2446dea3101eS #define LA_UNKNW_LINK 0x0 /* lnkSpeed */ 2447dea3101eS #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 2448dea3101eS #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 2449dea3101eS #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 2450dea3101eS #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 2451dea3101eS #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 2452dea3101eS 2453dea3101eS } READ_LA_VAR; 2454dea3101eS 2455dea3101eS /* Structure for MB Command CLEAR_LA (22) */ 2456dea3101eS 2457dea3101eS typedef struct { 2458dea3101eS uint32_t eventTag; /* Event tag */ 2459dea3101eS uint32_t rsvd1; 2460dea3101eS } CLEAR_LA_VAR; 2461dea3101eS 2462dea3101eS /* Structure for MB Command DUMP */ 2463dea3101eS 2464dea3101eS typedef struct { 2465dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2466dea3101eS uint32_t rsvd:25; 2467dea3101eS uint32_t ra:1; 2468dea3101eS uint32_t co:1; 2469dea3101eS uint32_t cv:1; 2470dea3101eS uint32_t type:4; 2471dea3101eS uint32_t entry_index:16; 2472dea3101eS uint32_t region_id:16; 2473dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2474dea3101eS uint32_t type:4; 2475dea3101eS uint32_t cv:1; 2476dea3101eS uint32_t co:1; 2477dea3101eS uint32_t ra:1; 2478dea3101eS uint32_t rsvd:25; 2479dea3101eS uint32_t region_id:16; 2480dea3101eS uint32_t entry_index:16; 2481dea3101eS #endif 2482dea3101eS 2483da0436e9SJames Smart uint32_t sli4_length; 2484dea3101eS uint32_t word_cnt; 2485dea3101eS uint32_t resp_offset; 2486dea3101eS } DUMP_VAR; 2487dea3101eS 2488dea3101eS #define DMP_MEM_REG 0x1 2489dea3101eS #define DMP_NV_PARAMS 0x2 2490dea3101eS 2491dea3101eS #define DMP_REGION_VPD 0xe 2492dea3101eS #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2493dea3101eS #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2494dea3101eS #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2495dea3101eS 2496da0436e9SJames Smart #define DMP_REGION_VPORT 0x16 /* VPort info region */ 2497da0436e9SJames Smart #define DMP_VPORT_REGION_SIZE 0x200 2498da0436e9SJames Smart #define DMP_MBOX_OFFSET_WORD 0x5 2499da0436e9SJames Smart 2500da0436e9SJames Smart #define DMP_REGION_FCOEPARAM 0x17 /* fcoe param region */ 2501da0436e9SJames Smart #define DMP_FCOEPARAM_RGN_SIZE 0x400 2502da0436e9SJames Smart 250397207482SJames Smart #define WAKE_UP_PARMS_REGION_ID 4 250497207482SJames Smart #define WAKE_UP_PARMS_WORD_SIZE 15 250597207482SJames Smart 2506da0436e9SJames Smart struct vport_rec { 2507da0436e9SJames Smart uint8_t wwpn[8]; 2508da0436e9SJames Smart uint8_t wwnn[8]; 2509da0436e9SJames Smart }; 2510da0436e9SJames Smart 2511da0436e9SJames Smart #define VPORT_INFO_SIG 0x32324752 2512da0436e9SJames Smart #define VPORT_INFO_REV_MASK 0xff 2513da0436e9SJames Smart #define VPORT_INFO_REV 0x1 2514da0436e9SJames Smart #define MAX_STATIC_VPORT_COUNT 16 2515da0436e9SJames Smart struct static_vport_info { 2516da0436e9SJames Smart uint32_t signature; 2517da0436e9SJames Smart uint32_t rev; 2518da0436e9SJames Smart struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 2519da0436e9SJames Smart uint32_t resvd[66]; 2520da0436e9SJames Smart }; 2521da0436e9SJames Smart 252297207482SJames Smart /* Option rom version structure */ 252397207482SJames Smart struct prog_id { 252497207482SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 252597207482SJames Smart uint8_t type; 252697207482SJames Smart uint8_t id; 252797207482SJames Smart uint32_t ver:4; /* Major Version */ 252897207482SJames Smart uint32_t rev:4; /* Revision */ 252997207482SJames Smart uint32_t lev:2; /* Level */ 253097207482SJames Smart uint32_t dist:2; /* Dist Type */ 253197207482SJames Smart uint32_t num:4; /* number after dist type */ 253297207482SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 253397207482SJames Smart uint32_t num:4; /* number after dist type */ 253497207482SJames Smart uint32_t dist:2; /* Dist Type */ 253597207482SJames Smart uint32_t lev:2; /* Level */ 253697207482SJames Smart uint32_t rev:4; /* Revision */ 253797207482SJames Smart uint32_t ver:4; /* Major Version */ 253897207482SJames Smart uint8_t id; 253997207482SJames Smart uint8_t type; 254097207482SJames Smart #endif 254197207482SJames Smart }; 254297207482SJames Smart 2543d7c255b2SJames Smart /* Structure for MB Command UPDATE_CFG (0x1B) */ 2544d7c255b2SJames Smart 2545d7c255b2SJames Smart struct update_cfg_var { 2546d7c255b2SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2547d7c255b2SJames Smart uint32_t rsvd2:16; 2548d7c255b2SJames Smart uint32_t type:8; 2549d7c255b2SJames Smart uint32_t rsvd:1; 2550d7c255b2SJames Smart uint32_t ra:1; 2551d7c255b2SJames Smart uint32_t co:1; 2552d7c255b2SJames Smart uint32_t cv:1; 2553d7c255b2SJames Smart uint32_t req:4; 2554d7c255b2SJames Smart uint32_t entry_length:16; 2555d7c255b2SJames Smart uint32_t region_id:16; 2556d7c255b2SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 2557d7c255b2SJames Smart uint32_t req:4; 2558d7c255b2SJames Smart uint32_t cv:1; 2559d7c255b2SJames Smart uint32_t co:1; 2560d7c255b2SJames Smart uint32_t ra:1; 2561d7c255b2SJames Smart uint32_t rsvd:1; 2562d7c255b2SJames Smart uint32_t type:8; 2563d7c255b2SJames Smart uint32_t rsvd2:16; 2564d7c255b2SJames Smart uint32_t region_id:16; 2565d7c255b2SJames Smart uint32_t entry_length:16; 2566d7c255b2SJames Smart #endif 2567d7c255b2SJames Smart 2568d7c255b2SJames Smart uint32_t resp_info; 2569d7c255b2SJames Smart uint32_t byte_cnt; 2570d7c255b2SJames Smart uint32_t data_offset; 2571d7c255b2SJames Smart }; 2572d7c255b2SJames Smart 2573ed957684SJames Smart struct hbq_mask { 2574ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2575ed957684SJames Smart uint8_t tmatch; 2576ed957684SJames Smart uint8_t tmask; 2577ed957684SJames Smart uint8_t rctlmatch; 2578ed957684SJames Smart uint8_t rctlmask; 2579ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2580ed957684SJames Smart uint8_t rctlmask; 2581ed957684SJames Smart uint8_t rctlmatch; 2582ed957684SJames Smart uint8_t tmask; 2583ed957684SJames Smart uint8_t tmatch; 2584ed957684SJames Smart #endif 2585ed957684SJames Smart }; 2586ed957684SJames Smart 2587ed957684SJames Smart 2588ed957684SJames Smart /* Structure for MB Command CONFIG_HBQ (7c) */ 2589ed957684SJames Smart 2590ed957684SJames Smart struct config_hbq_var { 2591ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2592ed957684SJames Smart uint32_t rsvd1 :7; 2593ed957684SJames Smart uint32_t recvNotify :1; /* Receive Notification */ 2594ed957684SJames Smart uint32_t numMask :8; /* # Mask Entries */ 2595ed957684SJames Smart uint32_t profile :8; /* Selection Profile */ 2596ed957684SJames Smart uint32_t rsvd2 :8; 2597ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2598ed957684SJames Smart uint32_t rsvd2 :8; 2599ed957684SJames Smart uint32_t profile :8; /* Selection Profile */ 2600ed957684SJames Smart uint32_t numMask :8; /* # Mask Entries */ 2601ed957684SJames Smart uint32_t recvNotify :1; /* Receive Notification */ 2602ed957684SJames Smart uint32_t rsvd1 :7; 2603ed957684SJames Smart #endif 2604ed957684SJames Smart 2605ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2606ed957684SJames Smart uint32_t hbqId :16; 2607ed957684SJames Smart uint32_t rsvd3 :12; 2608ed957684SJames Smart uint32_t ringMask :4; 2609ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2610ed957684SJames Smart uint32_t ringMask :4; 2611ed957684SJames Smart uint32_t rsvd3 :12; 2612ed957684SJames Smart uint32_t hbqId :16; 2613ed957684SJames Smart #endif 2614ed957684SJames Smart 2615ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2616ed957684SJames Smart uint32_t entry_count :16; 2617ed957684SJames Smart uint32_t rsvd4 :8; 2618ed957684SJames Smart uint32_t headerLen :8; 2619ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2620ed957684SJames Smart uint32_t headerLen :8; 2621ed957684SJames Smart uint32_t rsvd4 :8; 2622ed957684SJames Smart uint32_t entry_count :16; 2623ed957684SJames Smart #endif 2624ed957684SJames Smart 2625ed957684SJames Smart uint32_t hbqaddrLow; 2626ed957684SJames Smart uint32_t hbqaddrHigh; 2627ed957684SJames Smart 2628ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2629ed957684SJames Smart uint32_t rsvd5 :31; 2630ed957684SJames Smart uint32_t logEntry :1; 2631ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2632ed957684SJames Smart uint32_t logEntry :1; 2633ed957684SJames Smart uint32_t rsvd5 :31; 2634ed957684SJames Smart #endif 2635ed957684SJames Smart 2636ed957684SJames Smart uint32_t rsvd6; /* w7 */ 2637ed957684SJames Smart uint32_t rsvd7; /* w8 */ 2638ed957684SJames Smart uint32_t rsvd8; /* w9 */ 2639ed957684SJames Smart 2640ed957684SJames Smart struct hbq_mask hbqMasks[6]; 2641ed957684SJames Smart 2642ed957684SJames Smart 2643ed957684SJames Smart union { 2644ed957684SJames Smart uint32_t allprofiles[12]; 2645ed957684SJames Smart 2646ed957684SJames Smart struct { 2647ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2648ed957684SJames Smart uint32_t seqlenoff :16; 2649ed957684SJames Smart uint32_t maxlen :16; 2650ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2651ed957684SJames Smart uint32_t maxlen :16; 2652ed957684SJames Smart uint32_t seqlenoff :16; 2653ed957684SJames Smart #endif 2654ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2655ed957684SJames Smart uint32_t rsvd1 :28; 2656ed957684SJames Smart uint32_t seqlenbcnt :4; 2657ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2658ed957684SJames Smart uint32_t seqlenbcnt :4; 2659ed957684SJames Smart uint32_t rsvd1 :28; 2660ed957684SJames Smart #endif 2661ed957684SJames Smart uint32_t rsvd[10]; 2662ed957684SJames Smart } profile2; 2663ed957684SJames Smart 2664ed957684SJames Smart struct { 2665ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2666ed957684SJames Smart uint32_t seqlenoff :16; 2667ed957684SJames Smart uint32_t maxlen :16; 2668ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2669ed957684SJames Smart uint32_t maxlen :16; 2670ed957684SJames Smart uint32_t seqlenoff :16; 2671ed957684SJames Smart #endif 2672ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2673ed957684SJames Smart uint32_t cmdcodeoff :28; 2674ed957684SJames Smart uint32_t rsvd1 :12; 2675ed957684SJames Smart uint32_t seqlenbcnt :4; 2676ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2677ed957684SJames Smart uint32_t seqlenbcnt :4; 2678ed957684SJames Smart uint32_t rsvd1 :12; 2679ed957684SJames Smart uint32_t cmdcodeoff :28; 2680ed957684SJames Smart #endif 2681ed957684SJames Smart uint32_t cmdmatch[8]; 2682ed957684SJames Smart 2683ed957684SJames Smart uint32_t rsvd[2]; 2684ed957684SJames Smart } profile3; 2685ed957684SJames Smart 2686ed957684SJames Smart struct { 2687ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2688ed957684SJames Smart uint32_t seqlenoff :16; 2689ed957684SJames Smart uint32_t maxlen :16; 2690ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2691ed957684SJames Smart uint32_t maxlen :16; 2692ed957684SJames Smart uint32_t seqlenoff :16; 2693ed957684SJames Smart #endif 2694ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2695ed957684SJames Smart uint32_t cmdcodeoff :28; 2696ed957684SJames Smart uint32_t rsvd1 :12; 2697ed957684SJames Smart uint32_t seqlenbcnt :4; 2698ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2699ed957684SJames Smart uint32_t seqlenbcnt :4; 2700ed957684SJames Smart uint32_t rsvd1 :12; 2701ed957684SJames Smart uint32_t cmdcodeoff :28; 2702ed957684SJames Smart #endif 2703ed957684SJames Smart uint32_t cmdmatch[8]; 2704ed957684SJames Smart 2705ed957684SJames Smart uint32_t rsvd[2]; 2706ed957684SJames Smart } profile5; 2707ed957684SJames Smart 2708ed957684SJames Smart } profiles; 2709ed957684SJames Smart 2710ed957684SJames Smart }; 2711ed957684SJames Smart 2712ed957684SJames Smart 2713dea3101eS 27142e0fef85SJames Smart /* Structure for MB Command CONFIG_PORT (0x88) */ 2715dea3101eS typedef struct { 2716ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2717ed957684SJames Smart uint32_t cBE : 1; 2718ed957684SJames Smart uint32_t cET : 1; 2719ed957684SJames Smart uint32_t cHpcb : 1; 2720ed957684SJames Smart uint32_t cMA : 1; 2721ed957684SJames Smart uint32_t sli_mode : 4; 2722ed957684SJames Smart uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2723ed957684SJames Smart * config block */ 2724ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2725ed957684SJames Smart uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2726ed957684SJames Smart * config block */ 2727ed957684SJames Smart uint32_t sli_mode : 4; 2728ed957684SJames Smart uint32_t cMA : 1; 2729ed957684SJames Smart uint32_t cHpcb : 1; 2730ed957684SJames Smart uint32_t cET : 1; 2731ed957684SJames Smart uint32_t cBE : 1; 2732ed957684SJames Smart #endif 2733ed957684SJames Smart 2734dea3101eS uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2735dea3101eS uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 273697207482SJames Smart uint32_t hbainit[5]; 273797207482SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 273897207482SJames Smart uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 273997207482SJames Smart uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 274097207482SJames Smart #else /* __LITTLE_ENDIAN */ 274197207482SJames Smart uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 274297207482SJames Smart uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 274397207482SJames Smart #endif 2744ed957684SJames Smart 2745ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2746da0436e9SJames Smart uint32_t rsvd1 : 19; /* Reserved */ 2747da0436e9SJames Smart uint32_t cdss : 1; /* Configure Data Security SLI */ 2748da0436e9SJames Smart uint32_t rsvd2 : 3; /* Reserved */ 274981301a9bSJames Smart uint32_t cbg : 1; /* Configure BlockGuard */ 2750ed957684SJames Smart uint32_t cmv : 1; /* Configure Max VPIs */ 2751ed957684SJames Smart uint32_t ccrp : 1; /* Config Command Ring Polling */ 2752ed957684SJames Smart uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2753ed957684SJames Smart uint32_t chbs : 1; /* Cofigure Host Backing store */ 2754ed957684SJames Smart uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2755ed957684SJames Smart uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2756ed957684SJames Smart uint32_t cmx : 1; /* Configure Max XRIs */ 2757ed957684SJames Smart uint32_t cmr : 1; /* Configure Max RPIs */ 2758ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2759ed957684SJames Smart uint32_t cmr : 1; /* Configure Max RPIs */ 2760ed957684SJames Smart uint32_t cmx : 1; /* Configure Max XRIs */ 2761ed957684SJames Smart uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2762ed957684SJames Smart uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2763ed957684SJames Smart uint32_t chbs : 1; /* Cofigure Host Backing store */ 2764ed957684SJames Smart uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2765ed957684SJames Smart uint32_t ccrp : 1; /* Config Command Ring Polling */ 2766ed957684SJames Smart uint32_t cmv : 1; /* Configure Max VPIs */ 276781301a9bSJames Smart uint32_t cbg : 1; /* Configure BlockGuard */ 2768da0436e9SJames Smart uint32_t rsvd2 : 3; /* Reserved */ 2769da0436e9SJames Smart uint32_t cdss : 1; /* Configure Data Security SLI */ 2770da0436e9SJames Smart uint32_t rsvd1 : 19; /* Reserved */ 2771ed957684SJames Smart #endif 2772ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2773da0436e9SJames Smart uint32_t rsvd3 : 19; /* Reserved */ 2774da0436e9SJames Smart uint32_t gdss : 1; /* Configure Data Security SLI */ 2775da0436e9SJames Smart uint32_t rsvd4 : 3; /* Reserved */ 277681301a9bSJames Smart uint32_t gbg : 1; /* Grant BlockGuard */ 2777ed957684SJames Smart uint32_t gmv : 1; /* Grant Max VPIs */ 2778ed957684SJames Smart uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2779ed957684SJames Smart uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2780ed957684SJames Smart uint32_t ghbs : 1; /* Grant Host Backing Store */ 2781ed957684SJames Smart uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2782ed957684SJames Smart uint32_t gerbm : 1; /* Grant ERBM Request */ 2783ed957684SJames Smart uint32_t gmx : 1; /* Grant Max XRIs */ 2784ed957684SJames Smart uint32_t gmr : 1; /* Grant Max RPIs */ 2785ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2786ed957684SJames Smart uint32_t gmr : 1; /* Grant Max RPIs */ 2787ed957684SJames Smart uint32_t gmx : 1; /* Grant Max XRIs */ 2788ed957684SJames Smart uint32_t gerbm : 1; /* Grant ERBM Request */ 2789ed957684SJames Smart uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2790ed957684SJames Smart uint32_t ghbs : 1; /* Grant Host Backing Store */ 2791ed957684SJames Smart uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2792ed957684SJames Smart uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2793ed957684SJames Smart uint32_t gmv : 1; /* Grant Max VPIs */ 279481301a9bSJames Smart uint32_t gbg : 1; /* Grant BlockGuard */ 2795da0436e9SJames Smart uint32_t rsvd4 : 3; /* Reserved */ 2796da0436e9SJames Smart uint32_t gdss : 1; /* Configure Data Security SLI */ 2797da0436e9SJames Smart uint32_t rsvd3 : 19; /* Reserved */ 2798ed957684SJames Smart #endif 2799ed957684SJames Smart 2800ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2801ed957684SJames Smart uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2802ed957684SJames Smart uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2803ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2804ed957684SJames Smart uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2805ed957684SJames Smart uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2806ed957684SJames Smart #endif 2807ed957684SJames Smart 2808ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2809ed957684SJames Smart uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2810da0436e9SJames Smart uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2811ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2812da0436e9SJames Smart uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2813ed957684SJames Smart uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2814ed957684SJames Smart #endif 2815ed957684SJames Smart 2816da0436e9SJames Smart uint32_t rsvd6; /* Reserved */ 2817ed957684SJames Smart 2818ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2819da0436e9SJames Smart uint32_t rsvd7 : 16; /* Reserved */ 2820ed957684SJames Smart uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2821ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2822ed957684SJames Smart uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2823da0436e9SJames Smart uint32_t rsvd7 : 16; /* Reserved */ 2824ed957684SJames Smart #endif 2825ed957684SJames Smart 2826dea3101eS } CONFIG_PORT_VAR; 2827dea3101eS 28289399627fSJames Smart /* Structure for MB Command CONFIG_MSI (0x30) */ 28299399627fSJames Smart struct config_msi_var { 28309399627fSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 28319399627fSJames Smart uint32_t dfltMsgNum:8; /* Default message number */ 28329399627fSJames Smart uint32_t rsvd1:11; /* Reserved */ 28339399627fSJames Smart uint32_t NID:5; /* Number of secondary attention IDs */ 28349399627fSJames Smart uint32_t rsvd2:5; /* Reserved */ 28359399627fSJames Smart uint32_t dfltPresent:1; /* Default message number present */ 28369399627fSJames Smart uint32_t addFlag:1; /* Add association flag */ 28379399627fSJames Smart uint32_t reportFlag:1; /* Report association flag */ 28389399627fSJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 28399399627fSJames Smart uint32_t reportFlag:1; /* Report association flag */ 28409399627fSJames Smart uint32_t addFlag:1; /* Add association flag */ 28419399627fSJames Smart uint32_t dfltPresent:1; /* Default message number present */ 28429399627fSJames Smart uint32_t rsvd2:5; /* Reserved */ 28439399627fSJames Smart uint32_t NID:5; /* Number of secondary attention IDs */ 28449399627fSJames Smart uint32_t rsvd1:11; /* Reserved */ 28459399627fSJames Smart uint32_t dfltMsgNum:8; /* Default message number */ 28469399627fSJames Smart #endif 28479399627fSJames Smart uint32_t attentionConditions[2]; 28489399627fSJames Smart uint8_t attentionId[16]; 28499399627fSJames Smart uint8_t messageNumberByHA[64]; 28509399627fSJames Smart uint8_t messageNumberByID[16]; 28519399627fSJames Smart uint32_t autoClearHA[2]; 28529399627fSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 28539399627fSJames Smart uint32_t rsvd3:16; 28549399627fSJames Smart uint32_t autoClearID:16; 28559399627fSJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 28569399627fSJames Smart uint32_t autoClearID:16; 28579399627fSJames Smart uint32_t rsvd3:16; 28589399627fSJames Smart #endif 28599399627fSJames Smart uint32_t rsvd4; 28609399627fSJames Smart }; 28619399627fSJames Smart 2862dea3101eS /* SLI-2 Port Control Block */ 2863dea3101eS 2864dea3101eS /* SLIM POINTER */ 2865dea3101eS #define SLIMOFF 0x30 /* WORD */ 2866dea3101eS 2867dea3101eS typedef struct _SLI2_RDSC { 2868dea3101eS uint32_t cmdEntries; 2869dea3101eS uint32_t cmdAddrLow; 2870dea3101eS uint32_t cmdAddrHigh; 2871dea3101eS 2872dea3101eS uint32_t rspEntries; 2873dea3101eS uint32_t rspAddrLow; 2874dea3101eS uint32_t rspAddrHigh; 2875dea3101eS } SLI2_RDSC; 2876dea3101eS 2877dea3101eS typedef struct _PCB { 2878dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2879dea3101eS uint32_t type:8; 2880dea3101eS #define TYPE_NATIVE_SLI2 0x01; 2881dea3101eS uint32_t feature:8; 2882dea3101eS #define FEATURE_INITIAL_SLI2 0x01; 2883dea3101eS uint32_t rsvd:12; 2884dea3101eS uint32_t maxRing:4; 2885dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2886dea3101eS uint32_t maxRing:4; 2887dea3101eS uint32_t rsvd:12; 2888dea3101eS uint32_t feature:8; 2889dea3101eS #define FEATURE_INITIAL_SLI2 0x01; 2890dea3101eS uint32_t type:8; 2891dea3101eS #define TYPE_NATIVE_SLI2 0x01; 2892dea3101eS #endif 2893dea3101eS 2894dea3101eS uint32_t mailBoxSize; 2895dea3101eS uint32_t mbAddrLow; 2896dea3101eS uint32_t mbAddrHigh; 2897dea3101eS 2898dea3101eS uint32_t hgpAddrLow; 2899dea3101eS uint32_t hgpAddrHigh; 2900dea3101eS 2901dea3101eS uint32_t pgpAddrLow; 2902dea3101eS uint32_t pgpAddrHigh; 2903dea3101eS SLI2_RDSC rdsc[MAX_RINGS]; 2904dea3101eS } PCB_t; 2905dea3101eS 2906dea3101eS /* NEW_FEATURE */ 2907dea3101eS typedef struct { 2908dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2909dea3101eS uint32_t rsvd0:27; 2910dea3101eS uint32_t discardFarp:1; 2911dea3101eS uint32_t IPEnable:1; 2912dea3101eS uint32_t nodeName:1; 2913dea3101eS uint32_t portName:1; 2914dea3101eS uint32_t filterEnable:1; 2915dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2916dea3101eS uint32_t filterEnable:1; 2917dea3101eS uint32_t portName:1; 2918dea3101eS uint32_t nodeName:1; 2919dea3101eS uint32_t IPEnable:1; 2920dea3101eS uint32_t discardFarp:1; 2921dea3101eS uint32_t rsvd:27; 2922dea3101eS #endif 2923dea3101eS 2924dea3101eS uint8_t portname[8]; /* Used to be struct lpfc_name */ 2925dea3101eS uint8_t nodename[8]; 2926dea3101eS uint32_t rsvd1; 2927dea3101eS uint32_t rsvd2; 2928dea3101eS uint32_t rsvd3; 2929dea3101eS uint32_t IPAddress; 2930dea3101eS } CONFIG_FARP_VAR; 2931dea3101eS 293257127f15SJames Smart /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 293357127f15SJames Smart 293457127f15SJames Smart typedef struct { 293557127f15SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 293657127f15SJames Smart uint32_t rsvd:30; 293757127f15SJames Smart uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 293857127f15SJames Smart #else /* __LITTLE_ENDIAN */ 293957127f15SJames Smart uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 294057127f15SJames Smart uint32_t rsvd:30; 294157127f15SJames Smart #endif 294257127f15SJames Smart } ASYNCEVT_ENABLE_VAR; 294357127f15SJames Smart 2944dea3101eS /* Union of all Mailbox Command types */ 2945dea3101eS #define MAILBOX_CMD_WSIZE 32 2946dea3101eS #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 2947dea3101eS 2948dea3101eS typedef union { 2949ed957684SJames Smart uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 2950ed957684SJames Smart * feature/max ring number 2951ed957684SJames Smart */ 2952dea3101eS LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 2953dea3101eS READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 2954dea3101eS WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 2955dea3101eS BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 2956dea3101eS INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 2957dea3101eS DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 2958dea3101eS CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 2959dea3101eS PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 2960dea3101eS CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 2961dea3101eS RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 2962dea3101eS READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 2963dea3101eS READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 2964dea3101eS READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 2965dea3101eS READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 2966dea3101eS READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 2967dea3101eS READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 2968dea3101eS READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 2969dea3101eS READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 2970dea3101eS REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 2971dea3101eS UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 2972dea3101eS READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 2973dea3101eS CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 2974dea3101eS DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 2975dea3101eS UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 2976ed957684SJames Smart CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 2977ed957684SJames Smart * NEW_FEATURE 2978ed957684SJames Smart */ 2979ed957684SJames Smart struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 2980d7c255b2SJames Smart struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 2981dea3101eS CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 298292d7f7b0SJames Smart REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 298392d7f7b0SJames Smart UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 298457127f15SJames Smart ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 29859399627fSJames Smart struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 2986dea3101eS } MAILVARIANTS; 2987dea3101eS 2988dea3101eS /* 2989dea3101eS * SLI-2 specific structures 2990dea3101eS */ 2991dea3101eS 29924cc2da1dSJames.Smart@Emulex.Com struct lpfc_hgp { 29934cc2da1dSJames.Smart@Emulex.Com __le32 cmdPutInx; 29944cc2da1dSJames.Smart@Emulex.Com __le32 rspGetInx; 29954cc2da1dSJames.Smart@Emulex.Com }; 2996dea3101eS 29974cc2da1dSJames.Smart@Emulex.Com struct lpfc_pgp { 29984cc2da1dSJames.Smart@Emulex.Com __le32 cmdGetInx; 29994cc2da1dSJames.Smart@Emulex.Com __le32 rspPutInx; 30004cc2da1dSJames.Smart@Emulex.Com }; 3001dea3101eS 3002ed957684SJames Smart struct sli2_desc { 3003dea3101eS uint32_t unused1[16]; 3004ed957684SJames Smart struct lpfc_hgp host[MAX_RINGS]; 30054cc2da1dSJames.Smart@Emulex.Com struct lpfc_pgp port[MAX_RINGS]; 3006ed957684SJames Smart }; 3007ed957684SJames Smart 3008ed957684SJames Smart struct sli3_desc { 3009ed957684SJames Smart struct lpfc_hgp host[MAX_RINGS]; 3010ed957684SJames Smart uint32_t reserved[8]; 3011ed957684SJames Smart uint32_t hbq_put[16]; 3012ed957684SJames Smart }; 3013ed957684SJames Smart 3014ed957684SJames Smart struct sli3_pgp { 3015ed957684SJames Smart struct lpfc_pgp port[MAX_RINGS]; 3016ed957684SJames Smart uint32_t hbq_get[16]; 3017ed957684SJames Smart }; 3018dea3101eS 301934b02dcdSJames Smart struct sli3_inb_pgp { 302034b02dcdSJames Smart uint32_t ha_copy; 302134b02dcdSJames Smart uint32_t counter; 302234b02dcdSJames Smart struct lpfc_pgp port[MAX_RINGS]; 302334b02dcdSJames Smart uint32_t hbq_get[16]; 302434b02dcdSJames Smart }; 302534b02dcdSJames Smart 302634b02dcdSJames Smart union sli_var { 3027ed957684SJames Smart struct sli2_desc s2; 3028ed957684SJames Smart struct sli3_desc s3; 3029ed957684SJames Smart struct sli3_pgp s3_pgp; 303034b02dcdSJames Smart struct sli3_inb_pgp s3_inb_pgp; 303134b02dcdSJames Smart }; 3032dea3101eS 3033dea3101eS typedef struct { 3034dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3035dea3101eS uint16_t mbxStatus; 3036dea3101eS uint8_t mbxCommand; 3037dea3101eS uint8_t mbxReserved:6; 3038dea3101eS uint8_t mbxHc:1; 3039dea3101eS uint8_t mbxOwner:1; /* Low order bit first word */ 3040dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3041dea3101eS uint8_t mbxOwner:1; /* Low order bit first word */ 3042dea3101eS uint8_t mbxHc:1; 3043dea3101eS uint8_t mbxReserved:6; 3044dea3101eS uint8_t mbxCommand; 3045dea3101eS uint16_t mbxStatus; 3046dea3101eS #endif 3047dea3101eS 3048dea3101eS MAILVARIANTS un; 304934b02dcdSJames Smart union sli_var us; 3050dea3101eS } MAILBOX_t; 3051dea3101eS 3052dea3101eS /* 3053dea3101eS * Begin Structure Definitions for IOCB Commands 3054dea3101eS */ 3055dea3101eS 3056dea3101eS typedef struct { 3057dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3058dea3101eS uint8_t statAction; 3059dea3101eS uint8_t statRsn; 3060dea3101eS uint8_t statBaExp; 3061dea3101eS uint8_t statLocalError; 3062dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3063dea3101eS uint8_t statLocalError; 3064dea3101eS uint8_t statBaExp; 3065dea3101eS uint8_t statRsn; 3066dea3101eS uint8_t statAction; 3067dea3101eS #endif 3068dea3101eS /* statRsn P/F_RJT reason codes */ 3069dea3101eS #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3070dea3101eS #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3071dea3101eS #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3072dea3101eS #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3073dea3101eS #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3074dea3101eS #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3075dea3101eS #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3076dea3101eS #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3077dea3101eS #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3078dea3101eS #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3079dea3101eS #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3080dea3101eS #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3081dea3101eS #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3082dea3101eS #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3083dea3101eS #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3084dea3101eS #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3085dea3101eS #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3086dea3101eS #define RJT_PROT_ERR 0x12 /* Protocol error */ 3087dea3101eS #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3088dea3101eS #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3089dea3101eS #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3090dea3101eS #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3091dea3101eS #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3092dea3101eS #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3093dea3101eS #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3094dea3101eS #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3095dea3101eS 3096dea3101eS #define IOERR_SUCCESS 0x00 /* statLocalError */ 3097dea3101eS #define IOERR_MISSING_CONTINUE 0x01 3098dea3101eS #define IOERR_SEQUENCE_TIMEOUT 0x02 3099dea3101eS #define IOERR_INTERNAL_ERROR 0x03 3100dea3101eS #define IOERR_INVALID_RPI 0x04 3101dea3101eS #define IOERR_NO_XRI 0x05 3102dea3101eS #define IOERR_ILLEGAL_COMMAND 0x06 3103dea3101eS #define IOERR_XCHG_DROPPED 0x07 3104dea3101eS #define IOERR_ILLEGAL_FIELD 0x08 3105dea3101eS #define IOERR_BAD_CONTINUE 0x09 3106dea3101eS #define IOERR_TOO_MANY_BUFFERS 0x0A 3107dea3101eS #define IOERR_RCV_BUFFER_WAITING 0x0B 3108dea3101eS #define IOERR_NO_CONNECTION 0x0C 3109dea3101eS #define IOERR_TX_DMA_FAILED 0x0D 3110dea3101eS #define IOERR_RX_DMA_FAILED 0x0E 3111dea3101eS #define IOERR_ILLEGAL_FRAME 0x0F 3112dea3101eS #define IOERR_EXTRA_DATA 0x10 3113dea3101eS #define IOERR_NO_RESOURCES 0x11 3114dea3101eS #define IOERR_RESERVED 0x12 3115dea3101eS #define IOERR_ILLEGAL_LENGTH 0x13 3116dea3101eS #define IOERR_UNSUPPORTED_FEATURE 0x14 3117dea3101eS #define IOERR_ABORT_IN_PROGRESS 0x15 3118dea3101eS #define IOERR_ABORT_REQUESTED 0x16 3119dea3101eS #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3120dea3101eS #define IOERR_LOOP_OPEN_FAILURE 0x18 3121dea3101eS #define IOERR_RING_RESET 0x19 3122dea3101eS #define IOERR_LINK_DOWN 0x1A 3123dea3101eS #define IOERR_CORRUPTED_DATA 0x1B 3124dea3101eS #define IOERR_CORRUPTED_RPI 0x1C 3125dea3101eS #define IOERR_OUT_OF_ORDER_DATA 0x1D 3126dea3101eS #define IOERR_OUT_OF_ORDER_ACK 0x1E 3127dea3101eS #define IOERR_DUP_FRAME 0x1F 3128dea3101eS #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3129dea3101eS #define IOERR_BAD_HOST_ADDRESS 0x21 3130dea3101eS #define IOERR_RCV_HDRBUF_WAITING 0x22 3131dea3101eS #define IOERR_MISSING_HDR_BUFFER 0x23 3132dea3101eS #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3133dea3101eS #define IOERR_ABORTMULT_REQUESTED 0x25 3134dea3101eS #define IOERR_BUFFER_SHORTAGE 0x28 3135dea3101eS #define IOERR_DEFAULT 0x29 3136dea3101eS #define IOERR_CNT 0x2A 3137dea3101eS 3138dea3101eS #define IOERR_DRVR_MASK 0x100 3139dea3101eS #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3140dea3101eS #define IOERR_SLI_BRESET 0x102 3141dea3101eS #define IOERR_SLI_ABORTED 0x103 3142dea3101eS } PARM_ERR; 3143dea3101eS 3144dea3101eS typedef union { 3145dea3101eS struct { 3146dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3147dea3101eS uint8_t Rctl; /* R_CTL field */ 3148dea3101eS uint8_t Type; /* TYPE field */ 3149dea3101eS uint8_t Dfctl; /* DF_CTL field */ 3150dea3101eS uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3151dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3152dea3101eS uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3153dea3101eS uint8_t Dfctl; /* DF_CTL field */ 3154dea3101eS uint8_t Type; /* TYPE field */ 3155dea3101eS uint8_t Rctl; /* R_CTL field */ 3156dea3101eS #endif 3157dea3101eS 3158dea3101eS #define BC 0x02 /* Broadcast Received - Fctl */ 3159dea3101eS #define SI 0x04 /* Sequence Initiative */ 3160dea3101eS #define LA 0x08 /* Ignore Link Attention state */ 3161dea3101eS #define LS 0x80 /* Last Sequence */ 3162dea3101eS } hcsw; 3163dea3101eS uint32_t reserved; 3164dea3101eS } WORD5; 3165dea3101eS 3166dea3101eS /* IOCB Command template for a generic response */ 3167dea3101eS typedef struct { 3168dea3101eS uint32_t reserved[4]; 3169dea3101eS PARM_ERR perr; 3170dea3101eS } GENERIC_RSP; 3171dea3101eS 3172dea3101eS /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3173dea3101eS typedef struct { 3174dea3101eS struct ulp_bde xrsqbde[2]; 3175dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3176dea3101eS WORD5 w5; /* Header control/status word */ 3177dea3101eS } XR_SEQ_FIELDS; 3178dea3101eS 3179dea3101eS /* IOCB Command template for ELS_REQUEST */ 3180dea3101eS typedef struct { 3181dea3101eS struct ulp_bde elsReq; 3182dea3101eS struct ulp_bde elsRsp; 3183dea3101eS 3184dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3185dea3101eS uint32_t word4Rsvd:7; 3186dea3101eS uint32_t fl:1; 3187dea3101eS uint32_t myID:24; 3188dea3101eS uint32_t word5Rsvd:8; 3189dea3101eS uint32_t remoteID:24; 3190dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3191dea3101eS uint32_t myID:24; 3192dea3101eS uint32_t fl:1; 3193dea3101eS uint32_t word4Rsvd:7; 3194dea3101eS uint32_t remoteID:24; 3195dea3101eS uint32_t word5Rsvd:8; 3196dea3101eS #endif 3197dea3101eS } ELS_REQUEST; 3198dea3101eS 3199dea3101eS /* IOCB Command template for RCV_ELS_REQ */ 3200dea3101eS typedef struct { 3201dea3101eS struct ulp_bde elsReq[2]; 3202dea3101eS uint32_t parmRo; 3203dea3101eS 3204dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3205dea3101eS uint32_t word5Rsvd:8; 3206dea3101eS uint32_t remoteID:24; 3207dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3208dea3101eS uint32_t remoteID:24; 3209dea3101eS uint32_t word5Rsvd:8; 3210dea3101eS #endif 3211dea3101eS } RCV_ELS_REQ; 3212dea3101eS 3213dea3101eS /* IOCB Command template for ABORT / CLOSE_XRI */ 3214dea3101eS typedef struct { 3215dea3101eS uint32_t rsvd[3]; 3216dea3101eS uint32_t abortType; 3217dea3101eS #define ABORT_TYPE_ABTX 0x00000000 3218dea3101eS #define ABORT_TYPE_ABTS 0x00000001 3219dea3101eS uint32_t parm; 3220dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3221dea3101eS uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3222dea3101eS uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3223dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3224dea3101eS uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3225dea3101eS uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3226dea3101eS #endif 3227dea3101eS } AC_XRI; 3228dea3101eS 3229dea3101eS /* IOCB Command template for ABORT_MXRI64 */ 3230dea3101eS typedef struct { 3231dea3101eS uint32_t rsvd[3]; 3232dea3101eS uint32_t abortType; 3233dea3101eS uint32_t parm; 3234dea3101eS uint32_t iotag32; 3235dea3101eS } A_MXRI64; 3236dea3101eS 3237dea3101eS /* IOCB Command template for GET_RPI */ 3238dea3101eS typedef struct { 3239dea3101eS uint32_t rsvd[4]; 3240dea3101eS uint32_t parmRo; 3241dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3242dea3101eS uint32_t word5Rsvd:8; 3243dea3101eS uint32_t remoteID:24; 3244dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3245dea3101eS uint32_t remoteID:24; 3246dea3101eS uint32_t word5Rsvd:8; 3247dea3101eS #endif 3248dea3101eS } GET_RPI; 3249dea3101eS 3250dea3101eS /* IOCB Command template for all FCP Initiator commands */ 3251dea3101eS typedef struct { 3252dea3101eS struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3253dea3101eS struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3254dea3101eS uint32_t fcpi_parm; 3255dea3101eS uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3256dea3101eS } FCPI_FIELDS; 3257dea3101eS 3258dea3101eS /* IOCB Command template for all FCP Target commands */ 3259dea3101eS typedef struct { 3260dea3101eS struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3261dea3101eS uint32_t fcpt_Offset; 3262dea3101eS uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3263dea3101eS } FCPT_FIELDS; 3264dea3101eS 3265dea3101eS /* SLI-2 IOCB structure definitions */ 3266dea3101eS 3267dea3101eS /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3268dea3101eS typedef struct { 3269dea3101eS ULP_BDL bdl; 3270dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3271dea3101eS WORD5 w5; /* Header control/status word */ 3272dea3101eS } XMT_SEQ_FIELDS64; 3273dea3101eS 3274dea3101eS /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3275dea3101eS typedef struct { 3276dea3101eS struct ulp_bde64 rcvBde; 3277dea3101eS uint32_t rsvd1; 3278dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3279dea3101eS WORD5 w5; /* Header control/status word */ 3280dea3101eS } RCV_SEQ_FIELDS64; 3281dea3101eS 3282dea3101eS /* IOCB Command template for ELS_REQUEST64 */ 3283dea3101eS typedef struct { 3284dea3101eS ULP_BDL bdl; 3285dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3286dea3101eS uint32_t word4Rsvd:7; 3287dea3101eS uint32_t fl:1; 3288dea3101eS uint32_t myID:24; 3289dea3101eS uint32_t word5Rsvd:8; 3290dea3101eS uint32_t remoteID:24; 3291dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3292dea3101eS uint32_t myID:24; 3293dea3101eS uint32_t fl:1; 3294dea3101eS uint32_t word4Rsvd:7; 3295dea3101eS uint32_t remoteID:24; 3296dea3101eS uint32_t word5Rsvd:8; 3297dea3101eS #endif 3298dea3101eS } ELS_REQUEST64; 3299dea3101eS 3300dea3101eS /* IOCB Command template for GEN_REQUEST64 */ 3301dea3101eS typedef struct { 3302dea3101eS ULP_BDL bdl; 3303dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3304dea3101eS WORD5 w5; /* Header control/status word */ 3305dea3101eS } GEN_REQUEST64; 3306dea3101eS 3307dea3101eS /* IOCB Command template for RCV_ELS_REQ64 */ 3308dea3101eS typedef struct { 3309dea3101eS struct ulp_bde64 elsReq; 3310dea3101eS uint32_t rcvd1; 3311dea3101eS uint32_t parmRo; 3312dea3101eS 3313dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3314dea3101eS uint32_t word5Rsvd:8; 3315dea3101eS uint32_t remoteID:24; 3316dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3317dea3101eS uint32_t remoteID:24; 3318dea3101eS uint32_t word5Rsvd:8; 3319dea3101eS #endif 3320dea3101eS } RCV_ELS_REQ64; 3321dea3101eS 33229c2face6SJames Smart /* IOCB Command template for RCV_SEQ64 */ 33239c2face6SJames Smart struct rcv_seq64 { 33249c2face6SJames Smart struct ulp_bde64 elsReq; 33259c2face6SJames Smart uint32_t hbq_1; 33269c2face6SJames Smart uint32_t parmRo; 33279c2face6SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 33289c2face6SJames Smart uint32_t rctl:8; 33299c2face6SJames Smart uint32_t type:8; 33309c2face6SJames Smart uint32_t dfctl:8; 33319c2face6SJames Smart uint32_t ls:1; 33329c2face6SJames Smart uint32_t fs:1; 33339c2face6SJames Smart uint32_t rsvd2:3; 33349c2face6SJames Smart uint32_t si:1; 33359c2face6SJames Smart uint32_t bc:1; 33369c2face6SJames Smart uint32_t rsvd3:1; 33379c2face6SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 33389c2face6SJames Smart uint32_t rsvd3:1; 33399c2face6SJames Smart uint32_t bc:1; 33409c2face6SJames Smart uint32_t si:1; 33419c2face6SJames Smart uint32_t rsvd2:3; 33429c2face6SJames Smart uint32_t fs:1; 33439c2face6SJames Smart uint32_t ls:1; 33449c2face6SJames Smart uint32_t dfctl:8; 33459c2face6SJames Smart uint32_t type:8; 33469c2face6SJames Smart uint32_t rctl:8; 33479c2face6SJames Smart #endif 33489c2face6SJames Smart }; 33499c2face6SJames Smart 3350dea3101eS /* IOCB Command template for all 64 bit FCP Initiator commands */ 3351dea3101eS typedef struct { 3352dea3101eS ULP_BDL bdl; 3353dea3101eS uint32_t fcpi_parm; 3354dea3101eS uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3355dea3101eS } FCPI_FIELDS64; 3356dea3101eS 3357dea3101eS /* IOCB Command template for all 64 bit FCP Target commands */ 3358dea3101eS typedef struct { 3359dea3101eS ULP_BDL bdl; 3360dea3101eS uint32_t fcpt_Offset; 3361dea3101eS uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3362dea3101eS } FCPT_FIELDS64; 3363dea3101eS 336457127f15SJames Smart /* IOCB Command template for Async Status iocb commands */ 336557127f15SJames Smart typedef struct { 336657127f15SJames Smart uint32_t rsvd[4]; 336757127f15SJames Smart uint32_t param; 336857127f15SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 336957127f15SJames Smart uint16_t evt_code; /* High order bits word 5 */ 337057127f15SJames Smart uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 337157127f15SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 337257127f15SJames Smart uint16_t sub_ctxt_tag; /* High order bits word 5 */ 337357127f15SJames Smart uint16_t evt_code; /* Low order bits word 5 */ 337457127f15SJames Smart #endif 337557127f15SJames Smart } ASYNCSTAT_FIELDS; 337657127f15SJames Smart #define ASYNC_TEMP_WARN 0x100 337757127f15SJames Smart #define ASYNC_TEMP_SAFE 0x101 337857127f15SJames Smart 3379ed957684SJames Smart /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3380ed957684SJames Smart or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3381ed957684SJames Smart 3382ed957684SJames Smart struct rcv_sli3 { 3383ed957684SJames Smart uint32_t word8Rsvd; 3384ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 3385ed957684SJames Smart uint16_t vpi; 3386ed957684SJames Smart uint16_t word9Rsvd; 3387ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 3388ed957684SJames Smart uint16_t word9Rsvd; 3389ed957684SJames Smart uint16_t vpi; 3390ed957684SJames Smart #endif 3391ed957684SJames Smart uint32_t word10Rsvd; 3392ed957684SJames Smart uint32_t acc_len; /* accumulated length */ 3393ed957684SJames Smart struct ulp_bde64 bde2; 3394ed957684SJames Smart }; 3395ed957684SJames Smart 339676bb24efSJames Smart /* Structure used for a single HBQ entry */ 339776bb24efSJames Smart struct lpfc_hbq_entry { 339876bb24efSJames Smart struct ulp_bde64 bde; 339976bb24efSJames Smart uint32_t buffer_tag; 340076bb24efSJames Smart }; 340192d7f7b0SJames Smart 340276bb24efSJames Smart /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 340376bb24efSJames Smart typedef struct { 340476bb24efSJames Smart struct lpfc_hbq_entry buff; 340576bb24efSJames Smart uint32_t rsvd; 340676bb24efSJames Smart uint32_t rsvd1; 340776bb24efSJames Smart } QUE_XRI64_CX_FIELDS; 340876bb24efSJames Smart 340976bb24efSJames Smart struct que_xri64cx_ext_fields { 341076bb24efSJames Smart uint32_t iotag64_low; 341176bb24efSJames Smart uint32_t iotag64_high; 341276bb24efSJames Smart uint32_t ebde_count; 341376bb24efSJames Smart uint32_t rsvd; 341476bb24efSJames Smart struct lpfc_hbq_entry buff[5]; 341576bb24efSJames Smart }; 341692d7f7b0SJames Smart 341781301a9bSJames Smart struct sli3_bg_fields { 341881301a9bSJames Smart uint32_t filler[6]; /* word 8-13 in IOCB */ 341981301a9bSJames Smart uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 342081301a9bSJames Smart /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 342181301a9bSJames Smart #define BGS_BIDIR_BG_PROF_MASK 0xff000000 342281301a9bSJames Smart #define BGS_BIDIR_BG_PROF_SHIFT 24 342381301a9bSJames Smart #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 342481301a9bSJames Smart #define BGS_BIDIR_ERR_COND_SHIFT 16 342581301a9bSJames Smart #define BGS_BG_PROFILE_MASK 0x0000ff00 342681301a9bSJames Smart #define BGS_BG_PROFILE_SHIFT 8 342781301a9bSJames Smart #define BGS_INVALID_PROF_MASK 0x00000020 342881301a9bSJames Smart #define BGS_INVALID_PROF_SHIFT 5 342981301a9bSJames Smart #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 343081301a9bSJames Smart #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 343181301a9bSJames Smart #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 343281301a9bSJames Smart #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 343381301a9bSJames Smart #define BGS_REFTAG_ERR_MASK 0x00000004 343481301a9bSJames Smart #define BGS_REFTAG_ERR_SHIFT 2 343581301a9bSJames Smart #define BGS_APPTAG_ERR_MASK 0x00000002 343681301a9bSJames Smart #define BGS_APPTAG_ERR_SHIFT 1 343781301a9bSJames Smart #define BGS_GUARD_ERR_MASK 0x00000001 343881301a9bSJames Smart #define BGS_GUARD_ERR_SHIFT 0 343981301a9bSJames Smart uint32_t bgstat; /* word 15 - BlockGuard Status */ 344081301a9bSJames Smart }; 344181301a9bSJames Smart 344281301a9bSJames Smart static inline uint32_t 344381301a9bSJames Smart lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 344481301a9bSJames Smart { 344581301a9bSJames Smart return (le32_to_cpu(bgstat) & BGS_BIDIR_BG_PROF_MASK) >> 344681301a9bSJames Smart BGS_BIDIR_BG_PROF_SHIFT; 344781301a9bSJames Smart } 344881301a9bSJames Smart 344981301a9bSJames Smart static inline uint32_t 345081301a9bSJames Smart lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 345181301a9bSJames Smart { 345281301a9bSJames Smart return (le32_to_cpu(bgstat) & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 345381301a9bSJames Smart BGS_BIDIR_ERR_COND_SHIFT; 345481301a9bSJames Smart } 345581301a9bSJames Smart 345681301a9bSJames Smart static inline uint32_t 345781301a9bSJames Smart lpfc_bgs_get_bg_prof(uint32_t bgstat) 345881301a9bSJames Smart { 345981301a9bSJames Smart return (le32_to_cpu(bgstat) & BGS_BG_PROFILE_MASK) >> 346081301a9bSJames Smart BGS_BG_PROFILE_SHIFT; 346181301a9bSJames Smart } 346281301a9bSJames Smart 346381301a9bSJames Smart static inline uint32_t 346481301a9bSJames Smart lpfc_bgs_get_invalid_prof(uint32_t bgstat) 346581301a9bSJames Smart { 346681301a9bSJames Smart return (le32_to_cpu(bgstat) & BGS_INVALID_PROF_MASK) >> 346781301a9bSJames Smart BGS_INVALID_PROF_SHIFT; 346881301a9bSJames Smart } 346981301a9bSJames Smart 347081301a9bSJames Smart static inline uint32_t 347181301a9bSJames Smart lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 347281301a9bSJames Smart { 347381301a9bSJames Smart return (le32_to_cpu(bgstat) & BGS_UNINIT_DIF_BLOCK_MASK) >> 347481301a9bSJames Smart BGS_UNINIT_DIF_BLOCK_SHIFT; 347581301a9bSJames Smart } 347681301a9bSJames Smart 347781301a9bSJames Smart static inline uint32_t 347881301a9bSJames Smart lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 347981301a9bSJames Smart { 348081301a9bSJames Smart return (le32_to_cpu(bgstat) & BGS_HI_WATER_MARK_PRESENT_MASK) >> 348181301a9bSJames Smart BGS_HI_WATER_MARK_PRESENT_SHIFT; 348281301a9bSJames Smart } 348381301a9bSJames Smart 348481301a9bSJames Smart static inline uint32_t 348581301a9bSJames Smart lpfc_bgs_get_reftag_err(uint32_t bgstat) 348681301a9bSJames Smart { 348781301a9bSJames Smart return (le32_to_cpu(bgstat) & BGS_REFTAG_ERR_MASK) >> 348881301a9bSJames Smart BGS_REFTAG_ERR_SHIFT; 348981301a9bSJames Smart } 349081301a9bSJames Smart 349181301a9bSJames Smart static inline uint32_t 349281301a9bSJames Smart lpfc_bgs_get_apptag_err(uint32_t bgstat) 349381301a9bSJames Smart { 349481301a9bSJames Smart return (le32_to_cpu(bgstat) & BGS_APPTAG_ERR_MASK) >> 349581301a9bSJames Smart BGS_APPTAG_ERR_SHIFT; 349681301a9bSJames Smart } 349781301a9bSJames Smart 349881301a9bSJames Smart static inline uint32_t 349981301a9bSJames Smart lpfc_bgs_get_guard_err(uint32_t bgstat) 350081301a9bSJames Smart { 350181301a9bSJames Smart return (le32_to_cpu(bgstat) & BGS_GUARD_ERR_MASK) >> 350281301a9bSJames Smart BGS_GUARD_ERR_SHIFT; 350381301a9bSJames Smart } 350481301a9bSJames Smart 350534b02dcdSJames Smart #define LPFC_EXT_DATA_BDE_COUNT 3 350634b02dcdSJames Smart struct fcp_irw_ext { 350734b02dcdSJames Smart uint32_t io_tag64_low; 350834b02dcdSJames Smart uint32_t io_tag64_high; 350934b02dcdSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 351034b02dcdSJames Smart uint8_t reserved1; 351134b02dcdSJames Smart uint8_t reserved2; 351234b02dcdSJames Smart uint8_t reserved3; 351334b02dcdSJames Smart uint8_t ebde_count; 351434b02dcdSJames Smart #else /* __LITTLE_ENDIAN */ 351534b02dcdSJames Smart uint8_t ebde_count; 351634b02dcdSJames Smart uint8_t reserved3; 351734b02dcdSJames Smart uint8_t reserved2; 351834b02dcdSJames Smart uint8_t reserved1; 351934b02dcdSJames Smart #endif 352034b02dcdSJames Smart uint32_t reserved4; 352134b02dcdSJames Smart struct ulp_bde64 rbde; /* response bde */ 352234b02dcdSJames Smart struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 352334b02dcdSJames Smart uint8_t icd[32]; /* immediate command data (32 bytes) */ 352434b02dcdSJames Smart }; 352534b02dcdSJames Smart 3526dea3101eS typedef struct _IOCB { /* IOCB structure */ 3527dea3101eS union { 3528dea3101eS GENERIC_RSP grsp; /* Generic response */ 3529dea3101eS XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 3530dea3101eS struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 3531dea3101eS RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 3532dea3101eS AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 3533dea3101eS A_MXRI64 amxri; /* abort multiple xri command overlay */ 3534dea3101eS GET_RPI getrpi; /* GET_RPI template */ 3535dea3101eS FCPI_FIELDS fcpi; /* FCP Initiator template */ 3536dea3101eS FCPT_FIELDS fcpt; /* FCP target template */ 3537dea3101eS 3538dea3101eS /* SLI-2 structures */ 3539dea3101eS 3540dea3101eS struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 3541ed957684SJames Smart * bde_64s */ 3542dea3101eS ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 3543dea3101eS GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 3544dea3101eS RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 3545dea3101eS XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 3546dea3101eS FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 3547dea3101eS FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 354857127f15SJames Smart ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 354976bb24efSJames Smart QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 35509c2face6SJames Smart struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 3551dea3101eS 3552dea3101eS uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 3553dea3101eS } un; 3554dea3101eS union { 3555dea3101eS struct { 3556dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3557dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3558dea3101eS uint16_t ulpIoTag; /* Low order bits word 6 */ 3559dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3560dea3101eS uint16_t ulpIoTag; /* Low order bits word 6 */ 3561dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3562dea3101eS #endif 3563dea3101eS } t1; 3564dea3101eS struct { 3565dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3566dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3567dea3101eS uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3568dea3101eS uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3569dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3570dea3101eS uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3571dea3101eS uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3572dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3573dea3101eS #endif 3574dea3101eS } t2; 3575dea3101eS } un1; 3576dea3101eS #define ulpContext un1.t1.ulpContext 3577dea3101eS #define ulpIoTag un1.t1.ulpIoTag 3578dea3101eS #define ulpIoTag0 un1.t2.ulpIoTag0 3579dea3101eS 3580dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3581dea3101eS uint32_t ulpTimeout:8; 3582dea3101eS uint32_t ulpXS:1; 3583dea3101eS uint32_t ulpFCP2Rcvy:1; 3584dea3101eS uint32_t ulpPU:2; 3585dea3101eS uint32_t ulpIr:1; 3586dea3101eS uint32_t ulpClass:3; 3587dea3101eS uint32_t ulpCommand:8; 3588dea3101eS uint32_t ulpStatus:4; 3589dea3101eS uint32_t ulpBdeCount:2; 3590dea3101eS uint32_t ulpLe:1; 3591dea3101eS uint32_t ulpOwner:1; /* Low order bit word 7 */ 3592dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3593dea3101eS uint32_t ulpOwner:1; /* Low order bit word 7 */ 3594dea3101eS uint32_t ulpLe:1; 3595dea3101eS uint32_t ulpBdeCount:2; 3596dea3101eS uint32_t ulpStatus:4; 3597dea3101eS uint32_t ulpCommand:8; 3598dea3101eS uint32_t ulpClass:3; 3599dea3101eS uint32_t ulpIr:1; 3600dea3101eS uint32_t ulpPU:2; 3601dea3101eS uint32_t ulpFCP2Rcvy:1; 3602dea3101eS uint32_t ulpXS:1; 3603dea3101eS uint32_t ulpTimeout:8; 3604dea3101eS #endif 360592d7f7b0SJames Smart 3606ed957684SJames Smart union { 3607ed957684SJames Smart struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 360876bb24efSJames Smart 360976bb24efSJames Smart /* words 8-31 used for que_xri_cx iocb */ 361076bb24efSJames Smart struct que_xri64cx_ext_fields que_xri64cx_ext_words; 361134b02dcdSJames Smart struct fcp_irw_ext fcp_ext; 3612ed957684SJames Smart uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 361381301a9bSJames Smart 361481301a9bSJames Smart /* words 8-15 for BlockGuard */ 361581301a9bSJames Smart struct sli3_bg_fields sli3_bg; 3616ed957684SJames Smart } unsli3; 3617dea3101eS 3618ed957684SJames Smart #define ulpCt_h ulpXS 3619ed957684SJames Smart #define ulpCt_l ulpFCP2Rcvy 3620ed957684SJames Smart 3621ed957684SJames Smart #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 3622ed957684SJames Smart #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 3623dea3101eS #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 3624dea3101eS #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 3625dea3101eS #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 362692d7f7b0SJames Smart #define PARM_NPIV_DID 3 3627dea3101eS #define CLASS1 0 /* Class 1 */ 3628dea3101eS #define CLASS2 1 /* Class 2 */ 3629dea3101eS #define CLASS3 2 /* Class 3 */ 3630dea3101eS #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 3631dea3101eS 3632dea3101eS #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 3633dea3101eS #define IOSTAT_FCP_RSP_ERROR 0x1 3634dea3101eS #define IOSTAT_REMOTE_STOP 0x2 3635dea3101eS #define IOSTAT_LOCAL_REJECT 0x3 3636dea3101eS #define IOSTAT_NPORT_RJT 0x4 3637dea3101eS #define IOSTAT_FABRIC_RJT 0x5 3638dea3101eS #define IOSTAT_NPORT_BSY 0x6 3639dea3101eS #define IOSTAT_FABRIC_BSY 0x7 3640dea3101eS #define IOSTAT_INTERMED_RSP 0x8 3641dea3101eS #define IOSTAT_LS_RJT 0x9 3642dea3101eS #define IOSTAT_BA_RJT 0xA 3643dea3101eS #define IOSTAT_RSVD1 0xB 3644dea3101eS #define IOSTAT_RSVD2 0xC 3645dea3101eS #define IOSTAT_RSVD3 0xD 3646dea3101eS #define IOSTAT_RSVD4 0xE 364792d7f7b0SJames Smart #define IOSTAT_NEED_BUFFER 0xF 3648dea3101eS #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 3649dea3101eS #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 3650dea3101eS #define IOSTAT_CNT 0x11 3651dea3101eS 3652dea3101eS } IOCB_t; 3653dea3101eS 3654dea3101eS 3655dea3101eS #define SLI1_SLIM_SIZE (4 * 1024) 3656dea3101eS 3657dea3101eS /* Up to 498 IOCBs will fit into 16k 3658dea3101eS * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 3659dea3101eS */ 3660ed957684SJames Smart #define SLI2_SLIM_SIZE (64 * 1024) 3661dea3101eS 3662dea3101eS /* Maximum IOCBs that will fit in SLI2 slim */ 3663dea3101eS #define MAX_SLI2_IOCB 498 3664ed957684SJames Smart #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 3665ed957684SJames Smart (sizeof(MAILBOX_t) + sizeof(PCB_t))) 3666ed957684SJames Smart 3667ed957684SJames Smart /* HBQ entries are 4 words each = 4k */ 3668ed957684SJames Smart #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 3669ed957684SJames Smart lpfc_sli_hbq_count()) 3670dea3101eS 3671dea3101eS struct lpfc_sli2_slim { 3672dea3101eS MAILBOX_t mbx; 3673dea3101eS PCB_t pcb; 3674ed957684SJames Smart IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 3675dea3101eS }; 3676dea3101eS 36772e0fef85SJames Smart /* 36782e0fef85SJames Smart * This function checks PCI device to allow special handling for LC HBAs. 36792e0fef85SJames Smart * 36802e0fef85SJames Smart * Parameters: 36812e0fef85SJames Smart * device : struct pci_dev 's device field 36822e0fef85SJames Smart * 36832e0fef85SJames Smart * return 1 => TRUE 36842e0fef85SJames Smart * 0 => FALSE 36852e0fef85SJames Smart */ 3686dea3101eS static inline int 3687dea3101eS lpfc_is_LC_HBA(unsigned short device) 3688dea3101eS { 3689dea3101eS if ((device == PCI_DEVICE_ID_TFLY) || 3690dea3101eS (device == PCI_DEVICE_ID_PFLY) || 3691dea3101eS (device == PCI_DEVICE_ID_LP101) || 3692dea3101eS (device == PCI_DEVICE_ID_BMID) || 3693dea3101eS (device == PCI_DEVICE_ID_BSMB) || 3694dea3101eS (device == PCI_DEVICE_ID_ZMID) || 3695dea3101eS (device == PCI_DEVICE_ID_ZSMB) || 369609372820SJames Smart (device == PCI_DEVICE_ID_SAT_MID) || 369709372820SJames Smart (device == PCI_DEVICE_ID_SAT_SMB) || 3698dea3101eS (device == PCI_DEVICE_ID_RFLY)) 3699dea3101eS return 1; 3700dea3101eS else 3701dea3101eS return 0; 3702dea3101eS } 3703858c9f6cSJames Smart 3704858c9f6cSJames Smart /* 3705858c9f6cSJames Smart * Determine if an IOCB failed because of a link event or firmware reset. 3706858c9f6cSJames Smart */ 3707858c9f6cSJames Smart 3708858c9f6cSJames Smart static inline int 3709858c9f6cSJames Smart lpfc_error_lost_link(IOCB_t *iocbp) 3710858c9f6cSJames Smart { 3711858c9f6cSJames Smart return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 3712858c9f6cSJames Smart (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 3713858c9f6cSJames Smart iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 3714858c9f6cSJames Smart iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 3715858c9f6cSJames Smart } 371684774a4dSJames Smart 371784774a4dSJames Smart #define MENLO_TRANSPORT_TYPE 0xfe 371884774a4dSJames Smart #define MENLO_CONTEXT 0 371984774a4dSJames Smart #define MENLO_PU 3 372084774a4dSJames Smart #define MENLO_TIMEOUT 30 372184774a4dSJames Smart #define SETVAR_MLOMNT 0x103107 372284774a4dSJames Smart #define SETVAR_MLORST 0x103007 3723da0436e9SJames Smart 3724da0436e9SJames Smart #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 3725