1dea3101eS /******************************************************************* 2dea3101eS * This file is part of the Emulex Linux Device Driver for * 3c44ce173SJames.Smart@Emulex.Com * Fibre Channel Host Bus Adapters. * 44fede78fSJames Smart * Copyright (C) 2004-2010 Emulex. All rights reserved. * 5c44ce173SJames.Smart@Emulex.Com * EMULEX and SLI are trademarks of Emulex. * 6dea3101eS * www.emulex.com * 7dea3101eS * * 8dea3101eS * This program is free software; you can redistribute it and/or * 9c44ce173SJames.Smart@Emulex.Com * modify it under the terms of version 2 of the GNU General * 10c44ce173SJames.Smart@Emulex.Com * Public License as published by the Free Software Foundation. * 11c44ce173SJames.Smart@Emulex.Com * This program is distributed in the hope that it will be useful. * 12c44ce173SJames.Smart@Emulex.Com * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13c44ce173SJames.Smart@Emulex.Com * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14c44ce173SJames.Smart@Emulex.Com * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15c44ce173SJames.Smart@Emulex.Com * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16c44ce173SJames.Smart@Emulex.Com * TO BE LEGALLY INVALID. See the GNU General Public License for * 17c44ce173SJames.Smart@Emulex.Com * more details, a copy of which can be found in the file COPYING * 18c44ce173SJames.Smart@Emulex.Com * included with this package. * 19dea3101eS *******************************************************************/ 20dea3101eS 21dea3101eS #define FDMI_DID 0xfffffaU 22dea3101eS #define NameServer_DID 0xfffffcU 23dea3101eS #define SCR_DID 0xfffffdU 24dea3101eS #define Fabric_DID 0xfffffeU 25dea3101eS #define Bcast_DID 0xffffffU 26dea3101eS #define Mask_DID 0xffffffU 27dea3101eS #define CT_DID_MASK 0xffff00U 28dea3101eS #define Fabric_DID_MASK 0xfff000U 29dea3101eS #define WELL_KNOWN_DID_MASK 0xfffff0U 30dea3101eS 31dea3101eS #define PT2PT_LocalID 1 32dea3101eS #define PT2PT_RemoteID 2 33dea3101eS 34dea3101eS #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35dea3101eS #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36dea3101eS #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37dea3101eS #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38dea3101eS 39dea3101eS #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40dea3101eS 0 */ 41dea3101eS 42dea3101eS #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43dea3101eS 44dea3101eS #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45a4bc3379SJames Smart #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46dea3101eS #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47dea3101eS #define LPFC_FCP_NEXT_RING 3 48dea3101eS 49dea3101eS #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50dea3101eS #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51a4bc3379SJames Smart #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 52a4bc3379SJames Smart #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 53dea3101eS #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54dea3101eS #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55dea3101eS #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56dea3101eS #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57dea3101eS #define SLI2_IOCB_CMD_R3_ENTRIES 0 58dea3101eS #define SLI2_IOCB_RSP_R3_ENTRIES 0 59dea3101eS #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60dea3101eS #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61dea3101eS 62ed957684SJames Smart #define SLI2_IOCB_CMD_SIZE 32 63ed957684SJames Smart #define SLI2_IOCB_RSP_SIZE 32 64ed957684SJames Smart #define SLI3_IOCB_CMD_SIZE 128 65ed957684SJames Smart #define SLI3_IOCB_RSP_SIZE 64 66ed957684SJames Smart 6792d7f7b0SJames Smart 68ddcc50f0SJames Smart /* vendor ID used in SCSI netlink calls */ 69ddcc50f0SJames Smart #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 70ddcc50f0SJames Smart 71dea3101eS /* Common Transport structures and definitions */ 72dea3101eS 73dea3101eS union CtRevisionId { 74dea3101eS /* Structure is in Big Endian format */ 75dea3101eS struct { 76dea3101eS uint32_t Revision:8; 77dea3101eS uint32_t InId:24; 78dea3101eS } bits; 79dea3101eS uint32_t word; 80dea3101eS }; 81dea3101eS 82dea3101eS union CtCommandResponse { 83dea3101eS /* Structure is in Big Endian format */ 84dea3101eS struct { 85dea3101eS uint32_t CmdRsp:16; 86dea3101eS uint32_t Size:16; 87dea3101eS } bits; 88dea3101eS uint32_t word; 89dea3101eS }; 90dea3101eS 9192d7f7b0SJames Smart #define FC4_FEATURE_INIT 0x2 9292d7f7b0SJames Smart #define FC4_FEATURE_TARGET 0x1 9392d7f7b0SJames Smart 94dea3101eS struct lpfc_sli_ct_request { 95dea3101eS /* Structure is in Big Endian format */ 96dea3101eS union CtRevisionId RevisionId; 97dea3101eS uint8_t FsType; 98dea3101eS uint8_t FsSubType; 99dea3101eS uint8_t Options; 100dea3101eS uint8_t Rsrvd1; 101dea3101eS union CtCommandResponse CommandResponse; 102dea3101eS uint8_t Rsrvd2; 103dea3101eS uint8_t ReasonCode; 104dea3101eS uint8_t Explanation; 105dea3101eS uint8_t VendorUnique; 106dea3101eS 107dea3101eS union { 108dea3101eS uint32_t PortID; 109dea3101eS struct gid { 110dea3101eS uint8_t PortType; /* for GID_PT requests */ 111dea3101eS uint8_t DomainScope; 112dea3101eS uint8_t AreaScope; 113dea3101eS uint8_t Fc4Type; /* for GID_FT requests */ 114dea3101eS } gid; 115dea3101eS struct rft { 116dea3101eS uint32_t PortId; /* For RFT_ID requests */ 117dea3101eS 118dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 119dea3101eS uint32_t rsvd0:16; 120dea3101eS uint32_t rsvd1:7; 121dea3101eS uint32_t fcpReg:1; /* Type 8 */ 122dea3101eS uint32_t rsvd2:2; 123dea3101eS uint32_t ipReg:1; /* Type 5 */ 124dea3101eS uint32_t rsvd3:5; 125dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 126dea3101eS uint32_t rsvd0:16; 127dea3101eS uint32_t fcpReg:1; /* Type 8 */ 128dea3101eS uint32_t rsvd1:7; 129dea3101eS uint32_t rsvd3:5; 130dea3101eS uint32_t ipReg:1; /* Type 5 */ 131dea3101eS uint32_t rsvd2:2; 132dea3101eS #endif 133dea3101eS 134dea3101eS uint32_t rsvd[7]; 135dea3101eS } rft; 136dea3101eS struct rnn { 137dea3101eS uint32_t PortId; /* For RNN_ID requests */ 138dea3101eS uint8_t wwnn[8]; 139dea3101eS } rnn; 140dea3101eS struct rsnn { /* For RSNN_ID requests */ 141dea3101eS uint8_t wwnn[8]; 142dea3101eS uint8_t len; 143dea3101eS uint8_t symbname[255]; 144dea3101eS } rsnn; 1457ee5d43eSJames Smart struct da_id { /* For DA_ID requests */ 1467ee5d43eSJames Smart uint32_t port_id; 1477ee5d43eSJames Smart } da_id; 14892d7f7b0SJames Smart struct rspn { /* For RSPN_ID requests */ 14992d7f7b0SJames Smart uint32_t PortId; 15092d7f7b0SJames Smart uint8_t len; 15192d7f7b0SJames Smart uint8_t symbname[255]; 15292d7f7b0SJames Smart } rspn; 15392d7f7b0SJames Smart struct gff { 15492d7f7b0SJames Smart uint32_t PortId; 15592d7f7b0SJames Smart } gff; 15692d7f7b0SJames Smart struct gff_acc { 15792d7f7b0SJames Smart uint8_t fbits[128]; 15892d7f7b0SJames Smart } gff_acc; 15951ef4c26SJames Smart #define FCP_TYPE_FEATURE_OFFSET 7 16092d7f7b0SJames Smart struct rff { 16192d7f7b0SJames Smart uint32_t PortId; 16292d7f7b0SJames Smart uint8_t reserved[2]; 16392d7f7b0SJames Smart uint8_t fbits; 16492d7f7b0SJames Smart uint8_t type_code; /* type=8 for FCP */ 16592d7f7b0SJames Smart } rff; 166dea3101eS } un; 167dea3101eS }; 168dea3101eS 169dea3101eS #define SLI_CT_REVISION 1 17092d7f7b0SJames Smart #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17192d7f7b0SJames Smart sizeof(struct gid)) 17292d7f7b0SJames Smart #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17392d7f7b0SJames Smart sizeof(struct gff)) 17492d7f7b0SJames Smart #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17592d7f7b0SJames Smart sizeof(struct rft)) 17692d7f7b0SJames Smart #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17792d7f7b0SJames Smart sizeof(struct rff)) 17892d7f7b0SJames Smart #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 17992d7f7b0SJames Smart sizeof(struct rnn)) 18092d7f7b0SJames Smart #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 18192d7f7b0SJames Smart sizeof(struct rsnn)) 1827ee5d43eSJames Smart #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 1837ee5d43eSJames Smart sizeof(struct da_id)) 18492d7f7b0SJames Smart #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 18592d7f7b0SJames Smart sizeof(struct rspn)) 186dea3101eS 187dea3101eS /* 188dea3101eS * FsType Definitions 189dea3101eS */ 190dea3101eS 191dea3101eS #define SLI_CT_MANAGEMENT_SERVICE 0xFA 192dea3101eS #define SLI_CT_TIME_SERVICE 0xFB 193dea3101eS #define SLI_CT_DIRECTORY_SERVICE 0xFC 194dea3101eS #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 195dea3101eS 196dea3101eS /* 197dea3101eS * Directory Service Subtypes 198dea3101eS */ 199dea3101eS 200dea3101eS #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 201dea3101eS 202dea3101eS /* 203dea3101eS * Response Codes 204dea3101eS */ 205dea3101eS 206dea3101eS #define SLI_CT_RESPONSE_FS_RJT 0x8001 207dea3101eS #define SLI_CT_RESPONSE_FS_ACC 0x8002 208dea3101eS 209dea3101eS /* 210dea3101eS * Reason Codes 211dea3101eS */ 212dea3101eS 213dea3101eS #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 214dea3101eS #define SLI_CT_INVALID_COMMAND 0x01 215dea3101eS #define SLI_CT_INVALID_VERSION 0x02 216dea3101eS #define SLI_CT_LOGICAL_ERROR 0x03 217dea3101eS #define SLI_CT_INVALID_IU_SIZE 0x04 218dea3101eS #define SLI_CT_LOGICAL_BUSY 0x05 219dea3101eS #define SLI_CT_PROTOCOL_ERROR 0x07 220dea3101eS #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 221dea3101eS #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 222dea3101eS #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 223dea3101eS #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 224dea3101eS #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 225dea3101eS #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 226dea3101eS #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 227dea3101eS #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 228dea3101eS #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 229dea3101eS #define SLI_CT_VENDOR_UNIQUE 0xff 230dea3101eS 231dea3101eS /* 232dea3101eS * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 233dea3101eS */ 234dea3101eS 235dea3101eS #define SLI_CT_NO_PORT_ID 0x01 236dea3101eS #define SLI_CT_NO_PORT_NAME 0x02 237dea3101eS #define SLI_CT_NO_NODE_NAME 0x03 238dea3101eS #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 239dea3101eS #define SLI_CT_NO_IP_ADDRESS 0x05 240dea3101eS #define SLI_CT_NO_IPA 0x06 241dea3101eS #define SLI_CT_NO_FC4_TYPES 0x07 242dea3101eS #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 243dea3101eS #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 244dea3101eS #define SLI_CT_NO_PORT_TYPE 0x0A 245dea3101eS #define SLI_CT_ACCESS_DENIED 0x10 246dea3101eS #define SLI_CT_INVALID_PORT_ID 0x11 247dea3101eS #define SLI_CT_DATABASE_EMPTY 0x12 248dea3101eS 249dea3101eS /* 250dea3101eS * Name Server Command Codes 251dea3101eS */ 252dea3101eS 253dea3101eS #define SLI_CTNS_GA_NXT 0x0100 254dea3101eS #define SLI_CTNS_GPN_ID 0x0112 255dea3101eS #define SLI_CTNS_GNN_ID 0x0113 256dea3101eS #define SLI_CTNS_GCS_ID 0x0114 257dea3101eS #define SLI_CTNS_GFT_ID 0x0117 258dea3101eS #define SLI_CTNS_GSPN_ID 0x0118 259dea3101eS #define SLI_CTNS_GPT_ID 0x011A 26092d7f7b0SJames Smart #define SLI_CTNS_GFF_ID 0x011F 261dea3101eS #define SLI_CTNS_GID_PN 0x0121 262dea3101eS #define SLI_CTNS_GID_NN 0x0131 263dea3101eS #define SLI_CTNS_GIP_NN 0x0135 264dea3101eS #define SLI_CTNS_GIPA_NN 0x0136 265dea3101eS #define SLI_CTNS_GSNN_NN 0x0139 266dea3101eS #define SLI_CTNS_GNN_IP 0x0153 267dea3101eS #define SLI_CTNS_GIPA_IP 0x0156 268dea3101eS #define SLI_CTNS_GID_FT 0x0171 269dea3101eS #define SLI_CTNS_GID_PT 0x01A1 270dea3101eS #define SLI_CTNS_RPN_ID 0x0212 271dea3101eS #define SLI_CTNS_RNN_ID 0x0213 272dea3101eS #define SLI_CTNS_RCS_ID 0x0214 273dea3101eS #define SLI_CTNS_RFT_ID 0x0217 274dea3101eS #define SLI_CTNS_RSPN_ID 0x0218 275dea3101eS #define SLI_CTNS_RPT_ID 0x021A 27692d7f7b0SJames Smart #define SLI_CTNS_RFF_ID 0x021F 277dea3101eS #define SLI_CTNS_RIP_NN 0x0235 278dea3101eS #define SLI_CTNS_RIPA_NN 0x0236 279dea3101eS #define SLI_CTNS_RSNN_NN 0x0239 280dea3101eS #define SLI_CTNS_DA_ID 0x0300 281dea3101eS 282dea3101eS /* 283dea3101eS * Port Types 284dea3101eS */ 285dea3101eS 286dea3101eS #define SLI_CTPT_N_PORT 0x01 287dea3101eS #define SLI_CTPT_NL_PORT 0x02 288dea3101eS #define SLI_CTPT_FNL_PORT 0x03 289dea3101eS #define SLI_CTPT_IP 0x04 290dea3101eS #define SLI_CTPT_FCP 0x08 291dea3101eS #define SLI_CTPT_NX_PORT 0x7F 292dea3101eS #define SLI_CTPT_F_PORT 0x81 293dea3101eS #define SLI_CTPT_FL_PORT 0x82 294dea3101eS #define SLI_CTPT_E_PORT 0x84 295dea3101eS 296dea3101eS #define SLI_CT_LAST_ENTRY 0x80000000 297dea3101eS 298dea3101eS /* Fibre Channel Service Parameter definitions */ 299dea3101eS 300dea3101eS #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 301dea3101eS #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 302dea3101eS #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 303dea3101eS #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 304dea3101eS 305dea3101eS #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 306dea3101eS #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 307dea3101eS #define FC_PH3 0x20 /* FC-PH-3 version */ 308dea3101eS 309dea3101eS #define FF_FRAME_SIZE 2048 310dea3101eS 311dea3101eS struct lpfc_name { 312f631b4beSAndrew Vasquez union { 313f631b4beSAndrew Vasquez struct { 314dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 315dea3101eS uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 3161de933f3SJames.Smart@Emulex.Com uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 3171de933f3SJames.Smart@Emulex.Com 8:11 of IEEE ext */ 318dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3191de933f3SJames.Smart@Emulex.Com uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 3201de933f3SJames.Smart@Emulex.Com 8:11 of IEEE ext */ 321dea3101eS uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 322dea3101eS #endif 323dea3101eS 324dea3101eS #define NAME_IEEE 0x1 /* IEEE name - nameType */ 325dea3101eS #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 326dea3101eS #define NAME_FC_TYPE 0x3 /* FC native name type */ 327dea3101eS #define NAME_IP_TYPE 0x4 /* IP address */ 328dea3101eS #define NAME_CCITT_TYPE 0xC 329dea3101eS #define NAME_CCITT_GR_TYPE 0xE 3301de933f3SJames.Smart@Emulex.Com uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 3311de933f3SJames.Smart@Emulex.Com extended Lsb */ 332dea3101eS uint8_t IEEE[6]; /* FC IEEE address */ 33368ce1eb5SAndrew Morton } s; 334f631b4beSAndrew Vasquez uint8_t wwn[8]; 33568ce1eb5SAndrew Morton } u; 336f631b4beSAndrew Vasquez }; 337dea3101eS 338dea3101eS struct csp { 339dea3101eS uint8_t fcphHigh; /* FC Word 0, byte 0 */ 340dea3101eS uint8_t fcphLow; 341dea3101eS uint8_t bbCreditMsb; 342dea3101eS uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 343dea3101eS 34492494144SJames Smart /* 34592494144SJames Smart * Word 1 Bit 31 in common service parameter is overloaded. 34692494144SJames Smart * Word 1 Bit 31 in FLOGI request is multiple NPort request 34792494144SJames Smart * Word 1 Bit 31 in FLOGI response is clean address bit 34892494144SJames Smart */ 34992494144SJames Smart #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 350dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 35192d7f7b0SJames Smart uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 35292d7f7b0SJames Smart uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 35392d7f7b0SJames Smart uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 354dea3101eS uint16_t fPort:1; /* FC Word 1, bit 28 */ 355dea3101eS uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 356dea3101eS uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 357dea3101eS uint16_t multicast:1; /* FC Word 1, bit 25 */ 358dea3101eS uint16_t broadcast:1; /* FC Word 1, bit 24 */ 359dea3101eS 360dea3101eS uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 361dea3101eS uint16_t simplex:1; /* FC Word 1, bit 22 */ 362dea3101eS uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 363dea3101eS uint16_t dhd:1; /* FC Word 1, bit 18 */ 364dea3101eS uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 365dea3101eS uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 366dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 367dea3101eS uint16_t broadcast:1; /* FC Word 1, bit 24 */ 368dea3101eS uint16_t multicast:1; /* FC Word 1, bit 25 */ 369dea3101eS uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 370dea3101eS uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 371dea3101eS uint16_t fPort:1; /* FC Word 1, bit 28 */ 37292d7f7b0SJames Smart uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 373dea3101eS uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 37492d7f7b0SJames Smart uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 375dea3101eS 376dea3101eS uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 377dea3101eS uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 378dea3101eS uint16_t dhd:1; /* FC Word 1, bit 18 */ 379dea3101eS uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 380dea3101eS uint16_t simplex:1; /* FC Word 1, bit 22 */ 381dea3101eS uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 382dea3101eS #endif 383dea3101eS 384dea3101eS uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 385dea3101eS uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 386dea3101eS union { 387dea3101eS struct { 388dea3101eS uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 389dea3101eS 390dea3101eS uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 391dea3101eS uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 392dea3101eS 393dea3101eS uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 394dea3101eS } nPort; 395dea3101eS uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 396dea3101eS } w2; 397dea3101eS 398dea3101eS uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 399dea3101eS }; 400dea3101eS 401dea3101eS struct class_parms { 402dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 403dea3101eS uint8_t classValid:1; /* FC Word 0, bit 31 */ 404dea3101eS uint8_t intermix:1; /* FC Word 0, bit 30 */ 405dea3101eS uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 406dea3101eS uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 407dea3101eS uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 408dea3101eS uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 409dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 410dea3101eS uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 411dea3101eS uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 412dea3101eS uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 413dea3101eS uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 414dea3101eS uint8_t intermix:1; /* FC Word 0, bit 30 */ 415dea3101eS uint8_t classValid:1; /* FC Word 0, bit 31 */ 416dea3101eS 417dea3101eS #endif 418dea3101eS 419dea3101eS uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 420dea3101eS 421dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 422dea3101eS uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 423dea3101eS uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 424dea3101eS uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 425dea3101eS uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 426dea3101eS uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 427dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 428dea3101eS uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 429dea3101eS uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 430dea3101eS uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 431dea3101eS uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 432dea3101eS uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 433dea3101eS #endif 434dea3101eS 435dea3101eS uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 436dea3101eS 437dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 438dea3101eS uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 439dea3101eS uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 440dea3101eS uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 441dea3101eS uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 442dea3101eS uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 443dea3101eS uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 444dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 445dea3101eS uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 446dea3101eS uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 447dea3101eS uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 448dea3101eS uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 449dea3101eS uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 450dea3101eS uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 451dea3101eS #endif 452dea3101eS 453dea3101eS uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 454dea3101eS uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 455dea3101eS uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 456dea3101eS 457dea3101eS uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 458dea3101eS uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 459dea3101eS uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 460dea3101eS uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 461dea3101eS 462dea3101eS uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 463dea3101eS uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 464dea3101eS uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 465dea3101eS uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 466dea3101eS }; 467dea3101eS 468dea3101eS struct serv_parm { /* Structure is in Big Endian format */ 469dea3101eS struct csp cmn; 470dea3101eS struct lpfc_name portName; 471dea3101eS struct lpfc_name nodeName; 472dea3101eS struct class_parms cls1; 473dea3101eS struct class_parms cls2; 474dea3101eS struct class_parms cls3; 475dea3101eS struct class_parms cls4; 476dea3101eS uint8_t vendorVersion[16]; 477dea3101eS }; 478dea3101eS 479dea3101eS /* 480da0436e9SJames Smart * Virtual Fabric Tagging Header 481da0436e9SJames Smart */ 482da0436e9SJames Smart struct fc_vft_header { 483da0436e9SJames Smart uint32_t word0; 484da0436e9SJames Smart #define fc_vft_hdr_r_ctl_SHIFT 24 485da0436e9SJames Smart #define fc_vft_hdr_r_ctl_MASK 0xFF 486da0436e9SJames Smart #define fc_vft_hdr_r_ctl_WORD word0 487da0436e9SJames Smart #define fc_vft_hdr_ver_SHIFT 22 488da0436e9SJames Smart #define fc_vft_hdr_ver_MASK 0x3 489da0436e9SJames Smart #define fc_vft_hdr_ver_WORD word0 490da0436e9SJames Smart #define fc_vft_hdr_type_SHIFT 18 491da0436e9SJames Smart #define fc_vft_hdr_type_MASK 0xF 492da0436e9SJames Smart #define fc_vft_hdr_type_WORD word0 493da0436e9SJames Smart #define fc_vft_hdr_e_SHIFT 16 494da0436e9SJames Smart #define fc_vft_hdr_e_MASK 0x1 495da0436e9SJames Smart #define fc_vft_hdr_e_WORD word0 496da0436e9SJames Smart #define fc_vft_hdr_priority_SHIFT 13 497da0436e9SJames Smart #define fc_vft_hdr_priority_MASK 0x7 498da0436e9SJames Smart #define fc_vft_hdr_priority_WORD word0 499da0436e9SJames Smart #define fc_vft_hdr_vf_id_SHIFT 1 500da0436e9SJames Smart #define fc_vft_hdr_vf_id_MASK 0xFFF 501da0436e9SJames Smart #define fc_vft_hdr_vf_id_WORD word0 502da0436e9SJames Smart uint32_t word1; 503da0436e9SJames Smart #define fc_vft_hdr_hopct_SHIFT 24 504da0436e9SJames Smart #define fc_vft_hdr_hopct_MASK 0xFF 505da0436e9SJames Smart #define fc_vft_hdr_hopct_WORD word1 506da0436e9SJames Smart }; 507da0436e9SJames Smart 508da0436e9SJames Smart /* 509dea3101eS * Extended Link Service LS_COMMAND codes (Payload Word 0) 510dea3101eS */ 511dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 512dea3101eS #define ELS_CMD_MASK 0xffff0000 513dea3101eS #define ELS_RSP_MASK 0xff000000 514dea3101eS #define ELS_CMD_LS_RJT 0x01000000 515dea3101eS #define ELS_CMD_ACC 0x02000000 516dea3101eS #define ELS_CMD_PLOGI 0x03000000 517dea3101eS #define ELS_CMD_FLOGI 0x04000000 518dea3101eS #define ELS_CMD_LOGO 0x05000000 519dea3101eS #define ELS_CMD_ABTX 0x06000000 520dea3101eS #define ELS_CMD_RCS 0x07000000 521dea3101eS #define ELS_CMD_RES 0x08000000 522dea3101eS #define ELS_CMD_RSS 0x09000000 523dea3101eS #define ELS_CMD_RSI 0x0A000000 524dea3101eS #define ELS_CMD_ESTS 0x0B000000 525dea3101eS #define ELS_CMD_ESTC 0x0C000000 526dea3101eS #define ELS_CMD_ADVC 0x0D000000 527dea3101eS #define ELS_CMD_RTV 0x0E000000 528dea3101eS #define ELS_CMD_RLS 0x0F000000 529dea3101eS #define ELS_CMD_ECHO 0x10000000 530dea3101eS #define ELS_CMD_TEST 0x11000000 531dea3101eS #define ELS_CMD_RRQ 0x12000000 532dea3101eS #define ELS_CMD_PRLI 0x20100014 533dea3101eS #define ELS_CMD_PRLO 0x21100014 53482d9a2a2SJames Smart #define ELS_CMD_PRLO_ACC 0x02100014 535dea3101eS #define ELS_CMD_PDISC 0x50000000 536dea3101eS #define ELS_CMD_FDISC 0x51000000 537dea3101eS #define ELS_CMD_ADISC 0x52000000 538dea3101eS #define ELS_CMD_FARP 0x54000000 539dea3101eS #define ELS_CMD_FARPR 0x55000000 5407bb3b137SJamie Wellnitz #define ELS_CMD_RPS 0x56000000 5417bb3b137SJamie Wellnitz #define ELS_CMD_RPL 0x57000000 542dea3101eS #define ELS_CMD_FAN 0x60000000 543dea3101eS #define ELS_CMD_RSCN 0x61040000 544dea3101eS #define ELS_CMD_SCR 0x62000000 545dea3101eS #define ELS_CMD_RNID 0x78000000 5467bb3b137SJamie Wellnitz #define ELS_CMD_LIRR 0x7A000000 547dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 548dea3101eS #define ELS_CMD_MASK 0xffff 549dea3101eS #define ELS_RSP_MASK 0xff 550dea3101eS #define ELS_CMD_LS_RJT 0x01 551dea3101eS #define ELS_CMD_ACC 0x02 552dea3101eS #define ELS_CMD_PLOGI 0x03 553dea3101eS #define ELS_CMD_FLOGI 0x04 554dea3101eS #define ELS_CMD_LOGO 0x05 555dea3101eS #define ELS_CMD_ABTX 0x06 556dea3101eS #define ELS_CMD_RCS 0x07 557dea3101eS #define ELS_CMD_RES 0x08 558dea3101eS #define ELS_CMD_RSS 0x09 559dea3101eS #define ELS_CMD_RSI 0x0A 560dea3101eS #define ELS_CMD_ESTS 0x0B 561dea3101eS #define ELS_CMD_ESTC 0x0C 562dea3101eS #define ELS_CMD_ADVC 0x0D 563dea3101eS #define ELS_CMD_RTV 0x0E 564dea3101eS #define ELS_CMD_RLS 0x0F 565dea3101eS #define ELS_CMD_ECHO 0x10 566dea3101eS #define ELS_CMD_TEST 0x11 567dea3101eS #define ELS_CMD_RRQ 0x12 568dea3101eS #define ELS_CMD_PRLI 0x14001020 569dea3101eS #define ELS_CMD_PRLO 0x14001021 57082d9a2a2SJames Smart #define ELS_CMD_PRLO_ACC 0x14001002 571dea3101eS #define ELS_CMD_PDISC 0x50 572dea3101eS #define ELS_CMD_FDISC 0x51 573dea3101eS #define ELS_CMD_ADISC 0x52 574dea3101eS #define ELS_CMD_FARP 0x54 575dea3101eS #define ELS_CMD_FARPR 0x55 5767bb3b137SJamie Wellnitz #define ELS_CMD_RPS 0x56 5777bb3b137SJamie Wellnitz #define ELS_CMD_RPL 0x57 578dea3101eS #define ELS_CMD_FAN 0x60 579dea3101eS #define ELS_CMD_RSCN 0x0461 580dea3101eS #define ELS_CMD_SCR 0x62 581dea3101eS #define ELS_CMD_RNID 0x78 5827bb3b137SJamie Wellnitz #define ELS_CMD_LIRR 0x7A 583dea3101eS #endif 584dea3101eS 585dea3101eS /* 586dea3101eS * LS_RJT Payload Definition 587dea3101eS */ 588dea3101eS 589dea3101eS struct ls_rjt { /* Structure is in Big Endian format */ 590dea3101eS union { 591dea3101eS uint32_t lsRjtError; 592dea3101eS struct { 593dea3101eS uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 594dea3101eS 595dea3101eS uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 596dea3101eS /* LS_RJT reason codes */ 597dea3101eS #define LSRJT_INVALID_CMD 0x01 598dea3101eS #define LSRJT_LOGICAL_ERR 0x03 599dea3101eS #define LSRJT_LOGICAL_BSY 0x05 600dea3101eS #define LSRJT_PROTOCOL_ERR 0x07 601dea3101eS #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 602dea3101eS #define LSRJT_CMD_UNSUPPORTED 0x0B 603dea3101eS #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 604dea3101eS 605dea3101eS uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 606dea3101eS /* LS_RJT reason explanation */ 607dea3101eS #define LSEXP_NOTHING_MORE 0x00 608dea3101eS #define LSEXP_SPARM_OPTIONS 0x01 609dea3101eS #define LSEXP_SPARM_ICTL 0x03 610dea3101eS #define LSEXP_SPARM_RCTL 0x05 611dea3101eS #define LSEXP_SPARM_RCV_SIZE 0x07 612dea3101eS #define LSEXP_SPARM_CONCUR_SEQ 0x09 613dea3101eS #define LSEXP_SPARM_CREDIT 0x0B 614dea3101eS #define LSEXP_INVALID_PNAME 0x0D 615dea3101eS #define LSEXP_INVALID_NNAME 0x0E 616dea3101eS #define LSEXP_INVALID_CSP 0x0F 617dea3101eS #define LSEXP_INVALID_ASSOC_HDR 0x11 618dea3101eS #define LSEXP_ASSOC_HDR_REQ 0x13 619dea3101eS #define LSEXP_INVALID_O_SID 0x15 620dea3101eS #define LSEXP_INVALID_OX_RX 0x17 621dea3101eS #define LSEXP_CMD_IN_PROGRESS 0x19 6227f5f3d0dSJames Smart #define LSEXP_PORT_LOGIN_REQ 0x1E 623dea3101eS #define LSEXP_INVALID_NPORT_ID 0x1F 624dea3101eS #define LSEXP_INVALID_SEQ_ID 0x21 625dea3101eS #define LSEXP_INVALID_XCHG 0x23 626dea3101eS #define LSEXP_INACTIVE_XCHG 0x25 627dea3101eS #define LSEXP_RQ_REQUIRED 0x27 628dea3101eS #define LSEXP_OUT_OF_RESOURCE 0x29 629dea3101eS #define LSEXP_CANT_GIVE_DATA 0x2A 630dea3101eS #define LSEXP_REQ_UNSUPPORTED 0x2C 631dea3101eS uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 632dea3101eS } b; 633dea3101eS } un; 634dea3101eS }; 635dea3101eS 636dea3101eS /* 637dea3101eS * N_Port Login (FLOGO/PLOGO Request) Payload Definition 638dea3101eS */ 639dea3101eS 640dea3101eS typedef struct _LOGO { /* Structure is in Big Endian format */ 641dea3101eS union { 642dea3101eS uint32_t nPortId32; /* Access nPortId as a word */ 643dea3101eS struct { 644dea3101eS uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 645dea3101eS uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 646dea3101eS uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 647dea3101eS uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 648dea3101eS } b; 649dea3101eS } un; 650dea3101eS struct lpfc_name portName; /* N_port name field */ 651dea3101eS } LOGO; 652dea3101eS 653dea3101eS /* 654dea3101eS * FCP Login (PRLI Request / ACC) Payload Definition 655dea3101eS */ 656dea3101eS 657dea3101eS #define PRLX_PAGE_LEN 0x10 658dea3101eS #define TPRLO_PAGE_LEN 0x14 659dea3101eS 660dea3101eS typedef struct _PRLI { /* Structure is in Big Endian format */ 661dea3101eS uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 662dea3101eS 663dea3101eS #define PRLI_FCP_TYPE 0x08 664dea3101eS uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 665dea3101eS 666dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 667dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 668dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 669dea3101eS uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 670dea3101eS 671dea3101eS /* ACC = imagePairEstablished */ 672dea3101eS uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 673dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 674dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 675dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 676dea3101eS uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 677dea3101eS uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 678dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 679dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 680dea3101eS /* ACC = imagePairEstablished */ 681dea3101eS #endif 682dea3101eS 683dea3101eS #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 684dea3101eS #define PRLI_NO_RESOURCES 0x2 685dea3101eS #define PRLI_INIT_INCOMPLETE 0x3 686dea3101eS #define PRLI_NO_SUCH_PA 0x4 687dea3101eS #define PRLI_PREDEF_CONFIG 0x5 688dea3101eS #define PRLI_PARTIAL_SUCCESS 0x6 689dea3101eS #define PRLI_INVALID_PAGE_CNT 0x7 690dea3101eS uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 691dea3101eS 692dea3101eS uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 693dea3101eS 694dea3101eS uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 695dea3101eS 696dea3101eS uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 697dea3101eS uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 698dea3101eS 699dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 700dea3101eS uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 701dea3101eS uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 702dea3101eS uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 703dea3101eS uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 704dea3101eS uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 705dea3101eS uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 706dea3101eS uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 707dea3101eS uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 708dea3101eS uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 709dea3101eS uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 710dea3101eS uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 711dea3101eS uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 712dea3101eS uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 713dea3101eS uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 714dea3101eS uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 715dea3101eS uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 716dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 717dea3101eS uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 718dea3101eS uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 719dea3101eS uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 720dea3101eS uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 721dea3101eS uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 722dea3101eS uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 723dea3101eS uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 724dea3101eS uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 725dea3101eS uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 726dea3101eS uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 727dea3101eS uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 728dea3101eS uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 729dea3101eS uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 730dea3101eS uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 731dea3101eS uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 732dea3101eS uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 733dea3101eS #endif 734dea3101eS } PRLI; 735dea3101eS 736dea3101eS /* 737dea3101eS * FCP Logout (PRLO Request / ACC) Payload Definition 738dea3101eS */ 739dea3101eS 740dea3101eS typedef struct _PRLO { /* Structure is in Big Endian format */ 741dea3101eS uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 742dea3101eS 743dea3101eS #define PRLO_FCP_TYPE 0x08 744dea3101eS uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 745dea3101eS 746dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 747dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 748dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 749dea3101eS uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 750dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 751dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 752dea3101eS uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 753dea3101eS uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 754dea3101eS uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 755dea3101eS uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 756dea3101eS #endif 757dea3101eS 758dea3101eS #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 759dea3101eS #define PRLO_NO_SUCH_IMAGE 0x4 760dea3101eS #define PRLO_INVALID_PAGE_CNT 0x7 761dea3101eS 762dea3101eS uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 763dea3101eS 764dea3101eS uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 765dea3101eS 766dea3101eS uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 767dea3101eS 768dea3101eS uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 769dea3101eS } PRLO; 770dea3101eS 771dea3101eS typedef struct _ADISC { /* Structure is in Big Endian format */ 772dea3101eS uint32_t hardAL_PA; 773dea3101eS struct lpfc_name portName; 774dea3101eS struct lpfc_name nodeName; 775dea3101eS uint32_t DID; 776dea3101eS } ADISC; 777dea3101eS 778dea3101eS typedef struct _FARP { /* Structure is in Big Endian format */ 779dea3101eS uint32_t Mflags:8; 780dea3101eS uint32_t Odid:24; 781dea3101eS #define FARP_NO_ACTION 0 /* FARP information enclosed, no 782dea3101eS action */ 783dea3101eS #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 784dea3101eS #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 785dea3101eS #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 786dea3101eS #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 787dea3101eS supported */ 788dea3101eS #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 789dea3101eS supported */ 790dea3101eS uint32_t Rflags:8; 791dea3101eS uint32_t Rdid:24; 792dea3101eS #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 793dea3101eS #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 794dea3101eS struct lpfc_name OportName; 795dea3101eS struct lpfc_name OnodeName; 796dea3101eS struct lpfc_name RportName; 797dea3101eS struct lpfc_name RnodeName; 798dea3101eS uint8_t Oipaddr[16]; 799dea3101eS uint8_t Ripaddr[16]; 800dea3101eS } FARP; 801dea3101eS 802dea3101eS typedef struct _FAN { /* Structure is in Big Endian format */ 803dea3101eS uint32_t Fdid; 804dea3101eS struct lpfc_name FportName; 805dea3101eS struct lpfc_name FnodeName; 806dea3101eS } FAN; 807dea3101eS 808dea3101eS typedef struct _SCR { /* Structure is in Big Endian format */ 809dea3101eS uint8_t resvd1; 810dea3101eS uint8_t resvd2; 811dea3101eS uint8_t resvd3; 812dea3101eS uint8_t Function; 813dea3101eS #define SCR_FUNC_FABRIC 0x01 814dea3101eS #define SCR_FUNC_NPORT 0x02 815dea3101eS #define SCR_FUNC_FULL 0x03 816dea3101eS #define SCR_CLEAR 0xff 817dea3101eS } SCR; 818dea3101eS 819dea3101eS typedef struct _RNID_TOP_DISC { 820dea3101eS struct lpfc_name portName; 821dea3101eS uint8_t resvd[8]; 822dea3101eS uint32_t unitType; 823dea3101eS #define RNID_HBA 0x7 824dea3101eS #define RNID_HOST 0xa 825dea3101eS #define RNID_DRIVER 0xd 826dea3101eS uint32_t physPort; 827dea3101eS uint32_t attachedNodes; 828dea3101eS uint16_t ipVersion; 829dea3101eS #define RNID_IPV4 0x1 830dea3101eS #define RNID_IPV6 0x2 831dea3101eS uint16_t UDPport; 832dea3101eS uint8_t ipAddr[16]; 833dea3101eS uint16_t resvd1; 834dea3101eS uint16_t flags; 835dea3101eS #define RNID_TD_SUPPORT 0x1 836dea3101eS #define RNID_LP_VALID 0x2 837dea3101eS } RNID_TOP_DISC; 838dea3101eS 839dea3101eS typedef struct _RNID { /* Structure is in Big Endian format */ 840dea3101eS uint8_t Format; 841dea3101eS #define RNID_TOPOLOGY_DISC 0xdf 842dea3101eS uint8_t CommonLen; 843dea3101eS uint8_t resvd1; 844dea3101eS uint8_t SpecificLen; 845dea3101eS struct lpfc_name portName; 846dea3101eS struct lpfc_name nodeName; 847dea3101eS union { 848dea3101eS RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 849dea3101eS } un; 850dea3101eS } RNID; 851dea3101eS 8527bb3b137SJamie Wellnitz typedef struct _RPS { /* Structure is in Big Endian format */ 8537bb3b137SJamie Wellnitz union { 8547bb3b137SJamie Wellnitz uint32_t portNum; 8557bb3b137SJamie Wellnitz struct lpfc_name portName; 8567bb3b137SJamie Wellnitz } un; 8577bb3b137SJamie Wellnitz } RPS; 8587bb3b137SJamie Wellnitz 8597bb3b137SJamie Wellnitz typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 8607bb3b137SJamie Wellnitz uint16_t rsvd1; 8617bb3b137SJamie Wellnitz uint16_t portStatus; 8627bb3b137SJamie Wellnitz uint32_t linkFailureCnt; 8637bb3b137SJamie Wellnitz uint32_t lossSyncCnt; 8647bb3b137SJamie Wellnitz uint32_t lossSignalCnt; 8657bb3b137SJamie Wellnitz uint32_t primSeqErrCnt; 8667bb3b137SJamie Wellnitz uint32_t invalidXmitWord; 8677bb3b137SJamie Wellnitz uint32_t crcCnt; 8687bb3b137SJamie Wellnitz } RPS_RSP; 8697bb3b137SJamie Wellnitz 87012265f68SJames Smart struct RLS { /* Structure is in Big Endian format */ 87112265f68SJames Smart uint32_t rls; 87212265f68SJames Smart #define rls_rsvd_SHIFT 24 87312265f68SJames Smart #define rls_rsvd_MASK 0x000000ff 87412265f68SJames Smart #define rls_rsvd_WORD rls 87512265f68SJames Smart #define rls_did_SHIFT 0 87612265f68SJames Smart #define rls_did_MASK 0x00ffffff 87712265f68SJames Smart #define rls_did_WORD rls 87812265f68SJames Smart }; 87912265f68SJames Smart 88012265f68SJames Smart struct RLS_RSP { /* Structure is in Big Endian format */ 88112265f68SJames Smart uint32_t linkFailureCnt; 88212265f68SJames Smart uint32_t lossSyncCnt; 88312265f68SJames Smart uint32_t lossSignalCnt; 88412265f68SJames Smart uint32_t primSeqErrCnt; 88512265f68SJames Smart uint32_t invalidXmitWord; 88612265f68SJames Smart uint32_t crcCnt; 88712265f68SJames Smart }; 88812265f68SJames Smart 88919ca7609SJames Smart struct RRQ { /* Structure is in Big Endian format */ 89019ca7609SJames Smart uint32_t rrq; 89119ca7609SJames Smart #define rrq_rsvd_SHIFT 24 89219ca7609SJames Smart #define rrq_rsvd_MASK 0x000000ff 89319ca7609SJames Smart #define rrq_rsvd_WORD rrq 89419ca7609SJames Smart #define rrq_did_SHIFT 0 89519ca7609SJames Smart #define rrq_did_MASK 0x00ffffff 89619ca7609SJames Smart #define rrq_did_WORD rrq 89719ca7609SJames Smart uint32_t rrq_exchg; 89819ca7609SJames Smart #define rrq_oxid_SHIFT 16 89919ca7609SJames Smart #define rrq_oxid_MASK 0xffff 90019ca7609SJames Smart #define rrq_oxid_WORD rrq_exchg 90119ca7609SJames Smart #define rrq_rxid_SHIFT 0 90219ca7609SJames Smart #define rrq_rxid_MASK 0xffff 90319ca7609SJames Smart #define rrq_rxid_WORD rrq_exchg 90419ca7609SJames Smart }; 90519ca7609SJames Smart 90619ca7609SJames Smart 90712265f68SJames Smart struct RTV_RSP { /* Structure is in Big Endian format */ 90812265f68SJames Smart uint32_t ratov; 90912265f68SJames Smart uint32_t edtov; 91012265f68SJames Smart uint32_t qtov; 91112265f68SJames Smart #define qtov_rsvd0_SHIFT 28 91212265f68SJames Smart #define qtov_rsvd0_MASK 0x0000000f 91312265f68SJames Smart #define qtov_rsvd0_WORD qtov /* reserved */ 91412265f68SJames Smart #define qtov_edtovres_SHIFT 27 91512265f68SJames Smart #define qtov_edtovres_MASK 0x00000001 91612265f68SJames Smart #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 91712265f68SJames Smart #define qtov__rsvd1_SHIFT 19 91812265f68SJames Smart #define qtov_rsvd1_MASK 0x0000003f 91912265f68SJames Smart #define qtov_rsvd1_WORD qtov /* reserved */ 92012265f68SJames Smart #define qtov_rttov_SHIFT 18 92112265f68SJames Smart #define qtov_rttov_MASK 0x00000001 92212265f68SJames Smart #define qtov_rttov_WORD qtov /* R_T_TOV value */ 92312265f68SJames Smart #define qtov_rsvd2_SHIFT 0 92412265f68SJames Smart #define qtov_rsvd2_MASK 0x0003ffff 92512265f68SJames Smart #define qtov_rsvd2_WORD qtov /* reserved */ 92612265f68SJames Smart }; 92712265f68SJames Smart 92812265f68SJames Smart 9297bb3b137SJamie Wellnitz typedef struct _RPL { /* Structure is in Big Endian format */ 9307bb3b137SJamie Wellnitz uint32_t maxsize; 9317bb3b137SJamie Wellnitz uint32_t index; 9327bb3b137SJamie Wellnitz } RPL; 9337bb3b137SJamie Wellnitz 9347bb3b137SJamie Wellnitz typedef struct _PORT_NUM_BLK { 9357bb3b137SJamie Wellnitz uint32_t portNum; 9367bb3b137SJamie Wellnitz uint32_t portID; 9377bb3b137SJamie Wellnitz struct lpfc_name portName; 9387bb3b137SJamie Wellnitz } PORT_NUM_BLK; 9397bb3b137SJamie Wellnitz 9407bb3b137SJamie Wellnitz typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 9417bb3b137SJamie Wellnitz uint32_t listLen; 9427bb3b137SJamie Wellnitz uint32_t index; 9437bb3b137SJamie Wellnitz PORT_NUM_BLK port_num_blk; 9447bb3b137SJamie Wellnitz } RPL_RSP; 945dea3101eS 946dea3101eS /* This is used for RSCN command */ 947dea3101eS typedef struct _D_ID { /* Structure is in Big Endian format */ 948dea3101eS union { 949dea3101eS uint32_t word; 950dea3101eS struct { 951dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 952dea3101eS uint8_t resv; 953dea3101eS uint8_t domain; 954dea3101eS uint8_t area; 955dea3101eS uint8_t id; 956dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 957dea3101eS uint8_t id; 958dea3101eS uint8_t area; 959dea3101eS uint8_t domain; 960dea3101eS uint8_t resv; 961dea3101eS #endif 962dea3101eS } b; 963dea3101eS } un; 964dea3101eS } D_ID; 965dea3101eS 966eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_PORT 0x0 967eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_AREA 0x1 968eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 969eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 970eaf15d5bSJames Smart #define RSCN_ADDRESS_FORMAT_MASK 0x3 971eaf15d5bSJames Smart 972dea3101eS /* 973dea3101eS * Structure to define all ELS Payload types 974dea3101eS */ 975dea3101eS 976dea3101eS typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 977dea3101eS uint8_t elsCode; /* FC Word 0, bit 24:31 */ 978dea3101eS uint8_t elsByte1; 979dea3101eS uint8_t elsByte2; 980dea3101eS uint8_t elsByte3; 981dea3101eS union { 982dea3101eS struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 983dea3101eS struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 984dea3101eS LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 985dea3101eS PRLI prli; /* Payload for PRLI/ACC */ 986dea3101eS PRLO prlo; /* Payload for PRLO/ACC */ 987dea3101eS ADISC adisc; /* Payload for ADISC/ACC */ 988dea3101eS FARP farp; /* Payload for FARP/ACC */ 989dea3101eS FAN fan; /* Payload for FAN */ 990dea3101eS SCR scr; /* Payload for SCR/ACC */ 991dea3101eS RNID rnid; /* Payload for RNID */ 992dea3101eS uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 993dea3101eS } un; 994dea3101eS } ELS_PKT; 995dea3101eS 996dea3101eS /* 997dea3101eS * FDMI 998dea3101eS * HBA MAnagement Operations Command Codes 999dea3101eS */ 1000dea3101eS #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1001dea3101eS #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1002dea3101eS #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1003dea3101eS #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1004dea3101eS #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1005dea3101eS #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 1006dea3101eS #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1007dea3101eS #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1008dea3101eS #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1009dea3101eS #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1010dea3101eS 1011dea3101eS /* 1012dea3101eS * Management Service Subtypes 1013dea3101eS */ 1014dea3101eS #define SLI_CT_FDMI_Subtypes 0x10 1015dea3101eS 1016dea3101eS /* 1017dea3101eS * HBA Management Service Reject Code 1018dea3101eS */ 1019dea3101eS #define REJECT_CODE 0x9 /* Unable to perform command request */ 1020dea3101eS 1021dea3101eS /* 1022dea3101eS * HBA Management Service Reject Reason Code 1023dea3101eS * Please refer to the Reason Codes above 1024dea3101eS */ 1025dea3101eS 1026dea3101eS /* 1027dea3101eS * HBA Attribute Types 1028dea3101eS */ 1029dea3101eS #define NODE_NAME 0x1 1030dea3101eS #define MANUFACTURER 0x2 1031dea3101eS #define SERIAL_NUMBER 0x3 1032dea3101eS #define MODEL 0x4 1033dea3101eS #define MODEL_DESCRIPTION 0x5 1034dea3101eS #define HARDWARE_VERSION 0x6 1035dea3101eS #define DRIVER_VERSION 0x7 1036dea3101eS #define OPTION_ROM_VERSION 0x8 1037dea3101eS #define FIRMWARE_VERSION 0x9 1038dea3101eS #define OS_NAME_VERSION 0xa 1039dea3101eS #define MAX_CT_PAYLOAD_LEN 0xb 1040dea3101eS 1041dea3101eS /* 1042dea3101eS * Port Attrubute Types 1043dea3101eS */ 1044dea3101eS #define SUPPORTED_FC4_TYPES 0x1 1045dea3101eS #define SUPPORTED_SPEED 0x2 1046dea3101eS #define PORT_SPEED 0x3 1047dea3101eS #define MAX_FRAME_SIZE 0x4 1048dea3101eS #define OS_DEVICE_NAME 0x5 1049dea3101eS #define HOST_NAME 0x6 1050dea3101eS 1051dea3101eS union AttributesDef { 1052dea3101eS /* Structure is in Big Endian format */ 1053dea3101eS struct { 1054dea3101eS uint32_t AttrType:16; 1055dea3101eS uint32_t AttrLen:16; 1056dea3101eS } bits; 1057dea3101eS uint32_t word; 1058dea3101eS }; 1059dea3101eS 1060dea3101eS 1061dea3101eS /* 1062dea3101eS * HBA Attribute Entry (8 - 260 bytes) 1063dea3101eS */ 1064dea3101eS typedef struct { 1065dea3101eS union AttributesDef ad; 1066dea3101eS union { 1067dea3101eS uint32_t VendorSpecific; 1068dea3101eS uint8_t Manufacturer[64]; 1069dea3101eS uint8_t SerialNumber[64]; 1070dea3101eS uint8_t Model[256]; 1071dea3101eS uint8_t ModelDescription[256]; 1072dea3101eS uint8_t HardwareVersion[256]; 1073dea3101eS uint8_t DriverVersion[256]; 1074dea3101eS uint8_t OptionROMVersion[256]; 1075dea3101eS uint8_t FirmwareVersion[256]; 1076dea3101eS struct lpfc_name NodeName; 1077dea3101eS uint8_t SupportFC4Types[32]; 1078dea3101eS uint32_t SupportSpeed; 1079dea3101eS uint32_t PortSpeed; 1080dea3101eS uint32_t MaxFrameSize; 1081dea3101eS uint8_t OsDeviceName[256]; 1082dea3101eS uint8_t OsNameVersion[256]; 1083dea3101eS uint32_t MaxCTPayloadLen; 1084dea3101eS uint8_t HostName[256]; 1085dea3101eS } un; 1086dea3101eS } ATTRIBUTE_ENTRY; 1087dea3101eS 1088dea3101eS /* 1089dea3101eS * HBA Attribute Block 1090dea3101eS */ 1091dea3101eS typedef struct { 1092dea3101eS uint32_t EntryCnt; /* Number of HBA attribute entries */ 1093dea3101eS ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 1094dea3101eS } ATTRIBUTE_BLOCK; 1095dea3101eS 1096dea3101eS /* 1097dea3101eS * Port Entry 1098dea3101eS */ 1099dea3101eS typedef struct { 1100dea3101eS struct lpfc_name PortName; 1101dea3101eS } PORT_ENTRY; 1102dea3101eS 1103dea3101eS /* 1104dea3101eS * HBA Identifier 1105dea3101eS */ 1106dea3101eS typedef struct { 1107dea3101eS struct lpfc_name PortName; 1108dea3101eS } HBA_IDENTIFIER; 1109dea3101eS 1110dea3101eS /* 1111dea3101eS * Registered Port List Format 1112dea3101eS */ 1113dea3101eS typedef struct { 1114dea3101eS uint32_t EntryCnt; 1115dea3101eS PORT_ENTRY pe; /* Variable-length array */ 1116dea3101eS } REG_PORT_LIST; 1117dea3101eS 1118dea3101eS /* 1119dea3101eS * Register HBA(RHBA) 1120dea3101eS */ 1121dea3101eS typedef struct { 1122dea3101eS HBA_IDENTIFIER hi; 1123dea3101eS REG_PORT_LIST rpl; /* variable-length array */ 1124dea3101eS /* ATTRIBUTE_BLOCK ab; */ 1125dea3101eS } REG_HBA; 1126dea3101eS 1127dea3101eS /* 1128dea3101eS * Register HBA Attributes (RHAT) 1129dea3101eS */ 1130dea3101eS typedef struct { 1131dea3101eS struct lpfc_name HBA_PortName; 1132dea3101eS ATTRIBUTE_BLOCK ab; 1133dea3101eS } REG_HBA_ATTRIBUTE; 1134dea3101eS 1135dea3101eS /* 1136dea3101eS * Register Port Attributes (RPA) 1137dea3101eS */ 1138dea3101eS typedef struct { 1139dea3101eS struct lpfc_name PortName; 1140dea3101eS ATTRIBUTE_BLOCK ab; 1141dea3101eS } REG_PORT_ATTRIBUTE; 1142dea3101eS 1143dea3101eS /* 1144dea3101eS * Get Registered HBA List (GRHL) Accept Payload Format 1145dea3101eS */ 1146dea3101eS typedef struct { 1147dea3101eS uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 1148dea3101eS struct lpfc_name HBA_PortName; /* Variable-length array */ 1149dea3101eS } GRHL_ACC_PAYLOAD; 1150dea3101eS 1151dea3101eS /* 1152dea3101eS * Get Registered Port List (GRPL) Accept Payload Format 1153dea3101eS */ 1154dea3101eS typedef struct { 1155dea3101eS uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 1156dea3101eS PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 1157dea3101eS } GRPL_ACC_PAYLOAD; 1158dea3101eS 1159dea3101eS /* 1160dea3101eS * Get Port Attributes (GPAT) Accept Payload Format 1161dea3101eS */ 1162dea3101eS 1163dea3101eS typedef struct { 1164dea3101eS ATTRIBUTE_BLOCK pab; 1165dea3101eS } GPAT_ACC_PAYLOAD; 1166dea3101eS 1167dea3101eS 1168dea3101eS /* 1169dea3101eS * Begin HBA configuration parameters. 1170dea3101eS * The PCI configuration register BAR assignments are: 1171dea3101eS * BAR0, offset 0x10 - SLIM base memory address 1172dea3101eS * BAR1, offset 0x14 - SLIM base memory high address 1173dea3101eS * BAR2, offset 0x18 - REGISTER base memory address 1174dea3101eS * BAR3, offset 0x1c - REGISTER base memory high address 1175dea3101eS * BAR4, offset 0x20 - BIU I/O registers 1176dea3101eS * BAR5, offset 0x24 - REGISTER base io high address 1177dea3101eS */ 1178dea3101eS 1179dea3101eS /* Number of rings currently used and available. */ 1180dea3101eS #define MAX_CONFIGURED_RINGS 3 1181dea3101eS #define MAX_RINGS 4 1182dea3101eS 1183dea3101eS /* IOCB / Mailbox is owned by FireFly */ 1184dea3101eS #define OWN_CHIP 1 1185dea3101eS 1186dea3101eS /* IOCB / Mailbox is owned by Host */ 1187dea3101eS #define OWN_HOST 0 1188dea3101eS 1189dea3101eS /* Number of 4-byte words in an IOCB. */ 1190dea3101eS #define IOCB_WORD_SZ 8 1191dea3101eS 1192dea3101eS /* network headers for Dfctl field */ 1193dea3101eS #define FC_NET_HDR 0x20 1194dea3101eS 1195dea3101eS /* Start FireFly Register definitions */ 1196dea3101eS #define PCI_VENDOR_ID_EMULEX 0x10df 1197dea3101eS #define PCI_DEVICE_ID_FIREFLY 0x1ae5 119884774a4dSJames Smart #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1199085c647cSJames Smart #define PCI_DEVICE_ID_BALIUS 0xe131 120084774a4dSJames Smart #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1201085c647cSJames Smart #define PCI_DEVICE_ID_LANCER_FC 0xe200 1202085c647cSJames Smart #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1203b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_SMB 0xf011 1204b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_MID 0xf015 1205dea3101eS #define PCI_DEVICE_ID_RFLY 0xf095 1206dea3101eS #define PCI_DEVICE_ID_PFLY 0xf098 1207e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_LP101 0xf0a1 1208dea3101eS #define PCI_DEVICE_ID_TFLY 0xf0a5 1209e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_BSMB 0xf0d1 1210e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_BMID 0xf0d5 1211e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZSMB 0xf0e1 1212e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZMID 0xf0e5 1213e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1214e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1215e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1216b87eab38SJames Smart #define PCI_DEVICE_ID_SAT 0xf100 1217b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1218b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1219085c647cSJames Smart #define PCI_DEVICE_ID_FALCON 0xf180 1220e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_SUPERFLY 0xf700 1221e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1222dea3101eS #define PCI_DEVICE_ID_CENTAUR 0xf900 1223dea3101eS #define PCI_DEVICE_ID_PEGASUS 0xf980 1224dea3101eS #define PCI_DEVICE_ID_THOR 0xfa00 1225dea3101eS #define PCI_DEVICE_ID_VIPER 0xfb00 1226dea3101eS #define PCI_DEVICE_ID_LP10000S 0xfc00 1227e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_LP11000S 0xfc10 1228e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_LPE11000S 0xfc20 1229b87eab38SJames Smart #define PCI_DEVICE_ID_SAT_S 0xfc40 123084774a4dSJames Smart #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1231e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_HELIOS 0xfd00 1232e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1233e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1234e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZEPHYR 0xfe00 123584774a4dSJames Smart #define PCI_DEVICE_ID_HORNET 0xfe05 1236e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1237e4adb204SJames.Smart@Emulex.Com #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1238da0436e9SJames Smart #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1239da0436e9SJames Smart #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1240a747c9ceSJames Smart #define PCI_DEVICE_ID_TOMCAT 0x0714 1241dea3101eS 1242dea3101eS #define JEDEC_ID_ADDRESS 0x0080001c 1243dea3101eS #define FIREFLY_JEDEC_ID 0x1ACC 1244dea3101eS #define SUPERFLY_JEDEC_ID 0x0020 1245dea3101eS #define DRAGONFLY_JEDEC_ID 0x0021 1246dea3101eS #define DRAGONFLY_V2_JEDEC_ID 0x0025 1247dea3101eS #define CENTAUR_2G_JEDEC_ID 0x0026 1248dea3101eS #define CENTAUR_1G_JEDEC_ID 0x0028 1249dea3101eS #define PEGASUS_ORION_JEDEC_ID 0x0036 1250dea3101eS #define PEGASUS_JEDEC_ID 0x0038 1251dea3101eS #define THOR_JEDEC_ID 0x0012 1252dea3101eS #define HELIOS_JEDEC_ID 0x0364 1253dea3101eS #define ZEPHYR_JEDEC_ID 0x0577 1254dea3101eS #define VIPER_JEDEC_ID 0x4838 1255b87eab38SJames Smart #define SATURN_JEDEC_ID 0x1004 125684774a4dSJames Smart #define HORNET_JDEC_ID 0x2057706D 1257dea3101eS 1258dea3101eS #define JEDEC_ID_MASK 0x0FFFF000 1259dea3101eS #define JEDEC_ID_SHIFT 12 1260dea3101eS #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1261dea3101eS 1262dea3101eS typedef struct { /* FireFly BIU registers */ 1263dea3101eS uint32_t hostAtt; /* See definitions for Host Attention 1264dea3101eS register */ 1265dea3101eS uint32_t chipAtt; /* See definitions for Chip Attention 1266dea3101eS register */ 1267dea3101eS uint32_t hostStatus; /* See definitions for Host Status register */ 1268dea3101eS uint32_t hostControl; /* See definitions for Host Control register */ 1269dea3101eS uint32_t buiConfig; /* See definitions for BIU configuration 1270dea3101eS register */ 1271dea3101eS } FF_REGS; 1272dea3101eS 1273dea3101eS /* IO Register size in bytes */ 1274dea3101eS #define FF_REG_AREA_SIZE 256 1275dea3101eS 1276dea3101eS /* Host Attention Register */ 1277dea3101eS 1278dea3101eS #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1279dea3101eS 1280dea3101eS #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1281dea3101eS #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1282dea3101eS #define HA_R0ATT 0x00000008 /* Bit 3 */ 1283dea3101eS #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1284dea3101eS #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1285dea3101eS #define HA_R1ATT 0x00000080 /* Bit 7 */ 1286dea3101eS #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1287dea3101eS #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1288dea3101eS #define HA_R2ATT 0x00000800 /* Bit 11 */ 1289dea3101eS #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1290dea3101eS #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1291dea3101eS #define HA_R3ATT 0x00008000 /* Bit 15 */ 1292dea3101eS #define HA_LATT 0x20000000 /* Bit 29 */ 1293dea3101eS #define HA_MBATT 0x40000000 /* Bit 30 */ 1294dea3101eS #define HA_ERATT 0x80000000 /* Bit 31 */ 1295dea3101eS 1296dea3101eS #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1297dea3101eS #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1298dea3101eS #define HA_RXATT 0x00000008 /* Bit 3 */ 1299dea3101eS #define HA_RXMASK 0x0000000f 1300dea3101eS 13019399627fSJames Smart #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 13029399627fSJames Smart #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 13039399627fSJames Smart #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 13049399627fSJames Smart #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 13059399627fSJames Smart 13069399627fSJames Smart #define HA_R0_POS 3 13079399627fSJames Smart #define HA_R1_POS 7 13089399627fSJames Smart #define HA_R2_POS 11 13099399627fSJames Smart #define HA_R3_POS 15 13109399627fSJames Smart #define HA_LE_POS 29 13119399627fSJames Smart #define HA_MB_POS 30 13129399627fSJames Smart #define HA_ER_POS 31 1313dea3101eS /* Chip Attention Register */ 1314dea3101eS 1315dea3101eS #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1316dea3101eS 1317dea3101eS #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1318dea3101eS #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1319dea3101eS #define CA_R0ATT 0x00000008 /* Bit 3 */ 1320dea3101eS #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1321dea3101eS #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1322dea3101eS #define CA_R1ATT 0x00000080 /* Bit 7 */ 1323dea3101eS #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1324dea3101eS #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1325dea3101eS #define CA_R2ATT 0x00000800 /* Bit 11 */ 1326dea3101eS #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1327dea3101eS #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1328dea3101eS #define CA_R3ATT 0x00008000 /* Bit 15 */ 1329dea3101eS #define CA_MBATT 0x40000000 /* Bit 30 */ 1330dea3101eS 1331dea3101eS /* Host Status Register */ 1332dea3101eS 1333dea3101eS #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1334dea3101eS 1335dea3101eS #define HS_MBRDY 0x00400000 /* Bit 22 */ 1336dea3101eS #define HS_FFRDY 0x00800000 /* Bit 23 */ 1337dea3101eS #define HS_FFER8 0x01000000 /* Bit 24 */ 1338dea3101eS #define HS_FFER7 0x02000000 /* Bit 25 */ 1339dea3101eS #define HS_FFER6 0x04000000 /* Bit 26 */ 1340dea3101eS #define HS_FFER5 0x08000000 /* Bit 27 */ 1341dea3101eS #define HS_FFER4 0x10000000 /* Bit 28 */ 1342dea3101eS #define HS_FFER3 0x20000000 /* Bit 29 */ 1343dea3101eS #define HS_FFER2 0x40000000 /* Bit 30 */ 1344dea3101eS #define HS_FFER1 0x80000000 /* Bit 31 */ 134557127f15SJames Smart #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 134657127f15SJames Smart #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1347dea3101eS 1348dea3101eS /* Host Control Register */ 1349dea3101eS 13509399627fSJames Smart #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1351dea3101eS 1352dea3101eS #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1353dea3101eS #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1354dea3101eS #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1355dea3101eS #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1356dea3101eS #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1357dea3101eS #define HC_INITHBI 0x02000000 /* Bit 25 */ 1358dea3101eS #define HC_INITMB 0x04000000 /* Bit 26 */ 1359dea3101eS #define HC_INITFF 0x08000000 /* Bit 27 */ 1360dea3101eS #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1361dea3101eS #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1362dea3101eS 13639399627fSJames Smart /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 13649399627fSJames Smart #define MSIX_DFLT_ID 0 13659399627fSJames Smart #define MSIX_RNG0_ID 0 13669399627fSJames Smart #define MSIX_RNG1_ID 1 13679399627fSJames Smart #define MSIX_RNG2_ID 2 13689399627fSJames Smart #define MSIX_RNG3_ID 3 13699399627fSJames Smart 13709399627fSJames Smart #define MSIX_LINK_ID 4 13719399627fSJames Smart #define MSIX_MBOX_ID 5 13729399627fSJames Smart 13739399627fSJames Smart #define MSIX_SPARE0_ID 6 13749399627fSJames Smart #define MSIX_SPARE1_ID 7 13759399627fSJames Smart 1376dea3101eS /* Mailbox Commands */ 1377dea3101eS #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1378dea3101eS #define MBX_LOAD_SM 0x01 1379dea3101eS #define MBX_READ_NV 0x02 1380dea3101eS #define MBX_WRITE_NV 0x03 1381dea3101eS #define MBX_RUN_BIU_DIAG 0x04 1382dea3101eS #define MBX_INIT_LINK 0x05 1383dea3101eS #define MBX_DOWN_LINK 0x06 1384dea3101eS #define MBX_CONFIG_LINK 0x07 1385dea3101eS #define MBX_CONFIG_RING 0x09 1386dea3101eS #define MBX_RESET_RING 0x0A 1387dea3101eS #define MBX_READ_CONFIG 0x0B 1388dea3101eS #define MBX_READ_RCONFIG 0x0C 1389dea3101eS #define MBX_READ_SPARM 0x0D 1390dea3101eS #define MBX_READ_STATUS 0x0E 1391dea3101eS #define MBX_READ_RPI 0x0F 1392dea3101eS #define MBX_READ_XRI 0x10 1393dea3101eS #define MBX_READ_REV 0x11 1394dea3101eS #define MBX_READ_LNK_STAT 0x12 1395dea3101eS #define MBX_REG_LOGIN 0x13 1396dea3101eS #define MBX_UNREG_LOGIN 0x14 1397dea3101eS #define MBX_CLEAR_LA 0x16 1398dea3101eS #define MBX_DUMP_MEMORY 0x17 1399dea3101eS #define MBX_DUMP_CONTEXT 0x18 1400dea3101eS #define MBX_RUN_DIAGS 0x19 1401dea3101eS #define MBX_RESTART 0x1A 1402dea3101eS #define MBX_UPDATE_CFG 0x1B 1403dea3101eS #define MBX_DOWN_LOAD 0x1C 1404dea3101eS #define MBX_DEL_LD_ENTRY 0x1D 1405dea3101eS #define MBX_RUN_PROGRAM 0x1E 1406dea3101eS #define MBX_SET_MASK 0x20 140709372820SJames Smart #define MBX_SET_VARIABLE 0x21 1408dea3101eS #define MBX_UNREG_D_ID 0x23 140941415862SJamie Wellnitz #define MBX_KILL_BOARD 0x24 1410dea3101eS #define MBX_CONFIG_FARP 0x25 141141415862SJamie Wellnitz #define MBX_BEACON 0x2A 14129399627fSJames Smart #define MBX_CONFIG_MSI 0x30 1413858c9f6cSJames Smart #define MBX_HEARTBEAT 0x31 1414a8adb832SJames Smart #define MBX_WRITE_VPARMS 0x32 1415a8adb832SJames Smart #define MBX_ASYNCEVT_ENABLE 0x33 14164fede78fSJames Smart #define MBX_READ_EVENT_LOG_STATUS 0x37 14174fede78fSJames Smart #define MBX_READ_EVENT_LOG 0x38 14184fede78fSJames Smart #define MBX_WRITE_EVENT_LOG 0x39 1419dea3101eS 142084774a4dSJames Smart #define MBX_PORT_CAPABILITIES 0x3B 142184774a4dSJames Smart #define MBX_PORT_IOV_CONTROL 0x3C 142284774a4dSJames Smart 1423ed957684SJames Smart #define MBX_CONFIG_HBQ 0x7C 1424dea3101eS #define MBX_LOAD_AREA 0x81 1425dea3101eS #define MBX_RUN_BIU_DIAG64 0x84 1426dea3101eS #define MBX_CONFIG_PORT 0x88 1427dea3101eS #define MBX_READ_SPARM64 0x8D 1428dea3101eS #define MBX_READ_RPI64 0x8F 1429dea3101eS #define MBX_REG_LOGIN64 0x93 143076a95d75SJames Smart #define MBX_READ_TOPOLOGY 0x95 143192d7f7b0SJames Smart #define MBX_REG_VPI 0x96 143292d7f7b0SJames Smart #define MBX_UNREG_VPI 0x97 1433dea3101eS 143409372820SJames Smart #define MBX_WRITE_WWN 0x98 1435dea3101eS #define MBX_SET_DEBUG 0x99 1436dea3101eS #define MBX_LOAD_EXP_ROM 0x9C 1437da0436e9SJames Smart #define MBX_SLI4_CONFIG 0x9B 1438da0436e9SJames Smart #define MBX_SLI4_REQ_FTRS 0x9D 1439da0436e9SJames Smart #define MBX_MAX_CMDS 0x9E 1440da0436e9SJames Smart #define MBX_RESUME_RPI 0x9E 1441dea3101eS #define MBX_SLI2_CMD_MASK 0x80 1442da0436e9SJames Smart #define MBX_REG_VFI 0x9F 1443da0436e9SJames Smart #define MBX_REG_FCFI 0xA0 1444da0436e9SJames Smart #define MBX_UNREG_VFI 0xA1 1445da0436e9SJames Smart #define MBX_UNREG_FCFI 0xA2 1446da0436e9SJames Smart #define MBX_INIT_VFI 0xA3 1447da0436e9SJames Smart #define MBX_INIT_VPI 0xA4 1448dea3101eS 1449dcf2a4e0SJames Smart #define MBX_AUTH_PORT 0xF8 1450dcf2a4e0SJames Smart #define MBX_SECURITY_MGMT 0xF9 1451dcf2a4e0SJames Smart 1452dea3101eS /* IOCB Commands */ 1453dea3101eS 1454dea3101eS #define CMD_RCV_SEQUENCE_CX 0x01 1455dea3101eS #define CMD_XMIT_SEQUENCE_CR 0x02 1456dea3101eS #define CMD_XMIT_SEQUENCE_CX 0x03 1457dea3101eS #define CMD_XMIT_BCAST_CN 0x04 1458dea3101eS #define CMD_XMIT_BCAST_CX 0x05 1459dea3101eS #define CMD_QUE_RING_BUF_CN 0x06 1460dea3101eS #define CMD_QUE_XRI_BUF_CX 0x07 1461dea3101eS #define CMD_IOCB_CONTINUE_CN 0x08 1462dea3101eS #define CMD_RET_XRI_BUF_CX 0x09 1463dea3101eS #define CMD_ELS_REQUEST_CR 0x0A 1464dea3101eS #define CMD_ELS_REQUEST_CX 0x0B 1465dea3101eS #define CMD_RCV_ELS_REQ_CX 0x0D 1466dea3101eS #define CMD_ABORT_XRI_CN 0x0E 1467dea3101eS #define CMD_ABORT_XRI_CX 0x0F 1468dea3101eS #define CMD_CLOSE_XRI_CN 0x10 1469dea3101eS #define CMD_CLOSE_XRI_CX 0x11 1470dea3101eS #define CMD_CREATE_XRI_CR 0x12 1471dea3101eS #define CMD_CREATE_XRI_CX 0x13 1472dea3101eS #define CMD_GET_RPI_CN 0x14 1473dea3101eS #define CMD_XMIT_ELS_RSP_CX 0x15 1474dea3101eS #define CMD_GET_RPI_CR 0x16 1475dea3101eS #define CMD_XRI_ABORTED_CX 0x17 1476dea3101eS #define CMD_FCP_IWRITE_CR 0x18 1477dea3101eS #define CMD_FCP_IWRITE_CX 0x19 1478dea3101eS #define CMD_FCP_IREAD_CR 0x1A 1479dea3101eS #define CMD_FCP_IREAD_CX 0x1B 1480dea3101eS #define CMD_FCP_ICMND_CR 0x1C 1481dea3101eS #define CMD_FCP_ICMND_CX 0x1D 1482f5603511SJames Smart #define CMD_FCP_TSEND_CX 0x1F 1483f5603511SJames Smart #define CMD_FCP_TRECEIVE_CX 0x21 1484f5603511SJames Smart #define CMD_FCP_TRSP_CX 0x23 1485f5603511SJames Smart #define CMD_FCP_AUTO_TRSP_CX 0x29 1486dea3101eS 1487dea3101eS #define CMD_ADAPTER_MSG 0x20 1488dea3101eS #define CMD_ADAPTER_DUMP 0x22 1489dea3101eS 1490dea3101eS /* SLI_2 IOCB Command Set */ 1491dea3101eS 149257127f15SJames Smart #define CMD_ASYNC_STATUS 0x7C 1493dea3101eS #define CMD_RCV_SEQUENCE64_CX 0x81 1494dea3101eS #define CMD_XMIT_SEQUENCE64_CR 0x82 1495dea3101eS #define CMD_XMIT_SEQUENCE64_CX 0x83 1496dea3101eS #define CMD_XMIT_BCAST64_CN 0x84 1497dea3101eS #define CMD_XMIT_BCAST64_CX 0x85 1498dea3101eS #define CMD_QUE_RING_BUF64_CN 0x86 1499dea3101eS #define CMD_QUE_XRI_BUF64_CX 0x87 1500dea3101eS #define CMD_IOCB_CONTINUE64_CN 0x88 1501dea3101eS #define CMD_RET_XRI_BUF64_CX 0x89 1502dea3101eS #define CMD_ELS_REQUEST64_CR 0x8A 1503dea3101eS #define CMD_ELS_REQUEST64_CX 0x8B 1504dea3101eS #define CMD_ABORT_MXRI64_CN 0x8C 1505dea3101eS #define CMD_RCV_ELS_REQ64_CX 0x8D 1506dea3101eS #define CMD_XMIT_ELS_RSP64_CX 0x95 15076669f9bbSJames Smart #define CMD_XMIT_BLS_RSP64_CX 0x97 1508dea3101eS #define CMD_FCP_IWRITE64_CR 0x98 1509dea3101eS #define CMD_FCP_IWRITE64_CX 0x99 1510dea3101eS #define CMD_FCP_IREAD64_CR 0x9A 1511dea3101eS #define CMD_FCP_IREAD64_CX 0x9B 1512dea3101eS #define CMD_FCP_ICMND64_CR 0x9C 1513dea3101eS #define CMD_FCP_ICMND64_CX 0x9D 1514f5603511SJames Smart #define CMD_FCP_TSEND64_CX 0x9F 1515f5603511SJames Smart #define CMD_FCP_TRECEIVE64_CX 0xA1 1516f5603511SJames Smart #define CMD_FCP_TRSP64_CX 0xA3 1517dea3101eS 151876bb24efSJames Smart #define CMD_QUE_XRI64_CX 0xB3 1519ed957684SJames Smart #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1520ed957684SJames Smart #define CMD_IOCB_RCV_ELS64_CX 0xB7 15213163f725SJames Smart #define CMD_IOCB_RET_XRI64_CX 0xB9 1522ed957684SJames Smart #define CMD_IOCB_RCV_CONT64_CX 0xBB 1523ed957684SJames Smart 1524dea3101eS #define CMD_GEN_REQUEST64_CR 0xC2 1525dea3101eS #define CMD_GEN_REQUEST64_CX 0xC3 1526dea3101eS 15273163f725SJames Smart /* Unhandled SLI-3 Commands */ 15283163f725SJames Smart #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 15293163f725SJames Smart #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 15303163f725SJames Smart #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 15313163f725SJames Smart #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 15323163f725SJames Smart #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 15333163f725SJames Smart #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 15343163f725SJames Smart #define CMD_IOCB_RET_HBQE64_CN 0xCA 15353163f725SJames Smart #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 15363163f725SJames Smart #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 15373163f725SJames Smart #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 15383163f725SJames Smart #define CMD_IOCB_LOGENTRY_CN 0x94 15393163f725SJames Smart #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 15403163f725SJames Smart 1541341af102SJames Smart /* Data Security SLI Commands */ 1542341af102SJames Smart #define DSSCMD_IWRITE64_CR 0xF8 1543341af102SJames Smart #define DSSCMD_IWRITE64_CX 0xF9 1544341af102SJames Smart #define DSSCMD_IREAD64_CR 0xFA 1545341af102SJames Smart #define DSSCMD_IREAD64_CX 0xFB 1546da0436e9SJames Smart 1547341af102SJames Smart #define CMD_MAX_IOCB_CMD 0xFB 1548dea3101eS #define CMD_IOCB_MASK 0xff 1549dea3101eS 1550dea3101eS #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1551dea3101eS iocb */ 1552dea3101eS #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1553dea3101eS /* 1554dea3101eS * Define Status 1555dea3101eS */ 1556dea3101eS #define MBX_SUCCESS 0 1557dea3101eS #define MBXERR_NUM_RINGS 1 1558dea3101eS #define MBXERR_NUM_IOCBS 2 1559dea3101eS #define MBXERR_IOCBS_EXCEEDED 3 1560dea3101eS #define MBXERR_BAD_RING_NUMBER 4 1561dea3101eS #define MBXERR_MASK_ENTRIES_RANGE 5 1562dea3101eS #define MBXERR_MASKS_EXCEEDED 6 1563dea3101eS #define MBXERR_BAD_PROFILE 7 1564dea3101eS #define MBXERR_BAD_DEF_CLASS 8 1565dea3101eS #define MBXERR_BAD_MAX_RESPONDER 9 1566dea3101eS #define MBXERR_BAD_MAX_ORIGINATOR 10 1567dea3101eS #define MBXERR_RPI_REGISTERED 11 1568dea3101eS #define MBXERR_RPI_FULL 12 1569dea3101eS #define MBXERR_NO_RESOURCES 13 1570dea3101eS #define MBXERR_BAD_RCV_LENGTH 14 1571dea3101eS #define MBXERR_DMA_ERROR 15 1572dea3101eS #define MBXERR_ERROR 16 1573da0436e9SJames Smart #define MBXERR_LINK_DOWN 0x33 1574dcf2a4e0SJames Smart #define MBXERR_SEC_NO_PERMISSION 0xF02 1575dea3101eS #define MBX_NOT_FINISHED 255 1576dea3101eS 1577dea3101eS #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1578dea3101eS #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1579dea3101eS 158057127f15SJames Smart #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 158157127f15SJames Smart 1582dea3101eS /* 1583dea3101eS * Begin Structure Definitions for Mailbox Commands 1584dea3101eS */ 1585dea3101eS 1586dea3101eS typedef struct { 1587dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1588dea3101eS uint8_t tval; 1589dea3101eS uint8_t tmask; 1590dea3101eS uint8_t rval; 1591dea3101eS uint8_t rmask; 1592dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1593dea3101eS uint8_t rmask; 1594dea3101eS uint8_t rval; 1595dea3101eS uint8_t tmask; 1596dea3101eS uint8_t tval; 1597dea3101eS #endif 1598dea3101eS } RR_REG; 1599dea3101eS 1600dea3101eS struct ulp_bde { 1601dea3101eS uint32_t bdeAddress; 1602dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1603dea3101eS uint32_t bdeReserved:4; 1604dea3101eS uint32_t bdeAddrHigh:4; 1605dea3101eS uint32_t bdeSize:24; 1606dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1607dea3101eS uint32_t bdeSize:24; 1608dea3101eS uint32_t bdeAddrHigh:4; 1609dea3101eS uint32_t bdeReserved:4; 1610dea3101eS #endif 1611dea3101eS }; 1612dea3101eS 1613dea3101eS typedef struct ULP_BDL { /* SLI-2 */ 1614dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1615dea3101eS uint32_t bdeFlags:8; /* BDL Flags */ 1616dea3101eS uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1617dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1618dea3101eS uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1619dea3101eS uint32_t bdeFlags:8; /* BDL Flags */ 1620dea3101eS #endif 1621dea3101eS 1622dea3101eS uint32_t addrLow; /* Address 0:31 */ 1623dea3101eS uint32_t addrHigh; /* Address 32:63 */ 1624dea3101eS uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1625dea3101eS } ULP_BDL; 1626dea3101eS 162781301a9bSJames Smart /* 162881301a9bSJames Smart * BlockGuard Definitions 162981301a9bSJames Smart */ 163081301a9bSJames Smart 163181301a9bSJames Smart enum lpfc_protgrp_type { 163281301a9bSJames Smart LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 163381301a9bSJames Smart LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 163481301a9bSJames Smart LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 163581301a9bSJames Smart LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 163681301a9bSJames Smart }; 163781301a9bSJames Smart 163881301a9bSJames Smart /* PDE Descriptors */ 16396c8eea54SJames Smart #define LPFC_PDE5_DESCRIPTOR 0x85 16406c8eea54SJames Smart #define LPFC_PDE6_DESCRIPTOR 0x86 16416c8eea54SJames Smart #define LPFC_PDE7_DESCRIPTOR 0x87 164281301a9bSJames Smart 16436c8eea54SJames Smart /* BlockGuard Opcodes */ 16446c8eea54SJames Smart #define BG_OP_IN_NODIF_OUT_CRC 0x0 16456c8eea54SJames Smart #define BG_OP_IN_CRC_OUT_NODIF 0x1 16466c8eea54SJames Smart #define BG_OP_IN_NODIF_OUT_CSUM 0x2 16476c8eea54SJames Smart #define BG_OP_IN_CSUM_OUT_NODIF 0x3 16486c8eea54SJames Smart #define BG_OP_IN_CRC_OUT_CRC 0x4 16496c8eea54SJames Smart #define BG_OP_IN_CSUM_OUT_CSUM 0x5 16506c8eea54SJames Smart #define BG_OP_IN_CRC_OUT_CSUM 0x6 16516c8eea54SJames Smart #define BG_OP_IN_CSUM_OUT_CRC 0x7 16526c8eea54SJames Smart 16536c8eea54SJames Smart struct lpfc_pde5 { 16546c8eea54SJames Smart uint32_t word0; 16556c8eea54SJames Smart #define pde5_type_SHIFT 24 16566c8eea54SJames Smart #define pde5_type_MASK 0x000000ff 16576c8eea54SJames Smart #define pde5_type_WORD word0 16586c8eea54SJames Smart #define pde5_rsvd0_SHIFT 0 16596c8eea54SJames Smart #define pde5_rsvd0_MASK 0x00ffffff 16606c8eea54SJames Smart #define pde5_rsvd0_WORD word0 16616c8eea54SJames Smart uint32_t reftag; /* Reference Tag Value */ 16626c8eea54SJames Smart uint32_t reftagtr; /* Reference Tag Translation Value */ 166381301a9bSJames Smart }; 166481301a9bSJames Smart 16656c8eea54SJames Smart struct lpfc_pde6 { 16666c8eea54SJames Smart uint32_t word0; 16676c8eea54SJames Smart #define pde6_type_SHIFT 24 16686c8eea54SJames Smart #define pde6_type_MASK 0x000000ff 16696c8eea54SJames Smart #define pde6_type_WORD word0 16706c8eea54SJames Smart #define pde6_rsvd0_SHIFT 0 16716c8eea54SJames Smart #define pde6_rsvd0_MASK 0x00ffffff 16726c8eea54SJames Smart #define pde6_rsvd0_WORD word0 16736c8eea54SJames Smart uint32_t word1; 16746c8eea54SJames Smart #define pde6_rsvd1_SHIFT 26 16756c8eea54SJames Smart #define pde6_rsvd1_MASK 0x0000003f 16766c8eea54SJames Smart #define pde6_rsvd1_WORD word1 16776c8eea54SJames Smart #define pde6_na_SHIFT 25 16786c8eea54SJames Smart #define pde6_na_MASK 0x00000001 16796c8eea54SJames Smart #define pde6_na_WORD word1 16806c8eea54SJames Smart #define pde6_rsvd2_SHIFT 16 16816c8eea54SJames Smart #define pde6_rsvd2_MASK 0x000001FF 16826c8eea54SJames Smart #define pde6_rsvd2_WORD word1 16836c8eea54SJames Smart #define pde6_apptagtr_SHIFT 0 16846c8eea54SJames Smart #define pde6_apptagtr_MASK 0x0000ffff 16856c8eea54SJames Smart #define pde6_apptagtr_WORD word1 16866c8eea54SJames Smart uint32_t word2; 16876c8eea54SJames Smart #define pde6_optx_SHIFT 28 16886c8eea54SJames Smart #define pde6_optx_MASK 0x0000000f 16896c8eea54SJames Smart #define pde6_optx_WORD word2 16906c8eea54SJames Smart #define pde6_oprx_SHIFT 24 16916c8eea54SJames Smart #define pde6_oprx_MASK 0x0000000f 16926c8eea54SJames Smart #define pde6_oprx_WORD word2 16936c8eea54SJames Smart #define pde6_nr_SHIFT 23 16946c8eea54SJames Smart #define pde6_nr_MASK 0x00000001 16956c8eea54SJames Smart #define pde6_nr_WORD word2 16966c8eea54SJames Smart #define pde6_ce_SHIFT 22 16976c8eea54SJames Smart #define pde6_ce_MASK 0x00000001 16986c8eea54SJames Smart #define pde6_ce_WORD word2 16996c8eea54SJames Smart #define pde6_re_SHIFT 21 17006c8eea54SJames Smart #define pde6_re_MASK 0x00000001 17016c8eea54SJames Smart #define pde6_re_WORD word2 17026c8eea54SJames Smart #define pde6_ae_SHIFT 20 17036c8eea54SJames Smart #define pde6_ae_MASK 0x00000001 17046c8eea54SJames Smart #define pde6_ae_WORD word2 17056c8eea54SJames Smart #define pde6_ai_SHIFT 19 17066c8eea54SJames Smart #define pde6_ai_MASK 0x00000001 17076c8eea54SJames Smart #define pde6_ai_WORD word2 17086c8eea54SJames Smart #define pde6_bs_SHIFT 16 17096c8eea54SJames Smart #define pde6_bs_MASK 0x00000007 17106c8eea54SJames Smart #define pde6_bs_WORD word2 17116c8eea54SJames Smart #define pde6_apptagval_SHIFT 0 17126c8eea54SJames Smart #define pde6_apptagval_MASK 0x0000ffff 17136c8eea54SJames Smart #define pde6_apptagval_WORD word2 171481301a9bSJames Smart }; 171581301a9bSJames Smart 171681301a9bSJames Smart 1717dea3101eS /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1718dea3101eS 1719dea3101eS typedef struct { 1720dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1721dea3101eS uint32_t rsvd2:25; 1722dea3101eS uint32_t acknowledgment:1; 1723dea3101eS uint32_t version:1; 1724dea3101eS uint32_t erase_or_prog:1; 1725dea3101eS uint32_t update_flash:1; 1726dea3101eS uint32_t update_ram:1; 1727dea3101eS uint32_t method:1; 1728dea3101eS uint32_t load_cmplt:1; 1729dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1730dea3101eS uint32_t load_cmplt:1; 1731dea3101eS uint32_t method:1; 1732dea3101eS uint32_t update_ram:1; 1733dea3101eS uint32_t update_flash:1; 1734dea3101eS uint32_t erase_or_prog:1; 1735dea3101eS uint32_t version:1; 1736dea3101eS uint32_t acknowledgment:1; 1737dea3101eS uint32_t rsvd2:25; 1738dea3101eS #endif 1739dea3101eS 1740dea3101eS uint32_t dl_to_adr_low; 1741dea3101eS uint32_t dl_to_adr_high; 1742dea3101eS uint32_t dl_len; 1743dea3101eS union { 1744dea3101eS uint32_t dl_from_mbx_offset; 1745dea3101eS struct ulp_bde dl_from_bde; 1746dea3101eS struct ulp_bde64 dl_from_bde64; 1747dea3101eS } un; 1748dea3101eS 1749dea3101eS } LOAD_SM_VAR; 1750dea3101eS 1751dea3101eS /* Structure for MB Command READ_NVPARM (02) */ 1752dea3101eS 1753dea3101eS typedef struct { 1754dea3101eS uint32_t rsvd1[3]; /* Read as all one's */ 1755dea3101eS uint32_t rsvd2; /* Read as all zero's */ 1756dea3101eS uint32_t portname[2]; /* N_PORT name */ 1757dea3101eS uint32_t nodename[2]; /* NODE name */ 1758dea3101eS 1759dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1760dea3101eS uint32_t pref_DID:24; 1761dea3101eS uint32_t hardAL_PA:8; 1762dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1763dea3101eS uint32_t hardAL_PA:8; 1764dea3101eS uint32_t pref_DID:24; 1765dea3101eS #endif 1766dea3101eS 1767dea3101eS uint32_t rsvd3[21]; /* Read as all one's */ 1768dea3101eS } READ_NV_VAR; 1769dea3101eS 1770dea3101eS /* Structure for MB Command WRITE_NVPARMS (03) */ 1771dea3101eS 1772dea3101eS typedef struct { 1773dea3101eS uint32_t rsvd1[3]; /* Must be all one's */ 1774dea3101eS uint32_t rsvd2; /* Must be all zero's */ 1775dea3101eS uint32_t portname[2]; /* N_PORT name */ 1776dea3101eS uint32_t nodename[2]; /* NODE name */ 1777dea3101eS 1778dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1779dea3101eS uint32_t pref_DID:24; 1780dea3101eS uint32_t hardAL_PA:8; 1781dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1782dea3101eS uint32_t hardAL_PA:8; 1783dea3101eS uint32_t pref_DID:24; 1784dea3101eS #endif 1785dea3101eS 1786dea3101eS uint32_t rsvd3[21]; /* Must be all one's */ 1787dea3101eS } WRITE_NV_VAR; 1788dea3101eS 1789dea3101eS /* Structure for MB Command RUN_BIU_DIAG (04) */ 1790dea3101eS /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1791dea3101eS 1792dea3101eS typedef struct { 1793dea3101eS uint32_t rsvd1; 1794dea3101eS union { 1795dea3101eS struct { 1796dea3101eS struct ulp_bde xmit_bde; 1797dea3101eS struct ulp_bde rcv_bde; 1798dea3101eS } s1; 1799dea3101eS struct { 1800dea3101eS struct ulp_bde64 xmit_bde64; 1801dea3101eS struct ulp_bde64 rcv_bde64; 1802dea3101eS } s2; 1803dea3101eS } un; 1804dea3101eS } BIU_DIAG_VAR; 1805dea3101eS 1806c7495937SJames Smart /* Structure for MB command READ_EVENT_LOG (0x38) */ 1807c7495937SJames Smart struct READ_EVENT_LOG_VAR { 1808c7495937SJames Smart uint32_t word1; 1809c7495937SJames Smart #define lpfc_event_log_SHIFT 29 1810c7495937SJames Smart #define lpfc_event_log_MASK 0x00000001 1811c7495937SJames Smart #define lpfc_event_log_WORD word1 1812c7495937SJames Smart #define USE_MAILBOX_RESPONSE 1 1813c7495937SJames Smart uint32_t offset; 1814c7495937SJames Smart struct ulp_bde64 rcv_bde64; 1815c7495937SJames Smart }; 1816c7495937SJames Smart 1817dea3101eS /* Structure for MB Command INIT_LINK (05) */ 1818dea3101eS 1819dea3101eS typedef struct { 1820dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1821dea3101eS uint32_t rsvd1:24; 1822dea3101eS uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1823dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1824dea3101eS uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1825dea3101eS uint32_t rsvd1:24; 1826dea3101eS #endif 1827dea3101eS 1828dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1829dea3101eS uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1830dea3101eS uint8_t rsvd2; 1831dea3101eS uint16_t link_flags; 1832dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1833dea3101eS uint16_t link_flags; 1834dea3101eS uint8_t rsvd2; 1835dea3101eS uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1836dea3101eS #endif 1837dea3101eS 1838dea3101eS #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1839dea3101eS #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1840dea3101eS #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1841dea3101eS #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1842dea3101eS #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1843ed957684SJames Smart #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 1844dea3101eS #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1845dea3101eS 1846dea3101eS #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1847dea3101eS #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 18484b0b91d4SJames Smart #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 1849dea3101eS 1850dea3101eS uint32_t link_speed; 185176a95d75SJames Smart #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 185276a95d75SJames Smart #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 185376a95d75SJames Smart #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 185476a95d75SJames Smart #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 185576a95d75SJames Smart #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 185676a95d75SJames Smart #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 185776a95d75SJames Smart #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 1858dea3101eS 1859dea3101eS } INIT_LINK_VAR; 1860dea3101eS 1861dea3101eS /* Structure for MB Command DOWN_LINK (06) */ 1862dea3101eS 1863dea3101eS typedef struct { 1864dea3101eS uint32_t rsvd1; 1865dea3101eS } DOWN_LINK_VAR; 1866dea3101eS 1867dea3101eS /* Structure for MB Command CONFIG_LINK (07) */ 1868dea3101eS 1869dea3101eS typedef struct { 1870dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1871dea3101eS uint32_t cr:1; 1872dea3101eS uint32_t ci:1; 1873dea3101eS uint32_t cr_delay:6; 1874dea3101eS uint32_t cr_count:8; 1875dea3101eS uint32_t rsvd1:8; 1876dea3101eS uint32_t MaxBBC:8; 1877dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1878dea3101eS uint32_t MaxBBC:8; 1879dea3101eS uint32_t rsvd1:8; 1880dea3101eS uint32_t cr_count:8; 1881dea3101eS uint32_t cr_delay:6; 1882dea3101eS uint32_t ci:1; 1883dea3101eS uint32_t cr:1; 1884dea3101eS #endif 1885dea3101eS 1886dea3101eS uint32_t myId; 1887dea3101eS uint32_t rsvd2; 1888dea3101eS uint32_t edtov; 1889dea3101eS uint32_t arbtov; 1890dea3101eS uint32_t ratov; 1891dea3101eS uint32_t rttov; 1892dea3101eS uint32_t altov; 1893dea3101eS uint32_t crtov; 1894dea3101eS uint32_t citov; 1895dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1896dea3101eS uint32_t rrq_enable:1; 1897dea3101eS uint32_t rrq_immed:1; 1898dea3101eS uint32_t rsvd4:29; 1899dea3101eS uint32_t ack0_enable:1; 1900dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1901dea3101eS uint32_t ack0_enable:1; 1902dea3101eS uint32_t rsvd4:29; 1903dea3101eS uint32_t rrq_immed:1; 1904dea3101eS uint32_t rrq_enable:1; 1905dea3101eS #endif 1906dea3101eS } CONFIG_LINK; 1907dea3101eS 1908dea3101eS /* Structure for MB Command PART_SLIM (08) 1909dea3101eS * will be removed since SLI1 is no longer supported! 1910dea3101eS */ 1911dea3101eS typedef struct { 1912dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1913dea3101eS uint16_t offCiocb; 1914dea3101eS uint16_t numCiocb; 1915dea3101eS uint16_t offRiocb; 1916dea3101eS uint16_t numRiocb; 1917dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1918dea3101eS uint16_t numCiocb; 1919dea3101eS uint16_t offCiocb; 1920dea3101eS uint16_t numRiocb; 1921dea3101eS uint16_t offRiocb; 1922dea3101eS #endif 1923dea3101eS } RING_DEF; 1924dea3101eS 1925dea3101eS typedef struct { 1926dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1927dea3101eS uint32_t unused1:24; 1928dea3101eS uint32_t numRing:8; 1929dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1930dea3101eS uint32_t numRing:8; 1931dea3101eS uint32_t unused1:24; 1932dea3101eS #endif 1933dea3101eS 1934dea3101eS RING_DEF ringdef[4]; 1935dea3101eS uint32_t hbainit; 1936dea3101eS } PART_SLIM_VAR; 1937dea3101eS 1938dea3101eS /* Structure for MB Command CONFIG_RING (09) */ 1939dea3101eS 1940dea3101eS typedef struct { 1941dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1942dea3101eS uint32_t unused2:6; 1943dea3101eS uint32_t recvSeq:1; 1944dea3101eS uint32_t recvNotify:1; 1945dea3101eS uint32_t numMask:8; 1946dea3101eS uint32_t profile:8; 1947dea3101eS uint32_t unused1:4; 1948dea3101eS uint32_t ring:4; 1949dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1950dea3101eS uint32_t ring:4; 1951dea3101eS uint32_t unused1:4; 1952dea3101eS uint32_t profile:8; 1953dea3101eS uint32_t numMask:8; 1954dea3101eS uint32_t recvNotify:1; 1955dea3101eS uint32_t recvSeq:1; 1956dea3101eS uint32_t unused2:6; 1957dea3101eS #endif 1958dea3101eS 1959dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1960dea3101eS uint16_t maxRespXchg; 1961dea3101eS uint16_t maxOrigXchg; 1962dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1963dea3101eS uint16_t maxOrigXchg; 1964dea3101eS uint16_t maxRespXchg; 1965dea3101eS #endif 1966dea3101eS 1967dea3101eS RR_REG rrRegs[6]; 1968dea3101eS } CONFIG_RING_VAR; 1969dea3101eS 1970dea3101eS /* Structure for MB Command RESET_RING (10) */ 1971dea3101eS 1972dea3101eS typedef struct { 1973dea3101eS uint32_t ring_no; 1974dea3101eS } RESET_RING_VAR; 1975dea3101eS 1976dea3101eS /* Structure for MB Command READ_CONFIG (11) */ 1977dea3101eS 1978dea3101eS typedef struct { 1979dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1980dea3101eS uint32_t cr:1; 1981dea3101eS uint32_t ci:1; 1982dea3101eS uint32_t cr_delay:6; 1983dea3101eS uint32_t cr_count:8; 1984dea3101eS uint32_t InitBBC:8; 1985dea3101eS uint32_t MaxBBC:8; 1986dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1987dea3101eS uint32_t MaxBBC:8; 1988dea3101eS uint32_t InitBBC:8; 1989dea3101eS uint32_t cr_count:8; 1990dea3101eS uint32_t cr_delay:6; 1991dea3101eS uint32_t ci:1; 1992dea3101eS uint32_t cr:1; 1993dea3101eS #endif 1994dea3101eS 1995dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 1996dea3101eS uint32_t topology:8; 1997dea3101eS uint32_t myDid:24; 1998dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 1999dea3101eS uint32_t myDid:24; 2000dea3101eS uint32_t topology:8; 2001dea3101eS #endif 2002dea3101eS 2003dea3101eS /* Defines for topology (defined previously) */ 2004dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2005dea3101eS uint32_t AR:1; 2006dea3101eS uint32_t IR:1; 2007dea3101eS uint32_t rsvd1:29; 2008dea3101eS uint32_t ack0:1; 2009dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2010dea3101eS uint32_t ack0:1; 2011dea3101eS uint32_t rsvd1:29; 2012dea3101eS uint32_t IR:1; 2013dea3101eS uint32_t AR:1; 2014dea3101eS #endif 2015dea3101eS 2016dea3101eS uint32_t edtov; 2017dea3101eS uint32_t arbtov; 2018dea3101eS uint32_t ratov; 2019dea3101eS uint32_t rttov; 2020dea3101eS uint32_t altov; 2021dea3101eS uint32_t lmt; 202274b72a59SJamie Wellnitz #define LMT_RESERVED 0x000 /* Not used */ 202374b72a59SJamie Wellnitz #define LMT_1Gb 0x004 202474b72a59SJamie Wellnitz #define LMT_2Gb 0x008 202574b72a59SJamie Wellnitz #define LMT_4Gb 0x040 202674b72a59SJamie Wellnitz #define LMT_8Gb 0x080 202774b72a59SJamie Wellnitz #define LMT_10Gb 0x100 202876a95d75SJames Smart #define LMT_16Gb 0x200 2029dea3101eS uint32_t rsvd2; 2030dea3101eS uint32_t rsvd3; 2031dea3101eS uint32_t max_xri; 2032dea3101eS uint32_t max_iocb; 2033dea3101eS uint32_t max_rpi; 2034dea3101eS uint32_t avail_xri; 2035dea3101eS uint32_t avail_iocb; 2036dea3101eS uint32_t avail_rpi; 2037858c9f6cSJames Smart uint32_t max_vpi; 2038858c9f6cSJames Smart uint32_t rsvd4; 2039858c9f6cSJames Smart uint32_t rsvd5; 2040858c9f6cSJames Smart uint32_t avail_vpi; 2041dea3101eS } READ_CONFIG_VAR; 2042dea3101eS 2043dea3101eS /* Structure for MB Command READ_RCONFIG (12) */ 2044dea3101eS 2045dea3101eS typedef struct { 2046dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2047dea3101eS uint32_t rsvd2:7; 2048dea3101eS uint32_t recvNotify:1; 2049dea3101eS uint32_t numMask:8; 2050dea3101eS uint32_t profile:8; 2051dea3101eS uint32_t rsvd1:4; 2052dea3101eS uint32_t ring:4; 2053dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2054dea3101eS uint32_t ring:4; 2055dea3101eS uint32_t rsvd1:4; 2056dea3101eS uint32_t profile:8; 2057dea3101eS uint32_t numMask:8; 2058dea3101eS uint32_t recvNotify:1; 2059dea3101eS uint32_t rsvd2:7; 2060dea3101eS #endif 2061dea3101eS 2062dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2063dea3101eS uint16_t maxResp; 2064dea3101eS uint16_t maxOrig; 2065dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2066dea3101eS uint16_t maxOrig; 2067dea3101eS uint16_t maxResp; 2068dea3101eS #endif 2069dea3101eS 2070dea3101eS RR_REG rrRegs[6]; 2071dea3101eS 2072dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2073dea3101eS uint16_t cmdRingOffset; 2074dea3101eS uint16_t cmdEntryCnt; 2075dea3101eS uint16_t rspRingOffset; 2076dea3101eS uint16_t rspEntryCnt; 2077dea3101eS uint16_t nextCmdOffset; 2078dea3101eS uint16_t rsvd3; 2079dea3101eS uint16_t nextRspOffset; 2080dea3101eS uint16_t rsvd4; 2081dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2082dea3101eS uint16_t cmdEntryCnt; 2083dea3101eS uint16_t cmdRingOffset; 2084dea3101eS uint16_t rspEntryCnt; 2085dea3101eS uint16_t rspRingOffset; 2086dea3101eS uint16_t rsvd3; 2087dea3101eS uint16_t nextCmdOffset; 2088dea3101eS uint16_t rsvd4; 2089dea3101eS uint16_t nextRspOffset; 2090dea3101eS #endif 2091dea3101eS } READ_RCONF_VAR; 2092dea3101eS 2093dea3101eS /* Structure for MB Command READ_SPARM (13) */ 2094dea3101eS /* Structure for MB Command READ_SPARM64 (0x8D) */ 2095dea3101eS 2096dea3101eS typedef struct { 2097dea3101eS uint32_t rsvd1; 2098dea3101eS uint32_t rsvd2; 2099dea3101eS union { 2100dea3101eS struct ulp_bde sp; /* This BDE points to struct serv_parm 2101dea3101eS structure */ 2102dea3101eS struct ulp_bde64 sp64; 2103dea3101eS } un; 2104ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2105ed957684SJames Smart uint16_t rsvd3; 2106ed957684SJames Smart uint16_t vpi; 2107ed957684SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 2108ed957684SJames Smart uint16_t vpi; 2109ed957684SJames Smart uint16_t rsvd3; 2110ed957684SJames Smart #endif 2111dea3101eS } READ_SPARM_VAR; 2112dea3101eS 2113dea3101eS /* Structure for MB Command READ_STATUS (14) */ 2114dea3101eS 2115dea3101eS typedef struct { 2116dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2117dea3101eS uint32_t rsvd1:31; 2118dea3101eS uint32_t clrCounters:1; 2119dea3101eS uint16_t activeXriCnt; 2120dea3101eS uint16_t activeRpiCnt; 2121dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2122dea3101eS uint32_t clrCounters:1; 2123dea3101eS uint32_t rsvd1:31; 2124dea3101eS uint16_t activeRpiCnt; 2125dea3101eS uint16_t activeXriCnt; 2126dea3101eS #endif 2127dea3101eS 2128dea3101eS uint32_t xmitByteCnt; 2129dea3101eS uint32_t rcvByteCnt; 2130dea3101eS uint32_t xmitFrameCnt; 2131dea3101eS uint32_t rcvFrameCnt; 2132dea3101eS uint32_t xmitSeqCnt; 2133dea3101eS uint32_t rcvSeqCnt; 2134dea3101eS uint32_t totalOrigExchanges; 2135dea3101eS uint32_t totalRespExchanges; 2136dea3101eS uint32_t rcvPbsyCnt; 2137dea3101eS uint32_t rcvFbsyCnt; 2138dea3101eS } READ_STATUS_VAR; 2139dea3101eS 2140dea3101eS /* Structure for MB Command READ_RPI (15) */ 2141dea3101eS /* Structure for MB Command READ_RPI64 (0x8F) */ 2142dea3101eS 2143dea3101eS typedef struct { 2144dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2145dea3101eS uint16_t nextRpi; 2146dea3101eS uint16_t reqRpi; 2147dea3101eS uint32_t rsvd2:8; 2148dea3101eS uint32_t DID:24; 2149dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2150dea3101eS uint16_t reqRpi; 2151dea3101eS uint16_t nextRpi; 2152dea3101eS uint32_t DID:24; 2153dea3101eS uint32_t rsvd2:8; 2154dea3101eS #endif 2155dea3101eS 2156dea3101eS union { 2157dea3101eS struct ulp_bde sp; 2158dea3101eS struct ulp_bde64 sp64; 2159dea3101eS } un; 2160dea3101eS 2161dea3101eS } READ_RPI_VAR; 2162dea3101eS 2163dea3101eS /* Structure for MB Command READ_XRI (16) */ 2164dea3101eS 2165dea3101eS typedef struct { 2166dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2167dea3101eS uint16_t nextXri; 2168dea3101eS uint16_t reqXri; 2169dea3101eS uint16_t rsvd1; 2170dea3101eS uint16_t rpi; 2171dea3101eS uint32_t rsvd2:8; 2172dea3101eS uint32_t DID:24; 2173dea3101eS uint32_t rsvd3:8; 2174dea3101eS uint32_t SID:24; 2175dea3101eS uint32_t rsvd4; 2176dea3101eS uint8_t seqId; 2177dea3101eS uint8_t rsvd5; 2178dea3101eS uint16_t seqCount; 2179dea3101eS uint16_t oxId; 2180dea3101eS uint16_t rxId; 2181dea3101eS uint32_t rsvd6:30; 2182dea3101eS uint32_t si:1; 2183dea3101eS uint32_t exchOrig:1; 2184dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2185dea3101eS uint16_t reqXri; 2186dea3101eS uint16_t nextXri; 2187dea3101eS uint16_t rpi; 2188dea3101eS uint16_t rsvd1; 2189dea3101eS uint32_t DID:24; 2190dea3101eS uint32_t rsvd2:8; 2191dea3101eS uint32_t SID:24; 2192dea3101eS uint32_t rsvd3:8; 2193dea3101eS uint32_t rsvd4; 2194dea3101eS uint16_t seqCount; 2195dea3101eS uint8_t rsvd5; 2196dea3101eS uint8_t seqId; 2197dea3101eS uint16_t rxId; 2198dea3101eS uint16_t oxId; 2199dea3101eS uint32_t exchOrig:1; 2200dea3101eS uint32_t si:1; 2201dea3101eS uint32_t rsvd6:30; 2202dea3101eS #endif 2203dea3101eS } READ_XRI_VAR; 2204dea3101eS 2205dea3101eS /* Structure for MB Command READ_REV (17) */ 2206dea3101eS 2207dea3101eS typedef struct { 2208dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2209dea3101eS uint32_t cv:1; 2210dea3101eS uint32_t rr:1; 2211ed957684SJames Smart uint32_t rsvd2:2; 2212ed957684SJames Smart uint32_t v3req:1; 2213ed957684SJames Smart uint32_t v3rsp:1; 2214ed957684SJames Smart uint32_t rsvd1:25; 2215dea3101eS uint32_t rv:1; 2216dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2217dea3101eS uint32_t rv:1; 2218ed957684SJames Smart uint32_t rsvd1:25; 2219ed957684SJames Smart uint32_t v3rsp:1; 2220ed957684SJames Smart uint32_t v3req:1; 2221ed957684SJames Smart uint32_t rsvd2:2; 2222dea3101eS uint32_t rr:1; 2223dea3101eS uint32_t cv:1; 2224dea3101eS #endif 2225dea3101eS 2226dea3101eS uint32_t biuRev; 2227dea3101eS uint32_t smRev; 2228dea3101eS union { 2229dea3101eS uint32_t smFwRev; 2230dea3101eS struct { 2231dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2232dea3101eS uint8_t ProgType; 2233dea3101eS uint8_t ProgId; 2234dea3101eS uint16_t ProgVer:4; 2235dea3101eS uint16_t ProgRev:4; 2236dea3101eS uint16_t ProgFixLvl:2; 2237dea3101eS uint16_t ProgDistType:2; 2238dea3101eS uint16_t DistCnt:4; 2239dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2240dea3101eS uint16_t DistCnt:4; 2241dea3101eS uint16_t ProgDistType:2; 2242dea3101eS uint16_t ProgFixLvl:2; 2243dea3101eS uint16_t ProgRev:4; 2244dea3101eS uint16_t ProgVer:4; 2245dea3101eS uint8_t ProgId; 2246dea3101eS uint8_t ProgType; 2247dea3101eS #endif 2248dea3101eS 2249dea3101eS } b; 2250dea3101eS } un; 2251dea3101eS uint32_t endecRev; 2252dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2253dea3101eS uint8_t feaLevelHigh; 2254dea3101eS uint8_t feaLevelLow; 2255dea3101eS uint8_t fcphHigh; 2256dea3101eS uint8_t fcphLow; 2257dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2258dea3101eS uint8_t fcphLow; 2259dea3101eS uint8_t fcphHigh; 2260dea3101eS uint8_t feaLevelLow; 2261dea3101eS uint8_t feaLevelHigh; 2262dea3101eS #endif 2263dea3101eS 2264dea3101eS uint32_t postKernRev; 2265dea3101eS uint32_t opFwRev; 2266dea3101eS uint8_t opFwName[16]; 2267dea3101eS uint32_t sli1FwRev; 2268dea3101eS uint8_t sli1FwName[16]; 2269dea3101eS uint32_t sli2FwRev; 2270dea3101eS uint8_t sli2FwName[16]; 2271ed957684SJames Smart uint32_t sli3Feat; 2272ed957684SJames Smart uint32_t RandomData[6]; 2273dea3101eS } READ_REV_VAR; 2274dea3101eS 2275dea3101eS /* Structure for MB Command READ_LINK_STAT (18) */ 2276dea3101eS 2277dea3101eS typedef struct { 2278dea3101eS uint32_t rsvd1; 2279dea3101eS uint32_t linkFailureCnt; 2280dea3101eS uint32_t lossSyncCnt; 2281dea3101eS 2282dea3101eS uint32_t lossSignalCnt; 2283dea3101eS uint32_t primSeqErrCnt; 2284dea3101eS uint32_t invalidXmitWord; 2285dea3101eS uint32_t crcCnt; 2286dea3101eS uint32_t primSeqTimeout; 2287dea3101eS uint32_t elasticOverrun; 2288dea3101eS uint32_t arbTimeout; 2289dea3101eS } READ_LNK_VAR; 2290dea3101eS 2291dea3101eS /* Structure for MB Command REG_LOGIN (19) */ 2292dea3101eS /* Structure for MB Command REG_LOGIN64 (0x93) */ 2293dea3101eS 2294dea3101eS typedef struct { 2295dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2296dea3101eS uint16_t rsvd1; 2297dea3101eS uint16_t rpi; 2298dea3101eS uint32_t rsvd2:8; 2299dea3101eS uint32_t did:24; 2300dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2301dea3101eS uint16_t rpi; 2302dea3101eS uint16_t rsvd1; 2303dea3101eS uint32_t did:24; 2304dea3101eS uint32_t rsvd2:8; 2305dea3101eS #endif 2306dea3101eS 2307dea3101eS union { 2308dea3101eS struct ulp_bde sp; 2309dea3101eS struct ulp_bde64 sp64; 2310dea3101eS } un; 2311dea3101eS 2312ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2313ed957684SJames Smart uint16_t rsvd6; 2314ed957684SJames Smart uint16_t vpi; 2315ed957684SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 2316ed957684SJames Smart uint16_t vpi; 2317ed957684SJames Smart uint16_t rsvd6; 2318ed957684SJames Smart #endif 2319ed957684SJames Smart 2320dea3101eS } REG_LOGIN_VAR; 2321dea3101eS 2322dea3101eS /* Word 30 contents for REG_LOGIN */ 2323dea3101eS typedef union { 2324dea3101eS struct { 2325dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2326dea3101eS uint16_t rsvd1:12; 2327dea3101eS uint16_t wd30_class:4; 2328dea3101eS uint16_t xri; 2329dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2330dea3101eS uint16_t xri; 2331dea3101eS uint16_t wd30_class:4; 2332dea3101eS uint16_t rsvd1:12; 2333dea3101eS #endif 2334dea3101eS } f; 2335dea3101eS uint32_t word; 2336dea3101eS } REG_WD30; 2337dea3101eS 2338dea3101eS /* Structure for MB Command UNREG_LOGIN (20) */ 2339dea3101eS 2340dea3101eS typedef struct { 2341dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2342dea3101eS uint16_t rsvd1; 2343dea3101eS uint16_t rpi; 2344ed957684SJames Smart uint32_t rsvd2; 2345ed957684SJames Smart uint32_t rsvd3; 2346ed957684SJames Smart uint32_t rsvd4; 2347ed957684SJames Smart uint32_t rsvd5; 2348ed957684SJames Smart uint16_t rsvd6; 2349ed957684SJames Smart uint16_t vpi; 2350dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2351dea3101eS uint16_t rpi; 2352dea3101eS uint16_t rsvd1; 2353ed957684SJames Smart uint32_t rsvd2; 2354ed957684SJames Smart uint32_t rsvd3; 2355ed957684SJames Smart uint32_t rsvd4; 2356ed957684SJames Smart uint32_t rsvd5; 2357ed957684SJames Smart uint16_t vpi; 2358ed957684SJames Smart uint16_t rsvd6; 2359dea3101eS #endif 2360dea3101eS } UNREG_LOGIN_VAR; 2361dea3101eS 236292d7f7b0SJames Smart /* Structure for MB Command REG_VPI (0x96) */ 236392d7f7b0SJames Smart typedef struct { 236492d7f7b0SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 236592d7f7b0SJames Smart uint32_t rsvd1; 236638b92ef8SJames Smart uint32_t rsvd2:7; 236738b92ef8SJames Smart uint32_t upd:1; 236892d7f7b0SJames Smart uint32_t sid:24; 2369c868595dSJames Smart uint32_t wwn[2]; 237092d7f7b0SJames Smart uint32_t rsvd5; 2371da0436e9SJames Smart uint16_t vfi; 237292d7f7b0SJames Smart uint16_t vpi; 237392d7f7b0SJames Smart #else /* __LITTLE_ENDIAN */ 237492d7f7b0SJames Smart uint32_t rsvd1; 237592d7f7b0SJames Smart uint32_t sid:24; 237638b92ef8SJames Smart uint32_t upd:1; 237738b92ef8SJames Smart uint32_t rsvd2:7; 2378c868595dSJames Smart uint32_t wwn[2]; 237992d7f7b0SJames Smart uint32_t rsvd5; 238092d7f7b0SJames Smart uint16_t vpi; 2381da0436e9SJames Smart uint16_t vfi; 238292d7f7b0SJames Smart #endif 238392d7f7b0SJames Smart } REG_VPI_VAR; 238492d7f7b0SJames Smart 238592d7f7b0SJames Smart /* Structure for MB Command UNREG_VPI (0x97) */ 238692d7f7b0SJames Smart typedef struct { 238792d7f7b0SJames Smart uint32_t rsvd1; 23886669f9bbSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 23896669f9bbSJames Smart uint16_t rsvd2; 23906669f9bbSJames Smart uint16_t sli4_vpi; 23916669f9bbSJames Smart #else /* __LITTLE_ENDIAN */ 23926669f9bbSJames Smart uint16_t sli4_vpi; 23936669f9bbSJames Smart uint16_t rsvd2; 23946669f9bbSJames Smart #endif 239592d7f7b0SJames Smart uint32_t rsvd3; 239692d7f7b0SJames Smart uint32_t rsvd4; 239792d7f7b0SJames Smart uint32_t rsvd5; 239892d7f7b0SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 239992d7f7b0SJames Smart uint16_t rsvd6; 240092d7f7b0SJames Smart uint16_t vpi; 240192d7f7b0SJames Smart #else /* __LITTLE_ENDIAN */ 240292d7f7b0SJames Smart uint16_t vpi; 240392d7f7b0SJames Smart uint16_t rsvd6; 240492d7f7b0SJames Smart #endif 240592d7f7b0SJames Smart } UNREG_VPI_VAR; 240692d7f7b0SJames Smart 2407dea3101eS /* Structure for MB Command UNREG_D_ID (0x23) */ 2408dea3101eS 2409dea3101eS typedef struct { 2410dea3101eS uint32_t did; 2411ed957684SJames Smart uint32_t rsvd2; 2412ed957684SJames Smart uint32_t rsvd3; 2413ed957684SJames Smart uint32_t rsvd4; 2414ed957684SJames Smart uint32_t rsvd5; 2415ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2416ed957684SJames Smart uint16_t rsvd6; 2417ed957684SJames Smart uint16_t vpi; 2418ed957684SJames Smart #else 2419ed957684SJames Smart uint16_t vpi; 2420ed957684SJames Smart uint16_t rsvd6; 2421ed957684SJames Smart #endif 2422dea3101eS } UNREG_D_ID_VAR; 2423dea3101eS 242476a95d75SJames Smart /* Structure for MB Command READ_TOPOLOGY (0x95) */ 242576a95d75SJames Smart struct lpfc_mbx_read_top { 2426dea3101eS uint32_t eventTag; /* Event tag */ 242776a95d75SJames Smart uint32_t word2; 242876a95d75SJames Smart #define lpfc_mbx_read_top_fa_SHIFT 12 242976a95d75SJames Smart #define lpfc_mbx_read_top_fa_MASK 0x00000001 243076a95d75SJames Smart #define lpfc_mbx_read_top_fa_WORD word2 243176a95d75SJames Smart #define lpfc_mbx_read_top_mm_SHIFT 11 243276a95d75SJames Smart #define lpfc_mbx_read_top_mm_MASK 0x00000001 243376a95d75SJames Smart #define lpfc_mbx_read_top_mm_WORD word2 243476a95d75SJames Smart #define lpfc_mbx_read_top_pb_SHIFT 9 243576a95d75SJames Smart #define lpfc_mbx_read_top_pb_MASK 0X00000001 243676a95d75SJames Smart #define lpfc_mbx_read_top_pb_WORD word2 243776a95d75SJames Smart #define lpfc_mbx_read_top_il_SHIFT 8 243876a95d75SJames Smart #define lpfc_mbx_read_top_il_MASK 0x00000001 243976a95d75SJames Smart #define lpfc_mbx_read_top_il_WORD word2 244076a95d75SJames Smart #define lpfc_mbx_read_top_att_type_SHIFT 0 244176a95d75SJames Smart #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 244276a95d75SJames Smart #define lpfc_mbx_read_top_att_type_WORD word2 244376a95d75SJames Smart #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 244476a95d75SJames Smart #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 244576a95d75SJames Smart #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 244676a95d75SJames Smart uint32_t word3; 244776a95d75SJames Smart #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 244876a95d75SJames Smart #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 244976a95d75SJames Smart #define lpfc_mbx_read_top_alpa_granted_WORD word3 245076a95d75SJames Smart #define lpfc_mbx_read_top_lip_alps_SHIFT 16 245176a95d75SJames Smart #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 245276a95d75SJames Smart #define lpfc_mbx_read_top_lip_alps_WORD word3 245376a95d75SJames Smart #define lpfc_mbx_read_top_lip_type_SHIFT 8 245476a95d75SJames Smart #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 245576a95d75SJames Smart #define lpfc_mbx_read_top_lip_type_WORD word3 245676a95d75SJames Smart #define lpfc_mbx_read_top_topology_SHIFT 0 245776a95d75SJames Smart #define lpfc_mbx_read_top_topology_MASK 0x000000FF 245876a95d75SJames Smart #define lpfc_mbx_read_top_topology_WORD word3 245976a95d75SJames Smart #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 246076a95d75SJames Smart #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 246176a95d75SJames Smart #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ 2462dea3101eS /* store the LILP AL_PA position map into */ 2463dea3101eS struct ulp_bde64 lilpBde64; 246476a95d75SJames Smart #define LPFC_ALPA_MAP_SIZE 128 246576a95d75SJames Smart uint32_t word7; 246676a95d75SJames Smart #define lpfc_mbx_read_top_ld_lu_SHIFT 31 246776a95d75SJames Smart #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 246876a95d75SJames Smart #define lpfc_mbx_read_top_ld_lu_WORD word7 246976a95d75SJames Smart #define lpfc_mbx_read_top_ld_tf_SHIFT 30 247076a95d75SJames Smart #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 247176a95d75SJames Smart #define lpfc_mbx_read_top_ld_tf_WORD word7 247276a95d75SJames Smart #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 247376a95d75SJames Smart #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 247476a95d75SJames Smart #define lpfc_mbx_read_top_ld_link_spd_WORD word7 247576a95d75SJames Smart #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 247676a95d75SJames Smart #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 247776a95d75SJames Smart #define lpfc_mbx_read_top_ld_nl_port_WORD word7 247876a95d75SJames Smart #define lpfc_mbx_read_top_ld_tx_SHIFT 2 247976a95d75SJames Smart #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 248076a95d75SJames Smart #define lpfc_mbx_read_top_ld_tx_WORD word7 248176a95d75SJames Smart #define lpfc_mbx_read_top_ld_rx_SHIFT 0 248276a95d75SJames Smart #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 248376a95d75SJames Smart #define lpfc_mbx_read_top_ld_rx_WORD word7 248476a95d75SJames Smart uint32_t word8; 248576a95d75SJames Smart #define lpfc_mbx_read_top_lu_SHIFT 31 248676a95d75SJames Smart #define lpfc_mbx_read_top_lu_MASK 0x00000001 248776a95d75SJames Smart #define lpfc_mbx_read_top_lu_WORD word8 248876a95d75SJames Smart #define lpfc_mbx_read_top_tf_SHIFT 30 248976a95d75SJames Smart #define lpfc_mbx_read_top_tf_MASK 0x00000001 249076a95d75SJames Smart #define lpfc_mbx_read_top_tf_WORD word8 249176a95d75SJames Smart #define lpfc_mbx_read_top_link_spd_SHIFT 8 249276a95d75SJames Smart #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 249376a95d75SJames Smart #define lpfc_mbx_read_top_link_spd_WORD word8 249476a95d75SJames Smart #define lpfc_mbx_read_top_nl_port_SHIFT 4 249576a95d75SJames Smart #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 249676a95d75SJames Smart #define lpfc_mbx_read_top_nl_port_WORD word8 249776a95d75SJames Smart #define lpfc_mbx_read_top_tx_SHIFT 2 249876a95d75SJames Smart #define lpfc_mbx_read_top_tx_MASK 0x00000003 249976a95d75SJames Smart #define lpfc_mbx_read_top_tx_WORD word8 250076a95d75SJames Smart #define lpfc_mbx_read_top_rx_SHIFT 0 250176a95d75SJames Smart #define lpfc_mbx_read_top_rx_MASK 0x00000003 250276a95d75SJames Smart #define lpfc_mbx_read_top_rx_WORD word8 250376a95d75SJames Smart #define LPFC_LINK_SPEED_UNKNOWN 0x0 250476a95d75SJames Smart #define LPFC_LINK_SPEED_1GHZ 0x04 250576a95d75SJames Smart #define LPFC_LINK_SPEED_2GHZ 0x08 250676a95d75SJames Smart #define LPFC_LINK_SPEED_4GHZ 0x10 250776a95d75SJames Smart #define LPFC_LINK_SPEED_8GHZ 0x20 250876a95d75SJames Smart #define LPFC_LINK_SPEED_10GHZ 0x40 250976a95d75SJames Smart #define LPFC_LINK_SPEED_16GHZ 0x80 251076a95d75SJames Smart }; 2511dea3101eS 2512dea3101eS /* Structure for MB Command CLEAR_LA (22) */ 2513dea3101eS 2514dea3101eS typedef struct { 2515dea3101eS uint32_t eventTag; /* Event tag */ 2516dea3101eS uint32_t rsvd1; 2517dea3101eS } CLEAR_LA_VAR; 2518dea3101eS 2519dea3101eS /* Structure for MB Command DUMP */ 2520dea3101eS 2521dea3101eS typedef struct { 2522dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2523dea3101eS uint32_t rsvd:25; 2524dea3101eS uint32_t ra:1; 2525dea3101eS uint32_t co:1; 2526dea3101eS uint32_t cv:1; 2527dea3101eS uint32_t type:4; 2528dea3101eS uint32_t entry_index:16; 2529dea3101eS uint32_t region_id:16; 2530dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2531dea3101eS uint32_t type:4; 2532dea3101eS uint32_t cv:1; 2533dea3101eS uint32_t co:1; 2534dea3101eS uint32_t ra:1; 2535dea3101eS uint32_t rsvd:25; 2536dea3101eS uint32_t region_id:16; 2537dea3101eS uint32_t entry_index:16; 2538dea3101eS #endif 2539dea3101eS 2540da0436e9SJames Smart uint32_t sli4_length; 2541dea3101eS uint32_t word_cnt; 2542dea3101eS uint32_t resp_offset; 2543dea3101eS } DUMP_VAR; 2544dea3101eS 2545dea3101eS #define DMP_MEM_REG 0x1 2546dea3101eS #define DMP_NV_PARAMS 0x2 2547dea3101eS 2548dea3101eS #define DMP_REGION_VPD 0xe 2549dea3101eS #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2550dea3101eS #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2551dea3101eS #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2552dea3101eS 2553da0436e9SJames Smart #define DMP_REGION_VPORT 0x16 /* VPort info region */ 2554da0436e9SJames Smart #define DMP_VPORT_REGION_SIZE 0x200 2555da0436e9SJames Smart #define DMP_MBOX_OFFSET_WORD 0x5 2556da0436e9SJames Smart 2557a0c87cbdSJames Smart #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 2558a0c87cbdSJames Smart #define DMP_RGN23_SIZE 0x400 2559da0436e9SJames Smart 256097207482SJames Smart #define WAKE_UP_PARMS_REGION_ID 4 256197207482SJames Smart #define WAKE_UP_PARMS_WORD_SIZE 15 256297207482SJames Smart 2563da0436e9SJames Smart struct vport_rec { 2564da0436e9SJames Smart uint8_t wwpn[8]; 2565da0436e9SJames Smart uint8_t wwnn[8]; 2566da0436e9SJames Smart }; 2567da0436e9SJames Smart 2568da0436e9SJames Smart #define VPORT_INFO_SIG 0x32324752 2569da0436e9SJames Smart #define VPORT_INFO_REV_MASK 0xff 2570da0436e9SJames Smart #define VPORT_INFO_REV 0x1 2571da0436e9SJames Smart #define MAX_STATIC_VPORT_COUNT 16 2572da0436e9SJames Smart struct static_vport_info { 2573da0436e9SJames Smart uint32_t signature; 2574da0436e9SJames Smart uint32_t rev; 2575da0436e9SJames Smart struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 2576da0436e9SJames Smart uint32_t resvd[66]; 2577da0436e9SJames Smart }; 2578da0436e9SJames Smart 257997207482SJames Smart /* Option rom version structure */ 258097207482SJames Smart struct prog_id { 258197207482SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 258297207482SJames Smart uint8_t type; 258397207482SJames Smart uint8_t id; 258497207482SJames Smart uint32_t ver:4; /* Major Version */ 258597207482SJames Smart uint32_t rev:4; /* Revision */ 258697207482SJames Smart uint32_t lev:2; /* Level */ 258797207482SJames Smart uint32_t dist:2; /* Dist Type */ 258897207482SJames Smart uint32_t num:4; /* number after dist type */ 258997207482SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 259097207482SJames Smart uint32_t num:4; /* number after dist type */ 259197207482SJames Smart uint32_t dist:2; /* Dist Type */ 259297207482SJames Smart uint32_t lev:2; /* Level */ 259397207482SJames Smart uint32_t rev:4; /* Revision */ 259497207482SJames Smart uint32_t ver:4; /* Major Version */ 259597207482SJames Smart uint8_t id; 259697207482SJames Smart uint8_t type; 259797207482SJames Smart #endif 259897207482SJames Smart }; 259997207482SJames Smart 2600d7c255b2SJames Smart /* Structure for MB Command UPDATE_CFG (0x1B) */ 2601d7c255b2SJames Smart 2602d7c255b2SJames Smart struct update_cfg_var { 2603d7c255b2SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2604d7c255b2SJames Smart uint32_t rsvd2:16; 2605d7c255b2SJames Smart uint32_t type:8; 2606d7c255b2SJames Smart uint32_t rsvd:1; 2607d7c255b2SJames Smart uint32_t ra:1; 2608d7c255b2SJames Smart uint32_t co:1; 2609d7c255b2SJames Smart uint32_t cv:1; 2610d7c255b2SJames Smart uint32_t req:4; 2611d7c255b2SJames Smart uint32_t entry_length:16; 2612d7c255b2SJames Smart uint32_t region_id:16; 2613d7c255b2SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 2614d7c255b2SJames Smart uint32_t req:4; 2615d7c255b2SJames Smart uint32_t cv:1; 2616d7c255b2SJames Smart uint32_t co:1; 2617d7c255b2SJames Smart uint32_t ra:1; 2618d7c255b2SJames Smart uint32_t rsvd:1; 2619d7c255b2SJames Smart uint32_t type:8; 2620d7c255b2SJames Smart uint32_t rsvd2:16; 2621d7c255b2SJames Smart uint32_t region_id:16; 2622d7c255b2SJames Smart uint32_t entry_length:16; 2623d7c255b2SJames Smart #endif 2624d7c255b2SJames Smart 2625d7c255b2SJames Smart uint32_t resp_info; 2626d7c255b2SJames Smart uint32_t byte_cnt; 2627d7c255b2SJames Smart uint32_t data_offset; 2628d7c255b2SJames Smart }; 2629d7c255b2SJames Smart 2630ed957684SJames Smart struct hbq_mask { 2631ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2632ed957684SJames Smart uint8_t tmatch; 2633ed957684SJames Smart uint8_t tmask; 2634ed957684SJames Smart uint8_t rctlmatch; 2635ed957684SJames Smart uint8_t rctlmask; 2636ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2637ed957684SJames Smart uint8_t rctlmask; 2638ed957684SJames Smart uint8_t rctlmatch; 2639ed957684SJames Smart uint8_t tmask; 2640ed957684SJames Smart uint8_t tmatch; 2641ed957684SJames Smart #endif 2642ed957684SJames Smart }; 2643ed957684SJames Smart 2644ed957684SJames Smart 2645ed957684SJames Smart /* Structure for MB Command CONFIG_HBQ (7c) */ 2646ed957684SJames Smart 2647ed957684SJames Smart struct config_hbq_var { 2648ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2649ed957684SJames Smart uint32_t rsvd1 :7; 2650ed957684SJames Smart uint32_t recvNotify :1; /* Receive Notification */ 2651ed957684SJames Smart uint32_t numMask :8; /* # Mask Entries */ 2652ed957684SJames Smart uint32_t profile :8; /* Selection Profile */ 2653ed957684SJames Smart uint32_t rsvd2 :8; 2654ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2655ed957684SJames Smart uint32_t rsvd2 :8; 2656ed957684SJames Smart uint32_t profile :8; /* Selection Profile */ 2657ed957684SJames Smart uint32_t numMask :8; /* # Mask Entries */ 2658ed957684SJames Smart uint32_t recvNotify :1; /* Receive Notification */ 2659ed957684SJames Smart uint32_t rsvd1 :7; 2660ed957684SJames Smart #endif 2661ed957684SJames Smart 2662ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2663ed957684SJames Smart uint32_t hbqId :16; 2664ed957684SJames Smart uint32_t rsvd3 :12; 2665ed957684SJames Smart uint32_t ringMask :4; 2666ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2667ed957684SJames Smart uint32_t ringMask :4; 2668ed957684SJames Smart uint32_t rsvd3 :12; 2669ed957684SJames Smart uint32_t hbqId :16; 2670ed957684SJames Smart #endif 2671ed957684SJames Smart 2672ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2673ed957684SJames Smart uint32_t entry_count :16; 2674ed957684SJames Smart uint32_t rsvd4 :8; 2675ed957684SJames Smart uint32_t headerLen :8; 2676ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2677ed957684SJames Smart uint32_t headerLen :8; 2678ed957684SJames Smart uint32_t rsvd4 :8; 2679ed957684SJames Smart uint32_t entry_count :16; 2680ed957684SJames Smart #endif 2681ed957684SJames Smart 2682ed957684SJames Smart uint32_t hbqaddrLow; 2683ed957684SJames Smart uint32_t hbqaddrHigh; 2684ed957684SJames Smart 2685ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2686ed957684SJames Smart uint32_t rsvd5 :31; 2687ed957684SJames Smart uint32_t logEntry :1; 2688ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2689ed957684SJames Smart uint32_t logEntry :1; 2690ed957684SJames Smart uint32_t rsvd5 :31; 2691ed957684SJames Smart #endif 2692ed957684SJames Smart 2693ed957684SJames Smart uint32_t rsvd6; /* w7 */ 2694ed957684SJames Smart uint32_t rsvd7; /* w8 */ 2695ed957684SJames Smart uint32_t rsvd8; /* w9 */ 2696ed957684SJames Smart 2697ed957684SJames Smart struct hbq_mask hbqMasks[6]; 2698ed957684SJames Smart 2699ed957684SJames Smart 2700ed957684SJames Smart union { 2701ed957684SJames Smart uint32_t allprofiles[12]; 2702ed957684SJames Smart 2703ed957684SJames Smart struct { 2704ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2705ed957684SJames Smart uint32_t seqlenoff :16; 2706ed957684SJames Smart uint32_t maxlen :16; 2707ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2708ed957684SJames Smart uint32_t maxlen :16; 2709ed957684SJames Smart uint32_t seqlenoff :16; 2710ed957684SJames Smart #endif 2711ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2712ed957684SJames Smart uint32_t rsvd1 :28; 2713ed957684SJames Smart uint32_t seqlenbcnt :4; 2714ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2715ed957684SJames Smart uint32_t seqlenbcnt :4; 2716ed957684SJames Smart uint32_t rsvd1 :28; 2717ed957684SJames Smart #endif 2718ed957684SJames Smart uint32_t rsvd[10]; 2719ed957684SJames Smart } profile2; 2720ed957684SJames Smart 2721ed957684SJames Smart struct { 2722ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2723ed957684SJames Smart uint32_t seqlenoff :16; 2724ed957684SJames Smart uint32_t maxlen :16; 2725ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2726ed957684SJames Smart uint32_t maxlen :16; 2727ed957684SJames Smart uint32_t seqlenoff :16; 2728ed957684SJames Smart #endif 2729ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2730ed957684SJames Smart uint32_t cmdcodeoff :28; 2731ed957684SJames Smart uint32_t rsvd1 :12; 2732ed957684SJames Smart uint32_t seqlenbcnt :4; 2733ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2734ed957684SJames Smart uint32_t seqlenbcnt :4; 2735ed957684SJames Smart uint32_t rsvd1 :12; 2736ed957684SJames Smart uint32_t cmdcodeoff :28; 2737ed957684SJames Smart #endif 2738ed957684SJames Smart uint32_t cmdmatch[8]; 2739ed957684SJames Smart 2740ed957684SJames Smart uint32_t rsvd[2]; 2741ed957684SJames Smart } profile3; 2742ed957684SJames Smart 2743ed957684SJames Smart struct { 2744ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2745ed957684SJames Smart uint32_t seqlenoff :16; 2746ed957684SJames Smart uint32_t maxlen :16; 2747ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2748ed957684SJames Smart uint32_t maxlen :16; 2749ed957684SJames Smart uint32_t seqlenoff :16; 2750ed957684SJames Smart #endif 2751ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2752ed957684SJames Smart uint32_t cmdcodeoff :28; 2753ed957684SJames Smart uint32_t rsvd1 :12; 2754ed957684SJames Smart uint32_t seqlenbcnt :4; 2755ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2756ed957684SJames Smart uint32_t seqlenbcnt :4; 2757ed957684SJames Smart uint32_t rsvd1 :12; 2758ed957684SJames Smart uint32_t cmdcodeoff :28; 2759ed957684SJames Smart #endif 2760ed957684SJames Smart uint32_t cmdmatch[8]; 2761ed957684SJames Smart 2762ed957684SJames Smart uint32_t rsvd[2]; 2763ed957684SJames Smart } profile5; 2764ed957684SJames Smart 2765ed957684SJames Smart } profiles; 2766ed957684SJames Smart 2767ed957684SJames Smart }; 2768ed957684SJames Smart 2769ed957684SJames Smart 2770dea3101eS 27712e0fef85SJames Smart /* Structure for MB Command CONFIG_PORT (0x88) */ 2772dea3101eS typedef struct { 2773ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2774ed957684SJames Smart uint32_t cBE : 1; 2775ed957684SJames Smart uint32_t cET : 1; 2776ed957684SJames Smart uint32_t cHpcb : 1; 2777ed957684SJames Smart uint32_t cMA : 1; 2778ed957684SJames Smart uint32_t sli_mode : 4; 2779ed957684SJames Smart uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2780ed957684SJames Smart * config block */ 2781ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2782ed957684SJames Smart uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2783ed957684SJames Smart * config block */ 2784ed957684SJames Smart uint32_t sli_mode : 4; 2785ed957684SJames Smart uint32_t cMA : 1; 2786ed957684SJames Smart uint32_t cHpcb : 1; 2787ed957684SJames Smart uint32_t cET : 1; 2788ed957684SJames Smart uint32_t cBE : 1; 2789ed957684SJames Smart #endif 2790ed957684SJames Smart 2791dea3101eS uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2792dea3101eS uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 279397207482SJames Smart uint32_t hbainit[5]; 279497207482SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 279597207482SJames Smart uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 279697207482SJames Smart uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 279797207482SJames Smart #else /* __LITTLE_ENDIAN */ 279897207482SJames Smart uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 279997207482SJames Smart uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 280097207482SJames Smart #endif 2801ed957684SJames Smart 2802ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2803da0436e9SJames Smart uint32_t rsvd1 : 19; /* Reserved */ 2804da0436e9SJames Smart uint32_t cdss : 1; /* Configure Data Security SLI */ 2805da0436e9SJames Smart uint32_t rsvd2 : 3; /* Reserved */ 280681301a9bSJames Smart uint32_t cbg : 1; /* Configure BlockGuard */ 2807ed957684SJames Smart uint32_t cmv : 1; /* Configure Max VPIs */ 2808ed957684SJames Smart uint32_t ccrp : 1; /* Config Command Ring Polling */ 2809ed957684SJames Smart uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2810ed957684SJames Smart uint32_t chbs : 1; /* Cofigure Host Backing store */ 2811ed957684SJames Smart uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2812ed957684SJames Smart uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2813ed957684SJames Smart uint32_t cmx : 1; /* Configure Max XRIs */ 2814ed957684SJames Smart uint32_t cmr : 1; /* Configure Max RPIs */ 2815ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2816ed957684SJames Smart uint32_t cmr : 1; /* Configure Max RPIs */ 2817ed957684SJames Smart uint32_t cmx : 1; /* Configure Max XRIs */ 2818ed957684SJames Smart uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2819ed957684SJames Smart uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2820ed957684SJames Smart uint32_t chbs : 1; /* Cofigure Host Backing store */ 2821ed957684SJames Smart uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2822ed957684SJames Smart uint32_t ccrp : 1; /* Config Command Ring Polling */ 2823ed957684SJames Smart uint32_t cmv : 1; /* Configure Max VPIs */ 282481301a9bSJames Smart uint32_t cbg : 1; /* Configure BlockGuard */ 2825da0436e9SJames Smart uint32_t rsvd2 : 3; /* Reserved */ 2826da0436e9SJames Smart uint32_t cdss : 1; /* Configure Data Security SLI */ 2827da0436e9SJames Smart uint32_t rsvd1 : 19; /* Reserved */ 2828ed957684SJames Smart #endif 2829ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2830da0436e9SJames Smart uint32_t rsvd3 : 19; /* Reserved */ 2831da0436e9SJames Smart uint32_t gdss : 1; /* Configure Data Security SLI */ 2832da0436e9SJames Smart uint32_t rsvd4 : 3; /* Reserved */ 283381301a9bSJames Smart uint32_t gbg : 1; /* Grant BlockGuard */ 2834ed957684SJames Smart uint32_t gmv : 1; /* Grant Max VPIs */ 2835ed957684SJames Smart uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2836ed957684SJames Smart uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2837ed957684SJames Smart uint32_t ghbs : 1; /* Grant Host Backing Store */ 2838ed957684SJames Smart uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2839ed957684SJames Smart uint32_t gerbm : 1; /* Grant ERBM Request */ 2840ed957684SJames Smart uint32_t gmx : 1; /* Grant Max XRIs */ 2841ed957684SJames Smart uint32_t gmr : 1; /* Grant Max RPIs */ 2842ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2843ed957684SJames Smart uint32_t gmr : 1; /* Grant Max RPIs */ 2844ed957684SJames Smart uint32_t gmx : 1; /* Grant Max XRIs */ 2845ed957684SJames Smart uint32_t gerbm : 1; /* Grant ERBM Request */ 2846ed957684SJames Smart uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2847ed957684SJames Smart uint32_t ghbs : 1; /* Grant Host Backing Store */ 2848ed957684SJames Smart uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2849ed957684SJames Smart uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2850ed957684SJames Smart uint32_t gmv : 1; /* Grant Max VPIs */ 285181301a9bSJames Smart uint32_t gbg : 1; /* Grant BlockGuard */ 2852da0436e9SJames Smart uint32_t rsvd4 : 3; /* Reserved */ 2853da0436e9SJames Smart uint32_t gdss : 1; /* Configure Data Security SLI */ 2854da0436e9SJames Smart uint32_t rsvd3 : 19; /* Reserved */ 2855ed957684SJames Smart #endif 2856ed957684SJames Smart 2857ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2858ed957684SJames Smart uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2859ed957684SJames Smart uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2860ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2861ed957684SJames Smart uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2862ed957684SJames Smart uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2863ed957684SJames Smart #endif 2864ed957684SJames Smart 2865ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2866ed957684SJames Smart uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2867da0436e9SJames Smart uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2868ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2869da0436e9SJames Smart uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2870ed957684SJames Smart uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2871ed957684SJames Smart #endif 2872ed957684SJames Smart 2873da0436e9SJames Smart uint32_t rsvd6; /* Reserved */ 2874ed957684SJames Smart 2875ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 2876bc73905aSJames Smart uint32_t fips_rev : 3; /* FIPS Spec Revision */ 2877bc73905aSJames Smart uint32_t fips_level : 4; /* FIPS Level */ 2878bc73905aSJames Smart uint32_t sec_err : 9; /* security crypto error */ 2879ed957684SJames Smart uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2880ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 2881ed957684SJames Smart uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2882bc73905aSJames Smart uint32_t sec_err : 9; /* security crypto error */ 2883bc73905aSJames Smart uint32_t fips_level : 4; /* FIPS Level */ 2884bc73905aSJames Smart uint32_t fips_rev : 3; /* FIPS Spec Revision */ 2885ed957684SJames Smart #endif 2886ed957684SJames Smart 2887dea3101eS } CONFIG_PORT_VAR; 2888dea3101eS 28899399627fSJames Smart /* Structure for MB Command CONFIG_MSI (0x30) */ 28909399627fSJames Smart struct config_msi_var { 28919399627fSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 28929399627fSJames Smart uint32_t dfltMsgNum:8; /* Default message number */ 28939399627fSJames Smart uint32_t rsvd1:11; /* Reserved */ 28949399627fSJames Smart uint32_t NID:5; /* Number of secondary attention IDs */ 28959399627fSJames Smart uint32_t rsvd2:5; /* Reserved */ 28969399627fSJames Smart uint32_t dfltPresent:1; /* Default message number present */ 28979399627fSJames Smart uint32_t addFlag:1; /* Add association flag */ 28989399627fSJames Smart uint32_t reportFlag:1; /* Report association flag */ 28999399627fSJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 29009399627fSJames Smart uint32_t reportFlag:1; /* Report association flag */ 29019399627fSJames Smart uint32_t addFlag:1; /* Add association flag */ 29029399627fSJames Smart uint32_t dfltPresent:1; /* Default message number present */ 29039399627fSJames Smart uint32_t rsvd2:5; /* Reserved */ 29049399627fSJames Smart uint32_t NID:5; /* Number of secondary attention IDs */ 29059399627fSJames Smart uint32_t rsvd1:11; /* Reserved */ 29069399627fSJames Smart uint32_t dfltMsgNum:8; /* Default message number */ 29079399627fSJames Smart #endif 29089399627fSJames Smart uint32_t attentionConditions[2]; 29099399627fSJames Smart uint8_t attentionId[16]; 29109399627fSJames Smart uint8_t messageNumberByHA[64]; 29119399627fSJames Smart uint8_t messageNumberByID[16]; 29129399627fSJames Smart uint32_t autoClearHA[2]; 29139399627fSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 29149399627fSJames Smart uint32_t rsvd3:16; 29159399627fSJames Smart uint32_t autoClearID:16; 29169399627fSJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 29179399627fSJames Smart uint32_t autoClearID:16; 29189399627fSJames Smart uint32_t rsvd3:16; 29199399627fSJames Smart #endif 29209399627fSJames Smart uint32_t rsvd4; 29219399627fSJames Smart }; 29229399627fSJames Smart 2923dea3101eS /* SLI-2 Port Control Block */ 2924dea3101eS 2925dea3101eS /* SLIM POINTER */ 2926dea3101eS #define SLIMOFF 0x30 /* WORD */ 2927dea3101eS 2928dea3101eS typedef struct _SLI2_RDSC { 2929dea3101eS uint32_t cmdEntries; 2930dea3101eS uint32_t cmdAddrLow; 2931dea3101eS uint32_t cmdAddrHigh; 2932dea3101eS 2933dea3101eS uint32_t rspEntries; 2934dea3101eS uint32_t rspAddrLow; 2935dea3101eS uint32_t rspAddrHigh; 2936dea3101eS } SLI2_RDSC; 2937dea3101eS 2938dea3101eS typedef struct _PCB { 2939dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2940dea3101eS uint32_t type:8; 2941dea3101eS #define TYPE_NATIVE_SLI2 0x01; 2942dea3101eS uint32_t feature:8; 2943dea3101eS #define FEATURE_INITIAL_SLI2 0x01; 2944dea3101eS uint32_t rsvd:12; 2945dea3101eS uint32_t maxRing:4; 2946dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2947dea3101eS uint32_t maxRing:4; 2948dea3101eS uint32_t rsvd:12; 2949dea3101eS uint32_t feature:8; 2950dea3101eS #define FEATURE_INITIAL_SLI2 0x01; 2951dea3101eS uint32_t type:8; 2952dea3101eS #define TYPE_NATIVE_SLI2 0x01; 2953dea3101eS #endif 2954dea3101eS 2955dea3101eS uint32_t mailBoxSize; 2956dea3101eS uint32_t mbAddrLow; 2957dea3101eS uint32_t mbAddrHigh; 2958dea3101eS 2959dea3101eS uint32_t hgpAddrLow; 2960dea3101eS uint32_t hgpAddrHigh; 2961dea3101eS 2962dea3101eS uint32_t pgpAddrLow; 2963dea3101eS uint32_t pgpAddrHigh; 2964dea3101eS SLI2_RDSC rdsc[MAX_RINGS]; 2965dea3101eS } PCB_t; 2966dea3101eS 2967dea3101eS /* NEW_FEATURE */ 2968dea3101eS typedef struct { 2969dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 2970dea3101eS uint32_t rsvd0:27; 2971dea3101eS uint32_t discardFarp:1; 2972dea3101eS uint32_t IPEnable:1; 2973dea3101eS uint32_t nodeName:1; 2974dea3101eS uint32_t portName:1; 2975dea3101eS uint32_t filterEnable:1; 2976dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 2977dea3101eS uint32_t filterEnable:1; 2978dea3101eS uint32_t portName:1; 2979dea3101eS uint32_t nodeName:1; 2980dea3101eS uint32_t IPEnable:1; 2981dea3101eS uint32_t discardFarp:1; 2982dea3101eS uint32_t rsvd:27; 2983dea3101eS #endif 2984dea3101eS 2985dea3101eS uint8_t portname[8]; /* Used to be struct lpfc_name */ 2986dea3101eS uint8_t nodename[8]; 2987dea3101eS uint32_t rsvd1; 2988dea3101eS uint32_t rsvd2; 2989dea3101eS uint32_t rsvd3; 2990dea3101eS uint32_t IPAddress; 2991dea3101eS } CONFIG_FARP_VAR; 2992dea3101eS 299357127f15SJames Smart /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 299457127f15SJames Smart 299557127f15SJames Smart typedef struct { 299657127f15SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 299757127f15SJames Smart uint32_t rsvd:30; 299857127f15SJames Smart uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 299957127f15SJames Smart #else /* __LITTLE_ENDIAN */ 300057127f15SJames Smart uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 300157127f15SJames Smart uint32_t rsvd:30; 300257127f15SJames Smart #endif 300357127f15SJames Smart } ASYNCEVT_ENABLE_VAR; 300457127f15SJames Smart 3005dea3101eS /* Union of all Mailbox Command types */ 3006dea3101eS #define MAILBOX_CMD_WSIZE 32 3007dea3101eS #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 30087a470277SJames Smart /* ext_wsize times 4 bytes should not be greater than max xmit size */ 30097a470277SJames Smart #define MAILBOX_EXT_WSIZE 512 30107a470277SJames Smart #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 30117a470277SJames Smart #define MAILBOX_HBA_EXT_OFFSET 0x100 30127a470277SJames Smart /* max mbox xmit size is a page size for sysfs IO operations */ 30137a470277SJames Smart #define MAILBOX_MAX_XMIT_SIZE PAGE_SIZE 3014dea3101eS 3015dea3101eS typedef union { 3016ed957684SJames Smart uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3017ed957684SJames Smart * feature/max ring number 3018ed957684SJames Smart */ 3019dea3101eS LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3020dea3101eS READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3021dea3101eS WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3022dea3101eS BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3023dea3101eS INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3024dea3101eS DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3025dea3101eS CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3026dea3101eS PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3027dea3101eS CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3028dea3101eS RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3029dea3101eS READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3030dea3101eS READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3031dea3101eS READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3032dea3101eS READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3033dea3101eS READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3034dea3101eS READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3035dea3101eS READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3036dea3101eS READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3037dea3101eS REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3038dea3101eS UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3039dea3101eS CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3040dea3101eS DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3041dea3101eS UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3042ed957684SJames Smart CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3043ed957684SJames Smart * NEW_FEATURE 3044ed957684SJames Smart */ 3045ed957684SJames Smart struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3046d7c255b2SJames Smart struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3047dea3101eS CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 304876a95d75SJames Smart struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 304992d7f7b0SJames Smart REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 305092d7f7b0SJames Smart UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 305157127f15SJames Smart ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3052c7495937SJames Smart struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3053c7495937SJames Smart * (READ_EVENT_LOG) 3054c7495937SJames Smart */ 30559399627fSJames Smart struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3056dea3101eS } MAILVARIANTS; 3057dea3101eS 3058dea3101eS /* 3059dea3101eS * SLI-2 specific structures 3060dea3101eS */ 3061dea3101eS 30624cc2da1dSJames.Smart@Emulex.Com struct lpfc_hgp { 30634cc2da1dSJames.Smart@Emulex.Com __le32 cmdPutInx; 30644cc2da1dSJames.Smart@Emulex.Com __le32 rspGetInx; 30654cc2da1dSJames.Smart@Emulex.Com }; 3066dea3101eS 30674cc2da1dSJames.Smart@Emulex.Com struct lpfc_pgp { 30684cc2da1dSJames.Smart@Emulex.Com __le32 cmdGetInx; 30694cc2da1dSJames.Smart@Emulex.Com __le32 rspPutInx; 30704cc2da1dSJames.Smart@Emulex.Com }; 3071dea3101eS 3072ed957684SJames Smart struct sli2_desc { 3073dea3101eS uint32_t unused1[16]; 3074ed957684SJames Smart struct lpfc_hgp host[MAX_RINGS]; 30754cc2da1dSJames.Smart@Emulex.Com struct lpfc_pgp port[MAX_RINGS]; 3076ed957684SJames Smart }; 3077ed957684SJames Smart 3078ed957684SJames Smart struct sli3_desc { 3079ed957684SJames Smart struct lpfc_hgp host[MAX_RINGS]; 3080ed957684SJames Smart uint32_t reserved[8]; 3081ed957684SJames Smart uint32_t hbq_put[16]; 3082ed957684SJames Smart }; 3083ed957684SJames Smart 3084ed957684SJames Smart struct sli3_pgp { 3085ed957684SJames Smart struct lpfc_pgp port[MAX_RINGS]; 3086ed957684SJames Smart uint32_t hbq_get[16]; 3087ed957684SJames Smart }; 3088dea3101eS 308934b02dcdSJames Smart union sli_var { 3090ed957684SJames Smart struct sli2_desc s2; 3091ed957684SJames Smart struct sli3_desc s3; 3092ed957684SJames Smart struct sli3_pgp s3_pgp; 309334b02dcdSJames Smart }; 3094dea3101eS 3095dea3101eS typedef struct { 3096dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3097dea3101eS uint16_t mbxStatus; 3098dea3101eS uint8_t mbxCommand; 3099dea3101eS uint8_t mbxReserved:6; 3100dea3101eS uint8_t mbxHc:1; 3101dea3101eS uint8_t mbxOwner:1; /* Low order bit first word */ 3102dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3103dea3101eS uint8_t mbxOwner:1; /* Low order bit first word */ 3104dea3101eS uint8_t mbxHc:1; 3105dea3101eS uint8_t mbxReserved:6; 3106dea3101eS uint8_t mbxCommand; 3107dea3101eS uint16_t mbxStatus; 3108dea3101eS #endif 3109dea3101eS 3110dea3101eS MAILVARIANTS un; 311134b02dcdSJames Smart union sli_var us; 3112dea3101eS } MAILBOX_t; 3113dea3101eS 3114dea3101eS /* 3115dea3101eS * Begin Structure Definitions for IOCB Commands 3116dea3101eS */ 3117dea3101eS 3118dea3101eS typedef struct { 3119dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3120dea3101eS uint8_t statAction; 3121dea3101eS uint8_t statRsn; 3122dea3101eS uint8_t statBaExp; 3123dea3101eS uint8_t statLocalError; 3124dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3125dea3101eS uint8_t statLocalError; 3126dea3101eS uint8_t statBaExp; 3127dea3101eS uint8_t statRsn; 3128dea3101eS uint8_t statAction; 3129dea3101eS #endif 3130dea3101eS /* statRsn P/F_RJT reason codes */ 3131dea3101eS #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3132dea3101eS #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3133dea3101eS #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3134dea3101eS #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3135dea3101eS #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3136dea3101eS #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3137dea3101eS #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3138dea3101eS #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3139dea3101eS #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3140dea3101eS #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3141dea3101eS #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3142dea3101eS #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3143dea3101eS #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3144dea3101eS #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3145dea3101eS #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3146dea3101eS #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3147dea3101eS #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3148dea3101eS #define RJT_PROT_ERR 0x12 /* Protocol error */ 3149dea3101eS #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3150dea3101eS #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3151dea3101eS #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3152dea3101eS #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3153dea3101eS #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3154dea3101eS #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3155dea3101eS #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3156dea3101eS #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3157dea3101eS 3158dea3101eS #define IOERR_SUCCESS 0x00 /* statLocalError */ 3159dea3101eS #define IOERR_MISSING_CONTINUE 0x01 3160dea3101eS #define IOERR_SEQUENCE_TIMEOUT 0x02 3161dea3101eS #define IOERR_INTERNAL_ERROR 0x03 3162dea3101eS #define IOERR_INVALID_RPI 0x04 3163dea3101eS #define IOERR_NO_XRI 0x05 3164dea3101eS #define IOERR_ILLEGAL_COMMAND 0x06 3165dea3101eS #define IOERR_XCHG_DROPPED 0x07 3166dea3101eS #define IOERR_ILLEGAL_FIELD 0x08 3167dea3101eS #define IOERR_BAD_CONTINUE 0x09 3168dea3101eS #define IOERR_TOO_MANY_BUFFERS 0x0A 3169dea3101eS #define IOERR_RCV_BUFFER_WAITING 0x0B 3170dea3101eS #define IOERR_NO_CONNECTION 0x0C 3171dea3101eS #define IOERR_TX_DMA_FAILED 0x0D 3172dea3101eS #define IOERR_RX_DMA_FAILED 0x0E 3173dea3101eS #define IOERR_ILLEGAL_FRAME 0x0F 3174dea3101eS #define IOERR_EXTRA_DATA 0x10 3175dea3101eS #define IOERR_NO_RESOURCES 0x11 3176dea3101eS #define IOERR_RESERVED 0x12 3177dea3101eS #define IOERR_ILLEGAL_LENGTH 0x13 3178dea3101eS #define IOERR_UNSUPPORTED_FEATURE 0x14 3179dea3101eS #define IOERR_ABORT_IN_PROGRESS 0x15 3180dea3101eS #define IOERR_ABORT_REQUESTED 0x16 3181dea3101eS #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3182dea3101eS #define IOERR_LOOP_OPEN_FAILURE 0x18 3183dea3101eS #define IOERR_RING_RESET 0x19 3184dea3101eS #define IOERR_LINK_DOWN 0x1A 3185dea3101eS #define IOERR_CORRUPTED_DATA 0x1B 3186dea3101eS #define IOERR_CORRUPTED_RPI 0x1C 3187dea3101eS #define IOERR_OUT_OF_ORDER_DATA 0x1D 3188dea3101eS #define IOERR_OUT_OF_ORDER_ACK 0x1E 3189dea3101eS #define IOERR_DUP_FRAME 0x1F 3190dea3101eS #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3191dea3101eS #define IOERR_BAD_HOST_ADDRESS 0x21 3192dea3101eS #define IOERR_RCV_HDRBUF_WAITING 0x22 3193dea3101eS #define IOERR_MISSING_HDR_BUFFER 0x23 3194dea3101eS #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3195dea3101eS #define IOERR_ABORTMULT_REQUESTED 0x25 3196dea3101eS #define IOERR_BUFFER_SHORTAGE 0x28 3197dea3101eS #define IOERR_DEFAULT 0x29 3198dea3101eS #define IOERR_CNT 0x2A 3199b92938b4SJames Smart #define IOERR_SLER_FAILURE 0x46 3200b92938b4SJames Smart #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3201b92938b4SJames Smart #define IOERR_SLER_REC_RJT_ERR 0x48 3202b92938b4SJames Smart #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3203b92938b4SJames Smart #define IOERR_SLER_SRR_RJT_ERR 0x4A 3204b92938b4SJames Smart #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3205b92938b4SJames Smart #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3206b92938b4SJames Smart #define IOERR_SLER_ABTS_ERR 0x4E 3207*ab56dc2eSJames Smart #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3208*ab56dc2eSJames Smart #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3209*ab56dc2eSJames Smart #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3210*ab56dc2eSJames Smart #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3211dea3101eS #define IOERR_DRVR_MASK 0x100 3212dea3101eS #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3213dea3101eS #define IOERR_SLI_BRESET 0x102 3214dea3101eS #define IOERR_SLI_ABORTED 0x103 3215dea3101eS } PARM_ERR; 3216dea3101eS 3217dea3101eS typedef union { 3218dea3101eS struct { 3219dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3220dea3101eS uint8_t Rctl; /* R_CTL field */ 3221dea3101eS uint8_t Type; /* TYPE field */ 3222dea3101eS uint8_t Dfctl; /* DF_CTL field */ 3223dea3101eS uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3224dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3225dea3101eS uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3226dea3101eS uint8_t Dfctl; /* DF_CTL field */ 3227dea3101eS uint8_t Type; /* TYPE field */ 3228dea3101eS uint8_t Rctl; /* R_CTL field */ 3229dea3101eS #endif 3230dea3101eS 3231dea3101eS #define BC 0x02 /* Broadcast Received - Fctl */ 3232dea3101eS #define SI 0x04 /* Sequence Initiative */ 3233dea3101eS #define LA 0x08 /* Ignore Link Attention state */ 3234dea3101eS #define LS 0x80 /* Last Sequence */ 3235dea3101eS } hcsw; 3236dea3101eS uint32_t reserved; 3237dea3101eS } WORD5; 3238dea3101eS 3239dea3101eS /* IOCB Command template for a generic response */ 3240dea3101eS typedef struct { 3241dea3101eS uint32_t reserved[4]; 3242dea3101eS PARM_ERR perr; 3243dea3101eS } GENERIC_RSP; 3244dea3101eS 3245dea3101eS /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3246dea3101eS typedef struct { 3247dea3101eS struct ulp_bde xrsqbde[2]; 3248dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3249dea3101eS WORD5 w5; /* Header control/status word */ 3250dea3101eS } XR_SEQ_FIELDS; 3251dea3101eS 3252dea3101eS /* IOCB Command template for ELS_REQUEST */ 3253dea3101eS typedef struct { 3254dea3101eS struct ulp_bde elsReq; 3255dea3101eS struct ulp_bde elsRsp; 3256dea3101eS 3257dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3258dea3101eS uint32_t word4Rsvd:7; 3259dea3101eS uint32_t fl:1; 3260dea3101eS uint32_t myID:24; 3261dea3101eS uint32_t word5Rsvd:8; 3262dea3101eS uint32_t remoteID:24; 3263dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3264dea3101eS uint32_t myID:24; 3265dea3101eS uint32_t fl:1; 3266dea3101eS uint32_t word4Rsvd:7; 3267dea3101eS uint32_t remoteID:24; 3268dea3101eS uint32_t word5Rsvd:8; 3269dea3101eS #endif 3270dea3101eS } ELS_REQUEST; 3271dea3101eS 3272dea3101eS /* IOCB Command template for RCV_ELS_REQ */ 3273dea3101eS typedef struct { 3274dea3101eS struct ulp_bde elsReq[2]; 3275dea3101eS uint32_t parmRo; 3276dea3101eS 3277dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3278dea3101eS uint32_t word5Rsvd:8; 3279dea3101eS uint32_t remoteID:24; 3280dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3281dea3101eS uint32_t remoteID:24; 3282dea3101eS uint32_t word5Rsvd:8; 3283dea3101eS #endif 3284dea3101eS } RCV_ELS_REQ; 3285dea3101eS 3286dea3101eS /* IOCB Command template for ABORT / CLOSE_XRI */ 3287dea3101eS typedef struct { 3288dea3101eS uint32_t rsvd[3]; 3289dea3101eS uint32_t abortType; 3290dea3101eS #define ABORT_TYPE_ABTX 0x00000000 3291dea3101eS #define ABORT_TYPE_ABTS 0x00000001 3292dea3101eS uint32_t parm; 3293dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3294dea3101eS uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3295dea3101eS uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3296dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3297dea3101eS uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3298dea3101eS uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3299dea3101eS #endif 3300dea3101eS } AC_XRI; 3301dea3101eS 3302dea3101eS /* IOCB Command template for ABORT_MXRI64 */ 3303dea3101eS typedef struct { 3304dea3101eS uint32_t rsvd[3]; 3305dea3101eS uint32_t abortType; 3306dea3101eS uint32_t parm; 3307dea3101eS uint32_t iotag32; 3308dea3101eS } A_MXRI64; 3309dea3101eS 3310dea3101eS /* IOCB Command template for GET_RPI */ 3311dea3101eS typedef struct { 3312dea3101eS uint32_t rsvd[4]; 3313dea3101eS uint32_t parmRo; 3314dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3315dea3101eS uint32_t word5Rsvd:8; 3316dea3101eS uint32_t remoteID:24; 3317dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3318dea3101eS uint32_t remoteID:24; 3319dea3101eS uint32_t word5Rsvd:8; 3320dea3101eS #endif 3321dea3101eS } GET_RPI; 3322dea3101eS 3323dea3101eS /* IOCB Command template for all FCP Initiator commands */ 3324dea3101eS typedef struct { 3325dea3101eS struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3326dea3101eS struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3327dea3101eS uint32_t fcpi_parm; 3328dea3101eS uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3329dea3101eS } FCPI_FIELDS; 3330dea3101eS 3331dea3101eS /* IOCB Command template for all FCP Target commands */ 3332dea3101eS typedef struct { 3333dea3101eS struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3334dea3101eS uint32_t fcpt_Offset; 3335dea3101eS uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3336dea3101eS } FCPT_FIELDS; 3337dea3101eS 3338dea3101eS /* SLI-2 IOCB structure definitions */ 3339dea3101eS 3340dea3101eS /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3341dea3101eS typedef struct { 3342dea3101eS ULP_BDL bdl; 3343dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3344dea3101eS WORD5 w5; /* Header control/status word */ 3345dea3101eS } XMT_SEQ_FIELDS64; 3346dea3101eS 3347dea3101eS /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3348dea3101eS typedef struct { 3349dea3101eS struct ulp_bde64 rcvBde; 3350dea3101eS uint32_t rsvd1; 3351dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3352dea3101eS WORD5 w5; /* Header control/status word */ 3353dea3101eS } RCV_SEQ_FIELDS64; 3354dea3101eS 3355dea3101eS /* IOCB Command template for ELS_REQUEST64 */ 3356dea3101eS typedef struct { 3357dea3101eS ULP_BDL bdl; 3358dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3359dea3101eS uint32_t word4Rsvd:7; 3360dea3101eS uint32_t fl:1; 3361dea3101eS uint32_t myID:24; 3362dea3101eS uint32_t word5Rsvd:8; 3363dea3101eS uint32_t remoteID:24; 3364dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3365dea3101eS uint32_t myID:24; 3366dea3101eS uint32_t fl:1; 3367dea3101eS uint32_t word4Rsvd:7; 3368dea3101eS uint32_t remoteID:24; 3369dea3101eS uint32_t word5Rsvd:8; 3370dea3101eS #endif 3371dea3101eS } ELS_REQUEST64; 3372dea3101eS 3373dea3101eS /* IOCB Command template for GEN_REQUEST64 */ 3374dea3101eS typedef struct { 3375dea3101eS ULP_BDL bdl; 3376dea3101eS uint32_t xrsqRo; /* Starting Relative Offset */ 3377dea3101eS WORD5 w5; /* Header control/status word */ 3378dea3101eS } GEN_REQUEST64; 3379dea3101eS 3380dea3101eS /* IOCB Command template for RCV_ELS_REQ64 */ 3381dea3101eS typedef struct { 3382dea3101eS struct ulp_bde64 elsReq; 3383dea3101eS uint32_t rcvd1; 3384dea3101eS uint32_t parmRo; 3385dea3101eS 3386dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3387dea3101eS uint32_t word5Rsvd:8; 3388dea3101eS uint32_t remoteID:24; 3389dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3390dea3101eS uint32_t remoteID:24; 3391dea3101eS uint32_t word5Rsvd:8; 3392dea3101eS #endif 3393dea3101eS } RCV_ELS_REQ64; 3394dea3101eS 33959c2face6SJames Smart /* IOCB Command template for RCV_SEQ64 */ 33969c2face6SJames Smart struct rcv_seq64 { 33979c2face6SJames Smart struct ulp_bde64 elsReq; 33989c2face6SJames Smart uint32_t hbq_1; 33999c2face6SJames Smart uint32_t parmRo; 34009c2face6SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 34019c2face6SJames Smart uint32_t rctl:8; 34029c2face6SJames Smart uint32_t type:8; 34039c2face6SJames Smart uint32_t dfctl:8; 34049c2face6SJames Smart uint32_t ls:1; 34059c2face6SJames Smart uint32_t fs:1; 34069c2face6SJames Smart uint32_t rsvd2:3; 34079c2face6SJames Smart uint32_t si:1; 34089c2face6SJames Smart uint32_t bc:1; 34099c2face6SJames Smart uint32_t rsvd3:1; 34109c2face6SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 34119c2face6SJames Smart uint32_t rsvd3:1; 34129c2face6SJames Smart uint32_t bc:1; 34139c2face6SJames Smart uint32_t si:1; 34149c2face6SJames Smart uint32_t rsvd2:3; 34159c2face6SJames Smart uint32_t fs:1; 34169c2face6SJames Smart uint32_t ls:1; 34179c2face6SJames Smart uint32_t dfctl:8; 34189c2face6SJames Smart uint32_t type:8; 34199c2face6SJames Smart uint32_t rctl:8; 34209c2face6SJames Smart #endif 34219c2face6SJames Smart }; 34229c2face6SJames Smart 3423dea3101eS /* IOCB Command template for all 64 bit FCP Initiator commands */ 3424dea3101eS typedef struct { 3425dea3101eS ULP_BDL bdl; 3426dea3101eS uint32_t fcpi_parm; 3427dea3101eS uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3428dea3101eS } FCPI_FIELDS64; 3429dea3101eS 3430dea3101eS /* IOCB Command template for all 64 bit FCP Target commands */ 3431dea3101eS typedef struct { 3432dea3101eS ULP_BDL bdl; 3433dea3101eS uint32_t fcpt_Offset; 3434dea3101eS uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3435dea3101eS } FCPT_FIELDS64; 3436dea3101eS 343757127f15SJames Smart /* IOCB Command template for Async Status iocb commands */ 343857127f15SJames Smart typedef struct { 343957127f15SJames Smart uint32_t rsvd[4]; 344057127f15SJames Smart uint32_t param; 344157127f15SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 344257127f15SJames Smart uint16_t evt_code; /* High order bits word 5 */ 344357127f15SJames Smart uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 344457127f15SJames Smart #else /* __LITTLE_ENDIAN_BITFIELD */ 344557127f15SJames Smart uint16_t sub_ctxt_tag; /* High order bits word 5 */ 344657127f15SJames Smart uint16_t evt_code; /* Low order bits word 5 */ 344757127f15SJames Smart #endif 344857127f15SJames Smart } ASYNCSTAT_FIELDS; 344957127f15SJames Smart #define ASYNC_TEMP_WARN 0x100 345057127f15SJames Smart #define ASYNC_TEMP_SAFE 0x101 345157127f15SJames Smart 3452ed957684SJames Smart /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3453ed957684SJames Smart or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3454ed957684SJames Smart 3455ed957684SJames Smart struct rcv_sli3 { 3456ed957684SJames Smart uint32_t word8Rsvd; 3457ed957684SJames Smart #ifdef __BIG_ENDIAN_BITFIELD 3458ed957684SJames Smart uint16_t vpi; 3459ed957684SJames Smart uint16_t word9Rsvd; 3460ed957684SJames Smart #else /* __LITTLE_ENDIAN */ 3461ed957684SJames Smart uint16_t word9Rsvd; 3462ed957684SJames Smart uint16_t vpi; 3463ed957684SJames Smart #endif 3464ed957684SJames Smart uint32_t word10Rsvd; 3465ed957684SJames Smart uint32_t acc_len; /* accumulated length */ 3466ed957684SJames Smart struct ulp_bde64 bde2; 3467ed957684SJames Smart }; 3468ed957684SJames Smart 346976bb24efSJames Smart /* Structure used for a single HBQ entry */ 347076bb24efSJames Smart struct lpfc_hbq_entry { 347176bb24efSJames Smart struct ulp_bde64 bde; 347276bb24efSJames Smart uint32_t buffer_tag; 347376bb24efSJames Smart }; 347492d7f7b0SJames Smart 347576bb24efSJames Smart /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 347676bb24efSJames Smart typedef struct { 347776bb24efSJames Smart struct lpfc_hbq_entry buff; 347876bb24efSJames Smart uint32_t rsvd; 347976bb24efSJames Smart uint32_t rsvd1; 348076bb24efSJames Smart } QUE_XRI64_CX_FIELDS; 348176bb24efSJames Smart 348276bb24efSJames Smart struct que_xri64cx_ext_fields { 348376bb24efSJames Smart uint32_t iotag64_low; 348476bb24efSJames Smart uint32_t iotag64_high; 348576bb24efSJames Smart uint32_t ebde_count; 348676bb24efSJames Smart uint32_t rsvd; 348776bb24efSJames Smart struct lpfc_hbq_entry buff[5]; 348876bb24efSJames Smart }; 348992d7f7b0SJames Smart 349081301a9bSJames Smart struct sli3_bg_fields { 349181301a9bSJames Smart uint32_t filler[6]; /* word 8-13 in IOCB */ 349281301a9bSJames Smart uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 349381301a9bSJames Smart /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 349481301a9bSJames Smart #define BGS_BIDIR_BG_PROF_MASK 0xff000000 349581301a9bSJames Smart #define BGS_BIDIR_BG_PROF_SHIFT 24 349681301a9bSJames Smart #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 349781301a9bSJames Smart #define BGS_BIDIR_ERR_COND_SHIFT 16 349881301a9bSJames Smart #define BGS_BG_PROFILE_MASK 0x0000ff00 349981301a9bSJames Smart #define BGS_BG_PROFILE_SHIFT 8 350081301a9bSJames Smart #define BGS_INVALID_PROF_MASK 0x00000020 350181301a9bSJames Smart #define BGS_INVALID_PROF_SHIFT 5 350281301a9bSJames Smart #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 350381301a9bSJames Smart #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 350481301a9bSJames Smart #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 350581301a9bSJames Smart #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 350681301a9bSJames Smart #define BGS_REFTAG_ERR_MASK 0x00000004 350781301a9bSJames Smart #define BGS_REFTAG_ERR_SHIFT 2 350881301a9bSJames Smart #define BGS_APPTAG_ERR_MASK 0x00000002 350981301a9bSJames Smart #define BGS_APPTAG_ERR_SHIFT 1 351081301a9bSJames Smart #define BGS_GUARD_ERR_MASK 0x00000001 351181301a9bSJames Smart #define BGS_GUARD_ERR_SHIFT 0 351281301a9bSJames Smart uint32_t bgstat; /* word 15 - BlockGuard Status */ 351381301a9bSJames Smart }; 351481301a9bSJames Smart 351581301a9bSJames Smart static inline uint32_t 351681301a9bSJames Smart lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 351781301a9bSJames Smart { 3518bc73905aSJames Smart return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 351981301a9bSJames Smart BGS_BIDIR_BG_PROF_SHIFT; 352081301a9bSJames Smart } 352181301a9bSJames Smart 352281301a9bSJames Smart static inline uint32_t 352381301a9bSJames Smart lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 352481301a9bSJames Smart { 3525bc73905aSJames Smart return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 352681301a9bSJames Smart BGS_BIDIR_ERR_COND_SHIFT; 352781301a9bSJames Smart } 352881301a9bSJames Smart 352981301a9bSJames Smart static inline uint32_t 353081301a9bSJames Smart lpfc_bgs_get_bg_prof(uint32_t bgstat) 353181301a9bSJames Smart { 3532bc73905aSJames Smart return (bgstat & BGS_BG_PROFILE_MASK) >> 353381301a9bSJames Smart BGS_BG_PROFILE_SHIFT; 353481301a9bSJames Smart } 353581301a9bSJames Smart 353681301a9bSJames Smart static inline uint32_t 353781301a9bSJames Smart lpfc_bgs_get_invalid_prof(uint32_t bgstat) 353881301a9bSJames Smart { 3539bc73905aSJames Smart return (bgstat & BGS_INVALID_PROF_MASK) >> 354081301a9bSJames Smart BGS_INVALID_PROF_SHIFT; 354181301a9bSJames Smart } 354281301a9bSJames Smart 354381301a9bSJames Smart static inline uint32_t 354481301a9bSJames Smart lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 354581301a9bSJames Smart { 3546bc73905aSJames Smart return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 354781301a9bSJames Smart BGS_UNINIT_DIF_BLOCK_SHIFT; 354881301a9bSJames Smart } 354981301a9bSJames Smart 355081301a9bSJames Smart static inline uint32_t 355181301a9bSJames Smart lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 355281301a9bSJames Smart { 3553bc73905aSJames Smart return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 355481301a9bSJames Smart BGS_HI_WATER_MARK_PRESENT_SHIFT; 355581301a9bSJames Smart } 355681301a9bSJames Smart 355781301a9bSJames Smart static inline uint32_t 355881301a9bSJames Smart lpfc_bgs_get_reftag_err(uint32_t bgstat) 355981301a9bSJames Smart { 3560bc73905aSJames Smart return (bgstat & BGS_REFTAG_ERR_MASK) >> 356181301a9bSJames Smart BGS_REFTAG_ERR_SHIFT; 356281301a9bSJames Smart } 356381301a9bSJames Smart 356481301a9bSJames Smart static inline uint32_t 356581301a9bSJames Smart lpfc_bgs_get_apptag_err(uint32_t bgstat) 356681301a9bSJames Smart { 3567bc73905aSJames Smart return (bgstat & BGS_APPTAG_ERR_MASK) >> 356881301a9bSJames Smart BGS_APPTAG_ERR_SHIFT; 356981301a9bSJames Smart } 357081301a9bSJames Smart 357181301a9bSJames Smart static inline uint32_t 357281301a9bSJames Smart lpfc_bgs_get_guard_err(uint32_t bgstat) 357381301a9bSJames Smart { 3574bc73905aSJames Smart return (bgstat & BGS_GUARD_ERR_MASK) >> 357581301a9bSJames Smart BGS_GUARD_ERR_SHIFT; 357681301a9bSJames Smart } 357781301a9bSJames Smart 357834b02dcdSJames Smart #define LPFC_EXT_DATA_BDE_COUNT 3 357934b02dcdSJames Smart struct fcp_irw_ext { 358034b02dcdSJames Smart uint32_t io_tag64_low; 358134b02dcdSJames Smart uint32_t io_tag64_high; 358234b02dcdSJames Smart #ifdef __BIG_ENDIAN_BITFIELD 358334b02dcdSJames Smart uint8_t reserved1; 358434b02dcdSJames Smart uint8_t reserved2; 358534b02dcdSJames Smart uint8_t reserved3; 358634b02dcdSJames Smart uint8_t ebde_count; 358734b02dcdSJames Smart #else /* __LITTLE_ENDIAN */ 358834b02dcdSJames Smart uint8_t ebde_count; 358934b02dcdSJames Smart uint8_t reserved3; 359034b02dcdSJames Smart uint8_t reserved2; 359134b02dcdSJames Smart uint8_t reserved1; 359234b02dcdSJames Smart #endif 359334b02dcdSJames Smart uint32_t reserved4; 359434b02dcdSJames Smart struct ulp_bde64 rbde; /* response bde */ 359534b02dcdSJames Smart struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 359634b02dcdSJames Smart uint8_t icd[32]; /* immediate command data (32 bytes) */ 359734b02dcdSJames Smart }; 359834b02dcdSJames Smart 3599dea3101eS typedef struct _IOCB { /* IOCB structure */ 3600dea3101eS union { 3601dea3101eS GENERIC_RSP grsp; /* Generic response */ 3602dea3101eS XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 3603dea3101eS struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 3604dea3101eS RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 3605dea3101eS AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 3606dea3101eS A_MXRI64 amxri; /* abort multiple xri command overlay */ 3607dea3101eS GET_RPI getrpi; /* GET_RPI template */ 3608dea3101eS FCPI_FIELDS fcpi; /* FCP Initiator template */ 3609dea3101eS FCPT_FIELDS fcpt; /* FCP target template */ 3610dea3101eS 3611dea3101eS /* SLI-2 structures */ 3612dea3101eS 3613dea3101eS struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 3614ed957684SJames Smart * bde_64s */ 3615dea3101eS ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 3616dea3101eS GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 3617dea3101eS RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 3618dea3101eS XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 3619dea3101eS FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 3620dea3101eS FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 362157127f15SJames Smart ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 362276bb24efSJames Smart QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 36239c2face6SJames Smart struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 36245ffc266eSJames Smart struct sli4_bls_acc bls_acc; /* UNSOL ABTS BLS_ACC params */ 3625dea3101eS uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 3626dea3101eS } un; 3627dea3101eS union { 3628dea3101eS struct { 3629dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3630dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3631dea3101eS uint16_t ulpIoTag; /* Low order bits word 6 */ 3632dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3633dea3101eS uint16_t ulpIoTag; /* Low order bits word 6 */ 3634dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3635dea3101eS #endif 3636dea3101eS } t1; 3637dea3101eS struct { 3638dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3639dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3640dea3101eS uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3641dea3101eS uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3642dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3643dea3101eS uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3644dea3101eS uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3645dea3101eS uint16_t ulpContext; /* High order bits word 6 */ 3646dea3101eS #endif 3647dea3101eS } t2; 3648dea3101eS } un1; 3649dea3101eS #define ulpContext un1.t1.ulpContext 3650dea3101eS #define ulpIoTag un1.t1.ulpIoTag 3651dea3101eS #define ulpIoTag0 un1.t2.ulpIoTag0 3652dea3101eS 3653dea3101eS #ifdef __BIG_ENDIAN_BITFIELD 3654dea3101eS uint32_t ulpTimeout:8; 3655dea3101eS uint32_t ulpXS:1; 3656dea3101eS uint32_t ulpFCP2Rcvy:1; 3657dea3101eS uint32_t ulpPU:2; 3658dea3101eS uint32_t ulpIr:1; 3659dea3101eS uint32_t ulpClass:3; 3660dea3101eS uint32_t ulpCommand:8; 3661dea3101eS uint32_t ulpStatus:4; 3662dea3101eS uint32_t ulpBdeCount:2; 3663dea3101eS uint32_t ulpLe:1; 3664dea3101eS uint32_t ulpOwner:1; /* Low order bit word 7 */ 3665dea3101eS #else /* __LITTLE_ENDIAN_BITFIELD */ 3666dea3101eS uint32_t ulpOwner:1; /* Low order bit word 7 */ 3667dea3101eS uint32_t ulpLe:1; 3668dea3101eS uint32_t ulpBdeCount:2; 3669dea3101eS uint32_t ulpStatus:4; 3670dea3101eS uint32_t ulpCommand:8; 3671dea3101eS uint32_t ulpClass:3; 3672dea3101eS uint32_t ulpIr:1; 3673dea3101eS uint32_t ulpPU:2; 3674dea3101eS uint32_t ulpFCP2Rcvy:1; 3675dea3101eS uint32_t ulpXS:1; 3676dea3101eS uint32_t ulpTimeout:8; 3677dea3101eS #endif 367892d7f7b0SJames Smart 3679ed957684SJames Smart union { 3680ed957684SJames Smart struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 368176bb24efSJames Smart 368276bb24efSJames Smart /* words 8-31 used for que_xri_cx iocb */ 368376bb24efSJames Smart struct que_xri64cx_ext_fields que_xri64cx_ext_words; 368434b02dcdSJames Smart struct fcp_irw_ext fcp_ext; 3685ed957684SJames Smart uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 368681301a9bSJames Smart 368781301a9bSJames Smart /* words 8-15 for BlockGuard */ 368881301a9bSJames Smart struct sli3_bg_fields sli3_bg; 3689ed957684SJames Smart } unsli3; 3690dea3101eS 3691ed957684SJames Smart #define ulpCt_h ulpXS 3692ed957684SJames Smart #define ulpCt_l ulpFCP2Rcvy 3693ed957684SJames Smart 3694ed957684SJames Smart #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 3695ed957684SJames Smart #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 3696dea3101eS #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 3697dea3101eS #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 3698dea3101eS #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 369992d7f7b0SJames Smart #define PARM_NPIV_DID 3 3700dea3101eS #define CLASS1 0 /* Class 1 */ 3701dea3101eS #define CLASS2 1 /* Class 2 */ 3702dea3101eS #define CLASS3 2 /* Class 3 */ 3703dea3101eS #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 3704dea3101eS 3705dea3101eS #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 3706dea3101eS #define IOSTAT_FCP_RSP_ERROR 0x1 3707dea3101eS #define IOSTAT_REMOTE_STOP 0x2 3708dea3101eS #define IOSTAT_LOCAL_REJECT 0x3 3709dea3101eS #define IOSTAT_NPORT_RJT 0x4 3710dea3101eS #define IOSTAT_FABRIC_RJT 0x5 3711dea3101eS #define IOSTAT_NPORT_BSY 0x6 3712dea3101eS #define IOSTAT_FABRIC_BSY 0x7 3713dea3101eS #define IOSTAT_INTERMED_RSP 0x8 3714dea3101eS #define IOSTAT_LS_RJT 0x9 3715dea3101eS #define IOSTAT_BA_RJT 0xA 3716dea3101eS #define IOSTAT_RSVD1 0xB 3717dea3101eS #define IOSTAT_RSVD2 0xC 3718dea3101eS #define IOSTAT_RSVD3 0xD 3719dea3101eS #define IOSTAT_RSVD4 0xE 372092d7f7b0SJames Smart #define IOSTAT_NEED_BUFFER 0xF 3721dea3101eS #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 3722dea3101eS #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 3723dea3101eS #define IOSTAT_CNT 0x11 3724dea3101eS 3725dea3101eS } IOCB_t; 3726dea3101eS 3727dea3101eS 3728dea3101eS #define SLI1_SLIM_SIZE (4 * 1024) 3729dea3101eS 3730dea3101eS /* Up to 498 IOCBs will fit into 16k 3731dea3101eS * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 3732dea3101eS */ 3733ed957684SJames Smart #define SLI2_SLIM_SIZE (64 * 1024) 3734dea3101eS 3735dea3101eS /* Maximum IOCBs that will fit in SLI2 slim */ 3736dea3101eS #define MAX_SLI2_IOCB 498 3737ed957684SJames Smart #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 37387a470277SJames Smart (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 37397a470277SJames Smart sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 3740ed957684SJames Smart 3741ed957684SJames Smart /* HBQ entries are 4 words each = 4k */ 3742ed957684SJames Smart #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 3743ed957684SJames Smart lpfc_sli_hbq_count()) 3744dea3101eS 3745dea3101eS struct lpfc_sli2_slim { 3746dea3101eS MAILBOX_t mbx; 37477a470277SJames Smart uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 3748dea3101eS PCB_t pcb; 3749ed957684SJames Smart IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 3750dea3101eS }; 3751dea3101eS 37522e0fef85SJames Smart /* 37532e0fef85SJames Smart * This function checks PCI device to allow special handling for LC HBAs. 37542e0fef85SJames Smart * 37552e0fef85SJames Smart * Parameters: 37562e0fef85SJames Smart * device : struct pci_dev 's device field 37572e0fef85SJames Smart * 37582e0fef85SJames Smart * return 1 => TRUE 37592e0fef85SJames Smart * 0 => FALSE 37602e0fef85SJames Smart */ 3761dea3101eS static inline int 3762dea3101eS lpfc_is_LC_HBA(unsigned short device) 3763dea3101eS { 3764dea3101eS if ((device == PCI_DEVICE_ID_TFLY) || 3765dea3101eS (device == PCI_DEVICE_ID_PFLY) || 3766dea3101eS (device == PCI_DEVICE_ID_LP101) || 3767dea3101eS (device == PCI_DEVICE_ID_BMID) || 3768dea3101eS (device == PCI_DEVICE_ID_BSMB) || 3769dea3101eS (device == PCI_DEVICE_ID_ZMID) || 3770dea3101eS (device == PCI_DEVICE_ID_ZSMB) || 377109372820SJames Smart (device == PCI_DEVICE_ID_SAT_MID) || 377209372820SJames Smart (device == PCI_DEVICE_ID_SAT_SMB) || 3773dea3101eS (device == PCI_DEVICE_ID_RFLY)) 3774dea3101eS return 1; 3775dea3101eS else 3776dea3101eS return 0; 3777dea3101eS } 3778858c9f6cSJames Smart 3779858c9f6cSJames Smart /* 3780858c9f6cSJames Smart * Determine if an IOCB failed because of a link event or firmware reset. 3781858c9f6cSJames Smart */ 3782858c9f6cSJames Smart 3783858c9f6cSJames Smart static inline int 3784858c9f6cSJames Smart lpfc_error_lost_link(IOCB_t *iocbp) 3785858c9f6cSJames Smart { 3786858c9f6cSJames Smart return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 3787858c9f6cSJames Smart (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 3788858c9f6cSJames Smart iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 3789858c9f6cSJames Smart iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 3790858c9f6cSJames Smart } 379184774a4dSJames Smart 379284774a4dSJames Smart #define MENLO_TRANSPORT_TYPE 0xfe 379384774a4dSJames Smart #define MENLO_CONTEXT 0 379484774a4dSJames Smart #define MENLO_PU 3 379584774a4dSJames Smart #define MENLO_TIMEOUT 30 379684774a4dSJames Smart #define SETVAR_MLOMNT 0x103107 379784774a4dSJames Smart #define SETVAR_MLORST 0x103007 3798da0436e9SJames Smart 3799da0436e9SJames Smart #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 3800