1 /* 2 * ipr.h -- driver for IBM Power Linux RAID adapters 3 * 4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation 5 * 6 * Copyright (C) 2003, 2004 IBM Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * Alan Cox <alan@redhat.com> - Removed several careless u32/dma_addr_t errors 23 * that broke 64bit platforms. 24 */ 25 26 #ifndef _IPR_H 27 #define _IPR_H 28 29 #include <linux/types.h> 30 #include <linux/completion.h> 31 #include <linux/libata.h> 32 #include <linux/list.h> 33 #include <linux/kref.h> 34 #include <scsi/scsi.h> 35 #include <scsi/scsi_cmnd.h> 36 37 /* 38 * Literals 39 */ 40 #define IPR_DRIVER_VERSION "2.3.2" 41 #define IPR_DRIVER_DATE "(March 23, 2007)" 42 43 /* 44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding 45 * ops per device for devices not running tagged command queuing. 46 * This can be adjusted at runtime through sysfs device attributes. 47 */ 48 #define IPR_MAX_CMD_PER_LUN 6 49 #define IPR_MAX_CMD_PER_ATA_LUN 1 50 51 /* 52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of 53 * ops the mid-layer can send to the adapter. 54 */ 55 #define IPR_NUM_BASE_CMD_BLKS 100 56 57 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 58 #define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A 59 60 #define IPR_SUBS_DEV_ID_2780 0x0264 61 #define IPR_SUBS_DEV_ID_5702 0x0266 62 #define IPR_SUBS_DEV_ID_5703 0x0278 63 #define IPR_SUBS_DEV_ID_572E 0x028D 64 #define IPR_SUBS_DEV_ID_573E 0x02D3 65 #define IPR_SUBS_DEV_ID_573D 0x02D4 66 #define IPR_SUBS_DEV_ID_571A 0x02C0 67 #define IPR_SUBS_DEV_ID_571B 0x02BE 68 #define IPR_SUBS_DEV_ID_571E 0x02BF 69 #define IPR_SUBS_DEV_ID_571F 0x02D5 70 #define IPR_SUBS_DEV_ID_572A 0x02C1 71 #define IPR_SUBS_DEV_ID_572B 0x02C2 72 #define IPR_SUBS_DEV_ID_572F 0x02C3 73 #define IPR_SUBS_DEV_ID_574D 0x030B 74 #define IPR_SUBS_DEV_ID_574E 0x030A 75 #define IPR_SUBS_DEV_ID_575B 0x030D 76 #define IPR_SUBS_DEV_ID_575C 0x0338 77 #define IPR_SUBS_DEV_ID_575D 0x033E 78 #define IPR_SUBS_DEV_ID_57B3 0x033A 79 #define IPR_SUBS_DEV_ID_57B7 0x0360 80 #define IPR_SUBS_DEV_ID_57B8 0x02C2 81 82 #define IPR_NAME "ipr" 83 84 /* 85 * Return codes 86 */ 87 #define IPR_RC_JOB_CONTINUE 1 88 #define IPR_RC_JOB_RETURN 2 89 90 /* 91 * IOASCs 92 */ 93 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 94 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000 95 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00 96 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000 97 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500 98 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00 99 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF 100 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000 101 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000 102 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100 103 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000 104 #define IPR_IOASC_BUS_WAS_RESET 0x06290000 105 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000 106 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000 107 108 #define IPR_FIRST_DRIVER_IOASC 0x10000000 109 #define IPR_IOASC_IOA_WAS_RESET 0x10000001 110 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002 111 112 /* Driver data flags */ 113 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001 114 115 #define IPR_DEFAULT_MAX_ERROR_DUMP 984 116 #define IPR_NUM_LOG_HCAMS 2 117 #define IPR_NUM_CFG_CHG_HCAMS 2 118 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) 119 #define IPR_MAX_NUM_TARGETS_PER_BUS 256 120 #define IPR_MAX_NUM_LUNS_PER_TARGET 256 121 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8 122 #define IPR_VSET_BUS 0xff 123 #define IPR_IOA_BUS 0xff 124 #define IPR_IOA_TARGET 0xff 125 #define IPR_IOA_LUN 0xff 126 #define IPR_MAX_NUM_BUSES 16 127 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES 128 129 #define IPR_NUM_RESET_RELOAD_RETRIES 3 130 131 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */ 132 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ 133 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3) 134 135 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS 136 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ 137 IPR_NUM_INTERNAL_CMD_BLKS) 138 139 #define IPR_MAX_PHYSICAL_DEVS 192 140 141 #define IPR_MAX_SGLIST 64 142 #define IPR_IOA_MAX_SECTORS 32767 143 #define IPR_VSET_MAX_SECTORS 512 144 #define IPR_MAX_CDB_LEN 16 145 146 #define IPR_DEFAULT_BUS_WIDTH 16 147 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 148 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 149 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 150 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8)) 151 152 #define IPR_IOA_RES_HANDLE 0xffffffff 153 #define IPR_INVALID_RES_HANDLE 0 154 #define IPR_IOA_RES_ADDR 0x00ffffff 155 156 /* 157 * Adapter Commands 158 */ 159 #define IPR_QUERY_RSRC_STATE 0xC2 160 #define IPR_RESET_DEVICE 0xC3 161 #define IPR_RESET_TYPE_SELECT 0x80 162 #define IPR_LUN_RESET 0x40 163 #define IPR_TARGET_RESET 0x20 164 #define IPR_BUS_RESET 0x10 165 #define IPR_ATA_PHY_RESET 0x80 166 #define IPR_ID_HOST_RR_Q 0xC4 167 #define IPR_QUERY_IOA_CONFIG 0xC5 168 #define IPR_CANCEL_ALL_REQUESTS 0xCE 169 #define IPR_HOST_CONTROLLED_ASYNC 0xCF 170 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 171 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 172 #define IPR_SET_SUPPORTED_DEVICES 0xFB 173 #define IPR_IOA_SHUTDOWN 0xF7 174 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 175 176 /* 177 * Timeouts 178 */ 179 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ) 180 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ) 181 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ) 182 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 183 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 184 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 185 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 186 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ) 187 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ) 188 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ) 189 #define IPR_OPERATIONAL_TIMEOUT (5 * 60) 190 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60) 191 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ) 192 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10) 193 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ) 194 #define IPR_DUMP_TIMEOUT (15 * HZ) 195 196 /* 197 * SCSI Literals 198 */ 199 #define IPR_VENDOR_ID_LEN 8 200 #define IPR_PROD_ID_LEN 16 201 #define IPR_SERIAL_NUM_LEN 8 202 203 /* 204 * Hardware literals 205 */ 206 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff 207 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000 208 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28 209 #define IPR_GET_FMT2_BAR_SEL(mbx) \ 210 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT) 211 #define IPR_SDT_FMT2_BAR0_SEL 0x0 212 #define IPR_SDT_FMT2_BAR1_SEL 0x1 213 #define IPR_SDT_FMT2_BAR2_SEL 0x2 214 #define IPR_SDT_FMT2_BAR3_SEL 0x3 215 #define IPR_SDT_FMT2_BAR4_SEL 0x4 216 #define IPR_SDT_FMT2_BAR5_SEL 0x5 217 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8 218 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 219 #define IPR_DOORBELL 0x82800000 220 #define IPR_RUNTIME_RESET 0x40000000 221 222 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) 223 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) 224 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) 225 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5) 226 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6) 227 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7) 228 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27) 229 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28) 230 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29) 231 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30) 232 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31) 233 234 #define IPR_PCII_ERROR_INTERRUPTS \ 235 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \ 236 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR) 237 238 #define IPR_PCII_OPER_INTERRUPTS \ 239 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER) 240 241 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7) 242 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9) 243 244 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */ 245 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */ 246 247 /* 248 * Dump literals 249 */ 250 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024) 251 #define IPR_NUM_SDT_ENTRIES 511 252 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) 253 254 /* 255 * Misc literals 256 */ 257 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST 258 259 /* 260 * Adapter interface types 261 */ 262 263 struct ipr_res_addr { 264 u8 reserved; 265 u8 bus; 266 u8 target; 267 u8 lun; 268 #define IPR_GET_PHYS_LOC(res_addr) \ 269 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun) 270 }__attribute__((packed, aligned (4))); 271 272 struct ipr_std_inq_vpids { 273 u8 vendor_id[IPR_VENDOR_ID_LEN]; 274 u8 product_id[IPR_PROD_ID_LEN]; 275 }__attribute__((packed)); 276 277 struct ipr_vpd { 278 struct ipr_std_inq_vpids vpids; 279 u8 sn[IPR_SERIAL_NUM_LEN]; 280 }__attribute__((packed)); 281 282 struct ipr_ext_vpd { 283 struct ipr_vpd vpd; 284 __be32 wwid[2]; 285 }__attribute__((packed)); 286 287 struct ipr_std_inq_data { 288 u8 peri_qual_dev_type; 289 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5) 290 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F) 291 292 u8 removeable_medium_rsvd; 293 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80 294 295 #define IPR_IS_DASD_DEVICE(std_inq) \ 296 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \ 297 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM)) 298 299 #define IPR_IS_SES_DEVICE(std_inq) \ 300 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE) 301 302 u8 version; 303 u8 aen_naca_fmt; 304 u8 additional_len; 305 u8 sccs_rsvd; 306 u8 bq_enc_multi; 307 u8 sync_cmdq_flags; 308 309 struct ipr_std_inq_vpids vpids; 310 311 u8 ros_rsvd_ram_rsvd[4]; 312 313 u8 serial_num[IPR_SERIAL_NUM_LEN]; 314 }__attribute__ ((packed)); 315 316 struct ipr_config_table_entry { 317 u8 proto; 318 #define IPR_PROTO_SATA 0x02 319 #define IPR_PROTO_SATA_ATAPI 0x03 320 #define IPR_PROTO_SAS_STP 0x06 321 #define IPR_PROTO_SAS_STP_ATAPI 0x07 322 u8 array_id; 323 u8 flags; 324 #define IPR_IS_IOA_RESOURCE 0x80 325 #define IPR_IS_ARRAY_MEMBER 0x20 326 #define IPR_IS_HOT_SPARE 0x10 327 328 u8 rsvd_subtype; 329 #define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f) 330 #define IPR_SUBTYPE_AF_DASD 0 331 #define IPR_SUBTYPE_GENERIC_SCSI 1 332 #define IPR_SUBTYPE_VOLUME_SET 2 333 #define IPR_SUBTYPE_GENERIC_ATA 4 334 335 #define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4) 336 #define IPR_QUEUE_FROZEN_MODEL 0 337 #define IPR_QUEUE_NACA_MODEL 1 338 339 struct ipr_res_addr res_addr; 340 __be32 res_handle; 341 __be32 reserved4[2]; 342 struct ipr_std_inq_data std_inq_data; 343 }__attribute__ ((packed, aligned (4))); 344 345 struct ipr_config_table_hdr { 346 u8 num_entries; 347 u8 flags; 348 #define IPR_UCODE_DOWNLOAD_REQ 0x10 349 __be16 reserved; 350 }__attribute__((packed, aligned (4))); 351 352 struct ipr_config_table { 353 struct ipr_config_table_hdr hdr; 354 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS]; 355 }__attribute__((packed, aligned (4))); 356 357 struct ipr_hostrcb_cfg_ch_not { 358 struct ipr_config_table_entry cfgte; 359 u8 reserved[936]; 360 }__attribute__((packed, aligned (4))); 361 362 struct ipr_supported_device { 363 __be16 data_length; 364 u8 reserved; 365 u8 num_records; 366 struct ipr_std_inq_vpids vpids; 367 u8 reserved2[16]; 368 }__attribute__((packed, aligned (4))); 369 370 /* Command packet structure */ 371 struct ipr_cmd_pkt { 372 __be16 reserved; /* Reserved by IOA */ 373 u8 request_type; 374 #define IPR_RQTYPE_SCSICDB 0x00 375 #define IPR_RQTYPE_IOACMD 0x01 376 #define IPR_RQTYPE_HCAM 0x02 377 #define IPR_RQTYPE_ATA_PASSTHRU 0x04 378 379 u8 luntar_luntrn; 380 381 u8 flags_hi; 382 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80 383 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20 384 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10 385 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08 386 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04 387 388 u8 flags_lo; 389 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20 390 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10 391 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00 392 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02 393 #define IPR_FLAGS_LO_ORDERED_TASK 0x04 394 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06 395 #define IPR_FLAGS_LO_ACA_TASK 0x08 396 397 u8 cdb[16]; 398 __be16 timeout; 399 }__attribute__ ((packed, aligned(4))); 400 401 struct ipr_ioarcb_ata_regs { 402 u8 flags; 403 #define IPR_ATA_FLAG_PACKET_CMD 0x80 404 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40 405 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20 406 u8 reserved[3]; 407 408 __be16 data; 409 u8 feature; 410 u8 nsect; 411 u8 lbal; 412 u8 lbam; 413 u8 lbah; 414 u8 device; 415 u8 command; 416 u8 reserved2[3]; 417 u8 hob_feature; 418 u8 hob_nsect; 419 u8 hob_lbal; 420 u8 hob_lbam; 421 u8 hob_lbah; 422 u8 ctl; 423 }__attribute__ ((packed, aligned(4))); 424 425 struct ipr_ioadl_desc { 426 __be32 flags_and_data_len; 427 #define IPR_IOADL_FLAGS_MASK 0xff000000 428 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK) 429 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff 430 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK) 431 #define IPR_IOADL_FLAGS_READ 0x48000000 432 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000 433 #define IPR_IOADL_FLAGS_WRITE 0x68000000 434 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000 435 #define IPR_IOADL_FLAGS_LAST 0x01000000 436 437 __be32 address; 438 }__attribute__((packed, aligned (8))); 439 440 struct ipr_ioarcb_add_data { 441 union { 442 struct ipr_ioarcb_ata_regs regs; 443 struct ipr_ioadl_desc ioadl[5]; 444 __be32 add_cmd_parms[10]; 445 }u; 446 }__attribute__ ((packed, aligned(4))); 447 448 /* IOA Request Control Block 128 bytes */ 449 struct ipr_ioarcb { 450 __be32 ioarcb_host_pci_addr; 451 __be32 reserved; 452 __be32 res_handle; 453 __be32 host_response_handle; 454 __be32 reserved1; 455 __be32 reserved2; 456 __be32 reserved3; 457 458 __be32 write_data_transfer_length; 459 __be32 read_data_transfer_length; 460 __be32 write_ioadl_addr; 461 __be32 write_ioadl_len; 462 __be32 read_ioadl_addr; 463 __be32 read_ioadl_len; 464 465 __be32 ioasa_host_pci_addr; 466 __be16 ioasa_len; 467 __be16 reserved4; 468 469 struct ipr_cmd_pkt cmd_pkt; 470 471 __be32 add_cmd_parms_len; 472 struct ipr_ioarcb_add_data add_data; 473 }__attribute__((packed, aligned (4))); 474 475 struct ipr_ioasa_vset { 476 __be32 failing_lba_hi; 477 __be32 failing_lba_lo; 478 __be32 reserved; 479 }__attribute__((packed, aligned (4))); 480 481 struct ipr_ioasa_af_dasd { 482 __be32 failing_lba; 483 __be32 reserved[2]; 484 }__attribute__((packed, aligned (4))); 485 486 struct ipr_ioasa_gpdd { 487 u8 end_state; 488 u8 bus_phase; 489 __be16 reserved; 490 __be32 ioa_data[2]; 491 }__attribute__((packed, aligned (4))); 492 493 struct ipr_ioasa_gata { 494 u8 error; 495 u8 nsect; /* Interrupt reason */ 496 u8 lbal; 497 u8 lbam; 498 u8 lbah; 499 u8 device; 500 u8 status; 501 u8 alt_status; /* ATA CTL */ 502 u8 hob_nsect; 503 u8 hob_lbal; 504 u8 hob_lbam; 505 u8 hob_lbah; 506 }__attribute__((packed, aligned (4))); 507 508 struct ipr_auto_sense { 509 __be16 auto_sense_len; 510 __be16 ioa_data_len; 511 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)]; 512 }; 513 514 struct ipr_ioasa { 515 __be32 ioasc; 516 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) 517 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) 518 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) 519 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) 520 521 __be16 ret_stat_len; /* Length of the returned IOASA */ 522 523 __be16 avail_stat_len; /* Total Length of status available. */ 524 525 __be32 residual_data_len; /* number of bytes in the host data */ 526 /* buffers that were not used by the IOARCB command. */ 527 528 __be32 ilid; 529 #define IPR_NO_ILID 0 530 #define IPR_DRIVER_ILID 0xffffffff 531 532 __be32 fd_ioasc; 533 534 __be32 fd_phys_locator; 535 536 __be32 fd_res_handle; 537 538 __be32 ioasc_specific; /* status code specific field */ 539 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000 540 #define IPR_AUTOSENSE_VALID 0x40000000 541 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000 542 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff 543 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8) 544 #define IPR_FIELD_POINTER_MASK 0x0000ffff 545 546 union { 547 struct ipr_ioasa_vset vset; 548 struct ipr_ioasa_af_dasd dasd; 549 struct ipr_ioasa_gpdd gpdd; 550 struct ipr_ioasa_gata gata; 551 } u; 552 553 struct ipr_auto_sense auto_sense; 554 }__attribute__((packed, aligned (4))); 555 556 struct ipr_mode_parm_hdr { 557 u8 length; 558 u8 medium_type; 559 u8 device_spec_parms; 560 u8 block_desc_len; 561 }__attribute__((packed)); 562 563 struct ipr_mode_pages { 564 struct ipr_mode_parm_hdr hdr; 565 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)]; 566 }__attribute__((packed)); 567 568 struct ipr_mode_page_hdr { 569 u8 ps_page_code; 570 #define IPR_MODE_PAGE_PS 0x80 571 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F) 572 u8 page_length; 573 }__attribute__ ((packed)); 574 575 struct ipr_dev_bus_entry { 576 struct ipr_res_addr res_addr; 577 u8 flags; 578 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80 579 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40 580 #define IPR_SCSI_ATTR_QAS_MASK 0xC0 581 #define IPR_SCSI_ATTR_ENABLE_TM 0x20 582 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10 583 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08 584 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04 585 586 u8 scsi_id; 587 u8 bus_width; 588 u8 extended_reset_delay; 589 #define IPR_EXTENDED_RESET_DELAY 7 590 591 __be32 max_xfer_rate; 592 593 u8 spinup_delay; 594 u8 reserved3; 595 __be16 reserved4; 596 }__attribute__((packed, aligned (4))); 597 598 struct ipr_mode_page28 { 599 struct ipr_mode_page_hdr hdr; 600 u8 num_entries; 601 u8 entry_length; 602 struct ipr_dev_bus_entry bus[0]; 603 }__attribute__((packed)); 604 605 struct ipr_ioa_vpd { 606 struct ipr_std_inq_data std_inq_data; 607 u8 ascii_part_num[12]; 608 u8 reserved[40]; 609 u8 ascii_plant_code[4]; 610 }__attribute__((packed)); 611 612 struct ipr_inquiry_page3 { 613 u8 peri_qual_dev_type; 614 u8 page_code; 615 u8 reserved1; 616 u8 page_length; 617 u8 ascii_len; 618 u8 reserved2[3]; 619 u8 load_id[4]; 620 u8 major_release; 621 u8 card_type; 622 u8 minor_release[2]; 623 u8 ptf_number[4]; 624 u8 patch_number[4]; 625 }__attribute__((packed)); 626 627 #define IPR_INQUIRY_PAGE0_ENTRIES 20 628 struct ipr_inquiry_page0 { 629 u8 peri_qual_dev_type; 630 u8 page_code; 631 u8 reserved1; 632 u8 len; 633 u8 page[IPR_INQUIRY_PAGE0_ENTRIES]; 634 }__attribute__((packed)); 635 636 struct ipr_hostrcb_device_data_entry { 637 struct ipr_vpd vpd; 638 struct ipr_res_addr dev_res_addr; 639 struct ipr_vpd new_vpd; 640 struct ipr_vpd ioa_last_with_dev_vpd; 641 struct ipr_vpd cfc_last_with_dev_vpd; 642 __be32 ioa_data[5]; 643 }__attribute__((packed, aligned (4))); 644 645 struct ipr_hostrcb_device_data_entry_enhanced { 646 struct ipr_ext_vpd vpd; 647 u8 ccin[4]; 648 struct ipr_res_addr dev_res_addr; 649 struct ipr_ext_vpd new_vpd; 650 u8 new_ccin[4]; 651 struct ipr_ext_vpd ioa_last_with_dev_vpd; 652 struct ipr_ext_vpd cfc_last_with_dev_vpd; 653 }__attribute__((packed, aligned (4))); 654 655 struct ipr_hostrcb_array_data_entry { 656 struct ipr_vpd vpd; 657 struct ipr_res_addr expected_dev_res_addr; 658 struct ipr_res_addr dev_res_addr; 659 }__attribute__((packed, aligned (4))); 660 661 struct ipr_hostrcb_array_data_entry_enhanced { 662 struct ipr_ext_vpd vpd; 663 u8 ccin[4]; 664 struct ipr_res_addr expected_dev_res_addr; 665 struct ipr_res_addr dev_res_addr; 666 }__attribute__((packed, aligned (4))); 667 668 struct ipr_hostrcb_type_ff_error { 669 __be32 ioa_data[502]; 670 }__attribute__((packed, aligned (4))); 671 672 struct ipr_hostrcb_type_01_error { 673 __be32 seek_counter; 674 __be32 read_counter; 675 u8 sense_data[32]; 676 __be32 ioa_data[236]; 677 }__attribute__((packed, aligned (4))); 678 679 struct ipr_hostrcb_type_02_error { 680 struct ipr_vpd ioa_vpd; 681 struct ipr_vpd cfc_vpd; 682 struct ipr_vpd ioa_last_attached_to_cfc_vpd; 683 struct ipr_vpd cfc_last_attached_to_ioa_vpd; 684 __be32 ioa_data[3]; 685 }__attribute__((packed, aligned (4))); 686 687 struct ipr_hostrcb_type_12_error { 688 struct ipr_ext_vpd ioa_vpd; 689 struct ipr_ext_vpd cfc_vpd; 690 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd; 691 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd; 692 __be32 ioa_data[3]; 693 }__attribute__((packed, aligned (4))); 694 695 struct ipr_hostrcb_type_03_error { 696 struct ipr_vpd ioa_vpd; 697 struct ipr_vpd cfc_vpd; 698 __be32 errors_detected; 699 __be32 errors_logged; 700 u8 ioa_data[12]; 701 struct ipr_hostrcb_device_data_entry dev[3]; 702 }__attribute__((packed, aligned (4))); 703 704 struct ipr_hostrcb_type_13_error { 705 struct ipr_ext_vpd ioa_vpd; 706 struct ipr_ext_vpd cfc_vpd; 707 __be32 errors_detected; 708 __be32 errors_logged; 709 struct ipr_hostrcb_device_data_entry_enhanced dev[3]; 710 }__attribute__((packed, aligned (4))); 711 712 struct ipr_hostrcb_type_04_error { 713 struct ipr_vpd ioa_vpd; 714 struct ipr_vpd cfc_vpd; 715 u8 ioa_data[12]; 716 struct ipr_hostrcb_array_data_entry array_member[10]; 717 __be32 exposed_mode_adn; 718 __be32 array_id; 719 struct ipr_vpd incomp_dev_vpd; 720 __be32 ioa_data2; 721 struct ipr_hostrcb_array_data_entry array_member2[8]; 722 struct ipr_res_addr last_func_vset_res_addr; 723 u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; 724 u8 protection_level[8]; 725 }__attribute__((packed, aligned (4))); 726 727 struct ipr_hostrcb_type_14_error { 728 struct ipr_ext_vpd ioa_vpd; 729 struct ipr_ext_vpd cfc_vpd; 730 __be32 exposed_mode_adn; 731 __be32 array_id; 732 struct ipr_res_addr last_func_vset_res_addr; 733 u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; 734 u8 protection_level[8]; 735 __be32 num_entries; 736 struct ipr_hostrcb_array_data_entry_enhanced array_member[18]; 737 }__attribute__((packed, aligned (4))); 738 739 struct ipr_hostrcb_type_07_error { 740 u8 failure_reason[64]; 741 struct ipr_vpd vpd; 742 u32 data[222]; 743 }__attribute__((packed, aligned (4))); 744 745 struct ipr_hostrcb_type_17_error { 746 u8 failure_reason[64]; 747 struct ipr_ext_vpd vpd; 748 u32 data[476]; 749 }__attribute__((packed, aligned (4))); 750 751 struct ipr_hostrcb_config_element { 752 u8 type_status; 753 #define IPR_PATH_CFG_TYPE_MASK 0xF0 754 #define IPR_PATH_CFG_NOT_EXIST 0x00 755 #define IPR_PATH_CFG_IOA_PORT 0x10 756 #define IPR_PATH_CFG_EXP_PORT 0x20 757 #define IPR_PATH_CFG_DEVICE_PORT 0x30 758 #define IPR_PATH_CFG_DEVICE_LUN 0x40 759 760 #define IPR_PATH_CFG_STATUS_MASK 0x0F 761 #define IPR_PATH_CFG_NO_PROB 0x00 762 #define IPR_PATH_CFG_DEGRADED 0x01 763 #define IPR_PATH_CFG_FAILED 0x02 764 #define IPR_PATH_CFG_SUSPECT 0x03 765 #define IPR_PATH_NOT_DETECTED 0x04 766 #define IPR_PATH_INCORRECT_CONN 0x05 767 768 u8 cascaded_expander; 769 u8 phy; 770 u8 link_rate; 771 #define IPR_PHY_LINK_RATE_MASK 0x0F 772 773 __be32 wwid[2]; 774 }__attribute__((packed, aligned (4))); 775 776 struct ipr_hostrcb_fabric_desc { 777 __be16 length; 778 u8 ioa_port; 779 u8 cascaded_expander; 780 u8 phy; 781 u8 path_state; 782 #define IPR_PATH_ACTIVE_MASK 0xC0 783 #define IPR_PATH_NO_INFO 0x00 784 #define IPR_PATH_ACTIVE 0x40 785 #define IPR_PATH_NOT_ACTIVE 0x80 786 787 #define IPR_PATH_STATE_MASK 0x0F 788 #define IPR_PATH_STATE_NO_INFO 0x00 789 #define IPR_PATH_HEALTHY 0x01 790 #define IPR_PATH_DEGRADED 0x02 791 #define IPR_PATH_FAILED 0x03 792 793 __be16 num_entries; 794 struct ipr_hostrcb_config_element elem[1]; 795 }__attribute__((packed, aligned (4))); 796 797 #define for_each_fabric_cfg(fabric, cfg) \ 798 for (cfg = (fabric)->elem; \ 799 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \ 800 cfg++) 801 802 struct ipr_hostrcb_type_20_error { 803 u8 failure_reason[64]; 804 u8 reserved[3]; 805 u8 num_entries; 806 struct ipr_hostrcb_fabric_desc desc[1]; 807 }__attribute__((packed, aligned (4))); 808 809 struct ipr_hostrcb_error { 810 __be32 failing_dev_ioasc; 811 struct ipr_res_addr failing_dev_res_addr; 812 __be32 failing_dev_res_handle; 813 __be32 prc; 814 union { 815 struct ipr_hostrcb_type_ff_error type_ff_error; 816 struct ipr_hostrcb_type_01_error type_01_error; 817 struct ipr_hostrcb_type_02_error type_02_error; 818 struct ipr_hostrcb_type_03_error type_03_error; 819 struct ipr_hostrcb_type_04_error type_04_error; 820 struct ipr_hostrcb_type_07_error type_07_error; 821 struct ipr_hostrcb_type_12_error type_12_error; 822 struct ipr_hostrcb_type_13_error type_13_error; 823 struct ipr_hostrcb_type_14_error type_14_error; 824 struct ipr_hostrcb_type_17_error type_17_error; 825 struct ipr_hostrcb_type_20_error type_20_error; 826 } u; 827 }__attribute__((packed, aligned (4))); 828 829 struct ipr_hostrcb_raw { 830 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)]; 831 }__attribute__((packed, aligned (4))); 832 833 struct ipr_hcam { 834 u8 op_code; 835 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1 836 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2 837 838 u8 notify_type; 839 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00 840 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01 841 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02 842 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10 843 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11 844 845 u8 notifications_lost; 846 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0 847 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80 848 849 u8 flags; 850 #define IPR_HOSTRCB_INTERNAL_OPER 0x80 851 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40 852 853 u8 overlay_id; 854 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01 855 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02 856 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03 857 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04 858 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06 859 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07 860 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12 861 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13 862 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14 863 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16 864 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17 865 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20 866 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF 867 868 u8 reserved1[3]; 869 __be32 ilid; 870 __be32 time_since_last_ioa_reset; 871 __be32 reserved2; 872 __be32 length; 873 874 union { 875 struct ipr_hostrcb_error error; 876 struct ipr_hostrcb_cfg_ch_not ccn; 877 struct ipr_hostrcb_raw raw; 878 } u; 879 }__attribute__((packed, aligned (4))); 880 881 struct ipr_hostrcb { 882 struct ipr_hcam hcam; 883 dma_addr_t hostrcb_dma; 884 struct list_head queue; 885 struct ipr_ioa_cfg *ioa_cfg; 886 }; 887 888 /* IPR smart dump table structures */ 889 struct ipr_sdt_entry { 890 __be32 bar_str_offset; 891 __be32 end_offset; 892 u8 entry_byte; 893 u8 reserved[3]; 894 895 u8 flags; 896 #define IPR_SDT_ENDIAN 0x80 897 #define IPR_SDT_VALID_ENTRY 0x20 898 899 u8 resv; 900 __be16 priority; 901 }__attribute__((packed, aligned (4))); 902 903 struct ipr_sdt_header { 904 __be32 state; 905 __be32 num_entries; 906 __be32 num_entries_used; 907 __be32 dump_size; 908 }__attribute__((packed, aligned (4))); 909 910 struct ipr_sdt { 911 struct ipr_sdt_header hdr; 912 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES]; 913 }__attribute__((packed, aligned (4))); 914 915 struct ipr_uc_sdt { 916 struct ipr_sdt_header hdr; 917 struct ipr_sdt_entry entry[1]; 918 }__attribute__((packed, aligned (4))); 919 920 /* 921 * Driver types 922 */ 923 struct ipr_bus_attributes { 924 u8 bus; 925 u8 qas_enabled; 926 u8 bus_width; 927 u8 reserved; 928 u32 max_xfer_rate; 929 }; 930 931 struct ipr_sata_port { 932 struct ipr_ioa_cfg *ioa_cfg; 933 struct ata_port *ap; 934 struct ipr_resource_entry *res; 935 struct ipr_ioasa_gata ioasa; 936 }; 937 938 struct ipr_resource_entry { 939 struct ipr_config_table_entry cfgte; 940 u8 needs_sync_complete:1; 941 u8 in_erp:1; 942 u8 add_to_ml:1; 943 u8 del_from_ml:1; 944 u8 resetting_device:1; 945 946 struct scsi_device *sdev; 947 struct ipr_sata_port *sata_port; 948 struct list_head queue; 949 }; 950 951 struct ipr_resource_hdr { 952 u16 num_entries; 953 u16 reserved; 954 }; 955 956 struct ipr_resource_table { 957 struct ipr_resource_hdr hdr; 958 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS]; 959 }; 960 961 struct ipr_misc_cbs { 962 struct ipr_ioa_vpd ioa_vpd; 963 struct ipr_inquiry_page0 page0_data; 964 struct ipr_inquiry_page3 page3_data; 965 struct ipr_mode_pages mode_pages; 966 struct ipr_supported_device supp_dev; 967 }; 968 969 struct ipr_interrupt_offsets { 970 unsigned long set_interrupt_mask_reg; 971 unsigned long clr_interrupt_mask_reg; 972 unsigned long sense_interrupt_mask_reg; 973 unsigned long clr_interrupt_reg; 974 975 unsigned long sense_interrupt_reg; 976 unsigned long ioarrin_reg; 977 unsigned long sense_uproc_interrupt_reg; 978 unsigned long set_uproc_interrupt_reg; 979 unsigned long clr_uproc_interrupt_reg; 980 }; 981 982 struct ipr_interrupts { 983 void __iomem *set_interrupt_mask_reg; 984 void __iomem *clr_interrupt_mask_reg; 985 void __iomem *sense_interrupt_mask_reg; 986 void __iomem *clr_interrupt_reg; 987 988 void __iomem *sense_interrupt_reg; 989 void __iomem *ioarrin_reg; 990 void __iomem *sense_uproc_interrupt_reg; 991 void __iomem *set_uproc_interrupt_reg; 992 void __iomem *clr_uproc_interrupt_reg; 993 }; 994 995 struct ipr_chip_cfg_t { 996 u32 mailbox; 997 u8 cache_line_size; 998 struct ipr_interrupt_offsets regs; 999 }; 1000 1001 struct ipr_chip_t { 1002 u16 vendor; 1003 u16 device; 1004 const struct ipr_chip_cfg_t *cfg; 1005 }; 1006 1007 enum ipr_shutdown_type { 1008 IPR_SHUTDOWN_NORMAL = 0x00, 1009 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40, 1010 IPR_SHUTDOWN_ABBREV = 0x80, 1011 IPR_SHUTDOWN_NONE = 0x100 1012 }; 1013 1014 struct ipr_trace_entry { 1015 u32 time; 1016 1017 u8 op_code; 1018 u8 ata_op_code; 1019 u8 type; 1020 #define IPR_TRACE_START 0x00 1021 #define IPR_TRACE_FINISH 0xff 1022 u8 cmd_index; 1023 1024 __be32 res_handle; 1025 union { 1026 u32 ioasc; 1027 u32 add_data; 1028 u32 res_addr; 1029 } u; 1030 }; 1031 1032 struct ipr_sglist { 1033 u32 order; 1034 u32 num_sg; 1035 u32 num_dma_sg; 1036 u32 buffer_len; 1037 struct scatterlist scatterlist[1]; 1038 }; 1039 1040 enum ipr_sdt_state { 1041 INACTIVE, 1042 WAIT_FOR_DUMP, 1043 GET_DUMP, 1044 ABORT_DUMP, 1045 DUMP_OBTAINED 1046 }; 1047 1048 enum ipr_cache_state { 1049 CACHE_NONE, 1050 CACHE_DISABLED, 1051 CACHE_ENABLED, 1052 CACHE_INVALID 1053 }; 1054 1055 /* Per-controller data */ 1056 struct ipr_ioa_cfg { 1057 char eye_catcher[8]; 1058 #define IPR_EYECATCHER "iprcfg" 1059 1060 struct list_head queue; 1061 1062 u8 allow_interrupts:1; 1063 u8 in_reset_reload:1; 1064 u8 in_ioa_bringdown:1; 1065 u8 ioa_unit_checked:1; 1066 u8 ioa_is_dead:1; 1067 u8 dump_taken:1; 1068 u8 allow_cmds:1; 1069 u8 allow_ml_add_del:1; 1070 u8 needs_hard_reset:1; 1071 1072 enum ipr_cache_state cache_state; 1073 u16 type; /* CCIN of the card */ 1074 1075 u8 log_level; 1076 #define IPR_MAX_LOG_LEVEL 4 1077 #define IPR_DEFAULT_LOG_LEVEL 2 1078 1079 #define IPR_NUM_TRACE_INDEX_BITS 8 1080 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS) 1081 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES) 1082 char trace_start[8]; 1083 #define IPR_TRACE_START_LABEL "trace" 1084 struct ipr_trace_entry *trace; 1085 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS; 1086 1087 /* 1088 * Queue for free command blocks 1089 */ 1090 char ipr_free_label[8]; 1091 #define IPR_FREEQ_LABEL "free-q" 1092 struct list_head free_q; 1093 1094 /* 1095 * Queue for command blocks outstanding to the adapter 1096 */ 1097 char ipr_pending_label[8]; 1098 #define IPR_PENDQ_LABEL "pend-q" 1099 struct list_head pending_q; 1100 1101 char cfg_table_start[8]; 1102 #define IPR_CFG_TBL_START "cfg" 1103 struct ipr_config_table *cfg_table; 1104 dma_addr_t cfg_table_dma; 1105 1106 char resource_table_label[8]; 1107 #define IPR_RES_TABLE_LABEL "res_tbl" 1108 struct ipr_resource_entry *res_entries; 1109 struct list_head free_res_q; 1110 struct list_head used_res_q; 1111 1112 char ipr_hcam_label[8]; 1113 #define IPR_HCAM_LABEL "hcams" 1114 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS]; 1115 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS]; 1116 struct list_head hostrcb_free_q; 1117 struct list_head hostrcb_pending_q; 1118 1119 __be32 *host_rrq; 1120 dma_addr_t host_rrq_dma; 1121 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc 1122 #define IPR_HRRQ_RESP_BIT_SET 0x00000002 1123 #define IPR_HRRQ_TOGGLE_BIT 0x00000001 1124 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2 1125 volatile __be32 *hrrq_start; 1126 volatile __be32 *hrrq_end; 1127 volatile __be32 *hrrq_curr; 1128 volatile u32 toggle_bit; 1129 1130 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES]; 1131 1132 unsigned int transop_timeout; 1133 const struct ipr_chip_cfg_t *chip_cfg; 1134 1135 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */ 1136 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */ 1137 void __iomem *ioa_mailbox; 1138 struct ipr_interrupts regs; 1139 1140 u16 saved_pcix_cmd_reg; 1141 u16 reset_retries; 1142 1143 u32 errors_logged; 1144 u32 doorbell; 1145 1146 struct Scsi_Host *host; 1147 struct pci_dev *pdev; 1148 struct ipr_sglist *ucode_sglist; 1149 u8 saved_mode_page_len; 1150 1151 struct work_struct work_q; 1152 1153 wait_queue_head_t reset_wait_q; 1154 1155 struct ipr_dump *dump; 1156 enum ipr_sdt_state sdt_state; 1157 1158 struct ipr_misc_cbs *vpd_cbs; 1159 dma_addr_t vpd_cbs_dma; 1160 1161 struct pci_pool *ipr_cmd_pool; 1162 1163 struct ipr_cmnd *reset_cmd; 1164 1165 struct ata_host ata_host; 1166 char ipr_cmd_label[8]; 1167 #define IPR_CMD_LABEL "ipr_cmnd" 1168 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS]; 1169 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS]; 1170 }; 1171 1172 struct ipr_cmnd { 1173 struct ipr_ioarcb ioarcb; 1174 struct ipr_ioasa ioasa; 1175 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES]; 1176 struct list_head queue; 1177 struct scsi_cmnd *scsi_cmd; 1178 struct ata_queued_cmd *qc; 1179 struct completion completion; 1180 struct timer_list timer; 1181 void (*done) (struct ipr_cmnd *); 1182 int (*job_step) (struct ipr_cmnd *); 1183 int (*job_step_failed) (struct ipr_cmnd *); 1184 u16 cmd_index; 1185 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; 1186 dma_addr_t sense_buffer_dma; 1187 unsigned short dma_use_sg; 1188 dma_addr_t dma_handle; 1189 struct ipr_cmnd *sibling; 1190 union { 1191 enum ipr_shutdown_type shutdown_type; 1192 struct ipr_hostrcb *hostrcb; 1193 unsigned long time_left; 1194 unsigned long scratch; 1195 struct ipr_resource_entry *res; 1196 struct scsi_device *sdev; 1197 } u; 1198 1199 struct ipr_ioa_cfg *ioa_cfg; 1200 }; 1201 1202 struct ipr_ses_table_entry { 1203 char product_id[17]; 1204 char compare_product_id_byte[17]; 1205 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */ 1206 }; 1207 1208 struct ipr_dump_header { 1209 u32 eye_catcher; 1210 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 1211 u32 len; 1212 u32 num_entries; 1213 u32 first_entry_offset; 1214 u32 status; 1215 #define IPR_DUMP_STATUS_SUCCESS 0 1216 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2 1217 #define IPR_DUMP_STATUS_FAILED 0xffffffff 1218 u32 os; 1219 #define IPR_DUMP_OS_LINUX 0x4C4E5558 1220 u32 driver_name; 1221 #define IPR_DUMP_DRIVER_NAME 0x49505232 1222 }__attribute__((packed, aligned (4))); 1223 1224 struct ipr_dump_entry_header { 1225 u32 eye_catcher; 1226 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 1227 u32 len; 1228 u32 num_elems; 1229 u32 offset; 1230 u32 data_type; 1231 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349 1232 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41 1233 u32 id; 1234 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131 1235 #define IPR_DUMP_LOCATION_ID 0x4C4F4341 1236 #define IPR_DUMP_TRACE_ID 0x54524143 1237 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652 1238 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045 1239 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342 1240 #define IPR_DUMP_PEND_OPS 0x414F5053 1241 u32 status; 1242 }__attribute__((packed, aligned (4))); 1243 1244 struct ipr_dump_location_entry { 1245 struct ipr_dump_entry_header hdr; 1246 u8 location[BUS_ID_SIZE]; 1247 }__attribute__((packed)); 1248 1249 struct ipr_dump_trace_entry { 1250 struct ipr_dump_entry_header hdr; 1251 u32 trace[IPR_TRACE_SIZE / sizeof(u32)]; 1252 }__attribute__((packed, aligned (4))); 1253 1254 struct ipr_dump_version_entry { 1255 struct ipr_dump_entry_header hdr; 1256 u8 version[sizeof(IPR_DRIVER_VERSION)]; 1257 }; 1258 1259 struct ipr_dump_ioa_type_entry { 1260 struct ipr_dump_entry_header hdr; 1261 u32 type; 1262 u32 fw_version; 1263 }; 1264 1265 struct ipr_driver_dump { 1266 struct ipr_dump_header hdr; 1267 struct ipr_dump_version_entry version_entry; 1268 struct ipr_dump_location_entry location_entry; 1269 struct ipr_dump_ioa_type_entry ioa_type_entry; 1270 struct ipr_dump_trace_entry trace_entry; 1271 }__attribute__((packed)); 1272 1273 struct ipr_ioa_dump { 1274 struct ipr_dump_entry_header hdr; 1275 struct ipr_sdt sdt; 1276 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES]; 1277 u32 reserved; 1278 u32 next_page_index; 1279 u32 page_offset; 1280 u32 format; 1281 #define IPR_SDT_FMT2 2 1282 #define IPR_SDT_UNKNOWN 3 1283 }__attribute__((packed, aligned (4))); 1284 1285 struct ipr_dump { 1286 struct kref kref; 1287 struct ipr_ioa_cfg *ioa_cfg; 1288 struct ipr_driver_dump driver_dump; 1289 struct ipr_ioa_dump ioa_dump; 1290 }; 1291 1292 struct ipr_error_table_t { 1293 u32 ioasc; 1294 int log_ioasa; 1295 int log_hcam; 1296 char *error; 1297 }; 1298 1299 struct ipr_software_inq_lid_info { 1300 __be32 load_id; 1301 __be32 timestamp[3]; 1302 }__attribute__((packed, aligned (4))); 1303 1304 struct ipr_ucode_image_header { 1305 __be32 header_length; 1306 __be32 lid_table_offset; 1307 u8 major_release; 1308 u8 card_type; 1309 u8 minor_release[2]; 1310 u8 reserved[20]; 1311 char eyecatcher[16]; 1312 __be32 num_lids; 1313 struct ipr_software_inq_lid_info lid[1]; 1314 }__attribute__((packed, aligned (4))); 1315 1316 /* 1317 * Macros 1318 */ 1319 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; } 1320 1321 #ifdef CONFIG_SCSI_IPR_TRACE 1322 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr) 1323 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) 1324 #else 1325 #define ipr_create_trace_file(kobj, attr) 0 1326 #define ipr_remove_trace_file(kobj, attr) do { } while(0) 1327 #endif 1328 1329 #ifdef CONFIG_SCSI_IPR_DUMP 1330 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr) 1331 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) 1332 #else 1333 #define ipr_create_dump_file(kobj, attr) 0 1334 #define ipr_remove_dump_file(kobj, attr) do { } while(0) 1335 #endif 1336 1337 /* 1338 * Error logging macros 1339 */ 1340 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__) 1341 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) 1342 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) 1343 1344 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \ 1345 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ 1346 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__) 1347 1348 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \ 1349 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__) 1350 1351 #define ipr_res_err(ioa_cfg, res, fmt, ...) \ 1352 ipr_ra_err(ioa_cfg, (res)->cfgte.res_addr, fmt, ##__VA_ARGS__) 1353 1354 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \ 1355 { \ 1356 if ((res).bus >= IPR_MAX_NUM_BUSES) { \ 1357 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \ 1358 } else { \ 1359 ipr_err(fmt": %d:%d:%d:%d\n", \ 1360 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \ 1361 (res).bus, (res).target, (res).lun); \ 1362 } \ 1363 } 1364 1365 #define ipr_hcam_err(hostrcb, fmt, ...) \ 1366 { \ 1367 if (ipr_is_device(&(hostrcb)->hcam.u.error.failing_dev_res_addr)) { \ 1368 ipr_ra_err((hostrcb)->ioa_cfg, \ 1369 (hostrcb)->hcam.u.error.failing_dev_res_addr, \ 1370 fmt, ##__VA_ARGS__); \ 1371 } else { \ 1372 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, ##__VA_ARGS__); \ 1373 } \ 1374 } 1375 1376 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\ 1377 __FILE__, __FUNCTION__, __LINE__) 1378 1379 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __FUNCTION__)) 1380 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __FUNCTION__)) 1381 1382 #define ipr_err_separator \ 1383 ipr_err("----------------------------------------------------------\n") 1384 1385 1386 /* 1387 * Inlines 1388 */ 1389 1390 /** 1391 * ipr_is_ioa_resource - Determine if a resource is the IOA 1392 * @res: resource entry struct 1393 * 1394 * Return value: 1395 * 1 if IOA / 0 if not IOA 1396 **/ 1397 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) 1398 { 1399 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0; 1400 } 1401 1402 /** 1403 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD 1404 * @res: resource entry struct 1405 * 1406 * Return value: 1407 * 1 if AF DASD / 0 if not AF DASD 1408 **/ 1409 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) 1410 { 1411 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) && 1412 !ipr_is_ioa_resource(res) && 1413 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD) 1414 return 1; 1415 else 1416 return 0; 1417 } 1418 1419 /** 1420 * ipr_is_vset_device - Determine if a resource is a VSET 1421 * @res: resource entry struct 1422 * 1423 * Return value: 1424 * 1 if VSET / 0 if not VSET 1425 **/ 1426 static inline int ipr_is_vset_device(struct ipr_resource_entry *res) 1427 { 1428 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) && 1429 !ipr_is_ioa_resource(res) && 1430 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET) 1431 return 1; 1432 else 1433 return 0; 1434 } 1435 1436 /** 1437 * ipr_is_gscsi - Determine if a resource is a generic scsi resource 1438 * @res: resource entry struct 1439 * 1440 * Return value: 1441 * 1 if GSCSI / 0 if not GSCSI 1442 **/ 1443 static inline int ipr_is_gscsi(struct ipr_resource_entry *res) 1444 { 1445 if (!ipr_is_ioa_resource(res) && 1446 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI) 1447 return 1; 1448 else 1449 return 0; 1450 } 1451 1452 /** 1453 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk 1454 * @res: resource entry struct 1455 * 1456 * Return value: 1457 * 1 if SCSI disk / 0 if not SCSI disk 1458 **/ 1459 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res) 1460 { 1461 if (ipr_is_af_dasd_device(res) || 1462 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data))) 1463 return 1; 1464 else 1465 return 0; 1466 } 1467 1468 /** 1469 * ipr_is_gata - Determine if a resource is a generic ATA resource 1470 * @res: resource entry struct 1471 * 1472 * Return value: 1473 * 1 if GATA / 0 if not GATA 1474 **/ 1475 static inline int ipr_is_gata(struct ipr_resource_entry *res) 1476 { 1477 if (!ipr_is_ioa_resource(res) && 1478 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_ATA) 1479 return 1; 1480 else 1481 return 0; 1482 } 1483 1484 /** 1485 * ipr_is_naca_model - Determine if a resource is using NACA queueing model 1486 * @res: resource entry struct 1487 * 1488 * Return value: 1489 * 1 if NACA queueing model / 0 if not NACA queueing model 1490 **/ 1491 static inline int ipr_is_naca_model(struct ipr_resource_entry *res) 1492 { 1493 if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL) 1494 return 1; 1495 return 0; 1496 } 1497 1498 /** 1499 * ipr_is_device - Determine if resource address is that of a device 1500 * @res_addr: resource address struct 1501 * 1502 * Return value: 1503 * 1 if AF / 0 if not AF 1504 **/ 1505 static inline int ipr_is_device(struct ipr_res_addr *res_addr) 1506 { 1507 if ((res_addr->bus < IPR_MAX_NUM_BUSES) && 1508 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) 1509 return 1; 1510 1511 return 0; 1512 } 1513 1514 /** 1515 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2 1516 * @sdt_word: SDT address 1517 * 1518 * Return value: 1519 * 1 if format 2 / 0 if not 1520 **/ 1521 static inline int ipr_sdt_is_fmt2(u32 sdt_word) 1522 { 1523 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word); 1524 1525 switch (bar_sel) { 1526 case IPR_SDT_FMT2_BAR0_SEL: 1527 case IPR_SDT_FMT2_BAR1_SEL: 1528 case IPR_SDT_FMT2_BAR2_SEL: 1529 case IPR_SDT_FMT2_BAR3_SEL: 1530 case IPR_SDT_FMT2_BAR4_SEL: 1531 case IPR_SDT_FMT2_BAR5_SEL: 1532 case IPR_SDT_FMT2_EXP_ROM_SEL: 1533 return 1; 1534 }; 1535 1536 return 0; 1537 } 1538 1539 #endif 1540