1 /* 2 * ipr.h -- driver for IBM Power Linux RAID adapters 3 * 4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation 5 * 6 * Copyright (C) 2003, 2004 IBM Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * Alan Cox <alan@redhat.com> - Removed several careless u32/dma_addr_t errors 23 * that broke 64bit platforms. 24 */ 25 26 #ifndef _IPR_H 27 #define _IPR_H 28 29 #include <linux/types.h> 30 #include <linux/completion.h> 31 #include <linux/list.h> 32 #include <linux/kref.h> 33 #include <scsi/scsi.h> 34 #include <scsi/scsi_cmnd.h> 35 36 /* 37 * Literals 38 */ 39 #define IPR_DRIVER_VERSION "2.1.2" 40 #define IPR_DRIVER_DATE "(February 8, 2006)" 41 42 /* 43 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding 44 * ops per device for devices not running tagged command queuing. 45 * This can be adjusted at runtime through sysfs device attributes. 46 */ 47 #define IPR_MAX_CMD_PER_LUN 6 48 49 /* 50 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of 51 * ops the mid-layer can send to the adapter. 52 */ 53 #define IPR_NUM_BASE_CMD_BLKS 100 54 55 #define IPR_SUBS_DEV_ID_2780 0x0264 56 #define IPR_SUBS_DEV_ID_5702 0x0266 57 #define IPR_SUBS_DEV_ID_5703 0x0278 58 #define IPR_SUBS_DEV_ID_572E 0x028D 59 #define IPR_SUBS_DEV_ID_573E 0x02D3 60 #define IPR_SUBS_DEV_ID_573D 0x02D4 61 #define IPR_SUBS_DEV_ID_571A 0x02C0 62 #define IPR_SUBS_DEV_ID_571B 0x02BE 63 #define IPR_SUBS_DEV_ID_571E 0x02BF 64 #define IPR_SUBS_DEV_ID_571F 0x02D5 65 #define IPR_SUBS_DEV_ID_572A 0x02C1 66 #define IPR_SUBS_DEV_ID_572B 0x02C2 67 #define IPR_SUBS_DEV_ID_575B 0x030D 68 69 #define IPR_NAME "ipr" 70 71 /* 72 * Return codes 73 */ 74 #define IPR_RC_JOB_CONTINUE 1 75 #define IPR_RC_JOB_RETURN 2 76 77 /* 78 * IOASCs 79 */ 80 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 81 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000 82 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00 83 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000 84 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500 85 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00 86 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF 87 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000 88 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000 89 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100 90 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000 91 #define IPR_IOASC_BUS_WAS_RESET 0x06290000 92 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000 93 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000 94 95 #define IPR_FIRST_DRIVER_IOASC 0x10000000 96 #define IPR_IOASC_IOA_WAS_RESET 0x10000001 97 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002 98 99 #define IPR_NUM_LOG_HCAMS 2 100 #define IPR_NUM_CFG_CHG_HCAMS 2 101 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) 102 #define IPR_MAX_NUM_TARGETS_PER_BUS 256 103 #define IPR_MAX_NUM_LUNS_PER_TARGET 256 104 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8 105 #define IPR_VSET_BUS 0xff 106 #define IPR_IOA_BUS 0xff 107 #define IPR_IOA_TARGET 0xff 108 #define IPR_IOA_LUN 0xff 109 #define IPR_MAX_NUM_BUSES 8 110 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES 111 112 #define IPR_NUM_RESET_RELOAD_RETRIES 3 113 114 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */ 115 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ 116 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3) 117 118 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS 119 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ 120 IPR_NUM_INTERNAL_CMD_BLKS) 121 122 #define IPR_MAX_PHYSICAL_DEVS 192 123 124 #define IPR_MAX_SGLIST 64 125 #define IPR_IOA_MAX_SECTORS 32767 126 #define IPR_VSET_MAX_SECTORS 512 127 #define IPR_MAX_CDB_LEN 16 128 129 #define IPR_DEFAULT_BUS_WIDTH 16 130 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 131 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 132 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 133 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8)) 134 135 #define IPR_IOA_RES_HANDLE 0xffffffff 136 #define IPR_IOA_RES_ADDR 0x00ffffff 137 138 /* 139 * Adapter Commands 140 */ 141 #define IPR_QUERY_RSRC_STATE 0xC2 142 #define IPR_RESET_DEVICE 0xC3 143 #define IPR_RESET_TYPE_SELECT 0x80 144 #define IPR_LUN_RESET 0x40 145 #define IPR_TARGET_RESET 0x20 146 #define IPR_BUS_RESET 0x10 147 #define IPR_ID_HOST_RR_Q 0xC4 148 #define IPR_QUERY_IOA_CONFIG 0xC5 149 #define IPR_CANCEL_ALL_REQUESTS 0xCE 150 #define IPR_HOST_CONTROLLED_ASYNC 0xCF 151 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 152 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 153 #define IPR_SET_SUPPORTED_DEVICES 0xFB 154 #define IPR_IOA_SHUTDOWN 0xF7 155 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 156 157 /* 158 * Timeouts 159 */ 160 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ) 161 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ) 162 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ) 163 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 164 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 165 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 166 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 167 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ) 168 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ) 169 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ) 170 #define IPR_OPERATIONAL_TIMEOUT (5 * 60) 171 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ) 172 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10) 173 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ) 174 #define IPR_DUMP_TIMEOUT (15 * HZ) 175 176 /* 177 * SCSI Literals 178 */ 179 #define IPR_VENDOR_ID_LEN 8 180 #define IPR_PROD_ID_LEN 16 181 #define IPR_SERIAL_NUM_LEN 8 182 183 /* 184 * Hardware literals 185 */ 186 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff 187 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000 188 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28 189 #define IPR_GET_FMT2_BAR_SEL(mbx) \ 190 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT) 191 #define IPR_SDT_FMT2_BAR0_SEL 0x0 192 #define IPR_SDT_FMT2_BAR1_SEL 0x1 193 #define IPR_SDT_FMT2_BAR2_SEL 0x2 194 #define IPR_SDT_FMT2_BAR3_SEL 0x3 195 #define IPR_SDT_FMT2_BAR4_SEL 0x4 196 #define IPR_SDT_FMT2_BAR5_SEL 0x5 197 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8 198 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 199 #define IPR_DOORBELL 0x82800000 200 #define IPR_RUNTIME_RESET 0x40000000 201 202 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) 203 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) 204 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) 205 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5) 206 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6) 207 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7) 208 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27) 209 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28) 210 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29) 211 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30) 212 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31) 213 214 #define IPR_PCII_ERROR_INTERRUPTS \ 215 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \ 216 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR) 217 218 #define IPR_PCII_OPER_INTERRUPTS \ 219 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER) 220 221 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7) 222 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9) 223 224 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */ 225 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */ 226 227 /* 228 * Dump literals 229 */ 230 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024) 231 #define IPR_NUM_SDT_ENTRIES 511 232 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) 233 234 /* 235 * Misc literals 236 */ 237 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST 238 239 /* 240 * Adapter interface types 241 */ 242 243 struct ipr_res_addr { 244 u8 reserved; 245 u8 bus; 246 u8 target; 247 u8 lun; 248 #define IPR_GET_PHYS_LOC(res_addr) \ 249 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun) 250 }__attribute__((packed, aligned (4))); 251 252 struct ipr_std_inq_vpids { 253 u8 vendor_id[IPR_VENDOR_ID_LEN]; 254 u8 product_id[IPR_PROD_ID_LEN]; 255 }__attribute__((packed)); 256 257 struct ipr_vpd { 258 struct ipr_std_inq_vpids vpids; 259 u8 sn[IPR_SERIAL_NUM_LEN]; 260 }__attribute__((packed)); 261 262 struct ipr_ext_vpd { 263 struct ipr_vpd vpd; 264 __be32 wwid[2]; 265 }__attribute__((packed)); 266 267 struct ipr_std_inq_data { 268 u8 peri_qual_dev_type; 269 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5) 270 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F) 271 272 u8 removeable_medium_rsvd; 273 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80 274 275 #define IPR_IS_DASD_DEVICE(std_inq) \ 276 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \ 277 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM)) 278 279 #define IPR_IS_SES_DEVICE(std_inq) \ 280 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE) 281 282 u8 version; 283 u8 aen_naca_fmt; 284 u8 additional_len; 285 u8 sccs_rsvd; 286 u8 bq_enc_multi; 287 u8 sync_cmdq_flags; 288 289 struct ipr_std_inq_vpids vpids; 290 291 u8 ros_rsvd_ram_rsvd[4]; 292 293 u8 serial_num[IPR_SERIAL_NUM_LEN]; 294 }__attribute__ ((packed)); 295 296 struct ipr_config_table_entry { 297 u8 service_level; 298 u8 array_id; 299 u8 flags; 300 #define IPR_IS_IOA_RESOURCE 0x80 301 #define IPR_IS_ARRAY_MEMBER 0x20 302 #define IPR_IS_HOT_SPARE 0x10 303 304 u8 rsvd_subtype; 305 #define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f) 306 #define IPR_SUBTYPE_AF_DASD 0 307 #define IPR_SUBTYPE_GENERIC_SCSI 1 308 #define IPR_SUBTYPE_VOLUME_SET 2 309 310 #define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4) 311 #define IPR_QUEUE_FROZEN_MODEL 0 312 #define IPR_QUEUE_NACA_MODEL 1 313 314 struct ipr_res_addr res_addr; 315 __be32 res_handle; 316 __be32 reserved4[2]; 317 struct ipr_std_inq_data std_inq_data; 318 }__attribute__ ((packed, aligned (4))); 319 320 struct ipr_config_table_hdr { 321 u8 num_entries; 322 u8 flags; 323 #define IPR_UCODE_DOWNLOAD_REQ 0x10 324 __be16 reserved; 325 }__attribute__((packed, aligned (4))); 326 327 struct ipr_config_table { 328 struct ipr_config_table_hdr hdr; 329 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS]; 330 }__attribute__((packed, aligned (4))); 331 332 struct ipr_hostrcb_cfg_ch_not { 333 struct ipr_config_table_entry cfgte; 334 u8 reserved[936]; 335 }__attribute__((packed, aligned (4))); 336 337 struct ipr_supported_device { 338 __be16 data_length; 339 u8 reserved; 340 u8 num_records; 341 struct ipr_std_inq_vpids vpids; 342 u8 reserved2[16]; 343 }__attribute__((packed, aligned (4))); 344 345 /* Command packet structure */ 346 struct ipr_cmd_pkt { 347 __be16 reserved; /* Reserved by IOA */ 348 u8 request_type; 349 #define IPR_RQTYPE_SCSICDB 0x00 350 #define IPR_RQTYPE_IOACMD 0x01 351 #define IPR_RQTYPE_HCAM 0x02 352 353 u8 luntar_luntrn; 354 355 u8 flags_hi; 356 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80 357 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20 358 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10 359 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08 360 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04 361 362 u8 flags_lo; 363 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20 364 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10 365 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00 366 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02 367 #define IPR_FLAGS_LO_ORDERED_TASK 0x04 368 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06 369 #define IPR_FLAGS_LO_ACA_TASK 0x08 370 371 u8 cdb[16]; 372 __be16 timeout; 373 }__attribute__ ((packed, aligned(4))); 374 375 /* IOA Request Control Block 128 bytes */ 376 struct ipr_ioarcb { 377 __be32 ioarcb_host_pci_addr; 378 __be32 reserved; 379 __be32 res_handle; 380 __be32 host_response_handle; 381 __be32 reserved1; 382 __be32 reserved2; 383 __be32 reserved3; 384 385 __be32 write_data_transfer_length; 386 __be32 read_data_transfer_length; 387 __be32 write_ioadl_addr; 388 __be32 write_ioadl_len; 389 __be32 read_ioadl_addr; 390 __be32 read_ioadl_len; 391 392 __be32 ioasa_host_pci_addr; 393 __be16 ioasa_len; 394 __be16 reserved4; 395 396 struct ipr_cmd_pkt cmd_pkt; 397 398 __be32 add_cmd_parms_len; 399 __be32 add_cmd_parms[10]; 400 }__attribute__((packed, aligned (4))); 401 402 struct ipr_ioadl_desc { 403 __be32 flags_and_data_len; 404 #define IPR_IOADL_FLAGS_MASK 0xff000000 405 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK) 406 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff 407 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK) 408 #define IPR_IOADL_FLAGS_READ 0x48000000 409 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000 410 #define IPR_IOADL_FLAGS_WRITE 0x68000000 411 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000 412 #define IPR_IOADL_FLAGS_LAST 0x01000000 413 414 __be32 address; 415 }__attribute__((packed, aligned (8))); 416 417 struct ipr_ioasa_vset { 418 __be32 failing_lba_hi; 419 __be32 failing_lba_lo; 420 __be32 reserved; 421 }__attribute__((packed, aligned (4))); 422 423 struct ipr_ioasa_af_dasd { 424 __be32 failing_lba; 425 __be32 reserved[2]; 426 }__attribute__((packed, aligned (4))); 427 428 struct ipr_ioasa_gpdd { 429 u8 end_state; 430 u8 bus_phase; 431 __be16 reserved; 432 __be32 ioa_data[2]; 433 }__attribute__((packed, aligned (4))); 434 435 struct ipr_auto_sense { 436 __be16 auto_sense_len; 437 __be16 ioa_data_len; 438 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)]; 439 }; 440 441 struct ipr_ioasa { 442 __be32 ioasc; 443 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) 444 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) 445 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) 446 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) 447 448 __be16 ret_stat_len; /* Length of the returned IOASA */ 449 450 __be16 avail_stat_len; /* Total Length of status available. */ 451 452 __be32 residual_data_len; /* number of bytes in the host data */ 453 /* buffers that were not used by the IOARCB command. */ 454 455 __be32 ilid; 456 #define IPR_NO_ILID 0 457 #define IPR_DRIVER_ILID 0xffffffff 458 459 __be32 fd_ioasc; 460 461 __be32 fd_phys_locator; 462 463 __be32 fd_res_handle; 464 465 __be32 ioasc_specific; /* status code specific field */ 466 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000 467 #define IPR_AUTOSENSE_VALID 0x40000000 468 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff 469 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8) 470 #define IPR_FIELD_POINTER_MASK 0x0000ffff 471 472 union { 473 struct ipr_ioasa_vset vset; 474 struct ipr_ioasa_af_dasd dasd; 475 struct ipr_ioasa_gpdd gpdd; 476 } u; 477 478 struct ipr_auto_sense auto_sense; 479 }__attribute__((packed, aligned (4))); 480 481 struct ipr_mode_parm_hdr { 482 u8 length; 483 u8 medium_type; 484 u8 device_spec_parms; 485 u8 block_desc_len; 486 }__attribute__((packed)); 487 488 struct ipr_mode_pages { 489 struct ipr_mode_parm_hdr hdr; 490 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)]; 491 }__attribute__((packed)); 492 493 struct ipr_mode_page_hdr { 494 u8 ps_page_code; 495 #define IPR_MODE_PAGE_PS 0x80 496 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F) 497 u8 page_length; 498 }__attribute__ ((packed)); 499 500 struct ipr_dev_bus_entry { 501 struct ipr_res_addr res_addr; 502 u8 flags; 503 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80 504 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40 505 #define IPR_SCSI_ATTR_QAS_MASK 0xC0 506 #define IPR_SCSI_ATTR_ENABLE_TM 0x20 507 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10 508 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08 509 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04 510 511 u8 scsi_id; 512 u8 bus_width; 513 u8 extended_reset_delay; 514 #define IPR_EXTENDED_RESET_DELAY 7 515 516 __be32 max_xfer_rate; 517 518 u8 spinup_delay; 519 u8 reserved3; 520 __be16 reserved4; 521 }__attribute__((packed, aligned (4))); 522 523 struct ipr_mode_page28 { 524 struct ipr_mode_page_hdr hdr; 525 u8 num_entries; 526 u8 entry_length; 527 struct ipr_dev_bus_entry bus[0]; 528 }__attribute__((packed)); 529 530 struct ipr_ioa_vpd { 531 struct ipr_std_inq_data std_inq_data; 532 u8 ascii_part_num[12]; 533 u8 reserved[40]; 534 u8 ascii_plant_code[4]; 535 }__attribute__((packed)); 536 537 struct ipr_inquiry_page3 { 538 u8 peri_qual_dev_type; 539 u8 page_code; 540 u8 reserved1; 541 u8 page_length; 542 u8 ascii_len; 543 u8 reserved2[3]; 544 u8 load_id[4]; 545 u8 major_release; 546 u8 card_type; 547 u8 minor_release[2]; 548 u8 ptf_number[4]; 549 u8 patch_number[4]; 550 }__attribute__((packed)); 551 552 #define IPR_INQUIRY_PAGE0_ENTRIES 20 553 struct ipr_inquiry_page0 { 554 u8 peri_qual_dev_type; 555 u8 page_code; 556 u8 reserved1; 557 u8 len; 558 u8 page[IPR_INQUIRY_PAGE0_ENTRIES]; 559 }__attribute__((packed)); 560 561 struct ipr_hostrcb_device_data_entry { 562 struct ipr_vpd vpd; 563 struct ipr_res_addr dev_res_addr; 564 struct ipr_vpd new_vpd; 565 struct ipr_vpd ioa_last_with_dev_vpd; 566 struct ipr_vpd cfc_last_with_dev_vpd; 567 __be32 ioa_data[5]; 568 }__attribute__((packed, aligned (4))); 569 570 struct ipr_hostrcb_device_data_entry_enhanced { 571 struct ipr_ext_vpd vpd; 572 u8 ccin[4]; 573 struct ipr_res_addr dev_res_addr; 574 struct ipr_ext_vpd new_vpd; 575 u8 new_ccin[4]; 576 struct ipr_ext_vpd ioa_last_with_dev_vpd; 577 struct ipr_ext_vpd cfc_last_with_dev_vpd; 578 }__attribute__((packed, aligned (4))); 579 580 struct ipr_hostrcb_array_data_entry { 581 struct ipr_vpd vpd; 582 struct ipr_res_addr expected_dev_res_addr; 583 struct ipr_res_addr dev_res_addr; 584 }__attribute__((packed, aligned (4))); 585 586 struct ipr_hostrcb_array_data_entry_enhanced { 587 struct ipr_ext_vpd vpd; 588 u8 ccin[4]; 589 struct ipr_res_addr expected_dev_res_addr; 590 struct ipr_res_addr dev_res_addr; 591 }__attribute__((packed, aligned (4))); 592 593 struct ipr_hostrcb_type_ff_error { 594 __be32 ioa_data[502]; 595 }__attribute__((packed, aligned (4))); 596 597 struct ipr_hostrcb_type_01_error { 598 __be32 seek_counter; 599 __be32 read_counter; 600 u8 sense_data[32]; 601 __be32 ioa_data[236]; 602 }__attribute__((packed, aligned (4))); 603 604 struct ipr_hostrcb_type_02_error { 605 struct ipr_vpd ioa_vpd; 606 struct ipr_vpd cfc_vpd; 607 struct ipr_vpd ioa_last_attached_to_cfc_vpd; 608 struct ipr_vpd cfc_last_attached_to_ioa_vpd; 609 __be32 ioa_data[3]; 610 }__attribute__((packed, aligned (4))); 611 612 struct ipr_hostrcb_type_12_error { 613 struct ipr_ext_vpd ioa_vpd; 614 struct ipr_ext_vpd cfc_vpd; 615 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd; 616 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd; 617 __be32 ioa_data[3]; 618 }__attribute__((packed, aligned (4))); 619 620 struct ipr_hostrcb_type_03_error { 621 struct ipr_vpd ioa_vpd; 622 struct ipr_vpd cfc_vpd; 623 __be32 errors_detected; 624 __be32 errors_logged; 625 u8 ioa_data[12]; 626 struct ipr_hostrcb_device_data_entry dev[3]; 627 }__attribute__((packed, aligned (4))); 628 629 struct ipr_hostrcb_type_13_error { 630 struct ipr_ext_vpd ioa_vpd; 631 struct ipr_ext_vpd cfc_vpd; 632 __be32 errors_detected; 633 __be32 errors_logged; 634 struct ipr_hostrcb_device_data_entry_enhanced dev[3]; 635 }__attribute__((packed, aligned (4))); 636 637 struct ipr_hostrcb_type_04_error { 638 struct ipr_vpd ioa_vpd; 639 struct ipr_vpd cfc_vpd; 640 u8 ioa_data[12]; 641 struct ipr_hostrcb_array_data_entry array_member[10]; 642 __be32 exposed_mode_adn; 643 __be32 array_id; 644 struct ipr_vpd incomp_dev_vpd; 645 __be32 ioa_data2; 646 struct ipr_hostrcb_array_data_entry array_member2[8]; 647 struct ipr_res_addr last_func_vset_res_addr; 648 u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; 649 u8 protection_level[8]; 650 }__attribute__((packed, aligned (4))); 651 652 struct ipr_hostrcb_type_14_error { 653 struct ipr_ext_vpd ioa_vpd; 654 struct ipr_ext_vpd cfc_vpd; 655 __be32 exposed_mode_adn; 656 __be32 array_id; 657 struct ipr_res_addr last_func_vset_res_addr; 658 u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; 659 u8 protection_level[8]; 660 __be32 num_entries; 661 struct ipr_hostrcb_array_data_entry_enhanced array_member[18]; 662 }__attribute__((packed, aligned (4))); 663 664 struct ipr_hostrcb_type_07_error { 665 u8 failure_reason[64]; 666 struct ipr_vpd vpd; 667 u32 data[222]; 668 }__attribute__((packed, aligned (4))); 669 670 struct ipr_hostrcb_type_17_error { 671 u8 failure_reason[64]; 672 struct ipr_ext_vpd vpd; 673 u32 data[476]; 674 }__attribute__((packed, aligned (4))); 675 676 struct ipr_hostrcb_error { 677 __be32 failing_dev_ioasc; 678 struct ipr_res_addr failing_dev_res_addr; 679 __be32 failing_dev_res_handle; 680 __be32 prc; 681 union { 682 struct ipr_hostrcb_type_ff_error type_ff_error; 683 struct ipr_hostrcb_type_01_error type_01_error; 684 struct ipr_hostrcb_type_02_error type_02_error; 685 struct ipr_hostrcb_type_03_error type_03_error; 686 struct ipr_hostrcb_type_04_error type_04_error; 687 struct ipr_hostrcb_type_07_error type_07_error; 688 struct ipr_hostrcb_type_12_error type_12_error; 689 struct ipr_hostrcb_type_13_error type_13_error; 690 struct ipr_hostrcb_type_14_error type_14_error; 691 struct ipr_hostrcb_type_17_error type_17_error; 692 } u; 693 }__attribute__((packed, aligned (4))); 694 695 struct ipr_hostrcb_raw { 696 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)]; 697 }__attribute__((packed, aligned (4))); 698 699 struct ipr_hcam { 700 u8 op_code; 701 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1 702 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2 703 704 u8 notify_type; 705 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00 706 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01 707 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02 708 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10 709 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11 710 711 u8 notifications_lost; 712 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0 713 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80 714 715 u8 flags; 716 #define IPR_HOSTRCB_INTERNAL_OPER 0x80 717 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40 718 719 u8 overlay_id; 720 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01 721 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02 722 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03 723 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04 724 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06 725 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07 726 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12 727 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13 728 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14 729 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16 730 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17 731 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF 732 733 u8 reserved1[3]; 734 __be32 ilid; 735 __be32 time_since_last_ioa_reset; 736 __be32 reserved2; 737 __be32 length; 738 739 union { 740 struct ipr_hostrcb_error error; 741 struct ipr_hostrcb_cfg_ch_not ccn; 742 struct ipr_hostrcb_raw raw; 743 } u; 744 }__attribute__((packed, aligned (4))); 745 746 struct ipr_hostrcb { 747 struct ipr_hcam hcam; 748 dma_addr_t hostrcb_dma; 749 struct list_head queue; 750 }; 751 752 /* IPR smart dump table structures */ 753 struct ipr_sdt_entry { 754 __be32 bar_str_offset; 755 __be32 end_offset; 756 u8 entry_byte; 757 u8 reserved[3]; 758 759 u8 flags; 760 #define IPR_SDT_ENDIAN 0x80 761 #define IPR_SDT_VALID_ENTRY 0x20 762 763 u8 resv; 764 __be16 priority; 765 }__attribute__((packed, aligned (4))); 766 767 struct ipr_sdt_header { 768 __be32 state; 769 __be32 num_entries; 770 __be32 num_entries_used; 771 __be32 dump_size; 772 }__attribute__((packed, aligned (4))); 773 774 struct ipr_sdt { 775 struct ipr_sdt_header hdr; 776 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES]; 777 }__attribute__((packed, aligned (4))); 778 779 struct ipr_uc_sdt { 780 struct ipr_sdt_header hdr; 781 struct ipr_sdt_entry entry[1]; 782 }__attribute__((packed, aligned (4))); 783 784 /* 785 * Driver types 786 */ 787 struct ipr_bus_attributes { 788 u8 bus; 789 u8 qas_enabled; 790 u8 bus_width; 791 u8 reserved; 792 u32 max_xfer_rate; 793 }; 794 795 struct ipr_resource_entry { 796 struct ipr_config_table_entry cfgte; 797 u8 needs_sync_complete:1; 798 u8 in_erp:1; 799 u8 add_to_ml:1; 800 u8 del_from_ml:1; 801 u8 resetting_device:1; 802 803 struct scsi_device *sdev; 804 struct list_head queue; 805 }; 806 807 struct ipr_resource_hdr { 808 u16 num_entries; 809 u16 reserved; 810 }; 811 812 struct ipr_resource_table { 813 struct ipr_resource_hdr hdr; 814 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS]; 815 }; 816 817 struct ipr_misc_cbs { 818 struct ipr_ioa_vpd ioa_vpd; 819 struct ipr_inquiry_page0 page0_data; 820 struct ipr_inquiry_page3 page3_data; 821 struct ipr_mode_pages mode_pages; 822 struct ipr_supported_device supp_dev; 823 }; 824 825 struct ipr_interrupt_offsets { 826 unsigned long set_interrupt_mask_reg; 827 unsigned long clr_interrupt_mask_reg; 828 unsigned long sense_interrupt_mask_reg; 829 unsigned long clr_interrupt_reg; 830 831 unsigned long sense_interrupt_reg; 832 unsigned long ioarrin_reg; 833 unsigned long sense_uproc_interrupt_reg; 834 unsigned long set_uproc_interrupt_reg; 835 unsigned long clr_uproc_interrupt_reg; 836 }; 837 838 struct ipr_interrupts { 839 void __iomem *set_interrupt_mask_reg; 840 void __iomem *clr_interrupt_mask_reg; 841 void __iomem *sense_interrupt_mask_reg; 842 void __iomem *clr_interrupt_reg; 843 844 void __iomem *sense_interrupt_reg; 845 void __iomem *ioarrin_reg; 846 void __iomem *sense_uproc_interrupt_reg; 847 void __iomem *set_uproc_interrupt_reg; 848 void __iomem *clr_uproc_interrupt_reg; 849 }; 850 851 struct ipr_chip_cfg_t { 852 u32 mailbox; 853 u8 cache_line_size; 854 struct ipr_interrupt_offsets regs; 855 }; 856 857 struct ipr_chip_t { 858 u16 vendor; 859 u16 device; 860 const struct ipr_chip_cfg_t *cfg; 861 }; 862 863 enum ipr_shutdown_type { 864 IPR_SHUTDOWN_NORMAL = 0x00, 865 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40, 866 IPR_SHUTDOWN_ABBREV = 0x80, 867 IPR_SHUTDOWN_NONE = 0x100 868 }; 869 870 struct ipr_trace_entry { 871 u32 time; 872 873 u8 op_code; 874 u8 type; 875 #define IPR_TRACE_START 0x00 876 #define IPR_TRACE_FINISH 0xff 877 u16 cmd_index; 878 879 __be32 res_handle; 880 union { 881 u32 ioasc; 882 u32 add_data; 883 u32 res_addr; 884 } u; 885 }; 886 887 struct ipr_sglist { 888 u32 order; 889 u32 num_sg; 890 u32 num_dma_sg; 891 u32 buffer_len; 892 struct scatterlist scatterlist[1]; 893 }; 894 895 enum ipr_sdt_state { 896 INACTIVE, 897 WAIT_FOR_DUMP, 898 GET_DUMP, 899 ABORT_DUMP, 900 DUMP_OBTAINED 901 }; 902 903 enum ipr_cache_state { 904 CACHE_NONE, 905 CACHE_DISABLED, 906 CACHE_ENABLED, 907 CACHE_INVALID 908 }; 909 910 /* Per-controller data */ 911 struct ipr_ioa_cfg { 912 char eye_catcher[8]; 913 #define IPR_EYECATCHER "iprcfg" 914 915 struct list_head queue; 916 917 u8 allow_interrupts:1; 918 u8 in_reset_reload:1; 919 u8 in_ioa_bringdown:1; 920 u8 ioa_unit_checked:1; 921 u8 ioa_is_dead:1; 922 u8 dump_taken:1; 923 u8 allow_cmds:1; 924 u8 allow_ml_add_del:1; 925 u8 needs_hard_reset:1; 926 927 enum ipr_cache_state cache_state; 928 u16 type; /* CCIN of the card */ 929 930 u8 log_level; 931 #define IPR_MAX_LOG_LEVEL 4 932 #define IPR_DEFAULT_LOG_LEVEL 2 933 934 #define IPR_NUM_TRACE_INDEX_BITS 8 935 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS) 936 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES) 937 char trace_start[8]; 938 #define IPR_TRACE_START_LABEL "trace" 939 struct ipr_trace_entry *trace; 940 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS; 941 942 /* 943 * Queue for free command blocks 944 */ 945 char ipr_free_label[8]; 946 #define IPR_FREEQ_LABEL "free-q" 947 struct list_head free_q; 948 949 /* 950 * Queue for command blocks outstanding to the adapter 951 */ 952 char ipr_pending_label[8]; 953 #define IPR_PENDQ_LABEL "pend-q" 954 struct list_head pending_q; 955 956 char cfg_table_start[8]; 957 #define IPR_CFG_TBL_START "cfg" 958 struct ipr_config_table *cfg_table; 959 dma_addr_t cfg_table_dma; 960 961 char resource_table_label[8]; 962 #define IPR_RES_TABLE_LABEL "res_tbl" 963 struct ipr_resource_entry *res_entries; 964 struct list_head free_res_q; 965 struct list_head used_res_q; 966 967 char ipr_hcam_label[8]; 968 #define IPR_HCAM_LABEL "hcams" 969 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS]; 970 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS]; 971 struct list_head hostrcb_free_q; 972 struct list_head hostrcb_pending_q; 973 974 __be32 *host_rrq; 975 dma_addr_t host_rrq_dma; 976 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc 977 #define IPR_HRRQ_RESP_BIT_SET 0x00000002 978 #define IPR_HRRQ_TOGGLE_BIT 0x00000001 979 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2 980 volatile __be32 *hrrq_start; 981 volatile __be32 *hrrq_end; 982 volatile __be32 *hrrq_curr; 983 volatile u32 toggle_bit; 984 985 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES]; 986 987 const struct ipr_chip_cfg_t *chip_cfg; 988 989 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */ 990 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */ 991 void __iomem *ioa_mailbox; 992 struct ipr_interrupts regs; 993 994 u16 saved_pcix_cmd_reg; 995 u16 reset_retries; 996 997 u32 errors_logged; 998 u32 doorbell; 999 1000 struct Scsi_Host *host; 1001 struct pci_dev *pdev; 1002 struct ipr_sglist *ucode_sglist; 1003 u8 saved_mode_page_len; 1004 1005 struct work_struct work_q; 1006 1007 wait_queue_head_t reset_wait_q; 1008 1009 struct ipr_dump *dump; 1010 enum ipr_sdt_state sdt_state; 1011 1012 struct ipr_misc_cbs *vpd_cbs; 1013 dma_addr_t vpd_cbs_dma; 1014 1015 struct pci_pool *ipr_cmd_pool; 1016 1017 struct ipr_cmnd *reset_cmd; 1018 1019 char ipr_cmd_label[8]; 1020 #define IPR_CMD_LABEL "ipr_cmnd" 1021 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS]; 1022 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS]; 1023 }; 1024 1025 struct ipr_cmnd { 1026 struct ipr_ioarcb ioarcb; 1027 struct ipr_ioasa ioasa; 1028 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES]; 1029 struct list_head queue; 1030 struct scsi_cmnd *scsi_cmd; 1031 struct completion completion; 1032 struct timer_list timer; 1033 void (*done) (struct ipr_cmnd *); 1034 int (*job_step) (struct ipr_cmnd *); 1035 int (*job_step_failed) (struct ipr_cmnd *); 1036 u16 cmd_index; 1037 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; 1038 dma_addr_t sense_buffer_dma; 1039 unsigned short dma_use_sg; 1040 dma_addr_t dma_handle; 1041 struct ipr_cmnd *sibling; 1042 union { 1043 enum ipr_shutdown_type shutdown_type; 1044 struct ipr_hostrcb *hostrcb; 1045 unsigned long time_left; 1046 unsigned long scratch; 1047 struct ipr_resource_entry *res; 1048 struct scsi_device *sdev; 1049 } u; 1050 1051 struct ipr_ioa_cfg *ioa_cfg; 1052 }; 1053 1054 struct ipr_ses_table_entry { 1055 char product_id[17]; 1056 char compare_product_id_byte[17]; 1057 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */ 1058 }; 1059 1060 struct ipr_dump_header { 1061 u32 eye_catcher; 1062 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 1063 u32 len; 1064 u32 num_entries; 1065 u32 first_entry_offset; 1066 u32 status; 1067 #define IPR_DUMP_STATUS_SUCCESS 0 1068 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2 1069 #define IPR_DUMP_STATUS_FAILED 0xffffffff 1070 u32 os; 1071 #define IPR_DUMP_OS_LINUX 0x4C4E5558 1072 u32 driver_name; 1073 #define IPR_DUMP_DRIVER_NAME 0x49505232 1074 }__attribute__((packed, aligned (4))); 1075 1076 struct ipr_dump_entry_header { 1077 u32 eye_catcher; 1078 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 1079 u32 len; 1080 u32 num_elems; 1081 u32 offset; 1082 u32 data_type; 1083 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349 1084 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41 1085 u32 id; 1086 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131 1087 #define IPR_DUMP_LOCATION_ID 0x4C4F4341 1088 #define IPR_DUMP_TRACE_ID 0x54524143 1089 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652 1090 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045 1091 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342 1092 #define IPR_DUMP_PEND_OPS 0x414F5053 1093 u32 status; 1094 }__attribute__((packed, aligned (4))); 1095 1096 struct ipr_dump_location_entry { 1097 struct ipr_dump_entry_header hdr; 1098 u8 location[BUS_ID_SIZE]; 1099 }__attribute__((packed)); 1100 1101 struct ipr_dump_trace_entry { 1102 struct ipr_dump_entry_header hdr; 1103 u32 trace[IPR_TRACE_SIZE / sizeof(u32)]; 1104 }__attribute__((packed, aligned (4))); 1105 1106 struct ipr_dump_version_entry { 1107 struct ipr_dump_entry_header hdr; 1108 u8 version[sizeof(IPR_DRIVER_VERSION)]; 1109 }; 1110 1111 struct ipr_dump_ioa_type_entry { 1112 struct ipr_dump_entry_header hdr; 1113 u32 type; 1114 u32 fw_version; 1115 }; 1116 1117 struct ipr_driver_dump { 1118 struct ipr_dump_header hdr; 1119 struct ipr_dump_version_entry version_entry; 1120 struct ipr_dump_location_entry location_entry; 1121 struct ipr_dump_ioa_type_entry ioa_type_entry; 1122 struct ipr_dump_trace_entry trace_entry; 1123 }__attribute__((packed)); 1124 1125 struct ipr_ioa_dump { 1126 struct ipr_dump_entry_header hdr; 1127 struct ipr_sdt sdt; 1128 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES]; 1129 u32 reserved; 1130 u32 next_page_index; 1131 u32 page_offset; 1132 u32 format; 1133 #define IPR_SDT_FMT2 2 1134 #define IPR_SDT_UNKNOWN 3 1135 }__attribute__((packed, aligned (4))); 1136 1137 struct ipr_dump { 1138 struct kref kref; 1139 struct ipr_ioa_cfg *ioa_cfg; 1140 struct ipr_driver_dump driver_dump; 1141 struct ipr_ioa_dump ioa_dump; 1142 }; 1143 1144 struct ipr_error_table_t { 1145 u32 ioasc; 1146 int log_ioasa; 1147 int log_hcam; 1148 char *error; 1149 }; 1150 1151 struct ipr_software_inq_lid_info { 1152 __be32 load_id; 1153 __be32 timestamp[3]; 1154 }__attribute__((packed, aligned (4))); 1155 1156 struct ipr_ucode_image_header { 1157 __be32 header_length; 1158 __be32 lid_table_offset; 1159 u8 major_release; 1160 u8 card_type; 1161 u8 minor_release[2]; 1162 u8 reserved[20]; 1163 char eyecatcher[16]; 1164 __be32 num_lids; 1165 struct ipr_software_inq_lid_info lid[1]; 1166 }__attribute__((packed, aligned (4))); 1167 1168 /* 1169 * Macros 1170 */ 1171 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; } 1172 1173 #ifdef CONFIG_SCSI_IPR_TRACE 1174 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr) 1175 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) 1176 #else 1177 #define ipr_create_trace_file(kobj, attr) 0 1178 #define ipr_remove_trace_file(kobj, attr) do { } while(0) 1179 #endif 1180 1181 #ifdef CONFIG_SCSI_IPR_DUMP 1182 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr) 1183 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) 1184 #else 1185 #define ipr_create_dump_file(kobj, attr) 0 1186 #define ipr_remove_dump_file(kobj, attr) do { } while(0) 1187 #endif 1188 1189 /* 1190 * Error logging macros 1191 */ 1192 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__) 1193 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) 1194 #define ipr_crit(...) printk(KERN_CRIT IPR_NAME ": "__VA_ARGS__) 1195 #define ipr_warn(...) printk(KERN_WARNING IPR_NAME": "__VA_ARGS__) 1196 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) 1197 1198 #define ipr_sdev_printk(level, sdev, fmt, args...) \ 1199 sdev_printk(level, sdev, fmt, ## args) 1200 1201 #define ipr_sdev_err(sdev, fmt, ...) \ 1202 ipr_sdev_printk(KERN_ERR, sdev, fmt, ##__VA_ARGS__) 1203 1204 #define ipr_sdev_info(sdev, fmt, ...) \ 1205 ipr_sdev_printk(KERN_INFO, sdev, fmt, ##__VA_ARGS__) 1206 1207 #define ipr_sdev_dbg(sdev, fmt, ...) \ 1208 IPR_DBG_CMD(ipr_sdev_printk(KERN_INFO, sdev, fmt, ##__VA_ARGS__)) 1209 1210 #define ipr_res_printk(level, ioa_cfg, res, fmt, ...) \ 1211 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, ioa_cfg->host->host_no, \ 1212 res.bus, res.target, res.lun, ##__VA_ARGS__) 1213 1214 #define ipr_res_err(ioa_cfg, res, fmt, ...) \ 1215 ipr_res_printk(KERN_ERR, ioa_cfg, res, fmt, ##__VA_ARGS__) 1216 #define ipr_res_dbg(ioa_cfg, res, fmt, ...) \ 1217 IPR_DBG_CMD(ipr_res_printk(KERN_INFO, ioa_cfg, res, fmt, ##__VA_ARGS__)) 1218 1219 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \ 1220 { \ 1221 if ((res).bus >= IPR_MAX_NUM_BUSES) { \ 1222 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \ 1223 } else { \ 1224 ipr_err(fmt": %d:%d:%d:%d\n", \ 1225 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \ 1226 (res).bus, (res).target, (res).lun); \ 1227 } \ 1228 } 1229 1230 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\ 1231 __FILE__, __FUNCTION__, __LINE__) 1232 1233 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __FUNCTION__)) 1234 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __FUNCTION__)) 1235 1236 #define ipr_err_separator \ 1237 ipr_err("----------------------------------------------------------\n") 1238 1239 1240 /* 1241 * Inlines 1242 */ 1243 1244 /** 1245 * ipr_is_ioa_resource - Determine if a resource is the IOA 1246 * @res: resource entry struct 1247 * 1248 * Return value: 1249 * 1 if IOA / 0 if not IOA 1250 **/ 1251 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) 1252 { 1253 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0; 1254 } 1255 1256 /** 1257 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD 1258 * @res: resource entry struct 1259 * 1260 * Return value: 1261 * 1 if AF DASD / 0 if not AF DASD 1262 **/ 1263 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) 1264 { 1265 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) && 1266 !ipr_is_ioa_resource(res) && 1267 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD) 1268 return 1; 1269 else 1270 return 0; 1271 } 1272 1273 /** 1274 * ipr_is_vset_device - Determine if a resource is a VSET 1275 * @res: resource entry struct 1276 * 1277 * Return value: 1278 * 1 if VSET / 0 if not VSET 1279 **/ 1280 static inline int ipr_is_vset_device(struct ipr_resource_entry *res) 1281 { 1282 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) && 1283 !ipr_is_ioa_resource(res) && 1284 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET) 1285 return 1; 1286 else 1287 return 0; 1288 } 1289 1290 /** 1291 * ipr_is_gscsi - Determine if a resource is a generic scsi resource 1292 * @res: resource entry struct 1293 * 1294 * Return value: 1295 * 1 if GSCSI / 0 if not GSCSI 1296 **/ 1297 static inline int ipr_is_gscsi(struct ipr_resource_entry *res) 1298 { 1299 if (!ipr_is_ioa_resource(res) && 1300 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI) 1301 return 1; 1302 else 1303 return 0; 1304 } 1305 1306 /** 1307 * ipr_is_naca_model - Determine if a resource is using NACA queueing model 1308 * @res: resource entry struct 1309 * 1310 * Return value: 1311 * 1 if NACA queueing model / 0 if not NACA queueing model 1312 **/ 1313 static inline int ipr_is_naca_model(struct ipr_resource_entry *res) 1314 { 1315 if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL) 1316 return 1; 1317 return 0; 1318 } 1319 1320 /** 1321 * ipr_is_device - Determine if resource address is that of a device 1322 * @res_addr: resource address struct 1323 * 1324 * Return value: 1325 * 1 if AF / 0 if not AF 1326 **/ 1327 static inline int ipr_is_device(struct ipr_res_addr *res_addr) 1328 { 1329 if ((res_addr->bus < IPR_MAX_NUM_BUSES) && 1330 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) 1331 return 1; 1332 1333 return 0; 1334 } 1335 1336 /** 1337 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2 1338 * @sdt_word: SDT address 1339 * 1340 * Return value: 1341 * 1 if format 2 / 0 if not 1342 **/ 1343 static inline int ipr_sdt_is_fmt2(u32 sdt_word) 1344 { 1345 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word); 1346 1347 switch (bar_sel) { 1348 case IPR_SDT_FMT2_BAR0_SEL: 1349 case IPR_SDT_FMT2_BAR1_SEL: 1350 case IPR_SDT_FMT2_BAR2_SEL: 1351 case IPR_SDT_FMT2_BAR3_SEL: 1352 case IPR_SDT_FMT2_BAR4_SEL: 1353 case IPR_SDT_FMT2_BAR5_SEL: 1354 case IPR_SDT_FMT2_EXP_ROM_SEL: 1355 return 1; 1356 }; 1357 1358 return 0; 1359 } 1360 1361 #endif 1362