1 /* 2 * ipr.h -- driver for IBM Power Linux RAID adapters 3 * 4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation 5 * 6 * Copyright (C) 2003, 2004 IBM Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors 23 * that broke 64bit platforms. 24 */ 25 26 #ifndef _IPR_H 27 #define _IPR_H 28 29 #include <linux/types.h> 30 #include <linux/completion.h> 31 #include <linux/libata.h> 32 #include <linux/list.h> 33 #include <linux/kref.h> 34 #include <scsi/scsi.h> 35 #include <scsi/scsi_cmnd.h> 36 37 /* 38 * Literals 39 */ 40 #define IPR_DRIVER_VERSION "2.5.0" 41 #define IPR_DRIVER_DATE "(February 11, 2010)" 42 43 /* 44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding 45 * ops per device for devices not running tagged command queuing. 46 * This can be adjusted at runtime through sysfs device attributes. 47 */ 48 #define IPR_MAX_CMD_PER_LUN 6 49 #define IPR_MAX_CMD_PER_ATA_LUN 1 50 51 /* 52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of 53 * ops the mid-layer can send to the adapter. 54 */ 55 #define IPR_NUM_BASE_CMD_BLKS 100 56 57 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 58 59 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D 60 #define PCI_DEVICE_ID_IBM_CROC_ASIC_E2 0x034A 61 62 #define IPR_SUBS_DEV_ID_2780 0x0264 63 #define IPR_SUBS_DEV_ID_5702 0x0266 64 #define IPR_SUBS_DEV_ID_5703 0x0278 65 #define IPR_SUBS_DEV_ID_572E 0x028D 66 #define IPR_SUBS_DEV_ID_573E 0x02D3 67 #define IPR_SUBS_DEV_ID_573D 0x02D4 68 #define IPR_SUBS_DEV_ID_571A 0x02C0 69 #define IPR_SUBS_DEV_ID_571B 0x02BE 70 #define IPR_SUBS_DEV_ID_571E 0x02BF 71 #define IPR_SUBS_DEV_ID_571F 0x02D5 72 #define IPR_SUBS_DEV_ID_572A 0x02C1 73 #define IPR_SUBS_DEV_ID_572B 0x02C2 74 #define IPR_SUBS_DEV_ID_572F 0x02C3 75 #define IPR_SUBS_DEV_ID_574E 0x030A 76 #define IPR_SUBS_DEV_ID_575B 0x030D 77 #define IPR_SUBS_DEV_ID_575C 0x0338 78 #define IPR_SUBS_DEV_ID_57B3 0x033A 79 #define IPR_SUBS_DEV_ID_57B7 0x0360 80 #define IPR_SUBS_DEV_ID_57B8 0x02C2 81 82 #define IPR_SUBS_DEV_ID_57B4 0x033B 83 #define IPR_SUBS_DEV_ID_57B2 0x035F 84 #define IPR_SUBS_DEV_ID_57C6 0x0357 85 86 #define IPR_SUBS_DEV_ID_57B5 0x033C 87 #define IPR_SUBS_DEV_ID_57CE 0x035E 88 #define IPR_SUBS_DEV_ID_57B1 0x0355 89 90 #define IPR_SUBS_DEV_ID_574D 0x0356 91 #define IPR_SUBS_DEV_ID_575D 0x035D 92 93 #define IPR_NAME "ipr" 94 95 /* 96 * Return codes 97 */ 98 #define IPR_RC_JOB_CONTINUE 1 99 #define IPR_RC_JOB_RETURN 2 100 101 /* 102 * IOASCs 103 */ 104 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 105 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000 106 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000 107 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00 108 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000 109 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500 110 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00 111 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF 112 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000 113 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000 114 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100 115 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000 116 #define IPR_IOASC_BUS_WAS_RESET 0x06290000 117 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000 118 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000 119 120 #define IPR_FIRST_DRIVER_IOASC 0x10000000 121 #define IPR_IOASC_IOA_WAS_RESET 0x10000001 122 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002 123 124 /* Driver data flags */ 125 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001 126 #define IPR_USE_PCI_WARM_RESET 0x00000002 127 128 #define IPR_DEFAULT_MAX_ERROR_DUMP 984 129 #define IPR_NUM_LOG_HCAMS 2 130 #define IPR_NUM_CFG_CHG_HCAMS 2 131 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) 132 133 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024 134 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff 135 136 #define IPR_MAX_NUM_TARGETS_PER_BUS 256 137 #define IPR_MAX_NUM_LUNS_PER_TARGET 256 138 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8 139 #define IPR_VSET_BUS 0xff 140 #define IPR_IOA_BUS 0xff 141 #define IPR_IOA_TARGET 0xff 142 #define IPR_IOA_LUN 0xff 143 #define IPR_MAX_NUM_BUSES 16 144 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES 145 146 #define IPR_NUM_RESET_RELOAD_RETRIES 3 147 148 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */ 149 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ 150 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4) 151 152 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS 153 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ 154 IPR_NUM_INTERNAL_CMD_BLKS) 155 156 #define IPR_MAX_PHYSICAL_DEVS 192 157 #define IPR_DEFAULT_SIS64_DEVS 1024 158 #define IPR_MAX_SIS64_DEVS 4096 159 160 #define IPR_MAX_SGLIST 64 161 #define IPR_IOA_MAX_SECTORS 32767 162 #define IPR_VSET_MAX_SECTORS 512 163 #define IPR_MAX_CDB_LEN 16 164 #define IPR_MAX_HRRQ_RETRIES 3 165 166 #define IPR_DEFAULT_BUS_WIDTH 16 167 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 168 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 169 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 170 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8)) 171 172 #define IPR_IOA_RES_HANDLE 0xffffffff 173 #define IPR_INVALID_RES_HANDLE 0 174 #define IPR_IOA_RES_ADDR 0x00ffffff 175 176 /* 177 * Adapter Commands 178 */ 179 #define IPR_QUERY_RSRC_STATE 0xC2 180 #define IPR_RESET_DEVICE 0xC3 181 #define IPR_RESET_TYPE_SELECT 0x80 182 #define IPR_LUN_RESET 0x40 183 #define IPR_TARGET_RESET 0x20 184 #define IPR_BUS_RESET 0x10 185 #define IPR_ATA_PHY_RESET 0x80 186 #define IPR_ID_HOST_RR_Q 0xC4 187 #define IPR_QUERY_IOA_CONFIG 0xC5 188 #define IPR_CANCEL_ALL_REQUESTS 0xCE 189 #define IPR_HOST_CONTROLLED_ASYNC 0xCF 190 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 191 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 192 #define IPR_SET_SUPPORTED_DEVICES 0xFB 193 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80 194 #define IPR_IOA_SHUTDOWN 0xF7 195 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 196 197 /* 198 * Timeouts 199 */ 200 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ) 201 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ) 202 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ) 203 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ) 204 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 205 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 206 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 207 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 208 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ) 209 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ) 210 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ) 211 #define IPR_OPERATIONAL_TIMEOUT (5 * 60) 212 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60) 213 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ) 214 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10) 215 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ) 216 #define IPR_PCI_RESET_TIMEOUT (HZ / 2) 217 #define IPR_DUMP_TIMEOUT (15 * HZ) 218 219 /* 220 * SCSI Literals 221 */ 222 #define IPR_VENDOR_ID_LEN 8 223 #define IPR_PROD_ID_LEN 16 224 #define IPR_SERIAL_NUM_LEN 8 225 226 /* 227 * Hardware literals 228 */ 229 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff 230 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000 231 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28 232 #define IPR_GET_FMT2_BAR_SEL(mbx) \ 233 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT) 234 #define IPR_SDT_FMT2_BAR0_SEL 0x0 235 #define IPR_SDT_FMT2_BAR1_SEL 0x1 236 #define IPR_SDT_FMT2_BAR2_SEL 0x2 237 #define IPR_SDT_FMT2_BAR3_SEL 0x3 238 #define IPR_SDT_FMT2_BAR4_SEL 0x4 239 #define IPR_SDT_FMT2_BAR5_SEL 0x5 240 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8 241 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 242 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3 243 #define IPR_DOORBELL 0x82800000 244 #define IPR_RUNTIME_RESET 0x40000000 245 246 #define IPR_IPL_INIT_MIN_STAGE_TIME 5 247 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0 248 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000 249 #define IPR_IPL_INIT_STAGE_MASK 0xff000000 250 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff 251 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0) 252 253 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) 254 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) 255 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) 256 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5) 257 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6) 258 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7) 259 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27) 260 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28) 261 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29) 262 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30) 263 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31) 264 265 #define IPR_PCII_ERROR_INTERRUPTS \ 266 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \ 267 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR) 268 269 #define IPR_PCII_OPER_INTERRUPTS \ 270 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER) 271 272 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7) 273 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9) 274 275 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */ 276 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */ 277 278 /* 279 * Dump literals 280 */ 281 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024) 282 #define IPR_NUM_SDT_ENTRIES 511 283 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) 284 285 /* 286 * Misc literals 287 */ 288 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST 289 290 /* 291 * Adapter interface types 292 */ 293 294 struct ipr_res_addr { 295 u8 reserved; 296 u8 bus; 297 u8 target; 298 u8 lun; 299 #define IPR_GET_PHYS_LOC(res_addr) \ 300 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun) 301 }__attribute__((packed, aligned (4))); 302 303 struct ipr_std_inq_vpids { 304 u8 vendor_id[IPR_VENDOR_ID_LEN]; 305 u8 product_id[IPR_PROD_ID_LEN]; 306 }__attribute__((packed)); 307 308 struct ipr_vpd { 309 struct ipr_std_inq_vpids vpids; 310 u8 sn[IPR_SERIAL_NUM_LEN]; 311 }__attribute__((packed)); 312 313 struct ipr_ext_vpd { 314 struct ipr_vpd vpd; 315 __be32 wwid[2]; 316 }__attribute__((packed)); 317 318 struct ipr_std_inq_data { 319 u8 peri_qual_dev_type; 320 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5) 321 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F) 322 323 u8 removeable_medium_rsvd; 324 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80 325 326 #define IPR_IS_DASD_DEVICE(std_inq) \ 327 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \ 328 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM)) 329 330 #define IPR_IS_SES_DEVICE(std_inq) \ 331 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE) 332 333 u8 version; 334 u8 aen_naca_fmt; 335 u8 additional_len; 336 u8 sccs_rsvd; 337 u8 bq_enc_multi; 338 u8 sync_cmdq_flags; 339 340 struct ipr_std_inq_vpids vpids; 341 342 u8 ros_rsvd_ram_rsvd[4]; 343 344 u8 serial_num[IPR_SERIAL_NUM_LEN]; 345 }__attribute__ ((packed)); 346 347 #define IPR_RES_TYPE_AF_DASD 0x00 348 #define IPR_RES_TYPE_GENERIC_SCSI 0x01 349 #define IPR_RES_TYPE_VOLUME_SET 0x02 350 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03 351 #define IPR_RES_TYPE_GENERIC_ATA 0x04 352 #define IPR_RES_TYPE_ARRAY 0x05 353 #define IPR_RES_TYPE_IOAFP 0xff 354 355 struct ipr_config_table_entry { 356 u8 proto; 357 #define IPR_PROTO_SATA 0x02 358 #define IPR_PROTO_SATA_ATAPI 0x03 359 #define IPR_PROTO_SAS_STP 0x06 360 #define IPR_PROTO_SAS_STP_ATAPI 0x07 361 u8 array_id; 362 u8 flags; 363 #define IPR_IS_IOA_RESOURCE 0x80 364 u8 rsvd_subtype; 365 366 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4) 367 #define IPR_QUEUE_FROZEN_MODEL 0 368 #define IPR_QUEUE_NACA_MODEL 1 369 370 struct ipr_res_addr res_addr; 371 __be32 res_handle; 372 __be32 reserved4[2]; 373 struct ipr_std_inq_data std_inq_data; 374 }__attribute__ ((packed, aligned (4))); 375 376 struct ipr_config_table_entry64 { 377 u8 res_type; 378 u8 proto; 379 u8 vset_num; 380 u8 array_id; 381 __be16 flags; 382 __be16 res_flags; 383 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12) 384 __be32 res_handle; 385 u8 dev_id_type; 386 u8 reserved[3]; 387 __be64 dev_id; 388 __be64 lun; 389 __be64 lun_wwn[2]; 390 #define IPR_MAX_RES_PATH_LENGTH 24 391 __be64 res_path; 392 struct ipr_std_inq_data std_inq_data; 393 u8 reserved2[4]; 394 __be64 reserved3[2]; // description text 395 u8 reserved4[8]; 396 }__attribute__ ((packed, aligned (8))); 397 398 struct ipr_config_table_hdr { 399 u8 num_entries; 400 u8 flags; 401 #define IPR_UCODE_DOWNLOAD_REQ 0x10 402 __be16 reserved; 403 }__attribute__((packed, aligned (4))); 404 405 struct ipr_config_table_hdr64 { 406 __be16 num_entries; 407 __be16 reserved; 408 u8 flags; 409 u8 reserved2[11]; 410 }__attribute__((packed, aligned (4))); 411 412 struct ipr_config_table { 413 struct ipr_config_table_hdr hdr; 414 struct ipr_config_table_entry dev[0]; 415 }__attribute__((packed, aligned (4))); 416 417 struct ipr_config_table64 { 418 struct ipr_config_table_hdr64 hdr64; 419 struct ipr_config_table_entry64 dev[0]; 420 }__attribute__((packed, aligned (8))); 421 422 struct ipr_config_table_entry_wrapper { 423 union { 424 struct ipr_config_table_entry *cfgte; 425 struct ipr_config_table_entry64 *cfgte64; 426 } u; 427 }; 428 429 struct ipr_hostrcb_cfg_ch_not { 430 union { 431 struct ipr_config_table_entry cfgte; 432 struct ipr_config_table_entry64 cfgte64; 433 } u; 434 u8 reserved[936]; 435 }__attribute__((packed, aligned (4))); 436 437 struct ipr_supported_device { 438 __be16 data_length; 439 u8 reserved; 440 u8 num_records; 441 struct ipr_std_inq_vpids vpids; 442 u8 reserved2[16]; 443 }__attribute__((packed, aligned (4))); 444 445 /* Command packet structure */ 446 struct ipr_cmd_pkt { 447 __be16 reserved; /* Reserved by IOA */ 448 u8 request_type; 449 #define IPR_RQTYPE_SCSICDB 0x00 450 #define IPR_RQTYPE_IOACMD 0x01 451 #define IPR_RQTYPE_HCAM 0x02 452 #define IPR_RQTYPE_ATA_PASSTHRU 0x04 453 454 u8 reserved2; 455 456 u8 flags_hi; 457 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80 458 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20 459 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10 460 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08 461 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04 462 463 u8 flags_lo; 464 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20 465 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10 466 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00 467 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02 468 #define IPR_FLAGS_LO_ORDERED_TASK 0x04 469 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06 470 #define IPR_FLAGS_LO_ACA_TASK 0x08 471 472 u8 cdb[16]; 473 __be16 timeout; 474 }__attribute__ ((packed, aligned(4))); 475 476 struct ipr_ioarcb_ata_regs { /* 22 bytes */ 477 u8 flags; 478 #define IPR_ATA_FLAG_PACKET_CMD 0x80 479 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40 480 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20 481 u8 reserved[3]; 482 483 __be16 data; 484 u8 feature; 485 u8 nsect; 486 u8 lbal; 487 u8 lbam; 488 u8 lbah; 489 u8 device; 490 u8 command; 491 u8 reserved2[3]; 492 u8 hob_feature; 493 u8 hob_nsect; 494 u8 hob_lbal; 495 u8 hob_lbam; 496 u8 hob_lbah; 497 u8 ctl; 498 }__attribute__ ((packed, aligned(4))); 499 500 struct ipr_ioadl_desc { 501 __be32 flags_and_data_len; 502 #define IPR_IOADL_FLAGS_MASK 0xff000000 503 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK) 504 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff 505 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK) 506 #define IPR_IOADL_FLAGS_READ 0x48000000 507 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000 508 #define IPR_IOADL_FLAGS_WRITE 0x68000000 509 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000 510 #define IPR_IOADL_FLAGS_LAST 0x01000000 511 512 __be32 address; 513 }__attribute__((packed, aligned (8))); 514 515 struct ipr_ioadl64_desc { 516 __be32 flags; 517 __be32 data_len; 518 __be64 address; 519 }__attribute__((packed, aligned (16))); 520 521 struct ipr_ata64_ioadl { 522 struct ipr_ioarcb_ata_regs regs; 523 u16 reserved[5]; 524 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; 525 }__attribute__((packed, aligned (16))); 526 527 struct ipr_ioarcb_add_data { 528 union { 529 struct ipr_ioarcb_ata_regs regs; 530 struct ipr_ioadl_desc ioadl[5]; 531 __be32 add_cmd_parms[10]; 532 } u; 533 }__attribute__ ((packed, aligned (4))); 534 535 struct ipr_ioarcb_sis64_add_addr_ecb { 536 __be64 ioasa_host_pci_addr; 537 __be64 data_ioadl_addr; 538 __be64 reserved; 539 __be32 ext_control_buf[4]; 540 }__attribute__((packed, aligned (8))); 541 542 /* IOA Request Control Block 128 bytes */ 543 struct ipr_ioarcb { 544 union { 545 __be32 ioarcb_host_pci_addr; 546 __be64 ioarcb_host_pci_addr64; 547 } a; 548 __be32 res_handle; 549 __be32 host_response_handle; 550 __be32 reserved1; 551 __be32 reserved2; 552 __be32 reserved3; 553 554 __be32 data_transfer_length; 555 __be32 read_data_transfer_length; 556 __be32 write_ioadl_addr; 557 __be32 ioadl_len; 558 __be32 read_ioadl_addr; 559 __be32 read_ioadl_len; 560 561 __be32 ioasa_host_pci_addr; 562 __be16 ioasa_len; 563 __be16 reserved4; 564 565 struct ipr_cmd_pkt cmd_pkt; 566 567 __be16 add_cmd_parms_offset; 568 __be16 add_cmd_parms_len; 569 570 union { 571 struct ipr_ioarcb_add_data add_data; 572 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data; 573 } u; 574 575 }__attribute__((packed, aligned (4))); 576 577 struct ipr_ioasa_vset { 578 __be32 failing_lba_hi; 579 __be32 failing_lba_lo; 580 __be32 reserved; 581 }__attribute__((packed, aligned (4))); 582 583 struct ipr_ioasa_af_dasd { 584 __be32 failing_lba; 585 __be32 reserved[2]; 586 }__attribute__((packed, aligned (4))); 587 588 struct ipr_ioasa_gpdd { 589 u8 end_state; 590 u8 bus_phase; 591 __be16 reserved; 592 __be32 ioa_data[2]; 593 }__attribute__((packed, aligned (4))); 594 595 struct ipr_ioasa_gata { 596 u8 error; 597 u8 nsect; /* Interrupt reason */ 598 u8 lbal; 599 u8 lbam; 600 u8 lbah; 601 u8 device; 602 u8 status; 603 u8 alt_status; /* ATA CTL */ 604 u8 hob_nsect; 605 u8 hob_lbal; 606 u8 hob_lbam; 607 u8 hob_lbah; 608 }__attribute__((packed, aligned (4))); 609 610 struct ipr_auto_sense { 611 __be16 auto_sense_len; 612 __be16 ioa_data_len; 613 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)]; 614 }; 615 616 struct ipr_ioasa { 617 __be32 ioasc; 618 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) 619 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) 620 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) 621 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) 622 623 __be16 ret_stat_len; /* Length of the returned IOASA */ 624 625 __be16 avail_stat_len; /* Total Length of status available. */ 626 627 __be32 residual_data_len; /* number of bytes in the host data */ 628 /* buffers that were not used by the IOARCB command. */ 629 630 __be32 ilid; 631 #define IPR_NO_ILID 0 632 #define IPR_DRIVER_ILID 0xffffffff 633 634 __be32 fd_ioasc; 635 636 __be32 fd_phys_locator; 637 638 __be32 fd_res_handle; 639 640 __be32 ioasc_specific; /* status code specific field */ 641 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000 642 #define IPR_AUTOSENSE_VALID 0x40000000 643 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000 644 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff 645 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8) 646 #define IPR_FIELD_POINTER_MASK 0x0000ffff 647 648 union { 649 struct ipr_ioasa_vset vset; 650 struct ipr_ioasa_af_dasd dasd; 651 struct ipr_ioasa_gpdd gpdd; 652 struct ipr_ioasa_gata gata; 653 } u; 654 655 struct ipr_auto_sense auto_sense; 656 }__attribute__((packed, aligned (4))); 657 658 struct ipr_mode_parm_hdr { 659 u8 length; 660 u8 medium_type; 661 u8 device_spec_parms; 662 u8 block_desc_len; 663 }__attribute__((packed)); 664 665 struct ipr_mode_pages { 666 struct ipr_mode_parm_hdr hdr; 667 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)]; 668 }__attribute__((packed)); 669 670 struct ipr_mode_page_hdr { 671 u8 ps_page_code; 672 #define IPR_MODE_PAGE_PS 0x80 673 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F) 674 u8 page_length; 675 }__attribute__ ((packed)); 676 677 struct ipr_dev_bus_entry { 678 struct ipr_res_addr res_addr; 679 u8 flags; 680 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80 681 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40 682 #define IPR_SCSI_ATTR_QAS_MASK 0xC0 683 #define IPR_SCSI_ATTR_ENABLE_TM 0x20 684 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10 685 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08 686 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04 687 688 u8 scsi_id; 689 u8 bus_width; 690 u8 extended_reset_delay; 691 #define IPR_EXTENDED_RESET_DELAY 7 692 693 __be32 max_xfer_rate; 694 695 u8 spinup_delay; 696 u8 reserved3; 697 __be16 reserved4; 698 }__attribute__((packed, aligned (4))); 699 700 struct ipr_mode_page28 { 701 struct ipr_mode_page_hdr hdr; 702 u8 num_entries; 703 u8 entry_length; 704 struct ipr_dev_bus_entry bus[0]; 705 }__attribute__((packed)); 706 707 struct ipr_mode_page24 { 708 struct ipr_mode_page_hdr hdr; 709 u8 flags; 710 #define IPR_ENABLE_DUAL_IOA_AF 0x80 711 }__attribute__((packed)); 712 713 struct ipr_ioa_vpd { 714 struct ipr_std_inq_data std_inq_data; 715 u8 ascii_part_num[12]; 716 u8 reserved[40]; 717 u8 ascii_plant_code[4]; 718 }__attribute__((packed)); 719 720 struct ipr_inquiry_page3 { 721 u8 peri_qual_dev_type; 722 u8 page_code; 723 u8 reserved1; 724 u8 page_length; 725 u8 ascii_len; 726 u8 reserved2[3]; 727 u8 load_id[4]; 728 u8 major_release; 729 u8 card_type; 730 u8 minor_release[2]; 731 u8 ptf_number[4]; 732 u8 patch_number[4]; 733 }__attribute__((packed)); 734 735 struct ipr_inquiry_cap { 736 u8 peri_qual_dev_type; 737 u8 page_code; 738 u8 reserved1; 739 u8 page_length; 740 u8 ascii_len; 741 u8 reserved2; 742 u8 sis_version[2]; 743 u8 cap; 744 #define IPR_CAP_DUAL_IOA_RAID 0x80 745 u8 reserved3[15]; 746 }__attribute__((packed)); 747 748 #define IPR_INQUIRY_PAGE0_ENTRIES 20 749 struct ipr_inquiry_page0 { 750 u8 peri_qual_dev_type; 751 u8 page_code; 752 u8 reserved1; 753 u8 len; 754 u8 page[IPR_INQUIRY_PAGE0_ENTRIES]; 755 }__attribute__((packed)); 756 757 struct ipr_hostrcb_device_data_entry { 758 struct ipr_vpd vpd; 759 struct ipr_res_addr dev_res_addr; 760 struct ipr_vpd new_vpd; 761 struct ipr_vpd ioa_last_with_dev_vpd; 762 struct ipr_vpd cfc_last_with_dev_vpd; 763 __be32 ioa_data[5]; 764 }__attribute__((packed, aligned (4))); 765 766 struct ipr_hostrcb_device_data_entry_enhanced { 767 struct ipr_ext_vpd vpd; 768 u8 ccin[4]; 769 struct ipr_res_addr dev_res_addr; 770 struct ipr_ext_vpd new_vpd; 771 u8 new_ccin[4]; 772 struct ipr_ext_vpd ioa_last_with_dev_vpd; 773 struct ipr_ext_vpd cfc_last_with_dev_vpd; 774 }__attribute__((packed, aligned (4))); 775 776 struct ipr_hostrcb64_device_data_entry_enhanced { 777 struct ipr_ext_vpd vpd; 778 u8 ccin[4]; 779 u8 res_path[8]; 780 struct ipr_ext_vpd new_vpd; 781 u8 new_ccin[4]; 782 struct ipr_ext_vpd ioa_last_with_dev_vpd; 783 struct ipr_ext_vpd cfc_last_with_dev_vpd; 784 }__attribute__((packed, aligned (4))); 785 786 struct ipr_hostrcb_array_data_entry { 787 struct ipr_vpd vpd; 788 struct ipr_res_addr expected_dev_res_addr; 789 struct ipr_res_addr dev_res_addr; 790 }__attribute__((packed, aligned (4))); 791 792 struct ipr_hostrcb64_array_data_entry { 793 struct ipr_ext_vpd vpd; 794 u8 ccin[4]; 795 u8 expected_res_path[8]; 796 u8 res_path[8]; 797 }__attribute__((packed, aligned (4))); 798 799 struct ipr_hostrcb_array_data_entry_enhanced { 800 struct ipr_ext_vpd vpd; 801 u8 ccin[4]; 802 struct ipr_res_addr expected_dev_res_addr; 803 struct ipr_res_addr dev_res_addr; 804 }__attribute__((packed, aligned (4))); 805 806 struct ipr_hostrcb_type_ff_error { 807 __be32 ioa_data[502]; 808 }__attribute__((packed, aligned (4))); 809 810 struct ipr_hostrcb_type_01_error { 811 __be32 seek_counter; 812 __be32 read_counter; 813 u8 sense_data[32]; 814 __be32 ioa_data[236]; 815 }__attribute__((packed, aligned (4))); 816 817 struct ipr_hostrcb_type_02_error { 818 struct ipr_vpd ioa_vpd; 819 struct ipr_vpd cfc_vpd; 820 struct ipr_vpd ioa_last_attached_to_cfc_vpd; 821 struct ipr_vpd cfc_last_attached_to_ioa_vpd; 822 __be32 ioa_data[3]; 823 }__attribute__((packed, aligned (4))); 824 825 struct ipr_hostrcb_type_12_error { 826 struct ipr_ext_vpd ioa_vpd; 827 struct ipr_ext_vpd cfc_vpd; 828 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd; 829 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd; 830 __be32 ioa_data[3]; 831 }__attribute__((packed, aligned (4))); 832 833 struct ipr_hostrcb_type_03_error { 834 struct ipr_vpd ioa_vpd; 835 struct ipr_vpd cfc_vpd; 836 __be32 errors_detected; 837 __be32 errors_logged; 838 u8 ioa_data[12]; 839 struct ipr_hostrcb_device_data_entry dev[3]; 840 }__attribute__((packed, aligned (4))); 841 842 struct ipr_hostrcb_type_13_error { 843 struct ipr_ext_vpd ioa_vpd; 844 struct ipr_ext_vpd cfc_vpd; 845 __be32 errors_detected; 846 __be32 errors_logged; 847 struct ipr_hostrcb_device_data_entry_enhanced dev[3]; 848 }__attribute__((packed, aligned (4))); 849 850 struct ipr_hostrcb_type_23_error { 851 struct ipr_ext_vpd ioa_vpd; 852 struct ipr_ext_vpd cfc_vpd; 853 __be32 errors_detected; 854 __be32 errors_logged; 855 struct ipr_hostrcb64_device_data_entry_enhanced dev[3]; 856 }__attribute__((packed, aligned (4))); 857 858 struct ipr_hostrcb_type_04_error { 859 struct ipr_vpd ioa_vpd; 860 struct ipr_vpd cfc_vpd; 861 u8 ioa_data[12]; 862 struct ipr_hostrcb_array_data_entry array_member[10]; 863 __be32 exposed_mode_adn; 864 __be32 array_id; 865 struct ipr_vpd incomp_dev_vpd; 866 __be32 ioa_data2; 867 struct ipr_hostrcb_array_data_entry array_member2[8]; 868 struct ipr_res_addr last_func_vset_res_addr; 869 u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; 870 u8 protection_level[8]; 871 }__attribute__((packed, aligned (4))); 872 873 struct ipr_hostrcb_type_14_error { 874 struct ipr_ext_vpd ioa_vpd; 875 struct ipr_ext_vpd cfc_vpd; 876 __be32 exposed_mode_adn; 877 __be32 array_id; 878 struct ipr_res_addr last_func_vset_res_addr; 879 u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; 880 u8 protection_level[8]; 881 __be32 num_entries; 882 struct ipr_hostrcb_array_data_entry_enhanced array_member[18]; 883 }__attribute__((packed, aligned (4))); 884 885 struct ipr_hostrcb_type_24_error { 886 struct ipr_ext_vpd ioa_vpd; 887 struct ipr_ext_vpd cfc_vpd; 888 u8 reserved[2]; 889 u8 exposed_mode_adn; 890 #define IPR_INVALID_ARRAY_DEV_NUM 0xff 891 u8 array_id; 892 u8 last_res_path[8]; 893 u8 protection_level[8]; 894 struct ipr_ext_vpd array_vpd; 895 u8 description[16]; 896 u8 reserved2[3]; 897 u8 num_entries; 898 struct ipr_hostrcb64_array_data_entry array_member[32]; 899 }__attribute__((packed, aligned (4))); 900 901 struct ipr_hostrcb_type_07_error { 902 u8 failure_reason[64]; 903 struct ipr_vpd vpd; 904 u32 data[222]; 905 }__attribute__((packed, aligned (4))); 906 907 struct ipr_hostrcb_type_17_error { 908 u8 failure_reason[64]; 909 struct ipr_ext_vpd vpd; 910 u32 data[476]; 911 }__attribute__((packed, aligned (4))); 912 913 struct ipr_hostrcb_config_element { 914 u8 type_status; 915 #define IPR_PATH_CFG_TYPE_MASK 0xF0 916 #define IPR_PATH_CFG_NOT_EXIST 0x00 917 #define IPR_PATH_CFG_IOA_PORT 0x10 918 #define IPR_PATH_CFG_EXP_PORT 0x20 919 #define IPR_PATH_CFG_DEVICE_PORT 0x30 920 #define IPR_PATH_CFG_DEVICE_LUN 0x40 921 922 #define IPR_PATH_CFG_STATUS_MASK 0x0F 923 #define IPR_PATH_CFG_NO_PROB 0x00 924 #define IPR_PATH_CFG_DEGRADED 0x01 925 #define IPR_PATH_CFG_FAILED 0x02 926 #define IPR_PATH_CFG_SUSPECT 0x03 927 #define IPR_PATH_NOT_DETECTED 0x04 928 #define IPR_PATH_INCORRECT_CONN 0x05 929 930 u8 cascaded_expander; 931 u8 phy; 932 u8 link_rate; 933 #define IPR_PHY_LINK_RATE_MASK 0x0F 934 935 __be32 wwid[2]; 936 }__attribute__((packed, aligned (4))); 937 938 struct ipr_hostrcb64_config_element { 939 __be16 length; 940 u8 descriptor_id; 941 #define IPR_DESCRIPTOR_MASK 0xC0 942 #define IPR_DESCRIPTOR_SIS64 0x00 943 944 u8 reserved; 945 u8 type_status; 946 947 u8 reserved2[2]; 948 u8 link_rate; 949 950 u8 res_path[8]; 951 __be32 wwid[2]; 952 }__attribute__((packed, aligned (8))); 953 954 struct ipr_hostrcb_fabric_desc { 955 __be16 length; 956 u8 ioa_port; 957 u8 cascaded_expander; 958 u8 phy; 959 u8 path_state; 960 #define IPR_PATH_ACTIVE_MASK 0xC0 961 #define IPR_PATH_NO_INFO 0x00 962 #define IPR_PATH_ACTIVE 0x40 963 #define IPR_PATH_NOT_ACTIVE 0x80 964 965 #define IPR_PATH_STATE_MASK 0x0F 966 #define IPR_PATH_STATE_NO_INFO 0x00 967 #define IPR_PATH_HEALTHY 0x01 968 #define IPR_PATH_DEGRADED 0x02 969 #define IPR_PATH_FAILED 0x03 970 971 __be16 num_entries; 972 struct ipr_hostrcb_config_element elem[1]; 973 }__attribute__((packed, aligned (4))); 974 975 struct ipr_hostrcb64_fabric_desc { 976 __be16 length; 977 u8 descriptor_id; 978 979 u8 reserved; 980 u8 path_state; 981 982 u8 reserved2[2]; 983 u8 res_path[8]; 984 u8 reserved3[6]; 985 __be16 num_entries; 986 struct ipr_hostrcb64_config_element elem[1]; 987 }__attribute__((packed, aligned (8))); 988 989 #define for_each_fabric_cfg(fabric, cfg) \ 990 for (cfg = (fabric)->elem; \ 991 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \ 992 cfg++) 993 994 struct ipr_hostrcb_type_20_error { 995 u8 failure_reason[64]; 996 u8 reserved[3]; 997 u8 num_entries; 998 struct ipr_hostrcb_fabric_desc desc[1]; 999 }__attribute__((packed, aligned (4))); 1000 1001 struct ipr_hostrcb_type_30_error { 1002 u8 failure_reason[64]; 1003 u8 reserved[3]; 1004 u8 num_entries; 1005 struct ipr_hostrcb64_fabric_desc desc[1]; 1006 }__attribute__((packed, aligned (4))); 1007 1008 struct ipr_hostrcb_error { 1009 __be32 fd_ioasc; 1010 struct ipr_res_addr fd_res_addr; 1011 __be32 fd_res_handle; 1012 __be32 prc; 1013 union { 1014 struct ipr_hostrcb_type_ff_error type_ff_error; 1015 struct ipr_hostrcb_type_01_error type_01_error; 1016 struct ipr_hostrcb_type_02_error type_02_error; 1017 struct ipr_hostrcb_type_03_error type_03_error; 1018 struct ipr_hostrcb_type_04_error type_04_error; 1019 struct ipr_hostrcb_type_07_error type_07_error; 1020 struct ipr_hostrcb_type_12_error type_12_error; 1021 struct ipr_hostrcb_type_13_error type_13_error; 1022 struct ipr_hostrcb_type_14_error type_14_error; 1023 struct ipr_hostrcb_type_17_error type_17_error; 1024 struct ipr_hostrcb_type_20_error type_20_error; 1025 } u; 1026 }__attribute__((packed, aligned (4))); 1027 1028 struct ipr_hostrcb64_error { 1029 __be32 fd_ioasc; 1030 __be32 ioa_fw_level; 1031 __be32 fd_res_handle; 1032 __be32 prc; 1033 __be64 fd_dev_id; 1034 __be64 fd_lun; 1035 u8 fd_res_path[8]; 1036 __be64 time_stamp; 1037 u8 reserved[2]; 1038 union { 1039 struct ipr_hostrcb_type_ff_error type_ff_error; 1040 struct ipr_hostrcb_type_12_error type_12_error; 1041 struct ipr_hostrcb_type_17_error type_17_error; 1042 struct ipr_hostrcb_type_23_error type_23_error; 1043 struct ipr_hostrcb_type_24_error type_24_error; 1044 struct ipr_hostrcb_type_30_error type_30_error; 1045 } u; 1046 }__attribute__((packed, aligned (8))); 1047 1048 struct ipr_hostrcb_raw { 1049 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)]; 1050 }__attribute__((packed, aligned (4))); 1051 1052 struct ipr_hcam { 1053 u8 op_code; 1054 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1 1055 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2 1056 1057 u8 notify_type; 1058 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00 1059 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01 1060 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02 1061 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10 1062 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11 1063 1064 u8 notifications_lost; 1065 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0 1066 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80 1067 1068 u8 flags; 1069 #define IPR_HOSTRCB_INTERNAL_OPER 0x80 1070 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40 1071 1072 u8 overlay_id; 1073 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01 1074 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02 1075 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03 1076 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04 1077 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06 1078 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07 1079 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12 1080 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13 1081 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14 1082 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16 1083 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17 1084 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20 1085 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23 1086 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24 1087 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26 1088 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30 1089 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF 1090 1091 u8 reserved1[3]; 1092 __be32 ilid; 1093 __be32 time_since_last_ioa_reset; 1094 __be32 reserved2; 1095 __be32 length; 1096 1097 union { 1098 struct ipr_hostrcb_error error; 1099 struct ipr_hostrcb64_error error64; 1100 struct ipr_hostrcb_cfg_ch_not ccn; 1101 struct ipr_hostrcb_raw raw; 1102 } u; 1103 }__attribute__((packed, aligned (4))); 1104 1105 struct ipr_hostrcb { 1106 struct ipr_hcam hcam; 1107 dma_addr_t hostrcb_dma; 1108 struct list_head queue; 1109 struct ipr_ioa_cfg *ioa_cfg; 1110 char rp_buffer[IPR_MAX_RES_PATH_LENGTH]; 1111 }; 1112 1113 /* IPR smart dump table structures */ 1114 struct ipr_sdt_entry { 1115 __be32 start_token; 1116 __be32 end_token; 1117 u8 reserved[4]; 1118 1119 u8 flags; 1120 #define IPR_SDT_ENDIAN 0x80 1121 #define IPR_SDT_VALID_ENTRY 0x20 1122 1123 u8 resv; 1124 __be16 priority; 1125 }__attribute__((packed, aligned (4))); 1126 1127 struct ipr_sdt_header { 1128 __be32 state; 1129 __be32 num_entries; 1130 __be32 num_entries_used; 1131 __be32 dump_size; 1132 }__attribute__((packed, aligned (4))); 1133 1134 struct ipr_sdt { 1135 struct ipr_sdt_header hdr; 1136 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES]; 1137 }__attribute__((packed, aligned (4))); 1138 1139 struct ipr_uc_sdt { 1140 struct ipr_sdt_header hdr; 1141 struct ipr_sdt_entry entry[1]; 1142 }__attribute__((packed, aligned (4))); 1143 1144 /* 1145 * Driver types 1146 */ 1147 struct ipr_bus_attributes { 1148 u8 bus; 1149 u8 qas_enabled; 1150 u8 bus_width; 1151 u8 reserved; 1152 u32 max_xfer_rate; 1153 }; 1154 1155 struct ipr_sata_port { 1156 struct ipr_ioa_cfg *ioa_cfg; 1157 struct ata_port *ap; 1158 struct ipr_resource_entry *res; 1159 struct ipr_ioasa_gata ioasa; 1160 }; 1161 1162 struct ipr_resource_entry { 1163 u8 needs_sync_complete:1; 1164 u8 in_erp:1; 1165 u8 add_to_ml:1; 1166 u8 del_from_ml:1; 1167 u8 resetting_device:1; 1168 1169 u32 bus; /* AKA channel */ 1170 u32 target; /* AKA id */ 1171 u32 lun; 1172 #define IPR_ARRAY_VIRTUAL_BUS 0x1 1173 #define IPR_VSET_VIRTUAL_BUS 0x2 1174 #define IPR_IOAFP_VIRTUAL_BUS 0x3 1175 1176 #define IPR_GET_RES_PHYS_LOC(res) \ 1177 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun) 1178 1179 u8 ata_class; 1180 1181 u8 flags; 1182 __be16 res_flags; 1183 1184 __be32 type; 1185 1186 u8 qmodel; 1187 struct ipr_std_inq_data std_inq_data; 1188 1189 __be32 res_handle; 1190 __be64 dev_id; 1191 struct scsi_lun dev_lun; 1192 u8 res_path[8]; 1193 1194 struct ipr_ioa_cfg *ioa_cfg; 1195 struct scsi_device *sdev; 1196 struct ipr_sata_port *sata_port; 1197 struct list_head queue; 1198 }; /* struct ipr_resource_entry */ 1199 1200 struct ipr_resource_hdr { 1201 u16 num_entries; 1202 u16 reserved; 1203 }; 1204 1205 struct ipr_misc_cbs { 1206 struct ipr_ioa_vpd ioa_vpd; 1207 struct ipr_inquiry_page0 page0_data; 1208 struct ipr_inquiry_page3 page3_data; 1209 struct ipr_inquiry_cap cap; 1210 struct ipr_mode_pages mode_pages; 1211 struct ipr_supported_device supp_dev; 1212 }; 1213 1214 struct ipr_interrupt_offsets { 1215 unsigned long set_interrupt_mask_reg; 1216 unsigned long clr_interrupt_mask_reg; 1217 unsigned long clr_interrupt_mask_reg32; 1218 unsigned long sense_interrupt_mask_reg; 1219 unsigned long sense_interrupt_mask_reg32; 1220 unsigned long clr_interrupt_reg; 1221 unsigned long clr_interrupt_reg32; 1222 1223 unsigned long sense_interrupt_reg; 1224 unsigned long sense_interrupt_reg32; 1225 unsigned long ioarrin_reg; 1226 unsigned long sense_uproc_interrupt_reg; 1227 unsigned long sense_uproc_interrupt_reg32; 1228 unsigned long set_uproc_interrupt_reg; 1229 unsigned long set_uproc_interrupt_reg32; 1230 unsigned long clr_uproc_interrupt_reg; 1231 unsigned long clr_uproc_interrupt_reg32; 1232 1233 unsigned long init_feedback_reg; 1234 1235 unsigned long dump_addr_reg; 1236 unsigned long dump_data_reg; 1237 }; 1238 1239 struct ipr_interrupts { 1240 void __iomem *set_interrupt_mask_reg; 1241 void __iomem *clr_interrupt_mask_reg; 1242 void __iomem *clr_interrupt_mask_reg32; 1243 void __iomem *sense_interrupt_mask_reg; 1244 void __iomem *sense_interrupt_mask_reg32; 1245 void __iomem *clr_interrupt_reg; 1246 void __iomem *clr_interrupt_reg32; 1247 1248 void __iomem *sense_interrupt_reg; 1249 void __iomem *sense_interrupt_reg32; 1250 void __iomem *ioarrin_reg; 1251 void __iomem *sense_uproc_interrupt_reg; 1252 void __iomem *sense_uproc_interrupt_reg32; 1253 void __iomem *set_uproc_interrupt_reg; 1254 void __iomem *set_uproc_interrupt_reg32; 1255 void __iomem *clr_uproc_interrupt_reg; 1256 void __iomem *clr_uproc_interrupt_reg32; 1257 1258 void __iomem *init_feedback_reg; 1259 1260 void __iomem *dump_addr_reg; 1261 void __iomem *dump_data_reg; 1262 }; 1263 1264 struct ipr_chip_cfg_t { 1265 u32 mailbox; 1266 u8 cache_line_size; 1267 struct ipr_interrupt_offsets regs; 1268 }; 1269 1270 struct ipr_chip_t { 1271 u16 vendor; 1272 u16 device; 1273 u16 intr_type; 1274 #define IPR_USE_LSI 0x00 1275 #define IPR_USE_MSI 0x01 1276 u16 sis_type; 1277 #define IPR_SIS32 0x00 1278 #define IPR_SIS64 0x01 1279 const struct ipr_chip_cfg_t *cfg; 1280 }; 1281 1282 enum ipr_shutdown_type { 1283 IPR_SHUTDOWN_NORMAL = 0x00, 1284 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40, 1285 IPR_SHUTDOWN_ABBREV = 0x80, 1286 IPR_SHUTDOWN_NONE = 0x100 1287 }; 1288 1289 struct ipr_trace_entry { 1290 u32 time; 1291 1292 u8 op_code; 1293 u8 ata_op_code; 1294 u8 type; 1295 #define IPR_TRACE_START 0x00 1296 #define IPR_TRACE_FINISH 0xff 1297 u8 cmd_index; 1298 1299 __be32 res_handle; 1300 union { 1301 u32 ioasc; 1302 u32 add_data; 1303 u32 res_addr; 1304 } u; 1305 }; 1306 1307 struct ipr_sglist { 1308 u32 order; 1309 u32 num_sg; 1310 u32 num_dma_sg; 1311 u32 buffer_len; 1312 struct scatterlist scatterlist[1]; 1313 }; 1314 1315 enum ipr_sdt_state { 1316 INACTIVE, 1317 WAIT_FOR_DUMP, 1318 GET_DUMP, 1319 ABORT_DUMP, 1320 DUMP_OBTAINED 1321 }; 1322 1323 /* Per-controller data */ 1324 struct ipr_ioa_cfg { 1325 char eye_catcher[8]; 1326 #define IPR_EYECATCHER "iprcfg" 1327 1328 struct list_head queue; 1329 1330 u8 allow_interrupts:1; 1331 u8 in_reset_reload:1; 1332 u8 in_ioa_bringdown:1; 1333 u8 ioa_unit_checked:1; 1334 u8 ioa_is_dead:1; 1335 u8 dump_taken:1; 1336 u8 allow_cmds:1; 1337 u8 allow_ml_add_del:1; 1338 u8 needs_hard_reset:1; 1339 u8 dual_raid:1; 1340 u8 needs_warm_reset:1; 1341 u8 msi_received:1; 1342 u8 sis64:1; 1343 1344 u8 revid; 1345 1346 /* 1347 * Bitmaps for SIS64 generated target values 1348 */ 1349 unsigned long *target_ids; 1350 unsigned long *array_ids; 1351 unsigned long *vset_ids; 1352 1353 u16 type; /* CCIN of the card */ 1354 1355 u8 log_level; 1356 #define IPR_MAX_LOG_LEVEL 4 1357 #define IPR_DEFAULT_LOG_LEVEL 2 1358 1359 #define IPR_NUM_TRACE_INDEX_BITS 8 1360 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS) 1361 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES) 1362 char trace_start[8]; 1363 #define IPR_TRACE_START_LABEL "trace" 1364 struct ipr_trace_entry *trace; 1365 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS; 1366 1367 /* 1368 * Queue for free command blocks 1369 */ 1370 char ipr_free_label[8]; 1371 #define IPR_FREEQ_LABEL "free-q" 1372 struct list_head free_q; 1373 1374 /* 1375 * Queue for command blocks outstanding to the adapter 1376 */ 1377 char ipr_pending_label[8]; 1378 #define IPR_PENDQ_LABEL "pend-q" 1379 struct list_head pending_q; 1380 1381 char cfg_table_start[8]; 1382 #define IPR_CFG_TBL_START "cfg" 1383 union { 1384 struct ipr_config_table *cfg_table; 1385 struct ipr_config_table64 *cfg_table64; 1386 } u; 1387 dma_addr_t cfg_table_dma; 1388 u32 cfg_table_size; 1389 u32 max_devs_supported; 1390 1391 char resource_table_label[8]; 1392 #define IPR_RES_TABLE_LABEL "res_tbl" 1393 struct ipr_resource_entry *res_entries; 1394 struct list_head free_res_q; 1395 struct list_head used_res_q; 1396 1397 char ipr_hcam_label[8]; 1398 #define IPR_HCAM_LABEL "hcams" 1399 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS]; 1400 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS]; 1401 struct list_head hostrcb_free_q; 1402 struct list_head hostrcb_pending_q; 1403 1404 __be32 *host_rrq; 1405 dma_addr_t host_rrq_dma; 1406 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc 1407 #define IPR_HRRQ_RESP_BIT_SET 0x00000002 1408 #define IPR_HRRQ_TOGGLE_BIT 0x00000001 1409 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2 1410 volatile __be32 *hrrq_start; 1411 volatile __be32 *hrrq_end; 1412 volatile __be32 *hrrq_curr; 1413 volatile u32 toggle_bit; 1414 1415 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES]; 1416 1417 unsigned int transop_timeout; 1418 const struct ipr_chip_cfg_t *chip_cfg; 1419 const struct ipr_chip_t *ipr_chip; 1420 1421 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */ 1422 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */ 1423 void __iomem *ioa_mailbox; 1424 struct ipr_interrupts regs; 1425 1426 u16 saved_pcix_cmd_reg; 1427 u16 reset_retries; 1428 1429 u32 errors_logged; 1430 u32 doorbell; 1431 1432 struct Scsi_Host *host; 1433 struct pci_dev *pdev; 1434 struct ipr_sglist *ucode_sglist; 1435 u8 saved_mode_page_len; 1436 1437 struct work_struct work_q; 1438 1439 wait_queue_head_t reset_wait_q; 1440 wait_queue_head_t msi_wait_q; 1441 1442 struct ipr_dump *dump; 1443 enum ipr_sdt_state sdt_state; 1444 1445 struct ipr_misc_cbs *vpd_cbs; 1446 dma_addr_t vpd_cbs_dma; 1447 1448 struct pci_pool *ipr_cmd_pool; 1449 1450 struct ipr_cmnd *reset_cmd; 1451 int (*reset) (struct ipr_cmnd *); 1452 1453 struct ata_host ata_host; 1454 char ipr_cmd_label[8]; 1455 #define IPR_CMD_LABEL "ipr_cmd" 1456 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS]; 1457 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS]; 1458 }; /* struct ipr_ioa_cfg */ 1459 1460 struct ipr_cmnd { 1461 struct ipr_ioarcb ioarcb; 1462 union { 1463 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES]; 1464 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; 1465 struct ipr_ata64_ioadl ata_ioadl; 1466 } i; 1467 struct ipr_ioasa ioasa; 1468 struct list_head queue; 1469 struct scsi_cmnd *scsi_cmd; 1470 struct ata_queued_cmd *qc; 1471 struct completion completion; 1472 struct timer_list timer; 1473 void (*done) (struct ipr_cmnd *); 1474 int (*job_step) (struct ipr_cmnd *); 1475 int (*job_step_failed) (struct ipr_cmnd *); 1476 u16 cmd_index; 1477 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; 1478 dma_addr_t sense_buffer_dma; 1479 unsigned short dma_use_sg; 1480 dma_addr_t dma_addr; 1481 struct ipr_cmnd *sibling; 1482 union { 1483 enum ipr_shutdown_type shutdown_type; 1484 struct ipr_hostrcb *hostrcb; 1485 unsigned long time_left; 1486 unsigned long scratch; 1487 struct ipr_resource_entry *res; 1488 struct scsi_device *sdev; 1489 } u; 1490 1491 struct ipr_ioa_cfg *ioa_cfg; 1492 }; 1493 1494 struct ipr_ses_table_entry { 1495 char product_id[17]; 1496 char compare_product_id_byte[17]; 1497 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */ 1498 }; 1499 1500 struct ipr_dump_header { 1501 u32 eye_catcher; 1502 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 1503 u32 len; 1504 u32 num_entries; 1505 u32 first_entry_offset; 1506 u32 status; 1507 #define IPR_DUMP_STATUS_SUCCESS 0 1508 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2 1509 #define IPR_DUMP_STATUS_FAILED 0xffffffff 1510 u32 os; 1511 #define IPR_DUMP_OS_LINUX 0x4C4E5558 1512 u32 driver_name; 1513 #define IPR_DUMP_DRIVER_NAME 0x49505232 1514 }__attribute__((packed, aligned (4))); 1515 1516 struct ipr_dump_entry_header { 1517 u32 eye_catcher; 1518 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 1519 u32 len; 1520 u32 num_elems; 1521 u32 offset; 1522 u32 data_type; 1523 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349 1524 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41 1525 u32 id; 1526 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131 1527 #define IPR_DUMP_LOCATION_ID 0x4C4F4341 1528 #define IPR_DUMP_TRACE_ID 0x54524143 1529 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652 1530 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045 1531 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342 1532 #define IPR_DUMP_PEND_OPS 0x414F5053 1533 u32 status; 1534 }__attribute__((packed, aligned (4))); 1535 1536 struct ipr_dump_location_entry { 1537 struct ipr_dump_entry_header hdr; 1538 u8 location[20]; 1539 }__attribute__((packed)); 1540 1541 struct ipr_dump_trace_entry { 1542 struct ipr_dump_entry_header hdr; 1543 u32 trace[IPR_TRACE_SIZE / sizeof(u32)]; 1544 }__attribute__((packed, aligned (4))); 1545 1546 struct ipr_dump_version_entry { 1547 struct ipr_dump_entry_header hdr; 1548 u8 version[sizeof(IPR_DRIVER_VERSION)]; 1549 }; 1550 1551 struct ipr_dump_ioa_type_entry { 1552 struct ipr_dump_entry_header hdr; 1553 u32 type; 1554 u32 fw_version; 1555 }; 1556 1557 struct ipr_driver_dump { 1558 struct ipr_dump_header hdr; 1559 struct ipr_dump_version_entry version_entry; 1560 struct ipr_dump_location_entry location_entry; 1561 struct ipr_dump_ioa_type_entry ioa_type_entry; 1562 struct ipr_dump_trace_entry trace_entry; 1563 }__attribute__((packed)); 1564 1565 struct ipr_ioa_dump { 1566 struct ipr_dump_entry_header hdr; 1567 struct ipr_sdt sdt; 1568 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES]; 1569 u32 reserved; 1570 u32 next_page_index; 1571 u32 page_offset; 1572 u32 format; 1573 }__attribute__((packed, aligned (4))); 1574 1575 struct ipr_dump { 1576 struct kref kref; 1577 struct ipr_ioa_cfg *ioa_cfg; 1578 struct ipr_driver_dump driver_dump; 1579 struct ipr_ioa_dump ioa_dump; 1580 }; 1581 1582 struct ipr_error_table_t { 1583 u32 ioasc; 1584 int log_ioasa; 1585 int log_hcam; 1586 char *error; 1587 }; 1588 1589 struct ipr_software_inq_lid_info { 1590 __be32 load_id; 1591 __be32 timestamp[3]; 1592 }__attribute__((packed, aligned (4))); 1593 1594 struct ipr_ucode_image_header { 1595 __be32 header_length; 1596 __be32 lid_table_offset; 1597 u8 major_release; 1598 u8 card_type; 1599 u8 minor_release[2]; 1600 u8 reserved[20]; 1601 char eyecatcher[16]; 1602 __be32 num_lids; 1603 struct ipr_software_inq_lid_info lid[1]; 1604 }__attribute__((packed, aligned (4))); 1605 1606 /* 1607 * Macros 1608 */ 1609 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; } 1610 1611 #ifdef CONFIG_SCSI_IPR_TRACE 1612 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr) 1613 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) 1614 #else 1615 #define ipr_create_trace_file(kobj, attr) 0 1616 #define ipr_remove_trace_file(kobj, attr) do { } while(0) 1617 #endif 1618 1619 #ifdef CONFIG_SCSI_IPR_DUMP 1620 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr) 1621 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) 1622 #else 1623 #define ipr_create_dump_file(kobj, attr) 0 1624 #define ipr_remove_dump_file(kobj, attr) do { } while(0) 1625 #endif 1626 1627 /* 1628 * Error logging macros 1629 */ 1630 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__) 1631 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) 1632 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) 1633 1634 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \ 1635 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ 1636 bus, target, lun, ##__VA_ARGS__) 1637 1638 #define ipr_res_err(ioa_cfg, res, fmt, ...) \ 1639 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__) 1640 1641 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \ 1642 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ 1643 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__) 1644 1645 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \ 1646 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__) 1647 1648 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \ 1649 { \ 1650 if ((res).bus >= IPR_MAX_NUM_BUSES) { \ 1651 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \ 1652 } else { \ 1653 ipr_err(fmt": %d:%d:%d:%d\n", \ 1654 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \ 1655 (res).bus, (res).target, (res).lun); \ 1656 } \ 1657 } 1658 1659 #define ipr_hcam_err(hostrcb, fmt, ...) \ 1660 { \ 1661 if (ipr_is_device(hostrcb)) { \ 1662 if ((hostrcb)->ioa_cfg->sis64) { \ 1663 printk(KERN_ERR IPR_NAME ": %s: " fmt, \ 1664 ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \ 1665 &hostrcb->rp_buffer[0]), \ 1666 __VA_ARGS__); \ 1667 } else { \ 1668 ipr_ra_err((hostrcb)->ioa_cfg, \ 1669 (hostrcb)->hcam.u.error.fd_res_addr, \ 1670 fmt, __VA_ARGS__); \ 1671 } \ 1672 } else { \ 1673 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \ 1674 } \ 1675 } 1676 1677 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\ 1678 __FILE__, __func__, __LINE__) 1679 1680 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__)) 1681 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__)) 1682 1683 #define ipr_err_separator \ 1684 ipr_err("----------------------------------------------------------\n") 1685 1686 1687 /* 1688 * Inlines 1689 */ 1690 1691 /** 1692 * ipr_is_ioa_resource - Determine if a resource is the IOA 1693 * @res: resource entry struct 1694 * 1695 * Return value: 1696 * 1 if IOA / 0 if not IOA 1697 **/ 1698 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) 1699 { 1700 return res->type == IPR_RES_TYPE_IOAFP; 1701 } 1702 1703 /** 1704 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD 1705 * @res: resource entry struct 1706 * 1707 * Return value: 1708 * 1 if AF DASD / 0 if not AF DASD 1709 **/ 1710 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) 1711 { 1712 return res->type == IPR_RES_TYPE_AF_DASD || 1713 res->type == IPR_RES_TYPE_REMOTE_AF_DASD; 1714 } 1715 1716 /** 1717 * ipr_is_vset_device - Determine if a resource is a VSET 1718 * @res: resource entry struct 1719 * 1720 * Return value: 1721 * 1 if VSET / 0 if not VSET 1722 **/ 1723 static inline int ipr_is_vset_device(struct ipr_resource_entry *res) 1724 { 1725 return res->type == IPR_RES_TYPE_VOLUME_SET; 1726 } 1727 1728 /** 1729 * ipr_is_gscsi - Determine if a resource is a generic scsi resource 1730 * @res: resource entry struct 1731 * 1732 * Return value: 1733 * 1 if GSCSI / 0 if not GSCSI 1734 **/ 1735 static inline int ipr_is_gscsi(struct ipr_resource_entry *res) 1736 { 1737 return res->type == IPR_RES_TYPE_GENERIC_SCSI; 1738 } 1739 1740 /** 1741 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk 1742 * @res: resource entry struct 1743 * 1744 * Return value: 1745 * 1 if SCSI disk / 0 if not SCSI disk 1746 **/ 1747 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res) 1748 { 1749 if (ipr_is_af_dasd_device(res) || 1750 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data))) 1751 return 1; 1752 else 1753 return 0; 1754 } 1755 1756 /** 1757 * ipr_is_gata - Determine if a resource is a generic ATA resource 1758 * @res: resource entry struct 1759 * 1760 * Return value: 1761 * 1 if GATA / 0 if not GATA 1762 **/ 1763 static inline int ipr_is_gata(struct ipr_resource_entry *res) 1764 { 1765 return res->type == IPR_RES_TYPE_GENERIC_ATA; 1766 } 1767 1768 /** 1769 * ipr_is_naca_model - Determine if a resource is using NACA queueing model 1770 * @res: resource entry struct 1771 * 1772 * Return value: 1773 * 1 if NACA queueing model / 0 if not NACA queueing model 1774 **/ 1775 static inline int ipr_is_naca_model(struct ipr_resource_entry *res) 1776 { 1777 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL) 1778 return 1; 1779 return 0; 1780 } 1781 1782 /** 1783 * ipr_is_device - Determine if the hostrcb structure is related to a device 1784 * @hostrcb: host resource control blocks struct 1785 * 1786 * Return value: 1787 * 1 if AF / 0 if not AF 1788 **/ 1789 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb) 1790 { 1791 struct ipr_res_addr *res_addr; 1792 u8 *res_path; 1793 1794 if (hostrcb->ioa_cfg->sis64) { 1795 res_path = &hostrcb->hcam.u.error64.fd_res_path[0]; 1796 if ((res_path[0] == 0x00 || res_path[0] == 0x80 || 1797 res_path[0] == 0x81) && res_path[2] != 0xFF) 1798 return 1; 1799 } else { 1800 res_addr = &hostrcb->hcam.u.error.fd_res_addr; 1801 1802 if ((res_addr->bus < IPR_MAX_NUM_BUSES) && 1803 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) 1804 return 1; 1805 } 1806 return 0; 1807 } 1808 1809 /** 1810 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2 1811 * @sdt_word: SDT address 1812 * 1813 * Return value: 1814 * 1 if format 2 / 0 if not 1815 **/ 1816 static inline int ipr_sdt_is_fmt2(u32 sdt_word) 1817 { 1818 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word); 1819 1820 switch (bar_sel) { 1821 case IPR_SDT_FMT2_BAR0_SEL: 1822 case IPR_SDT_FMT2_BAR1_SEL: 1823 case IPR_SDT_FMT2_BAR2_SEL: 1824 case IPR_SDT_FMT2_BAR3_SEL: 1825 case IPR_SDT_FMT2_BAR4_SEL: 1826 case IPR_SDT_FMT2_BAR5_SEL: 1827 case IPR_SDT_FMT2_EXP_ROM_SEL: 1828 return 1; 1829 }; 1830 1831 return 0; 1832 } 1833 1834 #endif 1835