1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 * NON INFRINGEMENT. See the GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 * 18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com 19 * 20 */ 21 #ifndef HPSA_CMD_H 22 #define HPSA_CMD_H 23 24 /* general boundary defintions */ 25 #define SENSEINFOBYTES 32 /* may vary between hbas */ 26 #define MAXSGENTRIES 32 27 #define HPSA_SG_CHAIN 0x80000000 28 #define MAXREPLYQS 256 29 30 /* Command Status value */ 31 #define CMD_SUCCESS 0x0000 32 #define CMD_TARGET_STATUS 0x0001 33 #define CMD_DATA_UNDERRUN 0x0002 34 #define CMD_DATA_OVERRUN 0x0003 35 #define CMD_INVALID 0x0004 36 #define CMD_PROTOCOL_ERR 0x0005 37 #define CMD_HARDWARE_ERR 0x0006 38 #define CMD_CONNECTION_LOST 0x0007 39 #define CMD_ABORTED 0x0008 40 #define CMD_ABORT_FAILED 0x0009 41 #define CMD_UNSOLICITED_ABORT 0x000A 42 #define CMD_TIMEOUT 0x000B 43 #define CMD_UNABORTABLE 0x000C 44 45 /* Unit Attentions ASC's as defined for the MSA2012sa */ 46 #define POWER_OR_RESET 0x29 47 #define STATE_CHANGED 0x2a 48 #define UNIT_ATTENTION_CLEARED 0x2f 49 #define LUN_FAILED 0x3e 50 #define REPORT_LUNS_CHANGED 0x3f 51 52 /* Unit Attentions ASCQ's as defined for the MSA2012sa */ 53 54 /* These ASCQ's defined for ASC = POWER_OR_RESET */ 55 #define POWER_ON_RESET 0x00 56 #define POWER_ON_REBOOT 0x01 57 #define SCSI_BUS_RESET 0x02 58 #define MSA_TARGET_RESET 0x03 59 #define CONTROLLER_FAILOVER 0x04 60 #define TRANSCEIVER_SE 0x05 61 #define TRANSCEIVER_LVD 0x06 62 63 /* These ASCQ's defined for ASC = STATE_CHANGED */ 64 #define RESERVATION_PREEMPTED 0x03 65 #define ASYM_ACCESS_CHANGED 0x06 66 #define LUN_CAPACITY_CHANGED 0x09 67 68 /* transfer direction */ 69 #define XFER_NONE 0x00 70 #define XFER_WRITE 0x01 71 #define XFER_READ 0x02 72 #define XFER_RSVD 0x03 73 74 /* task attribute */ 75 #define ATTR_UNTAGGED 0x00 76 #define ATTR_SIMPLE 0x04 77 #define ATTR_HEADOFQUEUE 0x05 78 #define ATTR_ORDERED 0x06 79 #define ATTR_ACA 0x07 80 81 /* cdb type */ 82 #define TYPE_CMD 0x00 83 #define TYPE_MSG 0x01 84 85 /* config space register offsets */ 86 #define CFG_VENDORID 0x00 87 #define CFG_DEVICEID 0x02 88 #define CFG_I2OBAR 0x10 89 #define CFG_MEM1BAR 0x14 90 91 /* i2o space register offsets */ 92 #define I2O_IBDB_SET 0x20 93 #define I2O_IBDB_CLEAR 0x70 94 #define I2O_INT_STATUS 0x30 95 #define I2O_INT_MASK 0x34 96 #define I2O_IBPOST_Q 0x40 97 #define I2O_OBPOST_Q 0x44 98 #define I2O_DMA1_CFG 0x214 99 100 /* Configuration Table */ 101 #define CFGTBL_ChangeReq 0x00000001l 102 #define CFGTBL_AccCmds 0x00000001l 103 104 #define CFGTBL_Trans_Simple 0x00000002l 105 #define CFGTBL_Trans_Performant 0x00000004l 106 107 #define CFGTBL_BusType_Ultra2 0x00000001l 108 #define CFGTBL_BusType_Ultra3 0x00000002l 109 #define CFGTBL_BusType_Fibre1G 0x00000100l 110 #define CFGTBL_BusType_Fibre2G 0x00000200l 111 struct vals32 { 112 u32 lower; 113 u32 upper; 114 }; 115 116 union u64bit { 117 struct vals32 val32; 118 u64 val; 119 }; 120 121 /* FIXME this is a per controller value (barf!) */ 122 #define HPSA_MAX_TARGETS_PER_CTLR 16 123 #define HPSA_MAX_LUN 256 124 #define HPSA_MAX_PHYS_LUN 1024 125 126 /* SCSI-3 Commands */ 127 #pragma pack(1) 128 129 #define HPSA_INQUIRY 0x12 130 struct InquiryData { 131 u8 data_byte[36]; 132 }; 133 134 #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ 135 #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 136 struct ReportLUNdata { 137 u8 LUNListLength[4]; 138 u32 reserved; 139 u8 LUN[HPSA_MAX_LUN][8]; 140 }; 141 142 struct ReportExtendedLUNdata { 143 u8 LUNListLength[4]; 144 u8 extended_response_flag; 145 u8 reserved[3]; 146 u8 LUN[HPSA_MAX_LUN][24]; 147 }; 148 149 struct SenseSubsystem_info { 150 u8 reserved[36]; 151 u8 portname[8]; 152 u8 reserved1[1108]; 153 }; 154 155 /* BMIC commands */ 156 #define BMIC_READ 0x26 157 #define BMIC_WRITE 0x27 158 #define BMIC_CACHE_FLUSH 0xc2 159 #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ 160 161 /* Command List Structure */ 162 union SCSI3Addr { 163 struct { 164 u8 Dev; 165 u8 Bus:6; 166 u8 Mode:2; /* b00 */ 167 } PeripDev; 168 struct { 169 u8 DevLSB; 170 u8 DevMSB:6; 171 u8 Mode:2; /* b01 */ 172 } LogDev; 173 struct { 174 u8 Dev:5; 175 u8 Bus:3; 176 u8 Targ:6; 177 u8 Mode:2; /* b10 */ 178 } LogUnit; 179 }; 180 181 struct PhysDevAddr { 182 u32 TargetId:24; 183 u32 Bus:6; 184 u32 Mode:2; 185 /* 2 level target device addr */ 186 union SCSI3Addr Target[2]; 187 }; 188 189 struct LogDevAddr { 190 u32 VolId:30; 191 u32 Mode:2; 192 u8 reserved[4]; 193 }; 194 195 union LUNAddr { 196 u8 LunAddrBytes[8]; 197 union SCSI3Addr SCSI3Lun[4]; 198 struct PhysDevAddr PhysDev; 199 struct LogDevAddr LogDev; 200 }; 201 202 struct CommandListHeader { 203 u8 ReplyQueue; 204 u8 SGList; 205 u16 SGTotal; 206 struct vals32 Tag; 207 union LUNAddr LUN; 208 }; 209 210 struct RequestBlock { 211 u8 CDBLen; 212 struct { 213 u8 Type:3; 214 u8 Attribute:3; 215 u8 Direction:2; 216 } Type; 217 u16 Timeout; 218 u8 CDB[16]; 219 }; 220 221 struct ErrDescriptor { 222 struct vals32 Addr; 223 u32 Len; 224 }; 225 226 struct SGDescriptor { 227 struct vals32 Addr; 228 u32 Len; 229 u32 Ext; 230 }; 231 232 union MoreErrInfo { 233 struct { 234 u8 Reserved[3]; 235 u8 Type; 236 u32 ErrorInfo; 237 } Common_Info; 238 struct { 239 u8 Reserved[2]; 240 u8 offense_size; /* size of offending entry */ 241 u8 offense_num; /* byte # of offense 0-base */ 242 u32 offense_value; 243 } Invalid_Cmd; 244 }; 245 struct ErrorInfo { 246 u8 ScsiStatus; 247 u8 SenseLen; 248 u16 CommandStatus; 249 u32 ResidualCnt; 250 union MoreErrInfo MoreErrInfo; 251 u8 SenseInfo[SENSEINFOBYTES]; 252 }; 253 /* Command types */ 254 #define CMD_IOCTL_PEND 0x01 255 #define CMD_SCSI 0x03 256 257 /* This structure needs to be divisible by 32 for new 258 * indexing method and performant mode. 259 */ 260 #define PAD32 32 261 #define PAD64DIFF 0 262 #define USEEXTRA ((sizeof(void *) - 4)/4) 263 #define PADSIZE (PAD32 + PAD64DIFF * USEEXTRA) 264 265 #define DIRECT_LOOKUP_SHIFT 5 266 #define DIRECT_LOOKUP_BIT 0x10 267 268 #define HPSA_ERROR_BIT 0x02 269 struct ctlr_info; /* defined in hpsa.h */ 270 /* The size of this structure needs to be divisible by 32 271 * on all architectures because low 5 bits of the addresses 272 * are used as follows: 273 * 274 * bit 0: to device, used to indicate "performant mode" command 275 * from device, indidcates error status. 276 * bit 1-3: to device, indicates block fetch table entry for 277 * reducing DMA in fetching commands from host memory. 278 * bit 4: used to indicate whether tag is "direct lookup" (index), 279 * or a bus address. 280 */ 281 282 struct CommandList { 283 struct CommandListHeader Header; 284 struct RequestBlock Request; 285 struct ErrDescriptor ErrDesc; 286 struct SGDescriptor SG[MAXSGENTRIES]; 287 /* information associated with the command */ 288 u32 busaddr; /* physical addr of this record */ 289 struct ErrorInfo *err_info; /* pointer to the allocated mem */ 290 struct ctlr_info *h; 291 int cmd_type; 292 long cmdindex; 293 struct hlist_node list; 294 struct request *rq; 295 struct completion *waiting; 296 void *scsi_cmd; 297 298 /* on 64 bit architectures, to get this to be 32-byte-aligned 299 * it so happens we need PAD_64 bytes of padding, on 32 bit systems, 300 * we need PAD_32 bytes of padding (see below). This does that. 301 * If it happens that 64 bit and 32 bit systems need different 302 * padding, PAD_32 and PAD_64 can be set independently, and. 303 * the code below will do the right thing. 304 */ 305 #define IS_32_BIT ((8 - sizeof(long))/4) 306 #define IS_64_BIT (!IS_32_BIT) 307 #define PAD_32 (4) 308 #define PAD_64 (4) 309 #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64) 310 u8 pad[COMMANDLIST_PAD]; 311 }; 312 313 /* Configuration Table Structure */ 314 struct HostWrite { 315 u32 TransportRequest; 316 u32 Reserved; 317 u32 CoalIntDelay; 318 u32 CoalIntCount; 319 }; 320 321 #define SIMPLE_MODE 0x02 322 #define PERFORMANT_MODE 0x04 323 #define MEMQ_MODE 0x08 324 325 struct CfgTable { 326 u8 Signature[4]; 327 u32 SpecValence; 328 u32 TransportSupport; 329 u32 TransportActive; 330 struct HostWrite HostWrite; 331 u32 CmdsOutMax; 332 u32 BusTypes; 333 u32 TransMethodOffset; 334 u8 ServerName[16]; 335 u32 HeartBeat; 336 u32 SCSI_Prefetch; 337 u32 MaxScatterGatherElements; 338 u32 MaxLogicalUnits; 339 u32 MaxPhysicalDevices; 340 u32 MaxPhysicalDrivesPerLogicalUnit; 341 u32 MaxPerformantModeCommands; 342 }; 343 344 #define NUM_BLOCKFETCH_ENTRIES 8 345 struct TransTable_struct { 346 u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; 347 u32 RepQSize; 348 u32 RepQCount; 349 u32 RepQCtrAddrLow32; 350 u32 RepQCtrAddrHigh32; 351 u32 RepQAddr0Low32; 352 u32 RepQAddr0High32; 353 }; 354 355 struct hpsa_pci_info { 356 unsigned char bus; 357 unsigned char dev_fn; 358 unsigned short domain; 359 u32 board_id; 360 }; 361 362 #pragma pack() 363 #endif /* HPSA_CMD_H */ 364