1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 * NON INFRINGEMENT. See the GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 * 18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com 19 * 20 */ 21 #ifndef HPSA_CMD_H 22 #define HPSA_CMD_H 23 24 /* general boundary defintions */ 25 #define SENSEINFOBYTES 32 /* may vary between hbas */ 26 #define MAXSGENTRIES 32 27 #define HPSA_SG_CHAIN 0x80000000 28 #define MAXREPLYQS 256 29 30 /* Command Status value */ 31 #define CMD_SUCCESS 0x0000 32 #define CMD_TARGET_STATUS 0x0001 33 #define CMD_DATA_UNDERRUN 0x0002 34 #define CMD_DATA_OVERRUN 0x0003 35 #define CMD_INVALID 0x0004 36 #define CMD_PROTOCOL_ERR 0x0005 37 #define CMD_HARDWARE_ERR 0x0006 38 #define CMD_CONNECTION_LOST 0x0007 39 #define CMD_ABORTED 0x0008 40 #define CMD_ABORT_FAILED 0x0009 41 #define CMD_UNSOLICITED_ABORT 0x000A 42 #define CMD_TIMEOUT 0x000B 43 #define CMD_UNABORTABLE 0x000C 44 45 /* Unit Attentions ASC's as defined for the MSA2012sa */ 46 #define POWER_OR_RESET 0x29 47 #define STATE_CHANGED 0x2a 48 #define UNIT_ATTENTION_CLEARED 0x2f 49 #define LUN_FAILED 0x3e 50 #define REPORT_LUNS_CHANGED 0x3f 51 52 /* Unit Attentions ASCQ's as defined for the MSA2012sa */ 53 54 /* These ASCQ's defined for ASC = POWER_OR_RESET */ 55 #define POWER_ON_RESET 0x00 56 #define POWER_ON_REBOOT 0x01 57 #define SCSI_BUS_RESET 0x02 58 #define MSA_TARGET_RESET 0x03 59 #define CONTROLLER_FAILOVER 0x04 60 #define TRANSCEIVER_SE 0x05 61 #define TRANSCEIVER_LVD 0x06 62 63 /* These ASCQ's defined for ASC = STATE_CHANGED */ 64 #define RESERVATION_PREEMPTED 0x03 65 #define ASYM_ACCESS_CHANGED 0x06 66 #define LUN_CAPACITY_CHANGED 0x09 67 68 /* transfer direction */ 69 #define XFER_NONE 0x00 70 #define XFER_WRITE 0x01 71 #define XFER_READ 0x02 72 #define XFER_RSVD 0x03 73 74 /* task attribute */ 75 #define ATTR_UNTAGGED 0x00 76 #define ATTR_SIMPLE 0x04 77 #define ATTR_HEADOFQUEUE 0x05 78 #define ATTR_ORDERED 0x06 79 #define ATTR_ACA 0x07 80 81 /* cdb type */ 82 #define TYPE_CMD 0x00 83 #define TYPE_MSG 0x01 84 85 /* config space register offsets */ 86 #define CFG_VENDORID 0x00 87 #define CFG_DEVICEID 0x02 88 #define CFG_I2OBAR 0x10 89 #define CFG_MEM1BAR 0x14 90 91 /* i2o space register offsets */ 92 #define I2O_IBDB_SET 0x20 93 #define I2O_IBDB_CLEAR 0x70 94 #define I2O_INT_STATUS 0x30 95 #define I2O_INT_MASK 0x34 96 #define I2O_IBPOST_Q 0x40 97 #define I2O_OBPOST_Q 0x44 98 #define I2O_DMA1_CFG 0x214 99 100 /* Configuration Table */ 101 #define CFGTBL_ChangeReq 0x00000001l 102 #define CFGTBL_AccCmds 0x00000001l 103 #define DOORBELL_CTLR_RESET 0x00000004l 104 #define DOORBELL_CTLR_RESET2 0x00000020l 105 106 #define CFGTBL_Trans_Simple 0x00000002l 107 #define CFGTBL_Trans_Performant 0x00000004l 108 #define CFGTBL_Trans_use_short_tags 0x20000000l 109 110 #define CFGTBL_BusType_Ultra2 0x00000001l 111 #define CFGTBL_BusType_Ultra3 0x00000002l 112 #define CFGTBL_BusType_Fibre1G 0x00000100l 113 #define CFGTBL_BusType_Fibre2G 0x00000200l 114 struct vals32 { 115 u32 lower; 116 u32 upper; 117 }; 118 119 union u64bit { 120 struct vals32 val32; 121 u64 val; 122 }; 123 124 /* FIXME this is a per controller value (barf!) */ 125 #define HPSA_MAX_TARGETS_PER_CTLR 16 126 #define HPSA_MAX_LUN 1024 127 #define HPSA_MAX_PHYS_LUN 1024 128 #define MAX_MSA2XXX_ENCLOSURES 32 129 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \ 130 MAX_MSA2XXX_ENCLOSURES + 1) /* + 1 is for the controller itself */ 131 132 /* SCSI-3 Commands */ 133 #pragma pack(1) 134 135 #define HPSA_INQUIRY 0x12 136 struct InquiryData { 137 u8 data_byte[36]; 138 }; 139 140 #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ 141 #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 142 struct ReportLUNdata { 143 u8 LUNListLength[4]; 144 u32 reserved; 145 u8 LUN[HPSA_MAX_LUN][8]; 146 }; 147 148 struct ReportExtendedLUNdata { 149 u8 LUNListLength[4]; 150 u8 extended_response_flag; 151 u8 reserved[3]; 152 u8 LUN[HPSA_MAX_LUN][24]; 153 }; 154 155 struct SenseSubsystem_info { 156 u8 reserved[36]; 157 u8 portname[8]; 158 u8 reserved1[1108]; 159 }; 160 161 /* BMIC commands */ 162 #define BMIC_READ 0x26 163 #define BMIC_WRITE 0x27 164 #define BMIC_CACHE_FLUSH 0xc2 165 #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ 166 167 /* Command List Structure */ 168 union SCSI3Addr { 169 struct { 170 u8 Dev; 171 u8 Bus:6; 172 u8 Mode:2; /* b00 */ 173 } PeripDev; 174 struct { 175 u8 DevLSB; 176 u8 DevMSB:6; 177 u8 Mode:2; /* b01 */ 178 } LogDev; 179 struct { 180 u8 Dev:5; 181 u8 Bus:3; 182 u8 Targ:6; 183 u8 Mode:2; /* b10 */ 184 } LogUnit; 185 }; 186 187 struct PhysDevAddr { 188 u32 TargetId:24; 189 u32 Bus:6; 190 u32 Mode:2; 191 /* 2 level target device addr */ 192 union SCSI3Addr Target[2]; 193 }; 194 195 struct LogDevAddr { 196 u32 VolId:30; 197 u32 Mode:2; 198 u8 reserved[4]; 199 }; 200 201 union LUNAddr { 202 u8 LunAddrBytes[8]; 203 union SCSI3Addr SCSI3Lun[4]; 204 struct PhysDevAddr PhysDev; 205 struct LogDevAddr LogDev; 206 }; 207 208 struct CommandListHeader { 209 u8 ReplyQueue; 210 u8 SGList; 211 u16 SGTotal; 212 struct vals32 Tag; 213 union LUNAddr LUN; 214 }; 215 216 struct RequestBlock { 217 u8 CDBLen; 218 struct { 219 u8 Type:3; 220 u8 Attribute:3; 221 u8 Direction:2; 222 } Type; 223 u16 Timeout; 224 u8 CDB[16]; 225 }; 226 227 struct ErrDescriptor { 228 struct vals32 Addr; 229 u32 Len; 230 }; 231 232 struct SGDescriptor { 233 struct vals32 Addr; 234 u32 Len; 235 u32 Ext; 236 }; 237 238 union MoreErrInfo { 239 struct { 240 u8 Reserved[3]; 241 u8 Type; 242 u32 ErrorInfo; 243 } Common_Info; 244 struct { 245 u8 Reserved[2]; 246 u8 offense_size; /* size of offending entry */ 247 u8 offense_num; /* byte # of offense 0-base */ 248 u32 offense_value; 249 } Invalid_Cmd; 250 }; 251 struct ErrorInfo { 252 u8 ScsiStatus; 253 u8 SenseLen; 254 u16 CommandStatus; 255 u32 ResidualCnt; 256 union MoreErrInfo MoreErrInfo; 257 u8 SenseInfo[SENSEINFOBYTES]; 258 }; 259 /* Command types */ 260 #define CMD_IOCTL_PEND 0x01 261 #define CMD_SCSI 0x03 262 263 #define DIRECT_LOOKUP_SHIFT 5 264 #define DIRECT_LOOKUP_BIT 0x10 265 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1)) 266 267 #define HPSA_ERROR_BIT 0x02 268 struct ctlr_info; /* defined in hpsa.h */ 269 /* The size of this structure needs to be divisible by 32 270 * on all architectures because low 5 bits of the addresses 271 * are used as follows: 272 * 273 * bit 0: to device, used to indicate "performant mode" command 274 * from device, indidcates error status. 275 * bit 1-3: to device, indicates block fetch table entry for 276 * reducing DMA in fetching commands from host memory. 277 * bit 4: used to indicate whether tag is "direct lookup" (index), 278 * or a bus address. 279 */ 280 281 struct CommandList { 282 struct CommandListHeader Header; 283 struct RequestBlock Request; 284 struct ErrDescriptor ErrDesc; 285 struct SGDescriptor SG[MAXSGENTRIES]; 286 /* information associated with the command */ 287 u32 busaddr; /* physical addr of this record */ 288 struct ErrorInfo *err_info; /* pointer to the allocated mem */ 289 struct ctlr_info *h; 290 int cmd_type; 291 long cmdindex; 292 struct list_head list; 293 struct request *rq; 294 struct completion *waiting; 295 void *scsi_cmd; 296 297 /* on 64 bit architectures, to get this to be 32-byte-aligned 298 * it so happens we need PAD_64 bytes of padding, on 32 bit systems, 299 * we need PAD_32 bytes of padding (see below). This does that. 300 * If it happens that 64 bit and 32 bit systems need different 301 * padding, PAD_32 and PAD_64 can be set independently, and. 302 * the code below will do the right thing. 303 */ 304 #define IS_32_BIT ((8 - sizeof(long))/4) 305 #define IS_64_BIT (!IS_32_BIT) 306 #define PAD_32 (4) 307 #define PAD_64 (4) 308 #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64) 309 u8 pad[COMMANDLIST_PAD]; 310 }; 311 312 /* Configuration Table Structure */ 313 struct HostWrite { 314 u32 TransportRequest; 315 u32 Reserved; 316 u32 CoalIntDelay; 317 u32 CoalIntCount; 318 }; 319 320 #define SIMPLE_MODE 0x02 321 #define PERFORMANT_MODE 0x04 322 #define MEMQ_MODE 0x08 323 324 struct CfgTable { 325 u8 Signature[4]; 326 u32 SpecValence; 327 u32 TransportSupport; 328 u32 TransportActive; 329 struct HostWrite HostWrite; 330 u32 CmdsOutMax; 331 u32 BusTypes; 332 u32 TransMethodOffset; 333 u8 ServerName[16]; 334 u32 HeartBeat; 335 u32 SCSI_Prefetch; 336 u32 MaxScatterGatherElements; 337 u32 MaxLogicalUnits; 338 u32 MaxPhysicalDevices; 339 u32 MaxPhysicalDrivesPerLogicalUnit; 340 u32 MaxPerformantModeCommands; 341 u8 reserved[0x78 - 0x58]; 342 u32 misc_fw_support; /* offset 0x78 */ 343 #define MISC_FW_DOORBELL_RESET (0x02) 344 #define MISC_FW_DOORBELL_RESET2 (0x010) 345 u8 driver_version[32]; 346 }; 347 348 #define NUM_BLOCKFETCH_ENTRIES 8 349 struct TransTable_struct { 350 u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; 351 u32 RepQSize; 352 u32 RepQCount; 353 u32 RepQCtrAddrLow32; 354 u32 RepQCtrAddrHigh32; 355 u32 RepQAddr0Low32; 356 u32 RepQAddr0High32; 357 }; 358 359 struct hpsa_pci_info { 360 unsigned char bus; 361 unsigned char dev_fn; 362 unsigned short domain; 363 u32 board_id; 364 }; 365 366 #pragma pack() 367 #endif /* HPSA_CMD_H */ 368