1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 * NON INFRINGEMENT. See the GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 * 18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com 19 * 20 */ 21 #ifndef HPSA_H 22 #define HPSA_H 23 24 #include <scsi/scsicam.h> 25 26 #define IO_OK 0 27 #define IO_ERROR 1 28 29 struct ctlr_info; 30 31 struct access_method { 32 void (*submit_command)(struct ctlr_info *h, 33 struct CommandList *c); 34 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 35 unsigned long (*fifo_full)(struct ctlr_info *h); 36 bool (*intr_pending)(struct ctlr_info *h); 37 unsigned long (*command_completed)(struct ctlr_info *h); 38 }; 39 40 struct hpsa_scsi_dev_t { 41 int devtype; 42 int bus, target, lun; /* as presented to the OS */ 43 unsigned char scsi3addr[8]; /* as presented to the HW */ 44 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 45 unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 46 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 47 unsigned char model[16]; /* bytes 16-31 of inquiry data */ 48 unsigned char raid_level; /* from inquiry page 0xC1 */ 49 }; 50 51 struct ctlr_info { 52 int ctlr; 53 char devname[8]; 54 char *product_name; 55 struct pci_dev *pdev; 56 u32 board_id; 57 void __iomem *vaddr; 58 unsigned long paddr; 59 int nr_cmds; /* Number of commands allowed on this controller */ 60 struct CfgTable __iomem *cfgtable; 61 int max_sg_entries; 62 int interrupts_enabled; 63 int major; 64 int max_commands; 65 int commands_outstanding; 66 int max_outstanding; /* Debug */ 67 int usage_count; /* number of opens all all minor devices */ 68 # define PERF_MODE_INT 0 69 # define DOORBELL_INT 1 70 # define SIMPLE_MODE_INT 2 71 # define MEMQ_MODE_INT 3 72 unsigned int intr[4]; 73 unsigned int msix_vector; 74 unsigned int msi_vector; 75 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 76 struct access_method access; 77 78 /* queue and queue Info */ 79 struct list_head reqQ; 80 struct list_head cmpQ; 81 unsigned int Qdepth; 82 unsigned int maxQsinceinit; 83 unsigned int maxSG; 84 spinlock_t lock; 85 int maxsgentries; 86 u8 max_cmd_sg_entries; 87 int chainsize; 88 struct SGDescriptor **cmd_sg_list; 89 90 /* pointers to command and error info pool */ 91 struct CommandList *cmd_pool; 92 dma_addr_t cmd_pool_dhandle; 93 struct ErrorInfo *errinfo_pool; 94 dma_addr_t errinfo_pool_dhandle; 95 unsigned long *cmd_pool_bits; 96 int nr_allocs; 97 int nr_frees; 98 int busy_initializing; 99 int busy_scanning; 100 int scan_finished; 101 spinlock_t scan_lock; 102 wait_queue_head_t scan_wait_queue; 103 104 struct Scsi_Host *scsi_host; 105 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 106 int ndevices; /* number of used elements in .dev[] array. */ 107 #define HPSA_MAX_SCSI_DEVS_PER_HBA 256 108 struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA]; 109 /* 110 * Performant mode tables. 111 */ 112 u32 trans_support; 113 u32 trans_offset; 114 struct TransTable_struct *transtable; 115 unsigned long transMethod; 116 117 /* 118 * Performant mode completion buffer 119 */ 120 u64 *reply_pool; 121 dma_addr_t reply_pool_dhandle; 122 u64 *reply_pool_head; 123 size_t reply_pool_size; 124 unsigned char reply_pool_wraparound; 125 u32 *blockFetchTable; 126 unsigned char *hba_inquiry_data; 127 }; 128 #define HPSA_ABORT_MSG 0 129 #define HPSA_DEVICE_RESET_MSG 1 130 #define HPSA_BUS_RESET_MSG 2 131 #define HPSA_HOST_RESET_MSG 3 132 #define HPSA_MSG_SEND_RETRY_LIMIT 10 133 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000 134 135 /* Maximum time in seconds driver will wait for command completions 136 * when polling before giving up. 137 */ 138 #define HPSA_MAX_POLL_TIME_SECS (20) 139 140 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 141 * how many times to retry TEST UNIT READY on a device 142 * while waiting for it to become ready before giving up. 143 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 144 * between sending TURs while waiting for a device 145 * to become ready. 146 */ 147 #define HPSA_TUR_RETRY_LIMIT (20) 148 #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 149 150 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 151 * to become ready, in seconds, before giving up on it. 152 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 153 * between polling the board to see if it is ready, in 154 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 155 * HPSA_BOARD_READY_ITERATIONS are derived from those. 156 */ 157 #define HPSA_BOARD_READY_WAIT_SECS (120) 158 #define HPSA_BOARD_NOT_READY_WAIT_SECS (10) 159 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 160 #define HPSA_BOARD_READY_POLL_INTERVAL \ 161 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 162 #define HPSA_BOARD_READY_ITERATIONS \ 163 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 164 HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 165 #define HPSA_BOARD_NOT_READY_ITERATIONS \ 166 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 167 HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 168 #define HPSA_POST_RESET_PAUSE_MSECS (3000) 169 #define HPSA_POST_RESET_NOOP_RETRIES (12) 170 171 /* Defining the diffent access_menthods */ 172 /* 173 * Memory mapped FIFO interface (SMART 53xx cards) 174 */ 175 #define SA5_DOORBELL 0x20 176 #define SA5_REQUEST_PORT_OFFSET 0x40 177 #define SA5_REPLY_INTR_MASK_OFFSET 0x34 178 #define SA5_REPLY_PORT_OFFSET 0x44 179 #define SA5_INTR_STATUS 0x30 180 #define SA5_SCRATCHPAD_OFFSET 0xB0 181 182 #define SA5_CTCFG_OFFSET 0xB4 183 #define SA5_CTMEM_OFFSET 0xB8 184 185 #define SA5_INTR_OFF 0x08 186 #define SA5B_INTR_OFF 0x04 187 #define SA5_INTR_PENDING 0x08 188 #define SA5B_INTR_PENDING 0x04 189 #define FIFO_EMPTY 0xffffffff 190 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 191 192 #define HPSA_ERROR_BIT 0x02 193 194 /* Performant mode flags */ 195 #define SA5_PERF_INTR_PENDING 0x04 196 #define SA5_PERF_INTR_OFF 0x05 197 #define SA5_OUTDB_STATUS_PERF_BIT 0x01 198 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 199 #define SA5_OUTDB_CLEAR 0xA0 200 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 201 #define SA5_OUTDB_STATUS 0x9C 202 203 204 #define HPSA_INTR_ON 1 205 #define HPSA_INTR_OFF 0 206 /* 207 Send the command to the hardware 208 */ 209 static void SA5_submit_command(struct ctlr_info *h, 210 struct CommandList *c) 211 { 212 dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr, 213 c->Header.Tag.lower); 214 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 215 h->commands_outstanding++; 216 if (h->commands_outstanding > h->max_outstanding) 217 h->max_outstanding = h->commands_outstanding; 218 } 219 220 /* 221 * This card is the opposite of the other cards. 222 * 0 turns interrupts on... 223 * 0x08 turns them off... 224 */ 225 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 226 { 227 if (val) { /* Turn interrupts on */ 228 h->interrupts_enabled = 1; 229 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 230 } else { /* Turn them off */ 231 h->interrupts_enabled = 0; 232 writel(SA5_INTR_OFF, 233 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 234 } 235 } 236 237 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 238 { 239 if (val) { /* turn on interrupts */ 240 h->interrupts_enabled = 1; 241 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 242 } else { 243 h->interrupts_enabled = 0; 244 writel(SA5_PERF_INTR_OFF, 245 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 246 } 247 } 248 249 static unsigned long SA5_performant_completed(struct ctlr_info *h) 250 { 251 unsigned long register_value = FIFO_EMPTY; 252 253 /* flush the controller write of the reply queue by reading 254 * outbound doorbell status register. 255 */ 256 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 257 /* msi auto clears the interrupt pending bit. */ 258 if (!(h->msi_vector || h->msix_vector)) { 259 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 260 /* Do a read in order to flush the write to the controller 261 * (as per spec.) 262 */ 263 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 264 } 265 266 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) { 267 register_value = *(h->reply_pool_head); 268 (h->reply_pool_head)++; 269 h->commands_outstanding--; 270 } else { 271 register_value = FIFO_EMPTY; 272 } 273 /* Check for wraparound */ 274 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) { 275 h->reply_pool_head = h->reply_pool; 276 h->reply_pool_wraparound ^= 1; 277 } 278 279 return register_value; 280 } 281 282 /* 283 * Returns true if fifo is full. 284 * 285 */ 286 static unsigned long SA5_fifo_full(struct ctlr_info *h) 287 { 288 if (h->commands_outstanding >= h->max_commands) 289 return 1; 290 else 291 return 0; 292 293 } 294 /* 295 * returns value read from hardware. 296 * returns FIFO_EMPTY if there is nothing to read 297 */ 298 static unsigned long SA5_completed(struct ctlr_info *h) 299 { 300 unsigned long register_value 301 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 302 303 if (register_value != FIFO_EMPTY) 304 h->commands_outstanding--; 305 306 #ifdef HPSA_DEBUG 307 if (register_value != FIFO_EMPTY) 308 dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 309 register_value); 310 else 311 dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n"); 312 #endif 313 314 return register_value; 315 } 316 /* 317 * Returns true if an interrupt is pending.. 318 */ 319 static bool SA5_intr_pending(struct ctlr_info *h) 320 { 321 unsigned long register_value = 322 readl(h->vaddr + SA5_INTR_STATUS); 323 dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value); 324 return register_value & SA5_INTR_PENDING; 325 } 326 327 static bool SA5_performant_intr_pending(struct ctlr_info *h) 328 { 329 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 330 331 if (!register_value) 332 return false; 333 334 if (h->msi_vector || h->msix_vector) 335 return true; 336 337 /* Read outbound doorbell to flush */ 338 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 339 return register_value & SA5_OUTDB_STATUS_PERF_BIT; 340 } 341 342 static struct access_method SA5_access = { 343 SA5_submit_command, 344 SA5_intr_mask, 345 SA5_fifo_full, 346 SA5_intr_pending, 347 SA5_completed, 348 }; 349 350 static struct access_method SA5_performant_access = { 351 SA5_submit_command, 352 SA5_performant_intr_mask, 353 SA5_fifo_full, 354 SA5_performant_intr_pending, 355 SA5_performant_completed, 356 }; 357 358 struct board_type { 359 u32 board_id; 360 char *product_name; 361 struct access_method *access; 362 }; 363 364 #endif /* HPSA_H */ 365 366