xref: /linux/drivers/scsi/hpsa.h (revision 26b0d14106954ae46d2f4f7eec3481828a210f7d)
1 /*
2  *    Disk Array driver for HP Smart Array SAS controllers
3  *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4  *
5  *    This program is free software; you can redistribute it and/or modify
6  *    it under the terms of the GNU General Public License as published by
7  *    the Free Software Foundation; version 2 of the License.
8  *
9  *    This program is distributed in the hope that it will be useful,
10  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
11  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
13  *
14  *    You should have received a copy of the GNU General Public License
15  *    along with this program; if not, write to the Free Software
16  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17  *
18  *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
19  *
20  */
21 #ifndef HPSA_H
22 #define HPSA_H
23 
24 #include <scsi/scsicam.h>
25 
26 #define IO_OK		0
27 #define IO_ERROR	1
28 
29 struct ctlr_info;
30 
31 struct access_method {
32 	void (*submit_command)(struct ctlr_info *h,
33 		struct CommandList *c);
34 	void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35 	unsigned long (*fifo_full)(struct ctlr_info *h);
36 	bool (*intr_pending)(struct ctlr_info *h);
37 	unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
38 };
39 
40 struct hpsa_scsi_dev_t {
41 	int devtype;
42 	int bus, target, lun;		/* as presented to the OS */
43 	unsigned char scsi3addr[8];	/* as presented to the HW */
44 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
45 	unsigned char device_id[16];    /* from inquiry pg. 0x83 */
46 	unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
47 	unsigned char model[16];        /* bytes 16-31 of inquiry data */
48 	unsigned char raid_level;	/* from inquiry page 0xC1 */
49 };
50 
51 struct reply_pool {
52 	u64 *head;
53 	size_t size;
54 	u8 wraparound;
55 	u32 current_entry;
56 };
57 
58 struct ctlr_info {
59 	int	ctlr;
60 	char	devname[8];
61 	char    *product_name;
62 	struct pci_dev *pdev;
63 	u32	board_id;
64 	void __iomem *vaddr;
65 	unsigned long paddr;
66 	int 	nr_cmds; /* Number of commands allowed on this controller */
67 	struct CfgTable __iomem *cfgtable;
68 	int	interrupts_enabled;
69 	int	major;
70 	int 	max_commands;
71 	int	commands_outstanding;
72 	int 	max_outstanding; /* Debug */
73 	int	usage_count;  /* number of opens all all minor devices */
74 #	define PERF_MODE_INT	0
75 #	define DOORBELL_INT	1
76 #	define SIMPLE_MODE_INT	2
77 #	define MEMQ_MODE_INT	3
78 	unsigned int intr[MAX_REPLY_QUEUES];
79 	unsigned int msix_vector;
80 	unsigned int msi_vector;
81 	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
82 	struct access_method access;
83 
84 	/* queue and queue Info */
85 	struct list_head reqQ;
86 	struct list_head cmpQ;
87 	unsigned int Qdepth;
88 	unsigned int maxSG;
89 	spinlock_t lock;
90 	int maxsgentries;
91 	u8 max_cmd_sg_entries;
92 	int chainsize;
93 	struct SGDescriptor **cmd_sg_list;
94 
95 	/* pointers to command and error info pool */
96 	struct CommandList 	*cmd_pool;
97 	dma_addr_t		cmd_pool_dhandle;
98 	struct ErrorInfo 	*errinfo_pool;
99 	dma_addr_t		errinfo_pool_dhandle;
100 	unsigned long  		*cmd_pool_bits;
101 	int			nr_allocs;
102 	int			nr_frees;
103 	int			scan_finished;
104 	spinlock_t		scan_lock;
105 	wait_queue_head_t	scan_wait_queue;
106 
107 	struct Scsi_Host *scsi_host;
108 	spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
109 	int ndevices; /* number of used elements in .dev[] array. */
110 	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
111 	/*
112 	 * Performant mode tables.
113 	 */
114 	u32 trans_support;
115 	u32 trans_offset;
116 	struct TransTable_struct *transtable;
117 	unsigned long transMethod;
118 
119 	/*
120 	 * Performant mode completion buffers
121 	 */
122 	u64 *reply_pool;
123 	size_t reply_pool_size;
124 	struct reply_pool reply_queue[MAX_REPLY_QUEUES];
125 	u8 nreply_queues;
126 	dma_addr_t reply_pool_dhandle;
127 	u32 *blockFetchTable;
128 	unsigned char *hba_inquiry_data;
129 	u64 last_intr_timestamp;
130 	u32 last_heartbeat;
131 	u64 last_heartbeat_timestamp;
132 	u32 heartbeat_sample_interval;
133 	atomic_t firmware_flash_in_progress;
134 	u32 lockup_detected;
135 	struct list_head lockup_list;
136 	/* Address of h->q[x] is passed to intr handler to know which queue */
137 	u8 q[MAX_REPLY_QUEUES];
138 	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
139 #define HPSATMF_BITS_SUPPORTED  (1 << 0)
140 #define HPSATMF_PHYS_LUN_RESET  (1 << 1)
141 #define HPSATMF_PHYS_NEX_RESET  (1 << 2)
142 #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
143 #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
144 #define HPSATMF_PHYS_CLEAR_ACA  (1 << 5)
145 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
146 #define HPSATMF_PHYS_QRY_TASK   (1 << 7)
147 #define HPSATMF_PHYS_QRY_TSET   (1 << 8)
148 #define HPSATMF_PHYS_QRY_ASYNC  (1 << 9)
149 #define HPSATMF_MASK_SUPPORTED  (1 << 16)
150 #define HPSATMF_LOG_LUN_RESET   (1 << 17)
151 #define HPSATMF_LOG_NEX_RESET   (1 << 18)
152 #define HPSATMF_LOG_TASK_ABORT  (1 << 19)
153 #define HPSATMF_LOG_TSET_ABORT  (1 << 20)
154 #define HPSATMF_LOG_CLEAR_ACA   (1 << 21)
155 #define HPSATMF_LOG_CLEAR_TSET  (1 << 22)
156 #define HPSATMF_LOG_QRY_TASK    (1 << 23)
157 #define HPSATMF_LOG_QRY_TSET    (1 << 24)
158 #define HPSATMF_LOG_QRY_ASYNC   (1 << 25)
159 };
160 #define HPSA_ABORT_MSG 0
161 #define HPSA_DEVICE_RESET_MSG 1
162 #define HPSA_RESET_TYPE_CONTROLLER 0x00
163 #define HPSA_RESET_TYPE_BUS 0x01
164 #define HPSA_RESET_TYPE_TARGET 0x03
165 #define HPSA_RESET_TYPE_LUN 0x04
166 #define HPSA_MSG_SEND_RETRY_LIMIT 10
167 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
168 
169 /* Maximum time in seconds driver will wait for command completions
170  * when polling before giving up.
171  */
172 #define HPSA_MAX_POLL_TIME_SECS (20)
173 
174 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
175  * how many times to retry TEST UNIT READY on a device
176  * while waiting for it to become ready before giving up.
177  * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
178  * between sending TURs while waiting for a device
179  * to become ready.
180  */
181 #define HPSA_TUR_RETRY_LIMIT (20)
182 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
183 
184 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
185  * to become ready, in seconds, before giving up on it.
186  * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
187  * between polling the board to see if it is ready, in
188  * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
189  * HPSA_BOARD_READY_ITERATIONS are derived from those.
190  */
191 #define HPSA_BOARD_READY_WAIT_SECS (120)
192 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
193 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
194 #define HPSA_BOARD_READY_POLL_INTERVAL \
195 	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
196 #define HPSA_BOARD_READY_ITERATIONS \
197 	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
198 		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
199 #define HPSA_BOARD_NOT_READY_ITERATIONS \
200 	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
201 		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
202 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
203 #define HPSA_POST_RESET_NOOP_RETRIES (12)
204 
205 /*  Defining the diffent access_menthods */
206 /*
207  * Memory mapped FIFO interface (SMART 53xx cards)
208  */
209 #define SA5_DOORBELL	0x20
210 #define SA5_REQUEST_PORT_OFFSET	0x40
211 #define SA5_REPLY_INTR_MASK_OFFSET	0x34
212 #define SA5_REPLY_PORT_OFFSET		0x44
213 #define SA5_INTR_STATUS		0x30
214 #define SA5_SCRATCHPAD_OFFSET	0xB0
215 
216 #define SA5_CTCFG_OFFSET	0xB4
217 #define SA5_CTMEM_OFFSET	0xB8
218 
219 #define SA5_INTR_OFF		0x08
220 #define SA5B_INTR_OFF		0x04
221 #define SA5_INTR_PENDING	0x08
222 #define SA5B_INTR_PENDING	0x04
223 #define FIFO_EMPTY		0xffffffff
224 #define HPSA_FIRMWARE_READY	0xffff0000 /* value in scratchpad register */
225 
226 #define HPSA_ERROR_BIT		0x02
227 
228 /* Performant mode flags */
229 #define SA5_PERF_INTR_PENDING   0x04
230 #define SA5_PERF_INTR_OFF       0x05
231 #define SA5_OUTDB_STATUS_PERF_BIT       0x01
232 #define SA5_OUTDB_CLEAR_PERF_BIT        0x01
233 #define SA5_OUTDB_CLEAR         0xA0
234 #define SA5_OUTDB_CLEAR_PERF_BIT        0x01
235 #define SA5_OUTDB_STATUS        0x9C
236 
237 
238 #define HPSA_INTR_ON 	1
239 #define HPSA_INTR_OFF	0
240 /*
241 	Send the command to the hardware
242 */
243 static void SA5_submit_command(struct ctlr_info *h,
244 	struct CommandList *c)
245 {
246 	dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
247 		c->Header.Tag.lower);
248 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
249 	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
250 }
251 
252 /*
253  *  This card is the opposite of the other cards.
254  *   0 turns interrupts on...
255  *   0x08 turns them off...
256  */
257 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
258 {
259 	if (val) { /* Turn interrupts on */
260 		h->interrupts_enabled = 1;
261 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
262 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
263 	} else { /* Turn them off */
264 		h->interrupts_enabled = 0;
265 		writel(SA5_INTR_OFF,
266 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
267 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
268 	}
269 }
270 
271 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
272 {
273 	if (val) { /* turn on interrupts */
274 		h->interrupts_enabled = 1;
275 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
276 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
277 	} else {
278 		h->interrupts_enabled = 0;
279 		writel(SA5_PERF_INTR_OFF,
280 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
281 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
282 	}
283 }
284 
285 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
286 {
287 	struct reply_pool *rq = &h->reply_queue[q];
288 	unsigned long flags, register_value = FIFO_EMPTY;
289 
290 	/* msi auto clears the interrupt pending bit. */
291 	if (!(h->msi_vector || h->msix_vector)) {
292 		/* flush the controller write of the reply queue by reading
293 		 * outbound doorbell status register.
294 		 */
295 		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
296 		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
297 		/* Do a read in order to flush the write to the controller
298 		 * (as per spec.)
299 		 */
300 		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
301 	}
302 
303 	if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
304 		register_value = rq->head[rq->current_entry];
305 		rq->current_entry++;
306 		spin_lock_irqsave(&h->lock, flags);
307 		h->commands_outstanding--;
308 		spin_unlock_irqrestore(&h->lock, flags);
309 	} else {
310 		register_value = FIFO_EMPTY;
311 	}
312 	/* Check for wraparound */
313 	if (rq->current_entry == h->max_commands) {
314 		rq->current_entry = 0;
315 		rq->wraparound ^= 1;
316 	}
317 	return register_value;
318 }
319 
320 /*
321  *  Returns true if fifo is full.
322  *
323  */
324 static unsigned long SA5_fifo_full(struct ctlr_info *h)
325 {
326 	if (h->commands_outstanding >= h->max_commands)
327 		return 1;
328 	else
329 		return 0;
330 
331 }
332 /*
333  *   returns value read from hardware.
334  *     returns FIFO_EMPTY if there is nothing to read
335  */
336 static unsigned long SA5_completed(struct ctlr_info *h,
337 	__attribute__((unused)) u8 q)
338 {
339 	unsigned long register_value
340 		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
341 	unsigned long flags;
342 
343 	if (register_value != FIFO_EMPTY) {
344 		spin_lock_irqsave(&h->lock, flags);
345 		h->commands_outstanding--;
346 		spin_unlock_irqrestore(&h->lock, flags);
347 	}
348 
349 #ifdef HPSA_DEBUG
350 	if (register_value != FIFO_EMPTY)
351 		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
352 			register_value);
353 	else
354 		dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
355 #endif
356 
357 	return register_value;
358 }
359 /*
360  *	Returns true if an interrupt is pending..
361  */
362 static bool SA5_intr_pending(struct ctlr_info *h)
363 {
364 	unsigned long register_value  =
365 		readl(h->vaddr + SA5_INTR_STATUS);
366 	dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
367 	return register_value & SA5_INTR_PENDING;
368 }
369 
370 static bool SA5_performant_intr_pending(struct ctlr_info *h)
371 {
372 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
373 
374 	if (!register_value)
375 		return false;
376 
377 	if (h->msi_vector || h->msix_vector)
378 		return true;
379 
380 	/* Read outbound doorbell to flush */
381 	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
382 	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
383 }
384 
385 static struct access_method SA5_access = {
386 	SA5_submit_command,
387 	SA5_intr_mask,
388 	SA5_fifo_full,
389 	SA5_intr_pending,
390 	SA5_completed,
391 };
392 
393 static struct access_method SA5_performant_access = {
394 	SA5_submit_command,
395 	SA5_performant_intr_mask,
396 	SA5_fifo_full,
397 	SA5_performant_intr_pending,
398 	SA5_performant_completed,
399 };
400 
401 struct board_type {
402 	u32	board_id;
403 	char	*product_name;
404 	struct access_method *access;
405 };
406 
407 #endif /* HPSA_H */
408 
409