1 /* 2 * Copyright (c) 2016 Linaro Ltd. 3 * Copyright (c) 2016 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 */ 11 12 #include "hisi_sas.h" 13 #define DRV_NAME "hisi_sas_v2_hw" 14 15 /* global registers need init*/ 16 #define DLVRY_QUEUE_ENABLE 0x0 17 #define IOST_BASE_ADDR_LO 0x8 18 #define IOST_BASE_ADDR_HI 0xc 19 #define ITCT_BASE_ADDR_LO 0x10 20 #define ITCT_BASE_ADDR_HI 0x14 21 #define IO_BROKEN_MSG_ADDR_LO 0x18 22 #define IO_BROKEN_MSG_ADDR_HI 0x1c 23 #define PHY_CONTEXT 0x20 24 #define PHY_STATE 0x24 25 #define PHY_PORT_NUM_MA 0x28 26 #define PORT_STATE 0x2c 27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16 28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF) 29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20 30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF) 31 #define PHY_CONN_RATE 0x30 32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38 33 #define AXI_AHB_CLK_CFG 0x3c 34 #define ITCT_CLR 0x44 35 #define ITCT_CLR_EN_OFF 16 36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 37 #define ITCT_DEV_OFF 0 38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 39 #define AXI_USER1 0x48 40 #define AXI_USER2 0x4c 41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 47 #define HGC_GET_ITV_TIME 0x90 48 #define DEVICE_MSG_WORK_MODE 0x94 49 #define OPENA_WT_CONTI_TIME 0x9c 50 #define I_T_NEXUS_LOSS_TIME 0xa0 51 #define MAX_CON_TIME_LIMIT_TIME 0xa4 52 #define BUS_INACTIVE_LIMIT_TIME 0xa8 53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 54 #define CFG_AGING_TIME 0xbc 55 #define HGC_DFX_CFG2 0xc0 56 #define HGC_IOMB_PROC1_STATUS 0x104 57 #define CFG_1US_TIMER_TRSH 0xcc 58 #define HGC_LM_DFX_STATUS2 0x128 59 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0 60 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \ 61 HGC_LM_DFX_STATUS2_IOSTLIST_OFF) 62 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12 63 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \ 64 HGC_LM_DFX_STATUS2_ITCTLIST_OFF) 65 #define HGC_CQE_ECC_ADDR 0x13c 66 #define HGC_CQE_ECC_1B_ADDR_OFF 0 67 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF) 68 #define HGC_CQE_ECC_MB_ADDR_OFF 8 69 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF) 70 #define HGC_IOST_ECC_ADDR 0x140 71 #define HGC_IOST_ECC_1B_ADDR_OFF 0 72 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF) 73 #define HGC_IOST_ECC_MB_ADDR_OFF 16 74 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF) 75 #define HGC_DQE_ECC_ADDR 0x144 76 #define HGC_DQE_ECC_1B_ADDR_OFF 0 77 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF) 78 #define HGC_DQE_ECC_MB_ADDR_OFF 16 79 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF) 80 #define HGC_INVLD_DQE_INFO 0x148 81 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9 82 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF) 83 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18 84 #define HGC_ITCT_ECC_ADDR 0x150 85 #define HGC_ITCT_ECC_1B_ADDR_OFF 0 86 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \ 87 HGC_ITCT_ECC_1B_ADDR_OFF) 88 #define HGC_ITCT_ECC_MB_ADDR_OFF 16 89 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \ 90 HGC_ITCT_ECC_MB_ADDR_OFF) 91 #define HGC_AXI_FIFO_ERR_INFO 0x154 92 #define AXI_ERR_INFO_OFF 0 93 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 94 #define FIFO_ERR_INFO_OFF 8 95 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 96 #define INT_COAL_EN 0x19c 97 #define OQ_INT_COAL_TIME 0x1a0 98 #define OQ_INT_COAL_CNT 0x1a4 99 #define ENT_INT_COAL_TIME 0x1a8 100 #define ENT_INT_COAL_CNT 0x1ac 101 #define OQ_INT_SRC 0x1b0 102 #define OQ_INT_SRC_MSK 0x1b4 103 #define ENT_INT_SRC1 0x1b8 104 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 105 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 106 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 107 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 108 #define ENT_INT_SRC2 0x1bc 109 #define ENT_INT_SRC3 0x1c0 110 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 111 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 112 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 113 #define ENT_INT_SRC3_AXI_OFF 11 114 #define ENT_INT_SRC3_FIFO_OFF 12 115 #define ENT_INT_SRC3_LM_OFF 14 116 #define ENT_INT_SRC3_ITC_INT_OFF 15 117 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 118 #define ENT_INT_SRC3_ABT_OFF 16 119 #define ENT_INT_SRC_MSK1 0x1c4 120 #define ENT_INT_SRC_MSK2 0x1c8 121 #define ENT_INT_SRC_MSK3 0x1cc 122 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 124 #define SAS_ECC_INTR 0x1e8 125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0 126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1 127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2 128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3 129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4 130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5 131 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6 132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7 133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8 134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9 135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10 136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11 137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12 138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13 139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14 140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15 141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16 142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17 143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18 144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19 145 #define SAS_ECC_INTR_MSK 0x1ec 146 #define HGC_ERR_STAT_EN 0x238 147 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 148 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 149 #define DLVRY_Q_0_DEPTH 0x268 150 #define DLVRY_Q_0_WR_PTR 0x26c 151 #define DLVRY_Q_0_RD_PTR 0x270 152 #define HYPER_STREAM_ID_EN_CFG 0xc80 153 #define OQ0_INT_SRC_MSK 0xc90 154 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 155 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 156 #define COMPL_Q_0_DEPTH 0x4e8 157 #define COMPL_Q_0_WR_PTR 0x4ec 158 #define COMPL_Q_0_RD_PTR 0x4f0 159 #define HGC_RXM_DFX_STATUS14 0xae8 160 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0 161 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \ 162 HGC_RXM_DFX_STATUS14_MEM0_OFF) 163 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9 164 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \ 165 HGC_RXM_DFX_STATUS14_MEM1_OFF) 166 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18 167 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \ 168 HGC_RXM_DFX_STATUS14_MEM2_OFF) 169 #define HGC_RXM_DFX_STATUS15 0xaec 170 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0 171 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \ 172 HGC_RXM_DFX_STATUS15_MEM3_OFF) 173 /* phy registers need init */ 174 #define PORT_BASE (0x2000) 175 176 #define PHY_CFG (PORT_BASE + 0x0) 177 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 178 #define PHY_CFG_ENA_OFF 0 179 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 180 #define PHY_CFG_DC_OPT_OFF 2 181 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 182 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 183 #define PROG_PHY_LINK_RATE_MAX_OFF 0 184 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF) 185 #define PHY_CTRL (PORT_BASE + 0x14) 186 #define PHY_CTRL_RESET_OFF 0 187 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 188 #define SAS_PHY_CTRL (PORT_BASE + 0x20) 189 #define SL_CFG (PORT_BASE + 0x84) 190 #define PHY_PCN (PORT_BASE + 0x44) 191 #define SL_TOUT_CFG (PORT_BASE + 0x8c) 192 #define SL_CONTROL (PORT_BASE + 0x94) 193 #define SL_CONTROL_NOTIFY_EN_OFF 0 194 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 195 #define SL_CONTROL_CTA_OFF 17 196 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF) 197 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 198 #define RX_BCAST_CHG_OFF 1 199 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 200 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 201 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 202 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 203 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 204 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 205 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 206 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 207 #define TXID_AUTO (PORT_BASE + 0xb8) 208 #define TXID_AUTO_CT3_OFF 1 209 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF) 210 #define TX_HARDRST_OFF 2 211 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 212 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 213 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) 214 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) 215 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) 216 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) 217 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) 218 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) 219 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 220 #define CON_CONTROL (PORT_BASE + 0x118) 221 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c) 222 #define CHL_INT0 (PORT_BASE + 0x1b4) 223 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 224 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 225 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 226 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 227 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 228 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 229 #define CHL_INT0_NOT_RDY_OFF 4 230 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 231 #define CHL_INT0_PHY_RDY_OFF 5 232 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 233 #define CHL_INT1 (PORT_BASE + 0x1b8) 234 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 235 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 236 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 237 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 238 #define CHL_INT2 (PORT_BASE + 0x1bc) 239 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 240 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 241 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 242 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 243 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 244 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 245 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 246 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 247 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 248 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 249 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 250 #define DMA_TX_STATUS_BUSY_OFF 0 251 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 252 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 253 #define DMA_RX_STATUS_BUSY_OFF 0 254 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 255 256 #define AXI_CFG (0x5100) 257 #define AM_CFG_MAX_TRANS (0x5010) 258 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 259 260 /* HW dma structures */ 261 /* Delivery queue header */ 262 /* dw0 */ 263 #define CMD_HDR_ABORT_FLAG_OFF 0 264 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 265 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 266 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 267 #define CMD_HDR_RESP_REPORT_OFF 5 268 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 269 #define CMD_HDR_TLR_CTRL_OFF 6 270 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 271 #define CMD_HDR_PORT_OFF 18 272 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 273 #define CMD_HDR_PRIORITY_OFF 27 274 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 275 #define CMD_HDR_CMD_OFF 29 276 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 277 /* dw1 */ 278 #define CMD_HDR_DIR_OFF 5 279 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 280 #define CMD_HDR_RESET_OFF 7 281 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 282 #define CMD_HDR_VDTL_OFF 10 283 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 284 #define CMD_HDR_FRAME_TYPE_OFF 11 285 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 286 #define CMD_HDR_DEV_ID_OFF 16 287 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 288 /* dw2 */ 289 #define CMD_HDR_CFL_OFF 0 290 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 291 #define CMD_HDR_NCQ_TAG_OFF 10 292 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 293 #define CMD_HDR_MRFL_OFF 15 294 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 295 #define CMD_HDR_SG_MOD_OFF 24 296 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 297 #define CMD_HDR_FIRST_BURST_OFF 26 298 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF) 299 /* dw3 */ 300 #define CMD_HDR_IPTT_OFF 0 301 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 302 /* dw6 */ 303 #define CMD_HDR_DIF_SGL_LEN_OFF 0 304 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 305 #define CMD_HDR_DATA_SGL_LEN_OFF 16 306 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 307 #define CMD_HDR_ABORT_IPTT_OFF 16 308 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 309 310 /* Completion header */ 311 /* dw0 */ 312 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 313 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 314 #define CMPLT_HDR_ERX_OFF 12 315 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 316 #define CMPLT_HDR_ABORT_STAT_OFF 13 317 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 318 /* abort_stat */ 319 #define STAT_IO_NOT_VALID 0x1 320 #define STAT_IO_NO_DEVICE 0x2 321 #define STAT_IO_COMPLETE 0x3 322 #define STAT_IO_ABORTED 0x4 323 /* dw1 */ 324 #define CMPLT_HDR_IPTT_OFF 0 325 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 326 #define CMPLT_HDR_DEV_ID_OFF 16 327 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 328 329 /* ITCT header */ 330 /* qw0 */ 331 #define ITCT_HDR_DEV_TYPE_OFF 0 332 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 333 #define ITCT_HDR_VALID_OFF 2 334 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 335 #define ITCT_HDR_MCR_OFF 5 336 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 337 #define ITCT_HDR_VLN_OFF 9 338 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 339 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 340 #define ITCT_HDR_SMP_TIMEOUT_8US 1 341 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \ 342 250) /* 2ms */ 343 #define ITCT_HDR_AWT_CONTINUE_OFF 25 344 #define ITCT_HDR_PORT_ID_OFF 28 345 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 346 /* qw2 */ 347 #define ITCT_HDR_INLT_OFF 0 348 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 349 #define ITCT_HDR_BITLT_OFF 16 350 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF) 351 #define ITCT_HDR_MCTLT_OFF 32 352 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF) 353 #define ITCT_HDR_RTOLT_OFF 48 354 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 355 356 #define HISI_SAS_FATAL_INT_NR 2 357 358 struct hisi_sas_complete_v2_hdr { 359 __le32 dw0; 360 __le32 dw1; 361 __le32 act; 362 __le32 dw3; 363 }; 364 365 struct hisi_sas_err_record_v2 { 366 /* dw0 */ 367 __le32 trans_tx_fail_type; 368 369 /* dw1 */ 370 __le32 trans_rx_fail_type; 371 372 /* dw2 */ 373 __le16 dma_tx_err_type; 374 __le16 sipc_rx_err_type; 375 376 /* dw3 */ 377 __le32 dma_rx_err_type; 378 }; 379 380 enum { 381 HISI_SAS_PHY_PHY_UPDOWN, 382 HISI_SAS_PHY_CHNL_INT, 383 HISI_SAS_PHY_INT_NR 384 }; 385 386 enum { 387 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */ 388 TRANS_RX_FAIL_BASE = 0x100, /* dw1 */ 389 DMA_TX_ERR_BASE = 0x200, /* dw2 bit 15-0 */ 390 SIPC_RX_ERR_BASE = 0x300, /* dw2 bit 31-16*/ 391 DMA_RX_ERR_BASE = 0x400, /* dw3 */ 392 393 /* trans tx*/ 394 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */ 395 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */ 396 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */ 397 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */ 398 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */ 399 RESERVED0, /* 0x5 */ 400 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */ 401 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */ 402 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */ 403 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */ 404 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */ 405 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */ 406 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */ 407 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */ 408 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */ 409 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */ 410 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */ 411 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */ 412 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */ 413 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */ 414 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */ 415 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */ 416 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/ 417 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */ 418 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */ 419 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */ 420 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/ 421 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/ 422 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */ 423 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */ 424 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */ 425 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */ 426 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */ 427 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */ 428 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */ 429 430 /* trans rx */ 431 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x100 */ 432 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x101 for sata/stp */ 433 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x102 for ssp/smp */ 434 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */ 435 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x103 for sata/stp */ 436 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x104 for sata/stp */ 437 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x105 for smp */ 438 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */ 439 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x106 for sata/stp*/ 440 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x107 */ 441 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x108 */ 442 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x109 */ 443 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x10a */ 444 RESERVED1, /* 0x10b */ 445 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x10c */ 446 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x10d */ 447 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x10e */ 448 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x10f */ 449 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x110 for ssp/smp */ 450 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x111 for ssp */ 451 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */ 452 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x112 for ssp*/ 453 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */ 454 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x113 for ssp */ 455 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */ 456 RESERVED2, /* 0x114 */ 457 RESERVED3, /* 0x115 */ 458 RESERVED4, /* 0x116 */ 459 RESERVED5, /* 0x117 */ 460 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x118 */ 461 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x119 */ 462 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x11a */ 463 RESERVED6, /* 0x11b */ 464 RESERVED7, /* 0x11c */ 465 RESERVED8, /* 0x11d */ 466 RESERVED9, /* 0x11e */ 467 TRANS_RX_R_ERR, /* 0x11f */ 468 469 /* dma tx */ 470 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x200 */ 471 DMA_TX_DIF_APP_ERR, /* 0x201 */ 472 DMA_TX_DIF_RPP_ERR, /* 0x202 */ 473 DMA_TX_DATA_SGL_OVERFLOW, /* 0x203 */ 474 DMA_TX_DIF_SGL_OVERFLOW, /* 0x204 */ 475 DMA_TX_UNEXP_XFER_ERR, /* 0x205 */ 476 DMA_TX_UNEXP_RETRANS_ERR, /* 0x206 */ 477 DMA_TX_XFER_LEN_OVERFLOW, /* 0x207 */ 478 DMA_TX_XFER_OFFSET_ERR, /* 0x208 */ 479 DMA_TX_RAM_ECC_ERR, /* 0x209 */ 480 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x20a */ 481 482 /* sipc rx */ 483 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x300 */ 484 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x301 */ 485 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x302 */ 486 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x303 */ 487 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x304 */ 488 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x305 */ 489 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x306 */ 490 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x307 */ 491 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x308 */ 492 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x309 */ 493 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x30a */ 494 495 /* dma rx */ 496 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x400 */ 497 DMA_RX_DIF_APP_ERR, /* 0x401 */ 498 DMA_RX_DIF_RPP_ERR, /* 0x402 */ 499 DMA_RX_DATA_SGL_OVERFLOW, /* 0x403 */ 500 DMA_RX_DIF_SGL_OVERFLOW, /* 0x404 */ 501 DMA_RX_DATA_LEN_OVERFLOW, /* 0x405 */ 502 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x406 */ 503 DMA_RX_DATA_OFFSET_ERR, /* 0x407 */ 504 RESERVED10, /* 0x408 */ 505 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x409 */ 506 DMA_RX_RESP_BUF_OVERFLOW, /* 0x40a */ 507 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x40b */ 508 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x40c */ 509 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x40d */ 510 DMA_RX_PIO_DATA_LEN_ERR, /* 0x40e */ 511 DMA_RX_RDSETUP_STATUS_ERR, /* 0x40f */ 512 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x410 */ 513 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x411 */ 514 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x412 */ 515 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x413 */ 516 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x414 */ 517 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x415 */ 518 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x416 */ 519 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x417 */ 520 DMA_RX_RAM_ECC_ERR, /* 0x418 */ 521 DMA_RX_UNKNOWN_FRM_ERR, /* 0x419 */ 522 }; 523 524 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096 525 526 #define DIR_NO_DATA 0 527 #define DIR_TO_INI 1 528 #define DIR_TO_DEVICE 2 529 #define DIR_RESERVED 3 530 531 #define SATA_PROTOCOL_NONDATA 0x1 532 #define SATA_PROTOCOL_PIO 0x2 533 #define SATA_PROTOCOL_DMA 0x4 534 #define SATA_PROTOCOL_FPDMA 0x8 535 #define SATA_PROTOCOL_ATAPI 0x10 536 537 static void hisi_sas_link_timeout_disable_link(unsigned long data); 538 539 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 540 { 541 void __iomem *regs = hisi_hba->regs + off; 542 543 return readl(regs); 544 } 545 546 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 547 { 548 void __iomem *regs = hisi_hba->regs + off; 549 550 return readl_relaxed(regs); 551 } 552 553 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 554 { 555 void __iomem *regs = hisi_hba->regs + off; 556 557 writel(val, regs); 558 } 559 560 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 561 u32 off, u32 val) 562 { 563 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 564 565 writel(val, regs); 566 } 567 568 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 569 int phy_no, u32 off) 570 { 571 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 572 573 return readl(regs); 574 } 575 576 /* This function needs to be protected from pre-emption. */ 577 static int 578 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx, 579 struct domain_device *device) 580 { 581 unsigned int index = 0; 582 void *bitmap = hisi_hba->slot_index_tags; 583 int sata_dev = dev_is_sata(device); 584 585 while (1) { 586 index = find_next_zero_bit(bitmap, hisi_hba->slot_index_count, 587 index); 588 if (index >= hisi_hba->slot_index_count) 589 return -SAS_QUEUE_FULL; 590 /* 591 * SAS IPTT bit0 should be 1 592 */ 593 if (sata_dev || (index & 1)) 594 break; 595 index++; 596 } 597 598 set_bit(index, bitmap); 599 *slot_idx = index; 600 return 0; 601 } 602 603 static struct 604 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device) 605 { 606 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha; 607 struct hisi_sas_device *sas_dev = NULL; 608 int i, sata_dev = dev_is_sata(device); 609 610 spin_lock(&hisi_hba->lock); 611 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) { 612 /* 613 * SATA device id bit0 should be 0 614 */ 615 if (sata_dev && (i & 1)) 616 continue; 617 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) { 618 hisi_hba->devices[i].device_id = i; 619 sas_dev = &hisi_hba->devices[i]; 620 sas_dev->dev_status = HISI_SAS_DEV_NORMAL; 621 sas_dev->dev_type = device->dev_type; 622 sas_dev->hisi_hba = hisi_hba; 623 sas_dev->sas_device = device; 624 break; 625 } 626 } 627 spin_unlock(&hisi_hba->lock); 628 629 return sas_dev; 630 } 631 632 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 633 { 634 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 635 636 cfg &= ~PHY_CFG_DC_OPT_MSK; 637 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 638 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 639 } 640 641 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 642 { 643 struct sas_identify_frame identify_frame; 644 u32 *identify_buffer; 645 646 memset(&identify_frame, 0, sizeof(identify_frame)); 647 identify_frame.dev_type = SAS_END_DEVICE; 648 identify_frame.frame_type = 0; 649 identify_frame._un1 = 1; 650 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 651 identify_frame.target_bits = SAS_PROTOCOL_NONE; 652 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 653 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 654 identify_frame.phy_id = phy_no; 655 identify_buffer = (u32 *)(&identify_frame); 656 657 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 658 __swab32(identify_buffer[0])); 659 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 660 __swab32(identify_buffer[1])); 661 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 662 __swab32(identify_buffer[2])); 663 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 664 __swab32(identify_buffer[3])); 665 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 666 __swab32(identify_buffer[4])); 667 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 668 __swab32(identify_buffer[5])); 669 } 670 671 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba, 672 struct hisi_sas_device *sas_dev) 673 { 674 struct domain_device *device = sas_dev->sas_device; 675 struct device *dev = &hisi_hba->pdev->dev; 676 u64 qw0, device_id = sas_dev->device_id; 677 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 678 struct domain_device *parent_dev = device->parent; 679 struct hisi_sas_port *port = device->port->lldd_port; 680 681 memset(itct, 0, sizeof(*itct)); 682 683 /* qw0 */ 684 qw0 = 0; 685 switch (sas_dev->dev_type) { 686 case SAS_END_DEVICE: 687 case SAS_EDGE_EXPANDER_DEVICE: 688 case SAS_FANOUT_EXPANDER_DEVICE: 689 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 690 break; 691 case SAS_SATA_DEV: 692 case SAS_SATA_PENDING: 693 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 694 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 695 else 696 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 697 break; 698 default: 699 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 700 sas_dev->dev_type); 701 } 702 703 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 704 (device->linkrate << ITCT_HDR_MCR_OFF) | 705 (1 << ITCT_HDR_VLN_OFF) | 706 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) | 707 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 708 (port->id << ITCT_HDR_PORT_ID_OFF)); 709 itct->qw0 = cpu_to_le64(qw0); 710 711 /* qw1 */ 712 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 713 itct->sas_addr = __swab64(itct->sas_addr); 714 715 /* qw2 */ 716 if (!dev_is_sata(device)) 717 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 718 (0x1ULL << ITCT_HDR_BITLT_OFF) | 719 (0x32ULL << ITCT_HDR_MCTLT_OFF) | 720 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 721 } 722 723 static void free_device_v2_hw(struct hisi_hba *hisi_hba, 724 struct hisi_sas_device *sas_dev) 725 { 726 u64 dev_id = sas_dev->device_id; 727 struct device *dev = &hisi_hba->pdev->dev; 728 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 729 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 730 int i; 731 732 /* clear the itct interrupt state */ 733 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 734 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 735 ENT_INT_SRC3_ITC_INT_MSK); 736 737 /* clear the itct int*/ 738 for (i = 0; i < 2; i++) { 739 /* clear the itct table*/ 740 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 741 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 742 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 743 744 udelay(10); 745 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 746 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) { 747 dev_dbg(dev, "got clear ITCT done interrupt\n"); 748 749 /* invalid the itct state*/ 750 memset(itct, 0, sizeof(struct hisi_sas_itct)); 751 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 752 ENT_INT_SRC3_ITC_INT_MSK); 753 754 /* clear the itct */ 755 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 756 dev_dbg(dev, "clear ITCT ok\n"); 757 break; 758 } 759 } 760 } 761 762 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba) 763 { 764 int i, reset_val; 765 u32 val; 766 unsigned long end_time; 767 struct device *dev = &hisi_hba->pdev->dev; 768 769 /* The mask needs to be set depending on the number of phys */ 770 if (hisi_hba->n_phy == 9) 771 reset_val = 0x1fffff; 772 else 773 reset_val = 0x7ffff; 774 775 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 776 777 /* Disable all of the PHYs */ 778 for (i = 0; i < hisi_hba->n_phy; i++) { 779 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG); 780 781 phy_cfg &= ~PHY_CTRL_RESET_MSK; 782 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg); 783 } 784 udelay(50); 785 786 /* Ensure DMA tx & rx idle */ 787 for (i = 0; i < hisi_hba->n_phy; i++) { 788 u32 dma_tx_status, dma_rx_status; 789 790 end_time = jiffies + msecs_to_jiffies(1000); 791 792 while (1) { 793 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i, 794 DMA_TX_STATUS); 795 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i, 796 DMA_RX_STATUS); 797 798 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) && 799 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK)) 800 break; 801 802 msleep(20); 803 if (time_after(jiffies, end_time)) 804 return -EIO; 805 } 806 } 807 808 /* Ensure axi bus idle */ 809 end_time = jiffies + msecs_to_jiffies(1000); 810 while (1) { 811 u32 axi_status = 812 hisi_sas_read32(hisi_hba, AXI_CFG); 813 814 if (axi_status == 0) 815 break; 816 817 msleep(20); 818 if (time_after(jiffies, end_time)) 819 return -EIO; 820 } 821 822 if (ACPI_HANDLE(dev)) { 823 acpi_status s; 824 825 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 826 if (ACPI_FAILURE(s)) { 827 dev_err(dev, "Reset failed\n"); 828 return -EIO; 829 } 830 } else if (hisi_hba->ctrl) { 831 /* reset and disable clock*/ 832 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg, 833 reset_val); 834 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4, 835 reset_val); 836 msleep(1); 837 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 838 if (reset_val != (val & reset_val)) { 839 dev_err(dev, "SAS reset fail.\n"); 840 return -EIO; 841 } 842 843 /* De-reset and enable clock*/ 844 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4, 845 reset_val); 846 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg, 847 reset_val); 848 msleep(1); 849 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, 850 &val); 851 if (val & reset_val) { 852 dev_err(dev, "SAS de-reset fail.\n"); 853 return -EIO; 854 } 855 } else 856 dev_warn(dev, "no reset method\n"); 857 858 return 0; 859 } 860 861 static void init_reg_v2_hw(struct hisi_hba *hisi_hba) 862 { 863 struct device *dev = &hisi_hba->pdev->dev; 864 int i; 865 866 /* Global registers init */ 867 868 /* Deal with am-max-transmissions quirk */ 869 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) { 870 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020); 871 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS, 872 0x2020); 873 } /* Else, use defaults -> do nothing */ 874 875 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 876 (u32)((1ULL << hisi_hba->queue_count) - 1)); 877 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000); 878 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000); 879 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 880 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF); 881 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1); 882 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4); 883 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32); 884 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1); 885 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 886 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1); 887 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1); 888 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 889 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 890 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 891 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1); 892 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1); 893 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0); 894 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 895 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 896 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 897 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe); 898 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe); 899 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe); 900 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30); 901 for (i = 0; i < hisi_hba->queue_count; i++) 902 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 903 904 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1); 905 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 906 907 for (i = 0; i < hisi_hba->n_phy; i++) { 908 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855); 909 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908); 910 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); 911 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0); 912 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2); 913 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10); 914 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 915 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 916 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff); 917 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 918 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 919 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff); 920 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc); 921 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 922 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 923 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 924 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 925 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 926 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0); 927 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0); 928 if (hisi_hba->refclk_frequency_mhz == 66) 929 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694); 930 /* else, do nothing -> leave it how you found it */ 931 } 932 933 for (i = 0; i < hisi_hba->queue_count; i++) { 934 /* Delivery queue */ 935 hisi_sas_write32(hisi_hba, 936 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 937 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 938 939 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 940 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 941 942 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 943 HISI_SAS_QUEUE_SLOTS); 944 945 /* Completion queue */ 946 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 947 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 948 949 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 950 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 951 952 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 953 HISI_SAS_QUEUE_SLOTS); 954 } 955 956 /* itct */ 957 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 958 lower_32_bits(hisi_hba->itct_dma)); 959 960 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 961 upper_32_bits(hisi_hba->itct_dma)); 962 963 /* iost */ 964 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 965 lower_32_bits(hisi_hba->iost_dma)); 966 967 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 968 upper_32_bits(hisi_hba->iost_dma)); 969 970 /* breakpoint */ 971 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 972 lower_32_bits(hisi_hba->breakpoint_dma)); 973 974 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 975 upper_32_bits(hisi_hba->breakpoint_dma)); 976 977 /* SATA broken msg */ 978 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 979 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 980 981 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 982 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 983 984 /* SATA initial fis */ 985 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 986 lower_32_bits(hisi_hba->initial_fis_dma)); 987 988 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 989 upper_32_bits(hisi_hba->initial_fis_dma)); 990 } 991 992 static void hisi_sas_link_timeout_enable_link(unsigned long data) 993 { 994 struct hisi_hba *hisi_hba = (struct hisi_hba *)data; 995 int i, reg_val; 996 997 for (i = 0; i < hisi_hba->n_phy; i++) { 998 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL); 999 if (!(reg_val & BIT(0))) { 1000 hisi_sas_phy_write32(hisi_hba, i, 1001 CON_CONTROL, 0x7); 1002 break; 1003 } 1004 } 1005 1006 hisi_hba->timer.function = hisi_sas_link_timeout_disable_link; 1007 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900)); 1008 } 1009 1010 static void hisi_sas_link_timeout_disable_link(unsigned long data) 1011 { 1012 struct hisi_hba *hisi_hba = (struct hisi_hba *)data; 1013 int i, reg_val; 1014 1015 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE); 1016 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) { 1017 if (reg_val & BIT(i)) { 1018 hisi_sas_phy_write32(hisi_hba, i, 1019 CON_CONTROL, 0x6); 1020 break; 1021 } 1022 } 1023 1024 hisi_hba->timer.function = hisi_sas_link_timeout_enable_link; 1025 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100)); 1026 } 1027 1028 static void set_link_timer_quirk(struct hisi_hba *hisi_hba) 1029 { 1030 hisi_hba->timer.data = (unsigned long)hisi_hba; 1031 hisi_hba->timer.function = hisi_sas_link_timeout_disable_link; 1032 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000); 1033 add_timer(&hisi_hba->timer); 1034 } 1035 1036 static int hw_init_v2_hw(struct hisi_hba *hisi_hba) 1037 { 1038 struct device *dev = &hisi_hba->pdev->dev; 1039 int rc; 1040 1041 rc = reset_hw_v2_hw(hisi_hba); 1042 if (rc) { 1043 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 1044 return rc; 1045 } 1046 1047 msleep(100); 1048 init_reg_v2_hw(hisi_hba); 1049 1050 return 0; 1051 } 1052 1053 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1054 { 1055 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 1056 1057 cfg |= PHY_CFG_ENA_MSK; 1058 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 1059 } 1060 1061 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1062 { 1063 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 1064 1065 cfg &= ~PHY_CFG_ENA_MSK; 1066 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 1067 } 1068 1069 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1070 { 1071 config_id_frame_v2_hw(hisi_hba, phy_no); 1072 config_phy_opt_mode_v2_hw(hisi_hba, phy_no); 1073 enable_phy_v2_hw(hisi_hba, phy_no); 1074 } 1075 1076 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1077 { 1078 disable_phy_v2_hw(hisi_hba, phy_no); 1079 } 1080 1081 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1082 { 1083 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1084 u32 txid_auto; 1085 1086 stop_phy_v2_hw(hisi_hba, phy_no); 1087 if (phy->identify.device_type == SAS_END_DEVICE) { 1088 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1089 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1090 txid_auto | TX_HARDRST_MSK); 1091 } 1092 msleep(100); 1093 start_phy_v2_hw(hisi_hba, phy_no); 1094 } 1095 1096 static void start_phys_v2_hw(struct hisi_hba *hisi_hba) 1097 { 1098 int i; 1099 1100 for (i = 0; i < hisi_hba->n_phy; i++) 1101 start_phy_v2_hw(hisi_hba, i); 1102 } 1103 1104 static void phys_init_v2_hw(struct hisi_hba *hisi_hba) 1105 { 1106 start_phys_v2_hw(hisi_hba); 1107 } 1108 1109 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 1110 { 1111 u32 sl_control; 1112 1113 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1114 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 1115 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 1116 msleep(1); 1117 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1118 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 1119 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 1120 } 1121 1122 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void) 1123 { 1124 return SAS_LINK_RATE_12_0_GBPS; 1125 } 1126 1127 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no, 1128 struct sas_phy_linkrates *r) 1129 { 1130 u32 prog_phy_link_rate = 1131 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE); 1132 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1133 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1134 int i; 1135 enum sas_linkrate min, max; 1136 u32 rate_mask = 0; 1137 1138 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) { 1139 max = sas_phy->phy->maximum_linkrate; 1140 min = r->minimum_linkrate; 1141 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) { 1142 max = r->maximum_linkrate; 1143 min = sas_phy->phy->minimum_linkrate; 1144 } else 1145 return; 1146 1147 sas_phy->phy->maximum_linkrate = max; 1148 sas_phy->phy->minimum_linkrate = min; 1149 1150 min -= SAS_LINK_RATE_1_5_GBPS; 1151 max -= SAS_LINK_RATE_1_5_GBPS; 1152 1153 for (i = 0; i <= max; i++) 1154 rate_mask |= 1 << (i * 2); 1155 1156 prog_phy_link_rate &= ~0xff; 1157 prog_phy_link_rate |= rate_mask; 1158 1159 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 1160 prog_phy_link_rate); 1161 1162 phy_hard_reset_v2_hw(hisi_hba, phy_no); 1163 } 1164 1165 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id) 1166 { 1167 int i, bitmap = 0; 1168 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1169 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1170 1171 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++) 1172 if (phy_state & 1 << i) 1173 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 1174 bitmap |= 1 << i; 1175 1176 if (hisi_hba->n_phy == 9) { 1177 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 1178 1179 if (phy_state & 1 << 8) 1180 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 1181 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id) 1182 bitmap |= 1 << 9; 1183 } 1184 1185 return bitmap; 1186 } 1187 1188 /** 1189 * This function allocates across all queues to load balance. 1190 * Slots are allocated from queues in a round-robin fashion. 1191 * 1192 * The callpath to this function and upto writing the write 1193 * queue pointer should be safe from interruption. 1194 */ 1195 static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, u32 dev_id, 1196 int *q, int *s) 1197 { 1198 struct device *dev = &hisi_hba->pdev->dev; 1199 struct hisi_sas_dq *dq; 1200 u32 r, w; 1201 int queue = dev_id % hisi_hba->queue_count; 1202 1203 dq = &hisi_hba->dq[queue]; 1204 w = dq->wr_point; 1205 r = hisi_sas_read32_relaxed(hisi_hba, 1206 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 1207 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 1208 dev_warn(dev, "full queue=%d r=%d w=%d\n\n", 1209 queue, r, w); 1210 return -EAGAIN; 1211 } 1212 1213 *q = queue; 1214 *s = w; 1215 return 0; 1216 } 1217 1218 static void start_delivery_v2_hw(struct hisi_hba *hisi_hba) 1219 { 1220 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue; 1221 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot; 1222 struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue]; 1223 1224 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; 1225 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), 1226 dq->wr_point); 1227 } 1228 1229 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba, 1230 struct hisi_sas_slot *slot, 1231 struct hisi_sas_cmd_hdr *hdr, 1232 struct scatterlist *scatter, 1233 int n_elem) 1234 { 1235 struct device *dev = &hisi_hba->pdev->dev; 1236 struct scatterlist *sg; 1237 int i; 1238 1239 if (n_elem > HISI_SAS_SGE_PAGE_CNT) { 1240 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT", 1241 n_elem); 1242 return -EINVAL; 1243 } 1244 1245 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC, 1246 &slot->sge_page_dma); 1247 if (!slot->sge_page) 1248 return -ENOMEM; 1249 1250 for_each_sg(scatter, sg, n_elem, i) { 1251 struct hisi_sas_sge *entry = &slot->sge_page->sge[i]; 1252 1253 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1254 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 1255 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1256 entry->data_off = 0; 1257 } 1258 1259 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma); 1260 1261 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 1262 1263 return 0; 1264 } 1265 1266 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba, 1267 struct hisi_sas_slot *slot) 1268 { 1269 struct sas_task *task = slot->task; 1270 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1271 struct domain_device *device = task->dev; 1272 struct device *dev = &hisi_hba->pdev->dev; 1273 struct hisi_sas_port *port = slot->port; 1274 struct scatterlist *sg_req, *sg_resp; 1275 struct hisi_sas_device *sas_dev = device->lldd_dev; 1276 dma_addr_t req_dma_addr; 1277 unsigned int req_len, resp_len; 1278 int elem, rc; 1279 1280 /* 1281 * DMA-map SMP request, response buffers 1282 */ 1283 /* req */ 1284 sg_req = &task->smp_task.smp_req; 1285 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE); 1286 if (!elem) 1287 return -ENOMEM; 1288 req_len = sg_dma_len(sg_req); 1289 req_dma_addr = sg_dma_address(sg_req); 1290 1291 /* resp */ 1292 sg_resp = &task->smp_task.smp_resp; 1293 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE); 1294 if (!elem) { 1295 rc = -ENOMEM; 1296 goto err_out_req; 1297 } 1298 resp_len = sg_dma_len(sg_resp); 1299 if ((req_len & 0x3) || (resp_len & 0x3)) { 1300 rc = -EINVAL; 1301 goto err_out_resp; 1302 } 1303 1304 /* create header */ 1305 /* dw0 */ 1306 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1307 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1308 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1309 1310 /* map itct entry */ 1311 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1312 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1313 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1314 1315 /* dw2 */ 1316 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1317 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1318 CMD_HDR_MRFL_OFF)); 1319 1320 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1321 1322 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1323 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1324 1325 return 0; 1326 1327 err_out_resp: 1328 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1, 1329 DMA_FROM_DEVICE); 1330 err_out_req: 1331 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1, 1332 DMA_TO_DEVICE); 1333 return rc; 1334 } 1335 1336 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba, 1337 struct hisi_sas_slot *slot, int is_tmf, 1338 struct hisi_sas_tmf_task *tmf) 1339 { 1340 struct sas_task *task = slot->task; 1341 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1342 struct domain_device *device = task->dev; 1343 struct hisi_sas_device *sas_dev = device->lldd_dev; 1344 struct hisi_sas_port *port = slot->port; 1345 struct sas_ssp_task *ssp_task = &task->ssp_task; 1346 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1347 int has_data = 0, rc, priority = is_tmf; 1348 u8 *buf_cmd; 1349 u32 dw1 = 0, dw2 = 0; 1350 1351 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1352 (2 << CMD_HDR_TLR_CTRL_OFF) | 1353 (port->id << CMD_HDR_PORT_OFF) | 1354 (priority << CMD_HDR_PRIORITY_OFF) | 1355 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1356 1357 dw1 = 1 << CMD_HDR_VDTL_OFF; 1358 if (is_tmf) { 1359 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1360 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1361 } else { 1362 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1363 switch (scsi_cmnd->sc_data_direction) { 1364 case DMA_TO_DEVICE: 1365 has_data = 1; 1366 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1367 break; 1368 case DMA_FROM_DEVICE: 1369 has_data = 1; 1370 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1371 break; 1372 default: 1373 dw1 &= ~CMD_HDR_DIR_MSK; 1374 } 1375 } 1376 1377 /* map itct entry */ 1378 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1379 hdr->dw1 = cpu_to_le32(dw1); 1380 1381 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1382 + 3) / 4) << CMD_HDR_CFL_OFF) | 1383 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1384 (2 << CMD_HDR_SG_MOD_OFF); 1385 hdr->dw2 = cpu_to_le32(dw2); 1386 1387 hdr->transfer_tags = cpu_to_le32(slot->idx); 1388 1389 if (has_data) { 1390 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter, 1391 slot->n_elem); 1392 if (rc) 1393 return rc; 1394 } 1395 1396 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1397 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); 1398 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1399 1400 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr); 1401 1402 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1403 if (!is_tmf) { 1404 buf_cmd[9] = task->ssp_task.task_attr | 1405 (task->ssp_task.task_prio << 3); 1406 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd, 1407 task->ssp_task.cmd->cmd_len); 1408 } else { 1409 buf_cmd[10] = tmf->tmf; 1410 switch (tmf->tmf) { 1411 case TMF_ABORT_TASK: 1412 case TMF_QUERY_TASK: 1413 buf_cmd[12] = 1414 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1415 buf_cmd[13] = 1416 tmf->tag_of_task_to_be_managed & 0xff; 1417 break; 1418 default: 1419 break; 1420 } 1421 } 1422 1423 return 0; 1424 } 1425 1426 static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1427 struct hisi_sas_slot *slot) 1428 { 1429 struct task_status_struct *ts = &task->task_status; 1430 struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf; 1431 struct dev_to_host_fis *d2h = slot->status_buffer + 1432 sizeof(struct hisi_sas_err_record); 1433 1434 resp->frame_len = sizeof(struct dev_to_host_fis); 1435 memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis)); 1436 1437 ts->buf_valid_size = sizeof(*resp); 1438 } 1439 1440 /* by default, task resp is complete */ 1441 static void slot_err_v2_hw(struct hisi_hba *hisi_hba, 1442 struct sas_task *task, 1443 struct hisi_sas_slot *slot) 1444 { 1445 struct task_status_struct *ts = &task->task_status; 1446 struct hisi_sas_err_record_v2 *err_record = slot->status_buffer; 1447 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type); 1448 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type); 1449 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type); 1450 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type); 1451 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type); 1452 int error = -1; 1453 1454 if (dma_rx_err_type) { 1455 error = ffs(dma_rx_err_type) 1456 - 1 + DMA_RX_ERR_BASE; 1457 } else if (sipc_rx_err_type) { 1458 error = ffs(sipc_rx_err_type) 1459 - 1 + SIPC_RX_ERR_BASE; 1460 } else if (dma_tx_err_type) { 1461 error = ffs(dma_tx_err_type) 1462 - 1 + DMA_TX_ERR_BASE; 1463 } else if (trans_rx_fail_type) { 1464 error = ffs(trans_rx_fail_type) 1465 - 1 + TRANS_RX_FAIL_BASE; 1466 } else if (trans_tx_fail_type) { 1467 error = ffs(trans_tx_fail_type) 1468 - 1 + TRANS_TX_FAIL_BASE; 1469 } 1470 1471 switch (task->task_proto) { 1472 case SAS_PROTOCOL_SSP: 1473 { 1474 switch (error) { 1475 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION: 1476 { 1477 ts->stat = SAS_OPEN_REJECT; 1478 ts->open_rej_reason = SAS_OREJ_NO_DEST; 1479 break; 1480 } 1481 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED: 1482 { 1483 ts->stat = SAS_OPEN_REJECT; 1484 ts->open_rej_reason = SAS_OREJ_PATH_BLOCKED; 1485 break; 1486 } 1487 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED: 1488 { 1489 ts->stat = SAS_OPEN_REJECT; 1490 ts->open_rej_reason = SAS_OREJ_EPROTO; 1491 break; 1492 } 1493 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED: 1494 { 1495 ts->stat = SAS_OPEN_REJECT; 1496 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1497 break; 1498 } 1499 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION: 1500 { 1501 ts->stat = SAS_OPEN_REJECT; 1502 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1503 break; 1504 } 1505 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD: 1506 { 1507 ts->stat = SAS_OPEN_REJECT; 1508 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1509 break; 1510 } 1511 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION: 1512 { 1513 ts->stat = SAS_OPEN_REJECT; 1514 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1515 break; 1516 } 1517 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION: 1518 { 1519 ts->stat = SAS_OPEN_REJECT; 1520 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1521 break; 1522 } 1523 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER: 1524 { 1525 /* not sure */ 1526 ts->stat = SAS_DEV_NO_RESPONSE; 1527 break; 1528 } 1529 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE: 1530 { 1531 ts->stat = SAS_PHY_DOWN; 1532 break; 1533 } 1534 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT: 1535 { 1536 ts->stat = SAS_OPEN_TO; 1537 break; 1538 } 1539 case DMA_RX_DATA_LEN_OVERFLOW: 1540 { 1541 ts->stat = SAS_DATA_OVERRUN; 1542 ts->residual = 0; 1543 break; 1544 } 1545 case DMA_RX_DATA_LEN_UNDERFLOW: 1546 case SIPC_RX_DATA_UNDERFLOW_ERR: 1547 { 1548 ts->residual = trans_tx_fail_type; 1549 ts->stat = SAS_DATA_UNDERRUN; 1550 break; 1551 } 1552 case TRANS_TX_ERR_FRAME_TXED: 1553 { 1554 /* This will request a retry */ 1555 ts->stat = SAS_QUEUE_FULL; 1556 slot->abort = 1; 1557 break; 1558 } 1559 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS: 1560 case TRANS_TX_ERR_PHY_NOT_ENABLE: 1561 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER: 1562 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT: 1563 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED: 1564 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT: 1565 case TRANS_TX_ERR_WITH_BREAK_REQUEST: 1566 case TRANS_TX_ERR_WITH_BREAK_RECEVIED: 1567 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT: 1568 case TRANS_TX_ERR_WITH_CLOSE_NORMAL: 1569 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1570 case TRANS_TX_ERR_WITH_CLOSE_COMINIT: 1571 case TRANS_TX_ERR_WITH_NAK_RECEVIED: 1572 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT: 1573 case TRANS_TX_ERR_WITH_IPTT_CONFLICT: 1574 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT: 1575 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR: 1576 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR: 1577 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM: 1578 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT: 1579 case TRANS_RX_ERR_WITH_BREAK_REQUEST: 1580 case TRANS_RX_ERR_WITH_BREAK_RECEVIED: 1581 case TRANS_RX_ERR_WITH_CLOSE_NORMAL: 1582 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1583 case TRANS_RX_ERR_WITH_CLOSE_COMINIT: 1584 case TRANS_RX_ERR_WITH_DATA_LEN0: 1585 case TRANS_RX_ERR_WITH_BAD_HASH: 1586 case TRANS_RX_XRDY_WLEN_ZERO_ERR: 1587 case TRANS_RX_SSP_FRM_LEN_ERR: 1588 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE: 1589 case DMA_TX_UNEXP_XFER_ERR: 1590 case DMA_TX_UNEXP_RETRANS_ERR: 1591 case DMA_TX_XFER_LEN_OVERFLOW: 1592 case DMA_TX_XFER_OFFSET_ERR: 1593 case DMA_RX_DATA_OFFSET_ERR: 1594 case DMA_RX_UNEXP_NORM_RESP_ERR: 1595 case DMA_RX_UNEXP_RDFRAME_ERR: 1596 case DMA_RX_UNKNOWN_FRM_ERR: 1597 { 1598 ts->stat = SAS_OPEN_REJECT; 1599 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1600 break; 1601 } 1602 default: 1603 break; 1604 } 1605 } 1606 break; 1607 case SAS_PROTOCOL_SMP: 1608 ts->stat = SAM_STAT_CHECK_CONDITION; 1609 break; 1610 1611 case SAS_PROTOCOL_SATA: 1612 case SAS_PROTOCOL_STP: 1613 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1614 { 1615 switch (error) { 1616 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER: 1617 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED: 1618 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION: 1619 { 1620 ts->resp = SAS_TASK_UNDELIVERED; 1621 ts->stat = SAS_DEV_NO_RESPONSE; 1622 break; 1623 } 1624 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED: 1625 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED: 1626 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION: 1627 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD: 1628 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION: 1629 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION: 1630 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY: 1631 { 1632 ts->stat = SAS_OPEN_REJECT; 1633 break; 1634 } 1635 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT: 1636 { 1637 ts->stat = SAS_OPEN_TO; 1638 break; 1639 } 1640 case DMA_RX_DATA_LEN_OVERFLOW: 1641 { 1642 ts->stat = SAS_DATA_OVERRUN; 1643 break; 1644 } 1645 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS: 1646 case TRANS_TX_ERR_PHY_NOT_ENABLE: 1647 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER: 1648 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT: 1649 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED: 1650 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT: 1651 case TRANS_TX_ERR_WITH_BREAK_REQUEST: 1652 case TRANS_TX_ERR_WITH_BREAK_RECEVIED: 1653 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT: 1654 case TRANS_TX_ERR_WITH_CLOSE_NORMAL: 1655 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1656 case TRANS_TX_ERR_WITH_CLOSE_COMINIT: 1657 case TRANS_TX_ERR_WITH_NAK_RECEVIED: 1658 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT: 1659 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT: 1660 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT: 1661 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR: 1662 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM: 1663 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR: 1664 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR: 1665 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN: 1666 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP: 1667 case TRANS_RX_ERR_WITH_CLOSE_NORMAL: 1668 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE: 1669 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1670 case TRANS_RX_ERR_WITH_CLOSE_COMINIT: 1671 case TRANS_RX_ERR_WITH_DATA_LEN0: 1672 case TRANS_RX_ERR_WITH_BAD_HASH: 1673 case TRANS_RX_XRDY_WLEN_ZERO_ERR: 1674 case TRANS_RX_SSP_FRM_LEN_ERR: 1675 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD: 1676 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR: 1677 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR: 1678 case SIPC_RX_WRSETUP_LEN_ODD_ERR: 1679 case SIPC_RX_WRSETUP_LEN_ZERO_ERR: 1680 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR: 1681 case SIPC_RX_SATA_UNEXP_FIS_ERR: 1682 case DMA_RX_SATA_FRAME_TYPE_ERR: 1683 case DMA_RX_UNEXP_RDFRAME_ERR: 1684 case DMA_RX_PIO_DATA_LEN_ERR: 1685 case DMA_RX_RDSETUP_STATUS_ERR: 1686 case DMA_RX_RDSETUP_STATUS_DRQ_ERR: 1687 case DMA_RX_RDSETUP_STATUS_BSY_ERR: 1688 case DMA_RX_RDSETUP_LEN_ODD_ERR: 1689 case DMA_RX_RDSETUP_LEN_ZERO_ERR: 1690 case DMA_RX_RDSETUP_LEN_OVER_ERR: 1691 case DMA_RX_RDSETUP_OFFSET_ERR: 1692 case DMA_RX_RDSETUP_ACTIVE_ERR: 1693 case DMA_RX_RDSETUP_ESTATUS_ERR: 1694 case DMA_RX_UNKNOWN_FRM_ERR: 1695 { 1696 ts->stat = SAS_OPEN_REJECT; 1697 break; 1698 } 1699 default: 1700 { 1701 ts->stat = SAS_PROTO_RESPONSE; 1702 break; 1703 } 1704 } 1705 sata_done_v2_hw(hisi_hba, task, slot); 1706 } 1707 break; 1708 default: 1709 break; 1710 } 1711 } 1712 1713 static int 1714 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot, 1715 int abort) 1716 { 1717 struct sas_task *task = slot->task; 1718 struct hisi_sas_device *sas_dev; 1719 struct device *dev = &hisi_hba->pdev->dev; 1720 struct task_status_struct *ts; 1721 struct domain_device *device; 1722 enum exec_status sts; 1723 struct hisi_sas_complete_v2_hdr *complete_queue = 1724 hisi_hba->complete_hdr[slot->cmplt_queue]; 1725 struct hisi_sas_complete_v2_hdr *complete_hdr = 1726 &complete_queue[slot->cmplt_queue_slot]; 1727 1728 if (unlikely(!task || !task->lldd_task || !task->dev)) 1729 return -EINVAL; 1730 1731 ts = &task->task_status; 1732 device = task->dev; 1733 sas_dev = device->lldd_dev; 1734 1735 task->task_state_flags &= 1736 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1737 task->task_state_flags |= SAS_TASK_STATE_DONE; 1738 1739 memset(ts, 0, sizeof(*ts)); 1740 ts->resp = SAS_TASK_COMPLETE; 1741 1742 if (unlikely(!sas_dev || abort)) { 1743 if (!sas_dev) 1744 dev_dbg(dev, "slot complete: port has not device\n"); 1745 ts->stat = SAS_PHY_DOWN; 1746 goto out; 1747 } 1748 1749 /* Use SAS+TMF status codes */ 1750 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) 1751 >> CMPLT_HDR_ABORT_STAT_OFF) { 1752 case STAT_IO_ABORTED: 1753 /* this io has been aborted by abort command */ 1754 ts->stat = SAS_ABORTED_TASK; 1755 goto out; 1756 case STAT_IO_COMPLETE: 1757 /* internal abort command complete */ 1758 ts->stat = TMF_RESP_FUNC_COMPLETE; 1759 goto out; 1760 case STAT_IO_NO_DEVICE: 1761 ts->stat = TMF_RESP_FUNC_COMPLETE; 1762 goto out; 1763 case STAT_IO_NOT_VALID: 1764 /* abort single io, controller don't find 1765 * the io need to abort 1766 */ 1767 ts->stat = TMF_RESP_FUNC_FAILED; 1768 goto out; 1769 default: 1770 break; 1771 } 1772 1773 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) && 1774 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) { 1775 1776 slot_err_v2_hw(hisi_hba, task, slot); 1777 if (unlikely(slot->abort)) { 1778 queue_work(hisi_hba->wq, &slot->abort_slot); 1779 /* immediately return and do not complete */ 1780 return ts->stat; 1781 } 1782 goto out; 1783 } 1784 1785 switch (task->task_proto) { 1786 case SAS_PROTOCOL_SSP: 1787 { 1788 struct ssp_response_iu *iu = slot->status_buffer + 1789 sizeof(struct hisi_sas_err_record); 1790 1791 sas_ssp_task_response(dev, task, iu); 1792 break; 1793 } 1794 case SAS_PROTOCOL_SMP: 1795 { 1796 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1797 void *to; 1798 1799 ts->stat = SAM_STAT_GOOD; 1800 to = kmap_atomic(sg_page(sg_resp)); 1801 1802 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1803 DMA_FROM_DEVICE); 1804 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1805 DMA_TO_DEVICE); 1806 memcpy(to + sg_resp->offset, 1807 slot->status_buffer + 1808 sizeof(struct hisi_sas_err_record), 1809 sg_dma_len(sg_resp)); 1810 kunmap_atomic(to); 1811 break; 1812 } 1813 case SAS_PROTOCOL_SATA: 1814 case SAS_PROTOCOL_STP: 1815 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1816 { 1817 ts->stat = SAM_STAT_GOOD; 1818 sata_done_v2_hw(hisi_hba, task, slot); 1819 break; 1820 } 1821 default: 1822 ts->stat = SAM_STAT_CHECK_CONDITION; 1823 break; 1824 } 1825 1826 if (!slot->port->port_attached) { 1827 dev_err(dev, "slot complete: port %d has removed\n", 1828 slot->port->sas_port.id); 1829 ts->stat = SAS_PHY_DOWN; 1830 } 1831 1832 out: 1833 1834 hisi_sas_slot_task_free(hisi_hba, task, slot); 1835 sts = ts->stat; 1836 1837 if (task->task_done) 1838 task->task_done(task); 1839 1840 return sts; 1841 } 1842 1843 static u8 get_ata_protocol(u8 cmd, int direction) 1844 { 1845 switch (cmd) { 1846 case ATA_CMD_FPDMA_WRITE: 1847 case ATA_CMD_FPDMA_READ: 1848 case ATA_CMD_FPDMA_RECV: 1849 case ATA_CMD_FPDMA_SEND: 1850 case ATA_CMD_NCQ_NON_DATA: 1851 return SATA_PROTOCOL_FPDMA; 1852 1853 case ATA_CMD_DOWNLOAD_MICRO: 1854 case ATA_CMD_ID_ATA: 1855 case ATA_CMD_PMP_READ: 1856 case ATA_CMD_READ_LOG_EXT: 1857 case ATA_CMD_PIO_READ: 1858 case ATA_CMD_PIO_READ_EXT: 1859 case ATA_CMD_PMP_WRITE: 1860 case ATA_CMD_WRITE_LOG_EXT: 1861 case ATA_CMD_PIO_WRITE: 1862 case ATA_CMD_PIO_WRITE_EXT: 1863 return SATA_PROTOCOL_PIO; 1864 1865 case ATA_CMD_DSM: 1866 case ATA_CMD_DOWNLOAD_MICRO_DMA: 1867 case ATA_CMD_PMP_READ_DMA: 1868 case ATA_CMD_PMP_WRITE_DMA: 1869 case ATA_CMD_READ: 1870 case ATA_CMD_READ_EXT: 1871 case ATA_CMD_READ_LOG_DMA_EXT: 1872 case ATA_CMD_READ_STREAM_DMA_EXT: 1873 case ATA_CMD_TRUSTED_RCV_DMA: 1874 case ATA_CMD_TRUSTED_SND_DMA: 1875 case ATA_CMD_WRITE: 1876 case ATA_CMD_WRITE_EXT: 1877 case ATA_CMD_WRITE_FUA_EXT: 1878 case ATA_CMD_WRITE_QUEUED: 1879 case ATA_CMD_WRITE_LOG_DMA_EXT: 1880 case ATA_CMD_WRITE_STREAM_DMA_EXT: 1881 return SATA_PROTOCOL_DMA; 1882 1883 case ATA_CMD_CHK_POWER: 1884 case ATA_CMD_DEV_RESET: 1885 case ATA_CMD_EDD: 1886 case ATA_CMD_FLUSH: 1887 case ATA_CMD_FLUSH_EXT: 1888 case ATA_CMD_VERIFY: 1889 case ATA_CMD_VERIFY_EXT: 1890 case ATA_CMD_SET_FEATURES: 1891 case ATA_CMD_STANDBY: 1892 case ATA_CMD_STANDBYNOW1: 1893 return SATA_PROTOCOL_NONDATA; 1894 default: 1895 if (direction == DMA_NONE) 1896 return SATA_PROTOCOL_NONDATA; 1897 return SATA_PROTOCOL_PIO; 1898 } 1899 } 1900 1901 static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag) 1902 { 1903 struct ata_queued_cmd *qc = task->uldd_task; 1904 1905 if (qc) { 1906 if (qc->tf.command == ATA_CMD_FPDMA_WRITE || 1907 qc->tf.command == ATA_CMD_FPDMA_READ) { 1908 *tag = qc->tag; 1909 return 1; 1910 } 1911 } 1912 return 0; 1913 } 1914 1915 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba, 1916 struct hisi_sas_slot *slot) 1917 { 1918 struct sas_task *task = slot->task; 1919 struct domain_device *device = task->dev; 1920 struct domain_device *parent_dev = device->parent; 1921 struct hisi_sas_device *sas_dev = device->lldd_dev; 1922 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1923 struct hisi_sas_port *port = device->port->lldd_port; 1924 u8 *buf_cmd; 1925 int has_data = 0, rc = 0, hdr_tag = 0; 1926 u32 dw1 = 0, dw2 = 0; 1927 1928 /* create header */ 1929 /* dw0 */ 1930 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1931 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1932 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1933 else 1934 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1935 1936 /* dw1 */ 1937 switch (task->data_dir) { 1938 case DMA_TO_DEVICE: 1939 has_data = 1; 1940 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1941 break; 1942 case DMA_FROM_DEVICE: 1943 has_data = 1; 1944 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1945 break; 1946 default: 1947 dw1 &= ~CMD_HDR_DIR_MSK; 1948 } 1949 1950 if (0 == task->ata_task.fis.command) 1951 dw1 |= 1 << CMD_HDR_RESET_OFF; 1952 1953 dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir)) 1954 << CMD_HDR_FRAME_TYPE_OFF; 1955 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1956 hdr->dw1 = cpu_to_le32(dw1); 1957 1958 /* dw2 */ 1959 if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) { 1960 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1961 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1962 } 1963 1964 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1965 2 << CMD_HDR_SG_MOD_OFF; 1966 hdr->dw2 = cpu_to_le32(dw2); 1967 1968 /* dw3 */ 1969 hdr->transfer_tags = cpu_to_le32(slot->idx); 1970 1971 if (has_data) { 1972 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter, 1973 slot->n_elem); 1974 if (rc) 1975 return rc; 1976 } 1977 1978 1979 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1980 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); 1981 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1982 1983 buf_cmd = slot->command_table; 1984 1985 if (likely(!task->ata_task.device_control_reg_update)) 1986 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1987 /* fill in command FIS */ 1988 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1989 1990 return 0; 1991 } 1992 1993 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba, 1994 struct hisi_sas_slot *slot, 1995 int device_id, int abort_flag, int tag_to_abort) 1996 { 1997 struct sas_task *task = slot->task; 1998 struct domain_device *dev = task->dev; 1999 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 2000 struct hisi_sas_port *port = slot->port; 2001 2002 /* dw0 */ 2003 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 2004 (port->id << CMD_HDR_PORT_OFF) | 2005 ((dev_is_sata(dev) ? 1:0) << 2006 CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 2007 (abort_flag << CMD_HDR_ABORT_FLAG_OFF)); 2008 2009 /* dw1 */ 2010 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF); 2011 2012 /* dw7 */ 2013 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 2014 hdr->transfer_tags = cpu_to_le32(slot->idx); 2015 2016 return 0; 2017 } 2018 2019 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 2020 { 2021 int i, res = 0; 2022 u32 context, port_id, link_rate, hard_phy_linkrate; 2023 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2024 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2025 struct device *dev = &hisi_hba->pdev->dev; 2026 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 2027 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; 2028 2029 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 2030 2031 /* Check for SATA dev */ 2032 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 2033 if (context & (1 << phy_no)) 2034 goto end; 2035 2036 if (phy_no == 8) { 2037 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 2038 2039 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 2040 PORT_STATE_PHY8_PORT_NUM_OFF; 2041 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> 2042 PORT_STATE_PHY8_CONN_RATE_OFF; 2043 } else { 2044 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 2045 port_id = (port_id >> (4 * phy_no)) & 0xf; 2046 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 2047 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 2048 } 2049 2050 if (port_id == 0xf) { 2051 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 2052 res = IRQ_NONE; 2053 goto end; 2054 } 2055 2056 for (i = 0; i < 6; i++) { 2057 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 2058 RX_IDAF_DWORD0 + (i * 4)); 2059 frame_rcvd[i] = __swab32(idaf); 2060 } 2061 2062 sas_phy->linkrate = link_rate; 2063 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, 2064 HARD_PHY_LINKRATE); 2065 phy->maximum_linkrate = hard_phy_linkrate & 0xf; 2066 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; 2067 2068 sas_phy->oob_mode = SAS_OOB_MODE; 2069 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE); 2070 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 2071 phy->port_id = port_id; 2072 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 2073 phy->phy_type |= PORT_TYPE_SAS; 2074 phy->phy_attached = 1; 2075 phy->identify.device_type = id->dev_type; 2076 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 2077 if (phy->identify.device_type == SAS_END_DEVICE) 2078 phy->identify.target_port_protocols = 2079 SAS_PROTOCOL_SSP; 2080 else if (phy->identify.device_type != SAS_PHY_UNUSED) { 2081 phy->identify.target_port_protocols = 2082 SAS_PROTOCOL_SMP; 2083 if (!timer_pending(&hisi_hba->timer)) 2084 set_link_timer_quirk(hisi_hba); 2085 } 2086 queue_work(hisi_hba->wq, &phy->phyup_ws); 2087 2088 end: 2089 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 2090 CHL_INT0_SL_PHY_ENABLE_MSK); 2091 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 2092 2093 return res; 2094 } 2095 2096 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba) 2097 { 2098 u32 port_state; 2099 2100 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 2101 if (port_state & 0x1ff) 2102 return true; 2103 2104 return false; 2105 } 2106 2107 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 2108 { 2109 int res = 0; 2110 u32 phy_state, sl_ctrl, txid_auto; 2111 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2112 struct hisi_sas_port *port = phy->port; 2113 2114 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 2115 2116 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 2117 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 2118 2119 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 2120 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 2121 sl_ctrl & ~SL_CONTROL_CTA_MSK); 2122 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id)) 2123 if (!check_any_wideports_v2_hw(hisi_hba) && 2124 timer_pending(&hisi_hba->timer)) 2125 del_timer(&hisi_hba->timer); 2126 2127 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 2128 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 2129 txid_auto | TXID_AUTO_CT3_MSK); 2130 2131 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 2132 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 2133 2134 return res; 2135 } 2136 2137 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p) 2138 { 2139 struct hisi_hba *hisi_hba = p; 2140 u32 irq_msk; 2141 int phy_no = 0; 2142 irqreturn_t res = IRQ_HANDLED; 2143 2144 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) 2145 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff; 2146 while (irq_msk) { 2147 if (irq_msk & 1) { 2148 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 2149 CHL_INT0); 2150 2151 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 2152 /* phy up */ 2153 if (phy_up_v2_hw(phy_no, hisi_hba)) { 2154 res = IRQ_NONE; 2155 goto end; 2156 } 2157 2158 if (irq_value & CHL_INT0_NOT_RDY_MSK) 2159 /* phy down */ 2160 if (phy_down_v2_hw(phy_no, hisi_hba)) { 2161 res = IRQ_NONE; 2162 goto end; 2163 } 2164 } 2165 irq_msk >>= 1; 2166 phy_no++; 2167 } 2168 2169 end: 2170 return res; 2171 } 2172 2173 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 2174 { 2175 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2176 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2177 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 2178 u32 bcast_status; 2179 2180 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 2181 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 2182 if (bcast_status & RX_BCAST_CHG_MSK) 2183 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 2184 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 2185 CHL_INT0_SL_RX_BCST_ACK_MSK); 2186 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 2187 } 2188 2189 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) 2190 { 2191 struct hisi_hba *hisi_hba = p; 2192 struct device *dev = &hisi_hba->pdev->dev; 2193 u32 ent_msk, ent_tmp, irq_msk; 2194 int phy_no = 0; 2195 2196 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 2197 ent_tmp = ent_msk; 2198 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK; 2199 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk); 2200 2201 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >> 2202 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff; 2203 2204 while (irq_msk) { 2205 if (irq_msk & (1 << phy_no)) { 2206 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 2207 CHL_INT0); 2208 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, 2209 CHL_INT1); 2210 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, 2211 CHL_INT2); 2212 2213 if (irq_value1) { 2214 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK | 2215 CHL_INT1_DMAC_TX_ECC_ERR_MSK)) 2216 panic("%s: DMAC RX/TX ecc bad error!\ 2217 (0x%x)", 2218 dev_name(dev), irq_value1); 2219 2220 hisi_sas_phy_write32(hisi_hba, phy_no, 2221 CHL_INT1, irq_value1); 2222 } 2223 2224 if (irq_value2) 2225 hisi_sas_phy_write32(hisi_hba, phy_no, 2226 CHL_INT2, irq_value2); 2227 2228 2229 if (irq_value0) { 2230 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK) 2231 phy_bcast_v2_hw(phy_no, hisi_hba); 2232 2233 hisi_sas_phy_write32(hisi_hba, phy_no, 2234 CHL_INT0, irq_value0 2235 & (~CHL_INT0_HOTPLUG_TOUT_MSK) 2236 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 2237 & (~CHL_INT0_NOT_RDY_MSK)); 2238 } 2239 } 2240 irq_msk &= ~(1 << phy_no); 2241 phy_no++; 2242 } 2243 2244 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp); 2245 2246 return IRQ_HANDLED; 2247 } 2248 2249 static void 2250 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value) 2251 { 2252 struct device *dev = &hisi_hba->pdev->dev; 2253 u32 reg_val; 2254 2255 if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF)) { 2256 reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR); 2257 dev_warn(dev, "hgc_dqe_acc1b_intr found: \ 2258 Ram address is 0x%08X\n", 2259 (reg_val & HGC_DQE_ECC_1B_ADDR_MSK) >> 2260 HGC_DQE_ECC_1B_ADDR_OFF); 2261 } 2262 2263 if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF)) { 2264 reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR); 2265 dev_warn(dev, "hgc_iost_acc1b_intr found: \ 2266 Ram address is 0x%08X\n", 2267 (reg_val & HGC_IOST_ECC_1B_ADDR_MSK) >> 2268 HGC_IOST_ECC_1B_ADDR_OFF); 2269 } 2270 2271 if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF)) { 2272 reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR); 2273 dev_warn(dev, "hgc_itct_acc1b_intr found: \ 2274 Ram address is 0x%08X\n", 2275 (reg_val & HGC_ITCT_ECC_1B_ADDR_MSK) >> 2276 HGC_ITCT_ECC_1B_ADDR_OFF); 2277 } 2278 2279 if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF)) { 2280 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2); 2281 dev_warn(dev, "hgc_iostl_acc1b_intr found: \ 2282 memory address is 0x%08X\n", 2283 (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK) >> 2284 HGC_LM_DFX_STATUS2_IOSTLIST_OFF); 2285 } 2286 2287 if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF)) { 2288 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2); 2289 dev_warn(dev, "hgc_itctl_acc1b_intr found: \ 2290 memory address is 0x%08X\n", 2291 (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK) >> 2292 HGC_LM_DFX_STATUS2_ITCTLIST_OFF); 2293 } 2294 2295 if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF)) { 2296 reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR); 2297 dev_warn(dev, "hgc_cqe_acc1b_intr found: \ 2298 Ram address is 0x%08X\n", 2299 (reg_val & HGC_CQE_ECC_1B_ADDR_MSK) >> 2300 HGC_CQE_ECC_1B_ADDR_OFF); 2301 } 2302 2303 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF)) { 2304 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); 2305 dev_warn(dev, "rxm_mem0_acc1b_intr found: \ 2306 memory address is 0x%08X\n", 2307 (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK) >> 2308 HGC_RXM_DFX_STATUS14_MEM0_OFF); 2309 } 2310 2311 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF)) { 2312 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); 2313 dev_warn(dev, "rxm_mem1_acc1b_intr found: \ 2314 memory address is 0x%08X\n", 2315 (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK) >> 2316 HGC_RXM_DFX_STATUS14_MEM1_OFF); 2317 } 2318 2319 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF)) { 2320 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); 2321 dev_warn(dev, "rxm_mem2_acc1b_intr found: \ 2322 memory address is 0x%08X\n", 2323 (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK) >> 2324 HGC_RXM_DFX_STATUS14_MEM2_OFF); 2325 } 2326 2327 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF)) { 2328 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15); 2329 dev_warn(dev, "rxm_mem3_acc1b_intr found: \ 2330 memory address is 0x%08X\n", 2331 (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK) >> 2332 HGC_RXM_DFX_STATUS15_MEM3_OFF); 2333 } 2334 2335 } 2336 2337 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, 2338 u32 irq_value) 2339 { 2340 u32 reg_val; 2341 struct device *dev = &hisi_hba->pdev->dev; 2342 2343 if (irq_value & BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF)) { 2344 reg_val = hisi_sas_read32(hisi_hba, HGC_DQE_ECC_ADDR); 2345 panic("%s: hgc_dqe_accbad_intr (0x%x) found: \ 2346 Ram address is 0x%08X\n", 2347 dev_name(dev), irq_value, 2348 (reg_val & HGC_DQE_ECC_MB_ADDR_MSK) >> 2349 HGC_DQE_ECC_MB_ADDR_OFF); 2350 } 2351 2352 if (irq_value & BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF)) { 2353 reg_val = hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR); 2354 panic("%s: hgc_iost_accbad_intr (0x%x) found: \ 2355 Ram address is 0x%08X\n", 2356 dev_name(dev), irq_value, 2357 (reg_val & HGC_IOST_ECC_MB_ADDR_MSK) >> 2358 HGC_IOST_ECC_MB_ADDR_OFF); 2359 } 2360 2361 if (irq_value & BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF)) { 2362 reg_val = hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR); 2363 panic("%s: hgc_itct_accbad_intr (0x%x) found: \ 2364 Ram address is 0x%08X\n", 2365 dev_name(dev), irq_value, 2366 (reg_val & HGC_ITCT_ECC_MB_ADDR_MSK) >> 2367 HGC_ITCT_ECC_MB_ADDR_OFF); 2368 } 2369 2370 if (irq_value & BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF)) { 2371 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2); 2372 panic("%s: hgc_iostl_accbad_intr (0x%x) found: \ 2373 memory address is 0x%08X\n", 2374 dev_name(dev), irq_value, 2375 (reg_val & HGC_LM_DFX_STATUS2_IOSTLIST_MSK) >> 2376 HGC_LM_DFX_STATUS2_IOSTLIST_OFF); 2377 } 2378 2379 if (irq_value & BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF)) { 2380 reg_val = hisi_sas_read32(hisi_hba, HGC_LM_DFX_STATUS2); 2381 panic("%s: hgc_itctl_accbad_intr (0x%x) found: \ 2382 memory address is 0x%08X\n", 2383 dev_name(dev), irq_value, 2384 (reg_val & HGC_LM_DFX_STATUS2_ITCTLIST_MSK) >> 2385 HGC_LM_DFX_STATUS2_ITCTLIST_OFF); 2386 } 2387 2388 if (irq_value & BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF)) { 2389 reg_val = hisi_sas_read32(hisi_hba, HGC_CQE_ECC_ADDR); 2390 panic("%s: hgc_cqe_accbad_intr (0x%x) found: \ 2391 Ram address is 0x%08X\n", 2392 dev_name(dev), irq_value, 2393 (reg_val & HGC_CQE_ECC_MB_ADDR_MSK) >> 2394 HGC_CQE_ECC_MB_ADDR_OFF); 2395 } 2396 2397 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF)) { 2398 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); 2399 panic("%s: rxm_mem0_accbad_intr (0x%x) found: \ 2400 memory address is 0x%08X\n", 2401 dev_name(dev), irq_value, 2402 (reg_val & HGC_RXM_DFX_STATUS14_MEM0_MSK) >> 2403 HGC_RXM_DFX_STATUS14_MEM0_OFF); 2404 } 2405 2406 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF)) { 2407 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); 2408 panic("%s: rxm_mem1_accbad_intr (0x%x) found: \ 2409 memory address is 0x%08X\n", 2410 dev_name(dev), irq_value, 2411 (reg_val & HGC_RXM_DFX_STATUS14_MEM1_MSK) >> 2412 HGC_RXM_DFX_STATUS14_MEM1_OFF); 2413 } 2414 2415 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF)) { 2416 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS14); 2417 panic("%s: rxm_mem2_accbad_intr (0x%x) found: \ 2418 memory address is 0x%08X\n", 2419 dev_name(dev), irq_value, 2420 (reg_val & HGC_RXM_DFX_STATUS14_MEM2_MSK) >> 2421 HGC_RXM_DFX_STATUS14_MEM2_OFF); 2422 } 2423 2424 if (irq_value & BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF)) { 2425 reg_val = hisi_sas_read32(hisi_hba, HGC_RXM_DFX_STATUS15); 2426 panic("%s: rxm_mem3_accbad_intr (0x%x) found: \ 2427 memory address is 0x%08X\n", 2428 dev_name(dev), irq_value, 2429 (reg_val & HGC_RXM_DFX_STATUS15_MEM3_MSK) >> 2430 HGC_RXM_DFX_STATUS15_MEM3_OFF); 2431 } 2432 2433 } 2434 2435 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p) 2436 { 2437 struct hisi_hba *hisi_hba = p; 2438 u32 irq_value, irq_msk; 2439 2440 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK); 2441 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff); 2442 2443 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); 2444 if (irq_value) { 2445 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value); 2446 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value); 2447 } 2448 2449 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value); 2450 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk); 2451 2452 return IRQ_HANDLED; 2453 } 2454 2455 #define AXI_ERR_NR 8 2456 static const char axi_err_info[AXI_ERR_NR][32] = { 2457 "IOST_AXI_W_ERR", 2458 "IOST_AXI_R_ERR", 2459 "ITCT_AXI_W_ERR", 2460 "ITCT_AXI_R_ERR", 2461 "SATA_AXI_W_ERR", 2462 "SATA_AXI_R_ERR", 2463 "DQE_AXI_R_ERR", 2464 "CQE_AXI_W_ERR" 2465 }; 2466 2467 #define FIFO_ERR_NR 5 2468 static const char fifo_err_info[FIFO_ERR_NR][32] = { 2469 "CQE_WINFO_FIFO", 2470 "CQE_MSG_FIFIO", 2471 "GETDQE_FIFO", 2472 "CMDP_FIFO", 2473 "AWTCTRL_FIFO" 2474 }; 2475 2476 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p) 2477 { 2478 struct hisi_hba *hisi_hba = p; 2479 u32 irq_value, irq_msk, err_value; 2480 struct device *dev = &hisi_hba->pdev->dev; 2481 2482 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 2483 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe); 2484 2485 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 2486 if (irq_value) { 2487 if (irq_value & BIT(ENT_INT_SRC3_WP_DEPTH_OFF)) { 2488 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 2489 1 << ENT_INT_SRC3_WP_DEPTH_OFF); 2490 panic("%s: write pointer and depth error (0x%x) \ 2491 found!\n", 2492 dev_name(dev), irq_value); 2493 } 2494 2495 if (irq_value & BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF)) { 2496 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 2497 1 << 2498 ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF); 2499 panic("%s: iptt no match slot error (0x%x) found!\n", 2500 dev_name(dev), irq_value); 2501 } 2502 2503 if (irq_value & BIT(ENT_INT_SRC3_RP_DEPTH_OFF)) 2504 panic("%s: read pointer and depth error (0x%x) \ 2505 found!\n", 2506 dev_name(dev), irq_value); 2507 2508 if (irq_value & BIT(ENT_INT_SRC3_AXI_OFF)) { 2509 int i; 2510 2511 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 2512 1 << ENT_INT_SRC3_AXI_OFF); 2513 err_value = hisi_sas_read32(hisi_hba, 2514 HGC_AXI_FIFO_ERR_INFO); 2515 2516 for (i = 0; i < AXI_ERR_NR; i++) { 2517 if (err_value & BIT(i)) 2518 panic("%s: %s (0x%x) found!\n", 2519 dev_name(dev), 2520 axi_err_info[i], irq_value); 2521 } 2522 } 2523 2524 if (irq_value & BIT(ENT_INT_SRC3_FIFO_OFF)) { 2525 int i; 2526 2527 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 2528 1 << ENT_INT_SRC3_FIFO_OFF); 2529 err_value = hisi_sas_read32(hisi_hba, 2530 HGC_AXI_FIFO_ERR_INFO); 2531 2532 for (i = 0; i < FIFO_ERR_NR; i++) { 2533 if (err_value & BIT(AXI_ERR_NR + i)) 2534 panic("%s: %s (0x%x) found!\n", 2535 dev_name(dev), 2536 fifo_err_info[i], irq_value); 2537 } 2538 2539 } 2540 2541 if (irq_value & BIT(ENT_INT_SRC3_LM_OFF)) { 2542 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 2543 1 << ENT_INT_SRC3_LM_OFF); 2544 panic("%s: LM add/fetch list error (0x%x) found!\n", 2545 dev_name(dev), irq_value); 2546 } 2547 2548 if (irq_value & BIT(ENT_INT_SRC3_ABT_OFF)) { 2549 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 2550 1 << ENT_INT_SRC3_ABT_OFF); 2551 panic("%s: SAS_HGC_ABT fetch LM list error (0x%x) found!\n", 2552 dev_name(dev), irq_value); 2553 } 2554 } 2555 2556 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 2557 2558 return IRQ_HANDLED; 2559 } 2560 2561 static void cq_tasklet_v2_hw(unsigned long val) 2562 { 2563 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 2564 struct hisi_hba *hisi_hba = cq->hisi_hba; 2565 struct hisi_sas_slot *slot; 2566 struct hisi_sas_itct *itct; 2567 struct hisi_sas_complete_v2_hdr *complete_queue; 2568 u32 rd_point = cq->rd_point, wr_point, dev_id; 2569 int queue = cq->id; 2570 2571 complete_queue = hisi_hba->complete_hdr[queue]; 2572 2573 spin_lock(&hisi_hba->lock); 2574 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 2575 (0x14 * queue)); 2576 2577 while (rd_point != wr_point) { 2578 struct hisi_sas_complete_v2_hdr *complete_hdr; 2579 int iptt; 2580 2581 complete_hdr = &complete_queue[rd_point]; 2582 2583 /* Check for NCQ completion */ 2584 if (complete_hdr->act) { 2585 u32 act_tmp = complete_hdr->act; 2586 int ncq_tag_count = ffs(act_tmp); 2587 2588 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >> 2589 CMPLT_HDR_DEV_ID_OFF; 2590 itct = &hisi_hba->itct[dev_id]; 2591 2592 /* The NCQ tags are held in the itct header */ 2593 while (ncq_tag_count) { 2594 __le64 *ncq_tag = &itct->qw4_15[0]; 2595 2596 ncq_tag_count -= 1; 2597 iptt = (ncq_tag[ncq_tag_count / 5] 2598 >> (ncq_tag_count % 5) * 12) & 0xfff; 2599 2600 slot = &hisi_hba->slot_info[iptt]; 2601 slot->cmplt_queue_slot = rd_point; 2602 slot->cmplt_queue = queue; 2603 slot_complete_v2_hw(hisi_hba, slot, 0); 2604 2605 act_tmp &= ~(1 << ncq_tag_count); 2606 ncq_tag_count = ffs(act_tmp); 2607 } 2608 } else { 2609 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; 2610 slot = &hisi_hba->slot_info[iptt]; 2611 slot->cmplt_queue_slot = rd_point; 2612 slot->cmplt_queue = queue; 2613 slot_complete_v2_hw(hisi_hba, slot, 0); 2614 } 2615 2616 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 2617 rd_point = 0; 2618 } 2619 2620 /* update rd_point */ 2621 cq->rd_point = rd_point; 2622 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 2623 spin_unlock(&hisi_hba->lock); 2624 } 2625 2626 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p) 2627 { 2628 struct hisi_sas_cq *cq = p; 2629 struct hisi_hba *hisi_hba = cq->hisi_hba; 2630 int queue = cq->id; 2631 2632 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 2633 2634 tasklet_schedule(&cq->tasklet); 2635 2636 return IRQ_HANDLED; 2637 } 2638 2639 static irqreturn_t sata_int_v2_hw(int irq_no, void *p) 2640 { 2641 struct hisi_sas_phy *phy = p; 2642 struct hisi_hba *hisi_hba = phy->hisi_hba; 2643 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2644 struct device *dev = &hisi_hba->pdev->dev; 2645 struct hisi_sas_initial_fis *initial_fis; 2646 struct dev_to_host_fis *fis; 2647 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate; 2648 irqreturn_t res = IRQ_HANDLED; 2649 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 2650 int phy_no, offset; 2651 2652 phy_no = sas_phy->id; 2653 initial_fis = &hisi_hba->initial_fis[phy_no]; 2654 fis = &initial_fis->fis; 2655 2656 offset = 4 * (phy_no / 4); 2657 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset); 2658 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, 2659 ent_msk | 1 << ((phy_no % 4) * 8)); 2660 2661 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset); 2662 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF * 2663 (phy_no % 4))); 2664 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4); 2665 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) { 2666 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no); 2667 res = IRQ_NONE; 2668 goto end; 2669 } 2670 2671 /* check ERR bit of Status Register */ 2672 if (fis->status & ATA_ERR) { 2673 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no, 2674 fis->status); 2675 disable_phy_v2_hw(hisi_hba, phy_no); 2676 enable_phy_v2_hw(hisi_hba, phy_no); 2677 res = IRQ_NONE; 2678 goto end; 2679 } 2680 2681 if (unlikely(phy_no == 8)) { 2682 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 2683 2684 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 2685 PORT_STATE_PHY8_PORT_NUM_OFF; 2686 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> 2687 PORT_STATE_PHY8_CONN_RATE_OFF; 2688 } else { 2689 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 2690 port_id = (port_id >> (4 * phy_no)) & 0xf; 2691 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 2692 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 2693 } 2694 2695 if (port_id == 0xf) { 2696 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no); 2697 res = IRQ_NONE; 2698 goto end; 2699 } 2700 2701 sas_phy->linkrate = link_rate; 2702 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, 2703 HARD_PHY_LINKRATE); 2704 phy->maximum_linkrate = hard_phy_linkrate & 0xf; 2705 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; 2706 2707 sas_phy->oob_mode = SATA_OOB_MODE; 2708 /* Make up some unique SAS address */ 2709 attached_sas_addr[0] = 0x50; 2710 attached_sas_addr[7] = phy_no; 2711 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE); 2712 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis)); 2713 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate); 2714 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 2715 phy->port_id = port_id; 2716 phy->phy_type |= PORT_TYPE_SATA; 2717 phy->phy_attached = 1; 2718 phy->identify.device_type = SAS_SATA_DEV; 2719 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 2720 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 2721 queue_work(hisi_hba->wq, &phy->phyup_ws); 2722 2723 end: 2724 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp); 2725 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk); 2726 2727 return res; 2728 } 2729 2730 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { 2731 int_phy_updown_v2_hw, 2732 int_chnl_int_v2_hw, 2733 }; 2734 2735 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = { 2736 fatal_ecc_int_v2_hw, 2737 fatal_axi_int_v2_hw 2738 }; 2739 2740 /** 2741 * There is a limitation in the hip06 chipset that we need 2742 * to map in all mbigen interrupts, even if they are not used. 2743 */ 2744 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba) 2745 { 2746 struct platform_device *pdev = hisi_hba->pdev; 2747 struct device *dev = &pdev->dev; 2748 int i, irq, rc, irq_map[128]; 2749 2750 2751 for (i = 0; i < 128; i++) 2752 irq_map[i] = platform_get_irq(pdev, i); 2753 2754 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) { 2755 int idx = i; 2756 2757 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */ 2758 if (!irq) { 2759 dev_err(dev, "irq init: fail map phy interrupt %d\n", 2760 idx); 2761 return -ENOENT; 2762 } 2763 2764 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0, 2765 DRV_NAME " phy", hisi_hba); 2766 if (rc) { 2767 dev_err(dev, "irq init: could not request " 2768 "phy interrupt %d, rc=%d\n", 2769 irq, rc); 2770 return -ENOENT; 2771 } 2772 } 2773 2774 for (i = 0; i < hisi_hba->n_phy; i++) { 2775 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 2776 int idx = i + 72; /* First SATA interrupt is irq72 */ 2777 2778 irq = irq_map[idx]; 2779 if (!irq) { 2780 dev_err(dev, "irq init: fail map phy interrupt %d\n", 2781 idx); 2782 return -ENOENT; 2783 } 2784 2785 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0, 2786 DRV_NAME " sata", phy); 2787 if (rc) { 2788 dev_err(dev, "irq init: could not request " 2789 "sata interrupt %d, rc=%d\n", 2790 irq, rc); 2791 return -ENOENT; 2792 } 2793 } 2794 2795 for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++) { 2796 int idx = i; 2797 2798 irq = irq_map[idx + 81]; 2799 if (!irq) { 2800 dev_err(dev, "irq init: fail map fatal interrupt %d\n", 2801 idx); 2802 return -ENOENT; 2803 } 2804 2805 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0, 2806 DRV_NAME " fatal", hisi_hba); 2807 if (rc) { 2808 dev_err(dev, 2809 "irq init: could not request fatal interrupt %d, rc=%d\n", 2810 irq, rc); 2811 return -ENOENT; 2812 } 2813 } 2814 2815 for (i = 0; i < hisi_hba->queue_count; i++) { 2816 int idx = i + 96; /* First cq interrupt is irq96 */ 2817 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2818 struct tasklet_struct *t = &cq->tasklet; 2819 2820 irq = irq_map[idx]; 2821 if (!irq) { 2822 dev_err(dev, 2823 "irq init: could not map cq interrupt %d\n", 2824 idx); 2825 return -ENOENT; 2826 } 2827 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0, 2828 DRV_NAME " cq", &hisi_hba->cq[i]); 2829 if (rc) { 2830 dev_err(dev, 2831 "irq init: could not request cq interrupt %d, rc=%d\n", 2832 irq, rc); 2833 return -ENOENT; 2834 } 2835 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq); 2836 } 2837 2838 return 0; 2839 } 2840 2841 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba) 2842 { 2843 int rc; 2844 2845 rc = hw_init_v2_hw(hisi_hba); 2846 if (rc) 2847 return rc; 2848 2849 rc = interrupt_init_v2_hw(hisi_hba); 2850 if (rc) 2851 return rc; 2852 2853 phys_init_v2_hw(hisi_hba); 2854 2855 return 0; 2856 } 2857 2858 static const struct hisi_sas_hw hisi_sas_v2_hw = { 2859 .hw_init = hisi_sas_v2_init, 2860 .setup_itct = setup_itct_v2_hw, 2861 .slot_index_alloc = slot_index_alloc_quirk_v2_hw, 2862 .alloc_dev = alloc_dev_quirk_v2_hw, 2863 .sl_notify = sl_notify_v2_hw, 2864 .get_wideport_bitmap = get_wideport_bitmap_v2_hw, 2865 .free_device = free_device_v2_hw, 2866 .prep_smp = prep_smp_v2_hw, 2867 .prep_ssp = prep_ssp_v2_hw, 2868 .prep_stp = prep_ata_v2_hw, 2869 .prep_abort = prep_abort_v2_hw, 2870 .get_free_slot = get_free_slot_v2_hw, 2871 .start_delivery = start_delivery_v2_hw, 2872 .slot_complete = slot_complete_v2_hw, 2873 .phy_enable = enable_phy_v2_hw, 2874 .phy_disable = disable_phy_v2_hw, 2875 .phy_hard_reset = phy_hard_reset_v2_hw, 2876 .phy_set_linkrate = phy_set_linkrate_v2_hw, 2877 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw, 2878 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW, 2879 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr), 2880 }; 2881 2882 static int hisi_sas_v2_probe(struct platform_device *pdev) 2883 { 2884 /* 2885 * Check if we should defer the probe before we probe the 2886 * upper layer, as it's hard to defer later on. 2887 */ 2888 int ret = platform_get_irq(pdev, 0); 2889 2890 if (ret < 0) { 2891 if (ret != -EPROBE_DEFER) 2892 dev_err(&pdev->dev, "cannot obtain irq\n"); 2893 return ret; 2894 } 2895 2896 return hisi_sas_probe(pdev, &hisi_sas_v2_hw); 2897 } 2898 2899 static int hisi_sas_v2_remove(struct platform_device *pdev) 2900 { 2901 struct sas_ha_struct *sha = platform_get_drvdata(pdev); 2902 struct hisi_hba *hisi_hba = sha->lldd_ha; 2903 2904 if (timer_pending(&hisi_hba->timer)) 2905 del_timer(&hisi_hba->timer); 2906 2907 return hisi_sas_remove(pdev); 2908 } 2909 2910 static const struct of_device_id sas_v2_of_match[] = { 2911 { .compatible = "hisilicon,hip06-sas-v2",}, 2912 { .compatible = "hisilicon,hip07-sas-v2",}, 2913 {}, 2914 }; 2915 MODULE_DEVICE_TABLE(of, sas_v2_of_match); 2916 2917 static const struct acpi_device_id sas_v2_acpi_match[] = { 2918 { "HISI0162", 0 }, 2919 { } 2920 }; 2921 2922 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match); 2923 2924 static struct platform_driver hisi_sas_v2_driver = { 2925 .probe = hisi_sas_v2_probe, 2926 .remove = hisi_sas_v2_remove, 2927 .driver = { 2928 .name = DRV_NAME, 2929 .of_match_table = sas_v2_of_match, 2930 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match), 2931 }, 2932 }; 2933 2934 module_platform_driver(hisi_sas_v2_driver); 2935 2936 MODULE_LICENSE("GPL"); 2937 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 2938 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver"); 2939 MODULE_ALIAS("platform:" DRV_NAME); 2940