1 /* 2 * Copyright (c) 2016 Linaro Ltd. 3 * Copyright (c) 2016 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 */ 11 12 #include "hisi_sas.h" 13 #define DRV_NAME "hisi_sas_v2_hw" 14 15 /* global registers need init*/ 16 #define DLVRY_QUEUE_ENABLE 0x0 17 #define IOST_BASE_ADDR_LO 0x8 18 #define IOST_BASE_ADDR_HI 0xc 19 #define ITCT_BASE_ADDR_LO 0x10 20 #define ITCT_BASE_ADDR_HI 0x14 21 #define IO_BROKEN_MSG_ADDR_LO 0x18 22 #define IO_BROKEN_MSG_ADDR_HI 0x1c 23 #define PHY_CONTEXT 0x20 24 #define PHY_STATE 0x24 25 #define PHY_PORT_NUM_MA 0x28 26 #define PORT_STATE 0x2c 27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16 28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF) 29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20 30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF) 31 #define PHY_CONN_RATE 0x30 32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38 33 #define AXI_AHB_CLK_CFG 0x3c 34 #define ITCT_CLR 0x44 35 #define ITCT_CLR_EN_OFF 16 36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 37 #define ITCT_DEV_OFF 0 38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 39 #define AXI_USER1 0x48 40 #define AXI_USER2 0x4c 41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 47 #define HGC_GET_ITV_TIME 0x90 48 #define DEVICE_MSG_WORK_MODE 0x94 49 #define OPENA_WT_CONTI_TIME 0x9c 50 #define I_T_NEXUS_LOSS_TIME 0xa0 51 #define MAX_CON_TIME_LIMIT_TIME 0xa4 52 #define BUS_INACTIVE_LIMIT_TIME 0xa8 53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 54 #define CFG_AGING_TIME 0xbc 55 #define HGC_DFX_CFG2 0xc0 56 #define HGC_IOMB_PROC1_STATUS 0x104 57 #define CFG_1US_TIMER_TRSH 0xcc 58 #define HGC_INVLD_DQE_INFO 0x148 59 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9 60 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF) 61 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18 62 #define INT_COAL_EN 0x19c 63 #define OQ_INT_COAL_TIME 0x1a0 64 #define OQ_INT_COAL_CNT 0x1a4 65 #define ENT_INT_COAL_TIME 0x1a8 66 #define ENT_INT_COAL_CNT 0x1ac 67 #define OQ_INT_SRC 0x1b0 68 #define OQ_INT_SRC_MSK 0x1b4 69 #define ENT_INT_SRC1 0x1b8 70 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 71 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 72 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 73 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 74 #define ENT_INT_SRC2 0x1bc 75 #define ENT_INT_SRC3 0x1c0 76 #define ENT_INT_SRC3_ITC_INT_OFF 15 77 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 78 #define ENT_INT_SRC_MSK1 0x1c4 79 #define ENT_INT_SRC_MSK2 0x1c8 80 #define ENT_INT_SRC_MSK3 0x1cc 81 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 82 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 83 #define SAS_ECC_INTR_MSK 0x1ec 84 #define HGC_ERR_STAT_EN 0x238 85 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 86 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 87 #define DLVRY_Q_0_DEPTH 0x268 88 #define DLVRY_Q_0_WR_PTR 0x26c 89 #define DLVRY_Q_0_RD_PTR 0x270 90 #define HYPER_STREAM_ID_EN_CFG 0xc80 91 #define OQ0_INT_SRC_MSK 0xc90 92 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 93 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 94 #define COMPL_Q_0_DEPTH 0x4e8 95 #define COMPL_Q_0_WR_PTR 0x4ec 96 #define COMPL_Q_0_RD_PTR 0x4f0 97 98 /* phy registers need init */ 99 #define PORT_BASE (0x2000) 100 101 #define PHY_CFG (PORT_BASE + 0x0) 102 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 103 #define PHY_CFG_ENA_OFF 0 104 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 105 #define PHY_CFG_DC_OPT_OFF 2 106 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 107 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 108 #define PROG_PHY_LINK_RATE_MAX_OFF 0 109 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF) 110 #define PHY_CTRL (PORT_BASE + 0x14) 111 #define PHY_CTRL_RESET_OFF 0 112 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 113 #define SAS_PHY_CTRL (PORT_BASE + 0x20) 114 #define SL_CFG (PORT_BASE + 0x84) 115 #define PHY_PCN (PORT_BASE + 0x44) 116 #define SL_TOUT_CFG (PORT_BASE + 0x8c) 117 #define SL_CONTROL (PORT_BASE + 0x94) 118 #define SL_CONTROL_NOTIFY_EN_OFF 0 119 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 120 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 121 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 122 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 123 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 124 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 125 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 126 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 127 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 128 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) 129 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) 130 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) 131 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) 132 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) 133 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) 134 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 135 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c) 136 #define CHL_INT0 (PORT_BASE + 0x1b4) 137 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 138 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 139 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 140 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 141 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 142 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 143 #define CHL_INT0_NOT_RDY_OFF 4 144 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 145 #define CHL_INT0_PHY_RDY_OFF 5 146 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 147 #define CHL_INT1 (PORT_BASE + 0x1b8) 148 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 149 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 150 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 151 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 152 #define CHL_INT2 (PORT_BASE + 0x1bc) 153 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 154 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 155 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 156 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 157 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 158 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 159 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 160 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 161 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 162 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 163 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 164 #define DMA_TX_STATUS_BUSY_OFF 0 165 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 166 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 167 #define DMA_RX_STATUS_BUSY_OFF 0 168 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 169 170 #define AXI_CFG (0x5100) 171 #define AM_CFG_MAX_TRANS (0x5010) 172 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 173 174 /* HW dma structures */ 175 /* Delivery queue header */ 176 /* dw0 */ 177 #define CMD_HDR_RESP_REPORT_OFF 5 178 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 179 #define CMD_HDR_TLR_CTRL_OFF 6 180 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 181 #define CMD_HDR_PORT_OFF 18 182 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 183 #define CMD_HDR_PRIORITY_OFF 27 184 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 185 #define CMD_HDR_CMD_OFF 29 186 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 187 /* dw1 */ 188 #define CMD_HDR_DIR_OFF 5 189 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 190 #define CMD_HDR_RESET_OFF 7 191 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 192 #define CMD_HDR_VDTL_OFF 10 193 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 194 #define CMD_HDR_FRAME_TYPE_OFF 11 195 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 196 #define CMD_HDR_DEV_ID_OFF 16 197 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 198 /* dw2 */ 199 #define CMD_HDR_CFL_OFF 0 200 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 201 #define CMD_HDR_NCQ_TAG_OFF 10 202 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 203 #define CMD_HDR_MRFL_OFF 15 204 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 205 #define CMD_HDR_SG_MOD_OFF 24 206 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 207 #define CMD_HDR_FIRST_BURST_OFF 26 208 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF) 209 /* dw3 */ 210 #define CMD_HDR_IPTT_OFF 0 211 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 212 /* dw6 */ 213 #define CMD_HDR_DIF_SGL_LEN_OFF 0 214 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 215 #define CMD_HDR_DATA_SGL_LEN_OFF 16 216 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 217 218 /* Completion header */ 219 /* dw0 */ 220 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 221 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 222 #define CMPLT_HDR_ERX_OFF 12 223 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 224 /* dw1 */ 225 #define CMPLT_HDR_IPTT_OFF 0 226 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 227 #define CMPLT_HDR_DEV_ID_OFF 16 228 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 229 230 /* ITCT header */ 231 /* qw0 */ 232 #define ITCT_HDR_DEV_TYPE_OFF 0 233 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 234 #define ITCT_HDR_VALID_OFF 2 235 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 236 #define ITCT_HDR_MCR_OFF 5 237 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 238 #define ITCT_HDR_VLN_OFF 9 239 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 240 #define ITCT_HDR_PORT_ID_OFF 28 241 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 242 /* qw2 */ 243 #define ITCT_HDR_INLT_OFF 0 244 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 245 #define ITCT_HDR_BITLT_OFF 16 246 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF) 247 #define ITCT_HDR_MCTLT_OFF 32 248 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF) 249 #define ITCT_HDR_RTOLT_OFF 48 250 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 251 252 struct hisi_sas_complete_v2_hdr { 253 __le32 dw0; 254 __le32 dw1; 255 __le32 act; 256 __le32 dw3; 257 }; 258 259 struct hisi_sas_err_record_v2 { 260 /* dw0 */ 261 __le32 trans_tx_fail_type; 262 263 /* dw1 */ 264 __le32 trans_rx_fail_type; 265 266 /* dw2 */ 267 __le16 dma_tx_err_type; 268 __le16 sipc_rx_err_type; 269 270 /* dw3 */ 271 __le32 dma_rx_err_type; 272 }; 273 274 enum { 275 HISI_SAS_PHY_PHY_UPDOWN, 276 HISI_SAS_PHY_CHNL_INT, 277 HISI_SAS_PHY_INT_NR 278 }; 279 280 enum { 281 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */ 282 TRANS_RX_FAIL_BASE = 0x100, /* dw1 */ 283 DMA_TX_ERR_BASE = 0x200, /* dw2 bit 15-0 */ 284 SIPC_RX_ERR_BASE = 0x300, /* dw2 bit 31-16*/ 285 DMA_RX_ERR_BASE = 0x400, /* dw3 */ 286 287 /* trans tx*/ 288 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */ 289 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */ 290 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */ 291 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */ 292 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */ 293 RESERVED0, /* 0x5 */ 294 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */ 295 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */ 296 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */ 297 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */ 298 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */ 299 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */ 300 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */ 301 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */ 302 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */ 303 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */ 304 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */ 305 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */ 306 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */ 307 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */ 308 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */ 309 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */ 310 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/ 311 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */ 312 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */ 313 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */ 314 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/ 315 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/ 316 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */ 317 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */ 318 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */ 319 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */ 320 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */ 321 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */ 322 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */ 323 324 /* trans rx */ 325 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x100 */ 326 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x101 for sata/stp */ 327 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x102 for ssp/smp */ 328 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */ 329 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x103 for sata/stp */ 330 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x104 for sata/stp */ 331 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x105 for smp */ 332 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */ 333 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x106 for sata/stp*/ 334 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x107 */ 335 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x108 */ 336 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x109 */ 337 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x10a */ 338 RESERVED1, /* 0x10b */ 339 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x10c */ 340 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x10d */ 341 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x10e */ 342 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x10f */ 343 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x110 for ssp/smp */ 344 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x111 for ssp */ 345 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */ 346 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x112 for ssp*/ 347 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */ 348 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x113 for ssp */ 349 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */ 350 RESERVED2, /* 0x114 */ 351 RESERVED3, /* 0x115 */ 352 RESERVED4, /* 0x116 */ 353 RESERVED5, /* 0x117 */ 354 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x118 */ 355 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x119 */ 356 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x11a */ 357 RESERVED6, /* 0x11b */ 358 RESERVED7, /* 0x11c */ 359 RESERVED8, /* 0x11d */ 360 RESERVED9, /* 0x11e */ 361 TRANS_RX_R_ERR, /* 0x11f */ 362 363 /* dma tx */ 364 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x200 */ 365 DMA_TX_DIF_APP_ERR, /* 0x201 */ 366 DMA_TX_DIF_RPP_ERR, /* 0x202 */ 367 DMA_TX_DATA_SGL_OVERFLOW, /* 0x203 */ 368 DMA_TX_DIF_SGL_OVERFLOW, /* 0x204 */ 369 DMA_TX_UNEXP_XFER_ERR, /* 0x205 */ 370 DMA_TX_UNEXP_RETRANS_ERR, /* 0x206 */ 371 DMA_TX_XFER_LEN_OVERFLOW, /* 0x207 */ 372 DMA_TX_XFER_OFFSET_ERR, /* 0x208 */ 373 DMA_TX_RAM_ECC_ERR, /* 0x209 */ 374 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x20a */ 375 376 /* sipc rx */ 377 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x300 */ 378 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x301 */ 379 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x302 */ 380 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x303 */ 381 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x304 */ 382 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x305 */ 383 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x306 */ 384 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x307 */ 385 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x308 */ 386 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x309 */ 387 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x30a */ 388 389 /* dma rx */ 390 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x400 */ 391 DMA_RX_DIF_APP_ERR, /* 0x401 */ 392 DMA_RX_DIF_RPP_ERR, /* 0x402 */ 393 DMA_RX_DATA_SGL_OVERFLOW, /* 0x403 */ 394 DMA_RX_DIF_SGL_OVERFLOW, /* 0x404 */ 395 DMA_RX_DATA_LEN_OVERFLOW, /* 0x405 */ 396 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x406 */ 397 DMA_RX_DATA_OFFSET_ERR, /* 0x407 */ 398 RESERVED10, /* 0x408 */ 399 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x409 */ 400 DMA_RX_RESP_BUF_OVERFLOW, /* 0x40a */ 401 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x40b */ 402 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x40c */ 403 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x40d */ 404 DMA_RX_PIO_DATA_LEN_ERR, /* 0x40e */ 405 DMA_RX_RDSETUP_STATUS_ERR, /* 0x40f */ 406 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x410 */ 407 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x411 */ 408 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x412 */ 409 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x413 */ 410 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x414 */ 411 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x415 */ 412 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x416 */ 413 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x417 */ 414 DMA_RX_RAM_ECC_ERR, /* 0x418 */ 415 DMA_RX_UNKNOWN_FRM_ERR, /* 0x419 */ 416 }; 417 418 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096 419 420 #define DIR_NO_DATA 0 421 #define DIR_TO_INI 1 422 #define DIR_TO_DEVICE 2 423 #define DIR_RESERVED 3 424 425 #define SATA_PROTOCOL_NONDATA 0x1 426 #define SATA_PROTOCOL_PIO 0x2 427 #define SATA_PROTOCOL_DMA 0x4 428 #define SATA_PROTOCOL_FPDMA 0x8 429 #define SATA_PROTOCOL_ATAPI 0x10 430 431 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 432 { 433 void __iomem *regs = hisi_hba->regs + off; 434 435 return readl(regs); 436 } 437 438 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 439 { 440 void __iomem *regs = hisi_hba->regs + off; 441 442 return readl_relaxed(regs); 443 } 444 445 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 446 { 447 void __iomem *regs = hisi_hba->regs + off; 448 449 writel(val, regs); 450 } 451 452 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 453 u32 off, u32 val) 454 { 455 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 456 457 writel(val, regs); 458 } 459 460 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 461 int phy_no, u32 off) 462 { 463 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 464 465 return readl(regs); 466 } 467 468 /* This function needs to be protected from pre-emption. */ 469 static int 470 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx, 471 struct domain_device *device) 472 { 473 unsigned int index = 0; 474 void *bitmap = hisi_hba->slot_index_tags; 475 int sata_dev = dev_is_sata(device); 476 477 while (1) { 478 index = find_next_zero_bit(bitmap, hisi_hba->slot_index_count, 479 index); 480 if (index >= hisi_hba->slot_index_count) 481 return -SAS_QUEUE_FULL; 482 /* 483 * SAS IPTT bit0 should be 1 484 */ 485 if (sata_dev || (index & 1)) 486 break; 487 index++; 488 } 489 490 set_bit(index, bitmap); 491 *slot_idx = index; 492 return 0; 493 } 494 495 static struct 496 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device) 497 { 498 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha; 499 struct hisi_sas_device *sas_dev = NULL; 500 int i, sata_dev = dev_is_sata(device); 501 502 spin_lock(&hisi_hba->lock); 503 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) { 504 /* 505 * SATA device id bit0 should be 0 506 */ 507 if (sata_dev && (i & 1)) 508 continue; 509 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) { 510 hisi_hba->devices[i].device_id = i; 511 sas_dev = &hisi_hba->devices[i]; 512 sas_dev->dev_status = HISI_SAS_DEV_NORMAL; 513 sas_dev->dev_type = device->dev_type; 514 sas_dev->hisi_hba = hisi_hba; 515 sas_dev->sas_device = device; 516 break; 517 } 518 } 519 spin_unlock(&hisi_hba->lock); 520 521 return sas_dev; 522 } 523 524 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 525 { 526 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 527 528 cfg &= ~PHY_CFG_DC_OPT_MSK; 529 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 530 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 531 } 532 533 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 534 { 535 struct sas_identify_frame identify_frame; 536 u32 *identify_buffer; 537 538 memset(&identify_frame, 0, sizeof(identify_frame)); 539 identify_frame.dev_type = SAS_END_DEVICE; 540 identify_frame.frame_type = 0; 541 identify_frame._un1 = 1; 542 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 543 identify_frame.target_bits = SAS_PROTOCOL_NONE; 544 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 545 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 546 identify_frame.phy_id = phy_no; 547 identify_buffer = (u32 *)(&identify_frame); 548 549 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 550 __swab32(identify_buffer[0])); 551 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 552 identify_buffer[2]); 553 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 554 identify_buffer[1]); 555 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 556 identify_buffer[4]); 557 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 558 identify_buffer[3]); 559 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 560 __swab32(identify_buffer[5])); 561 } 562 563 static void init_id_frame_v2_hw(struct hisi_hba *hisi_hba) 564 { 565 int i; 566 567 for (i = 0; i < hisi_hba->n_phy; i++) 568 config_id_frame_v2_hw(hisi_hba, i); 569 } 570 571 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba, 572 struct hisi_sas_device *sas_dev) 573 { 574 struct domain_device *device = sas_dev->sas_device; 575 struct device *dev = &hisi_hba->pdev->dev; 576 u64 qw0, device_id = sas_dev->device_id; 577 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 578 struct domain_device *parent_dev = device->parent; 579 struct hisi_sas_port *port = device->port->lldd_port; 580 581 memset(itct, 0, sizeof(*itct)); 582 583 /* qw0 */ 584 qw0 = 0; 585 switch (sas_dev->dev_type) { 586 case SAS_END_DEVICE: 587 case SAS_EDGE_EXPANDER_DEVICE: 588 case SAS_FANOUT_EXPANDER_DEVICE: 589 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 590 break; 591 case SAS_SATA_DEV: 592 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 593 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 594 else 595 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 596 break; 597 default: 598 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 599 sas_dev->dev_type); 600 } 601 602 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 603 (device->linkrate << ITCT_HDR_MCR_OFF) | 604 (1 << ITCT_HDR_VLN_OFF) | 605 (port->id << ITCT_HDR_PORT_ID_OFF)); 606 itct->qw0 = cpu_to_le64(qw0); 607 608 /* qw1 */ 609 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 610 itct->sas_addr = __swab64(itct->sas_addr); 611 612 /* qw2 */ 613 if (!dev_is_sata(device)) 614 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) | 615 (0x1ULL << ITCT_HDR_BITLT_OFF) | 616 (0x32ULL << ITCT_HDR_MCTLT_OFF) | 617 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 618 } 619 620 static void free_device_v2_hw(struct hisi_hba *hisi_hba, 621 struct hisi_sas_device *sas_dev) 622 { 623 u64 qw0, dev_id = sas_dev->device_id; 624 struct device *dev = &hisi_hba->pdev->dev; 625 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 626 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 627 int i; 628 629 /* clear the itct interrupt state */ 630 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 631 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 632 ENT_INT_SRC3_ITC_INT_MSK); 633 634 /* clear the itct int*/ 635 for (i = 0; i < 2; i++) { 636 /* clear the itct table*/ 637 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 638 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 639 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 640 641 udelay(10); 642 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 643 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) { 644 dev_dbg(dev, "got clear ITCT done interrupt\n"); 645 646 /* invalid the itct state*/ 647 qw0 = cpu_to_le64(itct->qw0); 648 qw0 &= ~(1 << ITCT_HDR_VALID_OFF); 649 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 650 ENT_INT_SRC3_ITC_INT_MSK); 651 hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED; 652 hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL; 653 654 /* clear the itct */ 655 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 656 dev_dbg(dev, "clear ITCT ok\n"); 657 break; 658 } 659 } 660 } 661 662 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba) 663 { 664 int i, reset_val; 665 u32 val; 666 unsigned long end_time; 667 struct device *dev = &hisi_hba->pdev->dev; 668 669 /* The mask needs to be set depending on the number of phys */ 670 if (hisi_hba->n_phy == 9) 671 reset_val = 0x1fffff; 672 else 673 reset_val = 0x7ffff; 674 675 /* Disable all of the DQ */ 676 for (i = 0; i < HISI_SAS_MAX_QUEUES; i++) 677 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 678 679 /* Disable all of the PHYs */ 680 for (i = 0; i < hisi_hba->n_phy; i++) { 681 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG); 682 683 phy_cfg &= ~PHY_CTRL_RESET_MSK; 684 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg); 685 } 686 udelay(50); 687 688 /* Ensure DMA tx & rx idle */ 689 for (i = 0; i < hisi_hba->n_phy; i++) { 690 u32 dma_tx_status, dma_rx_status; 691 692 end_time = jiffies + msecs_to_jiffies(1000); 693 694 while (1) { 695 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i, 696 DMA_TX_STATUS); 697 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i, 698 DMA_RX_STATUS); 699 700 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) && 701 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK)) 702 break; 703 704 msleep(20); 705 if (time_after(jiffies, end_time)) 706 return -EIO; 707 } 708 } 709 710 /* Ensure axi bus idle */ 711 end_time = jiffies + msecs_to_jiffies(1000); 712 while (1) { 713 u32 axi_status = 714 hisi_sas_read32(hisi_hba, AXI_CFG); 715 716 if (axi_status == 0) 717 break; 718 719 msleep(20); 720 if (time_after(jiffies, end_time)) 721 return -EIO; 722 } 723 724 /* reset and disable clock*/ 725 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg, 726 reset_val); 727 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4, 728 reset_val); 729 msleep(1); 730 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 731 if (reset_val != (val & reset_val)) { 732 dev_err(dev, "SAS reset fail.\n"); 733 return -EIO; 734 } 735 736 /* De-reset and enable clock*/ 737 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4, 738 reset_val); 739 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg, 740 reset_val); 741 msleep(1); 742 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, 743 &val); 744 if (val & reset_val) { 745 dev_err(dev, "SAS de-reset fail.\n"); 746 return -EIO; 747 } 748 749 return 0; 750 } 751 752 static void init_reg_v2_hw(struct hisi_hba *hisi_hba) 753 { 754 struct device *dev = &hisi_hba->pdev->dev; 755 struct device_node *np = dev->of_node; 756 int i; 757 758 /* Global registers init */ 759 760 /* Deal with am-max-transmissions quirk */ 761 if (of_get_property(np, "hip06-sas-v2-quirk-amt", NULL)) { 762 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020); 763 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS, 764 0x2020); 765 } /* Else, use defaults -> do nothing */ 766 767 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 768 (u32)((1ULL << hisi_hba->queue_count) - 1)); 769 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000); 770 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000); 771 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 772 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF); 773 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1); 774 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4); 775 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32); 776 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1); 777 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 778 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1); 779 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1); 780 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 781 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 782 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 783 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1); 784 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1); 785 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0); 786 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 787 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 788 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 789 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe); 790 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe); 791 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe); 792 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0); 793 for (i = 0; i < hisi_hba->queue_count; i++) 794 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 795 796 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1); 797 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 798 799 for (i = 0; i < hisi_hba->n_phy; i++) { 800 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855); 801 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908); 802 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); 803 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10); 804 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 805 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 806 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 807 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 808 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 809 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff); 810 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc); 811 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 812 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 813 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 814 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 815 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 816 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0); 817 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0); 818 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694); 819 } 820 821 for (i = 0; i < hisi_hba->queue_count; i++) { 822 /* Delivery queue */ 823 hisi_sas_write32(hisi_hba, 824 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 825 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 826 827 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 828 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 829 830 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 831 HISI_SAS_QUEUE_SLOTS); 832 833 /* Completion queue */ 834 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 835 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 836 837 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 838 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 839 840 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 841 HISI_SAS_QUEUE_SLOTS); 842 } 843 844 /* itct */ 845 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 846 lower_32_bits(hisi_hba->itct_dma)); 847 848 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 849 upper_32_bits(hisi_hba->itct_dma)); 850 851 /* iost */ 852 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 853 lower_32_bits(hisi_hba->iost_dma)); 854 855 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 856 upper_32_bits(hisi_hba->iost_dma)); 857 858 /* breakpoint */ 859 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 860 lower_32_bits(hisi_hba->breakpoint_dma)); 861 862 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 863 upper_32_bits(hisi_hba->breakpoint_dma)); 864 865 /* SATA broken msg */ 866 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 867 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 868 869 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 870 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 871 872 /* SATA initial fis */ 873 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 874 lower_32_bits(hisi_hba->initial_fis_dma)); 875 876 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 877 upper_32_bits(hisi_hba->initial_fis_dma)); 878 } 879 880 static int hw_init_v2_hw(struct hisi_hba *hisi_hba) 881 { 882 struct device *dev = &hisi_hba->pdev->dev; 883 int rc; 884 885 rc = reset_hw_v2_hw(hisi_hba); 886 if (rc) { 887 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 888 return rc; 889 } 890 891 msleep(100); 892 init_reg_v2_hw(hisi_hba); 893 894 init_id_frame_v2_hw(hisi_hba); 895 896 return 0; 897 } 898 899 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 900 { 901 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 902 903 cfg |= PHY_CFG_ENA_MSK; 904 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 905 } 906 907 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 908 { 909 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 910 911 cfg &= ~PHY_CFG_ENA_MSK; 912 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 913 } 914 915 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 916 { 917 config_id_frame_v2_hw(hisi_hba, phy_no); 918 config_phy_opt_mode_v2_hw(hisi_hba, phy_no); 919 enable_phy_v2_hw(hisi_hba, phy_no); 920 } 921 922 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 923 { 924 disable_phy_v2_hw(hisi_hba, phy_no); 925 } 926 927 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 928 { 929 stop_phy_v2_hw(hisi_hba, phy_no); 930 msleep(100); 931 start_phy_v2_hw(hisi_hba, phy_no); 932 } 933 934 static void start_phys_v2_hw(unsigned long data) 935 { 936 struct hisi_hba *hisi_hba = (struct hisi_hba *)data; 937 int i; 938 939 for (i = 0; i < hisi_hba->n_phy; i++) 940 start_phy_v2_hw(hisi_hba, i); 941 } 942 943 static void phys_init_v2_hw(struct hisi_hba *hisi_hba) 944 { 945 int i; 946 struct timer_list *timer = &hisi_hba->timer; 947 948 for (i = 0; i < hisi_hba->n_phy; i++) { 949 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a); 950 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK); 951 } 952 953 setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba); 954 mod_timer(timer, jiffies + HZ); 955 } 956 957 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 958 { 959 u32 sl_control; 960 961 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 962 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 963 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 964 msleep(1); 965 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 966 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 967 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 968 } 969 970 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id) 971 { 972 int i, bitmap = 0; 973 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 974 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 975 976 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++) 977 if (phy_state & 1 << i) 978 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 979 bitmap |= 1 << i; 980 981 if (hisi_hba->n_phy == 9) { 982 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 983 984 if (phy_state & 1 << 8) 985 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 986 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id) 987 bitmap |= 1 << 9; 988 } 989 990 return bitmap; 991 } 992 993 /** 994 * This function allocates across all queues to load balance. 995 * Slots are allocated from queues in a round-robin fashion. 996 * 997 * The callpath to this function and upto writing the write 998 * queue pointer should be safe from interruption. 999 */ 1000 static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s) 1001 { 1002 struct device *dev = &hisi_hba->pdev->dev; 1003 u32 r, w; 1004 int queue = hisi_hba->queue; 1005 1006 while (1) { 1007 w = hisi_sas_read32_relaxed(hisi_hba, 1008 DLVRY_Q_0_WR_PTR + (queue * 0x14)); 1009 r = hisi_sas_read32_relaxed(hisi_hba, 1010 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 1011 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 1012 queue = (queue + 1) % hisi_hba->queue_count; 1013 if (queue == hisi_hba->queue) { 1014 dev_warn(dev, "could not find free slot\n"); 1015 return -EAGAIN; 1016 } 1017 continue; 1018 } 1019 break; 1020 } 1021 hisi_hba->queue = (queue + 1) % hisi_hba->queue_count; 1022 *q = queue; 1023 *s = w; 1024 return 0; 1025 } 1026 1027 static void start_delivery_v2_hw(struct hisi_hba *hisi_hba) 1028 { 1029 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue; 1030 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot; 1031 1032 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), 1033 ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS); 1034 } 1035 1036 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba, 1037 struct hisi_sas_slot *slot, 1038 struct hisi_sas_cmd_hdr *hdr, 1039 struct scatterlist *scatter, 1040 int n_elem) 1041 { 1042 struct device *dev = &hisi_hba->pdev->dev; 1043 struct scatterlist *sg; 1044 int i; 1045 1046 if (n_elem > HISI_SAS_SGE_PAGE_CNT) { 1047 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT", 1048 n_elem); 1049 return -EINVAL; 1050 } 1051 1052 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC, 1053 &slot->sge_page_dma); 1054 if (!slot->sge_page) 1055 return -ENOMEM; 1056 1057 for_each_sg(scatter, sg, n_elem, i) { 1058 struct hisi_sas_sge *entry = &slot->sge_page->sge[i]; 1059 1060 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1061 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 1062 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1063 entry->data_off = 0; 1064 } 1065 1066 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma); 1067 1068 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 1069 1070 return 0; 1071 } 1072 1073 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba, 1074 struct hisi_sas_slot *slot) 1075 { 1076 struct sas_task *task = slot->task; 1077 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1078 struct domain_device *device = task->dev; 1079 struct device *dev = &hisi_hba->pdev->dev; 1080 struct hisi_sas_port *port = slot->port; 1081 struct scatterlist *sg_req, *sg_resp; 1082 struct hisi_sas_device *sas_dev = device->lldd_dev; 1083 dma_addr_t req_dma_addr; 1084 unsigned int req_len, resp_len; 1085 int elem, rc; 1086 1087 /* 1088 * DMA-map SMP request, response buffers 1089 */ 1090 /* req */ 1091 sg_req = &task->smp_task.smp_req; 1092 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE); 1093 if (!elem) 1094 return -ENOMEM; 1095 req_len = sg_dma_len(sg_req); 1096 req_dma_addr = sg_dma_address(sg_req); 1097 1098 /* resp */ 1099 sg_resp = &task->smp_task.smp_resp; 1100 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE); 1101 if (!elem) { 1102 rc = -ENOMEM; 1103 goto err_out_req; 1104 } 1105 resp_len = sg_dma_len(sg_resp); 1106 if ((req_len & 0x3) || (resp_len & 0x3)) { 1107 rc = -EINVAL; 1108 goto err_out_resp; 1109 } 1110 1111 /* create header */ 1112 /* dw0 */ 1113 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1114 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1115 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1116 1117 /* map itct entry */ 1118 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1119 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1120 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1121 1122 /* dw2 */ 1123 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1124 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1125 CMD_HDR_MRFL_OFF)); 1126 1127 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1128 1129 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1130 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1131 1132 return 0; 1133 1134 err_out_resp: 1135 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1, 1136 DMA_FROM_DEVICE); 1137 err_out_req: 1138 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1, 1139 DMA_TO_DEVICE); 1140 return rc; 1141 } 1142 1143 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba, 1144 struct hisi_sas_slot *slot, int is_tmf, 1145 struct hisi_sas_tmf_task *tmf) 1146 { 1147 struct sas_task *task = slot->task; 1148 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1149 struct domain_device *device = task->dev; 1150 struct hisi_sas_device *sas_dev = device->lldd_dev; 1151 struct hisi_sas_port *port = slot->port; 1152 struct sas_ssp_task *ssp_task = &task->ssp_task; 1153 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1154 int has_data = 0, rc, priority = is_tmf; 1155 u8 *buf_cmd; 1156 u32 dw1 = 0, dw2 = 0; 1157 1158 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1159 (2 << CMD_HDR_TLR_CTRL_OFF) | 1160 (port->id << CMD_HDR_PORT_OFF) | 1161 (priority << CMD_HDR_PRIORITY_OFF) | 1162 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1163 1164 dw1 = 1 << CMD_HDR_VDTL_OFF; 1165 if (is_tmf) { 1166 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1167 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1168 } else { 1169 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1170 switch (scsi_cmnd->sc_data_direction) { 1171 case DMA_TO_DEVICE: 1172 has_data = 1; 1173 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1174 break; 1175 case DMA_FROM_DEVICE: 1176 has_data = 1; 1177 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1178 break; 1179 default: 1180 dw1 &= ~CMD_HDR_DIR_MSK; 1181 } 1182 } 1183 1184 /* map itct entry */ 1185 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1186 hdr->dw1 = cpu_to_le32(dw1); 1187 1188 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1189 + 3) / 4) << CMD_HDR_CFL_OFF) | 1190 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1191 (2 << CMD_HDR_SG_MOD_OFF); 1192 hdr->dw2 = cpu_to_le32(dw2); 1193 1194 hdr->transfer_tags = cpu_to_le32(slot->idx); 1195 1196 if (has_data) { 1197 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter, 1198 slot->n_elem); 1199 if (rc) 1200 return rc; 1201 } 1202 1203 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1204 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); 1205 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1206 1207 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr); 1208 1209 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1210 if (!is_tmf) { 1211 buf_cmd[9] = task->ssp_task.task_attr | 1212 (task->ssp_task.task_prio << 3); 1213 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd, 1214 task->ssp_task.cmd->cmd_len); 1215 } else { 1216 buf_cmd[10] = tmf->tmf; 1217 switch (tmf->tmf) { 1218 case TMF_ABORT_TASK: 1219 case TMF_QUERY_TASK: 1220 buf_cmd[12] = 1221 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1222 buf_cmd[13] = 1223 tmf->tag_of_task_to_be_managed & 0xff; 1224 break; 1225 default: 1226 break; 1227 } 1228 } 1229 1230 return 0; 1231 } 1232 1233 static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1234 struct hisi_sas_slot *slot) 1235 { 1236 struct task_status_struct *ts = &task->task_status; 1237 struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf; 1238 struct dev_to_host_fis *d2h = slot->status_buffer + 1239 sizeof(struct hisi_sas_err_record); 1240 1241 resp->frame_len = sizeof(struct dev_to_host_fis); 1242 memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis)); 1243 1244 ts->buf_valid_size = sizeof(*resp); 1245 } 1246 1247 /* by default, task resp is complete */ 1248 static void slot_err_v2_hw(struct hisi_hba *hisi_hba, 1249 struct sas_task *task, 1250 struct hisi_sas_slot *slot) 1251 { 1252 struct task_status_struct *ts = &task->task_status; 1253 struct hisi_sas_err_record_v2 *err_record = slot->status_buffer; 1254 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type); 1255 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type); 1256 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type); 1257 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type); 1258 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type); 1259 int error = -1; 1260 1261 if (dma_rx_err_type) { 1262 error = ffs(dma_rx_err_type) 1263 - 1 + DMA_RX_ERR_BASE; 1264 } else if (sipc_rx_err_type) { 1265 error = ffs(sipc_rx_err_type) 1266 - 1 + SIPC_RX_ERR_BASE; 1267 } else if (dma_tx_err_type) { 1268 error = ffs(dma_tx_err_type) 1269 - 1 + DMA_TX_ERR_BASE; 1270 } else if (trans_rx_fail_type) { 1271 error = ffs(trans_rx_fail_type) 1272 - 1 + TRANS_RX_FAIL_BASE; 1273 } else if (trans_tx_fail_type) { 1274 error = ffs(trans_tx_fail_type) 1275 - 1 + TRANS_TX_FAIL_BASE; 1276 } 1277 1278 switch (task->task_proto) { 1279 case SAS_PROTOCOL_SSP: 1280 { 1281 switch (error) { 1282 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION: 1283 { 1284 ts->stat = SAS_OPEN_REJECT; 1285 ts->open_rej_reason = SAS_OREJ_NO_DEST; 1286 break; 1287 } 1288 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED: 1289 { 1290 ts->stat = SAS_OPEN_REJECT; 1291 ts->open_rej_reason = SAS_OREJ_PATH_BLOCKED; 1292 break; 1293 } 1294 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED: 1295 { 1296 ts->stat = SAS_OPEN_REJECT; 1297 ts->open_rej_reason = SAS_OREJ_EPROTO; 1298 break; 1299 } 1300 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED: 1301 { 1302 ts->stat = SAS_OPEN_REJECT; 1303 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1304 break; 1305 } 1306 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION: 1307 { 1308 ts->stat = SAS_OPEN_REJECT; 1309 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1310 break; 1311 } 1312 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD: 1313 { 1314 ts->stat = SAS_OPEN_REJECT; 1315 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1316 break; 1317 } 1318 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION: 1319 { 1320 ts->stat = SAS_OPEN_REJECT; 1321 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1322 break; 1323 } 1324 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION: 1325 { 1326 ts->stat = SAS_OPEN_REJECT; 1327 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1328 break; 1329 } 1330 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER: 1331 { 1332 /* not sure */ 1333 ts->stat = SAS_DEV_NO_RESPONSE; 1334 break; 1335 } 1336 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE: 1337 { 1338 ts->stat = SAS_PHY_DOWN; 1339 break; 1340 } 1341 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT: 1342 { 1343 ts->stat = SAS_OPEN_TO; 1344 break; 1345 } 1346 case DMA_RX_DATA_LEN_OVERFLOW: 1347 { 1348 ts->stat = SAS_DATA_OVERRUN; 1349 ts->residual = 0; 1350 break; 1351 } 1352 case DMA_RX_DATA_LEN_UNDERFLOW: 1353 case SIPC_RX_DATA_UNDERFLOW_ERR: 1354 { 1355 ts->residual = trans_tx_fail_type; 1356 ts->stat = SAS_DATA_UNDERRUN; 1357 break; 1358 } 1359 case TRANS_TX_ERR_FRAME_TXED: 1360 { 1361 /* This will request a retry */ 1362 ts->stat = SAS_QUEUE_FULL; 1363 slot->abort = 1; 1364 break; 1365 } 1366 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS: 1367 case TRANS_TX_ERR_PHY_NOT_ENABLE: 1368 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER: 1369 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT: 1370 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED: 1371 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT: 1372 case TRANS_TX_ERR_WITH_BREAK_REQUEST: 1373 case TRANS_TX_ERR_WITH_BREAK_RECEVIED: 1374 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT: 1375 case TRANS_TX_ERR_WITH_CLOSE_NORMAL: 1376 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1377 case TRANS_TX_ERR_WITH_CLOSE_COMINIT: 1378 case TRANS_TX_ERR_WITH_NAK_RECEVIED: 1379 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT: 1380 case TRANS_TX_ERR_WITH_IPTT_CONFLICT: 1381 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT: 1382 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR: 1383 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR: 1384 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM: 1385 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT: 1386 case TRANS_RX_ERR_WITH_BREAK_REQUEST: 1387 case TRANS_RX_ERR_WITH_BREAK_RECEVIED: 1388 case TRANS_RX_ERR_WITH_CLOSE_NORMAL: 1389 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1390 case TRANS_RX_ERR_WITH_CLOSE_COMINIT: 1391 case TRANS_RX_ERR_WITH_DATA_LEN0: 1392 case TRANS_RX_ERR_WITH_BAD_HASH: 1393 case TRANS_RX_XRDY_WLEN_ZERO_ERR: 1394 case TRANS_RX_SSP_FRM_LEN_ERR: 1395 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE: 1396 case DMA_TX_UNEXP_XFER_ERR: 1397 case DMA_TX_UNEXP_RETRANS_ERR: 1398 case DMA_TX_XFER_LEN_OVERFLOW: 1399 case DMA_TX_XFER_OFFSET_ERR: 1400 case DMA_RX_DATA_OFFSET_ERR: 1401 case DMA_RX_UNEXP_NORM_RESP_ERR: 1402 case DMA_RX_UNEXP_RDFRAME_ERR: 1403 case DMA_RX_UNKNOWN_FRM_ERR: 1404 { 1405 ts->stat = SAS_OPEN_REJECT; 1406 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1407 break; 1408 } 1409 default: 1410 break; 1411 } 1412 } 1413 break; 1414 case SAS_PROTOCOL_SMP: 1415 ts->stat = SAM_STAT_CHECK_CONDITION; 1416 break; 1417 1418 case SAS_PROTOCOL_SATA: 1419 case SAS_PROTOCOL_STP: 1420 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1421 { 1422 switch (error) { 1423 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER: 1424 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED: 1425 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION: 1426 { 1427 ts->resp = SAS_TASK_UNDELIVERED; 1428 ts->stat = SAS_DEV_NO_RESPONSE; 1429 break; 1430 } 1431 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED: 1432 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED: 1433 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION: 1434 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD: 1435 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION: 1436 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION: 1437 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY: 1438 { 1439 ts->stat = SAS_OPEN_REJECT; 1440 break; 1441 } 1442 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT: 1443 { 1444 ts->stat = SAS_OPEN_TO; 1445 break; 1446 } 1447 case DMA_RX_DATA_LEN_OVERFLOW: 1448 { 1449 ts->stat = SAS_DATA_OVERRUN; 1450 break; 1451 } 1452 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS: 1453 case TRANS_TX_ERR_PHY_NOT_ENABLE: 1454 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER: 1455 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT: 1456 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED: 1457 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT: 1458 case TRANS_TX_ERR_WITH_BREAK_REQUEST: 1459 case TRANS_TX_ERR_WITH_BREAK_RECEVIED: 1460 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT: 1461 case TRANS_TX_ERR_WITH_CLOSE_NORMAL: 1462 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1463 case TRANS_TX_ERR_WITH_CLOSE_COMINIT: 1464 case TRANS_TX_ERR_WITH_NAK_RECEVIED: 1465 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT: 1466 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT: 1467 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT: 1468 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR: 1469 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM: 1470 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR: 1471 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR: 1472 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN: 1473 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP: 1474 case TRANS_RX_ERR_WITH_CLOSE_NORMAL: 1475 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE: 1476 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1477 case TRANS_RX_ERR_WITH_CLOSE_COMINIT: 1478 case TRANS_RX_ERR_WITH_DATA_LEN0: 1479 case TRANS_RX_ERR_WITH_BAD_HASH: 1480 case TRANS_RX_XRDY_WLEN_ZERO_ERR: 1481 case TRANS_RX_SSP_FRM_LEN_ERR: 1482 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD: 1483 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR: 1484 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR: 1485 case SIPC_RX_WRSETUP_LEN_ODD_ERR: 1486 case SIPC_RX_WRSETUP_LEN_ZERO_ERR: 1487 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR: 1488 case SIPC_RX_SATA_UNEXP_FIS_ERR: 1489 case DMA_RX_SATA_FRAME_TYPE_ERR: 1490 case DMA_RX_UNEXP_RDFRAME_ERR: 1491 case DMA_RX_PIO_DATA_LEN_ERR: 1492 case DMA_RX_RDSETUP_STATUS_ERR: 1493 case DMA_RX_RDSETUP_STATUS_DRQ_ERR: 1494 case DMA_RX_RDSETUP_STATUS_BSY_ERR: 1495 case DMA_RX_RDSETUP_LEN_ODD_ERR: 1496 case DMA_RX_RDSETUP_LEN_ZERO_ERR: 1497 case DMA_RX_RDSETUP_LEN_OVER_ERR: 1498 case DMA_RX_RDSETUP_OFFSET_ERR: 1499 case DMA_RX_RDSETUP_ACTIVE_ERR: 1500 case DMA_RX_RDSETUP_ESTATUS_ERR: 1501 case DMA_RX_UNKNOWN_FRM_ERR: 1502 { 1503 ts->stat = SAS_OPEN_REJECT; 1504 break; 1505 } 1506 default: 1507 { 1508 ts->stat = SAS_PROTO_RESPONSE; 1509 break; 1510 } 1511 } 1512 sata_done_v2_hw(hisi_hba, task, slot); 1513 } 1514 break; 1515 default: 1516 break; 1517 } 1518 } 1519 1520 static int 1521 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot, 1522 int abort) 1523 { 1524 struct sas_task *task = slot->task; 1525 struct hisi_sas_device *sas_dev; 1526 struct device *dev = &hisi_hba->pdev->dev; 1527 struct task_status_struct *ts; 1528 struct domain_device *device; 1529 enum exec_status sts; 1530 struct hisi_sas_complete_v2_hdr *complete_queue = 1531 hisi_hba->complete_hdr[slot->cmplt_queue]; 1532 struct hisi_sas_complete_v2_hdr *complete_hdr = 1533 &complete_queue[slot->cmplt_queue_slot]; 1534 1535 if (unlikely(!task || !task->lldd_task || !task->dev)) 1536 return -EINVAL; 1537 1538 ts = &task->task_status; 1539 device = task->dev; 1540 sas_dev = device->lldd_dev; 1541 1542 task->task_state_flags &= 1543 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1544 task->task_state_flags |= SAS_TASK_STATE_DONE; 1545 1546 memset(ts, 0, sizeof(*ts)); 1547 ts->resp = SAS_TASK_COMPLETE; 1548 1549 if (unlikely(!sas_dev || abort)) { 1550 if (!sas_dev) 1551 dev_dbg(dev, "slot complete: port has not device\n"); 1552 ts->stat = SAS_PHY_DOWN; 1553 goto out; 1554 } 1555 1556 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) && 1557 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) { 1558 1559 slot_err_v2_hw(hisi_hba, task, slot); 1560 if (unlikely(slot->abort)) { 1561 queue_work(hisi_hba->wq, &slot->abort_slot); 1562 /* immediately return and do not complete */ 1563 return ts->stat; 1564 } 1565 goto out; 1566 } 1567 1568 switch (task->task_proto) { 1569 case SAS_PROTOCOL_SSP: 1570 { 1571 struct ssp_response_iu *iu = slot->status_buffer + 1572 sizeof(struct hisi_sas_err_record); 1573 1574 sas_ssp_task_response(dev, task, iu); 1575 break; 1576 } 1577 case SAS_PROTOCOL_SMP: 1578 { 1579 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1580 void *to; 1581 1582 ts->stat = SAM_STAT_GOOD; 1583 to = kmap_atomic(sg_page(sg_resp)); 1584 1585 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1586 DMA_FROM_DEVICE); 1587 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1588 DMA_TO_DEVICE); 1589 memcpy(to + sg_resp->offset, 1590 slot->status_buffer + 1591 sizeof(struct hisi_sas_err_record), 1592 sg_dma_len(sg_resp)); 1593 kunmap_atomic(to); 1594 break; 1595 } 1596 case SAS_PROTOCOL_SATA: 1597 case SAS_PROTOCOL_STP: 1598 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1599 { 1600 ts->stat = SAM_STAT_GOOD; 1601 sata_done_v2_hw(hisi_hba, task, slot); 1602 break; 1603 } 1604 default: 1605 ts->stat = SAM_STAT_CHECK_CONDITION; 1606 break; 1607 } 1608 1609 if (!slot->port->port_attached) { 1610 dev_err(dev, "slot complete: port %d has removed\n", 1611 slot->port->sas_port.id); 1612 ts->stat = SAS_PHY_DOWN; 1613 } 1614 1615 out: 1616 if (sas_dev && sas_dev->running_req) 1617 sas_dev->running_req--; 1618 1619 hisi_sas_slot_task_free(hisi_hba, task, slot); 1620 sts = ts->stat; 1621 1622 if (task->task_done) 1623 task->task_done(task); 1624 1625 return sts; 1626 } 1627 1628 static u8 get_ata_protocol(u8 cmd, int direction) 1629 { 1630 switch (cmd) { 1631 case ATA_CMD_FPDMA_WRITE: 1632 case ATA_CMD_FPDMA_READ: 1633 case ATA_CMD_FPDMA_RECV: 1634 case ATA_CMD_FPDMA_SEND: 1635 case ATA_CMD_NCQ_NON_DATA: 1636 return SATA_PROTOCOL_FPDMA; 1637 1638 case ATA_CMD_ID_ATA: 1639 case ATA_CMD_PMP_READ: 1640 case ATA_CMD_READ_LOG_EXT: 1641 case ATA_CMD_PIO_READ: 1642 case ATA_CMD_PIO_READ_EXT: 1643 case ATA_CMD_PMP_WRITE: 1644 case ATA_CMD_WRITE_LOG_EXT: 1645 case ATA_CMD_PIO_WRITE: 1646 case ATA_CMD_PIO_WRITE_EXT: 1647 return SATA_PROTOCOL_PIO; 1648 1649 case ATA_CMD_READ: 1650 case ATA_CMD_READ_EXT: 1651 case ATA_CMD_READ_LOG_DMA_EXT: 1652 case ATA_CMD_WRITE: 1653 case ATA_CMD_WRITE_EXT: 1654 case ATA_CMD_WRITE_QUEUED: 1655 case ATA_CMD_WRITE_LOG_DMA_EXT: 1656 return SATA_PROTOCOL_DMA; 1657 1658 case ATA_CMD_DOWNLOAD_MICRO: 1659 case ATA_CMD_DEV_RESET: 1660 case ATA_CMD_CHK_POWER: 1661 case ATA_CMD_FLUSH: 1662 case ATA_CMD_FLUSH_EXT: 1663 case ATA_CMD_VERIFY: 1664 case ATA_CMD_VERIFY_EXT: 1665 case ATA_CMD_SET_FEATURES: 1666 case ATA_CMD_STANDBY: 1667 case ATA_CMD_STANDBYNOW1: 1668 return SATA_PROTOCOL_NONDATA; 1669 default: 1670 if (direction == DMA_NONE) 1671 return SATA_PROTOCOL_NONDATA; 1672 return SATA_PROTOCOL_PIO; 1673 } 1674 } 1675 1676 static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag) 1677 { 1678 struct ata_queued_cmd *qc = task->uldd_task; 1679 1680 if (qc) { 1681 if (qc->tf.command == ATA_CMD_FPDMA_WRITE || 1682 qc->tf.command == ATA_CMD_FPDMA_READ) { 1683 *tag = qc->tag; 1684 return 1; 1685 } 1686 } 1687 return 0; 1688 } 1689 1690 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba, 1691 struct hisi_sas_slot *slot) 1692 { 1693 struct sas_task *task = slot->task; 1694 struct domain_device *device = task->dev; 1695 struct domain_device *parent_dev = device->parent; 1696 struct hisi_sas_device *sas_dev = device->lldd_dev; 1697 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1698 struct hisi_sas_port *port = device->port->lldd_port; 1699 u8 *buf_cmd; 1700 int has_data = 0, rc = 0, hdr_tag = 0; 1701 u32 dw1 = 0, dw2 = 0; 1702 1703 /* create header */ 1704 /* dw0 */ 1705 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1706 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1707 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1708 else 1709 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1710 1711 /* dw1 */ 1712 switch (task->data_dir) { 1713 case DMA_TO_DEVICE: 1714 has_data = 1; 1715 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1716 break; 1717 case DMA_FROM_DEVICE: 1718 has_data = 1; 1719 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1720 break; 1721 default: 1722 dw1 &= ~CMD_HDR_DIR_MSK; 1723 } 1724 1725 if (0 == task->ata_task.fis.command) 1726 dw1 |= 1 << CMD_HDR_RESET_OFF; 1727 1728 dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir)) 1729 << CMD_HDR_FRAME_TYPE_OFF; 1730 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1731 hdr->dw1 = cpu_to_le32(dw1); 1732 1733 /* dw2 */ 1734 if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) { 1735 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1736 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1737 } 1738 1739 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1740 2 << CMD_HDR_SG_MOD_OFF; 1741 hdr->dw2 = cpu_to_le32(dw2); 1742 1743 /* dw3 */ 1744 hdr->transfer_tags = cpu_to_le32(slot->idx); 1745 1746 if (has_data) { 1747 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter, 1748 slot->n_elem); 1749 if (rc) 1750 return rc; 1751 } 1752 1753 1754 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1755 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); 1756 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1757 1758 buf_cmd = slot->command_table; 1759 1760 if (likely(!task->ata_task.device_control_reg_update)) 1761 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1762 /* fill in command FIS */ 1763 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1764 1765 return 0; 1766 } 1767 1768 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 1769 { 1770 int i, res = 0; 1771 u32 context, port_id, link_rate, hard_phy_linkrate; 1772 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1773 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1774 struct device *dev = &hisi_hba->pdev->dev; 1775 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1776 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; 1777 1778 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1779 1780 /* Check for SATA dev */ 1781 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1782 if (context & (1 << phy_no)) 1783 goto end; 1784 1785 if (phy_no == 8) { 1786 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 1787 1788 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 1789 PORT_STATE_PHY8_PORT_NUM_OFF; 1790 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> 1791 PORT_STATE_PHY8_CONN_RATE_OFF; 1792 } else { 1793 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1794 port_id = (port_id >> (4 * phy_no)) & 0xf; 1795 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1796 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1797 } 1798 1799 if (port_id == 0xf) { 1800 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1801 res = IRQ_NONE; 1802 goto end; 1803 } 1804 1805 for (i = 0; i < 6; i++) { 1806 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1807 RX_IDAF_DWORD0 + (i * 4)); 1808 frame_rcvd[i] = __swab32(idaf); 1809 } 1810 1811 /* Get the linkrates */ 1812 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1813 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1814 sas_phy->linkrate = link_rate; 1815 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, 1816 HARD_PHY_LINKRATE); 1817 phy->maximum_linkrate = hard_phy_linkrate & 0xf; 1818 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; 1819 1820 sas_phy->oob_mode = SAS_OOB_MODE; 1821 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE); 1822 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1823 phy->port_id = port_id; 1824 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1825 phy->phy_type |= PORT_TYPE_SAS; 1826 phy->phy_attached = 1; 1827 phy->identify.device_type = id->dev_type; 1828 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1829 if (phy->identify.device_type == SAS_END_DEVICE) 1830 phy->identify.target_port_protocols = 1831 SAS_PROTOCOL_SSP; 1832 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1833 phy->identify.target_port_protocols = 1834 SAS_PROTOCOL_SMP; 1835 queue_work(hisi_hba->wq, &phy->phyup_ws); 1836 1837 end: 1838 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1839 CHL_INT0_SL_PHY_ENABLE_MSK); 1840 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1841 1842 return res; 1843 } 1844 1845 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 1846 { 1847 int res = 0; 1848 u32 phy_cfg, phy_state; 1849 1850 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1851 1852 phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 1853 1854 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1855 1856 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1857 1858 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1859 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1860 1861 return res; 1862 } 1863 1864 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p) 1865 { 1866 struct hisi_hba *hisi_hba = p; 1867 u32 irq_msk; 1868 int phy_no = 0; 1869 irqreturn_t res = IRQ_HANDLED; 1870 1871 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) 1872 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff; 1873 while (irq_msk) { 1874 if (irq_msk & 1) { 1875 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1876 CHL_INT0); 1877 1878 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1879 /* phy up */ 1880 if (phy_up_v2_hw(phy_no, hisi_hba)) { 1881 res = IRQ_NONE; 1882 goto end; 1883 } 1884 1885 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1886 /* phy down */ 1887 if (phy_down_v2_hw(phy_no, hisi_hba)) { 1888 res = IRQ_NONE; 1889 goto end; 1890 } 1891 } 1892 irq_msk >>= 1; 1893 phy_no++; 1894 } 1895 1896 end: 1897 return res; 1898 } 1899 1900 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 1901 { 1902 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1903 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1904 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1905 unsigned long flags; 1906 1907 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1908 1909 spin_lock_irqsave(&hisi_hba->lock, flags); 1910 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1911 spin_unlock_irqrestore(&hisi_hba->lock, flags); 1912 1913 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1914 CHL_INT0_SL_RX_BCST_ACK_MSK); 1915 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1916 } 1917 1918 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) 1919 { 1920 struct hisi_hba *hisi_hba = p; 1921 struct device *dev = &hisi_hba->pdev->dev; 1922 u32 ent_msk, ent_tmp, irq_msk; 1923 int phy_no = 0; 1924 1925 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1926 ent_tmp = ent_msk; 1927 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK; 1928 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk); 1929 1930 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >> 1931 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff; 1932 1933 while (irq_msk) { 1934 if (irq_msk & (1 << phy_no)) { 1935 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 1936 CHL_INT0); 1937 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, 1938 CHL_INT1); 1939 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, 1940 CHL_INT2); 1941 1942 if (irq_value1) { 1943 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK | 1944 CHL_INT1_DMAC_TX_ECC_ERR_MSK)) 1945 panic("%s: DMAC RX/TX ecc bad error! (0x%x)", 1946 dev_name(dev), irq_value1); 1947 1948 hisi_sas_phy_write32(hisi_hba, phy_no, 1949 CHL_INT1, irq_value1); 1950 } 1951 1952 if (irq_value2) 1953 hisi_sas_phy_write32(hisi_hba, phy_no, 1954 CHL_INT2, irq_value2); 1955 1956 1957 if (irq_value0) { 1958 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK) 1959 phy_bcast_v2_hw(phy_no, hisi_hba); 1960 1961 hisi_sas_phy_write32(hisi_hba, phy_no, 1962 CHL_INT0, irq_value0 1963 & (~CHL_INT0_HOTPLUG_TOUT_MSK) 1964 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1965 & (~CHL_INT0_NOT_RDY_MSK)); 1966 } 1967 } 1968 irq_msk &= ~(1 << phy_no); 1969 phy_no++; 1970 } 1971 1972 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp); 1973 1974 return IRQ_HANDLED; 1975 } 1976 1977 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p) 1978 { 1979 struct hisi_sas_cq *cq = p; 1980 struct hisi_hba *hisi_hba = cq->hisi_hba; 1981 struct hisi_sas_slot *slot; 1982 struct hisi_sas_itct *itct; 1983 struct hisi_sas_complete_v2_hdr *complete_queue; 1984 u32 irq_value, rd_point, wr_point, dev_id; 1985 int queue = cq->id; 1986 1987 complete_queue = hisi_hba->complete_hdr[queue]; 1988 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC); 1989 1990 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1991 1992 rd_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_RD_PTR + 1993 (0x14 * queue)); 1994 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 1995 (0x14 * queue)); 1996 1997 while (rd_point != wr_point) { 1998 struct hisi_sas_complete_v2_hdr *complete_hdr; 1999 int iptt; 2000 2001 complete_hdr = &complete_queue[rd_point]; 2002 2003 /* Check for NCQ completion */ 2004 if (complete_hdr->act) { 2005 u32 act_tmp = complete_hdr->act; 2006 int ncq_tag_count = ffs(act_tmp); 2007 2008 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >> 2009 CMPLT_HDR_DEV_ID_OFF; 2010 itct = &hisi_hba->itct[dev_id]; 2011 2012 /* The NCQ tags are held in the itct header */ 2013 while (ncq_tag_count) { 2014 __le64 *ncq_tag = &itct->qw4_15[0]; 2015 2016 ncq_tag_count -= 1; 2017 iptt = (ncq_tag[ncq_tag_count / 5] 2018 >> (ncq_tag_count % 5) * 12) & 0xfff; 2019 2020 slot = &hisi_hba->slot_info[iptt]; 2021 slot->cmplt_queue_slot = rd_point; 2022 slot->cmplt_queue = queue; 2023 slot_complete_v2_hw(hisi_hba, slot, 0); 2024 2025 act_tmp &= ~(1 << ncq_tag_count); 2026 ncq_tag_count = ffs(act_tmp); 2027 } 2028 } else { 2029 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; 2030 slot = &hisi_hba->slot_info[iptt]; 2031 slot->cmplt_queue_slot = rd_point; 2032 slot->cmplt_queue = queue; 2033 slot_complete_v2_hw(hisi_hba, slot, 0); 2034 } 2035 2036 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 2037 rd_point = 0; 2038 } 2039 2040 /* update rd_point */ 2041 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 2042 return IRQ_HANDLED; 2043 } 2044 2045 static irqreturn_t sata_int_v2_hw(int irq_no, void *p) 2046 { 2047 struct hisi_sas_phy *phy = p; 2048 struct hisi_hba *hisi_hba = phy->hisi_hba; 2049 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2050 struct device *dev = &hisi_hba->pdev->dev; 2051 struct hisi_sas_initial_fis *initial_fis; 2052 struct dev_to_host_fis *fis; 2053 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate; 2054 irqreturn_t res = IRQ_HANDLED; 2055 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 2056 int phy_no, offset; 2057 2058 phy_no = sas_phy->id; 2059 initial_fis = &hisi_hba->initial_fis[phy_no]; 2060 fis = &initial_fis->fis; 2061 2062 offset = 4 * (phy_no / 4); 2063 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset); 2064 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, 2065 ent_msk | 1 << ((phy_no % 4) * 8)); 2066 2067 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset); 2068 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF * 2069 (phy_no % 4))); 2070 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4); 2071 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) { 2072 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no); 2073 res = IRQ_NONE; 2074 goto end; 2075 } 2076 2077 if (unlikely(phy_no == 8)) { 2078 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 2079 2080 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 2081 PORT_STATE_PHY8_PORT_NUM_OFF; 2082 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> 2083 PORT_STATE_PHY8_CONN_RATE_OFF; 2084 } else { 2085 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 2086 port_id = (port_id >> (4 * phy_no)) & 0xf; 2087 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 2088 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 2089 } 2090 2091 if (port_id == 0xf) { 2092 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no); 2093 res = IRQ_NONE; 2094 goto end; 2095 } 2096 2097 sas_phy->linkrate = link_rate; 2098 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, 2099 HARD_PHY_LINKRATE); 2100 phy->maximum_linkrate = hard_phy_linkrate & 0xf; 2101 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; 2102 2103 sas_phy->oob_mode = SATA_OOB_MODE; 2104 /* Make up some unique SAS address */ 2105 attached_sas_addr[0] = 0x50; 2106 attached_sas_addr[7] = phy_no; 2107 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE); 2108 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis)); 2109 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate); 2110 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 2111 phy->port_id = port_id; 2112 phy->phy_type |= PORT_TYPE_SATA; 2113 phy->phy_attached = 1; 2114 phy->identify.device_type = SAS_SATA_DEV; 2115 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 2116 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 2117 queue_work(hisi_hba->wq, &phy->phyup_ws); 2118 2119 end: 2120 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp); 2121 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk); 2122 2123 return res; 2124 } 2125 2126 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { 2127 int_phy_updown_v2_hw, 2128 int_chnl_int_v2_hw, 2129 }; 2130 2131 /** 2132 * There is a limitation in the hip06 chipset that we need 2133 * to map in all mbigen interrupts, even if they are not used. 2134 */ 2135 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba) 2136 { 2137 struct platform_device *pdev = hisi_hba->pdev; 2138 struct device *dev = &pdev->dev; 2139 int i, irq, rc, irq_map[128]; 2140 2141 2142 for (i = 0; i < 128; i++) 2143 irq_map[i] = platform_get_irq(pdev, i); 2144 2145 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) { 2146 int idx = i; 2147 2148 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */ 2149 if (!irq) { 2150 dev_err(dev, "irq init: fail map phy interrupt %d\n", 2151 idx); 2152 return -ENOENT; 2153 } 2154 2155 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0, 2156 DRV_NAME " phy", hisi_hba); 2157 if (rc) { 2158 dev_err(dev, "irq init: could not request " 2159 "phy interrupt %d, rc=%d\n", 2160 irq, rc); 2161 return -ENOENT; 2162 } 2163 } 2164 2165 for (i = 0; i < hisi_hba->n_phy; i++) { 2166 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 2167 int idx = i + 72; /* First SATA interrupt is irq72 */ 2168 2169 irq = irq_map[idx]; 2170 if (!irq) { 2171 dev_err(dev, "irq init: fail map phy interrupt %d\n", 2172 idx); 2173 return -ENOENT; 2174 } 2175 2176 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0, 2177 DRV_NAME " sata", phy); 2178 if (rc) { 2179 dev_err(dev, "irq init: could not request " 2180 "sata interrupt %d, rc=%d\n", 2181 irq, rc); 2182 return -ENOENT; 2183 } 2184 } 2185 2186 for (i = 0; i < hisi_hba->queue_count; i++) { 2187 int idx = i + 96; /* First cq interrupt is irq96 */ 2188 2189 irq = irq_map[idx]; 2190 if (!irq) { 2191 dev_err(dev, 2192 "irq init: could not map cq interrupt %d\n", 2193 idx); 2194 return -ENOENT; 2195 } 2196 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0, 2197 DRV_NAME " cq", &hisi_hba->cq[i]); 2198 if (rc) { 2199 dev_err(dev, 2200 "irq init: could not request cq interrupt %d, rc=%d\n", 2201 irq, rc); 2202 return -ENOENT; 2203 } 2204 } 2205 2206 return 0; 2207 } 2208 2209 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba) 2210 { 2211 int rc; 2212 2213 rc = hw_init_v2_hw(hisi_hba); 2214 if (rc) 2215 return rc; 2216 2217 rc = interrupt_init_v2_hw(hisi_hba); 2218 if (rc) 2219 return rc; 2220 2221 phys_init_v2_hw(hisi_hba); 2222 2223 return 0; 2224 } 2225 2226 static const struct hisi_sas_hw hisi_sas_v2_hw = { 2227 .hw_init = hisi_sas_v2_init, 2228 .setup_itct = setup_itct_v2_hw, 2229 .slot_index_alloc = slot_index_alloc_quirk_v2_hw, 2230 .alloc_dev = alloc_dev_quirk_v2_hw, 2231 .sl_notify = sl_notify_v2_hw, 2232 .get_wideport_bitmap = get_wideport_bitmap_v2_hw, 2233 .free_device = free_device_v2_hw, 2234 .prep_smp = prep_smp_v2_hw, 2235 .prep_ssp = prep_ssp_v2_hw, 2236 .prep_stp = prep_ata_v2_hw, 2237 .get_free_slot = get_free_slot_v2_hw, 2238 .start_delivery = start_delivery_v2_hw, 2239 .slot_complete = slot_complete_v2_hw, 2240 .phy_enable = enable_phy_v2_hw, 2241 .phy_disable = disable_phy_v2_hw, 2242 .phy_hard_reset = phy_hard_reset_v2_hw, 2243 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW, 2244 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr), 2245 }; 2246 2247 static int hisi_sas_v2_probe(struct platform_device *pdev) 2248 { 2249 return hisi_sas_probe(pdev, &hisi_sas_v2_hw); 2250 } 2251 2252 static int hisi_sas_v2_remove(struct platform_device *pdev) 2253 { 2254 return hisi_sas_remove(pdev); 2255 } 2256 2257 static const struct of_device_id sas_v2_of_match[] = { 2258 { .compatible = "hisilicon,hip06-sas-v2",}, 2259 {}, 2260 }; 2261 MODULE_DEVICE_TABLE(of, sas_v2_of_match); 2262 2263 static struct platform_driver hisi_sas_v2_driver = { 2264 .probe = hisi_sas_v2_probe, 2265 .remove = hisi_sas_v2_remove, 2266 .driver = { 2267 .name = DRV_NAME, 2268 .of_match_table = sas_v2_of_match, 2269 }, 2270 }; 2271 2272 module_platform_driver(hisi_sas_v2_driver); 2273 2274 MODULE_LICENSE("GPL"); 2275 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 2276 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver"); 2277 MODULE_ALIAS("platform:" DRV_NAME); 2278