1 /* 2 * Copyright (c) 2015 Linaro Ltd. 3 * Copyright (c) 2015 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 */ 11 12 #include "hisi_sas.h" 13 #define DRV_NAME "hisi_sas_v1_hw" 14 15 /* global registers need init*/ 16 #define DLVRY_QUEUE_ENABLE 0x0 17 #define IOST_BASE_ADDR_LO 0x8 18 #define IOST_BASE_ADDR_HI 0xc 19 #define ITCT_BASE_ADDR_LO 0x10 20 #define ITCT_BASE_ADDR_HI 0x14 21 #define BROKEN_MSG_ADDR_LO 0x18 22 #define BROKEN_MSG_ADDR_HI 0x1c 23 #define PHY_CONTEXT 0x20 24 #define PHY_STATE 0x24 25 #define PHY_PORT_NUM_MA 0x28 26 #define PORT_STATE 0x2c 27 #define PHY_CONN_RATE 0x30 28 #define HGC_TRANS_TASK_CNT_LIMIT 0x38 29 #define AXI_AHB_CLK_CFG 0x3c 30 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x84 31 #define HGC_GET_ITV_TIME 0x90 32 #define DEVICE_MSG_WORK_MODE 0x94 33 #define I_T_NEXUS_LOSS_TIME 0xa0 34 #define BUS_INACTIVE_LIMIT_TIME 0xa8 35 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 36 #define CFG_AGING_TIME 0xbc 37 #define CFG_AGING_TIME_ITCT_REL_OFF 0 38 #define CFG_AGING_TIME_ITCT_REL_MSK (0x1 << CFG_AGING_TIME_ITCT_REL_OFF) 39 #define HGC_DFX_CFG2 0xc0 40 #define FIS_LIST_BADDR_L 0xc4 41 #define CFG_1US_TIMER_TRSH 0xcc 42 #define CFG_SAS_CONFIG 0xd4 43 #define HGC_IOST_ECC_ADDR 0x140 44 #define HGC_IOST_ECC_ADDR_BAD_OFF 16 45 #define HGC_IOST_ECC_ADDR_BAD_MSK (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF) 46 #define HGC_DQ_ECC_ADDR 0x144 47 #define HGC_DQ_ECC_ADDR_BAD_OFF 16 48 #define HGC_DQ_ECC_ADDR_BAD_MSK (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF) 49 #define HGC_INVLD_DQE_INFO 0x148 50 #define HGC_INVLD_DQE_INFO_DQ_OFF 0 51 #define HGC_INVLD_DQE_INFO_DQ_MSK (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF) 52 #define HGC_INVLD_DQE_INFO_TYPE_OFF 16 53 #define HGC_INVLD_DQE_INFO_TYPE_MSK (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF) 54 #define HGC_INVLD_DQE_INFO_FORCE_OFF 17 55 #define HGC_INVLD_DQE_INFO_FORCE_MSK (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF) 56 #define HGC_INVLD_DQE_INFO_PHY_OFF 18 57 #define HGC_INVLD_DQE_INFO_PHY_MSK (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF) 58 #define HGC_INVLD_DQE_INFO_ABORT_OFF 19 59 #define HGC_INVLD_DQE_INFO_ABORT_MSK (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF) 60 #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF 20 61 #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF) 62 #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF 21 63 #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF) 64 #define HGC_INVLD_DQE_INFO_OFL_OFF 22 65 #define HGC_INVLD_DQE_INFO_OFL_MSK (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF) 66 #define HGC_ITCT_ECC_ADDR 0x150 67 #define HGC_ITCT_ECC_ADDR_BAD_OFF 16 68 #define HGC_ITCT_ECC_ADDR_BAD_MSK (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF) 69 #define HGC_AXI_FIFO_ERR_INFO 0x154 70 #define INT_COAL_EN 0x1bc 71 #define OQ_INT_COAL_TIME 0x1c0 72 #define OQ_INT_COAL_CNT 0x1c4 73 #define ENT_INT_COAL_TIME 0x1c8 74 #define ENT_INT_COAL_CNT 0x1cc 75 #define OQ_INT_SRC 0x1d0 76 #define OQ_INT_SRC_MSK 0x1d4 77 #define ENT_INT_SRC1 0x1d8 78 #define ENT_INT_SRC2 0x1dc 79 #define ENT_INT_SRC2_DQ_CFG_ERR_OFF 25 80 #define ENT_INT_SRC2_DQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF) 81 #define ENT_INT_SRC2_CQ_CFG_ERR_OFF 27 82 #define ENT_INT_SRC2_CQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF) 83 #define ENT_INT_SRC2_AXI_WRONG_INT_OFF 28 84 #define ENT_INT_SRC2_AXI_WRONG_INT_MSK (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF) 85 #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29 86 #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF) 87 #define ENT_INT_SRC_MSK1 0x1e0 88 #define ENT_INT_SRC_MSK2 0x1e4 89 #define SAS_ECC_INTR 0x1e8 90 #define SAS_ECC_INTR_DQ_ECC1B_OFF 0 91 #define SAS_ECC_INTR_DQ_ECC1B_MSK (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF) 92 #define SAS_ECC_INTR_DQ_ECCBAD_OFF 1 93 #define SAS_ECC_INTR_DQ_ECCBAD_MSK (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF) 94 #define SAS_ECC_INTR_IOST_ECC1B_OFF 2 95 #define SAS_ECC_INTR_IOST_ECC1B_MSK (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF) 96 #define SAS_ECC_INTR_IOST_ECCBAD_OFF 3 97 #define SAS_ECC_INTR_IOST_ECCBAD_MSK (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF) 98 #define SAS_ECC_INTR_ITCT_ECC1B_OFF 4 99 #define SAS_ECC_INTR_ITCT_ECC1B_MSK (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF) 100 #define SAS_ECC_INTR_ITCT_ECCBAD_OFF 5 101 #define SAS_ECC_INTR_ITCT_ECCBAD_MSK (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF) 102 #define SAS_ECC_INTR_MSK 0x1ec 103 #define HGC_ERR_STAT_EN 0x238 104 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 105 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 106 #define DLVRY_Q_0_DEPTH 0x268 107 #define DLVRY_Q_0_WR_PTR 0x26c 108 #define DLVRY_Q_0_RD_PTR 0x270 109 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 110 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 111 #define COMPL_Q_0_DEPTH 0x4e8 112 #define COMPL_Q_0_WR_PTR 0x4ec 113 #define COMPL_Q_0_RD_PTR 0x4f0 114 #define HGC_ECC_ERR 0x7d0 115 116 /* phy registers need init */ 117 #define PORT_BASE (0x800) 118 119 #define PHY_CFG (PORT_BASE + 0x0) 120 #define PHY_CFG_ENA_OFF 0 121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 122 #define PHY_CFG_DC_OPT_OFF 2 123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 124 #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc) 125 #define PROG_PHY_LINK_RATE_MAX_OFF 0 126 #define PROG_PHY_LINK_RATE_MAX_MSK (0xf << PROG_PHY_LINK_RATE_MAX_OFF) 127 #define PROG_PHY_LINK_RATE_MIN_OFF 4 128 #define PROG_PHY_LINK_RATE_MIN_MSK (0xf << PROG_PHY_LINK_RATE_MIN_OFF) 129 #define PROG_PHY_LINK_RATE_OOB_OFF 8 130 #define PROG_PHY_LINK_RATE_OOB_MSK (0xf << PROG_PHY_LINK_RATE_OOB_OFF) 131 #define PHY_CTRL (PORT_BASE + 0x14) 132 #define PHY_CTRL_RESET_OFF 0 133 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 134 #define PHY_RATE_NEGO (PORT_BASE + 0x30) 135 #define PHY_PCN (PORT_BASE + 0x44) 136 #define SL_TOUT_CFG (PORT_BASE + 0x8c) 137 #define SL_CONTROL (PORT_BASE + 0x94) 138 #define SL_CONTROL_NOTIFY_EN_OFF 0 139 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 140 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 141 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 142 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 143 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 144 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 145 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 146 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 147 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 148 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) 149 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) 150 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) 151 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) 152 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) 153 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) 154 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 155 #define DONE_RECEIVED_TIME (PORT_BASE + 0x12c) 156 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 157 #define PHY_CONFIG2 (PORT_BASE + 0x1a8) 158 #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3 159 #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF) 160 #define PHY_CONFIG2_TX_TRAIN_COMP_OFF 24 161 #define PHY_CONFIG2_TX_TRAIN_COMP_MSK (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF) 162 #define CHL_INT0 (PORT_BASE + 0x1b0) 163 #define CHL_INT0_PHYCTRL_NOTRDY_OFF 0 164 #define CHL_INT0_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF) 165 #define CHL_INT0_SN_FAIL_NGR_OFF 2 166 #define CHL_INT0_SN_FAIL_NGR_MSK (0x1 << CHL_INT0_SN_FAIL_NGR_OFF) 167 #define CHL_INT0_DWS_LOST_OFF 4 168 #define CHL_INT0_DWS_LOST_MSK (0x1 << CHL_INT0_DWS_LOST_OFF) 169 #define CHL_INT0_SL_IDAF_FAIL_OFF 10 170 #define CHL_INT0_SL_IDAF_FAIL_MSK (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF) 171 #define CHL_INT0_ID_TIMEOUT_OFF 11 172 #define CHL_INT0_ID_TIMEOUT_MSK (0x1 << CHL_INT0_ID_TIMEOUT_OFF) 173 #define CHL_INT0_SL_OPAF_FAIL_OFF 12 174 #define CHL_INT0_SL_OPAF_FAIL_MSK (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF) 175 #define CHL_INT0_SL_PS_FAIL_OFF 21 176 #define CHL_INT0_SL_PS_FAIL_MSK (0x1 << CHL_INT0_SL_PS_FAIL_OFF) 177 #define CHL_INT1 (PORT_BASE + 0x1b4) 178 #define CHL_INT2 (PORT_BASE + 0x1b8) 179 #define CHL_INT2_SL_RX_BC_ACK_OFF 2 180 #define CHL_INT2_SL_RX_BC_ACK_MSK (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF) 181 #define CHL_INT2_SL_PHY_ENA_OFF 6 182 #define CHL_INT2_SL_PHY_ENA_MSK (0x1 << CHL_INT2_SL_PHY_ENA_OFF) 183 #define CHL_INT0_MSK (PORT_BASE + 0x1bc) 184 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0 185 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF) 186 #define CHL_INT1_MSK (PORT_BASE + 0x1c0) 187 #define CHL_INT2_MSK (PORT_BASE + 0x1c4) 188 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 189 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 190 #define DMA_TX_STATUS_BUSY_OFF 0 191 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 192 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 193 #define DMA_RX_STATUS_BUSY_OFF 0 194 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 195 196 #define AXI_CFG 0x5100 197 #define RESET_VALUE 0x7ffff 198 199 /* HW dma structures */ 200 /* Delivery queue header */ 201 /* dw0 */ 202 #define CMD_HDR_RESP_REPORT_OFF 5 203 #define CMD_HDR_RESP_REPORT_MSK 0x20 204 #define CMD_HDR_TLR_CTRL_OFF 6 205 #define CMD_HDR_TLR_CTRL_MSK 0xc0 206 #define CMD_HDR_PORT_OFF 17 207 #define CMD_HDR_PORT_MSK 0xe0000 208 #define CMD_HDR_PRIORITY_OFF 27 209 #define CMD_HDR_PRIORITY_MSK 0x8000000 210 #define CMD_HDR_MODE_OFF 28 211 #define CMD_HDR_MODE_MSK 0x10000000 212 #define CMD_HDR_CMD_OFF 29 213 #define CMD_HDR_CMD_MSK 0xe0000000 214 /* dw1 */ 215 #define CMD_HDR_VERIFY_DTL_OFF 10 216 #define CMD_HDR_VERIFY_DTL_MSK 0x400 217 #define CMD_HDR_SSP_FRAME_TYPE_OFF 13 218 #define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000 219 #define CMD_HDR_DEVICE_ID_OFF 16 220 #define CMD_HDR_DEVICE_ID_MSK 0xffff0000 221 /* dw2 */ 222 #define CMD_HDR_CFL_OFF 0 223 #define CMD_HDR_CFL_MSK 0x1ff 224 #define CMD_HDR_MRFL_OFF 15 225 #define CMD_HDR_MRFL_MSK 0xff8000 226 #define CMD_HDR_FIRST_BURST_OFF 25 227 #define CMD_HDR_FIRST_BURST_MSK 0x2000000 228 /* dw3 */ 229 #define CMD_HDR_IPTT_OFF 0 230 #define CMD_HDR_IPTT_MSK 0xffff 231 /* dw6 */ 232 #define CMD_HDR_DATA_SGL_LEN_OFF 16 233 #define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000 234 235 /* Completion header */ 236 #define CMPLT_HDR_IPTT_OFF 0 237 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 238 #define CMPLT_HDR_CMD_CMPLT_OFF 17 239 #define CMPLT_HDR_CMD_CMPLT_MSK (0x1 << CMPLT_HDR_CMD_CMPLT_OFF) 240 #define CMPLT_HDR_ERR_RCRD_XFRD_OFF 18 241 #define CMPLT_HDR_ERR_RCRD_XFRD_MSK (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF) 242 #define CMPLT_HDR_RSPNS_XFRD_OFF 19 243 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 244 #define CMPLT_HDR_IO_CFG_ERR_OFF 27 245 #define CMPLT_HDR_IO_CFG_ERR_MSK (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF) 246 247 /* ITCT header */ 248 /* qw0 */ 249 #define ITCT_HDR_DEV_TYPE_OFF 0 250 #define ITCT_HDR_DEV_TYPE_MSK (0x3ULL << ITCT_HDR_DEV_TYPE_OFF) 251 #define ITCT_HDR_VALID_OFF 2 252 #define ITCT_HDR_VALID_MSK (0x1ULL << ITCT_HDR_VALID_OFF) 253 #define ITCT_HDR_AWT_CONTROL_OFF 4 254 #define ITCT_HDR_AWT_CONTROL_MSK (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF) 255 #define ITCT_HDR_MAX_CONN_RATE_OFF 5 256 #define ITCT_HDR_MAX_CONN_RATE_MSK (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF) 257 #define ITCT_HDR_VALID_LINK_NUM_OFF 9 258 #define ITCT_HDR_VALID_LINK_NUM_MSK (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF) 259 #define ITCT_HDR_PORT_ID_OFF 13 260 #define ITCT_HDR_PORT_ID_MSK (0x7ULL << ITCT_HDR_PORT_ID_OFF) 261 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 262 #define ITCT_HDR_SMP_TIMEOUT_MSK (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF) 263 /* qw1 */ 264 #define ITCT_HDR_MAX_SAS_ADDR_OFF 0 265 #define ITCT_HDR_MAX_SAS_ADDR_MSK (0xffffffffffffffff << \ 266 ITCT_HDR_MAX_SAS_ADDR_OFF) 267 /* qw2 */ 268 #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF 0 269 #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK (0xffffULL << \ 270 ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) 271 #define ITCT_HDR_BUS_INACTIVE_TL_OFF 16 272 #define ITCT_HDR_BUS_INACTIVE_TL_MSK (0xffffULL << \ 273 ITCT_HDR_BUS_INACTIVE_TL_OFF) 274 #define ITCT_HDR_MAX_CONN_TL_OFF 32 275 #define ITCT_HDR_MAX_CONN_TL_MSK (0xffffULL << \ 276 ITCT_HDR_MAX_CONN_TL_OFF) 277 #define ITCT_HDR_REJ_OPEN_TL_OFF 48 278 #define ITCT_HDR_REJ_OPEN_TL_MSK (0xffffULL << \ 279 ITCT_HDR_REJ_OPEN_TL_OFF) 280 281 /* Err record header */ 282 #define ERR_HDR_DMA_TX_ERR_TYPE_OFF 0 283 #define ERR_HDR_DMA_TX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF) 284 #define ERR_HDR_DMA_RX_ERR_TYPE_OFF 16 285 #define ERR_HDR_DMA_RX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF) 286 287 struct hisi_sas_complete_v1_hdr { 288 __le32 data; 289 }; 290 291 struct hisi_sas_err_record_v1 { 292 /* dw0 */ 293 __le32 dma_err_type; 294 295 /* dw1 */ 296 __le32 trans_tx_fail_type; 297 298 /* dw2 */ 299 __le32 trans_rx_fail_type; 300 301 /* dw3 */ 302 u32 rsvd; 303 }; 304 305 enum { 306 HISI_SAS_PHY_BCAST_ACK = 0, 307 HISI_SAS_PHY_SL_PHY_ENABLED, 308 HISI_SAS_PHY_INT_ABNORMAL, 309 HISI_SAS_PHY_INT_NR 310 }; 311 312 enum { 313 DMA_TX_ERR_BASE = 0x0, 314 DMA_RX_ERR_BASE = 0x100, 315 TRANS_TX_FAIL_BASE = 0x200, 316 TRANS_RX_FAIL_BASE = 0x300, 317 318 /* dma tx */ 319 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */ 320 DMA_TX_DIF_APP_ERR, /* 0x1 */ 321 DMA_TX_DIF_RPP_ERR, /* 0x2 */ 322 DMA_TX_AXI_BUS_ERR, /* 0x3 */ 323 DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */ 324 DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */ 325 DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */ 326 DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */ 327 DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */ 328 DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */ 329 330 /* dma rx */ 331 DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */ 332 DMA_RX_DIF_CRC_ERR, /* 0x101 */ 333 DMA_RX_DIF_APP_ERR, /* 0x102 */ 334 DMA_RX_DIF_RPP_ERR, /* 0x103 */ 335 DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */ 336 DMA_RX_AXI_BUS_ERR, /* 0x105 */ 337 DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */ 338 DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */ 339 DMA_RX_DATA_OFFSET_ERR, /* 0x108 */ 340 DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */ 341 DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */ 342 DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */ 343 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */ 344 345 /* trans tx */ 346 TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */ 347 TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */ 348 TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */ 349 TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */ 350 TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */ 351 TRANS_TX_RSVD1_ERR, /* 0x205 */ 352 TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */ 353 TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */ 354 TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */ 355 TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */ 356 TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */ 357 TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */ 358 TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */ 359 TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */ 360 TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */ 361 TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */ 362 TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */ 363 TRANS_TX_RSVD2_ERR, /* 0x211 */ 364 TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */ 365 TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */ 366 TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */ 367 TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */ 368 TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */ 369 TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */ 370 TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */ 371 TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */ 372 TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */ 373 TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */ 374 TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */ 375 TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */ 376 TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */ 377 TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */ 378 379 /* trans rx */ 380 TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */ 381 TRANS_RX_FRAME_DONE_ERR, /* 0x301 */ 382 TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */ 383 TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */ 384 TRANS_RX_RSVD0_ERR, /* 0x304 */ 385 TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */ 386 TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */ 387 TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */ 388 TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */ 389 TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */ 390 TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */ 391 TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */ 392 TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */ 393 TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */ 394 TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */ 395 TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */ 396 TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */ 397 TRANS_RX_BAD_HASH_ERR, /* 0x311 */ 398 TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */ 399 TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */ 400 TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */ 401 TRANS_RX_NO_BALANCE_ERR, /* 0x315 */ 402 TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */ 403 TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */ 404 TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */ 405 TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */ 406 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */ 407 }; 408 409 #define HISI_SAS_COMMAND_ENTRIES_V1_HW 8192 410 411 #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS) 412 #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES) 413 #define HISI_SAS_FATAL_INT_NR (2) 414 415 #define HISI_SAS_MAX_INT_NR \ 416 (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\ 417 HISI_SAS_FATAL_INT_NR) 418 419 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 420 { 421 void __iomem *regs = hisi_hba->regs + off; 422 423 return readl(regs); 424 } 425 426 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 427 { 428 void __iomem *regs = hisi_hba->regs + off; 429 430 return readl_relaxed(regs); 431 } 432 433 static void hisi_sas_write32(struct hisi_hba *hisi_hba, 434 u32 off, u32 val) 435 { 436 void __iomem *regs = hisi_hba->regs + off; 437 438 writel(val, regs); 439 } 440 441 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, 442 int phy_no, u32 off, u32 val) 443 { 444 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 445 446 writel(val, regs); 447 } 448 449 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 450 int phy_no, u32 off) 451 { 452 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 453 454 return readl(regs); 455 } 456 457 static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 458 { 459 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 460 461 cfg &= ~PHY_CFG_DC_OPT_MSK; 462 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 463 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 464 } 465 466 static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 467 { 468 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2); 469 470 cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK; 471 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg); 472 } 473 474 static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 475 { 476 struct sas_identify_frame identify_frame; 477 u32 *identify_buffer; 478 479 memset(&identify_frame, 0, sizeof(identify_frame)); 480 identify_frame.dev_type = SAS_END_DEVICE; 481 identify_frame.frame_type = 0; 482 identify_frame._un1 = 1; 483 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 484 identify_frame.target_bits = SAS_PROTOCOL_NONE; 485 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 486 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 487 identify_frame.phy_id = phy_no; 488 identify_buffer = (u32 *)(&identify_frame); 489 490 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 491 __swab32(identify_buffer[0])); 492 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 493 __swab32(identify_buffer[1])); 494 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 495 __swab32(identify_buffer[2])); 496 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 497 __swab32(identify_buffer[3])); 498 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 499 __swab32(identify_buffer[4])); 500 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 501 __swab32(identify_buffer[5])); 502 } 503 504 static void setup_itct_v1_hw(struct hisi_hba *hisi_hba, 505 struct hisi_sas_device *sas_dev) 506 { 507 struct domain_device *device = sas_dev->sas_device; 508 struct device *dev = &hisi_hba->pdev->dev; 509 u64 qw0, device_id = sas_dev->device_id; 510 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 511 512 memset(itct, 0, sizeof(*itct)); 513 514 /* qw0 */ 515 qw0 = 0; 516 switch (sas_dev->dev_type) { 517 case SAS_END_DEVICE: 518 case SAS_EDGE_EXPANDER_DEVICE: 519 case SAS_FANOUT_EXPANDER_DEVICE: 520 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 521 break; 522 default: 523 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 524 sas_dev->dev_type); 525 } 526 527 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 528 (1 << ITCT_HDR_AWT_CONTROL_OFF) | 529 (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) | 530 (1 << ITCT_HDR_VALID_LINK_NUM_OFF) | 531 (device->port->id << ITCT_HDR_PORT_ID_OFF)); 532 itct->qw0 = cpu_to_le64(qw0); 533 534 /* qw1 */ 535 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 536 itct->sas_addr = __swab64(itct->sas_addr); 537 538 /* qw2 */ 539 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) | 540 (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) | 541 (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) | 542 (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF)); 543 } 544 545 static void free_device_v1_hw(struct hisi_hba *hisi_hba, 546 struct hisi_sas_device *sas_dev) 547 { 548 u64 dev_id = sas_dev->device_id; 549 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 550 u64 qw0; 551 u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); 552 553 reg_val |= CFG_AGING_TIME_ITCT_REL_MSK; 554 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val); 555 556 /* free itct */ 557 udelay(1); 558 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); 559 reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK; 560 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val); 561 562 qw0 = cpu_to_le64(itct->qw0); 563 qw0 &= ~ITCT_HDR_VALID_MSK; 564 itct->qw0 = cpu_to_le64(qw0); 565 } 566 567 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba) 568 { 569 int i; 570 unsigned long end_time; 571 u32 val; 572 struct device *dev = &hisi_hba->pdev->dev; 573 574 for (i = 0; i < hisi_hba->n_phy; i++) { 575 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); 576 577 phy_ctrl |= PHY_CTRL_RESET_MSK; 578 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl); 579 } 580 msleep(1); /* It is safe to wait for 50us */ 581 582 /* Ensure DMA tx & rx idle */ 583 for (i = 0; i < hisi_hba->n_phy; i++) { 584 u32 dma_tx_status, dma_rx_status; 585 586 end_time = jiffies + msecs_to_jiffies(1000); 587 588 while (1) { 589 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i, 590 DMA_TX_STATUS); 591 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i, 592 DMA_RX_STATUS); 593 594 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) && 595 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK)) 596 break; 597 598 msleep(20); 599 if (time_after(jiffies, end_time)) 600 return -EIO; 601 } 602 } 603 604 /* Ensure axi bus idle */ 605 end_time = jiffies + msecs_to_jiffies(1000); 606 while (1) { 607 u32 axi_status = 608 hisi_sas_read32(hisi_hba, AXI_CFG); 609 610 if (axi_status == 0) 611 break; 612 613 msleep(20); 614 if (time_after(jiffies, end_time)) 615 return -EIO; 616 } 617 618 if (ACPI_HANDLE(dev)) { 619 acpi_status s; 620 621 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 622 if (ACPI_FAILURE(s)) { 623 dev_err(dev, "Reset failed\n"); 624 return -EIO; 625 } 626 } else if (hisi_hba->ctrl) { 627 /* Apply reset and disable clock */ 628 /* clk disable reg is offset by +4 bytes from clk enable reg */ 629 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg, 630 RESET_VALUE); 631 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4, 632 RESET_VALUE); 633 msleep(1); 634 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 635 if (RESET_VALUE != (val & RESET_VALUE)) { 636 dev_err(dev, "Reset failed\n"); 637 return -EIO; 638 } 639 640 /* De-reset and enable clock */ 641 /* deassert rst reg is offset by +4 bytes from assert reg */ 642 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4, 643 RESET_VALUE); 644 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg, 645 RESET_VALUE); 646 msleep(1); 647 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 648 if (val & RESET_VALUE) { 649 dev_err(dev, "De-reset failed\n"); 650 return -EIO; 651 } 652 } else 653 dev_warn(dev, "no reset method\n"); 654 655 return 0; 656 } 657 658 static void init_reg_v1_hw(struct hisi_hba *hisi_hba) 659 { 660 int i; 661 662 /* Global registers init*/ 663 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 664 (u32)((1ULL << hisi_hba->queue_count) - 1)); 665 hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11); 666 hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1); 667 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff); 668 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401); 669 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64); 670 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1); 671 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64); 672 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710); 673 hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1); 674 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12); 675 hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40); 676 hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2); 677 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc); 678 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0); 679 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1); 680 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1); 681 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1); 682 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff); 683 hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0); 684 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 685 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0); 686 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 687 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0); 688 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0); 689 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2); 690 hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000); 691 692 for (i = 0; i < hisi_hba->n_phy; i++) { 693 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a); 694 hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080); 695 hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00); 696 hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000); 697 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); 698 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0); 699 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 700 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0); 701 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a); 702 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3); 703 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8); 704 } 705 706 for (i = 0; i < hisi_hba->queue_count; i++) { 707 /* Delivery queue */ 708 hisi_sas_write32(hisi_hba, 709 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 710 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 711 712 hisi_sas_write32(hisi_hba, 713 DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 714 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 715 716 hisi_sas_write32(hisi_hba, 717 DLVRY_Q_0_DEPTH + (i * 0x14), 718 HISI_SAS_QUEUE_SLOTS); 719 720 /* Completion queue */ 721 hisi_sas_write32(hisi_hba, 722 COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 723 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 724 725 hisi_sas_write32(hisi_hba, 726 COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 727 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 728 729 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 730 HISI_SAS_QUEUE_SLOTS); 731 } 732 733 /* itct */ 734 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 735 lower_32_bits(hisi_hba->itct_dma)); 736 737 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 738 upper_32_bits(hisi_hba->itct_dma)); 739 740 /* iost */ 741 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 742 lower_32_bits(hisi_hba->iost_dma)); 743 744 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 745 upper_32_bits(hisi_hba->iost_dma)); 746 747 /* breakpoint */ 748 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO, 749 lower_32_bits(hisi_hba->breakpoint_dma)); 750 751 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI, 752 upper_32_bits(hisi_hba->breakpoint_dma)); 753 } 754 755 static int hw_init_v1_hw(struct hisi_hba *hisi_hba) 756 { 757 struct device *dev = &hisi_hba->pdev->dev; 758 int rc; 759 760 rc = reset_hw_v1_hw(hisi_hba); 761 if (rc) { 762 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 763 return rc; 764 } 765 766 msleep(100); 767 init_reg_v1_hw(hisi_hba); 768 769 return 0; 770 } 771 772 static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 773 { 774 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 775 776 cfg |= PHY_CFG_ENA_MSK; 777 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 778 } 779 780 static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 781 { 782 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 783 784 cfg &= ~PHY_CFG_ENA_MSK; 785 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 786 } 787 788 static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 789 { 790 config_id_frame_v1_hw(hisi_hba, phy_no); 791 config_phy_opt_mode_v1_hw(hisi_hba, phy_no); 792 config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no); 793 enable_phy_v1_hw(hisi_hba, phy_no); 794 } 795 796 static void stop_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 797 { 798 disable_phy_v1_hw(hisi_hba, phy_no); 799 } 800 801 static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 802 { 803 stop_phy_v1_hw(hisi_hba, phy_no); 804 msleep(100); 805 start_phy_v1_hw(hisi_hba, phy_no); 806 } 807 808 static void start_phys_v1_hw(unsigned long data) 809 { 810 struct hisi_hba *hisi_hba = (struct hisi_hba *)data; 811 int i; 812 813 for (i = 0; i < hisi_hba->n_phy; i++) { 814 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a); 815 start_phy_v1_hw(hisi_hba, i); 816 } 817 } 818 819 static void phys_init_v1_hw(struct hisi_hba *hisi_hba) 820 { 821 int i; 822 struct timer_list *timer = &hisi_hba->timer; 823 824 for (i = 0; i < hisi_hba->n_phy; i++) { 825 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a); 826 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK); 827 } 828 829 setup_timer(timer, start_phys_v1_hw, (unsigned long)hisi_hba); 830 mod_timer(timer, jiffies + HZ); 831 } 832 833 static void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 834 { 835 u32 sl_control; 836 837 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 838 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 839 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 840 msleep(1); 841 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 842 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 843 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 844 } 845 846 static enum sas_linkrate phy_get_max_linkrate_v1_hw(void) 847 { 848 return SAS_LINK_RATE_6_0_GBPS; 849 } 850 851 static void phy_set_linkrate_v1_hw(struct hisi_hba *hisi_hba, int phy_no, 852 struct sas_phy_linkrates *r) 853 { 854 u32 prog_phy_link_rate = 855 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE); 856 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 857 struct asd_sas_phy *sas_phy = &phy->sas_phy; 858 int i; 859 enum sas_linkrate min, max; 860 u32 rate_mask = 0; 861 862 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) { 863 max = sas_phy->phy->maximum_linkrate; 864 min = r->minimum_linkrate; 865 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) { 866 max = r->maximum_linkrate; 867 min = sas_phy->phy->minimum_linkrate; 868 } else 869 return; 870 871 sas_phy->phy->maximum_linkrate = max; 872 sas_phy->phy->minimum_linkrate = min; 873 874 min -= SAS_LINK_RATE_1_5_GBPS; 875 max -= SAS_LINK_RATE_1_5_GBPS; 876 877 for (i = 0; i <= max; i++) 878 rate_mask |= 1 << (i * 2); 879 880 prog_phy_link_rate &= ~0xff; 881 prog_phy_link_rate |= rate_mask; 882 883 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 884 prog_phy_link_rate); 885 886 phy_hard_reset_v1_hw(hisi_hba, phy_no); 887 } 888 889 static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id) 890 { 891 int i, bitmap = 0; 892 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 893 894 for (i = 0; i < hisi_hba->n_phy; i++) 895 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 896 bitmap |= 1 << i; 897 898 return bitmap; 899 } 900 901 /** 902 * This function allocates across all queues to load balance. 903 * Slots are allocated from queues in a round-robin fashion. 904 * 905 * The callpath to this function and upto writing the write 906 * queue pointer should be safe from interruption. 907 */ 908 static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, u32 dev_id, 909 int *q, int *s) 910 { 911 struct device *dev = &hisi_hba->pdev->dev; 912 struct hisi_sas_dq *dq; 913 u32 r, w; 914 int queue = dev_id % hisi_hba->queue_count; 915 916 dq = &hisi_hba->dq[queue]; 917 w = dq->wr_point; 918 r = hisi_sas_read32_relaxed(hisi_hba, 919 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 920 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 921 dev_warn(dev, "could not find free slot\n"); 922 return -EAGAIN; 923 } 924 925 *q = queue; 926 *s = w; 927 return 0; 928 } 929 930 static void start_delivery_v1_hw(struct hisi_hba *hisi_hba) 931 { 932 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue; 933 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot; 934 struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue]; 935 936 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; 937 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), 938 dq->wr_point); 939 } 940 941 static int prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba, 942 struct hisi_sas_slot *slot, 943 struct hisi_sas_cmd_hdr *hdr, 944 struct scatterlist *scatter, 945 int n_elem) 946 { 947 struct device *dev = &hisi_hba->pdev->dev; 948 struct scatterlist *sg; 949 int i; 950 951 if (n_elem > HISI_SAS_SGE_PAGE_CNT) { 952 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT", 953 n_elem); 954 return -EINVAL; 955 } 956 957 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC, 958 &slot->sge_page_dma); 959 if (!slot->sge_page) 960 return -ENOMEM; 961 962 for_each_sg(scatter, sg, n_elem, i) { 963 struct hisi_sas_sge *entry = &slot->sge_page->sge[i]; 964 965 entry->addr = cpu_to_le64(sg_dma_address(sg)); 966 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 967 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 968 entry->data_off = 0; 969 } 970 971 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma); 972 973 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 974 975 return 0; 976 } 977 978 static int prep_smp_v1_hw(struct hisi_hba *hisi_hba, 979 struct hisi_sas_slot *slot) 980 { 981 struct sas_task *task = slot->task; 982 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 983 struct domain_device *device = task->dev; 984 struct device *dev = &hisi_hba->pdev->dev; 985 struct hisi_sas_port *port = slot->port; 986 struct scatterlist *sg_req, *sg_resp; 987 struct hisi_sas_device *sas_dev = device->lldd_dev; 988 dma_addr_t req_dma_addr; 989 unsigned int req_len, resp_len; 990 int elem, rc; 991 992 /* 993 * DMA-map SMP request, response buffers 994 */ 995 /* req */ 996 sg_req = &task->smp_task.smp_req; 997 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE); 998 if (!elem) 999 return -ENOMEM; 1000 req_len = sg_dma_len(sg_req); 1001 req_dma_addr = sg_dma_address(sg_req); 1002 1003 /* resp */ 1004 sg_resp = &task->smp_task.smp_resp; 1005 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE); 1006 if (!elem) { 1007 rc = -ENOMEM; 1008 goto err_out_req; 1009 } 1010 resp_len = sg_dma_len(sg_resp); 1011 if ((req_len & 0x3) || (resp_len & 0x3)) { 1012 rc = -EINVAL; 1013 goto err_out_resp; 1014 } 1015 1016 /* create header */ 1017 /* dw0 */ 1018 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1019 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1020 (1 << CMD_HDR_MODE_OFF) | /* ini mode */ 1021 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1022 1023 /* map itct entry */ 1024 hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF); 1025 1026 /* dw2 */ 1027 hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) | 1028 (HISI_SAS_MAX_SMP_RESP_SZ/4 << 1029 CMD_HDR_MRFL_OFF)); 1030 1031 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1032 1033 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1034 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1035 1036 return 0; 1037 1038 err_out_resp: 1039 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1, 1040 DMA_FROM_DEVICE); 1041 err_out_req: 1042 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1, 1043 DMA_TO_DEVICE); 1044 return rc; 1045 } 1046 1047 static int prep_ssp_v1_hw(struct hisi_hba *hisi_hba, 1048 struct hisi_sas_slot *slot, int is_tmf, 1049 struct hisi_sas_tmf_task *tmf) 1050 { 1051 struct sas_task *task = slot->task; 1052 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1053 struct domain_device *device = task->dev; 1054 struct hisi_sas_device *sas_dev = device->lldd_dev; 1055 struct hisi_sas_port *port = slot->port; 1056 struct sas_ssp_task *ssp_task = &task->ssp_task; 1057 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1058 int has_data = 0, rc, priority = is_tmf; 1059 u8 *buf_cmd, fburst = 0; 1060 u32 dw1, dw2; 1061 1062 /* create header */ 1063 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1064 (0x2 << CMD_HDR_TLR_CTRL_OFF) | 1065 (port->id << CMD_HDR_PORT_OFF) | 1066 (priority << CMD_HDR_PRIORITY_OFF) | 1067 (1 << CMD_HDR_MODE_OFF) | /* ini mode */ 1068 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1069 1070 dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF; 1071 1072 if (is_tmf) { 1073 dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1074 } else { 1075 switch (scsi_cmnd->sc_data_direction) { 1076 case DMA_TO_DEVICE: 1077 dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1078 has_data = 1; 1079 break; 1080 case DMA_FROM_DEVICE: 1081 dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1082 has_data = 1; 1083 break; 1084 default: 1085 dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1086 } 1087 } 1088 1089 /* map itct entry */ 1090 dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF; 1091 hdr->dw1 = cpu_to_le32(dw1); 1092 1093 if (is_tmf) { 1094 dw2 = ((sizeof(struct ssp_tmf_iu) + 1095 sizeof(struct ssp_frame_hdr)+3)/4) << 1096 CMD_HDR_CFL_OFF; 1097 } else { 1098 dw2 = ((sizeof(struct ssp_command_iu) + 1099 sizeof(struct ssp_frame_hdr)+3)/4) << 1100 CMD_HDR_CFL_OFF; 1101 } 1102 1103 dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF; 1104 1105 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1106 1107 if (has_data) { 1108 rc = prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter, 1109 slot->n_elem); 1110 if (rc) 1111 return rc; 1112 } 1113 1114 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1115 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); 1116 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1117 1118 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr); 1119 if (task->ssp_task.enable_first_burst) { 1120 fburst = (1 << 7); 1121 dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF; 1122 } 1123 hdr->dw2 = cpu_to_le32(dw2); 1124 1125 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1126 if (!is_tmf) { 1127 buf_cmd[9] = fburst | task->ssp_task.task_attr | 1128 (task->ssp_task.task_prio << 3); 1129 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd, 1130 task->ssp_task.cmd->cmd_len); 1131 } else { 1132 buf_cmd[10] = tmf->tmf; 1133 switch (tmf->tmf) { 1134 case TMF_ABORT_TASK: 1135 case TMF_QUERY_TASK: 1136 buf_cmd[12] = 1137 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1138 buf_cmd[13] = 1139 tmf->tag_of_task_to_be_managed & 0xff; 1140 break; 1141 default: 1142 break; 1143 } 1144 } 1145 1146 return 0; 1147 } 1148 1149 /* by default, task resp is complete */ 1150 static void slot_err_v1_hw(struct hisi_hba *hisi_hba, 1151 struct sas_task *task, 1152 struct hisi_sas_slot *slot) 1153 { 1154 struct task_status_struct *ts = &task->task_status; 1155 struct hisi_sas_err_record_v1 *err_record = slot->status_buffer; 1156 struct device *dev = &hisi_hba->pdev->dev; 1157 1158 switch (task->task_proto) { 1159 case SAS_PROTOCOL_SSP: 1160 { 1161 int error = -1; 1162 u32 dma_err_type = cpu_to_le32(err_record->dma_err_type); 1163 u32 dma_tx_err_type = ((dma_err_type & 1164 ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >> 1165 ERR_HDR_DMA_TX_ERR_TYPE_OFF; 1166 u32 dma_rx_err_type = ((dma_err_type & 1167 ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >> 1168 ERR_HDR_DMA_RX_ERR_TYPE_OFF; 1169 u32 trans_tx_fail_type = 1170 cpu_to_le32(err_record->trans_tx_fail_type); 1171 u32 trans_rx_fail_type = 1172 cpu_to_le32(err_record->trans_rx_fail_type); 1173 1174 if (dma_tx_err_type) { 1175 /* dma tx err */ 1176 error = ffs(dma_tx_err_type) 1177 - 1 + DMA_TX_ERR_BASE; 1178 } else if (dma_rx_err_type) { 1179 /* dma rx err */ 1180 error = ffs(dma_rx_err_type) 1181 - 1 + DMA_RX_ERR_BASE; 1182 } else if (trans_tx_fail_type) { 1183 /* trans tx err */ 1184 error = ffs(trans_tx_fail_type) 1185 - 1 + TRANS_TX_FAIL_BASE; 1186 } else if (trans_rx_fail_type) { 1187 /* trans rx err */ 1188 error = ffs(trans_rx_fail_type) 1189 - 1 + TRANS_RX_FAIL_BASE; 1190 } 1191 1192 switch (error) { 1193 case DMA_TX_DATA_UNDERFLOW_ERR: 1194 case DMA_RX_DATA_UNDERFLOW_ERR: 1195 { 1196 ts->residual = 0; 1197 ts->stat = SAS_DATA_UNDERRUN; 1198 break; 1199 } 1200 case DMA_TX_DATA_SGL_OVERFLOW_ERR: 1201 case DMA_TX_DIF_SGL_OVERFLOW_ERR: 1202 case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR: 1203 case DMA_RX_DATA_OVERFLOW_ERR: 1204 case TRANS_RX_FRAME_OVERRUN_ERR: 1205 case TRANS_RX_LINK_BUF_OVERRUN_ERR: 1206 { 1207 ts->stat = SAS_DATA_OVERRUN; 1208 ts->residual = 0; 1209 break; 1210 } 1211 case TRANS_TX_PHY_NOT_ENABLE_ERR: 1212 { 1213 ts->stat = SAS_PHY_DOWN; 1214 break; 1215 } 1216 case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR: 1217 case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR: 1218 case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR: 1219 case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR: 1220 case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR: 1221 case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR: 1222 case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR: 1223 case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR: 1224 case TRANS_TX_OPEN_BREAK_RECEIVE_ERR: 1225 case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR: 1226 case TRANS_TX_OPEN_REJCT_NO_DEST_ERR: 1227 case TRANS_TX_OPEN_RETRY_ERR: 1228 { 1229 ts->stat = SAS_OPEN_REJECT; 1230 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1231 break; 1232 } 1233 case TRANS_TX_OPEN_TIMEOUT_ERR: 1234 { 1235 ts->stat = SAS_OPEN_TO; 1236 break; 1237 } 1238 case TRANS_TX_NAK_RECEIVE_ERR: 1239 case TRANS_TX_ACK_NAK_TIMEOUT_ERR: 1240 { 1241 ts->stat = SAS_NAK_R_ERR; 1242 break; 1243 } 1244 case TRANS_TX_CREDIT_TIMEOUT_ERR: 1245 case TRANS_TX_CLOSE_NORMAL_ERR: 1246 { 1247 /* This will request a retry */ 1248 ts->stat = SAS_QUEUE_FULL; 1249 slot->abort = 1; 1250 break; 1251 } 1252 default: 1253 { 1254 ts->stat = SAM_STAT_CHECK_CONDITION; 1255 break; 1256 } 1257 } 1258 } 1259 break; 1260 case SAS_PROTOCOL_SMP: 1261 ts->stat = SAM_STAT_CHECK_CONDITION; 1262 break; 1263 1264 case SAS_PROTOCOL_SATA: 1265 case SAS_PROTOCOL_STP: 1266 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1267 { 1268 dev_err(dev, "slot err: SATA/STP not supported"); 1269 } 1270 break; 1271 default: 1272 break; 1273 } 1274 1275 } 1276 1277 static int slot_complete_v1_hw(struct hisi_hba *hisi_hba, 1278 struct hisi_sas_slot *slot, int abort) 1279 { 1280 struct sas_task *task = slot->task; 1281 struct hisi_sas_device *sas_dev; 1282 struct device *dev = &hisi_hba->pdev->dev; 1283 struct task_status_struct *ts; 1284 struct domain_device *device; 1285 enum exec_status sts; 1286 struct hisi_sas_complete_v1_hdr *complete_queue = 1287 hisi_hba->complete_hdr[slot->cmplt_queue]; 1288 struct hisi_sas_complete_v1_hdr *complete_hdr; 1289 u32 cmplt_hdr_data; 1290 1291 complete_hdr = &complete_queue[slot->cmplt_queue_slot]; 1292 cmplt_hdr_data = le32_to_cpu(complete_hdr->data); 1293 1294 if (unlikely(!task || !task->lldd_task || !task->dev)) 1295 return -EINVAL; 1296 1297 ts = &task->task_status; 1298 device = task->dev; 1299 sas_dev = device->lldd_dev; 1300 1301 task->task_state_flags &= 1302 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1303 task->task_state_flags |= SAS_TASK_STATE_DONE; 1304 1305 memset(ts, 0, sizeof(*ts)); 1306 ts->resp = SAS_TASK_COMPLETE; 1307 1308 if (unlikely(!sas_dev || abort)) { 1309 if (!sas_dev) 1310 dev_dbg(dev, "slot complete: port has not device\n"); 1311 ts->stat = SAS_PHY_DOWN; 1312 goto out; 1313 } 1314 1315 if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) { 1316 u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO); 1317 1318 if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK) 1319 dev_err(dev, "slot complete: [%d:%d] has dq IPTT err", 1320 slot->cmplt_queue, slot->cmplt_queue_slot); 1321 1322 if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK) 1323 dev_err(dev, "slot complete: [%d:%d] has dq type err", 1324 slot->cmplt_queue, slot->cmplt_queue_slot); 1325 1326 if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK) 1327 dev_err(dev, "slot complete: [%d:%d] has dq force phy err", 1328 slot->cmplt_queue, slot->cmplt_queue_slot); 1329 1330 if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK) 1331 dev_err(dev, "slot complete: [%d:%d] has dq phy id err", 1332 slot->cmplt_queue, slot->cmplt_queue_slot); 1333 1334 if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK) 1335 dev_err(dev, "slot complete: [%d:%d] has dq abort flag err", 1336 slot->cmplt_queue, slot->cmplt_queue_slot); 1337 1338 if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK) 1339 dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err", 1340 slot->cmplt_queue, slot->cmplt_queue_slot); 1341 1342 if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK) 1343 dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err", 1344 slot->cmplt_queue, slot->cmplt_queue_slot); 1345 1346 if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK) 1347 dev_err(dev, "slot complete: [%d:%d] has dq order frame len err", 1348 slot->cmplt_queue, slot->cmplt_queue_slot); 1349 1350 ts->stat = SAS_OPEN_REJECT; 1351 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1352 goto out; 1353 } 1354 1355 if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK && 1356 !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) { 1357 1358 slot_err_v1_hw(hisi_hba, task, slot); 1359 if (unlikely(slot->abort)) { 1360 queue_work(hisi_hba->wq, &slot->abort_slot); 1361 /* immediately return and do not complete */ 1362 return ts->stat; 1363 } 1364 goto out; 1365 } 1366 1367 switch (task->task_proto) { 1368 case SAS_PROTOCOL_SSP: 1369 { 1370 struct ssp_response_iu *iu = slot->status_buffer + 1371 sizeof(struct hisi_sas_err_record); 1372 sas_ssp_task_response(dev, task, iu); 1373 break; 1374 } 1375 case SAS_PROTOCOL_SMP: 1376 { 1377 void *to; 1378 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1379 1380 ts->stat = SAM_STAT_GOOD; 1381 to = kmap_atomic(sg_page(sg_resp)); 1382 1383 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1384 DMA_FROM_DEVICE); 1385 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1386 DMA_TO_DEVICE); 1387 memcpy(to + sg_resp->offset, 1388 slot->status_buffer + 1389 sizeof(struct hisi_sas_err_record), 1390 sg_dma_len(sg_resp)); 1391 kunmap_atomic(to); 1392 break; 1393 } 1394 case SAS_PROTOCOL_SATA: 1395 case SAS_PROTOCOL_STP: 1396 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1397 dev_err(dev, "slot complete: SATA/STP not supported"); 1398 break; 1399 1400 default: 1401 ts->stat = SAM_STAT_CHECK_CONDITION; 1402 break; 1403 } 1404 1405 if (!slot->port->port_attached) { 1406 dev_err(dev, "slot complete: port %d has removed\n", 1407 slot->port->sas_port.id); 1408 ts->stat = SAS_PHY_DOWN; 1409 } 1410 1411 out: 1412 if (sas_dev) 1413 atomic64_dec(&sas_dev->running_req); 1414 1415 hisi_sas_slot_task_free(hisi_hba, task, slot); 1416 sts = ts->stat; 1417 1418 if (task->task_done) 1419 task->task_done(task); 1420 1421 return sts; 1422 } 1423 1424 /* Interrupts */ 1425 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p) 1426 { 1427 struct hisi_sas_phy *phy = p; 1428 struct hisi_hba *hisi_hba = phy->hisi_hba; 1429 struct device *dev = &hisi_hba->pdev->dev; 1430 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1431 int i, phy_no = sas_phy->id; 1432 u32 irq_value, context, port_id, link_rate; 1433 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1434 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; 1435 irqreturn_t res = IRQ_HANDLED; 1436 1437 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1438 if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) { 1439 dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n", 1440 irq_value); 1441 res = IRQ_NONE; 1442 goto end; 1443 } 1444 1445 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1446 if (context & 1 << phy_no) { 1447 dev_err(dev, "phyup: phy%d SATA attached equipment\n", 1448 phy_no); 1449 goto end; 1450 } 1451 1452 port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no)) 1453 & 0xf; 1454 if (port_id == 0xf) { 1455 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1456 res = IRQ_NONE; 1457 goto end; 1458 } 1459 1460 for (i = 0; i < 6; i++) { 1461 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1462 RX_IDAF_DWORD0 + (i * 4)); 1463 frame_rcvd[i] = __swab32(idaf); 1464 } 1465 1466 /* Get the linkrate */ 1467 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1468 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1469 sas_phy->linkrate = link_rate; 1470 sas_phy->oob_mode = SAS_OOB_MODE; 1471 memcpy(sas_phy->attached_sas_addr, 1472 &id->sas_addr, SAS_ADDR_SIZE); 1473 dev_info(dev, "phyup: phy%d link_rate=%d\n", 1474 phy_no, link_rate); 1475 phy->port_id = port_id; 1476 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1477 phy->phy_type |= PORT_TYPE_SAS; 1478 phy->phy_attached = 1; 1479 phy->identify.device_type = id->dev_type; 1480 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1481 if (phy->identify.device_type == SAS_END_DEVICE) 1482 phy->identify.target_port_protocols = 1483 SAS_PROTOCOL_SSP; 1484 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1485 phy->identify.target_port_protocols = 1486 SAS_PROTOCOL_SMP; 1487 queue_work(hisi_hba->wq, &phy->phyup_ws); 1488 1489 end: 1490 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, 1491 CHL_INT2_SL_PHY_ENA_MSK); 1492 1493 if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) { 1494 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1495 1496 chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK; 1497 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0); 1498 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee); 1499 } 1500 1501 return res; 1502 } 1503 1504 static irqreturn_t int_bcast_v1_hw(int irq, void *p) 1505 { 1506 struct hisi_sas_phy *phy = p; 1507 struct hisi_hba *hisi_hba = phy->hisi_hba; 1508 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1509 struct sas_ha_struct *sha = &hisi_hba->sha; 1510 struct device *dev = &hisi_hba->pdev->dev; 1511 int phy_no = sas_phy->id; 1512 u32 irq_value; 1513 irqreturn_t res = IRQ_HANDLED; 1514 1515 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1516 1517 if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) { 1518 dev_err(dev, "bcast: irq_value = %x not set enable bit", 1519 irq_value); 1520 res = IRQ_NONE; 1521 goto end; 1522 } 1523 1524 sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1525 1526 end: 1527 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, 1528 CHL_INT2_SL_RX_BC_ACK_MSK); 1529 1530 return res; 1531 } 1532 1533 static irqreturn_t int_abnormal_v1_hw(int irq, void *p) 1534 { 1535 struct hisi_sas_phy *phy = p; 1536 struct hisi_hba *hisi_hba = phy->hisi_hba; 1537 struct device *dev = &hisi_hba->pdev->dev; 1538 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1539 u32 irq_value, irq_mask_old; 1540 int phy_no = sas_phy->id; 1541 1542 /* mask_int0 */ 1543 irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK); 1544 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff); 1545 1546 /* read int0 */ 1547 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1548 1549 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) { 1550 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1551 1552 hisi_sas_phy_down(hisi_hba, phy_no, 1553 (phy_state & 1 << phy_no) ? 1 : 0); 1554 } 1555 1556 if (irq_value & CHL_INT0_ID_TIMEOUT_MSK) 1557 dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n", 1558 phy_no); 1559 1560 if (irq_value & CHL_INT0_DWS_LOST_MSK) 1561 dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no); 1562 1563 if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK) 1564 dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n", 1565 phy_no); 1566 1567 if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK || 1568 irq_value & CHL_INT0_SL_OPAF_FAIL_MSK) 1569 dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n", 1570 phy_no); 1571 1572 if (irq_value & CHL_INT0_SL_PS_FAIL_OFF) 1573 dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no); 1574 1575 /* write to zero */ 1576 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value); 1577 1578 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) 1579 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 1580 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK); 1581 else 1582 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 1583 irq_mask_old); 1584 1585 return IRQ_HANDLED; 1586 } 1587 1588 static irqreturn_t cq_interrupt_v1_hw(int irq, void *p) 1589 { 1590 struct hisi_sas_cq *cq = p; 1591 struct hisi_hba *hisi_hba = cq->hisi_hba; 1592 struct hisi_sas_slot *slot; 1593 int queue = cq->id; 1594 struct hisi_sas_complete_v1_hdr *complete_queue = 1595 (struct hisi_sas_complete_v1_hdr *) 1596 hisi_hba->complete_hdr[queue]; 1597 u32 irq_value, rd_point = cq->rd_point, wr_point; 1598 1599 spin_lock(&hisi_hba->lock); 1600 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC); 1601 1602 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1603 wr_point = hisi_sas_read32(hisi_hba, 1604 COMPL_Q_0_WR_PTR + (0x14 * queue)); 1605 1606 while (rd_point != wr_point) { 1607 struct hisi_sas_complete_v1_hdr *complete_hdr; 1608 int idx; 1609 u32 cmplt_hdr_data; 1610 1611 complete_hdr = &complete_queue[rd_point]; 1612 cmplt_hdr_data = cpu_to_le32(complete_hdr->data); 1613 idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >> 1614 CMPLT_HDR_IPTT_OFF; 1615 slot = &hisi_hba->slot_info[idx]; 1616 1617 /* The completion queue and queue slot index are not 1618 * necessarily the same as the delivery queue and 1619 * queue slot index. 1620 */ 1621 slot->cmplt_queue_slot = rd_point; 1622 slot->cmplt_queue = queue; 1623 slot_complete_v1_hw(hisi_hba, slot, 0); 1624 1625 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1626 rd_point = 0; 1627 } 1628 1629 /* update rd_point */ 1630 cq->rd_point = rd_point; 1631 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1632 spin_unlock(&hisi_hba->lock); 1633 1634 return IRQ_HANDLED; 1635 } 1636 1637 static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) 1638 { 1639 struct hisi_hba *hisi_hba = p; 1640 struct device *dev = &hisi_hba->pdev->dev; 1641 u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); 1642 1643 if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) { 1644 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1645 1646 panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n", 1647 dev_name(dev), ecc_err); 1648 } 1649 1650 if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) { 1651 u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) & 1652 HGC_DQ_ECC_ADDR_BAD_MSK) >> 1653 HGC_DQ_ECC_ADDR_BAD_OFF; 1654 1655 panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n", 1656 dev_name(dev), addr); 1657 } 1658 1659 if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) { 1660 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1661 1662 panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n", 1663 dev_name(dev), ecc_err); 1664 } 1665 1666 if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) { 1667 u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) & 1668 HGC_IOST_ECC_ADDR_BAD_MSK) >> 1669 HGC_IOST_ECC_ADDR_BAD_OFF; 1670 1671 panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n", 1672 dev_name(dev), addr); 1673 } 1674 1675 if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) { 1676 u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) & 1677 HGC_ITCT_ECC_ADDR_BAD_MSK) >> 1678 HGC_ITCT_ECC_ADDR_BAD_OFF; 1679 1680 panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n", 1681 dev_name(dev), addr); 1682 } 1683 1684 if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) { 1685 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1686 1687 panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n", 1688 dev_name(dev), ecc_err); 1689 } 1690 1691 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f); 1692 1693 return IRQ_HANDLED; 1694 } 1695 1696 static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) 1697 { 1698 struct hisi_hba *hisi_hba = p; 1699 struct device *dev = &hisi_hba->pdev->dev; 1700 u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2); 1701 u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO); 1702 1703 if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK) 1704 panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n", 1705 dev_name(dev), axi_info); 1706 1707 if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK) 1708 panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n", 1709 dev_name(dev), axi_info); 1710 1711 if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK) 1712 panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n", 1713 dev_name(dev), axi_info); 1714 1715 if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK) 1716 panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n", 1717 dev_name(dev), axi_info); 1718 1719 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000); 1720 1721 return IRQ_HANDLED; 1722 } 1723 1724 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { 1725 int_bcast_v1_hw, 1726 int_phyup_v1_hw, 1727 int_abnormal_v1_hw 1728 }; 1729 1730 static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = { 1731 fatal_ecc_int_v1_hw, 1732 fatal_axi_int_v1_hw 1733 }; 1734 1735 static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba) 1736 { 1737 struct platform_device *pdev = hisi_hba->pdev; 1738 struct device *dev = &pdev->dev; 1739 int i, j, irq, rc, idx; 1740 1741 for (i = 0; i < hisi_hba->n_phy; i++) { 1742 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 1743 1744 idx = i * HISI_SAS_PHY_INT_NR; 1745 for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) { 1746 irq = platform_get_irq(pdev, idx); 1747 if (!irq) { 1748 dev_err(dev, 1749 "irq init: fail map phy interrupt %d\n", 1750 idx); 1751 return -ENOENT; 1752 } 1753 1754 rc = devm_request_irq(dev, irq, phy_interrupts[j], 0, 1755 DRV_NAME " phy", phy); 1756 if (rc) { 1757 dev_err(dev, "irq init: could not request " 1758 "phy interrupt %d, rc=%d\n", 1759 irq, rc); 1760 return -ENOENT; 1761 } 1762 } 1763 } 1764 1765 idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR; 1766 for (i = 0; i < hisi_hba->queue_count; i++, idx++) { 1767 irq = platform_get_irq(pdev, idx); 1768 if (!irq) { 1769 dev_err(dev, "irq init: could not map cq interrupt %d\n", 1770 idx); 1771 return -ENOENT; 1772 } 1773 1774 rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0, 1775 DRV_NAME " cq", &hisi_hba->cq[i]); 1776 if (rc) { 1777 dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n", 1778 irq, rc); 1779 return -ENOENT; 1780 } 1781 } 1782 1783 idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count; 1784 for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) { 1785 irq = platform_get_irq(pdev, idx); 1786 if (!irq) { 1787 dev_err(dev, "irq init: could not map fatal interrupt %d\n", 1788 idx); 1789 return -ENOENT; 1790 } 1791 1792 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0, 1793 DRV_NAME " fatal", hisi_hba); 1794 if (rc) { 1795 dev_err(dev, 1796 "irq init: could not request fatal interrupt %d, rc=%d\n", 1797 irq, rc); 1798 return -ENOENT; 1799 } 1800 } 1801 1802 return 0; 1803 } 1804 1805 static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba) 1806 { 1807 int i; 1808 u32 val; 1809 1810 for (i = 0; i < hisi_hba->n_phy; i++) { 1811 /* Clear interrupt status */ 1812 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0); 1813 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val); 1814 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1); 1815 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val); 1816 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2); 1817 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val); 1818 1819 /* Unmask interrupt */ 1820 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee); 1821 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff); 1822 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a); 1823 1824 /* bypass chip bug mask abnormal intr */ 1825 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 1826 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK); 1827 } 1828 1829 return 0; 1830 } 1831 1832 static int hisi_sas_v1_init(struct hisi_hba *hisi_hba) 1833 { 1834 int rc; 1835 1836 rc = hw_init_v1_hw(hisi_hba); 1837 if (rc) 1838 return rc; 1839 1840 rc = interrupt_init_v1_hw(hisi_hba); 1841 if (rc) 1842 return rc; 1843 1844 rc = interrupt_openall_v1_hw(hisi_hba); 1845 if (rc) 1846 return rc; 1847 1848 phys_init_v1_hw(hisi_hba); 1849 1850 return 0; 1851 } 1852 1853 static const struct hisi_sas_hw hisi_sas_v1_hw = { 1854 .hw_init = hisi_sas_v1_init, 1855 .setup_itct = setup_itct_v1_hw, 1856 .sl_notify = sl_notify_v1_hw, 1857 .free_device = free_device_v1_hw, 1858 .prep_smp = prep_smp_v1_hw, 1859 .prep_ssp = prep_ssp_v1_hw, 1860 .get_free_slot = get_free_slot_v1_hw, 1861 .start_delivery = start_delivery_v1_hw, 1862 .slot_complete = slot_complete_v1_hw, 1863 .phy_enable = enable_phy_v1_hw, 1864 .phy_disable = disable_phy_v1_hw, 1865 .phy_hard_reset = phy_hard_reset_v1_hw, 1866 .phy_set_linkrate = phy_set_linkrate_v1_hw, 1867 .phy_get_max_linkrate = phy_get_max_linkrate_v1_hw, 1868 .get_wideport_bitmap = get_wideport_bitmap_v1_hw, 1869 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V1_HW, 1870 .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr), 1871 }; 1872 1873 static int hisi_sas_v1_probe(struct platform_device *pdev) 1874 { 1875 return hisi_sas_probe(pdev, &hisi_sas_v1_hw); 1876 } 1877 1878 static int hisi_sas_v1_remove(struct platform_device *pdev) 1879 { 1880 return hisi_sas_remove(pdev); 1881 } 1882 1883 static const struct of_device_id sas_v1_of_match[] = { 1884 { .compatible = "hisilicon,hip05-sas-v1",}, 1885 {}, 1886 }; 1887 MODULE_DEVICE_TABLE(of, sas_v1_of_match); 1888 1889 static const struct acpi_device_id sas_v1_acpi_match[] = { 1890 { "HISI0161", 0 }, 1891 { } 1892 }; 1893 1894 MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match); 1895 1896 static struct platform_driver hisi_sas_v1_driver = { 1897 .probe = hisi_sas_v1_probe, 1898 .remove = hisi_sas_v1_remove, 1899 .driver = { 1900 .name = DRV_NAME, 1901 .of_match_table = sas_v1_of_match, 1902 .acpi_match_table = ACPI_PTR(sas_v1_acpi_match), 1903 }, 1904 }; 1905 1906 module_platform_driver(hisi_sas_v1_driver); 1907 1908 MODULE_LICENSE("GPL"); 1909 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 1910 MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver"); 1911 MODULE_ALIAS("platform:" DRV_NAME); 1912