1 /* 2 * Copyright (c) 2015 Linaro Ltd. 3 * Copyright (c) 2015 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 */ 11 12 #include "hisi_sas.h" 13 #define DRV_NAME "hisi_sas_v1_hw" 14 15 /* global registers need init*/ 16 #define DLVRY_QUEUE_ENABLE 0x0 17 #define IOST_BASE_ADDR_LO 0x8 18 #define IOST_BASE_ADDR_HI 0xc 19 #define ITCT_BASE_ADDR_LO 0x10 20 #define ITCT_BASE_ADDR_HI 0x14 21 #define BROKEN_MSG_ADDR_LO 0x18 22 #define BROKEN_MSG_ADDR_HI 0x1c 23 #define PHY_CONTEXT 0x20 24 #define PHY_STATE 0x24 25 #define PHY_PORT_NUM_MA 0x28 26 #define PORT_STATE 0x2c 27 #define PHY_CONN_RATE 0x30 28 #define HGC_TRANS_TASK_CNT_LIMIT 0x38 29 #define AXI_AHB_CLK_CFG 0x3c 30 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x84 31 #define HGC_GET_ITV_TIME 0x90 32 #define DEVICE_MSG_WORK_MODE 0x94 33 #define I_T_NEXUS_LOSS_TIME 0xa0 34 #define BUS_INACTIVE_LIMIT_TIME 0xa8 35 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 36 #define CFG_AGING_TIME 0xbc 37 #define CFG_AGING_TIME_ITCT_REL_OFF 0 38 #define CFG_AGING_TIME_ITCT_REL_MSK (0x1 << CFG_AGING_TIME_ITCT_REL_OFF) 39 #define HGC_DFX_CFG2 0xc0 40 #define FIS_LIST_BADDR_L 0xc4 41 #define CFG_1US_TIMER_TRSH 0xcc 42 #define CFG_SAS_CONFIG 0xd4 43 #define HGC_IOST_ECC_ADDR 0x140 44 #define HGC_IOST_ECC_ADDR_BAD_OFF 16 45 #define HGC_IOST_ECC_ADDR_BAD_MSK (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF) 46 #define HGC_DQ_ECC_ADDR 0x144 47 #define HGC_DQ_ECC_ADDR_BAD_OFF 16 48 #define HGC_DQ_ECC_ADDR_BAD_MSK (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF) 49 #define HGC_INVLD_DQE_INFO 0x148 50 #define HGC_INVLD_DQE_INFO_DQ_OFF 0 51 #define HGC_INVLD_DQE_INFO_DQ_MSK (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF) 52 #define HGC_INVLD_DQE_INFO_TYPE_OFF 16 53 #define HGC_INVLD_DQE_INFO_TYPE_MSK (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF) 54 #define HGC_INVLD_DQE_INFO_FORCE_OFF 17 55 #define HGC_INVLD_DQE_INFO_FORCE_MSK (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF) 56 #define HGC_INVLD_DQE_INFO_PHY_OFF 18 57 #define HGC_INVLD_DQE_INFO_PHY_MSK (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF) 58 #define HGC_INVLD_DQE_INFO_ABORT_OFF 19 59 #define HGC_INVLD_DQE_INFO_ABORT_MSK (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF) 60 #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF 20 61 #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF) 62 #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF 21 63 #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF) 64 #define HGC_INVLD_DQE_INFO_OFL_OFF 22 65 #define HGC_INVLD_DQE_INFO_OFL_MSK (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF) 66 #define HGC_ITCT_ECC_ADDR 0x150 67 #define HGC_ITCT_ECC_ADDR_BAD_OFF 16 68 #define HGC_ITCT_ECC_ADDR_BAD_MSK (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF) 69 #define HGC_AXI_FIFO_ERR_INFO 0x154 70 #define INT_COAL_EN 0x1bc 71 #define OQ_INT_COAL_TIME 0x1c0 72 #define OQ_INT_COAL_CNT 0x1c4 73 #define ENT_INT_COAL_TIME 0x1c8 74 #define ENT_INT_COAL_CNT 0x1cc 75 #define OQ_INT_SRC 0x1d0 76 #define OQ_INT_SRC_MSK 0x1d4 77 #define ENT_INT_SRC1 0x1d8 78 #define ENT_INT_SRC2 0x1dc 79 #define ENT_INT_SRC2_DQ_CFG_ERR_OFF 25 80 #define ENT_INT_SRC2_DQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF) 81 #define ENT_INT_SRC2_CQ_CFG_ERR_OFF 27 82 #define ENT_INT_SRC2_CQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF) 83 #define ENT_INT_SRC2_AXI_WRONG_INT_OFF 28 84 #define ENT_INT_SRC2_AXI_WRONG_INT_MSK (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF) 85 #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29 86 #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF) 87 #define ENT_INT_SRC_MSK1 0x1e0 88 #define ENT_INT_SRC_MSK2 0x1e4 89 #define SAS_ECC_INTR 0x1e8 90 #define SAS_ECC_INTR_DQ_ECC1B_OFF 0 91 #define SAS_ECC_INTR_DQ_ECC1B_MSK (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF) 92 #define SAS_ECC_INTR_DQ_ECCBAD_OFF 1 93 #define SAS_ECC_INTR_DQ_ECCBAD_MSK (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF) 94 #define SAS_ECC_INTR_IOST_ECC1B_OFF 2 95 #define SAS_ECC_INTR_IOST_ECC1B_MSK (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF) 96 #define SAS_ECC_INTR_IOST_ECCBAD_OFF 3 97 #define SAS_ECC_INTR_IOST_ECCBAD_MSK (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF) 98 #define SAS_ECC_INTR_ITCT_ECC1B_OFF 4 99 #define SAS_ECC_INTR_ITCT_ECC1B_MSK (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF) 100 #define SAS_ECC_INTR_ITCT_ECCBAD_OFF 5 101 #define SAS_ECC_INTR_ITCT_ECCBAD_MSK (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF) 102 #define SAS_ECC_INTR_MSK 0x1ec 103 #define HGC_ERR_STAT_EN 0x238 104 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 105 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 106 #define DLVRY_Q_0_DEPTH 0x268 107 #define DLVRY_Q_0_WR_PTR 0x26c 108 #define DLVRY_Q_0_RD_PTR 0x270 109 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 110 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 111 #define COMPL_Q_0_DEPTH 0x4e8 112 #define COMPL_Q_0_WR_PTR 0x4ec 113 #define COMPL_Q_0_RD_PTR 0x4f0 114 #define HGC_ECC_ERR 0x7d0 115 116 /* phy registers need init */ 117 #define PORT_BASE (0x800) 118 119 #define PHY_CFG (PORT_BASE + 0x0) 120 #define PHY_CFG_ENA_OFF 0 121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 122 #define PHY_CFG_DC_OPT_OFF 2 123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 124 #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc) 125 #define PROG_PHY_LINK_RATE_MAX_OFF 0 126 #define PROG_PHY_LINK_RATE_MAX_MSK (0xf << PROG_PHY_LINK_RATE_MAX_OFF) 127 #define PROG_PHY_LINK_RATE_MIN_OFF 4 128 #define PROG_PHY_LINK_RATE_MIN_MSK (0xf << PROG_PHY_LINK_RATE_MIN_OFF) 129 #define PROG_PHY_LINK_RATE_OOB_OFF 8 130 #define PROG_PHY_LINK_RATE_OOB_MSK (0xf << PROG_PHY_LINK_RATE_OOB_OFF) 131 #define PHY_CTRL (PORT_BASE + 0x14) 132 #define PHY_CTRL_RESET_OFF 0 133 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 134 #define PHY_RATE_NEGO (PORT_BASE + 0x30) 135 #define PHY_PCN (PORT_BASE + 0x44) 136 #define SL_TOUT_CFG (PORT_BASE + 0x8c) 137 #define SL_CONTROL (PORT_BASE + 0x94) 138 #define SL_CONTROL_NOTIFY_EN_OFF 0 139 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 140 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 141 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 142 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 143 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 144 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 145 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 146 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 147 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 148 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) 149 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) 150 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) 151 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) 152 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) 153 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) 154 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 155 #define DONE_RECEIVED_TIME (PORT_BASE + 0x12c) 156 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 157 #define PHY_CONFIG2 (PORT_BASE + 0x1a8) 158 #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3 159 #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF) 160 #define PHY_CONFIG2_TX_TRAIN_COMP_OFF 24 161 #define PHY_CONFIG2_TX_TRAIN_COMP_MSK (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF) 162 #define CHL_INT0 (PORT_BASE + 0x1b0) 163 #define CHL_INT0_PHYCTRL_NOTRDY_OFF 0 164 #define CHL_INT0_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF) 165 #define CHL_INT0_SN_FAIL_NGR_OFF 2 166 #define CHL_INT0_SN_FAIL_NGR_MSK (0x1 << CHL_INT0_SN_FAIL_NGR_OFF) 167 #define CHL_INT0_DWS_LOST_OFF 4 168 #define CHL_INT0_DWS_LOST_MSK (0x1 << CHL_INT0_DWS_LOST_OFF) 169 #define CHL_INT0_SL_IDAF_FAIL_OFF 10 170 #define CHL_INT0_SL_IDAF_FAIL_MSK (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF) 171 #define CHL_INT0_ID_TIMEOUT_OFF 11 172 #define CHL_INT0_ID_TIMEOUT_MSK (0x1 << CHL_INT0_ID_TIMEOUT_OFF) 173 #define CHL_INT0_SL_OPAF_FAIL_OFF 12 174 #define CHL_INT0_SL_OPAF_FAIL_MSK (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF) 175 #define CHL_INT0_SL_PS_FAIL_OFF 21 176 #define CHL_INT0_SL_PS_FAIL_MSK (0x1 << CHL_INT0_SL_PS_FAIL_OFF) 177 #define CHL_INT1 (PORT_BASE + 0x1b4) 178 #define CHL_INT2 (PORT_BASE + 0x1b8) 179 #define CHL_INT2_SL_RX_BC_ACK_OFF 2 180 #define CHL_INT2_SL_RX_BC_ACK_MSK (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF) 181 #define CHL_INT2_SL_PHY_ENA_OFF 6 182 #define CHL_INT2_SL_PHY_ENA_MSK (0x1 << CHL_INT2_SL_PHY_ENA_OFF) 183 #define CHL_INT0_MSK (PORT_BASE + 0x1bc) 184 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0 185 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF) 186 #define CHL_INT1_MSK (PORT_BASE + 0x1c0) 187 #define CHL_INT2_MSK (PORT_BASE + 0x1c4) 188 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 189 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 190 #define DMA_TX_STATUS_BUSY_OFF 0 191 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 192 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 193 #define DMA_RX_STATUS_BUSY_OFF 0 194 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 195 196 #define AXI_CFG 0x5100 197 #define RESET_VALUE 0x7ffff 198 199 /* HW dma structures */ 200 /* Delivery queue header */ 201 /* dw0 */ 202 #define CMD_HDR_RESP_REPORT_OFF 5 203 #define CMD_HDR_RESP_REPORT_MSK 0x20 204 #define CMD_HDR_TLR_CTRL_OFF 6 205 #define CMD_HDR_TLR_CTRL_MSK 0xc0 206 #define CMD_HDR_PORT_OFF 17 207 #define CMD_HDR_PORT_MSK 0xe0000 208 #define CMD_HDR_PRIORITY_OFF 27 209 #define CMD_HDR_PRIORITY_MSK 0x8000000 210 #define CMD_HDR_MODE_OFF 28 211 #define CMD_HDR_MODE_MSK 0x10000000 212 #define CMD_HDR_CMD_OFF 29 213 #define CMD_HDR_CMD_MSK 0xe0000000 214 /* dw1 */ 215 #define CMD_HDR_VERIFY_DTL_OFF 10 216 #define CMD_HDR_VERIFY_DTL_MSK 0x400 217 #define CMD_HDR_SSP_FRAME_TYPE_OFF 13 218 #define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000 219 #define CMD_HDR_DEVICE_ID_OFF 16 220 #define CMD_HDR_DEVICE_ID_MSK 0xffff0000 221 /* dw2 */ 222 #define CMD_HDR_CFL_OFF 0 223 #define CMD_HDR_CFL_MSK 0x1ff 224 #define CMD_HDR_MRFL_OFF 15 225 #define CMD_HDR_MRFL_MSK 0xff8000 226 #define CMD_HDR_FIRST_BURST_OFF 25 227 #define CMD_HDR_FIRST_BURST_MSK 0x2000000 228 /* dw3 */ 229 #define CMD_HDR_IPTT_OFF 0 230 #define CMD_HDR_IPTT_MSK 0xffff 231 /* dw6 */ 232 #define CMD_HDR_DATA_SGL_LEN_OFF 16 233 #define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000 234 235 /* Completion header */ 236 #define CMPLT_HDR_IPTT_OFF 0 237 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 238 #define CMPLT_HDR_CMD_CMPLT_OFF 17 239 #define CMPLT_HDR_CMD_CMPLT_MSK (0x1 << CMPLT_HDR_CMD_CMPLT_OFF) 240 #define CMPLT_HDR_ERR_RCRD_XFRD_OFF 18 241 #define CMPLT_HDR_ERR_RCRD_XFRD_MSK (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF) 242 #define CMPLT_HDR_RSPNS_XFRD_OFF 19 243 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 244 #define CMPLT_HDR_IO_CFG_ERR_OFF 27 245 #define CMPLT_HDR_IO_CFG_ERR_MSK (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF) 246 247 /* ITCT header */ 248 /* qw0 */ 249 #define ITCT_HDR_DEV_TYPE_OFF 0 250 #define ITCT_HDR_DEV_TYPE_MSK (0x3ULL << ITCT_HDR_DEV_TYPE_OFF) 251 #define ITCT_HDR_VALID_OFF 2 252 #define ITCT_HDR_VALID_MSK (0x1ULL << ITCT_HDR_VALID_OFF) 253 #define ITCT_HDR_AWT_CONTROL_OFF 4 254 #define ITCT_HDR_AWT_CONTROL_MSK (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF) 255 #define ITCT_HDR_MAX_CONN_RATE_OFF 5 256 #define ITCT_HDR_MAX_CONN_RATE_MSK (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF) 257 #define ITCT_HDR_VALID_LINK_NUM_OFF 9 258 #define ITCT_HDR_VALID_LINK_NUM_MSK (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF) 259 #define ITCT_HDR_PORT_ID_OFF 13 260 #define ITCT_HDR_PORT_ID_MSK (0x7ULL << ITCT_HDR_PORT_ID_OFF) 261 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 262 #define ITCT_HDR_SMP_TIMEOUT_MSK (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF) 263 /* qw1 */ 264 #define ITCT_HDR_MAX_SAS_ADDR_OFF 0 265 #define ITCT_HDR_MAX_SAS_ADDR_MSK (0xffffffffffffffff << \ 266 ITCT_HDR_MAX_SAS_ADDR_OFF) 267 /* qw2 */ 268 #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF 0 269 #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK (0xffffULL << \ 270 ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) 271 #define ITCT_HDR_BUS_INACTIVE_TL_OFF 16 272 #define ITCT_HDR_BUS_INACTIVE_TL_MSK (0xffffULL << \ 273 ITCT_HDR_BUS_INACTIVE_TL_OFF) 274 #define ITCT_HDR_MAX_CONN_TL_OFF 32 275 #define ITCT_HDR_MAX_CONN_TL_MSK (0xffffULL << \ 276 ITCT_HDR_MAX_CONN_TL_OFF) 277 #define ITCT_HDR_REJ_OPEN_TL_OFF 48 278 #define ITCT_HDR_REJ_OPEN_TL_MSK (0xffffULL << \ 279 ITCT_HDR_REJ_OPEN_TL_OFF) 280 281 /* Err record header */ 282 #define ERR_HDR_DMA_TX_ERR_TYPE_OFF 0 283 #define ERR_HDR_DMA_TX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF) 284 #define ERR_HDR_DMA_RX_ERR_TYPE_OFF 16 285 #define ERR_HDR_DMA_RX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF) 286 287 struct hisi_sas_complete_v1_hdr { 288 __le32 data; 289 }; 290 291 struct hisi_sas_err_record_v1 { 292 /* dw0 */ 293 __le32 dma_err_type; 294 295 /* dw1 */ 296 __le32 trans_tx_fail_type; 297 298 /* dw2 */ 299 __le32 trans_rx_fail_type; 300 301 /* dw3 */ 302 u32 rsvd; 303 }; 304 305 enum { 306 HISI_SAS_PHY_BCAST_ACK = 0, 307 HISI_SAS_PHY_SL_PHY_ENABLED, 308 HISI_SAS_PHY_INT_ABNORMAL, 309 HISI_SAS_PHY_INT_NR 310 }; 311 312 enum { 313 DMA_TX_ERR_BASE = 0x0, 314 DMA_RX_ERR_BASE = 0x100, 315 TRANS_TX_FAIL_BASE = 0x200, 316 TRANS_RX_FAIL_BASE = 0x300, 317 318 /* dma tx */ 319 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */ 320 DMA_TX_DIF_APP_ERR, /* 0x1 */ 321 DMA_TX_DIF_RPP_ERR, /* 0x2 */ 322 DMA_TX_AXI_BUS_ERR, /* 0x3 */ 323 DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */ 324 DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */ 325 DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */ 326 DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */ 327 DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */ 328 DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */ 329 330 /* dma rx */ 331 DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */ 332 DMA_RX_DIF_CRC_ERR, /* 0x101 */ 333 DMA_RX_DIF_APP_ERR, /* 0x102 */ 334 DMA_RX_DIF_RPP_ERR, /* 0x103 */ 335 DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */ 336 DMA_RX_AXI_BUS_ERR, /* 0x105 */ 337 DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */ 338 DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */ 339 DMA_RX_DATA_OFFSET_ERR, /* 0x108 */ 340 DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */ 341 DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */ 342 DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */ 343 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */ 344 345 /* trans tx */ 346 TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */ 347 TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */ 348 TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */ 349 TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */ 350 TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */ 351 TRANS_TX_RSVD1_ERR, /* 0x205 */ 352 TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */ 353 TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */ 354 TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */ 355 TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */ 356 TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */ 357 TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */ 358 TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */ 359 TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */ 360 TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */ 361 TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */ 362 TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */ 363 TRANS_TX_RSVD2_ERR, /* 0x211 */ 364 TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */ 365 TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */ 366 TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */ 367 TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */ 368 TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */ 369 TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */ 370 TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */ 371 TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */ 372 TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */ 373 TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */ 374 TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */ 375 TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */ 376 TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */ 377 TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */ 378 379 /* trans rx */ 380 TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */ 381 TRANS_RX_FRAME_DONE_ERR, /* 0x301 */ 382 TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */ 383 TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */ 384 TRANS_RX_RSVD0_ERR, /* 0x304 */ 385 TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */ 386 TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */ 387 TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */ 388 TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */ 389 TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */ 390 TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */ 391 TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */ 392 TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */ 393 TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */ 394 TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */ 395 TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */ 396 TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */ 397 TRANS_RX_BAD_HASH_ERR, /* 0x311 */ 398 TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */ 399 TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */ 400 TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */ 401 TRANS_RX_NO_BALANCE_ERR, /* 0x315 */ 402 TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */ 403 TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */ 404 TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */ 405 TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */ 406 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */ 407 }; 408 409 #define HISI_SAS_COMMAND_ENTRIES_V1_HW 8192 410 411 #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS) 412 #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES) 413 #define HISI_SAS_FATAL_INT_NR (2) 414 415 #define HISI_SAS_MAX_INT_NR \ 416 (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\ 417 HISI_SAS_FATAL_INT_NR) 418 419 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 420 { 421 void __iomem *regs = hisi_hba->regs + off; 422 423 return readl(regs); 424 } 425 426 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 427 { 428 void __iomem *regs = hisi_hba->regs + off; 429 430 return readl_relaxed(regs); 431 } 432 433 static void hisi_sas_write32(struct hisi_hba *hisi_hba, 434 u32 off, u32 val) 435 { 436 void __iomem *regs = hisi_hba->regs + off; 437 438 writel(val, regs); 439 } 440 441 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, 442 int phy_no, u32 off, u32 val) 443 { 444 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 445 446 writel(val, regs); 447 } 448 449 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 450 int phy_no, u32 off) 451 { 452 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 453 454 return readl(regs); 455 } 456 457 static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 458 { 459 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 460 461 cfg &= ~PHY_CFG_DC_OPT_MSK; 462 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 463 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 464 } 465 466 static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 467 { 468 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2); 469 470 cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK; 471 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg); 472 } 473 474 static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 475 { 476 struct sas_identify_frame identify_frame; 477 u32 *identify_buffer; 478 479 memset(&identify_frame, 0, sizeof(identify_frame)); 480 identify_frame.dev_type = SAS_END_DEVICE; 481 identify_frame.frame_type = 0; 482 identify_frame._un1 = 1; 483 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 484 identify_frame.target_bits = SAS_PROTOCOL_NONE; 485 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 486 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 487 identify_frame.phy_id = phy_no; 488 identify_buffer = (u32 *)(&identify_frame); 489 490 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 491 __swab32(identify_buffer[0])); 492 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 493 identify_buffer[2]); 494 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 495 identify_buffer[1]); 496 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 497 identify_buffer[4]); 498 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 499 identify_buffer[3]); 500 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 501 __swab32(identify_buffer[5])); 502 } 503 504 static void init_id_frame_v1_hw(struct hisi_hba *hisi_hba) 505 { 506 int i; 507 508 for (i = 0; i < hisi_hba->n_phy; i++) 509 config_id_frame_v1_hw(hisi_hba, i); 510 } 511 512 static void setup_itct_v1_hw(struct hisi_hba *hisi_hba, 513 struct hisi_sas_device *sas_dev) 514 { 515 struct domain_device *device = sas_dev->sas_device; 516 struct device *dev = &hisi_hba->pdev->dev; 517 u64 qw0, device_id = sas_dev->device_id; 518 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 519 520 memset(itct, 0, sizeof(*itct)); 521 522 /* qw0 */ 523 qw0 = 0; 524 switch (sas_dev->dev_type) { 525 case SAS_END_DEVICE: 526 case SAS_EDGE_EXPANDER_DEVICE: 527 case SAS_FANOUT_EXPANDER_DEVICE: 528 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 529 break; 530 default: 531 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 532 sas_dev->dev_type); 533 } 534 535 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 536 (1 << ITCT_HDR_AWT_CONTROL_OFF) | 537 (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) | 538 (1 << ITCT_HDR_VALID_LINK_NUM_OFF) | 539 (device->port->id << ITCT_HDR_PORT_ID_OFF)); 540 itct->qw0 = cpu_to_le64(qw0); 541 542 /* qw1 */ 543 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 544 itct->sas_addr = __swab64(itct->sas_addr); 545 546 /* qw2 */ 547 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) | 548 (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) | 549 (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) | 550 (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF)); 551 } 552 553 static void free_device_v1_hw(struct hisi_hba *hisi_hba, 554 struct hisi_sas_device *sas_dev) 555 { 556 u64 dev_id = sas_dev->device_id; 557 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 558 u64 qw0; 559 u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); 560 561 reg_val |= CFG_AGING_TIME_ITCT_REL_MSK; 562 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val); 563 564 /* free itct */ 565 udelay(1); 566 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); 567 reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK; 568 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val); 569 570 qw0 = cpu_to_le64(itct->qw0); 571 qw0 &= ~ITCT_HDR_VALID_MSK; 572 itct->qw0 = cpu_to_le64(qw0); 573 } 574 575 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba) 576 { 577 int i; 578 unsigned long end_time; 579 u32 val; 580 struct device *dev = &hisi_hba->pdev->dev; 581 582 for (i = 0; i < hisi_hba->n_phy; i++) { 583 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); 584 585 phy_ctrl |= PHY_CTRL_RESET_MSK; 586 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl); 587 } 588 msleep(1); /* It is safe to wait for 50us */ 589 590 /* Ensure DMA tx & rx idle */ 591 for (i = 0; i < hisi_hba->n_phy; i++) { 592 u32 dma_tx_status, dma_rx_status; 593 594 end_time = jiffies + msecs_to_jiffies(1000); 595 596 while (1) { 597 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i, 598 DMA_TX_STATUS); 599 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i, 600 DMA_RX_STATUS); 601 602 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) && 603 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK)) 604 break; 605 606 msleep(20); 607 if (time_after(jiffies, end_time)) 608 return -EIO; 609 } 610 } 611 612 /* Ensure axi bus idle */ 613 end_time = jiffies + msecs_to_jiffies(1000); 614 while (1) { 615 u32 axi_status = 616 hisi_sas_read32(hisi_hba, AXI_CFG); 617 618 if (axi_status == 0) 619 break; 620 621 msleep(20); 622 if (time_after(jiffies, end_time)) 623 return -EIO; 624 } 625 626 if (ACPI_HANDLE(dev)) { 627 acpi_status s; 628 629 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 630 if (ACPI_FAILURE(s)) { 631 dev_err(dev, "Reset failed\n"); 632 return -EIO; 633 } 634 } else if (hisi_hba->ctrl) { 635 /* Apply reset and disable clock */ 636 /* clk disable reg is offset by +4 bytes from clk enable reg */ 637 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg, 638 RESET_VALUE); 639 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4, 640 RESET_VALUE); 641 msleep(1); 642 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 643 if (RESET_VALUE != (val & RESET_VALUE)) { 644 dev_err(dev, "Reset failed\n"); 645 return -EIO; 646 } 647 648 /* De-reset and enable clock */ 649 /* deassert rst reg is offset by +4 bytes from assert reg */ 650 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4, 651 RESET_VALUE); 652 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg, 653 RESET_VALUE); 654 msleep(1); 655 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 656 if (val & RESET_VALUE) { 657 dev_err(dev, "De-reset failed\n"); 658 return -EIO; 659 } 660 } else 661 dev_warn(dev, "no reset method\n"); 662 663 return 0; 664 } 665 666 static void init_reg_v1_hw(struct hisi_hba *hisi_hba) 667 { 668 int i; 669 670 /* Global registers init*/ 671 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 672 (u32)((1ULL << hisi_hba->queue_count) - 1)); 673 hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11); 674 hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1); 675 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff); 676 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401); 677 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64); 678 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1); 679 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64); 680 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710); 681 hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1); 682 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12); 683 hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40); 684 hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2); 685 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc); 686 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0); 687 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1); 688 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1); 689 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1); 690 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff); 691 hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0); 692 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 693 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0); 694 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 695 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0); 696 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0); 697 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2); 698 hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000); 699 700 for (i = 0; i < hisi_hba->n_phy; i++) { 701 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a); 702 hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080); 703 hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00); 704 hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000); 705 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); 706 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0); 707 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 708 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0); 709 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a); 710 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3); 711 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8); 712 } 713 714 for (i = 0; i < hisi_hba->queue_count; i++) { 715 /* Delivery queue */ 716 hisi_sas_write32(hisi_hba, 717 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 718 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 719 720 hisi_sas_write32(hisi_hba, 721 DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 722 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 723 724 hisi_sas_write32(hisi_hba, 725 DLVRY_Q_0_DEPTH + (i * 0x14), 726 HISI_SAS_QUEUE_SLOTS); 727 728 /* Completion queue */ 729 hisi_sas_write32(hisi_hba, 730 COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 731 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 732 733 hisi_sas_write32(hisi_hba, 734 COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 735 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 736 737 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 738 HISI_SAS_QUEUE_SLOTS); 739 } 740 741 /* itct */ 742 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 743 lower_32_bits(hisi_hba->itct_dma)); 744 745 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 746 upper_32_bits(hisi_hba->itct_dma)); 747 748 /* iost */ 749 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 750 lower_32_bits(hisi_hba->iost_dma)); 751 752 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 753 upper_32_bits(hisi_hba->iost_dma)); 754 755 /* breakpoint */ 756 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO, 757 lower_32_bits(hisi_hba->breakpoint_dma)); 758 759 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI, 760 upper_32_bits(hisi_hba->breakpoint_dma)); 761 } 762 763 static int hw_init_v1_hw(struct hisi_hba *hisi_hba) 764 { 765 struct device *dev = &hisi_hba->pdev->dev; 766 int rc; 767 768 rc = reset_hw_v1_hw(hisi_hba); 769 if (rc) { 770 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 771 return rc; 772 } 773 774 msleep(100); 775 init_reg_v1_hw(hisi_hba); 776 777 init_id_frame_v1_hw(hisi_hba); 778 779 return 0; 780 } 781 782 static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 783 { 784 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 785 786 cfg |= PHY_CFG_ENA_MSK; 787 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 788 } 789 790 static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 791 { 792 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 793 794 cfg &= ~PHY_CFG_ENA_MSK; 795 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 796 } 797 798 static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 799 { 800 config_id_frame_v1_hw(hisi_hba, phy_no); 801 config_phy_opt_mode_v1_hw(hisi_hba, phy_no); 802 config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no); 803 enable_phy_v1_hw(hisi_hba, phy_no); 804 } 805 806 static void stop_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 807 { 808 disable_phy_v1_hw(hisi_hba, phy_no); 809 } 810 811 static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 812 { 813 stop_phy_v1_hw(hisi_hba, phy_no); 814 msleep(100); 815 start_phy_v1_hw(hisi_hba, phy_no); 816 } 817 818 static void start_phys_v1_hw(unsigned long data) 819 { 820 struct hisi_hba *hisi_hba = (struct hisi_hba *)data; 821 int i; 822 823 for (i = 0; i < hisi_hba->n_phy; i++) { 824 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a); 825 start_phy_v1_hw(hisi_hba, i); 826 } 827 } 828 829 static void phys_init_v1_hw(struct hisi_hba *hisi_hba) 830 { 831 int i; 832 struct timer_list *timer = &hisi_hba->timer; 833 834 for (i = 0; i < hisi_hba->n_phy; i++) { 835 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a); 836 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK); 837 } 838 839 setup_timer(timer, start_phys_v1_hw, (unsigned long)hisi_hba); 840 mod_timer(timer, jiffies + HZ); 841 } 842 843 static void sl_notify_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 844 { 845 u32 sl_control; 846 847 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 848 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 849 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 850 msleep(1); 851 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 852 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 853 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 854 } 855 856 static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id) 857 { 858 int i, bitmap = 0; 859 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 860 861 for (i = 0; i < hisi_hba->n_phy; i++) 862 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 863 bitmap |= 1 << i; 864 865 return bitmap; 866 } 867 868 /** 869 * This function allocates across all queues to load balance. 870 * Slots are allocated from queues in a round-robin fashion. 871 * 872 * The callpath to this function and upto writing the write 873 * queue pointer should be safe from interruption. 874 */ 875 static int get_free_slot_v1_hw(struct hisi_hba *hisi_hba, int *q, int *s) 876 { 877 struct device *dev = &hisi_hba->pdev->dev; 878 u32 r, w; 879 int queue = hisi_hba->queue; 880 881 while (1) { 882 w = hisi_sas_read32_relaxed(hisi_hba, 883 DLVRY_Q_0_WR_PTR + (queue * 0x14)); 884 r = hisi_sas_read32_relaxed(hisi_hba, 885 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 886 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 887 queue = (queue + 1) % hisi_hba->queue_count; 888 if (queue == hisi_hba->queue) { 889 dev_warn(dev, "could not find free slot\n"); 890 return -EAGAIN; 891 } 892 continue; 893 } 894 break; 895 } 896 hisi_hba->queue = (queue + 1) % hisi_hba->queue_count; 897 *q = queue; 898 *s = w; 899 return 0; 900 } 901 902 static void start_delivery_v1_hw(struct hisi_hba *hisi_hba) 903 { 904 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue; 905 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot; 906 907 hisi_sas_write32(hisi_hba, 908 DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), 909 ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS); 910 } 911 912 static int prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba, 913 struct hisi_sas_slot *slot, 914 struct hisi_sas_cmd_hdr *hdr, 915 struct scatterlist *scatter, 916 int n_elem) 917 { 918 struct device *dev = &hisi_hba->pdev->dev; 919 struct scatterlist *sg; 920 int i; 921 922 if (n_elem > HISI_SAS_SGE_PAGE_CNT) { 923 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT", 924 n_elem); 925 return -EINVAL; 926 } 927 928 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC, 929 &slot->sge_page_dma); 930 if (!slot->sge_page) 931 return -ENOMEM; 932 933 for_each_sg(scatter, sg, n_elem, i) { 934 struct hisi_sas_sge *entry = &slot->sge_page->sge[i]; 935 936 entry->addr = cpu_to_le64(sg_dma_address(sg)); 937 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 938 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 939 entry->data_off = 0; 940 } 941 942 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma); 943 944 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 945 946 return 0; 947 } 948 949 static int prep_smp_v1_hw(struct hisi_hba *hisi_hba, 950 struct hisi_sas_slot *slot) 951 { 952 struct sas_task *task = slot->task; 953 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 954 struct domain_device *device = task->dev; 955 struct device *dev = &hisi_hba->pdev->dev; 956 struct hisi_sas_port *port = slot->port; 957 struct scatterlist *sg_req, *sg_resp; 958 struct hisi_sas_device *sas_dev = device->lldd_dev; 959 dma_addr_t req_dma_addr; 960 unsigned int req_len, resp_len; 961 int elem, rc; 962 963 /* 964 * DMA-map SMP request, response buffers 965 */ 966 /* req */ 967 sg_req = &task->smp_task.smp_req; 968 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE); 969 if (!elem) 970 return -ENOMEM; 971 req_len = sg_dma_len(sg_req); 972 req_dma_addr = sg_dma_address(sg_req); 973 974 /* resp */ 975 sg_resp = &task->smp_task.smp_resp; 976 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE); 977 if (!elem) { 978 rc = -ENOMEM; 979 goto err_out_req; 980 } 981 resp_len = sg_dma_len(sg_resp); 982 if ((req_len & 0x3) || (resp_len & 0x3)) { 983 rc = -EINVAL; 984 goto err_out_resp; 985 } 986 987 /* create header */ 988 /* dw0 */ 989 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 990 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 991 (1 << CMD_HDR_MODE_OFF) | /* ini mode */ 992 (2 << CMD_HDR_CMD_OFF)); /* smp */ 993 994 /* map itct entry */ 995 hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF); 996 997 /* dw2 */ 998 hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) | 999 (HISI_SAS_MAX_SMP_RESP_SZ/4 << 1000 CMD_HDR_MRFL_OFF)); 1001 1002 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1003 1004 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1005 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1006 1007 return 0; 1008 1009 err_out_resp: 1010 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1, 1011 DMA_FROM_DEVICE); 1012 err_out_req: 1013 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1, 1014 DMA_TO_DEVICE); 1015 return rc; 1016 } 1017 1018 static int prep_ssp_v1_hw(struct hisi_hba *hisi_hba, 1019 struct hisi_sas_slot *slot, int is_tmf, 1020 struct hisi_sas_tmf_task *tmf) 1021 { 1022 struct sas_task *task = slot->task; 1023 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1024 struct domain_device *device = task->dev; 1025 struct hisi_sas_device *sas_dev = device->lldd_dev; 1026 struct hisi_sas_port *port = slot->port; 1027 struct sas_ssp_task *ssp_task = &task->ssp_task; 1028 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1029 int has_data = 0, rc, priority = is_tmf; 1030 u8 *buf_cmd, fburst = 0; 1031 u32 dw1, dw2; 1032 1033 /* create header */ 1034 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1035 (0x2 << CMD_HDR_TLR_CTRL_OFF) | 1036 (port->id << CMD_HDR_PORT_OFF) | 1037 (priority << CMD_HDR_PRIORITY_OFF) | 1038 (1 << CMD_HDR_MODE_OFF) | /* ini mode */ 1039 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1040 1041 dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF; 1042 1043 if (is_tmf) { 1044 dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1045 } else { 1046 switch (scsi_cmnd->sc_data_direction) { 1047 case DMA_TO_DEVICE: 1048 dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1049 has_data = 1; 1050 break; 1051 case DMA_FROM_DEVICE: 1052 dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1053 has_data = 1; 1054 break; 1055 default: 1056 dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1057 } 1058 } 1059 1060 /* map itct entry */ 1061 dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF; 1062 hdr->dw1 = cpu_to_le32(dw1); 1063 1064 if (is_tmf) { 1065 dw2 = ((sizeof(struct ssp_tmf_iu) + 1066 sizeof(struct ssp_frame_hdr)+3)/4) << 1067 CMD_HDR_CFL_OFF; 1068 } else { 1069 dw2 = ((sizeof(struct ssp_command_iu) + 1070 sizeof(struct ssp_frame_hdr)+3)/4) << 1071 CMD_HDR_CFL_OFF; 1072 } 1073 1074 dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF; 1075 1076 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1077 1078 if (has_data) { 1079 rc = prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter, 1080 slot->n_elem); 1081 if (rc) 1082 return rc; 1083 } 1084 1085 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1086 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); 1087 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1088 1089 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr); 1090 if (task->ssp_task.enable_first_burst) { 1091 fburst = (1 << 7); 1092 dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF; 1093 } 1094 hdr->dw2 = cpu_to_le32(dw2); 1095 1096 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1097 if (!is_tmf) { 1098 buf_cmd[9] = fburst | task->ssp_task.task_attr | 1099 (task->ssp_task.task_prio << 3); 1100 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd, 1101 task->ssp_task.cmd->cmd_len); 1102 } else { 1103 buf_cmd[10] = tmf->tmf; 1104 switch (tmf->tmf) { 1105 case TMF_ABORT_TASK: 1106 case TMF_QUERY_TASK: 1107 buf_cmd[12] = 1108 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1109 buf_cmd[13] = 1110 tmf->tag_of_task_to_be_managed & 0xff; 1111 break; 1112 default: 1113 break; 1114 } 1115 } 1116 1117 return 0; 1118 } 1119 1120 /* by default, task resp is complete */ 1121 static void slot_err_v1_hw(struct hisi_hba *hisi_hba, 1122 struct sas_task *task, 1123 struct hisi_sas_slot *slot) 1124 { 1125 struct task_status_struct *ts = &task->task_status; 1126 struct hisi_sas_err_record_v1 *err_record = slot->status_buffer; 1127 struct device *dev = &hisi_hba->pdev->dev; 1128 1129 switch (task->task_proto) { 1130 case SAS_PROTOCOL_SSP: 1131 { 1132 int error = -1; 1133 u32 dma_err_type = cpu_to_le32(err_record->dma_err_type); 1134 u32 dma_tx_err_type = ((dma_err_type & 1135 ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >> 1136 ERR_HDR_DMA_TX_ERR_TYPE_OFF; 1137 u32 dma_rx_err_type = ((dma_err_type & 1138 ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >> 1139 ERR_HDR_DMA_RX_ERR_TYPE_OFF; 1140 u32 trans_tx_fail_type = 1141 cpu_to_le32(err_record->trans_tx_fail_type); 1142 u32 trans_rx_fail_type = 1143 cpu_to_le32(err_record->trans_rx_fail_type); 1144 1145 if (dma_tx_err_type) { 1146 /* dma tx err */ 1147 error = ffs(dma_tx_err_type) 1148 - 1 + DMA_TX_ERR_BASE; 1149 } else if (dma_rx_err_type) { 1150 /* dma rx err */ 1151 error = ffs(dma_rx_err_type) 1152 - 1 + DMA_RX_ERR_BASE; 1153 } else if (trans_tx_fail_type) { 1154 /* trans tx err */ 1155 error = ffs(trans_tx_fail_type) 1156 - 1 + TRANS_TX_FAIL_BASE; 1157 } else if (trans_rx_fail_type) { 1158 /* trans rx err */ 1159 error = ffs(trans_rx_fail_type) 1160 - 1 + TRANS_RX_FAIL_BASE; 1161 } 1162 1163 switch (error) { 1164 case DMA_TX_DATA_UNDERFLOW_ERR: 1165 case DMA_RX_DATA_UNDERFLOW_ERR: 1166 { 1167 ts->residual = 0; 1168 ts->stat = SAS_DATA_UNDERRUN; 1169 break; 1170 } 1171 case DMA_TX_DATA_SGL_OVERFLOW_ERR: 1172 case DMA_TX_DIF_SGL_OVERFLOW_ERR: 1173 case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR: 1174 case DMA_RX_DATA_OVERFLOW_ERR: 1175 case TRANS_RX_FRAME_OVERRUN_ERR: 1176 case TRANS_RX_LINK_BUF_OVERRUN_ERR: 1177 { 1178 ts->stat = SAS_DATA_OVERRUN; 1179 ts->residual = 0; 1180 break; 1181 } 1182 case TRANS_TX_PHY_NOT_ENABLE_ERR: 1183 { 1184 ts->stat = SAS_PHY_DOWN; 1185 break; 1186 } 1187 case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR: 1188 case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR: 1189 case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR: 1190 case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR: 1191 case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR: 1192 case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR: 1193 case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR: 1194 case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR: 1195 case TRANS_TX_OPEN_BREAK_RECEIVE_ERR: 1196 case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR: 1197 case TRANS_TX_OPEN_REJCT_NO_DEST_ERR: 1198 case TRANS_TX_OPEN_RETRY_ERR: 1199 { 1200 ts->stat = SAS_OPEN_REJECT; 1201 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1202 break; 1203 } 1204 case TRANS_TX_OPEN_TIMEOUT_ERR: 1205 { 1206 ts->stat = SAS_OPEN_TO; 1207 break; 1208 } 1209 case TRANS_TX_NAK_RECEIVE_ERR: 1210 case TRANS_TX_ACK_NAK_TIMEOUT_ERR: 1211 { 1212 ts->stat = SAS_NAK_R_ERR; 1213 break; 1214 } 1215 case TRANS_TX_CREDIT_TIMEOUT_ERR: 1216 case TRANS_TX_CLOSE_NORMAL_ERR: 1217 { 1218 /* This will request a retry */ 1219 ts->stat = SAS_QUEUE_FULL; 1220 slot->abort = 1; 1221 break; 1222 } 1223 default: 1224 { 1225 ts->stat = SAM_STAT_CHECK_CONDITION; 1226 break; 1227 } 1228 } 1229 } 1230 break; 1231 case SAS_PROTOCOL_SMP: 1232 ts->stat = SAM_STAT_CHECK_CONDITION; 1233 break; 1234 1235 case SAS_PROTOCOL_SATA: 1236 case SAS_PROTOCOL_STP: 1237 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1238 { 1239 dev_err(dev, "slot err: SATA/STP not supported"); 1240 } 1241 break; 1242 default: 1243 break; 1244 } 1245 1246 } 1247 1248 static int slot_complete_v1_hw(struct hisi_hba *hisi_hba, 1249 struct hisi_sas_slot *slot, int abort) 1250 { 1251 struct sas_task *task = slot->task; 1252 struct hisi_sas_device *sas_dev; 1253 struct device *dev = &hisi_hba->pdev->dev; 1254 struct task_status_struct *ts; 1255 struct domain_device *device; 1256 enum exec_status sts; 1257 struct hisi_sas_complete_v1_hdr *complete_queue = 1258 hisi_hba->complete_hdr[slot->cmplt_queue]; 1259 struct hisi_sas_complete_v1_hdr *complete_hdr; 1260 u32 cmplt_hdr_data; 1261 1262 complete_hdr = &complete_queue[slot->cmplt_queue_slot]; 1263 cmplt_hdr_data = le32_to_cpu(complete_hdr->data); 1264 1265 if (unlikely(!task || !task->lldd_task || !task->dev)) 1266 return -EINVAL; 1267 1268 ts = &task->task_status; 1269 device = task->dev; 1270 sas_dev = device->lldd_dev; 1271 1272 task->task_state_flags &= 1273 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1274 task->task_state_flags |= SAS_TASK_STATE_DONE; 1275 1276 memset(ts, 0, sizeof(*ts)); 1277 ts->resp = SAS_TASK_COMPLETE; 1278 1279 if (unlikely(!sas_dev || abort)) { 1280 if (!sas_dev) 1281 dev_dbg(dev, "slot complete: port has not device\n"); 1282 ts->stat = SAS_PHY_DOWN; 1283 goto out; 1284 } 1285 1286 if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) { 1287 u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO); 1288 1289 if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK) 1290 dev_err(dev, "slot complete: [%d:%d] has dq IPTT err", 1291 slot->cmplt_queue, slot->cmplt_queue_slot); 1292 1293 if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK) 1294 dev_err(dev, "slot complete: [%d:%d] has dq type err", 1295 slot->cmplt_queue, slot->cmplt_queue_slot); 1296 1297 if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK) 1298 dev_err(dev, "slot complete: [%d:%d] has dq force phy err", 1299 slot->cmplt_queue, slot->cmplt_queue_slot); 1300 1301 if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK) 1302 dev_err(dev, "slot complete: [%d:%d] has dq phy id err", 1303 slot->cmplt_queue, slot->cmplt_queue_slot); 1304 1305 if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK) 1306 dev_err(dev, "slot complete: [%d:%d] has dq abort flag err", 1307 slot->cmplt_queue, slot->cmplt_queue_slot); 1308 1309 if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK) 1310 dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err", 1311 slot->cmplt_queue, slot->cmplt_queue_slot); 1312 1313 if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK) 1314 dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err", 1315 slot->cmplt_queue, slot->cmplt_queue_slot); 1316 1317 if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK) 1318 dev_err(dev, "slot complete: [%d:%d] has dq order frame len err", 1319 slot->cmplt_queue, slot->cmplt_queue_slot); 1320 1321 ts->stat = SAS_OPEN_REJECT; 1322 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1323 goto out; 1324 } 1325 1326 if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK && 1327 !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) { 1328 1329 slot_err_v1_hw(hisi_hba, task, slot); 1330 if (unlikely(slot->abort)) { 1331 queue_work(hisi_hba->wq, &slot->abort_slot); 1332 /* immediately return and do not complete */ 1333 return ts->stat; 1334 } 1335 goto out; 1336 } 1337 1338 switch (task->task_proto) { 1339 case SAS_PROTOCOL_SSP: 1340 { 1341 struct ssp_response_iu *iu = slot->status_buffer + 1342 sizeof(struct hisi_sas_err_record); 1343 sas_ssp_task_response(dev, task, iu); 1344 break; 1345 } 1346 case SAS_PROTOCOL_SMP: 1347 { 1348 void *to; 1349 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1350 1351 ts->stat = SAM_STAT_GOOD; 1352 to = kmap_atomic(sg_page(sg_resp)); 1353 1354 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1355 DMA_FROM_DEVICE); 1356 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1357 DMA_TO_DEVICE); 1358 memcpy(to + sg_resp->offset, 1359 slot->status_buffer + 1360 sizeof(struct hisi_sas_err_record), 1361 sg_dma_len(sg_resp)); 1362 kunmap_atomic(to); 1363 break; 1364 } 1365 case SAS_PROTOCOL_SATA: 1366 case SAS_PROTOCOL_STP: 1367 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1368 dev_err(dev, "slot complete: SATA/STP not supported"); 1369 break; 1370 1371 default: 1372 ts->stat = SAM_STAT_CHECK_CONDITION; 1373 break; 1374 } 1375 1376 if (!slot->port->port_attached) { 1377 dev_err(dev, "slot complete: port %d has removed\n", 1378 slot->port->sas_port.id); 1379 ts->stat = SAS_PHY_DOWN; 1380 } 1381 1382 out: 1383 if (sas_dev && sas_dev->running_req) 1384 sas_dev->running_req--; 1385 1386 hisi_sas_slot_task_free(hisi_hba, task, slot); 1387 sts = ts->stat; 1388 1389 if (task->task_done) 1390 task->task_done(task); 1391 1392 return sts; 1393 } 1394 1395 /* Interrupts */ 1396 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p) 1397 { 1398 struct hisi_sas_phy *phy = p; 1399 struct hisi_hba *hisi_hba = phy->hisi_hba; 1400 struct device *dev = &hisi_hba->pdev->dev; 1401 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1402 int i, phy_no = sas_phy->id; 1403 u32 irq_value, context, port_id, link_rate; 1404 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1405 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; 1406 irqreturn_t res = IRQ_HANDLED; 1407 1408 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1409 if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) { 1410 dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n", 1411 irq_value); 1412 res = IRQ_NONE; 1413 goto end; 1414 } 1415 1416 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1417 if (context & 1 << phy_no) { 1418 dev_err(dev, "phyup: phy%d SATA attached equipment\n", 1419 phy_no); 1420 goto end; 1421 } 1422 1423 port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no)) 1424 & 0xf; 1425 if (port_id == 0xf) { 1426 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1427 res = IRQ_NONE; 1428 goto end; 1429 } 1430 1431 for (i = 0; i < 6; i++) { 1432 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1433 RX_IDAF_DWORD0 + (i * 4)); 1434 frame_rcvd[i] = __swab32(idaf); 1435 } 1436 1437 /* Get the linkrate */ 1438 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1439 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1440 sas_phy->linkrate = link_rate; 1441 sas_phy->oob_mode = SAS_OOB_MODE; 1442 memcpy(sas_phy->attached_sas_addr, 1443 &id->sas_addr, SAS_ADDR_SIZE); 1444 dev_info(dev, "phyup: phy%d link_rate=%d\n", 1445 phy_no, link_rate); 1446 phy->port_id = port_id; 1447 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1448 phy->phy_type |= PORT_TYPE_SAS; 1449 phy->phy_attached = 1; 1450 phy->identify.device_type = id->dev_type; 1451 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1452 if (phy->identify.device_type == SAS_END_DEVICE) 1453 phy->identify.target_port_protocols = 1454 SAS_PROTOCOL_SSP; 1455 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1456 phy->identify.target_port_protocols = 1457 SAS_PROTOCOL_SMP; 1458 queue_work(hisi_hba->wq, &phy->phyup_ws); 1459 1460 end: 1461 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, 1462 CHL_INT2_SL_PHY_ENA_MSK); 1463 1464 if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) { 1465 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1466 1467 chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK; 1468 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0); 1469 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee); 1470 } 1471 1472 return res; 1473 } 1474 1475 static irqreturn_t int_bcast_v1_hw(int irq, void *p) 1476 { 1477 struct hisi_sas_phy *phy = p; 1478 struct hisi_hba *hisi_hba = phy->hisi_hba; 1479 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1480 struct sas_ha_struct *sha = &hisi_hba->sha; 1481 struct device *dev = &hisi_hba->pdev->dev; 1482 int phy_no = sas_phy->id; 1483 u32 irq_value; 1484 irqreturn_t res = IRQ_HANDLED; 1485 1486 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1487 1488 if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) { 1489 dev_err(dev, "bcast: irq_value = %x not set enable bit", 1490 irq_value); 1491 res = IRQ_NONE; 1492 goto end; 1493 } 1494 1495 sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1496 1497 end: 1498 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, 1499 CHL_INT2_SL_RX_BC_ACK_MSK); 1500 1501 return res; 1502 } 1503 1504 static irqreturn_t int_abnormal_v1_hw(int irq, void *p) 1505 { 1506 struct hisi_sas_phy *phy = p; 1507 struct hisi_hba *hisi_hba = phy->hisi_hba; 1508 struct device *dev = &hisi_hba->pdev->dev; 1509 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1510 u32 irq_value, irq_mask_old; 1511 int phy_no = sas_phy->id; 1512 1513 /* mask_int0 */ 1514 irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK); 1515 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff); 1516 1517 /* read int0 */ 1518 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1519 1520 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) { 1521 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1522 1523 hisi_sas_phy_down(hisi_hba, phy_no, 1524 (phy_state & 1 << phy_no) ? 1 : 0); 1525 } 1526 1527 if (irq_value & CHL_INT0_ID_TIMEOUT_MSK) 1528 dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n", 1529 phy_no); 1530 1531 if (irq_value & CHL_INT0_DWS_LOST_MSK) 1532 dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no); 1533 1534 if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK) 1535 dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n", 1536 phy_no); 1537 1538 if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK || 1539 irq_value & CHL_INT0_SL_OPAF_FAIL_MSK) 1540 dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n", 1541 phy_no); 1542 1543 if (irq_value & CHL_INT0_SL_PS_FAIL_OFF) 1544 dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no); 1545 1546 /* write to zero */ 1547 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value); 1548 1549 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) 1550 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 1551 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK); 1552 else 1553 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 1554 irq_mask_old); 1555 1556 return IRQ_HANDLED; 1557 } 1558 1559 static irqreturn_t cq_interrupt_v1_hw(int irq, void *p) 1560 { 1561 struct hisi_sas_cq *cq = p; 1562 struct hisi_hba *hisi_hba = cq->hisi_hba; 1563 struct hisi_sas_slot *slot; 1564 int queue = cq->id; 1565 struct hisi_sas_complete_v1_hdr *complete_queue = 1566 (struct hisi_sas_complete_v1_hdr *) 1567 hisi_hba->complete_hdr[queue]; 1568 u32 irq_value, rd_point, wr_point; 1569 1570 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC); 1571 1572 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1573 1574 rd_point = hisi_sas_read32(hisi_hba, 1575 COMPL_Q_0_RD_PTR + (0x14 * queue)); 1576 wr_point = hisi_sas_read32(hisi_hba, 1577 COMPL_Q_0_WR_PTR + (0x14 * queue)); 1578 1579 while (rd_point != wr_point) { 1580 struct hisi_sas_complete_v1_hdr *complete_hdr; 1581 int idx; 1582 u32 cmplt_hdr_data; 1583 1584 complete_hdr = &complete_queue[rd_point]; 1585 cmplt_hdr_data = cpu_to_le32(complete_hdr->data); 1586 idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >> 1587 CMPLT_HDR_IPTT_OFF; 1588 slot = &hisi_hba->slot_info[idx]; 1589 1590 /* The completion queue and queue slot index are not 1591 * necessarily the same as the delivery queue and 1592 * queue slot index. 1593 */ 1594 slot->cmplt_queue_slot = rd_point; 1595 slot->cmplt_queue = queue; 1596 slot_complete_v1_hw(hisi_hba, slot, 0); 1597 1598 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1599 rd_point = 0; 1600 } 1601 1602 /* update rd_point */ 1603 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1604 1605 return IRQ_HANDLED; 1606 } 1607 1608 static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) 1609 { 1610 struct hisi_hba *hisi_hba = p; 1611 struct device *dev = &hisi_hba->pdev->dev; 1612 u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); 1613 1614 if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) { 1615 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1616 1617 panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n", 1618 dev_name(dev), ecc_err); 1619 } 1620 1621 if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) { 1622 u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) & 1623 HGC_DQ_ECC_ADDR_BAD_MSK) >> 1624 HGC_DQ_ECC_ADDR_BAD_OFF; 1625 1626 panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n", 1627 dev_name(dev), addr); 1628 } 1629 1630 if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) { 1631 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1632 1633 panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n", 1634 dev_name(dev), ecc_err); 1635 } 1636 1637 if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) { 1638 u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) & 1639 HGC_IOST_ECC_ADDR_BAD_MSK) >> 1640 HGC_IOST_ECC_ADDR_BAD_OFF; 1641 1642 panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n", 1643 dev_name(dev), addr); 1644 } 1645 1646 if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) { 1647 u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) & 1648 HGC_ITCT_ECC_ADDR_BAD_MSK) >> 1649 HGC_ITCT_ECC_ADDR_BAD_OFF; 1650 1651 panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n", 1652 dev_name(dev), addr); 1653 } 1654 1655 if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) { 1656 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1657 1658 panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n", 1659 dev_name(dev), ecc_err); 1660 } 1661 1662 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f); 1663 1664 return IRQ_HANDLED; 1665 } 1666 1667 static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) 1668 { 1669 struct hisi_hba *hisi_hba = p; 1670 struct device *dev = &hisi_hba->pdev->dev; 1671 u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2); 1672 u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO); 1673 1674 if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK) 1675 panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n", 1676 dev_name(dev), axi_info); 1677 1678 if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK) 1679 panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n", 1680 dev_name(dev), axi_info); 1681 1682 if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK) 1683 panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n", 1684 dev_name(dev), axi_info); 1685 1686 if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK) 1687 panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n", 1688 dev_name(dev), axi_info); 1689 1690 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000); 1691 1692 return IRQ_HANDLED; 1693 } 1694 1695 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { 1696 int_bcast_v1_hw, 1697 int_phyup_v1_hw, 1698 int_abnormal_v1_hw 1699 }; 1700 1701 static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = { 1702 fatal_ecc_int_v1_hw, 1703 fatal_axi_int_v1_hw 1704 }; 1705 1706 static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba) 1707 { 1708 struct platform_device *pdev = hisi_hba->pdev; 1709 struct device *dev = &pdev->dev; 1710 int i, j, irq, rc, idx; 1711 1712 for (i = 0; i < hisi_hba->n_phy; i++) { 1713 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 1714 1715 idx = i * HISI_SAS_PHY_INT_NR; 1716 for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) { 1717 irq = platform_get_irq(pdev, idx); 1718 if (!irq) { 1719 dev_err(dev, 1720 "irq init: fail map phy interrupt %d\n", 1721 idx); 1722 return -ENOENT; 1723 } 1724 1725 rc = devm_request_irq(dev, irq, phy_interrupts[j], 0, 1726 DRV_NAME " phy", phy); 1727 if (rc) { 1728 dev_err(dev, "irq init: could not request " 1729 "phy interrupt %d, rc=%d\n", 1730 irq, rc); 1731 return -ENOENT; 1732 } 1733 } 1734 } 1735 1736 idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR; 1737 for (i = 0; i < hisi_hba->queue_count; i++, idx++) { 1738 irq = platform_get_irq(pdev, idx); 1739 if (!irq) { 1740 dev_err(dev, "irq init: could not map cq interrupt %d\n", 1741 idx); 1742 return -ENOENT; 1743 } 1744 1745 rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0, 1746 DRV_NAME " cq", &hisi_hba->cq[i]); 1747 if (rc) { 1748 dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n", 1749 irq, rc); 1750 return -ENOENT; 1751 } 1752 } 1753 1754 idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count; 1755 for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) { 1756 irq = platform_get_irq(pdev, idx); 1757 if (!irq) { 1758 dev_err(dev, "irq init: could not map fatal interrupt %d\n", 1759 idx); 1760 return -ENOENT; 1761 } 1762 1763 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0, 1764 DRV_NAME " fatal", hisi_hba); 1765 if (rc) { 1766 dev_err(dev, 1767 "irq init: could not request fatal interrupt %d, rc=%d\n", 1768 irq, rc); 1769 return -ENOENT; 1770 } 1771 } 1772 1773 return 0; 1774 } 1775 1776 static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba) 1777 { 1778 int i; 1779 u32 val; 1780 1781 for (i = 0; i < hisi_hba->n_phy; i++) { 1782 /* Clear interrupt status */ 1783 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0); 1784 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val); 1785 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1); 1786 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val); 1787 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2); 1788 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val); 1789 1790 /* Unmask interrupt */ 1791 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee); 1792 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff); 1793 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a); 1794 1795 /* bypass chip bug mask abnormal intr */ 1796 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 1797 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK); 1798 } 1799 1800 return 0; 1801 } 1802 1803 static int hisi_sas_v1_init(struct hisi_hba *hisi_hba) 1804 { 1805 int rc; 1806 1807 rc = hw_init_v1_hw(hisi_hba); 1808 if (rc) 1809 return rc; 1810 1811 rc = interrupt_init_v1_hw(hisi_hba); 1812 if (rc) 1813 return rc; 1814 1815 rc = interrupt_openall_v1_hw(hisi_hba); 1816 if (rc) 1817 return rc; 1818 1819 phys_init_v1_hw(hisi_hba); 1820 1821 return 0; 1822 } 1823 1824 static const struct hisi_sas_hw hisi_sas_v1_hw = { 1825 .hw_init = hisi_sas_v1_init, 1826 .setup_itct = setup_itct_v1_hw, 1827 .sl_notify = sl_notify_v1_hw, 1828 .free_device = free_device_v1_hw, 1829 .prep_smp = prep_smp_v1_hw, 1830 .prep_ssp = prep_ssp_v1_hw, 1831 .get_free_slot = get_free_slot_v1_hw, 1832 .start_delivery = start_delivery_v1_hw, 1833 .slot_complete = slot_complete_v1_hw, 1834 .phy_enable = enable_phy_v1_hw, 1835 .phy_disable = disable_phy_v1_hw, 1836 .phy_hard_reset = phy_hard_reset_v1_hw, 1837 .get_wideport_bitmap = get_wideport_bitmap_v1_hw, 1838 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V1_HW, 1839 .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr), 1840 }; 1841 1842 static int hisi_sas_v1_probe(struct platform_device *pdev) 1843 { 1844 return hisi_sas_probe(pdev, &hisi_sas_v1_hw); 1845 } 1846 1847 static int hisi_sas_v1_remove(struct platform_device *pdev) 1848 { 1849 return hisi_sas_remove(pdev); 1850 } 1851 1852 static const struct of_device_id sas_v1_of_match[] = { 1853 { .compatible = "hisilicon,hip05-sas-v1",}, 1854 {}, 1855 }; 1856 MODULE_DEVICE_TABLE(of, sas_v1_of_match); 1857 1858 static const struct acpi_device_id sas_v1_acpi_match[] = { 1859 { "HISI0161", 0 }, 1860 { } 1861 }; 1862 1863 MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match); 1864 1865 static struct platform_driver hisi_sas_v1_driver = { 1866 .probe = hisi_sas_v1_probe, 1867 .remove = hisi_sas_v1_remove, 1868 .driver = { 1869 .name = DRV_NAME, 1870 .of_match_table = sas_v1_of_match, 1871 .acpi_match_table = ACPI_PTR(sas_v1_acpi_match), 1872 }, 1873 }; 1874 1875 module_platform_driver(hisi_sas_v1_driver); 1876 1877 MODULE_LICENSE("GPL"); 1878 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 1879 MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver"); 1880 MODULE_ALIAS("platform:" DRV_NAME); 1881