1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Generic Generic NCR5380 driver 4 * 5 * Copyright 1993, Drew Eckhardt 6 * Visionary Computing 7 * (Unix and Linux consulting and custom programming) 8 * drew@colorado.edu 9 * +1 (303) 440-4894 10 * 11 * NCR53C400 extensions (c) 1994,1995,1996, Kevin Lentin 12 * K.Lentin@cs.monash.edu.au 13 * 14 * NCR53C400A extensions (c) 1996, Ingmar Baumgart 15 * ingmar@gonzo.schwaben.de 16 * 17 * DTC3181E extensions (c) 1997, Ronald van Cuijlenborg 18 * ronald.van.cuijlenborg@tip.nl or nutty@dds.nl 19 * 20 * Added ISAPNP support for DTC436 adapters, 21 * Thomas Sailer, sailer@ife.ee.ethz.ch 22 * 23 * See Documentation/scsi/g_NCR5380.rst for more info. 24 */ 25 26 #include <asm/io.h> 27 #include <linux/blkdev.h> 28 #include <linux/module.h> 29 #include <scsi/scsi_host.h> 30 #include <linux/init.h> 31 #include <linux/ioport.h> 32 #include <linux/isa.h> 33 #include <linux/pnp.h> 34 #include <linux/interrupt.h> 35 36 /* Definitions for the core NCR5380 driver. */ 37 38 #define NCR5380_read(reg) \ 39 ioread8(hostdata->io + hostdata->offset + (reg)) 40 #define NCR5380_write(reg, value) \ 41 iowrite8(value, hostdata->io + hostdata->offset + (reg)) 42 43 #define NCR5380_implementation_fields \ 44 int offset; \ 45 int c400_ctl_status; \ 46 int c400_blk_cnt; \ 47 int c400_host_buf; \ 48 int io_width; \ 49 int pdma_residual; \ 50 int board 51 52 #define NCR5380_dma_xfer_len generic_NCR5380_dma_xfer_len 53 #define NCR5380_dma_recv_setup generic_NCR5380_precv 54 #define NCR5380_dma_send_setup generic_NCR5380_psend 55 #define NCR5380_dma_residual generic_NCR5380_dma_residual 56 57 #define NCR5380_intr generic_NCR5380_intr 58 #define NCR5380_queue_command generic_NCR5380_queue_command 59 #define NCR5380_abort generic_NCR5380_abort 60 #define NCR5380_host_reset generic_NCR5380_host_reset 61 #define NCR5380_info generic_NCR5380_info 62 63 #define NCR5380_io_delay(x) udelay(x) 64 65 #include "NCR5380.h" 66 67 #define DRV_MODULE_NAME "g_NCR5380" 68 69 #define NCR53C400_mem_base 0x3880 70 #define NCR53C400_host_buffer 0x3900 71 #define NCR53C400_region_size 0x3a00 72 73 #define BOARD_NCR5380 0 74 #define BOARD_NCR53C400 1 75 #define BOARD_NCR53C400A 2 76 #define BOARD_DTC3181E 3 77 #define BOARD_HP_C2502 4 78 79 #define IRQ_AUTO 254 80 81 #define MAX_CARDS 8 82 #define DMA_MAX_SIZE 32768 83 84 /* old-style parameters for compatibility */ 85 static int ncr_irq = -1; 86 static int ncr_addr; 87 static int ncr_5380; 88 static int ncr_53c400; 89 static int ncr_53c400a; 90 static int dtc_3181e; 91 static int hp_c2502; 92 module_param_hw(ncr_irq, int, irq, 0); 93 module_param_hw(ncr_addr, int, ioport, 0); 94 module_param(ncr_5380, int, 0); 95 module_param(ncr_53c400, int, 0); 96 module_param(ncr_53c400a, int, 0); 97 module_param(dtc_3181e, int, 0); 98 module_param(hp_c2502, int, 0); 99 100 static int irq[] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 101 module_param_hw_array(irq, int, irq, NULL, 0); 102 MODULE_PARM_DESC(irq, "IRQ number(s) (0=none, 254=auto [default])"); 103 104 static int base[] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 105 module_param_hw_array(base, int, ioport, NULL, 0); 106 MODULE_PARM_DESC(base, "base address(es)"); 107 108 static int card[] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 109 module_param_array(card, int, NULL, 0); 110 MODULE_PARM_DESC(card, "card type (0=NCR5380, 1=NCR53C400, 2=NCR53C400A, 3=DTC3181E, 4=HP C2502)"); 111 112 MODULE_ALIAS("g_NCR5380_mmio"); 113 MODULE_DESCRIPTION("Generic NCR5380/NCR53C400 SCSI driver"); 114 MODULE_LICENSE("GPL"); 115 116 static void g_NCR5380_trigger_irq(struct Scsi_Host *instance) 117 { 118 struct NCR5380_hostdata *hostdata = shost_priv(instance); 119 120 /* 121 * An interrupt is triggered whenever BSY = false, SEL = true 122 * and a bit set in the SELECT_ENABLE_REG is asserted on the 123 * SCSI bus. 124 * 125 * Note that the bus is only driven when the phase control signals 126 * (I/O, C/D, and MSG) match those in the TCR. 127 */ 128 NCR5380_write(TARGET_COMMAND_REG, 129 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK)); 130 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); 131 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask); 132 NCR5380_write(INITIATOR_COMMAND_REG, 133 ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_SEL); 134 135 msleep(1); 136 137 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); 138 NCR5380_write(SELECT_ENABLE_REG, 0); 139 NCR5380_write(TARGET_COMMAND_REG, 0); 140 } 141 142 /** 143 * g_NCR5380_probe_irq - find the IRQ of a NCR5380 or equivalent 144 * @instance: SCSI host instance 145 * 146 * Autoprobe for the IRQ line used by the card by triggering an IRQ 147 * and then looking to see what interrupt actually turned up. 148 */ 149 150 static int g_NCR5380_probe_irq(struct Scsi_Host *instance) 151 { 152 struct NCR5380_hostdata *hostdata = shost_priv(instance); 153 int irq_mask, irq; 154 155 NCR5380_read(RESET_PARITY_INTERRUPT_REG); 156 irq_mask = probe_irq_on(); 157 g_NCR5380_trigger_irq(instance); 158 irq = probe_irq_off(irq_mask); 159 NCR5380_read(RESET_PARITY_INTERRUPT_REG); 160 161 if (irq <= 0) 162 return NO_IRQ; 163 return irq; 164 } 165 166 /* 167 * Configure I/O address of 53C400A or DTC436 by writing magic numbers 168 * to ports 0x779 and 0x379. 169 */ 170 static void magic_configure(int idx, u8 irq, u8 magic[]) 171 { 172 u8 cfg = 0; 173 174 outb(magic[0], 0x779); 175 outb(magic[1], 0x379); 176 outb(magic[2], 0x379); 177 outb(magic[3], 0x379); 178 outb(magic[4], 0x379); 179 180 if (irq == 9) 181 irq = 2; 182 183 if (idx >= 0 && idx <= 7) 184 cfg = 0x80 | idx | (irq << 4); 185 outb(cfg, 0x379); 186 } 187 188 static irqreturn_t legacy_empty_irq_handler(int irq, void *dev_id) 189 { 190 return IRQ_HANDLED; 191 } 192 193 static int legacy_find_free_irq(int *irq_table) 194 { 195 while (*irq_table != -1) { 196 if (!request_irq(*irq_table, legacy_empty_irq_handler, 197 IRQF_PROBE_SHARED, "Test IRQ", 198 (void *)irq_table)) { 199 free_irq(*irq_table, (void *) irq_table); 200 return *irq_table; 201 } 202 irq_table++; 203 } 204 return -1; 205 } 206 207 static unsigned int ncr_53c400a_ports[] = { 208 0x280, 0x290, 0x300, 0x310, 0x330, 0x340, 0x348, 0x350, 0 209 }; 210 static unsigned int dtc_3181e_ports[] = { 211 0x220, 0x240, 0x280, 0x2a0, 0x2c0, 0x300, 0x320, 0x340, 0 212 }; 213 static u8 ncr_53c400a_magic[] = { /* 53C400A & DTC436 */ 214 0x59, 0xb9, 0xc5, 0xae, 0xa6 215 }; 216 static u8 hp_c2502_magic[] = { /* HP C2502 */ 217 0x0f, 0x22, 0xf0, 0x20, 0x80 218 }; 219 static int hp_c2502_irqs[] = { 220 9, 5, 7, 3, 4, -1 221 }; 222 223 static int generic_NCR5380_init_one(const struct scsi_host_template *tpnt, 224 struct device *pdev, int base, int irq, int board) 225 { 226 bool is_pmio = base <= 0xffff; 227 int ret; 228 int flags = 0; 229 unsigned int *ports = NULL; 230 u8 *magic = NULL; 231 int i; 232 int port_idx = -1; 233 unsigned long region_size; 234 struct Scsi_Host *instance; 235 struct NCR5380_hostdata *hostdata; 236 u8 __iomem *iomem; 237 238 switch (board) { 239 case BOARD_NCR5380: 240 flags = FLAG_NO_PSEUDO_DMA | FLAG_DMA_FIXUP; 241 break; 242 case BOARD_NCR53C400A: 243 ports = ncr_53c400a_ports; 244 magic = ncr_53c400a_magic; 245 break; 246 case BOARD_HP_C2502: 247 ports = ncr_53c400a_ports; 248 magic = hp_c2502_magic; 249 break; 250 case BOARD_DTC3181E: 251 ports = dtc_3181e_ports; 252 magic = ncr_53c400a_magic; 253 break; 254 } 255 256 if (is_pmio && ports && magic) { 257 /* wakeup sequence for the NCR53C400A and DTC3181E */ 258 259 /* Disable the adapter and look for a free io port */ 260 magic_configure(-1, 0, magic); 261 262 region_size = 16; 263 if (base) 264 for (i = 0; ports[i]; i++) { 265 if (base == ports[i]) { /* index found */ 266 if (!request_region(ports[i], 267 region_size, 268 "ncr53c80")) 269 return -EBUSY; 270 break; 271 } 272 } 273 else 274 for (i = 0; ports[i]; i++) { 275 if (!request_region(ports[i], region_size, 276 "ncr53c80")) 277 continue; 278 if (inb(ports[i]) == 0xff) 279 break; 280 release_region(ports[i], region_size); 281 } 282 if (ports[i]) { 283 /* At this point we have our region reserved */ 284 magic_configure(i, 0, magic); /* no IRQ yet */ 285 base = ports[i]; 286 outb(0xc0, base + 9); 287 if (inb(base + 9) != 0x80) { 288 ret = -ENODEV; 289 goto out_release; 290 } 291 port_idx = i; 292 } else 293 return -EINVAL; 294 } else if (is_pmio) { 295 /* NCR5380 - no configuration, just grab */ 296 region_size = 8; 297 if (!base || !request_region(base, region_size, "ncr5380")) 298 return -EBUSY; 299 } else { /* MMIO */ 300 region_size = NCR53C400_region_size; 301 if (!request_mem_region(base, region_size, "ncr5380")) 302 return -EBUSY; 303 } 304 305 if (is_pmio) 306 iomem = ioport_map(base, region_size); 307 else 308 iomem = ioremap(base, region_size); 309 310 if (!iomem) { 311 ret = -ENOMEM; 312 goto out_release; 313 } 314 315 instance = scsi_host_alloc(tpnt, sizeof(struct NCR5380_hostdata)); 316 if (instance == NULL) { 317 ret = -ENOMEM; 318 goto out_unmap; 319 } 320 hostdata = shost_priv(instance); 321 322 hostdata->board = board; 323 hostdata->io = iomem; 324 hostdata->region_size = region_size; 325 326 if (is_pmio) { 327 hostdata->io_port = base; 328 hostdata->io_width = 1; /* 8-bit PDMA by default */ 329 hostdata->offset = 0; 330 331 /* 332 * On NCR53C400 boards, NCR5380 registers are mapped 8 past 333 * the base address. 334 */ 335 switch (board) { 336 case BOARD_NCR53C400: 337 hostdata->io_port += 8; 338 hostdata->c400_ctl_status = 0; 339 hostdata->c400_blk_cnt = 1; 340 hostdata->c400_host_buf = 4; 341 break; 342 case BOARD_DTC3181E: 343 hostdata->io_width = 2; /* 16-bit PDMA */ 344 fallthrough; 345 case BOARD_NCR53C400A: 346 case BOARD_HP_C2502: 347 hostdata->c400_ctl_status = 9; 348 hostdata->c400_blk_cnt = 10; 349 hostdata->c400_host_buf = 8; 350 break; 351 } 352 } else { 353 hostdata->base = base; 354 hostdata->offset = NCR53C400_mem_base; 355 switch (board) { 356 case BOARD_NCR53C400: 357 hostdata->c400_ctl_status = 0x100; 358 hostdata->c400_blk_cnt = 0x101; 359 hostdata->c400_host_buf = 0x104; 360 break; 361 case BOARD_DTC3181E: 362 case BOARD_NCR53C400A: 363 case BOARD_HP_C2502: 364 pr_err(DRV_MODULE_NAME ": unknown register offsets\n"); 365 ret = -EINVAL; 366 goto out_unregister; 367 } 368 } 369 370 /* Check for vacant slot */ 371 NCR5380_write(MODE_REG, 0); 372 if (NCR5380_read(MODE_REG) != 0) { 373 ret = -ENODEV; 374 goto out_unregister; 375 } 376 377 ret = NCR5380_init(instance, flags | FLAG_LATE_DMA_SETUP); 378 if (ret) 379 goto out_unregister; 380 381 switch (board) { 382 case BOARD_NCR53C400: 383 case BOARD_DTC3181E: 384 case BOARD_NCR53C400A: 385 case BOARD_HP_C2502: 386 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); 387 } 388 389 NCR5380_maybe_reset_bus(instance); 390 391 /* Compatibility with documented NCR5380 kernel parameters */ 392 if (irq == 255 || irq == 0) 393 irq = NO_IRQ; 394 else if (irq == -1) 395 irq = IRQ_AUTO; 396 397 if (board == BOARD_HP_C2502) { 398 int *irq_table = hp_c2502_irqs; 399 int board_irq = -1; 400 401 switch (irq) { 402 case NO_IRQ: 403 board_irq = 0; 404 break; 405 case IRQ_AUTO: 406 board_irq = legacy_find_free_irq(irq_table); 407 break; 408 default: 409 while (*irq_table != -1) 410 if (*irq_table++ == irq) 411 board_irq = irq; 412 } 413 414 if (board_irq <= 0) { 415 board_irq = 0; 416 irq = NO_IRQ; 417 } 418 419 magic_configure(port_idx, board_irq, magic); 420 } 421 422 if (irq == IRQ_AUTO) { 423 instance->irq = g_NCR5380_probe_irq(instance); 424 if (instance->irq == NO_IRQ) 425 shost_printk(KERN_INFO, instance, "no irq detected\n"); 426 } else { 427 instance->irq = irq; 428 if (instance->irq == NO_IRQ) 429 shost_printk(KERN_INFO, instance, "no irq provided\n"); 430 } 431 432 if (instance->irq != NO_IRQ) { 433 if (request_irq(instance->irq, generic_NCR5380_intr, 434 0, "NCR5380", instance)) { 435 instance->irq = NO_IRQ; 436 shost_printk(KERN_INFO, instance, 437 "irq %d denied\n", instance->irq); 438 } else { 439 shost_printk(KERN_INFO, instance, 440 "irq %d acquired\n", instance->irq); 441 } 442 } 443 444 ret = scsi_add_host(instance, pdev); 445 if (ret) 446 goto out_free_irq; 447 scsi_scan_host(instance); 448 dev_set_drvdata(pdev, instance); 449 return 0; 450 451 out_free_irq: 452 if (instance->irq != NO_IRQ) 453 free_irq(instance->irq, instance); 454 NCR5380_exit(instance); 455 out_unregister: 456 scsi_host_put(instance); 457 out_unmap: 458 iounmap(iomem); 459 out_release: 460 if (is_pmio) 461 release_region(base, region_size); 462 else 463 release_mem_region(base, region_size); 464 return ret; 465 } 466 467 static void generic_NCR5380_release_resources(struct Scsi_Host *instance) 468 { 469 struct NCR5380_hostdata *hostdata = shost_priv(instance); 470 void __iomem *iomem = hostdata->io; 471 unsigned long io_port = hostdata->io_port; 472 unsigned long base = hostdata->base; 473 unsigned long region_size = hostdata->region_size; 474 475 scsi_remove_host(instance); 476 if (instance->irq != NO_IRQ) 477 free_irq(instance->irq, instance); 478 NCR5380_exit(instance); 479 scsi_host_put(instance); 480 iounmap(iomem); 481 if (io_port) 482 release_region(io_port, region_size); 483 else 484 release_mem_region(base, region_size); 485 } 486 487 /* wait_for_53c80_access - wait for 53C80 registers to become accessible 488 * @hostdata: scsi host private data 489 * 490 * The registers within the 53C80 logic block are inaccessible until 491 * bit 7 in the 53C400 control status register gets asserted. 492 */ 493 494 static void wait_for_53c80_access(struct NCR5380_hostdata *hostdata) 495 { 496 int count = 10000; 497 498 do { 499 if (hostdata->board == BOARD_DTC3181E) 500 udelay(4); /* DTC436 chip hangs without this */ 501 if (NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG) 502 return; 503 } while (--count > 0); 504 505 scmd_printk(KERN_ERR, hostdata->connected, 506 "53c80 registers not accessible, device will be reset\n"); 507 NCR5380_write(hostdata->c400_ctl_status, CSR_RESET); 508 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); 509 } 510 511 /** 512 * generic_NCR5380_precv - pseudo DMA receive 513 * @hostdata: scsi host private data 514 * @dst: buffer to write into 515 * @len: transfer size 516 * 517 * Perform a pseudo DMA mode receive from a 53C400 or equivalent device. 518 */ 519 520 static inline int generic_NCR5380_precv(struct NCR5380_hostdata *hostdata, 521 unsigned char *dst, int len) 522 { 523 int residual; 524 int start = 0; 525 526 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE | CSR_TRANS_DIR); 527 NCR5380_write(hostdata->c400_blk_cnt, len / 128); 528 529 do { 530 if (start == len - 128) { 531 /* Ignore End of DMA interrupt for the final buffer */ 532 if (NCR5380_poll_politely(hostdata, hostdata->c400_ctl_status, 533 CSR_HOST_BUF_NOT_RDY, 0, 0) < 0) 534 break; 535 } else { 536 if (NCR5380_poll_politely2(hostdata, hostdata->c400_ctl_status, 537 CSR_HOST_BUF_NOT_RDY, 0, 538 hostdata->c400_ctl_status, 539 CSR_GATED_53C80_IRQ, 540 CSR_GATED_53C80_IRQ, 0) < 0 || 541 NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) 542 break; 543 } 544 545 if (hostdata->io_port && hostdata->io_width == 2) 546 insw(hostdata->io_port + hostdata->c400_host_buf, 547 dst + start, 64); 548 else if (hostdata->io_port) 549 insb(hostdata->io_port + hostdata->c400_host_buf, 550 dst + start, 128); 551 else 552 memcpy_fromio(dst + start, 553 hostdata->io + NCR53C400_host_buffer, 128); 554 start += 128; 555 } while (start < len); 556 557 residual = len - start; 558 559 if (residual != 0) { 560 /* 53c80 interrupt or transfer timeout. Reset 53c400 logic. */ 561 NCR5380_write(hostdata->c400_ctl_status, CSR_RESET); 562 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); 563 } 564 wait_for_53c80_access(hostdata); 565 566 if (residual == 0 && NCR5380_poll_politely(hostdata, BUS_AND_STATUS_REG, 567 BASR_END_DMA_TRANSFER, 568 BASR_END_DMA_TRANSFER, 569 0) < 0) 570 scmd_printk(KERN_ERR, hostdata->connected, "%s: End of DMA timeout\n", 571 __func__); 572 573 hostdata->pdma_residual = residual; 574 575 return 0; 576 } 577 578 /** 579 * generic_NCR5380_psend - pseudo DMA send 580 * @hostdata: scsi host private data 581 * @src: buffer to read from 582 * @len: transfer size 583 * 584 * Perform a pseudo DMA mode send to a 53C400 or equivalent device. 585 */ 586 587 static inline int generic_NCR5380_psend(struct NCR5380_hostdata *hostdata, 588 unsigned char *src, int len) 589 { 590 int residual; 591 int start = 0; 592 593 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); 594 NCR5380_write(hostdata->c400_blk_cnt, len / 128); 595 596 do { 597 if (NCR5380_poll_politely2(hostdata, hostdata->c400_ctl_status, 598 CSR_HOST_BUF_NOT_RDY, 0, 599 hostdata->c400_ctl_status, 600 CSR_GATED_53C80_IRQ, 601 CSR_GATED_53C80_IRQ, 0) < 0 || 602 NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) { 603 /* Both 128 B buffers are in use */ 604 if (start >= 128) 605 start -= 128; 606 if (start >= 128) 607 start -= 128; 608 break; 609 } 610 611 if (start >= len && NCR5380_read(hostdata->c400_blk_cnt) == 0) 612 break; 613 614 if (NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ) { 615 /* Host buffer is empty, other one is in use */ 616 if (start >= 128) 617 start -= 128; 618 break; 619 } 620 621 if (start >= len) 622 continue; 623 624 if (hostdata->io_port && hostdata->io_width == 2) 625 outsw(hostdata->io_port + hostdata->c400_host_buf, 626 src + start, 64); 627 else if (hostdata->io_port) 628 outsb(hostdata->io_port + hostdata->c400_host_buf, 629 src + start, 128); 630 else 631 memcpy_toio(hostdata->io + NCR53C400_host_buffer, 632 src + start, 128); 633 start += 128; 634 } while (1); 635 636 residual = len - start; 637 638 if (residual != 0) { 639 /* 53c80 interrupt or transfer timeout. Reset 53c400 logic. */ 640 NCR5380_write(hostdata->c400_ctl_status, CSR_RESET); 641 NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); 642 } 643 wait_for_53c80_access(hostdata); 644 645 if (residual == 0) { 646 if (NCR5380_poll_politely(hostdata, TARGET_COMMAND_REG, 647 TCR_LAST_BYTE_SENT, TCR_LAST_BYTE_SENT, 648 0) < 0) 649 scmd_printk(KERN_ERR, hostdata->connected, 650 "%s: Last Byte Sent timeout\n", __func__); 651 652 if (NCR5380_poll_politely(hostdata, BUS_AND_STATUS_REG, 653 BASR_END_DMA_TRANSFER, BASR_END_DMA_TRANSFER, 654 0) < 0) 655 scmd_printk(KERN_ERR, hostdata->connected, "%s: End of DMA timeout\n", 656 __func__); 657 } 658 659 hostdata->pdma_residual = residual; 660 661 return 0; 662 } 663 664 static int generic_NCR5380_dma_xfer_len(struct NCR5380_hostdata *hostdata, 665 struct scsi_cmnd *cmd) 666 { 667 int transfersize = NCR5380_to_ncmd(cmd)->this_residual; 668 669 if (hostdata->flags & FLAG_NO_PSEUDO_DMA) 670 return 0; 671 672 /* 53C400 datasheet: non-modulo-128-byte transfers should use PIO */ 673 if (transfersize % 128) 674 return 0; 675 676 /* Limit PDMA send to 512 B to avoid random corruption on DTC3181E */ 677 if (hostdata->board == BOARD_DTC3181E && 678 cmd->sc_data_direction == DMA_TO_DEVICE) 679 transfersize = min(transfersize, 512); 680 681 return min(transfersize, DMA_MAX_SIZE); 682 } 683 684 static int generic_NCR5380_dma_residual(struct NCR5380_hostdata *hostdata) 685 { 686 return hostdata->pdma_residual; 687 } 688 689 /* Include the core driver code. */ 690 691 #include "NCR5380.c" 692 693 static const struct scsi_host_template driver_template = { 694 .module = THIS_MODULE, 695 .proc_name = DRV_MODULE_NAME, 696 .name = "Generic NCR5380/NCR53C400 SCSI", 697 .info = generic_NCR5380_info, 698 .queuecommand = generic_NCR5380_queue_command, 699 .eh_abort_handler = generic_NCR5380_abort, 700 .eh_host_reset_handler = generic_NCR5380_host_reset, 701 .can_queue = 16, 702 .this_id = 7, 703 .sg_tablesize = SG_ALL, 704 .cmd_per_lun = 2, 705 .dma_boundary = PAGE_SIZE - 1, 706 .cmd_size = sizeof(struct NCR5380_cmd), 707 .max_sectors = 128, 708 }; 709 710 static int generic_NCR5380_isa_match(struct device *pdev, unsigned int ndev) 711 { 712 int ret = generic_NCR5380_init_one(&driver_template, pdev, base[ndev], 713 irq[ndev], card[ndev]); 714 if (ret) { 715 if (base[ndev]) 716 printk(KERN_WARNING "Card not found at address 0x%03x\n", 717 base[ndev]); 718 return 0; 719 } 720 721 return 1; 722 } 723 724 static void generic_NCR5380_isa_remove(struct device *pdev, 725 unsigned int ndev) 726 { 727 generic_NCR5380_release_resources(dev_get_drvdata(pdev)); 728 dev_set_drvdata(pdev, NULL); 729 } 730 731 static struct isa_driver generic_NCR5380_isa_driver = { 732 .match = generic_NCR5380_isa_match, 733 .remove = generic_NCR5380_isa_remove, 734 .driver = { 735 .name = DRV_MODULE_NAME 736 }, 737 }; 738 739 #ifdef CONFIG_PNP 740 static const struct pnp_device_id generic_NCR5380_pnp_ids[] = { 741 { .id = "DTC436e", .driver_data = BOARD_DTC3181E }, 742 { .id = "" } 743 }; 744 MODULE_DEVICE_TABLE(pnp, generic_NCR5380_pnp_ids); 745 746 static int generic_NCR5380_pnp_probe(struct pnp_dev *pdev, 747 const struct pnp_device_id *id) 748 { 749 int base, irq; 750 751 if (pnp_activate_dev(pdev) < 0) 752 return -EBUSY; 753 754 base = pnp_port_start(pdev, 0); 755 irq = pnp_irq(pdev, 0); 756 757 return generic_NCR5380_init_one(&driver_template, &pdev->dev, base, irq, 758 id->driver_data); 759 } 760 761 static void generic_NCR5380_pnp_remove(struct pnp_dev *pdev) 762 { 763 generic_NCR5380_release_resources(pnp_get_drvdata(pdev)); 764 pnp_set_drvdata(pdev, NULL); 765 } 766 767 static struct pnp_driver generic_NCR5380_pnp_driver = { 768 .name = DRV_MODULE_NAME, 769 .id_table = generic_NCR5380_pnp_ids, 770 .probe = generic_NCR5380_pnp_probe, 771 .remove = generic_NCR5380_pnp_remove, 772 }; 773 #endif /* defined(CONFIG_PNP) */ 774 775 static int pnp_registered, isa_registered; 776 777 static int __init generic_NCR5380_init(void) 778 { 779 int ret = 0; 780 781 /* compatibility with old-style parameters */ 782 if (irq[0] == -1 && base[0] == 0 && card[0] == -1) { 783 irq[0] = ncr_irq; 784 base[0] = ncr_addr; 785 if (ncr_5380) 786 card[0] = BOARD_NCR5380; 787 if (ncr_53c400) 788 card[0] = BOARD_NCR53C400; 789 if (ncr_53c400a) 790 card[0] = BOARD_NCR53C400A; 791 if (dtc_3181e) 792 card[0] = BOARD_DTC3181E; 793 if (hp_c2502) 794 card[0] = BOARD_HP_C2502; 795 } 796 797 #ifdef CONFIG_PNP 798 if (!pnp_register_driver(&generic_NCR5380_pnp_driver)) 799 pnp_registered = 1; 800 #endif 801 ret = isa_register_driver(&generic_NCR5380_isa_driver, MAX_CARDS); 802 if (!ret) 803 isa_registered = 1; 804 805 return (pnp_registered || isa_registered) ? 0 : ret; 806 } 807 808 static void __exit generic_NCR5380_exit(void) 809 { 810 #ifdef CONFIG_PNP 811 if (pnp_registered) 812 pnp_unregister_driver(&generic_NCR5380_pnp_driver); 813 #endif 814 if (isa_registered) 815 isa_unregister_driver(&generic_NCR5380_isa_driver); 816 } 817 818 module_init(generic_NCR5380_init); 819 module_exit(generic_NCR5380_exit); 820