xref: /linux/drivers/scsi/cxlflash/main.h (revision cd43c221bb5eb5a6400a62ae44a9979c8fc6c87e)
1c21e0bbfSMatthew R. Ochs /*
2c21e0bbfSMatthew R. Ochs  * CXL Flash Device Driver
3c21e0bbfSMatthew R. Ochs  *
4c21e0bbfSMatthew R. Ochs  * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
5c21e0bbfSMatthew R. Ochs  *             Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
6c21e0bbfSMatthew R. Ochs  *
7c21e0bbfSMatthew R. Ochs  * Copyright (C) 2015 IBM Corporation
8c21e0bbfSMatthew R. Ochs  *
9c21e0bbfSMatthew R. Ochs  * This program is free software; you can redistribute it and/or
10c21e0bbfSMatthew R. Ochs  * modify it under the terms of the GNU General Public License
11c21e0bbfSMatthew R. Ochs  * as published by the Free Software Foundation; either version
12c21e0bbfSMatthew R. Ochs  * 2 of the License, or (at your option) any later version.
13c21e0bbfSMatthew R. Ochs  */
14c21e0bbfSMatthew R. Ochs 
15c21e0bbfSMatthew R. Ochs #ifndef _CXLFLASH_MAIN_H
16c21e0bbfSMatthew R. Ochs #define _CXLFLASH_MAIN_H
17c21e0bbfSMatthew R. Ochs 
18c21e0bbfSMatthew R. Ochs #include <linux/list.h>
19c21e0bbfSMatthew R. Ochs #include <linux/types.h>
20c21e0bbfSMatthew R. Ochs #include <scsi/scsi.h>
21c21e0bbfSMatthew R. Ochs #include <scsi/scsi_device.h>
22c21e0bbfSMatthew R. Ochs 
23de5d35afSUma Krishnan #include "backend.h"
24de5d35afSUma Krishnan 
25c21e0bbfSMatthew R. Ochs #define CXLFLASH_NAME		"cxlflash"
26c21e0bbfSMatthew R. Ochs #define CXLFLASH_ADAPTER_NAME	"IBM POWER CXL Flash Adapter"
27a834a36bSUma Krishnan #define CXLFLASH_MAX_ADAPTERS	32
28c21e0bbfSMatthew R. Ochs 
29c21e0bbfSMatthew R. Ochs #define PCI_DEVICE_ID_IBM_CORSA		0x04F0
30a2746fb1SManoj Kumar #define PCI_DEVICE_ID_IBM_FLASH_GT	0x0600
3194344520SMatthew R. Ochs #define PCI_DEVICE_ID_IBM_BRIARD	0x0624
32c21e0bbfSMatthew R. Ochs 
33c21e0bbfSMatthew R. Ochs /* Since there is only one target, make it 0 */
34c21e0bbfSMatthew R. Ochs #define CXLFLASH_TARGET		0
35c21e0bbfSMatthew R. Ochs #define CXLFLASH_MAX_CDB_LEN	16
36c21e0bbfSMatthew R. Ochs 
37c21e0bbfSMatthew R. Ochs /* Really only one target per bus since the Texan is directly attached */
38c21e0bbfSMatthew R. Ochs #define CXLFLASH_MAX_NUM_TARGETS_PER_BUS	1
39c21e0bbfSMatthew R. Ochs #define CXLFLASH_MAX_NUM_LUNS_PER_TARGET	65536
40c21e0bbfSMatthew R. Ochs 
41c21e0bbfSMatthew R. Ochs #define CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT	(120 * HZ)
42c21e0bbfSMatthew R. Ochs 
43c21e0bbfSMatthew R. Ochs /* FC defines */
44c21e0bbfSMatthew R. Ochs #define FC_MTIP_CMDCONFIG 0x010
45c21e0bbfSMatthew R. Ochs #define FC_MTIP_STATUS 0x018
469cf43a36SMatthew R. Ochs #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */
479cf43a36SMatthew R. Ochs #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */
489cf43a36SMatthew R. Ochs #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */
499cf43a36SMatthew R. Ochs #define FC_CUR_CAP_PORT 0x098 /* Cur capacity all LUNs for port (4K blocks) */
50c21e0bbfSMatthew R. Ochs 
51c21e0bbfSMatthew R. Ochs #define FC_PNAME 0x300
52c21e0bbfSMatthew R. Ochs #define FC_CONFIG 0x320
53c21e0bbfSMatthew R. Ochs #define FC_CONFIG2 0x328
54c21e0bbfSMatthew R. Ochs #define FC_STATUS 0x330
55c21e0bbfSMatthew R. Ochs #define FC_ERROR 0x380
56c21e0bbfSMatthew R. Ochs #define FC_ERRCAP 0x388
57c21e0bbfSMatthew R. Ochs #define FC_ERRMSK 0x390
58c21e0bbfSMatthew R. Ochs #define FC_CNT_CRCERR 0x538
59c21e0bbfSMatthew R. Ochs #define FC_CRC_THRESH 0x580
60c21e0bbfSMatthew R. Ochs 
61c21e0bbfSMatthew R. Ochs #define FC_MTIP_CMDCONFIG_ONLINE	0x20ULL
62c21e0bbfSMatthew R. Ochs #define FC_MTIP_CMDCONFIG_OFFLINE	0x40ULL
63c21e0bbfSMatthew R. Ochs 
64c21e0bbfSMatthew R. Ochs #define FC_MTIP_STATUS_MASK		0x30ULL
65c21e0bbfSMatthew R. Ochs #define FC_MTIP_STATUS_ONLINE		0x20ULL
66c21e0bbfSMatthew R. Ochs #define FC_MTIP_STATUS_OFFLINE		0x10ULL
67c21e0bbfSMatthew R. Ochs 
68c21e0bbfSMatthew R. Ochs /* TIMEOUT and RETRY definitions */
69c21e0bbfSMatthew R. Ochs 
70c21e0bbfSMatthew R. Ochs /* AFU command timeout values */
71c21e0bbfSMatthew R. Ochs #define MC_AFU_SYNC_TIMEOUT	5	/* 5 secs */
729cf43a36SMatthew R. Ochs #define MC_LUN_PROV_TIMEOUT	5	/* 5 secs */
73bc88ac47SMatthew R. Ochs #define MC_AFU_DEBUG_TIMEOUT	5	/* 5 secs */
74c21e0bbfSMatthew R. Ochs 
75c21e0bbfSMatthew R. Ochs /* AFU command room retry limit */
76c21e0bbfSMatthew R. Ochs #define MC_ROOM_RETRY_CNT	10
77c21e0bbfSMatthew R. Ochs 
78c21e0bbfSMatthew R. Ochs /* FC CRC clear periodic timer */
79c21e0bbfSMatthew R. Ochs #define MC_CRC_THRESH 100	/* threshold in 5 mins */
80c21e0bbfSMatthew R. Ochs 
81c21e0bbfSMatthew R. Ochs #define FC_PORT_STATUS_RETRY_CNT 100	/* 100 100ms retries = 10 seconds */
82c21e0bbfSMatthew R. Ochs #define FC_PORT_STATUS_RETRY_INTERVAL_US 100000	/* microseconds */
83c21e0bbfSMatthew R. Ochs 
84c21e0bbfSMatthew R. Ochs /* VPD defines */
85c21e0bbfSMatthew R. Ochs #define CXLFLASH_VPD_LEN	256
86c21e0bbfSMatthew R. Ochs #define WWPN_LEN	16
87c21e0bbfSMatthew R. Ochs #define WWPN_BUF_LEN	(WWPN_LEN + 1)
88c21e0bbfSMatthew R. Ochs 
89c21e0bbfSMatthew R. Ochs enum undo_level {
909526f360SManoj N. Kumar 	UNDO_NOOP = 0,
91c21e0bbfSMatthew R. Ochs 	FREE_IRQ,
92c21e0bbfSMatthew R. Ochs 	UNMAP_ONE,
93c21e0bbfSMatthew R. Ochs 	UNMAP_TWO,
949526f360SManoj N. Kumar 	UNMAP_THREE
95c21e0bbfSMatthew R. Ochs };
96c21e0bbfSMatthew R. Ochs 
97c21e0bbfSMatthew R. Ochs struct dev_dependent_vals {
98c21e0bbfSMatthew R. Ochs 	u64 max_sectors;
9996e1b660SUma Krishnan 	u64 flags;
100704c4b0dSUma Krishnan #define CXLFLASH_NOTIFY_SHUTDOWN	0x0000000000000001ULL
1010d419130SMatthew R. Ochs #define CXLFLASH_WWPN_VPD_REQUIRED	0x0000000000000002ULL
10207d0c52fSUma Krishnan #define CXLFLASH_OCXL_DEV		0x0000000000000004ULL
103c21e0bbfSMatthew R. Ochs };
104c21e0bbfSMatthew R. Ochs 
105de5d35afSUma Krishnan static inline const struct cxlflash_backend_ops *
106de5d35afSUma Krishnan cxlflash_assign_ops(struct dev_dependent_vals *ddv)
107de5d35afSUma Krishnan {
108de5d35afSUma Krishnan 	const struct cxlflash_backend_ops *ops = NULL;
109de5d35afSUma Krishnan 
110*cd43c221SUma Krishnan #ifdef CONFIG_OCXL
111de5d35afSUma Krishnan 	if (ddv->flags & CXLFLASH_OCXL_DEV)
112de5d35afSUma Krishnan 		ops = &cxlflash_ocxl_ops;
113*cd43c221SUma Krishnan #endif
114*cd43c221SUma Krishnan 
115*cd43c221SUma Krishnan #ifdef CONFIG_CXL
116de5d35afSUma Krishnan 	if (!(ddv->flags & CXLFLASH_OCXL_DEV))
117de5d35afSUma Krishnan 		ops = &cxlflash_cxl_ops;
118*cd43c221SUma Krishnan #endif
119de5d35afSUma Krishnan 
120de5d35afSUma Krishnan 	return ops;
121de5d35afSUma Krishnan }
122de5d35afSUma Krishnan 
123c21e0bbfSMatthew R. Ochs struct asyc_intr_info {
124c21e0bbfSMatthew R. Ochs 	u64 status;
125c21e0bbfSMatthew R. Ochs 	char *desc;
126c21e0bbfSMatthew R. Ochs 	u8 port;
127c21e0bbfSMatthew R. Ochs 	u8 action;
128c21e0bbfSMatthew R. Ochs #define CLR_FC_ERROR	0x01
129c21e0bbfSMatthew R. Ochs #define LINK_RESET	0x02
130ef51074aSMatthew R. Ochs #define SCAN_HOST	0x04
131c21e0bbfSMatthew R. Ochs };
132c21e0bbfSMatthew R. Ochs 
133c21e0bbfSMatthew R. Ochs #endif /* _CXLFLASH_MAIN_H */
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