xref: /linux/drivers/scsi/cxlflash/main.h (revision 943445200b049d5179b95297e5372d399c8ab0e2)
1c21e0bbfSMatthew R. Ochs /*
2c21e0bbfSMatthew R. Ochs  * CXL Flash Device Driver
3c21e0bbfSMatthew R. Ochs  *
4c21e0bbfSMatthew R. Ochs  * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
5c21e0bbfSMatthew R. Ochs  *             Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
6c21e0bbfSMatthew R. Ochs  *
7c21e0bbfSMatthew R. Ochs  * Copyright (C) 2015 IBM Corporation
8c21e0bbfSMatthew R. Ochs  *
9c21e0bbfSMatthew R. Ochs  * This program is free software; you can redistribute it and/or
10c21e0bbfSMatthew R. Ochs  * modify it under the terms of the GNU General Public License
11c21e0bbfSMatthew R. Ochs  * as published by the Free Software Foundation; either version
12c21e0bbfSMatthew R. Ochs  * 2 of the License, or (at your option) any later version.
13c21e0bbfSMatthew R. Ochs  */
14c21e0bbfSMatthew R. Ochs 
15c21e0bbfSMatthew R. Ochs #ifndef _CXLFLASH_MAIN_H
16c21e0bbfSMatthew R. Ochs #define _CXLFLASH_MAIN_H
17c21e0bbfSMatthew R. Ochs 
18c21e0bbfSMatthew R. Ochs #include <linux/list.h>
19c21e0bbfSMatthew R. Ochs #include <linux/types.h>
20c21e0bbfSMatthew R. Ochs #include <scsi/scsi.h>
21c21e0bbfSMatthew R. Ochs #include <scsi/scsi_device.h>
22c21e0bbfSMatthew R. Ochs 
23c21e0bbfSMatthew R. Ochs #define CXLFLASH_NAME		"cxlflash"
24c21e0bbfSMatthew R. Ochs #define CXLFLASH_ADAPTER_NAME	"IBM POWER CXL Flash Adapter"
25c21e0bbfSMatthew R. Ochs 
26c21e0bbfSMatthew R. Ochs #define PCI_DEVICE_ID_IBM_CORSA		0x04F0
27a2746fb1SManoj Kumar #define PCI_DEVICE_ID_IBM_FLASH_GT	0x0600
28*94344520SMatthew R. Ochs #define PCI_DEVICE_ID_IBM_BRIARD	0x0624
29c21e0bbfSMatthew R. Ochs 
30c21e0bbfSMatthew R. Ochs /* Since there is only one target, make it 0 */
31c21e0bbfSMatthew R. Ochs #define CXLFLASH_TARGET		0
32c21e0bbfSMatthew R. Ochs #define CXLFLASH_MAX_CDB_LEN	16
33c21e0bbfSMatthew R. Ochs 
34c21e0bbfSMatthew R. Ochs /* Really only one target per bus since the Texan is directly attached */
35c21e0bbfSMatthew R. Ochs #define CXLFLASH_MAX_NUM_TARGETS_PER_BUS	1
36c21e0bbfSMatthew R. Ochs #define CXLFLASH_MAX_NUM_LUNS_PER_TARGET	65536
37c21e0bbfSMatthew R. Ochs 
38c21e0bbfSMatthew R. Ochs #define CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT	(120 * HZ)
39c21e0bbfSMatthew R. Ochs 
40c21e0bbfSMatthew R. Ochs #define NUM_FC_PORTS	CXLFLASH_NUM_FC_PORTS	/* ports per AFU */
41c21e0bbfSMatthew R. Ochs 
42c21e0bbfSMatthew R. Ochs /* FC defines */
43c21e0bbfSMatthew R. Ochs #define FC_MTIP_CMDCONFIG 0x010
44c21e0bbfSMatthew R. Ochs #define FC_MTIP_STATUS 0x018
45c21e0bbfSMatthew R. Ochs 
46c21e0bbfSMatthew R. Ochs #define FC_PNAME 0x300
47c21e0bbfSMatthew R. Ochs #define FC_CONFIG 0x320
48c21e0bbfSMatthew R. Ochs #define FC_CONFIG2 0x328
49c21e0bbfSMatthew R. Ochs #define FC_STATUS 0x330
50c21e0bbfSMatthew R. Ochs #define FC_ERROR 0x380
51c21e0bbfSMatthew R. Ochs #define FC_ERRCAP 0x388
52c21e0bbfSMatthew R. Ochs #define FC_ERRMSK 0x390
53c21e0bbfSMatthew R. Ochs #define FC_CNT_CRCERR 0x538
54c21e0bbfSMatthew R. Ochs #define FC_CRC_THRESH 0x580
55c21e0bbfSMatthew R. Ochs 
56c21e0bbfSMatthew R. Ochs #define FC_MTIP_CMDCONFIG_ONLINE	0x20ULL
57c21e0bbfSMatthew R. Ochs #define FC_MTIP_CMDCONFIG_OFFLINE	0x40ULL
58c21e0bbfSMatthew R. Ochs 
59c21e0bbfSMatthew R. Ochs #define FC_MTIP_STATUS_MASK		0x30ULL
60c21e0bbfSMatthew R. Ochs #define FC_MTIP_STATUS_ONLINE		0x20ULL
61c21e0bbfSMatthew R. Ochs #define FC_MTIP_STATUS_OFFLINE		0x10ULL
62c21e0bbfSMatthew R. Ochs 
63c21e0bbfSMatthew R. Ochs /* TIMEOUT and RETRY definitions */
64c21e0bbfSMatthew R. Ochs 
65c21e0bbfSMatthew R. Ochs /* AFU command timeout values */
66c21e0bbfSMatthew R. Ochs #define MC_AFU_SYNC_TIMEOUT	5	/* 5 secs */
67c21e0bbfSMatthew R. Ochs 
68c21e0bbfSMatthew R. Ochs /* AFU command room retry limit */
69c21e0bbfSMatthew R. Ochs #define MC_ROOM_RETRY_CNT	10
70c21e0bbfSMatthew R. Ochs 
71c21e0bbfSMatthew R. Ochs /* FC CRC clear periodic timer */
72c21e0bbfSMatthew R. Ochs #define MC_CRC_THRESH 100	/* threshold in 5 mins */
73c21e0bbfSMatthew R. Ochs 
74c21e0bbfSMatthew R. Ochs #define FC_PORT_STATUS_RETRY_CNT 100	/* 100 100ms retries = 10 seconds */
75c21e0bbfSMatthew R. Ochs #define FC_PORT_STATUS_RETRY_INTERVAL_US 100000	/* microseconds */
76c21e0bbfSMatthew R. Ochs 
77c21e0bbfSMatthew R. Ochs /* VPD defines */
78c21e0bbfSMatthew R. Ochs #define CXLFLASH_VPD_LEN	256
79c21e0bbfSMatthew R. Ochs #define WWPN_LEN	16
80c21e0bbfSMatthew R. Ochs #define WWPN_BUF_LEN	(WWPN_LEN + 1)
81c21e0bbfSMatthew R. Ochs 
82c21e0bbfSMatthew R. Ochs enum undo_level {
839526f360SManoj N. Kumar 	UNDO_NOOP = 0,
84c21e0bbfSMatthew R. Ochs 	FREE_IRQ,
85c21e0bbfSMatthew R. Ochs 	UNMAP_ONE,
86c21e0bbfSMatthew R. Ochs 	UNMAP_TWO,
879526f360SManoj N. Kumar 	UNMAP_THREE
88c21e0bbfSMatthew R. Ochs };
89c21e0bbfSMatthew R. Ochs 
90c21e0bbfSMatthew R. Ochs struct dev_dependent_vals {
91c21e0bbfSMatthew R. Ochs 	u64 max_sectors;
9296e1b660SUma Krishnan 	u64 flags;
93704c4b0dSUma Krishnan #define CXLFLASH_NOTIFY_SHUTDOWN   0x0000000000000001ULL
94c21e0bbfSMatthew R. Ochs };
95c21e0bbfSMatthew R. Ochs 
96c21e0bbfSMatthew R. Ochs struct asyc_intr_info {
97c21e0bbfSMatthew R. Ochs 	u64 status;
98c21e0bbfSMatthew R. Ochs 	char *desc;
99c21e0bbfSMatthew R. Ochs 	u8 port;
100c21e0bbfSMatthew R. Ochs 	u8 action;
101c21e0bbfSMatthew R. Ochs #define CLR_FC_ERROR	0x01
102c21e0bbfSMatthew R. Ochs #define LINK_RESET	0x02
103ef51074aSMatthew R. Ochs #define SCAN_HOST	0x04
104c21e0bbfSMatthew R. Ochs };
105c21e0bbfSMatthew R. Ochs 
106c21e0bbfSMatthew R. Ochs #endif /* _CXLFLASH_MAIN_H */
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