1 /* bnx2fc_hwi.c: QLogic Linux FCoE offload driver. 2 * This file contains the code that low level functions that interact 3 * with 57712 FCoE firmware. 4 * 5 * Copyright (c) 2008-2013 Broadcom Corporation 6 * Copyright (c) 2014-2016 QLogic Corporation 7 * Copyright (c) 2016-2017 Cavium Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation. 12 * 13 * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com) 14 */ 15 16 #include "bnx2fc.h" 17 18 DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu); 19 20 static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba, 21 struct fcoe_kcqe *new_cqe_kcqe); 22 static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba, 23 struct fcoe_kcqe *ofld_kcqe); 24 static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba, 25 struct fcoe_kcqe *ofld_kcqe); 26 static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code); 27 static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba, 28 struct fcoe_kcqe *destroy_kcqe); 29 30 int bnx2fc_send_stat_req(struct bnx2fc_hba *hba) 31 { 32 struct fcoe_kwqe_stat stat_req; 33 struct kwqe *kwqe_arr[2]; 34 int num_kwqes = 1; 35 int rc = 0; 36 37 memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat)); 38 stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT; 39 stat_req.hdr.flags = 40 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 41 42 stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma; 43 stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32); 44 45 kwqe_arr[0] = (struct kwqe *) &stat_req; 46 47 if (hba->cnic && hba->cnic->submit_kwqes) 48 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 49 50 return rc; 51 } 52 53 /** 54 * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w 55 * 56 * @hba: adapter structure pointer 57 * 58 * Send down FCoE firmware init KWQEs which initiates the initial handshake 59 * with the f/w. 60 * 61 */ 62 int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba) 63 { 64 struct fcoe_kwqe_init1 fcoe_init1; 65 struct fcoe_kwqe_init2 fcoe_init2; 66 struct fcoe_kwqe_init3 fcoe_init3; 67 struct kwqe *kwqe_arr[3]; 68 int num_kwqes = 3; 69 int rc = 0; 70 71 if (!hba->cnic) { 72 printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n"); 73 return -ENODEV; 74 } 75 76 /* fill init1 KWQE */ 77 memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1)); 78 fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1; 79 fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE << 80 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 81 82 fcoe_init1.num_tasks = hba->max_tasks; 83 fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX; 84 fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX; 85 fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ; 86 fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX; 87 fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma; 88 fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32); 89 fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma; 90 fcoe_init1.task_list_pbl_addr_hi = 91 (u32) ((u64) hba->task_ctx_bd_dma >> 32); 92 fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU; 93 94 fcoe_init1.flags = (PAGE_SHIFT << 95 FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT); 96 97 fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG; 98 99 /* fill init2 KWQE */ 100 memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2)); 101 fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2; 102 fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE << 103 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 104 105 fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION; 106 fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION; 107 108 109 fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma; 110 fcoe_init2.hash_tbl_pbl_addr_hi = (u32) 111 ((u64) hba->hash_tbl_pbl_dma >> 32); 112 113 fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma; 114 fcoe_init2.t2_hash_tbl_addr_hi = (u32) 115 ((u64) hba->t2_hash_tbl_dma >> 32); 116 117 fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma; 118 fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32) 119 ((u64) hba->t2_hash_tbl_ptr_dma >> 32); 120 121 fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS; 122 123 /* fill init3 KWQE */ 124 memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3)); 125 fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3; 126 fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE << 127 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 128 fcoe_init3.error_bit_map_lo = 0xffffffff; 129 fcoe_init3.error_bit_map_hi = 0xffffffff; 130 131 /* 132 * enable both cached connection and cached tasks 133 * 0 = none, 1 = cached connection, 2 = cached tasks, 3 = both 134 */ 135 fcoe_init3.perf_config = 3; 136 137 kwqe_arr[0] = (struct kwqe *) &fcoe_init1; 138 kwqe_arr[1] = (struct kwqe *) &fcoe_init2; 139 kwqe_arr[2] = (struct kwqe *) &fcoe_init3; 140 141 if (hba->cnic && hba->cnic->submit_kwqes) 142 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 143 144 return rc; 145 } 146 int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba) 147 { 148 struct fcoe_kwqe_destroy fcoe_destroy; 149 struct kwqe *kwqe_arr[2]; 150 int num_kwqes = 1; 151 int rc = -1; 152 153 /* fill destroy KWQE */ 154 memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy)); 155 fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY; 156 fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE << 157 FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 158 kwqe_arr[0] = (struct kwqe *) &fcoe_destroy; 159 160 if (hba->cnic && hba->cnic->submit_kwqes) 161 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 162 return rc; 163 } 164 165 /** 166 * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process 167 * 168 * @port: port structure pointer 169 * @tgt: bnx2fc_rport structure pointer 170 */ 171 int bnx2fc_send_session_ofld_req(struct fcoe_port *port, 172 struct bnx2fc_rport *tgt) 173 { 174 struct fc_lport *lport = port->lport; 175 struct bnx2fc_interface *interface = port->priv; 176 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface); 177 struct bnx2fc_hba *hba = interface->hba; 178 struct kwqe *kwqe_arr[4]; 179 struct fcoe_kwqe_conn_offload1 ofld_req1; 180 struct fcoe_kwqe_conn_offload2 ofld_req2; 181 struct fcoe_kwqe_conn_offload3 ofld_req3; 182 struct fcoe_kwqe_conn_offload4 ofld_req4; 183 struct fc_rport_priv *rdata = tgt->rdata; 184 struct fc_rport *rport = tgt->rport; 185 int num_kwqes = 4; 186 u32 port_id; 187 int rc = 0; 188 u16 conn_id; 189 190 /* Initialize offload request 1 structure */ 191 memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1)); 192 193 ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1; 194 ofld_req1.hdr.flags = 195 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 196 197 198 conn_id = (u16)tgt->fcoe_conn_id; 199 ofld_req1.fcoe_conn_id = conn_id; 200 201 202 ofld_req1.sq_addr_lo = (u32) tgt->sq_dma; 203 ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32); 204 205 ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma; 206 ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32); 207 208 ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma; 209 ofld_req1.rq_first_pbe_addr_hi = 210 (u32)((u64) tgt->rq_dma >> 32); 211 212 ofld_req1.rq_prod = 0x8000; 213 214 /* Initialize offload request 2 structure */ 215 memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2)); 216 217 ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2; 218 ofld_req2.hdr.flags = 219 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 220 221 ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size; 222 223 ofld_req2.cq_addr_lo = (u32) tgt->cq_dma; 224 ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32); 225 226 ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma; 227 ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32); 228 229 ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma; 230 ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32); 231 232 /* Initialize offload request 3 structure */ 233 memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3)); 234 235 ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3; 236 ofld_req3.hdr.flags = 237 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 238 239 ofld_req3.vlan_tag = interface->vlan_id << 240 FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT; 241 ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT; 242 243 port_id = fc_host_port_id(lport->host); 244 if (port_id == 0) { 245 BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n"); 246 return -EINVAL; 247 } 248 249 /* 250 * Store s_id of the initiator for further reference. This will 251 * be used during disable/destroy during linkdown processing as 252 * when the lport is reset, the port_id also is reset to 0 253 */ 254 tgt->sid = port_id; 255 ofld_req3.s_id[0] = (port_id & 0x000000FF); 256 ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8; 257 ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16; 258 259 port_id = rport->port_id; 260 ofld_req3.d_id[0] = (port_id & 0x000000FF); 261 ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8; 262 ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16; 263 264 ofld_req3.tx_total_conc_seqs = rdata->max_seq; 265 266 ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq; 267 ofld_req3.rx_max_fc_pay_len = lport->mfs; 268 269 ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS; 270 ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS; 271 ofld_req3.rx_open_seqs_exch_c3 = 1; 272 273 ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma; 274 ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32); 275 276 /* set mul_n_port_ids supported flag to 0, until it is supported */ 277 ofld_req3.flags = 0; 278 /* 279 ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) << 280 FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT); 281 */ 282 /* Info from PLOGI response */ 283 ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) << 284 FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT); 285 286 ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) << 287 FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT); 288 289 /* 290 * Info from PRLI response, this info is used for sequence level error 291 * recovery support 292 */ 293 if (tgt->dev_type == TYPE_TAPE) { 294 ofld_req3.flags |= 1 << 295 FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT; 296 ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED) 297 ? 1 : 0) << 298 FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT); 299 } 300 301 /* vlan flag */ 302 ofld_req3.flags |= (interface->vlan_enabled << 303 FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT); 304 305 /* C2_VALID and ACK flags are not set as they are not supported */ 306 307 308 /* Initialize offload request 4 structure */ 309 memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4)); 310 ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4; 311 ofld_req4.hdr.flags = 312 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 313 314 ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20; 315 316 317 ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5]; 318 /* local mac */ 319 ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4]; 320 ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3]; 321 ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2]; 322 ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1]; 323 ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0]; 324 ofld_req4.dst_mac_addr_lo[0] = ctlr->dest_addr[5]; 325 /* fcf mac */ 326 ofld_req4.dst_mac_addr_lo[1] = ctlr->dest_addr[4]; 327 ofld_req4.dst_mac_addr_mid[0] = ctlr->dest_addr[3]; 328 ofld_req4.dst_mac_addr_mid[1] = ctlr->dest_addr[2]; 329 ofld_req4.dst_mac_addr_hi[0] = ctlr->dest_addr[1]; 330 ofld_req4.dst_mac_addr_hi[1] = ctlr->dest_addr[0]; 331 332 ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma; 333 ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32); 334 335 ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma; 336 ofld_req4.confq_pbl_base_addr_hi = 337 (u32)((u64) tgt->confq_pbl_dma >> 32); 338 339 kwqe_arr[0] = (struct kwqe *) &ofld_req1; 340 kwqe_arr[1] = (struct kwqe *) &ofld_req2; 341 kwqe_arr[2] = (struct kwqe *) &ofld_req3; 342 kwqe_arr[3] = (struct kwqe *) &ofld_req4; 343 344 if (hba->cnic && hba->cnic->submit_kwqes) 345 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 346 347 return rc; 348 } 349 350 /** 351 * bnx2fc_send_session_enable_req - initiates FCoE Session enablement 352 * 353 * @port: port structure pointer 354 * @tgt: bnx2fc_rport structure pointer 355 */ 356 int bnx2fc_send_session_enable_req(struct fcoe_port *port, 357 struct bnx2fc_rport *tgt) 358 { 359 struct kwqe *kwqe_arr[2]; 360 struct bnx2fc_interface *interface = port->priv; 361 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface); 362 struct bnx2fc_hba *hba = interface->hba; 363 struct fcoe_kwqe_conn_enable_disable enbl_req; 364 struct fc_lport *lport = port->lport; 365 struct fc_rport *rport = tgt->rport; 366 int num_kwqes = 1; 367 int rc = 0; 368 u32 port_id; 369 370 memset(&enbl_req, 0x00, 371 sizeof(struct fcoe_kwqe_conn_enable_disable)); 372 enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN; 373 enbl_req.hdr.flags = 374 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 375 376 enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5]; 377 /* local mac */ 378 enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4]; 379 enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3]; 380 enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2]; 381 enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1]; 382 enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0]; 383 memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN); 384 385 enbl_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5]; 386 enbl_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4]; 387 enbl_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3]; 388 enbl_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2]; 389 enbl_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1]; 390 enbl_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0]; 391 392 port_id = fc_host_port_id(lport->host); 393 if (port_id != tgt->sid) { 394 printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x," 395 "sid = 0x%x\n", port_id, tgt->sid); 396 port_id = tgt->sid; 397 } 398 enbl_req.s_id[0] = (port_id & 0x000000FF); 399 enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8; 400 enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16; 401 402 port_id = rport->port_id; 403 enbl_req.d_id[0] = (port_id & 0x000000FF); 404 enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8; 405 enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16; 406 enbl_req.vlan_tag = interface->vlan_id << 407 FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT; 408 enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT; 409 enbl_req.vlan_flag = interface->vlan_enabled; 410 enbl_req.context_id = tgt->context_id; 411 enbl_req.conn_id = tgt->fcoe_conn_id; 412 413 kwqe_arr[0] = (struct kwqe *) &enbl_req; 414 415 if (hba->cnic && hba->cnic->submit_kwqes) 416 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 417 return rc; 418 } 419 420 /** 421 * bnx2fc_send_session_disable_req - initiates FCoE Session disable 422 * 423 * @port: port structure pointer 424 * @tgt: bnx2fc_rport structure pointer 425 */ 426 int bnx2fc_send_session_disable_req(struct fcoe_port *port, 427 struct bnx2fc_rport *tgt) 428 { 429 struct bnx2fc_interface *interface = port->priv; 430 struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface); 431 struct bnx2fc_hba *hba = interface->hba; 432 struct fcoe_kwqe_conn_enable_disable disable_req; 433 struct kwqe *kwqe_arr[2]; 434 struct fc_rport *rport = tgt->rport; 435 int num_kwqes = 1; 436 int rc = 0; 437 u32 port_id; 438 439 memset(&disable_req, 0x00, 440 sizeof(struct fcoe_kwqe_conn_enable_disable)); 441 disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN; 442 disable_req.hdr.flags = 443 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 444 445 disable_req.src_mac_addr_lo[0] = tgt->src_addr[5]; 446 disable_req.src_mac_addr_lo[1] = tgt->src_addr[4]; 447 disable_req.src_mac_addr_mid[0] = tgt->src_addr[3]; 448 disable_req.src_mac_addr_mid[1] = tgt->src_addr[2]; 449 disable_req.src_mac_addr_hi[0] = tgt->src_addr[1]; 450 disable_req.src_mac_addr_hi[1] = tgt->src_addr[0]; 451 452 disable_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5]; 453 disable_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4]; 454 disable_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3]; 455 disable_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2]; 456 disable_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1]; 457 disable_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0]; 458 459 port_id = tgt->sid; 460 disable_req.s_id[0] = (port_id & 0x000000FF); 461 disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8; 462 disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16; 463 464 465 port_id = rport->port_id; 466 disable_req.d_id[0] = (port_id & 0x000000FF); 467 disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8; 468 disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16; 469 disable_req.context_id = tgt->context_id; 470 disable_req.conn_id = tgt->fcoe_conn_id; 471 disable_req.vlan_tag = interface->vlan_id << 472 FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT; 473 disable_req.vlan_tag |= 474 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT; 475 disable_req.vlan_flag = interface->vlan_enabled; 476 477 kwqe_arr[0] = (struct kwqe *) &disable_req; 478 479 if (hba->cnic && hba->cnic->submit_kwqes) 480 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 481 482 return rc; 483 } 484 485 /** 486 * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy 487 * 488 * @port: port structure pointer 489 * @tgt: bnx2fc_rport structure pointer 490 */ 491 int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba, 492 struct bnx2fc_rport *tgt) 493 { 494 struct fcoe_kwqe_conn_destroy destroy_req; 495 struct kwqe *kwqe_arr[2]; 496 int num_kwqes = 1; 497 int rc = 0; 498 499 memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy)); 500 destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN; 501 destroy_req.hdr.flags = 502 (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT); 503 504 destroy_req.context_id = tgt->context_id; 505 destroy_req.conn_id = tgt->fcoe_conn_id; 506 507 kwqe_arr[0] = (struct kwqe *) &destroy_req; 508 509 if (hba->cnic && hba->cnic->submit_kwqes) 510 rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes); 511 512 return rc; 513 } 514 515 static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport) 516 { 517 struct bnx2fc_lport *blport; 518 519 spin_lock_bh(&hba->hba_lock); 520 list_for_each_entry(blport, &hba->vports, list) { 521 if (blport->lport == lport) { 522 spin_unlock_bh(&hba->hba_lock); 523 return true; 524 } 525 } 526 spin_unlock_bh(&hba->hba_lock); 527 return false; 528 529 } 530 531 532 static void bnx2fc_unsol_els_work(struct work_struct *work) 533 { 534 struct bnx2fc_unsol_els *unsol_els; 535 struct fc_lport *lport; 536 struct bnx2fc_hba *hba; 537 struct fc_frame *fp; 538 539 unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work); 540 lport = unsol_els->lport; 541 fp = unsol_els->fp; 542 hba = unsol_els->hba; 543 if (is_valid_lport(hba, lport)) 544 fc_exch_recv(lport, fp); 545 kfree(unsol_els); 546 } 547 548 void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt, 549 unsigned char *buf, 550 u32 frame_len, u16 l2_oxid) 551 { 552 struct fcoe_port *port = tgt->port; 553 struct fc_lport *lport = port->lport; 554 struct bnx2fc_interface *interface = port->priv; 555 struct bnx2fc_unsol_els *unsol_els; 556 struct fc_frame_header *fh; 557 struct fc_frame *fp; 558 struct sk_buff *skb; 559 u32 payload_len; 560 u32 crc; 561 u8 op; 562 563 564 unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC); 565 if (!unsol_els) { 566 BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n"); 567 return; 568 } 569 570 BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n", 571 l2_oxid, frame_len); 572 573 payload_len = frame_len - sizeof(struct fc_frame_header); 574 575 fp = fc_frame_alloc(lport, payload_len); 576 if (!fp) { 577 printk(KERN_ERR PFX "fc_frame_alloc failure\n"); 578 kfree(unsol_els); 579 return; 580 } 581 582 fh = (struct fc_frame_header *) fc_frame_header_get(fp); 583 /* Copy FC Frame header and payload into the frame */ 584 memcpy(fh, buf, frame_len); 585 586 if (l2_oxid != FC_XID_UNKNOWN) 587 fh->fh_ox_id = htons(l2_oxid); 588 589 skb = fp_skb(fp); 590 591 if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) || 592 (fh->fh_r_ctl == FC_RCTL_ELS_REP)) { 593 594 if (fh->fh_type == FC_TYPE_ELS) { 595 op = fc_frame_payload_op(fp); 596 if ((op == ELS_TEST) || (op == ELS_ESTC) || 597 (op == ELS_FAN) || (op == ELS_CSU)) { 598 /* 599 * No need to reply for these 600 * ELS requests 601 */ 602 printk(KERN_ERR PFX "dropping ELS 0x%x\n", op); 603 kfree_skb(skb); 604 kfree(unsol_els); 605 return; 606 } 607 } 608 crc = fcoe_fc_crc(fp); 609 fc_frame_init(fp); 610 fr_dev(fp) = lport; 611 fr_sof(fp) = FC_SOF_I3; 612 fr_eof(fp) = FC_EOF_T; 613 fr_crc(fp) = cpu_to_le32(~crc); 614 unsol_els->lport = lport; 615 unsol_els->hba = interface->hba; 616 unsol_els->fp = fp; 617 INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work); 618 queue_work(bnx2fc_wq, &unsol_els->unsol_els_work); 619 } else { 620 BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl); 621 kfree_skb(skb); 622 kfree(unsol_els); 623 } 624 } 625 626 static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe) 627 { 628 u8 num_rq; 629 struct fcoe_err_report_entry *err_entry; 630 unsigned char *rq_data; 631 unsigned char *buf = NULL, *buf1; 632 int i; 633 u16 xid; 634 u32 frame_len, len; 635 struct bnx2fc_cmd *io_req = NULL; 636 struct bnx2fc_interface *interface = tgt->port->priv; 637 struct bnx2fc_hba *hba = interface->hba; 638 int task_idx, index; 639 int rc = 0; 640 u64 err_warn_bit_map; 641 u8 err_warn = 0xff; 642 643 644 BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe); 645 switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) { 646 case FCOE_UNSOLICITED_FRAME_CQE_TYPE: 647 frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >> 648 FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT; 649 650 num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ; 651 652 spin_lock_bh(&tgt->tgt_lock); 653 rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq); 654 spin_unlock_bh(&tgt->tgt_lock); 655 656 if (rq_data) { 657 buf = rq_data; 658 } else { 659 buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ), 660 GFP_ATOMIC); 661 662 if (!buf1) { 663 BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n"); 664 break; 665 } 666 667 for (i = 0; i < num_rq; i++) { 668 spin_lock_bh(&tgt->tgt_lock); 669 rq_data = (unsigned char *) 670 bnx2fc_get_next_rqe(tgt, 1); 671 spin_unlock_bh(&tgt->tgt_lock); 672 len = BNX2FC_RQ_BUF_SZ; 673 memcpy(buf1, rq_data, len); 674 buf1 += len; 675 } 676 } 677 bnx2fc_process_l2_frame_compl(tgt, buf, frame_len, 678 FC_XID_UNKNOWN); 679 680 if (buf != rq_data) 681 kfree(buf); 682 spin_lock_bh(&tgt->tgt_lock); 683 bnx2fc_return_rqe(tgt, num_rq); 684 spin_unlock_bh(&tgt->tgt_lock); 685 break; 686 687 case FCOE_ERROR_DETECTION_CQE_TYPE: 688 /* 689 * In case of error reporting CQE a single RQ entry 690 * is consumed. 691 */ 692 spin_lock_bh(&tgt->tgt_lock); 693 num_rq = 1; 694 err_entry = (struct fcoe_err_report_entry *) 695 bnx2fc_get_next_rqe(tgt, 1); 696 xid = err_entry->fc_hdr.ox_id; 697 BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid); 698 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n", 699 err_entry->data.err_warn_bitmap_hi, 700 err_entry->data.err_warn_bitmap_lo); 701 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n", 702 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off); 703 704 705 if (xid > hba->max_xid) { 706 BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", 707 xid); 708 goto ret_err_rqe; 709 } 710 711 task_idx = xid / BNX2FC_TASKS_PER_PAGE; 712 index = xid % BNX2FC_TASKS_PER_PAGE; 713 714 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid]; 715 if (!io_req) 716 goto ret_err_rqe; 717 718 if (io_req->cmd_type != BNX2FC_SCSI_CMD) { 719 printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n"); 720 goto ret_err_rqe; 721 } 722 723 if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP, 724 &io_req->req_flags)) { 725 BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in " 726 "progress.. ignore unsol err\n"); 727 goto ret_err_rqe; 728 } 729 730 err_warn_bit_map = (u64) 731 ((u64)err_entry->data.err_warn_bitmap_hi << 32) | 732 (u64)err_entry->data.err_warn_bitmap_lo; 733 for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) { 734 if (err_warn_bit_map & (u64)((u64)1 << i)) { 735 err_warn = i; 736 break; 737 } 738 } 739 740 /* 741 * If ABTS is already in progress, and FW error is 742 * received after that, do not cancel the timeout_work 743 * and let the error recovery continue by explicitly 744 * logging out the target, when the ABTS eventually 745 * times out. 746 */ 747 if (test_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags)) { 748 printk(KERN_ERR PFX "err_warn: io_req (0x%x) already " 749 "in ABTS processing\n", xid); 750 goto ret_err_rqe; 751 } 752 BNX2FC_TGT_DBG(tgt, "err = 0x%x\n", err_warn); 753 if (tgt->dev_type != TYPE_TAPE) 754 goto skip_rec; 755 switch (err_warn) { 756 case FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION: 757 case FCOE_ERROR_CODE_DATA_OOO_RO: 758 case FCOE_ERROR_CODE_COMMON_INCORRECT_SEQ_CNT: 759 case FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET: 760 case FCOE_ERROR_CODE_FCP_RSP_OPENED_SEQ: 761 case FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET: 762 BNX2FC_TGT_DBG(tgt, "REC TOV popped for xid - 0x%x\n", 763 xid); 764 memcpy(&io_req->err_entry, err_entry, 765 sizeof(struct fcoe_err_report_entry)); 766 if (!test_bit(BNX2FC_FLAG_SRR_SENT, 767 &io_req->req_flags)) { 768 spin_unlock_bh(&tgt->tgt_lock); 769 rc = bnx2fc_send_rec(io_req); 770 spin_lock_bh(&tgt->tgt_lock); 771 772 if (rc) 773 goto skip_rec; 774 } else 775 printk(KERN_ERR PFX "SRR in progress\n"); 776 goto ret_err_rqe; 777 break; 778 default: 779 break; 780 } 781 782 skip_rec: 783 set_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags); 784 /* 785 * Cancel the timeout_work, as we received IO 786 * completion with FW error. 787 */ 788 if (cancel_delayed_work(&io_req->timeout_work)) 789 kref_put(&io_req->refcount, bnx2fc_cmd_release); 790 791 rc = bnx2fc_initiate_abts(io_req); 792 if (rc != SUCCESS) { 793 printk(KERN_ERR PFX "err_warn: initiate_abts " 794 "failed xid = 0x%x. issue cleanup\n", 795 io_req->xid); 796 bnx2fc_initiate_cleanup(io_req); 797 } 798 ret_err_rqe: 799 bnx2fc_return_rqe(tgt, 1); 800 spin_unlock_bh(&tgt->tgt_lock); 801 break; 802 803 case FCOE_WARNING_DETECTION_CQE_TYPE: 804 /* 805 *In case of warning reporting CQE a single RQ entry 806 * is consumes. 807 */ 808 spin_lock_bh(&tgt->tgt_lock); 809 num_rq = 1; 810 err_entry = (struct fcoe_err_report_entry *) 811 bnx2fc_get_next_rqe(tgt, 1); 812 xid = cpu_to_be16(err_entry->fc_hdr.ox_id); 813 BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid); 814 BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x", 815 err_entry->data.err_warn_bitmap_hi, 816 err_entry->data.err_warn_bitmap_lo); 817 BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x", 818 err_entry->data.tx_buf_off, err_entry->data.rx_buf_off); 819 820 if (xid > hba->max_xid) { 821 BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", xid); 822 goto ret_warn_rqe; 823 } 824 825 err_warn_bit_map = (u64) 826 ((u64)err_entry->data.err_warn_bitmap_hi << 32) | 827 (u64)err_entry->data.err_warn_bitmap_lo; 828 for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) { 829 if (err_warn_bit_map & ((u64)1 << i)) { 830 err_warn = i; 831 break; 832 } 833 } 834 BNX2FC_TGT_DBG(tgt, "warn = 0x%x\n", err_warn); 835 836 task_idx = xid / BNX2FC_TASKS_PER_PAGE; 837 index = xid % BNX2FC_TASKS_PER_PAGE; 838 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid]; 839 if (!io_req) 840 goto ret_warn_rqe; 841 842 if (io_req->cmd_type != BNX2FC_SCSI_CMD) { 843 printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n"); 844 goto ret_warn_rqe; 845 } 846 847 memcpy(&io_req->err_entry, err_entry, 848 sizeof(struct fcoe_err_report_entry)); 849 850 if (err_warn == FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION) 851 /* REC_TOV is not a warning code */ 852 BUG_ON(1); 853 else 854 BNX2FC_TGT_DBG(tgt, "Unsolicited warning\n"); 855 ret_warn_rqe: 856 bnx2fc_return_rqe(tgt, 1); 857 spin_unlock_bh(&tgt->tgt_lock); 858 break; 859 860 default: 861 printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n"); 862 break; 863 } 864 } 865 866 void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe) 867 { 868 struct fcoe_task_ctx_entry *task; 869 struct fcoe_task_ctx_entry *task_page; 870 struct fcoe_port *port = tgt->port; 871 struct bnx2fc_interface *interface = port->priv; 872 struct bnx2fc_hba *hba = interface->hba; 873 struct bnx2fc_cmd *io_req; 874 int task_idx, index; 875 u16 xid; 876 u8 cmd_type; 877 u8 rx_state = 0; 878 u8 num_rq; 879 880 spin_lock_bh(&tgt->tgt_lock); 881 xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID; 882 if (xid >= hba->max_tasks) { 883 printk(KERN_ERR PFX "ERROR:xid out of range\n"); 884 spin_unlock_bh(&tgt->tgt_lock); 885 return; 886 } 887 task_idx = xid / BNX2FC_TASKS_PER_PAGE; 888 index = xid % BNX2FC_TASKS_PER_PAGE; 889 task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx]; 890 task = &(task_page[index]); 891 892 num_rq = ((task->rxwr_txrd.var_ctx.rx_flags & 893 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >> 894 FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT); 895 896 io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid]; 897 898 if (io_req == NULL) { 899 printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n"); 900 spin_unlock_bh(&tgt->tgt_lock); 901 return; 902 } 903 904 /* Timestamp IO completion time */ 905 cmd_type = io_req->cmd_type; 906 907 rx_state = ((task->rxwr_txrd.var_ctx.rx_flags & 908 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >> 909 FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT); 910 911 /* Process other IO completion types */ 912 switch (cmd_type) { 913 case BNX2FC_SCSI_CMD: 914 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) { 915 bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq); 916 spin_unlock_bh(&tgt->tgt_lock); 917 return; 918 } 919 920 if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED) 921 bnx2fc_process_abts_compl(io_req, task, num_rq); 922 else if (rx_state == 923 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED) 924 bnx2fc_process_cleanup_compl(io_req, task, num_rq); 925 else 926 printk(KERN_ERR PFX "Invalid rx state - %d\n", 927 rx_state); 928 break; 929 930 case BNX2FC_TASK_MGMT_CMD: 931 BNX2FC_IO_DBG(io_req, "Processing TM complete\n"); 932 bnx2fc_process_tm_compl(io_req, task, num_rq); 933 break; 934 935 case BNX2FC_ABTS: 936 /* 937 * ABTS request received by firmware. ABTS response 938 * will be delivered to the task belonging to the IO 939 * that was aborted 940 */ 941 BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n"); 942 kref_put(&io_req->refcount, bnx2fc_cmd_release); 943 break; 944 945 case BNX2FC_ELS: 946 if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) 947 bnx2fc_process_els_compl(io_req, task, num_rq); 948 else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED) 949 bnx2fc_process_abts_compl(io_req, task, num_rq); 950 else if (rx_state == 951 FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED) 952 bnx2fc_process_cleanup_compl(io_req, task, num_rq); 953 else 954 printk(KERN_ERR PFX "Invalid rx state = %d\n", 955 rx_state); 956 break; 957 958 case BNX2FC_CLEANUP: 959 BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n"); 960 kref_put(&io_req->refcount, bnx2fc_cmd_release); 961 break; 962 963 case BNX2FC_SEQ_CLEANUP: 964 BNX2FC_IO_DBG(io_req, "cq_compl(0x%x) - seq cleanup resp\n", 965 io_req->xid); 966 bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state); 967 kref_put(&io_req->refcount, bnx2fc_cmd_release); 968 break; 969 970 default: 971 printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type); 972 break; 973 } 974 spin_unlock_bh(&tgt->tgt_lock); 975 } 976 977 void bnx2fc_arm_cq(struct bnx2fc_rport *tgt) 978 { 979 struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db; 980 u32 msg; 981 982 wmb(); 983 rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit << 984 FCOE_CQE_TOGGLE_BIT_SHIFT); 985 msg = *((u32 *)rx_db); 986 writel(cpu_to_le32(msg), tgt->ctx_base); 987 988 } 989 990 static struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe) 991 { 992 struct bnx2fc_work *work; 993 work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC); 994 if (!work) 995 return NULL; 996 997 INIT_LIST_HEAD(&work->list); 998 work->tgt = tgt; 999 work->wqe = wqe; 1000 return work; 1001 } 1002 1003 /* Pending work request completion */ 1004 static void bnx2fc_pending_work(struct bnx2fc_rport *tgt, unsigned int wqe) 1005 { 1006 unsigned int cpu = wqe % num_possible_cpus(); 1007 struct bnx2fc_percpu_s *fps; 1008 struct bnx2fc_work *work; 1009 1010 fps = &per_cpu(bnx2fc_percpu, cpu); 1011 spin_lock_bh(&fps->fp_work_lock); 1012 if (fps->iothread) { 1013 work = bnx2fc_alloc_work(tgt, wqe); 1014 if (work) { 1015 list_add_tail(&work->list, &fps->work_list); 1016 wake_up_process(fps->iothread); 1017 spin_unlock_bh(&fps->fp_work_lock); 1018 return; 1019 } 1020 } 1021 spin_unlock_bh(&fps->fp_work_lock); 1022 bnx2fc_process_cq_compl(tgt, wqe); 1023 } 1024 1025 int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt) 1026 { 1027 struct fcoe_cqe *cq; 1028 u32 cq_cons; 1029 struct fcoe_cqe *cqe; 1030 u32 num_free_sqes = 0; 1031 u32 num_cqes = 0; 1032 u16 wqe; 1033 1034 /* 1035 * cq_lock is a low contention lock used to protect 1036 * the CQ data structure from being freed up during 1037 * the upload operation 1038 */ 1039 spin_lock_bh(&tgt->cq_lock); 1040 1041 if (!tgt->cq) { 1042 printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n"); 1043 spin_unlock_bh(&tgt->cq_lock); 1044 return 0; 1045 } 1046 cq = tgt->cq; 1047 cq_cons = tgt->cq_cons_idx; 1048 cqe = &cq[cq_cons]; 1049 1050 while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) == 1051 (tgt->cq_curr_toggle_bit << 1052 FCOE_CQE_TOGGLE_BIT_SHIFT)) { 1053 1054 /* new entry on the cq */ 1055 if (wqe & FCOE_CQE_CQE_TYPE) { 1056 /* Unsolicited event notification */ 1057 bnx2fc_process_unsol_compl(tgt, wqe); 1058 } else { 1059 bnx2fc_pending_work(tgt, wqe); 1060 num_free_sqes++; 1061 } 1062 cqe++; 1063 tgt->cq_cons_idx++; 1064 num_cqes++; 1065 1066 if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) { 1067 tgt->cq_cons_idx = 0; 1068 cqe = cq; 1069 tgt->cq_curr_toggle_bit = 1070 1 - tgt->cq_curr_toggle_bit; 1071 } 1072 } 1073 if (num_cqes) { 1074 /* Arm CQ only if doorbell is mapped */ 1075 if (tgt->ctx_base) 1076 bnx2fc_arm_cq(tgt); 1077 atomic_add(num_free_sqes, &tgt->free_sqes); 1078 } 1079 spin_unlock_bh(&tgt->cq_lock); 1080 return 0; 1081 } 1082 1083 /** 1084 * bnx2fc_fastpath_notification - process global event queue (KCQ) 1085 * 1086 * @hba: adapter structure pointer 1087 * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry 1088 * 1089 * Fast path event notification handler 1090 */ 1091 static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba, 1092 struct fcoe_kcqe *new_cqe_kcqe) 1093 { 1094 u32 conn_id = new_cqe_kcqe->fcoe_conn_id; 1095 struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id]; 1096 1097 if (!tgt) { 1098 printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id); 1099 return; 1100 } 1101 1102 bnx2fc_process_new_cqes(tgt); 1103 } 1104 1105 /** 1106 * bnx2fc_process_ofld_cmpl - process FCoE session offload completion 1107 * 1108 * @hba: adapter structure pointer 1109 * @ofld_kcqe: connection offload kcqe pointer 1110 * 1111 * handle session offload completion, enable the session if offload is 1112 * successful. 1113 */ 1114 static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba, 1115 struct fcoe_kcqe *ofld_kcqe) 1116 { 1117 struct bnx2fc_rport *tgt; 1118 struct bnx2fc_interface *interface; 1119 u32 conn_id; 1120 u32 context_id; 1121 1122 conn_id = ofld_kcqe->fcoe_conn_id; 1123 context_id = ofld_kcqe->fcoe_conn_context_id; 1124 tgt = hba->tgt_ofld_list[conn_id]; 1125 if (!tgt) { 1126 printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n"); 1127 return; 1128 } 1129 BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n", 1130 ofld_kcqe->fcoe_conn_context_id); 1131 interface = tgt->port->priv; 1132 if (hba != interface->hba) { 1133 printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n"); 1134 goto ofld_cmpl_err; 1135 } 1136 /* 1137 * cnic has allocated a context_id for this session; use this 1138 * while enabling the session. 1139 */ 1140 tgt->context_id = context_id; 1141 if (ofld_kcqe->completion_status) { 1142 if (ofld_kcqe->completion_status == 1143 FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) { 1144 printk(KERN_ERR PFX "unable to allocate FCoE context " 1145 "resources\n"); 1146 set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags); 1147 } 1148 } else { 1149 /* FW offload request successfully completed */ 1150 set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags); 1151 } 1152 ofld_cmpl_err: 1153 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags); 1154 wake_up_interruptible(&tgt->ofld_wait); 1155 } 1156 1157 /** 1158 * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion 1159 * 1160 * @hba: adapter structure pointer 1161 * @ofld_kcqe: connection offload kcqe pointer 1162 * 1163 * handle session enable completion, mark the rport as ready 1164 */ 1165 1166 static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba, 1167 struct fcoe_kcqe *ofld_kcqe) 1168 { 1169 struct bnx2fc_rport *tgt; 1170 struct bnx2fc_interface *interface; 1171 u32 conn_id; 1172 u32 context_id; 1173 1174 context_id = ofld_kcqe->fcoe_conn_context_id; 1175 conn_id = ofld_kcqe->fcoe_conn_id; 1176 tgt = hba->tgt_ofld_list[conn_id]; 1177 if (!tgt) { 1178 printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n"); 1179 return; 1180 } 1181 1182 BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n", 1183 ofld_kcqe->fcoe_conn_context_id); 1184 1185 /* 1186 * context_id should be the same for this target during offload 1187 * and enable 1188 */ 1189 if (tgt->context_id != context_id) { 1190 printk(KERN_ERR PFX "context id mis-match\n"); 1191 return; 1192 } 1193 interface = tgt->port->priv; 1194 if (hba != interface->hba) { 1195 printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n"); 1196 goto enbl_cmpl_err; 1197 } 1198 if (!ofld_kcqe->completion_status) 1199 /* enable successful - rport ready for issuing IOs */ 1200 set_bit(BNX2FC_FLAG_ENABLED, &tgt->flags); 1201 1202 enbl_cmpl_err: 1203 set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags); 1204 wake_up_interruptible(&tgt->ofld_wait); 1205 } 1206 1207 static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba, 1208 struct fcoe_kcqe *disable_kcqe) 1209 { 1210 1211 struct bnx2fc_rport *tgt; 1212 u32 conn_id; 1213 1214 conn_id = disable_kcqe->fcoe_conn_id; 1215 tgt = hba->tgt_ofld_list[conn_id]; 1216 if (!tgt) { 1217 printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n"); 1218 return; 1219 } 1220 1221 BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id); 1222 1223 if (disable_kcqe->completion_status) { 1224 printk(KERN_ERR PFX "Disable failed with cmpl status %d\n", 1225 disable_kcqe->completion_status); 1226 set_bit(BNX2FC_FLAG_DISABLE_FAILED, &tgt->flags); 1227 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags); 1228 wake_up_interruptible(&tgt->upld_wait); 1229 } else { 1230 /* disable successful */ 1231 BNX2FC_TGT_DBG(tgt, "disable successful\n"); 1232 clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags); 1233 clear_bit(BNX2FC_FLAG_ENABLED, &tgt->flags); 1234 set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags); 1235 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags); 1236 wake_up_interruptible(&tgt->upld_wait); 1237 } 1238 } 1239 1240 static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba, 1241 struct fcoe_kcqe *destroy_kcqe) 1242 { 1243 struct bnx2fc_rport *tgt; 1244 u32 conn_id; 1245 1246 conn_id = destroy_kcqe->fcoe_conn_id; 1247 tgt = hba->tgt_ofld_list[conn_id]; 1248 if (!tgt) { 1249 printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n"); 1250 return; 1251 } 1252 1253 BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id); 1254 1255 if (destroy_kcqe->completion_status) { 1256 printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n", 1257 destroy_kcqe->completion_status); 1258 return; 1259 } else { 1260 /* destroy successful */ 1261 BNX2FC_TGT_DBG(tgt, "upload successful\n"); 1262 clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags); 1263 set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags); 1264 set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags); 1265 wake_up_interruptible(&tgt->upld_wait); 1266 } 1267 } 1268 1269 static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code) 1270 { 1271 switch (err_code) { 1272 case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE: 1273 printk(KERN_ERR PFX "init_failure due to invalid opcode\n"); 1274 break; 1275 1276 case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE: 1277 printk(KERN_ERR PFX "init failed due to ctx alloc failure\n"); 1278 break; 1279 1280 case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR: 1281 printk(KERN_ERR PFX "init_failure due to NIC error\n"); 1282 break; 1283 case FCOE_KCQE_COMPLETION_STATUS_ERROR: 1284 printk(KERN_ERR PFX "init failure due to compl status err\n"); 1285 break; 1286 case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION: 1287 printk(KERN_ERR PFX "init failure due to HSI mismatch\n"); 1288 break; 1289 default: 1290 printk(KERN_ERR PFX "Unknown Error code %d\n", err_code); 1291 } 1292 } 1293 1294 /** 1295 * bnx2fc_indicae_kcqe - process KCQE 1296 * 1297 * @hba: adapter structure pointer 1298 * @kcqe: kcqe pointer 1299 * @num_cqe: Number of completion queue elements 1300 * 1301 * Generic KCQ event handler 1302 */ 1303 void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[], 1304 u32 num_cqe) 1305 { 1306 struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context; 1307 int i = 0; 1308 struct fcoe_kcqe *kcqe = NULL; 1309 1310 while (i < num_cqe) { 1311 kcqe = (struct fcoe_kcqe *) kcq[i++]; 1312 1313 switch (kcqe->op_code) { 1314 case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION: 1315 bnx2fc_fastpath_notification(hba, kcqe); 1316 break; 1317 1318 case FCOE_KCQE_OPCODE_OFFLOAD_CONN: 1319 bnx2fc_process_ofld_cmpl(hba, kcqe); 1320 break; 1321 1322 case FCOE_KCQE_OPCODE_ENABLE_CONN: 1323 bnx2fc_process_enable_conn_cmpl(hba, kcqe); 1324 break; 1325 1326 case FCOE_KCQE_OPCODE_INIT_FUNC: 1327 if (kcqe->completion_status != 1328 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) { 1329 bnx2fc_init_failure(hba, 1330 kcqe->completion_status); 1331 } else { 1332 set_bit(ADAPTER_STATE_UP, &hba->adapter_state); 1333 bnx2fc_get_link_state(hba); 1334 printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n", 1335 (u8)hba->pcidev->bus->number); 1336 } 1337 break; 1338 1339 case FCOE_KCQE_OPCODE_DESTROY_FUNC: 1340 if (kcqe->completion_status != 1341 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) { 1342 1343 printk(KERN_ERR PFX "DESTROY failed\n"); 1344 } else { 1345 printk(KERN_ERR PFX "DESTROY success\n"); 1346 } 1347 set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags); 1348 wake_up_interruptible(&hba->destroy_wait); 1349 break; 1350 1351 case FCOE_KCQE_OPCODE_DISABLE_CONN: 1352 bnx2fc_process_conn_disable_cmpl(hba, kcqe); 1353 break; 1354 1355 case FCOE_KCQE_OPCODE_DESTROY_CONN: 1356 bnx2fc_process_conn_destroy_cmpl(hba, kcqe); 1357 break; 1358 1359 case FCOE_KCQE_OPCODE_STAT_FUNC: 1360 if (kcqe->completion_status != 1361 FCOE_KCQE_COMPLETION_STATUS_SUCCESS) 1362 printk(KERN_ERR PFX "STAT failed\n"); 1363 complete(&hba->stat_req_done); 1364 break; 1365 1366 case FCOE_KCQE_OPCODE_FCOE_ERROR: 1367 /* fall thru */ 1368 default: 1369 printk(KERN_ERR PFX "unknown opcode 0x%x\n", 1370 kcqe->op_code); 1371 } 1372 } 1373 } 1374 1375 void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid) 1376 { 1377 struct fcoe_sqe *sqe; 1378 1379 sqe = &tgt->sq[tgt->sq_prod_idx]; 1380 1381 /* Fill SQ WQE */ 1382 sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT; 1383 sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT; 1384 1385 /* Advance SQ Prod Idx */ 1386 if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) { 1387 tgt->sq_prod_idx = 0; 1388 tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit; 1389 } 1390 } 1391 1392 void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt) 1393 { 1394 struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db; 1395 u32 msg; 1396 1397 wmb(); 1398 sq_db->prod = tgt->sq_prod_idx | 1399 (tgt->sq_curr_toggle_bit << 15); 1400 msg = *((u32 *)sq_db); 1401 writel(cpu_to_le32(msg), tgt->ctx_base); 1402 1403 } 1404 1405 int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt) 1406 { 1407 u32 context_id = tgt->context_id; 1408 struct fcoe_port *port = tgt->port; 1409 u32 reg_off; 1410 resource_size_t reg_base; 1411 struct bnx2fc_interface *interface = port->priv; 1412 struct bnx2fc_hba *hba = interface->hba; 1413 1414 reg_base = pci_resource_start(hba->pcidev, 1415 BNX2X_DOORBELL_PCI_BAR); 1416 reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF); 1417 tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4); 1418 if (!tgt->ctx_base) 1419 return -ENOMEM; 1420 return 0; 1421 } 1422 1423 char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items) 1424 { 1425 char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ); 1426 1427 if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX) 1428 return NULL; 1429 1430 tgt->rq_cons_idx += num_items; 1431 1432 if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX) 1433 tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX; 1434 1435 return buf; 1436 } 1437 1438 void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items) 1439 { 1440 /* return the rq buffer */ 1441 u32 next_prod_idx = tgt->rq_prod_idx + num_items; 1442 if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) { 1443 /* Wrap around RQ */ 1444 next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX; 1445 } 1446 tgt->rq_prod_idx = next_prod_idx; 1447 tgt->conn_db->rq_prod = tgt->rq_prod_idx; 1448 } 1449 1450 void bnx2fc_init_seq_cleanup_task(struct bnx2fc_cmd *seq_clnp_req, 1451 struct fcoe_task_ctx_entry *task, 1452 struct bnx2fc_cmd *orig_io_req, 1453 u32 offset) 1454 { 1455 struct scsi_cmnd *sc_cmd = orig_io_req->sc_cmd; 1456 struct bnx2fc_rport *tgt = seq_clnp_req->tgt; 1457 struct fcoe_bd_ctx *bd = orig_io_req->bd_tbl->bd_tbl; 1458 struct fcoe_ext_mul_sges_ctx *sgl; 1459 u8 task_type = FCOE_TASK_TYPE_SEQUENCE_CLEANUP; 1460 u8 orig_task_type; 1461 u16 orig_xid = orig_io_req->xid; 1462 u32 context_id = tgt->context_id; 1463 u64 phys_addr = (u64)orig_io_req->bd_tbl->bd_tbl_dma; 1464 u32 orig_offset = offset; 1465 int bd_count; 1466 int orig_task_idx, index; 1467 int i; 1468 1469 memset(task, 0, sizeof(struct fcoe_task_ctx_entry)); 1470 1471 if (sc_cmd->sc_data_direction == DMA_TO_DEVICE) 1472 orig_task_type = FCOE_TASK_TYPE_WRITE; 1473 else 1474 orig_task_type = FCOE_TASK_TYPE_READ; 1475 1476 /* Tx flags */ 1477 task->txwr_rxrd.const_ctx.tx_flags = 1478 FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP << 1479 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT; 1480 /* init flags */ 1481 task->txwr_rxrd.const_ctx.init_flags = task_type << 1482 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT; 1483 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1484 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT; 1485 task->rxwr_txrd.const_ctx.init_flags = context_id << 1486 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT; 1487 task->rxwr_txrd.const_ctx.init_flags = context_id << 1488 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT; 1489 1490 task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid; 1491 1492 task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_seq_cnt = 0; 1493 task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_data_offset = offset; 1494 1495 bd_count = orig_io_req->bd_tbl->bd_valid; 1496 1497 /* obtain the appropriate bd entry from relative offset */ 1498 for (i = 0; i < bd_count; i++) { 1499 if (offset < bd[i].buf_len) 1500 break; 1501 offset -= bd[i].buf_len; 1502 } 1503 phys_addr += (i * sizeof(struct fcoe_bd_ctx)); 1504 1505 if (orig_task_type == FCOE_TASK_TYPE_WRITE) { 1506 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo = 1507 (u32)phys_addr; 1508 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi = 1509 (u32)((u64)phys_addr >> 32); 1510 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1511 bd_count; 1512 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_off = 1513 offset; /* adjusted offset */ 1514 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_idx = i; 1515 } else { 1516 orig_task_idx = orig_xid / BNX2FC_TASKS_PER_PAGE; 1517 index = orig_xid % BNX2FC_TASKS_PER_PAGE; 1518 1519 /* Multiple SGEs were used for this IO */ 1520 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl; 1521 sgl->mul_sgl.cur_sge_addr.lo = (u32)phys_addr; 1522 sgl->mul_sgl.cur_sge_addr.hi = (u32)((u64)phys_addr >> 32); 1523 sgl->mul_sgl.sgl_size = bd_count; 1524 sgl->mul_sgl.cur_sge_off = offset; /*adjusted offset */ 1525 sgl->mul_sgl.cur_sge_idx = i; 1526 1527 memset(&task->rxwr_only.rx_seq_ctx, 0, 1528 sizeof(struct fcoe_rx_seq_ctx)); 1529 task->rxwr_only.rx_seq_ctx.low_exp_ro = orig_offset; 1530 task->rxwr_only.rx_seq_ctx.high_exp_ro = orig_offset; 1531 } 1532 } 1533 void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req, 1534 struct fcoe_task_ctx_entry *task, 1535 u16 orig_xid) 1536 { 1537 u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP; 1538 struct bnx2fc_rport *tgt = io_req->tgt; 1539 u32 context_id = tgt->context_id; 1540 1541 memset(task, 0, sizeof(struct fcoe_task_ctx_entry)); 1542 1543 /* Tx Write Rx Read */ 1544 /* init flags */ 1545 task->txwr_rxrd.const_ctx.init_flags = task_type << 1546 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT; 1547 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1548 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT; 1549 if (tgt->dev_type == TYPE_TAPE) 1550 task->txwr_rxrd.const_ctx.init_flags |= 1551 FCOE_TASK_DEV_TYPE_TAPE << 1552 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1553 else 1554 task->txwr_rxrd.const_ctx.init_flags |= 1555 FCOE_TASK_DEV_TYPE_DISK << 1556 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1557 task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid; 1558 1559 /* Tx flags */ 1560 task->txwr_rxrd.const_ctx.tx_flags = 1561 FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP << 1562 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT; 1563 1564 /* Rx Read Tx Write */ 1565 task->rxwr_txrd.const_ctx.init_flags = context_id << 1566 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT; 1567 task->rxwr_txrd.var_ctx.rx_flags |= 1 << 1568 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT; 1569 } 1570 1571 void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req, 1572 struct fcoe_task_ctx_entry *task) 1573 { 1574 struct bnx2fc_mp_req *mp_req = &(io_req->mp_req); 1575 struct bnx2fc_rport *tgt = io_req->tgt; 1576 struct fc_frame_header *fc_hdr; 1577 struct fcoe_ext_mul_sges_ctx *sgl; 1578 u8 task_type = 0; 1579 u64 *hdr; 1580 u64 temp_hdr[3]; 1581 u32 context_id; 1582 1583 1584 /* Obtain task_type */ 1585 if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) || 1586 (io_req->cmd_type == BNX2FC_ELS)) { 1587 task_type = FCOE_TASK_TYPE_MIDPATH; 1588 } else if (io_req->cmd_type == BNX2FC_ABTS) { 1589 task_type = FCOE_TASK_TYPE_ABTS; 1590 } 1591 1592 memset(task, 0, sizeof(struct fcoe_task_ctx_entry)); 1593 1594 /* Setup the task from io_req for easy reference */ 1595 io_req->task = task; 1596 1597 BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n", 1598 io_req->cmd_type, task_type); 1599 1600 /* Tx only */ 1601 if ((task_type == FCOE_TASK_TYPE_MIDPATH) || 1602 (task_type == FCOE_TASK_TYPE_UNSOLICITED)) { 1603 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo = 1604 (u32)mp_req->mp_req_bd_dma; 1605 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi = 1606 (u32)((u64)mp_req->mp_req_bd_dma >> 32); 1607 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1; 1608 } 1609 1610 /* Tx Write Rx Read */ 1611 /* init flags */ 1612 task->txwr_rxrd.const_ctx.init_flags = task_type << 1613 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT; 1614 if (tgt->dev_type == TYPE_TAPE) 1615 task->txwr_rxrd.const_ctx.init_flags |= 1616 FCOE_TASK_DEV_TYPE_TAPE << 1617 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1618 else 1619 task->txwr_rxrd.const_ctx.init_flags |= 1620 FCOE_TASK_DEV_TYPE_DISK << 1621 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1622 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1623 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT; 1624 1625 /* tx flags */ 1626 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT << 1627 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT; 1628 1629 /* Rx Write Tx Read */ 1630 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len; 1631 1632 /* rx flags */ 1633 task->rxwr_txrd.var_ctx.rx_flags |= 1 << 1634 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT; 1635 1636 context_id = tgt->context_id; 1637 task->rxwr_txrd.const_ctx.init_flags = context_id << 1638 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT; 1639 1640 fc_hdr = &(mp_req->req_fc_hdr); 1641 if (task_type == FCOE_TASK_TYPE_MIDPATH) { 1642 fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid); 1643 fc_hdr->fh_rx_id = htons(0xffff); 1644 task->rxwr_txrd.var_ctx.rx_id = 0xffff; 1645 } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) { 1646 fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid); 1647 } 1648 1649 /* Fill FC Header into middle path buffer */ 1650 hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr; 1651 memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr)); 1652 hdr[0] = cpu_to_be64(temp_hdr[0]); 1653 hdr[1] = cpu_to_be64(temp_hdr[1]); 1654 hdr[2] = cpu_to_be64(temp_hdr[2]); 1655 1656 /* Rx Only */ 1657 if (task_type == FCOE_TASK_TYPE_MIDPATH) { 1658 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl; 1659 1660 sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma; 1661 sgl->mul_sgl.cur_sge_addr.hi = 1662 (u32)((u64)mp_req->mp_resp_bd_dma >> 32); 1663 sgl->mul_sgl.sgl_size = 1; 1664 } 1665 } 1666 1667 void bnx2fc_init_task(struct bnx2fc_cmd *io_req, 1668 struct fcoe_task_ctx_entry *task) 1669 { 1670 u8 task_type; 1671 struct scsi_cmnd *sc_cmd = io_req->sc_cmd; 1672 struct io_bdt *bd_tbl = io_req->bd_tbl; 1673 struct bnx2fc_rport *tgt = io_req->tgt; 1674 struct fcoe_cached_sge_ctx *cached_sge; 1675 struct fcoe_ext_mul_sges_ctx *sgl; 1676 int dev_type = tgt->dev_type; 1677 u64 *fcp_cmnd; 1678 u64 tmp_fcp_cmnd[4]; 1679 u32 context_id; 1680 int cnt, i; 1681 int bd_count; 1682 1683 memset(task, 0, sizeof(struct fcoe_task_ctx_entry)); 1684 1685 /* Setup the task from io_req for easy reference */ 1686 io_req->task = task; 1687 1688 if (sc_cmd->sc_data_direction == DMA_TO_DEVICE) 1689 task_type = FCOE_TASK_TYPE_WRITE; 1690 else 1691 task_type = FCOE_TASK_TYPE_READ; 1692 1693 /* Tx only */ 1694 bd_count = bd_tbl->bd_valid; 1695 cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge; 1696 if (task_type == FCOE_TASK_TYPE_WRITE) { 1697 if ((dev_type == TYPE_DISK) && (bd_count == 1)) { 1698 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl; 1699 1700 task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.lo = 1701 cached_sge->cur_buf_addr.lo = 1702 fcoe_bd_tbl->buf_addr_lo; 1703 task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.hi = 1704 cached_sge->cur_buf_addr.hi = 1705 fcoe_bd_tbl->buf_addr_hi; 1706 task->txwr_only.sgl_ctx.cached_sge.cur_buf_rem = 1707 cached_sge->cur_buf_rem = 1708 fcoe_bd_tbl->buf_len; 1709 1710 task->txwr_rxrd.const_ctx.init_flags |= 1 << 1711 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT; 1712 } else { 1713 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo = 1714 (u32)bd_tbl->bd_tbl_dma; 1715 task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi = 1716 (u32)((u64)bd_tbl->bd_tbl_dma >> 32); 1717 task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1718 bd_tbl->bd_valid; 1719 } 1720 } 1721 1722 /*Tx Write Rx Read */ 1723 /* Init state to NORMAL */ 1724 task->txwr_rxrd.const_ctx.init_flags |= task_type << 1725 FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT; 1726 if (dev_type == TYPE_TAPE) { 1727 task->txwr_rxrd.const_ctx.init_flags |= 1728 FCOE_TASK_DEV_TYPE_TAPE << 1729 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1730 io_req->rec_retry = 0; 1731 io_req->rec_retry = 0; 1732 } else 1733 task->txwr_rxrd.const_ctx.init_flags |= 1734 FCOE_TASK_DEV_TYPE_DISK << 1735 FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT; 1736 task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 << 1737 FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT; 1738 /* tx flags */ 1739 task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL << 1740 FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT; 1741 1742 /* Set initial seq counter */ 1743 task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1; 1744 1745 /* Fill FCP_CMND IU */ 1746 fcp_cmnd = (u64 *) 1747 task->txwr_rxrd.union_ctx.fcp_cmd.opaque; 1748 bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd); 1749 1750 /* swap fcp_cmnd */ 1751 cnt = sizeof(struct fcp_cmnd) / sizeof(u64); 1752 1753 for (i = 0; i < cnt; i++) { 1754 *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]); 1755 fcp_cmnd++; 1756 } 1757 1758 /* Rx Write Tx Read */ 1759 task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len; 1760 1761 context_id = tgt->context_id; 1762 task->rxwr_txrd.const_ctx.init_flags = context_id << 1763 FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT; 1764 1765 /* rx flags */ 1766 /* Set state to "waiting for the first packet" */ 1767 task->rxwr_txrd.var_ctx.rx_flags |= 1 << 1768 FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT; 1769 1770 task->rxwr_txrd.var_ctx.rx_id = 0xffff; 1771 1772 /* Rx Only */ 1773 if (task_type != FCOE_TASK_TYPE_READ) 1774 return; 1775 1776 sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl; 1777 bd_count = bd_tbl->bd_valid; 1778 1779 if (dev_type == TYPE_DISK) { 1780 if (bd_count == 1) { 1781 1782 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl; 1783 1784 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo; 1785 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi; 1786 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len; 1787 task->txwr_rxrd.const_ctx.init_flags |= 1 << 1788 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT; 1789 } else if (bd_count == 2) { 1790 struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl; 1791 1792 cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo; 1793 cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi; 1794 cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len; 1795 1796 fcoe_bd_tbl++; 1797 cached_sge->second_buf_addr.lo = 1798 fcoe_bd_tbl->buf_addr_lo; 1799 cached_sge->second_buf_addr.hi = 1800 fcoe_bd_tbl->buf_addr_hi; 1801 cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len; 1802 task->txwr_rxrd.const_ctx.init_flags |= 1 << 1803 FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT; 1804 } else { 1805 1806 sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma; 1807 sgl->mul_sgl.cur_sge_addr.hi = 1808 (u32)((u64)bd_tbl->bd_tbl_dma >> 32); 1809 sgl->mul_sgl.sgl_size = bd_count; 1810 } 1811 } else { 1812 sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma; 1813 sgl->mul_sgl.cur_sge_addr.hi = 1814 (u32)((u64)bd_tbl->bd_tbl_dma >> 32); 1815 sgl->mul_sgl.sgl_size = bd_count; 1816 } 1817 } 1818 1819 /** 1820 * bnx2fc_setup_task_ctx - allocate and map task context 1821 * 1822 * @hba: pointer to adapter structure 1823 * 1824 * allocate memory for task context, and associated BD table to be used 1825 * by firmware 1826 * 1827 */ 1828 int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba) 1829 { 1830 int rc = 0; 1831 struct regpair *task_ctx_bdt; 1832 dma_addr_t addr; 1833 int task_ctx_arr_sz; 1834 int i; 1835 1836 /* 1837 * Allocate task context bd table. A page size of bd table 1838 * can map 256 buffers. Each buffer contains 32 task context 1839 * entries. Hence the limit with one page is 8192 task context 1840 * entries. 1841 */ 1842 hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev, 1843 PAGE_SIZE, 1844 &hba->task_ctx_bd_dma, 1845 GFP_KERNEL); 1846 if (!hba->task_ctx_bd_tbl) { 1847 printk(KERN_ERR PFX "unable to allocate task context BDT\n"); 1848 rc = -1; 1849 goto out; 1850 } 1851 1852 /* 1853 * Allocate task_ctx which is an array of pointers pointing to 1854 * a page containing 32 task contexts 1855 */ 1856 task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE); 1857 hba->task_ctx = kzalloc((task_ctx_arr_sz * sizeof(void *)), 1858 GFP_KERNEL); 1859 if (!hba->task_ctx) { 1860 printk(KERN_ERR PFX "unable to allocate task context array\n"); 1861 rc = -1; 1862 goto out1; 1863 } 1864 1865 /* 1866 * Allocate task_ctx_dma which is an array of dma addresses 1867 */ 1868 hba->task_ctx_dma = kmalloc((task_ctx_arr_sz * 1869 sizeof(dma_addr_t)), GFP_KERNEL); 1870 if (!hba->task_ctx_dma) { 1871 printk(KERN_ERR PFX "unable to alloc context mapping array\n"); 1872 rc = -1; 1873 goto out2; 1874 } 1875 1876 task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl; 1877 for (i = 0; i < task_ctx_arr_sz; i++) { 1878 1879 hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev, 1880 PAGE_SIZE, 1881 &hba->task_ctx_dma[i], 1882 GFP_KERNEL); 1883 if (!hba->task_ctx[i]) { 1884 printk(KERN_ERR PFX "unable to alloc task context\n"); 1885 rc = -1; 1886 goto out3; 1887 } 1888 addr = (u64)hba->task_ctx_dma[i]; 1889 task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32); 1890 task_ctx_bdt->lo = cpu_to_le32((u32)addr); 1891 task_ctx_bdt++; 1892 } 1893 return 0; 1894 1895 out3: 1896 for (i = 0; i < task_ctx_arr_sz; i++) { 1897 if (hba->task_ctx[i]) { 1898 1899 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 1900 hba->task_ctx[i], hba->task_ctx_dma[i]); 1901 hba->task_ctx[i] = NULL; 1902 } 1903 } 1904 1905 kfree(hba->task_ctx_dma); 1906 hba->task_ctx_dma = NULL; 1907 out2: 1908 kfree(hba->task_ctx); 1909 hba->task_ctx = NULL; 1910 out1: 1911 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 1912 hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma); 1913 hba->task_ctx_bd_tbl = NULL; 1914 out: 1915 return rc; 1916 } 1917 1918 void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba) 1919 { 1920 int task_ctx_arr_sz; 1921 int i; 1922 1923 if (hba->task_ctx_bd_tbl) { 1924 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 1925 hba->task_ctx_bd_tbl, 1926 hba->task_ctx_bd_dma); 1927 hba->task_ctx_bd_tbl = NULL; 1928 } 1929 1930 task_ctx_arr_sz = (hba->max_tasks / BNX2FC_TASKS_PER_PAGE); 1931 if (hba->task_ctx) { 1932 for (i = 0; i < task_ctx_arr_sz; i++) { 1933 if (hba->task_ctx[i]) { 1934 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 1935 hba->task_ctx[i], 1936 hba->task_ctx_dma[i]); 1937 hba->task_ctx[i] = NULL; 1938 } 1939 } 1940 kfree(hba->task_ctx); 1941 hba->task_ctx = NULL; 1942 } 1943 1944 kfree(hba->task_ctx_dma); 1945 hba->task_ctx_dma = NULL; 1946 } 1947 1948 static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba) 1949 { 1950 int i; 1951 int segment_count; 1952 u32 *pbl; 1953 1954 if (hba->hash_tbl_segments) { 1955 1956 pbl = hba->hash_tbl_pbl; 1957 if (pbl) { 1958 segment_count = hba->hash_tbl_segment_count; 1959 for (i = 0; i < segment_count; ++i) { 1960 dma_addr_t dma_address; 1961 1962 dma_address = le32_to_cpu(*pbl); 1963 ++pbl; 1964 dma_address += ((u64)le32_to_cpu(*pbl)) << 32; 1965 ++pbl; 1966 dma_free_coherent(&hba->pcidev->dev, 1967 BNX2FC_HASH_TBL_CHUNK_SIZE, 1968 hba->hash_tbl_segments[i], 1969 dma_address); 1970 } 1971 } 1972 1973 kfree(hba->hash_tbl_segments); 1974 hba->hash_tbl_segments = NULL; 1975 } 1976 1977 if (hba->hash_tbl_pbl) { 1978 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 1979 hba->hash_tbl_pbl, 1980 hba->hash_tbl_pbl_dma); 1981 hba->hash_tbl_pbl = NULL; 1982 } 1983 } 1984 1985 static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba) 1986 { 1987 int i; 1988 int hash_table_size; 1989 int segment_count; 1990 int segment_array_size; 1991 int dma_segment_array_size; 1992 dma_addr_t *dma_segment_array; 1993 u32 *pbl; 1994 1995 hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL * 1996 sizeof(struct fcoe_hash_table_entry); 1997 1998 segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1; 1999 segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE; 2000 hba->hash_tbl_segment_count = segment_count; 2001 2002 segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments); 2003 hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL); 2004 if (!hba->hash_tbl_segments) { 2005 printk(KERN_ERR PFX "hash table pointers alloc failed\n"); 2006 return -ENOMEM; 2007 } 2008 dma_segment_array_size = segment_count * sizeof(*dma_segment_array); 2009 dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL); 2010 if (!dma_segment_array) { 2011 printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n"); 2012 goto cleanup_ht; 2013 } 2014 2015 for (i = 0; i < segment_count; ++i) { 2016 hba->hash_tbl_segments[i] = dma_alloc_coherent(&hba->pcidev->dev, 2017 BNX2FC_HASH_TBL_CHUNK_SIZE, 2018 &dma_segment_array[i], 2019 GFP_KERNEL); 2020 if (!hba->hash_tbl_segments[i]) { 2021 printk(KERN_ERR PFX "hash segment alloc failed\n"); 2022 goto cleanup_dma; 2023 } 2024 } 2025 2026 hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev, PAGE_SIZE, 2027 &hba->hash_tbl_pbl_dma, 2028 GFP_KERNEL); 2029 if (!hba->hash_tbl_pbl) { 2030 printk(KERN_ERR PFX "hash table pbl alloc failed\n"); 2031 goto cleanup_dma; 2032 } 2033 2034 pbl = hba->hash_tbl_pbl; 2035 for (i = 0; i < segment_count; ++i) { 2036 u64 paddr = dma_segment_array[i]; 2037 *pbl = cpu_to_le32((u32) paddr); 2038 ++pbl; 2039 *pbl = cpu_to_le32((u32) (paddr >> 32)); 2040 ++pbl; 2041 } 2042 pbl = hba->hash_tbl_pbl; 2043 i = 0; 2044 while (*pbl && *(pbl + 1)) { 2045 u32 lo; 2046 u32 hi; 2047 lo = *pbl; 2048 ++pbl; 2049 hi = *pbl; 2050 ++pbl; 2051 ++i; 2052 } 2053 kfree(dma_segment_array); 2054 return 0; 2055 2056 cleanup_dma: 2057 for (i = 0; i < segment_count; ++i) { 2058 if (hba->hash_tbl_segments[i]) 2059 dma_free_coherent(&hba->pcidev->dev, 2060 BNX2FC_HASH_TBL_CHUNK_SIZE, 2061 hba->hash_tbl_segments[i], 2062 dma_segment_array[i]); 2063 } 2064 2065 kfree(dma_segment_array); 2066 2067 cleanup_ht: 2068 kfree(hba->hash_tbl_segments); 2069 hba->hash_tbl_segments = NULL; 2070 return -ENOMEM; 2071 } 2072 2073 /** 2074 * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer 2075 * 2076 * @hba: Pointer to adapter structure 2077 * 2078 */ 2079 int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba) 2080 { 2081 u64 addr; 2082 u32 mem_size; 2083 int i; 2084 2085 if (bnx2fc_allocate_hash_table(hba)) 2086 return -ENOMEM; 2087 2088 mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair); 2089 hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size, 2090 &hba->t2_hash_tbl_ptr_dma, 2091 GFP_KERNEL); 2092 if (!hba->t2_hash_tbl_ptr) { 2093 printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n"); 2094 bnx2fc_free_fw_resc(hba); 2095 return -ENOMEM; 2096 } 2097 2098 mem_size = BNX2FC_NUM_MAX_SESS * 2099 sizeof(struct fcoe_t2_hash_table_entry); 2100 hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size, 2101 &hba->t2_hash_tbl_dma, 2102 GFP_KERNEL); 2103 if (!hba->t2_hash_tbl) { 2104 printk(KERN_ERR PFX "unable to allocate t2 hash table\n"); 2105 bnx2fc_free_fw_resc(hba); 2106 return -ENOMEM; 2107 } 2108 for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) { 2109 addr = (unsigned long) hba->t2_hash_tbl_dma + 2110 ((i+1) * sizeof(struct fcoe_t2_hash_table_entry)); 2111 hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff; 2112 hba->t2_hash_tbl[i].next.hi = addr >> 32; 2113 } 2114 2115 hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev, 2116 PAGE_SIZE, &hba->dummy_buf_dma, 2117 GFP_KERNEL); 2118 if (!hba->dummy_buffer) { 2119 printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n"); 2120 bnx2fc_free_fw_resc(hba); 2121 return -ENOMEM; 2122 } 2123 2124 hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev, PAGE_SIZE, 2125 &hba->stats_buf_dma, 2126 GFP_KERNEL); 2127 if (!hba->stats_buffer) { 2128 printk(KERN_ERR PFX "unable to alloc Stats Buffer\n"); 2129 bnx2fc_free_fw_resc(hba); 2130 return -ENOMEM; 2131 } 2132 2133 return 0; 2134 } 2135 2136 void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba) 2137 { 2138 u32 mem_size; 2139 2140 if (hba->stats_buffer) { 2141 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 2142 hba->stats_buffer, hba->stats_buf_dma); 2143 hba->stats_buffer = NULL; 2144 } 2145 2146 if (hba->dummy_buffer) { 2147 dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE, 2148 hba->dummy_buffer, hba->dummy_buf_dma); 2149 hba->dummy_buffer = NULL; 2150 } 2151 2152 if (hba->t2_hash_tbl_ptr) { 2153 mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair); 2154 dma_free_coherent(&hba->pcidev->dev, mem_size, 2155 hba->t2_hash_tbl_ptr, 2156 hba->t2_hash_tbl_ptr_dma); 2157 hba->t2_hash_tbl_ptr = NULL; 2158 } 2159 2160 if (hba->t2_hash_tbl) { 2161 mem_size = BNX2FC_NUM_MAX_SESS * 2162 sizeof(struct fcoe_t2_hash_table_entry); 2163 dma_free_coherent(&hba->pcidev->dev, mem_size, 2164 hba->t2_hash_tbl, hba->t2_hash_tbl_dma); 2165 hba->t2_hash_tbl = NULL; 2166 } 2167 bnx2fc_free_hash_table(hba); 2168 } 2169