1 /* 2 * Copyright 2017 Broadcom. All Rights Reserved. 3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@broadcom.com 12 * 13 */ 14 15 #ifndef _BEISCSI_MAIN_ 16 #define _BEISCSI_MAIN_ 17 18 #include <linux/kernel.h> 19 #include <linux/pci.h> 20 #include <linux/if_ether.h> 21 #include <linux/in.h> 22 #include <linux/ctype.h> 23 #include <linux/module.h> 24 #include <linux/aer.h> 25 #include <scsi/scsi.h> 26 #include <scsi/scsi_cmnd.h> 27 #include <scsi/scsi_device.h> 28 #include <scsi/scsi_host.h> 29 #include <scsi/iscsi_proto.h> 30 #include <scsi/libiscsi.h> 31 #include <scsi/scsi_transport_iscsi.h> 32 33 #define DRV_NAME "be2iscsi" 34 #define BUILD_STR "11.4.0.1" 35 #define BE_NAME "Emulex OneConnect" \ 36 "Open-iSCSI Driver version" BUILD_STR 37 #define DRV_DESC BE_NAME " " "Driver" 38 39 #define BE_VENDOR_ID 0x19A2 40 #define ELX_VENDOR_ID 0x10DF 41 /* DEVICE ID's for BE2 */ 42 #define BE_DEVICE_ID1 0x212 43 #define OC_DEVICE_ID1 0x702 44 #define OC_DEVICE_ID2 0x703 45 46 /* DEVICE ID's for BE3 */ 47 #define BE_DEVICE_ID2 0x222 48 #define OC_DEVICE_ID3 0x712 49 50 /* DEVICE ID for SKH */ 51 #define OC_SKH_ID1 0x722 52 53 #define BE2_IO_DEPTH 1024 54 #define BE2_MAX_SESSIONS 256 55 #define BE2_TMFS 16 56 #define BE2_NOPOUT_REQ 16 57 #define BE2_SGE 32 58 #define BE2_DEFPDU_HDR_SZ 64 59 #define BE2_DEFPDU_DATA_SZ 8192 60 #define BE2_MAX_NUM_CQ_PROC 512 61 62 #define MAX_CPUS 64U 63 #define BEISCSI_MAX_NUM_CPUS 7 64 65 #define BEISCSI_VER_STRLEN 32 66 67 #define BEISCSI_SGLIST_ELEMENTS 30 68 69 /** 70 * BE_INVLDT_CMD_TBL_SZ is 128 which is total number commands that can 71 * be invalidated at a time, consider it before changing the value of 72 * BEISCSI_CMD_PER_LUN. 73 */ 74 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */ 75 #define BEISCSI_MAX_SECTORS 1024 /* scsi_host->max_sectors */ 76 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */ 77 78 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */ 79 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */ 80 #define BEISCSI_MAX_FRAGS_INIT 192 81 82 #define BE_SENSE_INFO_SIZE 258 83 #define BE_ISCSI_PDU_HEADER_SIZE 64 84 #define BE_MIN_MEM_SIZE 16384 85 #define MAX_CMD_SZ 65536 86 #define IIOC_SCSI_DATA 0x05 /* Write Operation */ 87 88 /** 89 * hardware needs the async PDU buffers to be posted in multiples of 8 90 * So have atleast 8 of them by default 91 */ 92 93 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \ 94 (phwi->phwi_ctxt->pasync_ctx[ulp_num]) 95 96 /********* Memory BAR register ************/ 97 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc 98 /** 99 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt 100 * Disable" may still globally block interrupts in addition to individual 101 * interrupt masks; a mechanism for the device driver to block all interrupts 102 * atomically without having to arbitrate for the PCI Interrupt Disable bit 103 * with the OS. 104 */ 105 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ 106 107 /********* ISR0 Register offset **********/ 108 #define CEV_ISR0_OFFSET 0xC18 109 #define CEV_ISR_SIZE 4 110 111 /** 112 * Macros for reading/writing a protection domain or CSR registers 113 * in BladeEngine. 114 */ 115 116 #define DB_TXULP0_OFFSET 0x40 117 #define DB_RXULP0_OFFSET 0xA0 118 /********* Event Q door bell *************/ 119 #define DB_EQ_OFFSET DB_CQ_OFFSET 120 #define DB_EQ_RING_ID_LOW_MASK 0x1FF /* bits 0 - 8 */ 121 /* Clear the interrupt for this eq */ 122 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ 123 /* Must be 1 */ 124 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ 125 /* Higher Order EQ_ID bit */ 126 #define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */ 127 #define DB_EQ_HIGH_SET_SHIFT 11 128 #define DB_EQ_HIGH_FEILD_SHIFT 9 129 /* Number of event entries processed */ 130 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 131 /* Rearm bit */ 132 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ 133 134 /********* Compl Q door bell *************/ 135 #define DB_CQ_OFFSET 0x120 136 #define DB_CQ_RING_ID_LOW_MASK 0x3FF /* bits 0 - 9 */ 137 /* Higher Order CQ_ID bit */ 138 #define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */ 139 #define DB_CQ_HIGH_SET_SHIFT 11 140 #define DB_CQ_HIGH_FEILD_SHIFT 10 141 142 /* Number of event entries processed */ 143 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 144 /* Rearm bit */ 145 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ 146 147 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr) 148 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\ 149 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id) 150 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\ 151 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id) 152 153 #define PAGES_REQUIRED(x) \ 154 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE)) 155 156 #define MEM_DESCR_OFFSET 8 157 #define BEISCSI_DEFQ_HDR 1 158 #define BEISCSI_DEFQ_DATA 0 159 enum be_mem_enum { 160 HWI_MEM_ADDN_CONTEXT, 161 HWI_MEM_WRB, 162 HWI_MEM_WRBH, 163 HWI_MEM_SGLH, 164 HWI_MEM_SGE, 165 HWI_MEM_TEMPLATE_HDR_ULP0, 166 HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */ 167 HWI_MEM_ASYNC_DATA_BUF_ULP0, 168 HWI_MEM_ASYNC_HEADER_RING_ULP0, 169 HWI_MEM_ASYNC_DATA_RING_ULP0, 170 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0, 171 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */ 172 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0, 173 HWI_MEM_TEMPLATE_HDR_ULP1, 174 HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */ 175 HWI_MEM_ASYNC_DATA_BUF_ULP1, 176 HWI_MEM_ASYNC_HEADER_RING_ULP1, 177 HWI_MEM_ASYNC_DATA_RING_ULP1, 178 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1, 179 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */ 180 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1, 181 ISCSI_MEM_GLOBAL_HEADER, 182 SE_MEM_MAX 183 }; 184 185 struct be_bus_address32 { 186 unsigned int address_lo; 187 unsigned int address_hi; 188 }; 189 190 struct be_bus_address64 { 191 unsigned long long address; 192 }; 193 194 struct be_bus_address { 195 union { 196 struct be_bus_address32 a32; 197 struct be_bus_address64 a64; 198 } u; 199 }; 200 201 struct mem_array { 202 struct be_bus_address bus_address; /* Bus address of location */ 203 void *virtual_address; /* virtual address to the location */ 204 unsigned int size; /* Size required by memory block */ 205 }; 206 207 struct be_mem_descriptor { 208 unsigned int size_in_bytes; /* Size required by memory block */ 209 unsigned int num_elements; 210 struct mem_array *mem_array; 211 }; 212 213 struct sgl_handle { 214 unsigned int sgl_index; 215 unsigned int type; 216 unsigned int cid; 217 struct iscsi_task *task; 218 struct iscsi_sge *pfrag; 219 }; 220 221 struct hba_parameters { 222 unsigned int ios_per_ctrl; 223 unsigned int cxns_per_ctrl; 224 unsigned int icds_per_ctrl; 225 unsigned int num_sge_per_io; 226 unsigned int defpdu_hdr_sz; 227 unsigned int defpdu_data_sz; 228 unsigned int num_cq_entries; 229 unsigned int num_eq_entries; 230 unsigned int wrbs_per_cxn; 231 unsigned int hwi_ws_sz; 232 }; 233 234 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \ 235 (phwi_ctrlr->wrb_context[cri].ulp_num) 236 struct hwi_wrb_context { 237 spinlock_t wrb_lock; 238 struct wrb_handle **pwrb_handle_base; 239 struct wrb_handle **pwrb_handle_basestd; 240 struct iscsi_wrb *plast_wrb; 241 unsigned short alloc_index; 242 unsigned short free_index; 243 unsigned short wrb_handles_available; 244 unsigned short cid; 245 uint8_t ulp_num; /* ULP to which CID binded */ 246 uint32_t doorbell_offset; 247 }; 248 249 struct ulp_cid_info { 250 unsigned short *cid_array; 251 unsigned short avlbl_cids; 252 unsigned short cid_alloc; 253 unsigned short cid_free; 254 }; 255 256 #include "be.h" 257 #define chip_be2(phba) (phba->generation == BE_GEN2) 258 #define chip_be3_r(phba) (phba->generation == BE_GEN3) 259 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba))) 260 261 #define BEISCSI_ULP0 0 262 #define BEISCSI_ULP1 1 263 #define BEISCSI_ULP_COUNT 2 264 #define BEISCSI_ULP0_LOADED 0x01 265 #define BEISCSI_ULP1_LOADED 0x02 266 267 #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \ 268 (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids) 269 #define BEISCSI_ULP0_AVLBL_CID(phba) \ 270 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0) 271 #define BEISCSI_ULP1_AVLBL_CID(phba) \ 272 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1) 273 274 struct beiscsi_hba { 275 struct hba_parameters params; 276 struct hwi_controller *phwi_ctrlr; 277 unsigned int mem_req[SE_MEM_MAX]; 278 /* PCI BAR mapped addresses */ 279 u8 __iomem *csr_va; /* CSR */ 280 u8 __iomem *db_va; /* Door Bell */ 281 u8 __iomem *pci_va; /* PCI Config */ 282 /* PCI representation of our HBA */ 283 struct pci_dev *pcidev; 284 unsigned int num_cpus; 285 unsigned int nxt_cqid; 286 char *msi_name[MAX_CPUS]; 287 struct be_mem_descriptor *init_mem; 288 289 unsigned short io_sgl_alloc_index; 290 unsigned short io_sgl_free_index; 291 unsigned short io_sgl_hndl_avbl; 292 struct sgl_handle **io_sgl_hndl_base; 293 294 unsigned short eh_sgl_alloc_index; 295 unsigned short eh_sgl_free_index; 296 unsigned short eh_sgl_hndl_avbl; 297 struct sgl_handle **eh_sgl_hndl_base; 298 spinlock_t io_sgl_lock; 299 spinlock_t mgmt_sgl_lock; 300 spinlock_t async_pdu_lock; 301 struct list_head hba_queue; 302 #define BE_MAX_SESSION 2048 303 #define BE_INVALID_CID 0xffff 304 #define BE_SET_CID_TO_CRI(cri_index, cid) \ 305 (phba->cid_to_cri_map[cid] = cri_index) 306 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid]) 307 unsigned short cid_to_cri_map[BE_MAX_SESSION]; 308 struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT]; 309 struct iscsi_endpoint **ep_array; 310 struct beiscsi_conn **conn_table; 311 struct Scsi_Host *shost; 312 struct iscsi_iface *ipv4_iface; 313 struct iscsi_iface *ipv6_iface; 314 struct { 315 /** 316 * group together since they are used most frequently 317 * for cid to cri conversion 318 */ 319 #define BEISCSI_PHYS_PORT_MAX 4 320 unsigned int phys_port; 321 /* valid values of phys_port id are 0, 1, 2, 3 */ 322 unsigned int eqid_count; 323 unsigned int cqid_count; 324 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT]; 325 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \ 326 (phba->fw_config.iscsi_cid_count[ulp_num]) 327 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT]; 328 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT]; 329 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT]; 330 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT]; 331 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT]; 332 333 unsigned short iscsi_features; 334 uint16_t dual_ulp_aware; 335 unsigned long ulp_supported; 336 } fw_config; 337 338 unsigned long state; 339 #define BEISCSI_HBA_ONLINE 0 340 #define BEISCSI_HBA_LINK_UP 1 341 #define BEISCSI_HBA_BOOT_FOUND 2 342 #define BEISCSI_HBA_BOOT_WORK 3 343 #define BEISCSI_HBA_UER_SUPP 4 344 #define BEISCSI_HBA_PCI_ERR 5 345 #define BEISCSI_HBA_FW_TIMEOUT 6 346 #define BEISCSI_HBA_IN_UE 7 347 #define BEISCSI_HBA_IN_TPE 8 348 349 /* error bits */ 350 #define BEISCSI_HBA_IN_ERR ((1 << BEISCSI_HBA_PCI_ERR) | \ 351 (1 << BEISCSI_HBA_FW_TIMEOUT) | \ 352 (1 << BEISCSI_HBA_IN_UE) | \ 353 (1 << BEISCSI_HBA_IN_TPE)) 354 355 u8 optic_state; 356 struct delayed_work eqd_update; 357 /* update EQ delay timer every 1000ms */ 358 #define BEISCSI_EQD_UPDATE_INTERVAL 1000 359 struct timer_list hw_check; 360 /* check for UE every 1000ms */ 361 #define BEISCSI_UE_DETECT_INTERVAL 1000 362 u32 ue2rp; 363 struct delayed_work recover_port; 364 struct work_struct sess_work; 365 366 bool mac_addr_set; 367 u8 mac_address[ETH_ALEN]; 368 u8 port_name; 369 u8 port_speed; 370 char fw_ver_str[BEISCSI_VER_STRLEN]; 371 struct workqueue_struct *wq; /* The actuak work queue */ 372 struct be_ctrl_info ctrl; 373 unsigned int generation; 374 unsigned int interface_handle; 375 376 struct be_aic_obj aic_obj[MAX_CPUS]; 377 unsigned int attr_log_enable; 378 int (*iotask_fn)(struct iscsi_task *, 379 struct scatterlist *sg, 380 uint32_t num_sg, uint32_t xferlen, 381 uint32_t writedir); 382 struct boot_struct { 383 int retry; 384 unsigned int tag; 385 unsigned int s_handle; 386 struct be_dma_mem nonemb_cmd; 387 enum { 388 BEISCSI_BOOT_REOPEN_SESS = 1, 389 BEISCSI_BOOT_GET_SHANDLE, 390 BEISCSI_BOOT_GET_SINFO, 391 BEISCSI_BOOT_LOGOUT_SESS, 392 BEISCSI_BOOT_CREATE_KSET, 393 } action; 394 struct mgmt_session_info boot_sess; 395 struct iscsi_boot_kset *boot_kset; 396 } boot_struct; 397 struct work_struct boot_work; 398 }; 399 400 #define beiscsi_hba_in_error(phba) ((phba)->state & BEISCSI_HBA_IN_ERR) 401 #define beiscsi_hba_is_online(phba) \ 402 (!beiscsi_hba_in_error((phba)) && \ 403 test_bit(BEISCSI_HBA_ONLINE, &phba->state)) 404 405 struct beiscsi_session { 406 struct dma_pool *bhs_pool; 407 }; 408 409 /** 410 * struct beiscsi_conn - iscsi connection structure 411 */ 412 struct beiscsi_conn { 413 struct iscsi_conn *conn; 414 struct beiscsi_hba *phba; 415 u32 exp_statsn; 416 u32 doorbell_offset; 417 u32 beiscsi_conn_cid; 418 struct beiscsi_endpoint *ep; 419 unsigned short login_in_progress; 420 struct wrb_handle *plogin_wrb_handle; 421 struct sgl_handle *plogin_sgl_handle; 422 struct beiscsi_session *beiscsi_sess; 423 struct iscsi_task *task; 424 }; 425 426 /* This structure is used by the chip */ 427 struct pdu_data_out { 428 u32 dw[12]; 429 }; 430 /** 431 * Pseudo amap definition in which each bit of the actual structure is defined 432 * as a byte: used to calculate offset/shift/mask of each field 433 */ 434 struct amap_pdu_data_out { 435 u8 opcode[6]; /* opcode */ 436 u8 rsvd0[2]; /* should be 0 */ 437 u8 rsvd1[7]; 438 u8 final_bit; /* F bit */ 439 u8 rsvd2[16]; 440 u8 ahs_length[8]; /* no AHS */ 441 u8 data_len_hi[8]; 442 u8 data_len_lo[16]; /* DataSegmentLength */ 443 u8 lun[64]; 444 u8 itt[32]; /* ITT; initiator task tag */ 445 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */ 446 u8 rsvd3[32]; 447 u8 exp_stat_sn[32]; 448 u8 rsvd4[32]; 449 u8 data_sn[32]; 450 u8 buffer_offset[32]; 451 u8 rsvd5[32]; 452 }; 453 454 struct be_cmd_bhs { 455 struct iscsi_scsi_req iscsi_hdr; 456 unsigned char pad1[16]; 457 struct pdu_data_out iscsi_data_pdu; 458 unsigned char pad2[BE_SENSE_INFO_SIZE - 459 sizeof(struct pdu_data_out)]; 460 }; 461 462 struct beiscsi_io_task { 463 struct wrb_handle *pwrb_handle; 464 struct sgl_handle *psgl_handle; 465 struct beiscsi_conn *conn; 466 struct scsi_cmnd *scsi_cmnd; 467 int num_sg; 468 struct hwi_wrb_context *pwrb_context; 469 itt_t libiscsi_itt; 470 struct be_cmd_bhs *cmd_bhs; 471 struct be_bus_address bhs_pa; 472 unsigned short bhs_len; 473 dma_addr_t mtask_addr; 474 uint32_t mtask_data_count; 475 uint8_t wrb_type; 476 }; 477 478 struct be_nonio_bhs { 479 struct iscsi_hdr iscsi_hdr; 480 unsigned char pad1[16]; 481 struct pdu_data_out iscsi_data_pdu; 482 unsigned char pad2[BE_SENSE_INFO_SIZE - 483 sizeof(struct pdu_data_out)]; 484 }; 485 486 struct be_status_bhs { 487 struct iscsi_scsi_req iscsi_hdr; 488 unsigned char pad1[16]; 489 /** 490 * The plus 2 below is to hold the sense info length that gets 491 * DMA'ed by RxULP 492 */ 493 unsigned char sense_info[BE_SENSE_INFO_SIZE]; 494 }; 495 496 struct iscsi_sge { 497 u32 dw[4]; 498 }; 499 500 /** 501 * Pseudo amap definition in which each bit of the actual structure is defined 502 * as a byte: used to calculate offset/shift/mask of each field 503 */ 504 struct amap_iscsi_sge { 505 u8 addr_hi[32]; 506 u8 addr_lo[32]; 507 u8 sge_offset[22]; /* DWORD 2 */ 508 u8 rsvd0[9]; /* DWORD 2 */ 509 u8 last_sge; /* DWORD 2 */ 510 u8 len[17]; /* DWORD 3 */ 511 u8 rsvd1[15]; /* DWORD 3 */ 512 }; 513 514 struct beiscsi_offload_params { 515 u32 dw[6]; 516 }; 517 518 #define OFFLD_PARAMS_ERL 0x00000003 519 #define OFFLD_PARAMS_DDE 0x00000004 520 #define OFFLD_PARAMS_HDE 0x00000008 521 #define OFFLD_PARAMS_IR2T 0x00000010 522 #define OFFLD_PARAMS_IMD 0x00000020 523 #define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040 524 #define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080 525 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00 526 527 /** 528 * Pseudo amap definition in which each bit of the actual structure is defined 529 * as a byte: used to calculate offset/shift/mask of each field 530 */ 531 struct amap_beiscsi_offload_params { 532 u8 max_burst_length[32]; 533 u8 max_send_data_segment_length[32]; 534 u8 first_burst_length[32]; 535 u8 erl[2]; 536 u8 dde[1]; 537 u8 hde[1]; 538 u8 ir2t[1]; 539 u8 imd[1]; 540 u8 data_seq_inorder[1]; 541 u8 pdu_seq_inorder[1]; 542 u8 max_r2t[16]; 543 u8 pad[8]; 544 u8 exp_statsn[32]; 545 u8 max_recv_data_segment_length[32]; 546 }; 547 548 struct hd_async_handle { 549 struct list_head link; 550 struct be_bus_address pa; 551 void *pbuffer; 552 u32 buffer_len; 553 u16 index; 554 u16 cri; 555 u8 is_header; 556 u8 is_final; 557 u8 in_use; 558 }; 559 560 #define BEISCSI_ASYNC_HDQ_SIZE(phba, ulp) \ 561 (BEISCSI_GET_CID_COUNT((phba), (ulp)) * 2) 562 563 /** 564 * This has list of async PDUs that are waiting to be processed. 565 * Buffers live in this list for a brief duration before they get 566 * processed and posted back to hardware. 567 * Note that we don't really need one cri_wait_queue per async_entry. 568 * We need one cri_wait_queue per CRI. Its easier to manage if this 569 * is tagged along with the async_entry. 570 */ 571 struct hd_async_entry { 572 struct cri_wait_queue { 573 unsigned short hdr_len; 574 unsigned int bytes_received; 575 unsigned int bytes_needed; 576 struct list_head list; 577 } wq; 578 /* handles posted to FW resides here */ 579 struct hd_async_handle *header; 580 struct hd_async_handle *data; 581 }; 582 583 struct hd_async_buf_context { 584 struct be_bus_address pa_base; 585 void *va_base; 586 void *ring_base; 587 struct hd_async_handle *handle_base; 588 u32 buffer_size; 589 u16 pi; 590 }; 591 592 /** 593 * hd_async_context is declared for each ULP supporting iSCSI function. 594 */ 595 struct hd_async_context { 596 struct hd_async_buf_context async_header; 597 struct hd_async_buf_context async_data; 598 u16 num_entries; 599 /** 600 * When unsol PDU is in, it needs to be chained till all the bytes are 601 * received and then processing is done. hd_async_entry is created 602 * based on the cid_count for each ULP. When unsol PDU comes in based 603 * on the conn_id it needs to be added to the correct async_entry wq. 604 * Below defined cid_to_async_cri_map is used to reterive the 605 * async_cri_map for a particular connection. 606 * 607 * This array is initialized after beiscsi_create_wrb_rings returns. 608 * 609 * - this method takes more memory space, fixed to 2K 610 * - any support for connections greater than this the array size needs 611 * to be incremented 612 */ 613 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid]) 614 unsigned short cid_to_async_cri_map[BE_MAX_SESSION]; 615 /** 616 * This is a variable size array. Don`t add anything after this field!! 617 */ 618 struct hd_async_entry *async_entry; 619 }; 620 621 struct i_t_dpdu_cqe { 622 u32 dw[4]; 623 } __packed; 624 625 /** 626 * Pseudo amap definition in which each bit of the actual structure is defined 627 * as a byte: used to calculate offset/shift/mask of each field 628 */ 629 struct amap_i_t_dpdu_cqe { 630 u8 db_addr_hi[32]; 631 u8 db_addr_lo[32]; 632 u8 code[6]; 633 u8 cid[10]; 634 u8 dpl[16]; 635 u8 index[16]; 636 u8 num_cons[10]; 637 u8 rsvd0[4]; 638 u8 final; 639 u8 valid; 640 } __packed; 641 642 struct amap_i_t_dpdu_cqe_v2 { 643 u8 db_addr_hi[32]; /* DWORD 0 */ 644 u8 db_addr_lo[32]; /* DWORD 1 */ 645 u8 code[6]; /* DWORD 2 */ 646 u8 num_cons; /* DWORD 2*/ 647 u8 rsvd0[8]; /* DWORD 2 */ 648 u8 dpl[17]; /* DWORD 2 */ 649 u8 index[16]; /* DWORD 3 */ 650 u8 cid[13]; /* DWORD 3 */ 651 u8 rsvd1; /* DWORD 3 */ 652 u8 final; /* DWORD 3 */ 653 u8 valid; /* DWORD 3 */ 654 } __packed; 655 656 #define CQE_VALID_MASK 0x80000000 657 #define CQE_CODE_MASK 0x0000003F 658 #define CQE_CID_MASK 0x0000FFC0 659 660 #define EQE_VALID_MASK 0x00000001 661 #define EQE_MAJORCODE_MASK 0x0000000E 662 #define EQE_RESID_MASK 0xFFFF0000 663 664 struct be_eq_entry { 665 u32 dw[1]; 666 } __packed; 667 668 /** 669 * Pseudo amap definition in which each bit of the actual structure is defined 670 * as a byte: used to calculate offset/shift/mask of each field 671 */ 672 struct amap_eq_entry { 673 u8 valid; /* DWORD 0 */ 674 u8 major_code[3]; /* DWORD 0 */ 675 u8 minor_code[12]; /* DWORD 0 */ 676 u8 resource_id[16]; /* DWORD 0 */ 677 678 } __packed; 679 680 struct cq_db { 681 u32 dw[1]; 682 } __packed; 683 684 /** 685 * Pseudo amap definition in which each bit of the actual structure is defined 686 * as a byte: used to calculate offset/shift/mask of each field 687 */ 688 struct amap_cq_db { 689 u8 qid[10]; 690 u8 event[1]; 691 u8 rsvd0[5]; 692 u8 num_popped[13]; 693 u8 rearm[1]; 694 u8 rsvd1[2]; 695 } __packed; 696 697 void beiscsi_process_eq(struct beiscsi_hba *phba); 698 699 struct iscsi_wrb { 700 u32 dw[16]; 701 } __packed; 702 703 #define WRB_TYPE_MASK 0xF0000000 704 #define SKH_WRB_TYPE_OFFSET 27 705 #define BE_WRB_TYPE_OFFSET 28 706 707 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \ 708 (pwrb->dw[0] |= (wrb_type << type_offset)) 709 710 /** 711 * Pseudo amap definition in which each bit of the actual structure is defined 712 * as a byte: used to calculate offset/shift/mask of each field 713 */ 714 struct amap_iscsi_wrb { 715 u8 lun[14]; /* DWORD 0 */ 716 u8 lt; /* DWORD 0 */ 717 u8 invld; /* DWORD 0 */ 718 u8 wrb_idx[8]; /* DWORD 0 */ 719 u8 dsp; /* DWORD 0 */ 720 u8 dmsg; /* DWORD 0 */ 721 u8 undr_run; /* DWORD 0 */ 722 u8 over_run; /* DWORD 0 */ 723 u8 type[4]; /* DWORD 0 */ 724 u8 ptr2nextwrb[8]; /* DWORD 1 */ 725 u8 r2t_exp_dtl[24]; /* DWORD 1 */ 726 u8 sgl_icd_idx[12]; /* DWORD 2 */ 727 u8 rsvd0[20]; /* DWORD 2 */ 728 u8 exp_data_sn[32]; /* DWORD 3 */ 729 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */ 730 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */ 731 u8 cmdsn_itt[32]; /* DWORD 6 */ 732 u8 dif_ref_tag[32]; /* DWORD 7 */ 733 u8 sge0_addr_hi[32]; /* DWORD 8 */ 734 u8 sge0_addr_lo[32]; /* DWORD 9 */ 735 u8 sge0_offset[22]; /* DWORD 10 */ 736 u8 pbs; /* DWORD 10 */ 737 u8 dif_mode[2]; /* DWORD 10 */ 738 u8 rsvd1[6]; /* DWORD 10 */ 739 u8 sge0_last; /* DWORD 10 */ 740 u8 sge0_len[17]; /* DWORD 11 */ 741 u8 dif_meta_tag[14]; /* DWORD 11 */ 742 u8 sge0_in_ddr; /* DWORD 11 */ 743 u8 sge1_addr_hi[32]; /* DWORD 12 */ 744 u8 sge1_addr_lo[32]; /* DWORD 13 */ 745 u8 sge1_r2t_offset[22]; /* DWORD 14 */ 746 u8 rsvd2[9]; /* DWORD 14 */ 747 u8 sge1_last; /* DWORD 14 */ 748 u8 sge1_len[17]; /* DWORD 15 */ 749 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */ 750 u8 rsvd3[2]; /* DWORD 15 */ 751 u8 sge1_in_ddr; /* DWORD 15 */ 752 753 } __packed; 754 755 struct amap_iscsi_wrb_v2 { 756 u8 r2t_exp_dtl[25]; /* DWORD 0 */ 757 u8 rsvd0[2]; /* DWORD 0*/ 758 u8 type[5]; /* DWORD 0 */ 759 u8 ptr2nextwrb[8]; /* DWORD 1 */ 760 u8 wrb_idx[8]; /* DWORD 1 */ 761 u8 lun[16]; /* DWORD 1 */ 762 u8 sgl_idx[16]; /* DWORD 2 */ 763 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */ 764 u8 exp_data_sn[32]; /* DWORD 3 */ 765 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */ 766 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */ 767 u8 cq_id[16]; /* DWORD 6 */ 768 u8 rsvd1[16]; /* DWORD 6 */ 769 u8 cmdsn_itt[32]; /* DWORD 7 */ 770 u8 sge0_addr_hi[32]; /* DWORD 8 */ 771 u8 sge0_addr_lo[32]; /* DWORD 9 */ 772 u8 sge0_offset[24]; /* DWORD 10 */ 773 u8 rsvd2[7]; /* DWORD 10 */ 774 u8 sge0_last; /* DWORD 10 */ 775 u8 sge0_len[17]; /* DWORD 11 */ 776 u8 rsvd3[7]; /* DWORD 11 */ 777 u8 diff_enbl; /* DWORD 11 */ 778 u8 u_run; /* DWORD 11 */ 779 u8 o_run; /* DWORD 11 */ 780 u8 invld; /* DWORD 11 */ 781 u8 dsp; /* DWORD 11 */ 782 u8 dmsg; /* DWORD 11 */ 783 u8 rsvd4; /* DWORD 11 */ 784 u8 lt; /* DWORD 11 */ 785 u8 sge1_addr_hi[32]; /* DWORD 12 */ 786 u8 sge1_addr_lo[32]; /* DWORD 13 */ 787 u8 sge1_r2t_offset[24]; /* DWORD 14 */ 788 u8 rsvd5[7]; /* DWORD 14 */ 789 u8 sge1_last; /* DWORD 14 */ 790 u8 sge1_len[17]; /* DWORD 15 */ 791 u8 rsvd6[15]; /* DWORD 15 */ 792 } __packed; 793 794 795 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid, 796 struct hwi_wrb_context **pcontext); 797 void 798 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle); 799 800 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, 801 struct iscsi_task *task); 802 803 void hwi_ring_cq_db(struct beiscsi_hba *phba, 804 unsigned int id, unsigned int num_processed, 805 unsigned char rearm); 806 807 unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget); 808 void beiscsi_process_mcc_cq(struct beiscsi_hba *phba); 809 810 struct pdu_nop_out { 811 u32 dw[12]; 812 }; 813 814 /** 815 * Pseudo amap definition in which each bit of the actual structure is defined 816 * as a byte: used to calculate offset/shift/mask of each field 817 */ 818 struct amap_pdu_nop_out { 819 u8 opcode[6]; /* opcode 0x00 */ 820 u8 i_bit; /* I Bit */ 821 u8 x_bit; /* reserved; should be 0 */ 822 u8 fp_bit_filler1[7]; 823 u8 f_bit; /* always 1 */ 824 u8 reserved1[16]; 825 u8 ahs_length[8]; /* no AHS */ 826 u8 data_len_hi[8]; 827 u8 data_len_lo[16]; /* DataSegmentLength */ 828 u8 lun[64]; 829 u8 itt[32]; /* initiator id for ping or 0xffffffff */ 830 u8 ttt[32]; /* target id for ping or 0xffffffff */ 831 u8 cmd_sn[32]; 832 u8 exp_stat_sn[32]; 833 u8 reserved5[128]; 834 }; 835 836 #define PDUBASE_OPCODE_MASK 0x0000003F 837 #define PDUBASE_DATALENHI_MASK 0x0000FF00 838 #define PDUBASE_DATALENLO_MASK 0xFFFF0000 839 840 struct pdu_base { 841 u32 dw[16]; 842 } __packed; 843 844 /** 845 * Pseudo amap definition in which each bit of the actual structure is defined 846 * as a byte: used to calculate offset/shift/mask of each field 847 */ 848 struct amap_pdu_base { 849 u8 opcode[6]; 850 u8 i_bit; /* immediate bit */ 851 u8 x_bit; /* reserved, always 0 */ 852 u8 reserved1[24]; /* opcode-specific fields */ 853 u8 ahs_length[8]; /* length units is 4 byte words */ 854 u8 data_len_hi[8]; 855 u8 data_len_lo[16]; /* DatasegmentLength */ 856 u8 lun[64]; /* lun or opcode-specific fields */ 857 u8 itt[32]; /* initiator task tag */ 858 u8 reserved4[224]; 859 }; 860 861 struct iscsi_target_context_update_wrb { 862 u32 dw[16]; 863 } __packed; 864 865 /** 866 * Pseudo amap definition in which each bit of the actual structure is defined 867 * as a byte: used to calculate offset/shift/mask of each field 868 */ 869 #define BE_TGT_CTX_UPDT_CMD 0x07 870 struct amap_iscsi_target_context_update_wrb { 871 u8 lun[14]; /* DWORD 0 */ 872 u8 lt; /* DWORD 0 */ 873 u8 invld; /* DWORD 0 */ 874 u8 wrb_idx[8]; /* DWORD 0 */ 875 u8 dsp; /* DWORD 0 */ 876 u8 dmsg; /* DWORD 0 */ 877 u8 undr_run; /* DWORD 0 */ 878 u8 over_run; /* DWORD 0 */ 879 u8 type[4]; /* DWORD 0 */ 880 u8 ptr2nextwrb[8]; /* DWORD 1 */ 881 u8 max_burst_length[19]; /* DWORD 1 */ 882 u8 rsvd0[5]; /* DWORD 1 */ 883 u8 rsvd1[15]; /* DWORD 2 */ 884 u8 max_send_data_segment_length[17]; /* DWORD 2 */ 885 u8 first_burst_length[14]; /* DWORD 3 */ 886 u8 rsvd2[2]; /* DWORD 3 */ 887 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */ 888 u8 rsvd3[5]; /* DWORD 3 */ 889 u8 session_state[3]; /* DWORD 3 */ 890 u8 rsvd4[16]; /* DWORD 4 */ 891 u8 tx_jumbo; /* DWORD 4 */ 892 u8 hde; /* DWORD 4 */ 893 u8 dde; /* DWORD 4 */ 894 u8 erl[2]; /* DWORD 4 */ 895 u8 domain_id[5]; /* DWORD 4 */ 896 u8 mode; /* DWORD 4 */ 897 u8 imd; /* DWORD 4 */ 898 u8 ir2t; /* DWORD 4 */ 899 u8 notpredblq[2]; /* DWORD 4 */ 900 u8 compltonack; /* DWORD 4 */ 901 u8 stat_sn[32]; /* DWORD 5 */ 902 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */ 903 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */ 904 u8 pad_addr_hi[32]; /* DWORD 8 */ 905 u8 pad_addr_lo[32]; /* DWORD 9 */ 906 u8 rsvd5[32]; /* DWORD 10 */ 907 u8 rsvd6[32]; /* DWORD 11 */ 908 u8 rsvd7[32]; /* DWORD 12 */ 909 u8 rsvd8[32]; /* DWORD 13 */ 910 u8 rsvd9[32]; /* DWORD 14 */ 911 u8 rsvd10[32]; /* DWORD 15 */ 912 913 } __packed; 914 915 #define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024) 916 #define BEISCSI_MAX_CXNS 1 917 struct amap_iscsi_target_context_update_wrb_v2 { 918 u8 max_burst_length[24]; /* DWORD 0 */ 919 u8 rsvd0[3]; /* DWORD 0 */ 920 u8 type[5]; /* DWORD 0 */ 921 u8 ptr2nextwrb[8]; /* DWORD 1 */ 922 u8 wrb_idx[8]; /* DWORD 1 */ 923 u8 rsvd1[16]; /* DWORD 1 */ 924 u8 max_send_data_segment_length[24]; /* DWORD 2 */ 925 u8 rsvd2[8]; /* DWORD 2 */ 926 u8 first_burst_length[24]; /* DWORD 3 */ 927 u8 rsvd3[8]; /* DOWRD 3 */ 928 u8 max_r2t[16]; /* DWORD 4 */ 929 u8 rsvd4; /* DWORD 4 */ 930 u8 hde; /* DWORD 4 */ 931 u8 dde; /* DWORD 4 */ 932 u8 erl[2]; /* DWORD 4 */ 933 u8 rsvd5[6]; /* DWORD 4 */ 934 u8 imd; /* DWORD 4 */ 935 u8 ir2t; /* DWORD 4 */ 936 u8 rsvd6[3]; /* DWORD 4 */ 937 u8 stat_sn[32]; /* DWORD 5 */ 938 u8 rsvd7[32]; /* DWORD 6 */ 939 u8 rsvd8[32]; /* DWORD 7 */ 940 u8 max_recv_dataseg_len[24]; /* DWORD 8 */ 941 u8 rsvd9[8]; /* DWORD 8 */ 942 u8 rsvd10[32]; /* DWORD 9 */ 943 u8 rsvd11[32]; /* DWORD 10 */ 944 u8 max_cxns[16]; /* DWORD 11 */ 945 u8 rsvd12[11]; /* DWORD 11*/ 946 u8 invld; /* DWORD 11 */ 947 u8 rsvd13;/* DWORD 11*/ 948 u8 dmsg; /* DWORD 11 */ 949 u8 data_seq_inorder; /* DWORD 11 */ 950 u8 pdu_seq_inorder; /* DWORD 11 */ 951 u8 rsvd14[32]; /*DWORD 12 */ 952 u8 rsvd15[32]; /* DWORD 13 */ 953 u8 rsvd16[32]; /* DWORD 14 */ 954 u8 rsvd17[32]; /* DWORD 15 */ 955 } __packed; 956 957 958 struct be_ring { 959 u32 pages; /* queue size in pages */ 960 u32 id; /* queue id assigned by beklib */ 961 u32 num; /* number of elements in queue */ 962 u32 cidx; /* consumer index */ 963 u32 pidx; /* producer index -- not used by most rings */ 964 u32 item_size; /* size in bytes of one object */ 965 u8 ulp_num; /* ULP to which CID binded */ 966 u16 register_set; 967 u16 doorbell_format; 968 u32 doorbell_offset; 969 970 void *va; /* The virtual address of the ring. This 971 * should be last to allow 32 & 64 bit debugger 972 * extensions to work. 973 */ 974 }; 975 976 struct hwi_controller { 977 struct hwi_wrb_context *wrb_context; 978 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT]; 979 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT]; 980 struct hwi_context_memory *phwi_ctxt; 981 }; 982 983 enum hwh_type_enum { 984 HWH_TYPE_IO = 1, 985 HWH_TYPE_LOGOUT = 2, 986 HWH_TYPE_TMF = 3, 987 HWH_TYPE_NOP = 4, 988 HWH_TYPE_IO_RD = 5, 989 HWH_TYPE_LOGIN = 11, 990 HWH_TYPE_INVALID = 0xFFFFFFFF 991 }; 992 993 struct wrb_handle { 994 unsigned short wrb_index; 995 struct iscsi_task *pio_handle; 996 struct iscsi_wrb *pwrb; 997 }; 998 999 struct hwi_context_memory { 1000 struct be_eq_obj be_eq[MAX_CPUS]; 1001 struct be_queue_info be_cq[MAX_CPUS - 1]; 1002 1003 struct be_queue_info *be_wrbq; 1004 /** 1005 * Create array of ULP number for below entries as DEFQ 1006 * will be created for both ULP if iSCSI Protocol is 1007 * loaded on both ULP. 1008 */ 1009 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT]; 1010 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT]; 1011 struct hd_async_context *pasync_ctx[BEISCSI_ULP_COUNT]; 1012 }; 1013 1014 void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle); 1015 1016 /* Logging related definitions */ 1017 #define BEISCSI_LOG_INIT 0x0001 /* Initialization events */ 1018 #define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */ 1019 #define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */ 1020 #define BEISCSI_LOG_EH 0x0008 /* Error Handler */ 1021 #define BEISCSI_LOG_IO 0x0010 /* IO Code Path */ 1022 #define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */ 1023 #define BEISCSI_LOG_ISCSI 0x0040 /* SCSI/iSCSI Protocol related Logs */ 1024 1025 #define __beiscsi_log(phba, level, fmt, arg...) \ 1026 shost_printk(level, phba->shost, fmt, __LINE__, ##arg) 1027 1028 #define beiscsi_log(phba, level, mask, fmt, arg...) \ 1029 do { \ 1030 uint32_t log_value = phba->attr_log_enable; \ 1031 if (((mask) & log_value) || (level[1] <= '3')) \ 1032 __beiscsi_log(phba, level, fmt, ##arg); \ 1033 } while (0); 1034 1035 #endif 1036