1 /** 2 * Copyright (C) 2005 - 2013 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com) 11 * 12 * Contact Information: 13 * linux-drivers@emulex.com 14 * 15 * Emulex 16 * 3333 Susan Street 17 * Costa Mesa, CA 92626 18 */ 19 20 #include <linux/reboot.h> 21 #include <linux/delay.h> 22 #include <linux/slab.h> 23 #include <linux/interrupt.h> 24 #include <linux/blkdev.h> 25 #include <linux/pci.h> 26 #include <linux/string.h> 27 #include <linux/kernel.h> 28 #include <linux/semaphore.h> 29 #include <linux/iscsi_boot_sysfs.h> 30 #include <linux/module.h> 31 #include <linux/bsg-lib.h> 32 33 #include <scsi/libiscsi.h> 34 #include <scsi/scsi_bsg_iscsi.h> 35 #include <scsi/scsi_netlink.h> 36 #include <scsi/scsi_transport_iscsi.h> 37 #include <scsi/scsi_transport.h> 38 #include <scsi/scsi_cmnd.h> 39 #include <scsi/scsi_device.h> 40 #include <scsi/scsi_host.h> 41 #include <scsi/scsi.h> 42 #include "be_main.h" 43 #include "be_iscsi.h" 44 #include "be_mgmt.h" 45 #include "be_cmds.h" 46 47 static unsigned int be_iopoll_budget = 10; 48 static unsigned int be_max_phys_size = 64; 49 static unsigned int enable_msix = 1; 50 51 MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table); 52 MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR); 53 MODULE_VERSION(BUILD_STR); 54 MODULE_AUTHOR("Emulex Corporation"); 55 MODULE_LICENSE("GPL"); 56 module_param(be_iopoll_budget, int, 0); 57 module_param(enable_msix, int, 0); 58 module_param(be_max_phys_size, uint, S_IRUGO); 59 MODULE_PARM_DESC(be_max_phys_size, 60 "Maximum Size (In Kilobytes) of physically contiguous " 61 "memory that can be allocated. Range is 16 - 128"); 62 63 #define beiscsi_disp_param(_name)\ 64 ssize_t \ 65 beiscsi_##_name##_disp(struct device *dev,\ 66 struct device_attribute *attrib, char *buf) \ 67 { \ 68 struct Scsi_Host *shost = class_to_shost(dev);\ 69 struct beiscsi_hba *phba = iscsi_host_priv(shost); \ 70 uint32_t param_val = 0; \ 71 param_val = phba->attr_##_name;\ 72 return snprintf(buf, PAGE_SIZE, "%d\n",\ 73 phba->attr_##_name);\ 74 } 75 76 #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\ 77 int \ 78 beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\ 79 {\ 80 if (val >= _minval && val <= _maxval) {\ 81 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\ 82 "BA_%d : beiscsi_"#_name" updated "\ 83 "from 0x%x ==> 0x%x\n",\ 84 phba->attr_##_name, val); \ 85 phba->attr_##_name = val;\ 86 return 0;\ 87 } \ 88 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \ 89 "BA_%d beiscsi_"#_name" attribute "\ 90 "cannot be updated to 0x%x, "\ 91 "range allowed is ["#_minval" - "#_maxval"]\n", val);\ 92 return -EINVAL;\ 93 } 94 95 #define beiscsi_store_param(_name) \ 96 ssize_t \ 97 beiscsi_##_name##_store(struct device *dev,\ 98 struct device_attribute *attr, const char *buf,\ 99 size_t count) \ 100 { \ 101 struct Scsi_Host *shost = class_to_shost(dev);\ 102 struct beiscsi_hba *phba = iscsi_host_priv(shost);\ 103 uint32_t param_val = 0;\ 104 if (!isdigit(buf[0]))\ 105 return -EINVAL;\ 106 if (sscanf(buf, "%i", ¶m_val) != 1)\ 107 return -EINVAL;\ 108 if (beiscsi_##_name##_change(phba, param_val) == 0) \ 109 return strlen(buf);\ 110 else \ 111 return -EINVAL;\ 112 } 113 114 #define beiscsi_init_param(_name, _minval, _maxval, _defval) \ 115 int \ 116 beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \ 117 { \ 118 if (val >= _minval && val <= _maxval) {\ 119 phba->attr_##_name = val;\ 120 return 0;\ 121 } \ 122 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\ 123 "BA_%d beiscsi_"#_name" attribute " \ 124 "cannot be updated to 0x%x, "\ 125 "range allowed is ["#_minval" - "#_maxval"]\n", val);\ 126 phba->attr_##_name = _defval;\ 127 return -EINVAL;\ 128 } 129 130 #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \ 131 static uint beiscsi_##_name = _defval;\ 132 module_param(beiscsi_##_name, uint, S_IRUGO);\ 133 MODULE_PARM_DESC(beiscsi_##_name, _descp);\ 134 beiscsi_disp_param(_name)\ 135 beiscsi_change_param(_name, _minval, _maxval, _defval)\ 136 beiscsi_store_param(_name)\ 137 beiscsi_init_param(_name, _minval, _maxval, _defval)\ 138 DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\ 139 beiscsi_##_name##_disp, beiscsi_##_name##_store) 140 141 /* 142 * When new log level added update the 143 * the MAX allowed value for log_enable 144 */ 145 BEISCSI_RW_ATTR(log_enable, 0x00, 146 0xFF, 0x00, "Enable logging Bit Mask\n" 147 "\t\t\t\tInitialization Events : 0x01\n" 148 "\t\t\t\tMailbox Events : 0x02\n" 149 "\t\t\t\tMiscellaneous Events : 0x04\n" 150 "\t\t\t\tError Handling : 0x08\n" 151 "\t\t\t\tIO Path Events : 0x10\n" 152 "\t\t\t\tConfiguration Path : 0x20\n" 153 "\t\t\t\tiSCSI Protocol : 0x40\n"); 154 155 DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL); 156 DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL); 157 DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL); 158 DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL); 159 DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO, 160 beiscsi_active_session_disp, NULL); 161 DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO, 162 beiscsi_free_session_disp, NULL); 163 struct device_attribute *beiscsi_attrs[] = { 164 &dev_attr_beiscsi_log_enable, 165 &dev_attr_beiscsi_drvr_ver, 166 &dev_attr_beiscsi_adapter_family, 167 &dev_attr_beiscsi_fw_ver, 168 &dev_attr_beiscsi_active_session_count, 169 &dev_attr_beiscsi_free_session_count, 170 &dev_attr_beiscsi_phys_port, 171 NULL, 172 }; 173 174 static char const *cqe_desc[] = { 175 "RESERVED_DESC", 176 "SOL_CMD_COMPLETE", 177 "SOL_CMD_KILLED_DATA_DIGEST_ERR", 178 "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL", 179 "CXN_KILLED_BURST_LEN_MISMATCH", 180 "CXN_KILLED_AHS_RCVD", 181 "CXN_KILLED_HDR_DIGEST_ERR", 182 "CXN_KILLED_UNKNOWN_HDR", 183 "CXN_KILLED_STALE_ITT_TTT_RCVD", 184 "CXN_KILLED_INVALID_ITT_TTT_RCVD", 185 "CXN_KILLED_RST_RCVD", 186 "CXN_KILLED_TIMED_OUT", 187 "CXN_KILLED_RST_SENT", 188 "CXN_KILLED_FIN_RCVD", 189 "CXN_KILLED_BAD_UNSOL_PDU_RCVD", 190 "CXN_KILLED_BAD_WRB_INDEX_ERROR", 191 "CXN_KILLED_OVER_RUN_RESIDUAL", 192 "CXN_KILLED_UNDER_RUN_RESIDUAL", 193 "CMD_KILLED_INVALID_STATSN_RCVD", 194 "CMD_KILLED_INVALID_R2T_RCVD", 195 "CMD_CXN_KILLED_LUN_INVALID", 196 "CMD_CXN_KILLED_ICD_INVALID", 197 "CMD_CXN_KILLED_ITT_INVALID", 198 "CMD_CXN_KILLED_SEQ_OUTOFORDER", 199 "CMD_CXN_KILLED_INVALID_DATASN_RCVD", 200 "CXN_INVALIDATE_NOTIFY", 201 "CXN_INVALIDATE_INDEX_NOTIFY", 202 "CMD_INVALIDATED_NOTIFY", 203 "UNSOL_HDR_NOTIFY", 204 "UNSOL_DATA_NOTIFY", 205 "UNSOL_DATA_DIGEST_ERROR_NOTIFY", 206 "DRIVERMSG_NOTIFY", 207 "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN", 208 "SOL_CMD_KILLED_DIF_ERR", 209 "CXN_KILLED_SYN_RCVD", 210 "CXN_KILLED_IMM_DATA_RCVD" 211 }; 212 213 static int beiscsi_slave_configure(struct scsi_device *sdev) 214 { 215 blk_queue_max_segment_size(sdev->request_queue, 65536); 216 return 0; 217 } 218 219 static int beiscsi_eh_abort(struct scsi_cmnd *sc) 220 { 221 struct iscsi_cls_session *cls_session; 222 struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr; 223 struct beiscsi_io_task *aborted_io_task; 224 struct iscsi_conn *conn; 225 struct beiscsi_conn *beiscsi_conn; 226 struct beiscsi_hba *phba; 227 struct iscsi_session *session; 228 struct invalidate_command_table *inv_tbl; 229 struct be_dma_mem nonemb_cmd; 230 unsigned int cid, tag, num_invalidate; 231 int rc; 232 233 cls_session = starget_to_session(scsi_target(sc->device)); 234 session = cls_session->dd_data; 235 236 spin_lock_bh(&session->frwd_lock); 237 if (!aborted_task || !aborted_task->sc) { 238 /* we raced */ 239 spin_unlock_bh(&session->frwd_lock); 240 return SUCCESS; 241 } 242 243 aborted_io_task = aborted_task->dd_data; 244 if (!aborted_io_task->scsi_cmnd) { 245 /* raced or invalid command */ 246 spin_unlock_bh(&session->frwd_lock); 247 return SUCCESS; 248 } 249 spin_unlock_bh(&session->frwd_lock); 250 /* Invalidate WRB Posted for this Task */ 251 AMAP_SET_BITS(struct amap_iscsi_wrb, invld, 252 aborted_io_task->pwrb_handle->pwrb, 253 1); 254 255 conn = aborted_task->conn; 256 beiscsi_conn = conn->dd_data; 257 phba = beiscsi_conn->phba; 258 259 /* invalidate iocb */ 260 cid = beiscsi_conn->beiscsi_conn_cid; 261 inv_tbl = phba->inv_tbl; 262 memset(inv_tbl, 0x0, sizeof(*inv_tbl)); 263 inv_tbl->cid = cid; 264 inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index; 265 num_invalidate = 1; 266 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, 267 sizeof(struct invalidate_commands_params_in), 268 &nonemb_cmd.dma); 269 if (nonemb_cmd.va == NULL) { 270 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH, 271 "BM_%d : Failed to allocate memory for" 272 "mgmt_invalidate_icds\n"); 273 return FAILED; 274 } 275 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in); 276 277 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, 278 cid, &nonemb_cmd); 279 if (!tag) { 280 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH, 281 "BM_%d : mgmt_invalidate_icds could not be" 282 "submitted\n"); 283 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 284 nonemb_cmd.va, nonemb_cmd.dma); 285 286 return FAILED; 287 } 288 289 rc = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd); 290 if (rc != -EBUSY) 291 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 292 nonemb_cmd.va, nonemb_cmd.dma); 293 294 return iscsi_eh_abort(sc); 295 } 296 297 static int beiscsi_eh_device_reset(struct scsi_cmnd *sc) 298 { 299 struct iscsi_task *abrt_task; 300 struct beiscsi_io_task *abrt_io_task; 301 struct iscsi_conn *conn; 302 struct beiscsi_conn *beiscsi_conn; 303 struct beiscsi_hba *phba; 304 struct iscsi_session *session; 305 struct iscsi_cls_session *cls_session; 306 struct invalidate_command_table *inv_tbl; 307 struct be_dma_mem nonemb_cmd; 308 unsigned int cid, tag, i, num_invalidate; 309 int rc; 310 311 /* invalidate iocbs */ 312 cls_session = starget_to_session(scsi_target(sc->device)); 313 session = cls_session->dd_data; 314 spin_lock_bh(&session->frwd_lock); 315 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) { 316 spin_unlock_bh(&session->frwd_lock); 317 return FAILED; 318 } 319 conn = session->leadconn; 320 beiscsi_conn = conn->dd_data; 321 phba = beiscsi_conn->phba; 322 cid = beiscsi_conn->beiscsi_conn_cid; 323 inv_tbl = phba->inv_tbl; 324 memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN); 325 num_invalidate = 0; 326 for (i = 0; i < conn->session->cmds_max; i++) { 327 abrt_task = conn->session->cmds[i]; 328 abrt_io_task = abrt_task->dd_data; 329 if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE) 330 continue; 331 332 if (sc->device->lun != abrt_task->sc->device->lun) 333 continue; 334 335 /* Invalidate WRB Posted for this Task */ 336 AMAP_SET_BITS(struct amap_iscsi_wrb, invld, 337 abrt_io_task->pwrb_handle->pwrb, 338 1); 339 340 inv_tbl->cid = cid; 341 inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index; 342 num_invalidate++; 343 inv_tbl++; 344 } 345 spin_unlock_bh(&session->frwd_lock); 346 inv_tbl = phba->inv_tbl; 347 348 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, 349 sizeof(struct invalidate_commands_params_in), 350 &nonemb_cmd.dma); 351 if (nonemb_cmd.va == NULL) { 352 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH, 353 "BM_%d : Failed to allocate memory for" 354 "mgmt_invalidate_icds\n"); 355 return FAILED; 356 } 357 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in); 358 memset(nonemb_cmd.va, 0, nonemb_cmd.size); 359 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, 360 cid, &nonemb_cmd); 361 if (!tag) { 362 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH, 363 "BM_%d : mgmt_invalidate_icds could not be" 364 " submitted\n"); 365 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 366 nonemb_cmd.va, nonemb_cmd.dma); 367 return FAILED; 368 } 369 370 rc = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd); 371 if (rc != -EBUSY) 372 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 373 nonemb_cmd.va, nonemb_cmd.dma); 374 return iscsi_eh_device_reset(sc); 375 } 376 377 static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf) 378 { 379 struct beiscsi_hba *phba = data; 380 struct mgmt_session_info *boot_sess = &phba->boot_sess; 381 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0]; 382 char *str = buf; 383 int rc; 384 385 switch (type) { 386 case ISCSI_BOOT_TGT_NAME: 387 rc = sprintf(buf, "%.*s\n", 388 (int)strlen(boot_sess->target_name), 389 (char *)&boot_sess->target_name); 390 break; 391 case ISCSI_BOOT_TGT_IP_ADDR: 392 if (boot_conn->dest_ipaddr.ip_type == 0x1) 393 rc = sprintf(buf, "%pI4\n", 394 (char *)&boot_conn->dest_ipaddr.addr); 395 else 396 rc = sprintf(str, "%pI6\n", 397 (char *)&boot_conn->dest_ipaddr.addr); 398 break; 399 case ISCSI_BOOT_TGT_PORT: 400 rc = sprintf(str, "%d\n", boot_conn->dest_port); 401 break; 402 403 case ISCSI_BOOT_TGT_CHAP_NAME: 404 rc = sprintf(str, "%.*s\n", 405 boot_conn->negotiated_login_options.auth_data.chap. 406 target_chap_name_length, 407 (char *)&boot_conn->negotiated_login_options. 408 auth_data.chap.target_chap_name); 409 break; 410 case ISCSI_BOOT_TGT_CHAP_SECRET: 411 rc = sprintf(str, "%.*s\n", 412 boot_conn->negotiated_login_options.auth_data.chap. 413 target_secret_length, 414 (char *)&boot_conn->negotiated_login_options. 415 auth_data.chap.target_secret); 416 break; 417 case ISCSI_BOOT_TGT_REV_CHAP_NAME: 418 rc = sprintf(str, "%.*s\n", 419 boot_conn->negotiated_login_options.auth_data.chap. 420 intr_chap_name_length, 421 (char *)&boot_conn->negotiated_login_options. 422 auth_data.chap.intr_chap_name); 423 break; 424 case ISCSI_BOOT_TGT_REV_CHAP_SECRET: 425 rc = sprintf(str, "%.*s\n", 426 boot_conn->negotiated_login_options.auth_data.chap. 427 intr_secret_length, 428 (char *)&boot_conn->negotiated_login_options. 429 auth_data.chap.intr_secret); 430 break; 431 case ISCSI_BOOT_TGT_FLAGS: 432 rc = sprintf(str, "2\n"); 433 break; 434 case ISCSI_BOOT_TGT_NIC_ASSOC: 435 rc = sprintf(str, "0\n"); 436 break; 437 default: 438 rc = -ENOSYS; 439 break; 440 } 441 return rc; 442 } 443 444 static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf) 445 { 446 struct beiscsi_hba *phba = data; 447 char *str = buf; 448 int rc; 449 450 switch (type) { 451 case ISCSI_BOOT_INI_INITIATOR_NAME: 452 rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname); 453 break; 454 default: 455 rc = -ENOSYS; 456 break; 457 } 458 return rc; 459 } 460 461 static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf) 462 { 463 struct beiscsi_hba *phba = data; 464 char *str = buf; 465 int rc; 466 467 switch (type) { 468 case ISCSI_BOOT_ETH_FLAGS: 469 rc = sprintf(str, "2\n"); 470 break; 471 case ISCSI_BOOT_ETH_INDEX: 472 rc = sprintf(str, "0\n"); 473 break; 474 case ISCSI_BOOT_ETH_MAC: 475 rc = beiscsi_get_macaddr(str, phba); 476 break; 477 default: 478 rc = -ENOSYS; 479 break; 480 } 481 return rc; 482 } 483 484 485 static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type) 486 { 487 umode_t rc; 488 489 switch (type) { 490 case ISCSI_BOOT_TGT_NAME: 491 case ISCSI_BOOT_TGT_IP_ADDR: 492 case ISCSI_BOOT_TGT_PORT: 493 case ISCSI_BOOT_TGT_CHAP_NAME: 494 case ISCSI_BOOT_TGT_CHAP_SECRET: 495 case ISCSI_BOOT_TGT_REV_CHAP_NAME: 496 case ISCSI_BOOT_TGT_REV_CHAP_SECRET: 497 case ISCSI_BOOT_TGT_NIC_ASSOC: 498 case ISCSI_BOOT_TGT_FLAGS: 499 rc = S_IRUGO; 500 break; 501 default: 502 rc = 0; 503 break; 504 } 505 return rc; 506 } 507 508 static umode_t beiscsi_ini_get_attr_visibility(void *data, int type) 509 { 510 umode_t rc; 511 512 switch (type) { 513 case ISCSI_BOOT_INI_INITIATOR_NAME: 514 rc = S_IRUGO; 515 break; 516 default: 517 rc = 0; 518 break; 519 } 520 return rc; 521 } 522 523 524 static umode_t beiscsi_eth_get_attr_visibility(void *data, int type) 525 { 526 umode_t rc; 527 528 switch (type) { 529 case ISCSI_BOOT_ETH_FLAGS: 530 case ISCSI_BOOT_ETH_MAC: 531 case ISCSI_BOOT_ETH_INDEX: 532 rc = S_IRUGO; 533 break; 534 default: 535 rc = 0; 536 break; 537 } 538 return rc; 539 } 540 541 /*------------------- PCI Driver operations and data ----------------- */ 542 static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = { 543 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) }, 544 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) }, 545 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) }, 546 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) }, 547 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) }, 548 { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) }, 549 { 0 } 550 }; 551 MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table); 552 553 554 static struct scsi_host_template beiscsi_sht = { 555 .module = THIS_MODULE, 556 .name = "Emulex 10Gbe open-iscsi Initiator Driver", 557 .proc_name = DRV_NAME, 558 .queuecommand = iscsi_queuecommand, 559 .change_queue_depth = iscsi_change_queue_depth, 560 .slave_configure = beiscsi_slave_configure, 561 .target_alloc = iscsi_target_alloc, 562 .eh_abort_handler = beiscsi_eh_abort, 563 .eh_device_reset_handler = beiscsi_eh_device_reset, 564 .eh_target_reset_handler = iscsi_eh_session_reset, 565 .shost_attrs = beiscsi_attrs, 566 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS, 567 .can_queue = BE2_IO_DEPTH, 568 .this_id = -1, 569 .max_sectors = BEISCSI_MAX_SECTORS, 570 .cmd_per_lun = BEISCSI_CMD_PER_LUN, 571 .use_clustering = ENABLE_CLUSTERING, 572 .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID, 573 574 }; 575 576 static struct scsi_transport_template *beiscsi_scsi_transport; 577 578 static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev) 579 { 580 struct beiscsi_hba *phba; 581 struct Scsi_Host *shost; 582 583 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0); 584 if (!shost) { 585 dev_err(&pcidev->dev, 586 "beiscsi_hba_alloc - iscsi_host_alloc failed\n"); 587 return NULL; 588 } 589 shost->dma_boundary = pcidev->dma_mask; 590 shost->max_id = BE2_MAX_SESSIONS; 591 shost->max_channel = 0; 592 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN; 593 shost->max_lun = BEISCSI_NUM_MAX_LUN; 594 shost->transportt = beiscsi_scsi_transport; 595 phba = iscsi_host_priv(shost); 596 memset(phba, 0, sizeof(*phba)); 597 phba->shost = shost; 598 phba->pcidev = pci_dev_get(pcidev); 599 pci_set_drvdata(pcidev, phba); 600 phba->interface_handle = 0xFFFFFFFF; 601 602 return phba; 603 } 604 605 static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba) 606 { 607 if (phba->csr_va) { 608 iounmap(phba->csr_va); 609 phba->csr_va = NULL; 610 } 611 if (phba->db_va) { 612 iounmap(phba->db_va); 613 phba->db_va = NULL; 614 } 615 if (phba->pci_va) { 616 iounmap(phba->pci_va); 617 phba->pci_va = NULL; 618 } 619 } 620 621 static int beiscsi_map_pci_bars(struct beiscsi_hba *phba, 622 struct pci_dev *pcidev) 623 { 624 u8 __iomem *addr; 625 int pcicfg_reg; 626 627 addr = ioremap_nocache(pci_resource_start(pcidev, 2), 628 pci_resource_len(pcidev, 2)); 629 if (addr == NULL) 630 return -ENOMEM; 631 phba->ctrl.csr = addr; 632 phba->csr_va = addr; 633 phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2); 634 635 addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024); 636 if (addr == NULL) 637 goto pci_map_err; 638 phba->ctrl.db = addr; 639 phba->db_va = addr; 640 phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4); 641 642 if (phba->generation == BE_GEN2) 643 pcicfg_reg = 1; 644 else 645 pcicfg_reg = 0; 646 647 addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg), 648 pci_resource_len(pcidev, pcicfg_reg)); 649 650 if (addr == NULL) 651 goto pci_map_err; 652 phba->ctrl.pcicfg = addr; 653 phba->pci_va = addr; 654 phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg); 655 return 0; 656 657 pci_map_err: 658 beiscsi_unmap_pci_function(phba); 659 return -ENOMEM; 660 } 661 662 static int beiscsi_enable_pci(struct pci_dev *pcidev) 663 { 664 int ret; 665 666 ret = pci_enable_device(pcidev); 667 if (ret) { 668 dev_err(&pcidev->dev, 669 "beiscsi_enable_pci - enable device failed\n"); 670 return ret; 671 } 672 673 pci_set_master(pcidev); 674 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64)); 675 if (ret) { 676 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)); 677 if (ret) { 678 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n"); 679 pci_disable_device(pcidev); 680 return ret; 681 } else { 682 ret = pci_set_consistent_dma_mask(pcidev, 683 DMA_BIT_MASK(32)); 684 } 685 } else { 686 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64)); 687 if (ret) { 688 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n"); 689 pci_disable_device(pcidev); 690 return ret; 691 } 692 } 693 return 0; 694 } 695 696 static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev) 697 { 698 struct be_ctrl_info *ctrl = &phba->ctrl; 699 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced; 700 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem; 701 int status = 0; 702 703 ctrl->pdev = pdev; 704 status = beiscsi_map_pci_bars(phba, pdev); 705 if (status) 706 return status; 707 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16; 708 mbox_mem_alloc->va = pci_alloc_consistent(pdev, 709 mbox_mem_alloc->size, 710 &mbox_mem_alloc->dma); 711 if (!mbox_mem_alloc->va) { 712 beiscsi_unmap_pci_function(phba); 713 return -ENOMEM; 714 } 715 716 mbox_mem_align->size = sizeof(struct be_mcc_mailbox); 717 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16); 718 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16); 719 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox)); 720 spin_lock_init(&ctrl->mbox_lock); 721 spin_lock_init(&phba->ctrl.mcc_lock); 722 spin_lock_init(&phba->ctrl.mcc_cq_lock); 723 724 return status; 725 } 726 727 /** 728 * beiscsi_get_params()- Set the config paramters 729 * @phba: ptr device priv structure 730 **/ 731 static void beiscsi_get_params(struct beiscsi_hba *phba) 732 { 733 uint32_t total_cid_count = 0; 734 uint32_t total_icd_count = 0; 735 uint8_t ulp_num = 0; 736 737 total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) + 738 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1); 739 740 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 741 uint32_t align_mask = 0; 742 uint32_t icd_post_per_page = 0; 743 uint32_t icd_count_unavailable = 0; 744 uint32_t icd_start = 0, icd_count = 0; 745 uint32_t icd_start_align = 0, icd_count_align = 0; 746 747 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 748 icd_start = phba->fw_config.iscsi_icd_start[ulp_num]; 749 icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; 750 751 /* Get ICD count that can be posted on each page */ 752 icd_post_per_page = (PAGE_SIZE / (BE2_SGE * 753 sizeof(struct iscsi_sge))); 754 align_mask = (icd_post_per_page - 1); 755 756 /* Check if icd_start is aligned ICD per page posting */ 757 if (icd_start % icd_post_per_page) { 758 icd_start_align = ((icd_start + 759 icd_post_per_page) & 760 ~(align_mask)); 761 phba->fw_config. 762 iscsi_icd_start[ulp_num] = 763 icd_start_align; 764 } 765 766 icd_count_align = (icd_count & ~align_mask); 767 768 /* ICD discarded in the process of alignment */ 769 if (icd_start_align) 770 icd_count_unavailable = ((icd_start_align - 771 icd_start) + 772 (icd_count - 773 icd_count_align)); 774 775 /* Updated ICD count available */ 776 phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count - 777 icd_count_unavailable); 778 779 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 780 "BM_%d : Aligned ICD values\n" 781 "\t ICD Start : %d\n" 782 "\t ICD Count : %d\n" 783 "\t ICD Discarded : %d\n", 784 phba->fw_config. 785 iscsi_icd_start[ulp_num], 786 phba->fw_config. 787 iscsi_icd_count[ulp_num], 788 icd_count_unavailable); 789 break; 790 } 791 } 792 793 total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; 794 phba->params.ios_per_ctrl = (total_icd_count - 795 (total_cid_count + 796 BE2_TMFS + BE2_NOPOUT_REQ)); 797 phba->params.cxns_per_ctrl = total_cid_count; 798 phba->params.asyncpdus_per_ctrl = total_cid_count; 799 phba->params.icds_per_ctrl = total_icd_count; 800 phba->params.num_sge_per_io = BE2_SGE; 801 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ; 802 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ; 803 phba->params.eq_timer = 64; 804 phba->params.num_eq_entries = 1024; 805 phba->params.num_cq_entries = 1024; 806 phba->params.wrbs_per_cxn = 256; 807 } 808 809 static void hwi_ring_eq_db(struct beiscsi_hba *phba, 810 unsigned int id, unsigned int clr_interrupt, 811 unsigned int num_processed, 812 unsigned char rearm, unsigned char event) 813 { 814 u32 val = 0; 815 816 if (rearm) 817 val |= 1 << DB_EQ_REARM_SHIFT; 818 if (clr_interrupt) 819 val |= 1 << DB_EQ_CLR_SHIFT; 820 if (event) 821 val |= 1 << DB_EQ_EVNT_SHIFT; 822 823 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT; 824 /* Setting lower order EQ_ID Bits */ 825 val |= (id & DB_EQ_RING_ID_LOW_MASK); 826 827 /* Setting Higher order EQ_ID Bits */ 828 val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) & 829 DB_EQ_RING_ID_HIGH_MASK) 830 << DB_EQ_HIGH_SET_SHIFT); 831 832 iowrite32(val, phba->db_va + DB_EQ_OFFSET); 833 } 834 835 /** 836 * be_isr_mcc - The isr routine of the driver. 837 * @irq: Not used 838 * @dev_id: Pointer to host adapter structure 839 */ 840 static irqreturn_t be_isr_mcc(int irq, void *dev_id) 841 { 842 struct beiscsi_hba *phba; 843 struct be_eq_entry *eqe = NULL; 844 struct be_queue_info *eq; 845 struct be_queue_info *mcc; 846 unsigned int num_eq_processed; 847 struct be_eq_obj *pbe_eq; 848 unsigned long flags; 849 850 pbe_eq = dev_id; 851 eq = &pbe_eq->q; 852 phba = pbe_eq->phba; 853 mcc = &phba->ctrl.mcc_obj.cq; 854 eqe = queue_tail_node(eq); 855 856 num_eq_processed = 0; 857 858 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 859 & EQE_VALID_MASK) { 860 if (((eqe->dw[offsetof(struct amap_eq_entry, 861 resource_id) / 32] & 862 EQE_RESID_MASK) >> 16) == mcc->id) { 863 spin_lock_irqsave(&phba->isr_lock, flags); 864 pbe_eq->todo_mcc_cq = true; 865 spin_unlock_irqrestore(&phba->isr_lock, flags); 866 } 867 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 868 queue_tail_inc(eq); 869 eqe = queue_tail_node(eq); 870 num_eq_processed++; 871 } 872 if (pbe_eq->todo_mcc_cq) 873 queue_work(phba->wq, &pbe_eq->work_cqs); 874 if (num_eq_processed) 875 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1); 876 877 return IRQ_HANDLED; 878 } 879 880 /** 881 * be_isr_msix - The isr routine of the driver. 882 * @irq: Not used 883 * @dev_id: Pointer to host adapter structure 884 */ 885 static irqreturn_t be_isr_msix(int irq, void *dev_id) 886 { 887 struct beiscsi_hba *phba; 888 struct be_eq_entry *eqe = NULL; 889 struct be_queue_info *eq; 890 struct be_queue_info *cq; 891 unsigned int num_eq_processed; 892 struct be_eq_obj *pbe_eq; 893 894 pbe_eq = dev_id; 895 eq = &pbe_eq->q; 896 cq = pbe_eq->cq; 897 eqe = queue_tail_node(eq); 898 899 phba = pbe_eq->phba; 900 num_eq_processed = 0; 901 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 902 & EQE_VALID_MASK) { 903 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll)) 904 blk_iopoll_sched(&pbe_eq->iopoll); 905 906 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 907 queue_tail_inc(eq); 908 eqe = queue_tail_node(eq); 909 num_eq_processed++; 910 } 911 912 if (num_eq_processed) 913 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1); 914 915 return IRQ_HANDLED; 916 } 917 918 /** 919 * be_isr - The isr routine of the driver. 920 * @irq: Not used 921 * @dev_id: Pointer to host adapter structure 922 */ 923 static irqreturn_t be_isr(int irq, void *dev_id) 924 { 925 struct beiscsi_hba *phba; 926 struct hwi_controller *phwi_ctrlr; 927 struct hwi_context_memory *phwi_context; 928 struct be_eq_entry *eqe = NULL; 929 struct be_queue_info *eq; 930 struct be_queue_info *mcc; 931 unsigned long flags, index; 932 unsigned int num_mcceq_processed, num_ioeq_processed; 933 struct be_ctrl_info *ctrl; 934 struct be_eq_obj *pbe_eq; 935 int isr; 936 937 phba = dev_id; 938 ctrl = &phba->ctrl; 939 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET + 940 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE)); 941 if (!isr) 942 return IRQ_NONE; 943 944 phwi_ctrlr = phba->phwi_ctrlr; 945 phwi_context = phwi_ctrlr->phwi_ctxt; 946 pbe_eq = &phwi_context->be_eq[0]; 947 948 eq = &phwi_context->be_eq[0].q; 949 mcc = &phba->ctrl.mcc_obj.cq; 950 index = 0; 951 eqe = queue_tail_node(eq); 952 953 num_ioeq_processed = 0; 954 num_mcceq_processed = 0; 955 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 956 & EQE_VALID_MASK) { 957 if (((eqe->dw[offsetof(struct amap_eq_entry, 958 resource_id) / 32] & 959 EQE_RESID_MASK) >> 16) == mcc->id) { 960 spin_lock_irqsave(&phba->isr_lock, flags); 961 pbe_eq->todo_mcc_cq = true; 962 spin_unlock_irqrestore(&phba->isr_lock, flags); 963 num_mcceq_processed++; 964 } else { 965 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll)) 966 blk_iopoll_sched(&pbe_eq->iopoll); 967 num_ioeq_processed++; 968 } 969 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 970 queue_tail_inc(eq); 971 eqe = queue_tail_node(eq); 972 } 973 if (num_ioeq_processed || num_mcceq_processed) { 974 if (pbe_eq->todo_mcc_cq) 975 queue_work(phba->wq, &pbe_eq->work_cqs); 976 977 if ((num_mcceq_processed) && (!num_ioeq_processed)) 978 hwi_ring_eq_db(phba, eq->id, 0, 979 (num_ioeq_processed + 980 num_mcceq_processed) , 1, 1); 981 else 982 hwi_ring_eq_db(phba, eq->id, 0, 983 (num_ioeq_processed + 984 num_mcceq_processed), 0, 1); 985 986 return IRQ_HANDLED; 987 } else 988 return IRQ_NONE; 989 } 990 991 static int beiscsi_init_irqs(struct beiscsi_hba *phba) 992 { 993 struct pci_dev *pcidev = phba->pcidev; 994 struct hwi_controller *phwi_ctrlr; 995 struct hwi_context_memory *phwi_context; 996 int ret, msix_vec, i, j; 997 998 phwi_ctrlr = phba->phwi_ctrlr; 999 phwi_context = phwi_ctrlr->phwi_ctxt; 1000 1001 if (phba->msix_enabled) { 1002 for (i = 0; i < phba->num_cpus; i++) { 1003 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, 1004 GFP_KERNEL); 1005 if (!phba->msi_name[i]) { 1006 ret = -ENOMEM; 1007 goto free_msix_irqs; 1008 } 1009 1010 sprintf(phba->msi_name[i], "beiscsi_%02x_%02x", 1011 phba->shost->host_no, i); 1012 msix_vec = phba->msix_entries[i].vector; 1013 ret = request_irq(msix_vec, be_isr_msix, 0, 1014 phba->msi_name[i], 1015 &phwi_context->be_eq[i]); 1016 if (ret) { 1017 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 1018 "BM_%d : beiscsi_init_irqs-Failed to" 1019 "register msix for i = %d\n", 1020 i); 1021 kfree(phba->msi_name[i]); 1022 goto free_msix_irqs; 1023 } 1024 } 1025 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL); 1026 if (!phba->msi_name[i]) { 1027 ret = -ENOMEM; 1028 goto free_msix_irqs; 1029 } 1030 sprintf(phba->msi_name[i], "beiscsi_mcc_%02x", 1031 phba->shost->host_no); 1032 msix_vec = phba->msix_entries[i].vector; 1033 ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i], 1034 &phwi_context->be_eq[i]); 1035 if (ret) { 1036 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT , 1037 "BM_%d : beiscsi_init_irqs-" 1038 "Failed to register beiscsi_msix_mcc\n"); 1039 kfree(phba->msi_name[i]); 1040 goto free_msix_irqs; 1041 } 1042 1043 } else { 1044 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED, 1045 "beiscsi", phba); 1046 if (ret) { 1047 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 1048 "BM_%d : beiscsi_init_irqs-" 1049 "Failed to register irq\\n"); 1050 return ret; 1051 } 1052 } 1053 return 0; 1054 free_msix_irqs: 1055 for (j = i - 1; j >= 0; j--) { 1056 kfree(phba->msi_name[j]); 1057 msix_vec = phba->msix_entries[j].vector; 1058 free_irq(msix_vec, &phwi_context->be_eq[j]); 1059 } 1060 return ret; 1061 } 1062 1063 void hwi_ring_cq_db(struct beiscsi_hba *phba, 1064 unsigned int id, unsigned int num_processed, 1065 unsigned char rearm, unsigned char event) 1066 { 1067 u32 val = 0; 1068 1069 if (rearm) 1070 val |= 1 << DB_CQ_REARM_SHIFT; 1071 1072 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT; 1073 1074 /* Setting lower order CQ_ID Bits */ 1075 val |= (id & DB_CQ_RING_ID_LOW_MASK); 1076 1077 /* Setting Higher order CQ_ID Bits */ 1078 val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) & 1079 DB_CQ_RING_ID_HIGH_MASK) 1080 << DB_CQ_HIGH_SET_SHIFT); 1081 1082 iowrite32(val, phba->db_va + DB_CQ_OFFSET); 1083 } 1084 1085 static unsigned int 1086 beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn, 1087 struct beiscsi_hba *phba, 1088 struct pdu_base *ppdu, 1089 unsigned long pdu_len, 1090 void *pbuffer, unsigned long buf_len) 1091 { 1092 struct iscsi_conn *conn = beiscsi_conn->conn; 1093 struct iscsi_session *session = conn->session; 1094 struct iscsi_task *task; 1095 struct beiscsi_io_task *io_task; 1096 struct iscsi_hdr *login_hdr; 1097 1098 switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] & 1099 PDUBASE_OPCODE_MASK) { 1100 case ISCSI_OP_NOOP_IN: 1101 pbuffer = NULL; 1102 buf_len = 0; 1103 break; 1104 case ISCSI_OP_ASYNC_EVENT: 1105 break; 1106 case ISCSI_OP_REJECT: 1107 WARN_ON(!pbuffer); 1108 WARN_ON(!(buf_len == 48)); 1109 beiscsi_log(phba, KERN_ERR, 1110 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1111 "BM_%d : In ISCSI_OP_REJECT\n"); 1112 break; 1113 case ISCSI_OP_LOGIN_RSP: 1114 case ISCSI_OP_TEXT_RSP: 1115 task = conn->login_task; 1116 io_task = task->dd_data; 1117 login_hdr = (struct iscsi_hdr *)ppdu; 1118 login_hdr->itt = io_task->libiscsi_itt; 1119 break; 1120 default: 1121 beiscsi_log(phba, KERN_WARNING, 1122 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1123 "BM_%d : Unrecognized opcode 0x%x in async msg\n", 1124 (ppdu-> 1125 dw[offsetof(struct amap_pdu_base, opcode) / 32] 1126 & PDUBASE_OPCODE_MASK)); 1127 return 1; 1128 } 1129 1130 spin_lock_bh(&session->back_lock); 1131 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len); 1132 spin_unlock_bh(&session->back_lock); 1133 return 0; 1134 } 1135 1136 static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba) 1137 { 1138 struct sgl_handle *psgl_handle; 1139 1140 if (phba->io_sgl_hndl_avbl) { 1141 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, 1142 "BM_%d : In alloc_io_sgl_handle," 1143 " io_sgl_alloc_index=%d\n", 1144 phba->io_sgl_alloc_index); 1145 1146 psgl_handle = phba->io_sgl_hndl_base[phba-> 1147 io_sgl_alloc_index]; 1148 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL; 1149 phba->io_sgl_hndl_avbl--; 1150 if (phba->io_sgl_alloc_index == (phba->params. 1151 ios_per_ctrl - 1)) 1152 phba->io_sgl_alloc_index = 0; 1153 else 1154 phba->io_sgl_alloc_index++; 1155 } else 1156 psgl_handle = NULL; 1157 return psgl_handle; 1158 } 1159 1160 static void 1161 free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) 1162 { 1163 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, 1164 "BM_%d : In free_,io_sgl_free_index=%d\n", 1165 phba->io_sgl_free_index); 1166 1167 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) { 1168 /* 1169 * this can happen if clean_task is called on a task that 1170 * failed in xmit_task or alloc_pdu. 1171 */ 1172 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, 1173 "BM_%d : Double Free in IO SGL io_sgl_free_index=%d," 1174 "value there=%p\n", phba->io_sgl_free_index, 1175 phba->io_sgl_hndl_base 1176 [phba->io_sgl_free_index]); 1177 return; 1178 } 1179 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle; 1180 phba->io_sgl_hndl_avbl++; 1181 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1)) 1182 phba->io_sgl_free_index = 0; 1183 else 1184 phba->io_sgl_free_index++; 1185 } 1186 1187 /** 1188 * alloc_wrb_handle - To allocate a wrb handle 1189 * @phba: The hba pointer 1190 * @cid: The cid to use for allocation 1191 * 1192 * This happens under session_lock until submission to chip 1193 */ 1194 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid) 1195 { 1196 struct hwi_wrb_context *pwrb_context; 1197 struct hwi_controller *phwi_ctrlr; 1198 struct wrb_handle *pwrb_handle, *pwrb_handle_tmp; 1199 uint16_t cri_index = BE_GET_CRI_FROM_CID(cid); 1200 1201 phwi_ctrlr = phba->phwi_ctrlr; 1202 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 1203 if (pwrb_context->wrb_handles_available >= 2) { 1204 pwrb_handle = pwrb_context->pwrb_handle_base[ 1205 pwrb_context->alloc_index]; 1206 pwrb_context->wrb_handles_available--; 1207 if (pwrb_context->alloc_index == 1208 (phba->params.wrbs_per_cxn - 1)) 1209 pwrb_context->alloc_index = 0; 1210 else 1211 pwrb_context->alloc_index++; 1212 pwrb_handle_tmp = pwrb_context->pwrb_handle_base[ 1213 pwrb_context->alloc_index]; 1214 pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index; 1215 } else 1216 pwrb_handle = NULL; 1217 return pwrb_handle; 1218 } 1219 1220 /** 1221 * free_wrb_handle - To free the wrb handle back to pool 1222 * @phba: The hba pointer 1223 * @pwrb_context: The context to free from 1224 * @pwrb_handle: The wrb_handle to free 1225 * 1226 * This happens under session_lock until submission to chip 1227 */ 1228 static void 1229 free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context, 1230 struct wrb_handle *pwrb_handle) 1231 { 1232 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle; 1233 pwrb_context->wrb_handles_available++; 1234 if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1)) 1235 pwrb_context->free_index = 0; 1236 else 1237 pwrb_context->free_index++; 1238 1239 beiscsi_log(phba, KERN_INFO, 1240 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1241 "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x" 1242 "wrb_handles_available=%d\n", 1243 pwrb_handle, pwrb_context->free_index, 1244 pwrb_context->wrb_handles_available); 1245 } 1246 1247 static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba) 1248 { 1249 struct sgl_handle *psgl_handle; 1250 1251 if (phba->eh_sgl_hndl_avbl) { 1252 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index]; 1253 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL; 1254 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, 1255 "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n", 1256 phba->eh_sgl_alloc_index, 1257 phba->eh_sgl_alloc_index); 1258 1259 phba->eh_sgl_hndl_avbl--; 1260 if (phba->eh_sgl_alloc_index == 1261 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1262 1)) 1263 phba->eh_sgl_alloc_index = 0; 1264 else 1265 phba->eh_sgl_alloc_index++; 1266 } else 1267 psgl_handle = NULL; 1268 return psgl_handle; 1269 } 1270 1271 void 1272 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) 1273 { 1274 1275 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, 1276 "BM_%d : In free_mgmt_sgl_handle," 1277 "eh_sgl_free_index=%d\n", 1278 phba->eh_sgl_free_index); 1279 1280 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) { 1281 /* 1282 * this can happen if clean_task is called on a task that 1283 * failed in xmit_task or alloc_pdu. 1284 */ 1285 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG, 1286 "BM_%d : Double Free in eh SGL ," 1287 "eh_sgl_free_index=%d\n", 1288 phba->eh_sgl_free_index); 1289 return; 1290 } 1291 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle; 1292 phba->eh_sgl_hndl_avbl++; 1293 if (phba->eh_sgl_free_index == 1294 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1)) 1295 phba->eh_sgl_free_index = 0; 1296 else 1297 phba->eh_sgl_free_index++; 1298 } 1299 1300 static void 1301 be_complete_io(struct beiscsi_conn *beiscsi_conn, 1302 struct iscsi_task *task, 1303 struct common_sol_cqe *csol_cqe) 1304 { 1305 struct beiscsi_io_task *io_task = task->dd_data; 1306 struct be_status_bhs *sts_bhs = 1307 (struct be_status_bhs *)io_task->cmd_bhs; 1308 struct iscsi_conn *conn = beiscsi_conn->conn; 1309 unsigned char *sense; 1310 u32 resid = 0, exp_cmdsn, max_cmdsn; 1311 u8 rsp, status, flags; 1312 1313 exp_cmdsn = csol_cqe->exp_cmdsn; 1314 max_cmdsn = (csol_cqe->exp_cmdsn + 1315 csol_cqe->cmd_wnd - 1); 1316 rsp = csol_cqe->i_resp; 1317 status = csol_cqe->i_sts; 1318 flags = csol_cqe->i_flags; 1319 resid = csol_cqe->res_cnt; 1320 1321 if (!task->sc) { 1322 if (io_task->scsi_cmnd) { 1323 scsi_dma_unmap(io_task->scsi_cmnd); 1324 io_task->scsi_cmnd = NULL; 1325 } 1326 1327 return; 1328 } 1329 task->sc->result = (DID_OK << 16) | status; 1330 if (rsp != ISCSI_STATUS_CMD_COMPLETED) { 1331 task->sc->result = DID_ERROR << 16; 1332 goto unmap; 1333 } 1334 1335 /* bidi not initially supported */ 1336 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) { 1337 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW)) 1338 task->sc->result = DID_ERROR << 16; 1339 1340 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) { 1341 scsi_set_resid(task->sc, resid); 1342 if (!status && (scsi_bufflen(task->sc) - resid < 1343 task->sc->underflow)) 1344 task->sc->result = DID_ERROR << 16; 1345 } 1346 } 1347 1348 if (status == SAM_STAT_CHECK_CONDITION) { 1349 u16 sense_len; 1350 unsigned short *slen = (unsigned short *)sts_bhs->sense_info; 1351 1352 sense = sts_bhs->sense_info + sizeof(unsigned short); 1353 sense_len = be16_to_cpu(*slen); 1354 memcpy(task->sc->sense_buffer, sense, 1355 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE)); 1356 } 1357 1358 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) 1359 conn->rxdata_octets += resid; 1360 unmap: 1361 scsi_dma_unmap(io_task->scsi_cmnd); 1362 io_task->scsi_cmnd = NULL; 1363 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn); 1364 } 1365 1366 static void 1367 be_complete_logout(struct beiscsi_conn *beiscsi_conn, 1368 struct iscsi_task *task, 1369 struct common_sol_cqe *csol_cqe) 1370 { 1371 struct iscsi_logout_rsp *hdr; 1372 struct beiscsi_io_task *io_task = task->dd_data; 1373 struct iscsi_conn *conn = beiscsi_conn->conn; 1374 1375 hdr = (struct iscsi_logout_rsp *)task->hdr; 1376 hdr->opcode = ISCSI_OP_LOGOUT_RSP; 1377 hdr->t2wait = 5; 1378 hdr->t2retain = 0; 1379 hdr->flags = csol_cqe->i_flags; 1380 hdr->response = csol_cqe->i_resp; 1381 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); 1382 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + 1383 csol_cqe->cmd_wnd - 1); 1384 1385 hdr->dlength[0] = 0; 1386 hdr->dlength[1] = 0; 1387 hdr->dlength[2] = 0; 1388 hdr->hlength = 0; 1389 hdr->itt = io_task->libiscsi_itt; 1390 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); 1391 } 1392 1393 static void 1394 be_complete_tmf(struct beiscsi_conn *beiscsi_conn, 1395 struct iscsi_task *task, 1396 struct common_sol_cqe *csol_cqe) 1397 { 1398 struct iscsi_tm_rsp *hdr; 1399 struct iscsi_conn *conn = beiscsi_conn->conn; 1400 struct beiscsi_io_task *io_task = task->dd_data; 1401 1402 hdr = (struct iscsi_tm_rsp *)task->hdr; 1403 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP; 1404 hdr->flags = csol_cqe->i_flags; 1405 hdr->response = csol_cqe->i_resp; 1406 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); 1407 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + 1408 csol_cqe->cmd_wnd - 1); 1409 1410 hdr->itt = io_task->libiscsi_itt; 1411 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); 1412 } 1413 1414 static void 1415 hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn, 1416 struct beiscsi_hba *phba, struct sol_cqe *psol) 1417 { 1418 struct hwi_wrb_context *pwrb_context; 1419 struct wrb_handle *pwrb_handle = NULL; 1420 struct hwi_controller *phwi_ctrlr; 1421 struct iscsi_task *task; 1422 struct beiscsi_io_task *io_task; 1423 uint16_t wrb_index, cid, cri_index; 1424 1425 phwi_ctrlr = phba->phwi_ctrlr; 1426 if (is_chip_be2_be3r(phba)) { 1427 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe, 1428 wrb_idx, psol); 1429 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe, 1430 cid, psol); 1431 } else { 1432 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2, 1433 wrb_idx, psol); 1434 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2, 1435 cid, psol); 1436 } 1437 1438 cri_index = BE_GET_CRI_FROM_CID(cid); 1439 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 1440 pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index]; 1441 task = pwrb_handle->pio_handle; 1442 1443 io_task = task->dd_data; 1444 memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb)); 1445 iscsi_put_task(task); 1446 } 1447 1448 static void 1449 be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn, 1450 struct iscsi_task *task, 1451 struct common_sol_cqe *csol_cqe) 1452 { 1453 struct iscsi_nopin *hdr; 1454 struct iscsi_conn *conn = beiscsi_conn->conn; 1455 struct beiscsi_io_task *io_task = task->dd_data; 1456 1457 hdr = (struct iscsi_nopin *)task->hdr; 1458 hdr->flags = csol_cqe->i_flags; 1459 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); 1460 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + 1461 csol_cqe->cmd_wnd - 1); 1462 1463 hdr->opcode = ISCSI_OP_NOOP_IN; 1464 hdr->itt = io_task->libiscsi_itt; 1465 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); 1466 } 1467 1468 static void adapter_get_sol_cqe(struct beiscsi_hba *phba, 1469 struct sol_cqe *psol, 1470 struct common_sol_cqe *csol_cqe) 1471 { 1472 if (is_chip_be2_be3r(phba)) { 1473 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe, 1474 i_exp_cmd_sn, psol); 1475 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe, 1476 i_res_cnt, psol); 1477 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe, 1478 i_cmd_wnd, psol); 1479 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe, 1480 wrb_index, psol); 1481 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe, 1482 cid, psol); 1483 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe, 1484 hw_sts, psol); 1485 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe, 1486 i_resp, psol); 1487 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe, 1488 i_sts, psol); 1489 csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe, 1490 i_flags, psol); 1491 } else { 1492 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1493 i_exp_cmd_sn, psol); 1494 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1495 i_res_cnt, psol); 1496 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1497 wrb_index, psol); 1498 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1499 cid, psol); 1500 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1501 hw_sts, psol); 1502 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1503 i_cmd_wnd, psol); 1504 if (AMAP_GET_BITS(struct amap_sol_cqe_v2, 1505 cmd_cmpl, psol)) 1506 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1507 i_sts, psol); 1508 else 1509 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1510 i_sts, psol); 1511 if (AMAP_GET_BITS(struct amap_sol_cqe_v2, 1512 u, psol)) 1513 csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW; 1514 1515 if (AMAP_GET_BITS(struct amap_sol_cqe_v2, 1516 o, psol)) 1517 csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW; 1518 } 1519 } 1520 1521 1522 static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn, 1523 struct beiscsi_hba *phba, struct sol_cqe *psol) 1524 { 1525 struct hwi_wrb_context *pwrb_context; 1526 struct wrb_handle *pwrb_handle; 1527 struct iscsi_wrb *pwrb = NULL; 1528 struct hwi_controller *phwi_ctrlr; 1529 struct iscsi_task *task; 1530 unsigned int type; 1531 struct iscsi_conn *conn = beiscsi_conn->conn; 1532 struct iscsi_session *session = conn->session; 1533 struct common_sol_cqe csol_cqe = {0}; 1534 uint16_t cri_index = 0; 1535 1536 phwi_ctrlr = phba->phwi_ctrlr; 1537 1538 /* Copy the elements to a common structure */ 1539 adapter_get_sol_cqe(phba, psol, &csol_cqe); 1540 1541 cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid); 1542 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 1543 1544 pwrb_handle = pwrb_context->pwrb_handle_basestd[ 1545 csol_cqe.wrb_index]; 1546 1547 task = pwrb_handle->pio_handle; 1548 pwrb = pwrb_handle->pwrb; 1549 type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type; 1550 1551 spin_lock_bh(&session->back_lock); 1552 switch (type) { 1553 case HWH_TYPE_IO: 1554 case HWH_TYPE_IO_RD: 1555 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == 1556 ISCSI_OP_NOOP_OUT) 1557 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe); 1558 else 1559 be_complete_io(beiscsi_conn, task, &csol_cqe); 1560 break; 1561 1562 case HWH_TYPE_LOGOUT: 1563 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT) 1564 be_complete_logout(beiscsi_conn, task, &csol_cqe); 1565 else 1566 be_complete_tmf(beiscsi_conn, task, &csol_cqe); 1567 break; 1568 1569 case HWH_TYPE_LOGIN: 1570 beiscsi_log(phba, KERN_ERR, 1571 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1572 "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in" 1573 " hwi_complete_cmd- Solicited path\n"); 1574 break; 1575 1576 case HWH_TYPE_NOP: 1577 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe); 1578 break; 1579 1580 default: 1581 beiscsi_log(phba, KERN_WARNING, 1582 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1583 "BM_%d : In hwi_complete_cmd, unknown type = %d" 1584 "wrb_index 0x%x CID 0x%x\n", type, 1585 csol_cqe.wrb_index, 1586 csol_cqe.cid); 1587 break; 1588 } 1589 1590 spin_unlock_bh(&session->back_lock); 1591 } 1592 1593 static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context 1594 *pasync_ctx, unsigned int is_header, 1595 unsigned int host_write_ptr) 1596 { 1597 if (is_header) 1598 return &pasync_ctx->async_entry[host_write_ptr]. 1599 header_busy_list; 1600 else 1601 return &pasync_ctx->async_entry[host_write_ptr].data_busy_list; 1602 } 1603 1604 static struct async_pdu_handle * 1605 hwi_get_async_handle(struct beiscsi_hba *phba, 1606 struct beiscsi_conn *beiscsi_conn, 1607 struct hwi_async_pdu_context *pasync_ctx, 1608 struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index) 1609 { 1610 struct be_bus_address phys_addr; 1611 struct list_head *pbusy_list; 1612 struct async_pdu_handle *pasync_handle = NULL; 1613 unsigned char is_header = 0; 1614 unsigned int index, dpl; 1615 1616 if (is_chip_be2_be3r(phba)) { 1617 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1618 dpl, pdpdu_cqe); 1619 index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1620 index, pdpdu_cqe); 1621 } else { 1622 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, 1623 dpl, pdpdu_cqe); 1624 index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, 1625 index, pdpdu_cqe); 1626 } 1627 1628 phys_addr.u.a32.address_lo = 1629 (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, 1630 db_addr_lo) / 32] - dpl); 1631 phys_addr.u.a32.address_hi = 1632 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, 1633 db_addr_hi) / 32]; 1634 1635 phys_addr.u.a64.address = 1636 *((unsigned long long *)(&phys_addr.u.a64.address)); 1637 1638 switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32] 1639 & PDUCQE_CODE_MASK) { 1640 case UNSOL_HDR_NOTIFY: 1641 is_header = 1; 1642 1643 pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1644 is_header, index); 1645 break; 1646 case UNSOL_DATA_NOTIFY: 1647 pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1648 is_header, index); 1649 break; 1650 default: 1651 pbusy_list = NULL; 1652 beiscsi_log(phba, KERN_WARNING, 1653 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1654 "BM_%d : Unexpected code=%d\n", 1655 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, 1656 code) / 32] & PDUCQE_CODE_MASK); 1657 return NULL; 1658 } 1659 1660 WARN_ON(list_empty(pbusy_list)); 1661 list_for_each_entry(pasync_handle, pbusy_list, link) { 1662 if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address) 1663 break; 1664 } 1665 1666 WARN_ON(!pasync_handle); 1667 1668 pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID( 1669 beiscsi_conn->beiscsi_conn_cid); 1670 pasync_handle->is_header = is_header; 1671 pasync_handle->buffer_len = dpl; 1672 *pcq_index = index; 1673 1674 return pasync_handle; 1675 } 1676 1677 static unsigned int 1678 hwi_update_async_writables(struct beiscsi_hba *phba, 1679 struct hwi_async_pdu_context *pasync_ctx, 1680 unsigned int is_header, unsigned int cq_index) 1681 { 1682 struct list_head *pbusy_list; 1683 struct async_pdu_handle *pasync_handle; 1684 unsigned int num_entries, writables = 0; 1685 unsigned int *pep_read_ptr, *pwritables; 1686 1687 num_entries = pasync_ctx->num_entries; 1688 if (is_header) { 1689 pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr; 1690 pwritables = &pasync_ctx->async_header.writables; 1691 } else { 1692 pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr; 1693 pwritables = &pasync_ctx->async_data.writables; 1694 } 1695 1696 while ((*pep_read_ptr) != cq_index) { 1697 (*pep_read_ptr)++; 1698 *pep_read_ptr = (*pep_read_ptr) % num_entries; 1699 1700 pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header, 1701 *pep_read_ptr); 1702 if (writables == 0) 1703 WARN_ON(list_empty(pbusy_list)); 1704 1705 if (!list_empty(pbusy_list)) { 1706 pasync_handle = list_entry(pbusy_list->next, 1707 struct async_pdu_handle, 1708 link); 1709 WARN_ON(!pasync_handle); 1710 pasync_handle->consumed = 1; 1711 } 1712 1713 writables++; 1714 } 1715 1716 if (!writables) { 1717 beiscsi_log(phba, KERN_ERR, 1718 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1719 "BM_%d : Duplicate notification received - index 0x%x!!\n", 1720 cq_index); 1721 WARN_ON(1); 1722 } 1723 1724 *pwritables = *pwritables + writables; 1725 return 0; 1726 } 1727 1728 static void hwi_free_async_msg(struct beiscsi_hba *phba, 1729 struct hwi_async_pdu_context *pasync_ctx, 1730 unsigned int cri) 1731 { 1732 struct async_pdu_handle *pasync_handle, *tmp_handle; 1733 struct list_head *plist; 1734 1735 plist = &pasync_ctx->async_entry[cri].wait_queue.list; 1736 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) { 1737 list_del(&pasync_handle->link); 1738 1739 if (pasync_handle->is_header) { 1740 list_add_tail(&pasync_handle->link, 1741 &pasync_ctx->async_header.free_list); 1742 pasync_ctx->async_header.free_entries++; 1743 } else { 1744 list_add_tail(&pasync_handle->link, 1745 &pasync_ctx->async_data.free_list); 1746 pasync_ctx->async_data.free_entries++; 1747 } 1748 } 1749 1750 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list); 1751 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0; 1752 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0; 1753 } 1754 1755 static struct phys_addr * 1756 hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx, 1757 unsigned int is_header, unsigned int host_write_ptr) 1758 { 1759 struct phys_addr *pasync_sge = NULL; 1760 1761 if (is_header) 1762 pasync_sge = pasync_ctx->async_header.ring_base; 1763 else 1764 pasync_sge = pasync_ctx->async_data.ring_base; 1765 1766 return pasync_sge + host_write_ptr; 1767 } 1768 1769 static void hwi_post_async_buffers(struct beiscsi_hba *phba, 1770 unsigned int is_header, uint8_t ulp_num) 1771 { 1772 struct hwi_controller *phwi_ctrlr; 1773 struct hwi_async_pdu_context *pasync_ctx; 1774 struct async_pdu_handle *pasync_handle; 1775 struct list_head *pfree_link, *pbusy_list; 1776 struct phys_addr *pasync_sge; 1777 unsigned int ring_id, num_entries; 1778 unsigned int host_write_num, doorbell_offset; 1779 unsigned int writables; 1780 unsigned int i = 0; 1781 u32 doorbell = 0; 1782 1783 phwi_ctrlr = phba->phwi_ctrlr; 1784 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num); 1785 num_entries = pasync_ctx->num_entries; 1786 1787 if (is_header) { 1788 writables = min(pasync_ctx->async_header.writables, 1789 pasync_ctx->async_header.free_entries); 1790 pfree_link = pasync_ctx->async_header.free_list.next; 1791 host_write_num = pasync_ctx->async_header.host_write_ptr; 1792 ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id; 1793 doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num]. 1794 doorbell_offset; 1795 } else { 1796 writables = min(pasync_ctx->async_data.writables, 1797 pasync_ctx->async_data.free_entries); 1798 pfree_link = pasync_ctx->async_data.free_list.next; 1799 host_write_num = pasync_ctx->async_data.host_write_ptr; 1800 ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id; 1801 doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num]. 1802 doorbell_offset; 1803 } 1804 1805 writables = (writables / 8) * 8; 1806 if (writables) { 1807 for (i = 0; i < writables; i++) { 1808 pbusy_list = 1809 hwi_get_async_busy_list(pasync_ctx, is_header, 1810 host_write_num); 1811 pasync_handle = 1812 list_entry(pfree_link, struct async_pdu_handle, 1813 link); 1814 WARN_ON(!pasync_handle); 1815 pasync_handle->consumed = 0; 1816 1817 pfree_link = pfree_link->next; 1818 1819 pasync_sge = hwi_get_ring_address(pasync_ctx, 1820 is_header, host_write_num); 1821 1822 pasync_sge->hi = pasync_handle->pa.u.a32.address_lo; 1823 pasync_sge->lo = pasync_handle->pa.u.a32.address_hi; 1824 1825 list_move(&pasync_handle->link, pbusy_list); 1826 1827 host_write_num++; 1828 host_write_num = host_write_num % num_entries; 1829 } 1830 1831 if (is_header) { 1832 pasync_ctx->async_header.host_write_ptr = 1833 host_write_num; 1834 pasync_ctx->async_header.free_entries -= writables; 1835 pasync_ctx->async_header.writables -= writables; 1836 pasync_ctx->async_header.busy_entries += writables; 1837 } else { 1838 pasync_ctx->async_data.host_write_ptr = host_write_num; 1839 pasync_ctx->async_data.free_entries -= writables; 1840 pasync_ctx->async_data.writables -= writables; 1841 pasync_ctx->async_data.busy_entries += writables; 1842 } 1843 1844 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK; 1845 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT; 1846 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT; 1847 doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK) 1848 << DB_DEF_PDU_CQPROC_SHIFT; 1849 1850 iowrite32(doorbell, phba->db_va + doorbell_offset); 1851 } 1852 } 1853 1854 static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba, 1855 struct beiscsi_conn *beiscsi_conn, 1856 struct i_t_dpdu_cqe *pdpdu_cqe) 1857 { 1858 struct hwi_controller *phwi_ctrlr; 1859 struct hwi_async_pdu_context *pasync_ctx; 1860 struct async_pdu_handle *pasync_handle = NULL; 1861 unsigned int cq_index = -1; 1862 uint16_t cri_index = BE_GET_CRI_FROM_CID( 1863 beiscsi_conn->beiscsi_conn_cid); 1864 1865 phwi_ctrlr = phba->phwi_ctrlr; 1866 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, 1867 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, 1868 cri_index)); 1869 1870 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx, 1871 pdpdu_cqe, &cq_index); 1872 BUG_ON(pasync_handle->is_header != 0); 1873 if (pasync_handle->consumed == 0) 1874 hwi_update_async_writables(phba, pasync_ctx, 1875 pasync_handle->is_header, cq_index); 1876 1877 hwi_free_async_msg(phba, pasync_ctx, pasync_handle->cri); 1878 hwi_post_async_buffers(phba, pasync_handle->is_header, 1879 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, 1880 cri_index)); 1881 } 1882 1883 static unsigned int 1884 hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn, 1885 struct beiscsi_hba *phba, 1886 struct hwi_async_pdu_context *pasync_ctx, unsigned short cri) 1887 { 1888 struct list_head *plist; 1889 struct async_pdu_handle *pasync_handle; 1890 void *phdr = NULL; 1891 unsigned int hdr_len = 0, buf_len = 0; 1892 unsigned int status, index = 0, offset = 0; 1893 void *pfirst_buffer = NULL; 1894 unsigned int num_buf = 0; 1895 1896 plist = &pasync_ctx->async_entry[cri].wait_queue.list; 1897 1898 list_for_each_entry(pasync_handle, plist, link) { 1899 if (index == 0) { 1900 phdr = pasync_handle->pbuffer; 1901 hdr_len = pasync_handle->buffer_len; 1902 } else { 1903 buf_len = pasync_handle->buffer_len; 1904 if (!num_buf) { 1905 pfirst_buffer = pasync_handle->pbuffer; 1906 num_buf++; 1907 } 1908 memcpy(pfirst_buffer + offset, 1909 pasync_handle->pbuffer, buf_len); 1910 offset += buf_len; 1911 } 1912 index++; 1913 } 1914 1915 status = beiscsi_process_async_pdu(beiscsi_conn, phba, 1916 phdr, hdr_len, pfirst_buffer, 1917 offset); 1918 1919 hwi_free_async_msg(phba, pasync_ctx, cri); 1920 return 0; 1921 } 1922 1923 static unsigned int 1924 hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn, 1925 struct beiscsi_hba *phba, 1926 struct async_pdu_handle *pasync_handle) 1927 { 1928 struct hwi_async_pdu_context *pasync_ctx; 1929 struct hwi_controller *phwi_ctrlr; 1930 unsigned int bytes_needed = 0, status = 0; 1931 unsigned short cri = pasync_handle->cri; 1932 struct pdu_base *ppdu; 1933 1934 phwi_ctrlr = phba->phwi_ctrlr; 1935 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, 1936 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, 1937 BE_GET_CRI_FROM_CID(beiscsi_conn-> 1938 beiscsi_conn_cid))); 1939 1940 list_del(&pasync_handle->link); 1941 if (pasync_handle->is_header) { 1942 pasync_ctx->async_header.busy_entries--; 1943 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) { 1944 hwi_free_async_msg(phba, pasync_ctx, cri); 1945 BUG(); 1946 } 1947 1948 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0; 1949 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1; 1950 pasync_ctx->async_entry[cri].wait_queue.hdr_len = 1951 (unsigned short)pasync_handle->buffer_len; 1952 list_add_tail(&pasync_handle->link, 1953 &pasync_ctx->async_entry[cri].wait_queue.list); 1954 1955 ppdu = pasync_handle->pbuffer; 1956 bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base, 1957 data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) & 1958 0xFFFF0000) | ((be16_to_cpu((ppdu-> 1959 dw[offsetof(struct amap_pdu_base, data_len_lo) / 32] 1960 & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF)); 1961 1962 if (status == 0) { 1963 pasync_ctx->async_entry[cri].wait_queue.bytes_needed = 1964 bytes_needed; 1965 1966 if (bytes_needed == 0) 1967 status = hwi_fwd_async_msg(beiscsi_conn, phba, 1968 pasync_ctx, cri); 1969 } 1970 } else { 1971 pasync_ctx->async_data.busy_entries--; 1972 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) { 1973 list_add_tail(&pasync_handle->link, 1974 &pasync_ctx->async_entry[cri].wait_queue. 1975 list); 1976 pasync_ctx->async_entry[cri].wait_queue. 1977 bytes_received += 1978 (unsigned short)pasync_handle->buffer_len; 1979 1980 if (pasync_ctx->async_entry[cri].wait_queue. 1981 bytes_received >= 1982 pasync_ctx->async_entry[cri].wait_queue. 1983 bytes_needed) 1984 status = hwi_fwd_async_msg(beiscsi_conn, phba, 1985 pasync_ctx, cri); 1986 } 1987 } 1988 return status; 1989 } 1990 1991 static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn, 1992 struct beiscsi_hba *phba, 1993 struct i_t_dpdu_cqe *pdpdu_cqe) 1994 { 1995 struct hwi_controller *phwi_ctrlr; 1996 struct hwi_async_pdu_context *pasync_ctx; 1997 struct async_pdu_handle *pasync_handle = NULL; 1998 unsigned int cq_index = -1; 1999 uint16_t cri_index = BE_GET_CRI_FROM_CID( 2000 beiscsi_conn->beiscsi_conn_cid); 2001 2002 phwi_ctrlr = phba->phwi_ctrlr; 2003 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, 2004 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, 2005 cri_index)); 2006 2007 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx, 2008 pdpdu_cqe, &cq_index); 2009 2010 if (pasync_handle->consumed == 0) 2011 hwi_update_async_writables(phba, pasync_ctx, 2012 pasync_handle->is_header, cq_index); 2013 2014 hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle); 2015 hwi_post_async_buffers(phba, pasync_handle->is_header, 2016 BEISCSI_GET_ULP_FROM_CRI( 2017 phwi_ctrlr, cri_index)); 2018 } 2019 2020 static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba) 2021 { 2022 struct be_queue_info *mcc_cq; 2023 struct be_mcc_compl *mcc_compl; 2024 unsigned int num_processed = 0; 2025 2026 mcc_cq = &phba->ctrl.mcc_obj.cq; 2027 mcc_compl = queue_tail_node(mcc_cq); 2028 mcc_compl->flags = le32_to_cpu(mcc_compl->flags); 2029 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) { 2030 2031 if (num_processed >= 32) { 2032 hwi_ring_cq_db(phba, mcc_cq->id, 2033 num_processed, 0, 0); 2034 num_processed = 0; 2035 } 2036 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) { 2037 /* Interpret flags as an async trailer */ 2038 if (is_link_state_evt(mcc_compl->flags)) 2039 /* Interpret compl as a async link evt */ 2040 beiscsi_async_link_state_process(phba, 2041 (struct be_async_event_link_state *) mcc_compl); 2042 else 2043 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX, 2044 "BM_%d : Unsupported Async Event, flags" 2045 " = 0x%08x\n", 2046 mcc_compl->flags); 2047 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) { 2048 be_mcc_compl_process_isr(&phba->ctrl, mcc_compl); 2049 atomic_dec(&phba->ctrl.mcc_obj.q.used); 2050 } 2051 2052 mcc_compl->flags = 0; 2053 queue_tail_inc(mcc_cq); 2054 mcc_compl = queue_tail_node(mcc_cq); 2055 mcc_compl->flags = le32_to_cpu(mcc_compl->flags); 2056 num_processed++; 2057 } 2058 2059 if (num_processed > 0) 2060 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0); 2061 2062 } 2063 2064 /** 2065 * beiscsi_process_cq()- Process the Completion Queue 2066 * @pbe_eq: Event Q on which the Completion has come 2067 * 2068 * return 2069 * Number of Completion Entries processed. 2070 **/ 2071 static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq) 2072 { 2073 struct be_queue_info *cq; 2074 struct sol_cqe *sol; 2075 struct dmsg_cqe *dmsg; 2076 unsigned int num_processed = 0; 2077 unsigned int tot_nump = 0; 2078 unsigned short code = 0, cid = 0; 2079 uint16_t cri_index = 0; 2080 struct beiscsi_conn *beiscsi_conn; 2081 struct beiscsi_endpoint *beiscsi_ep; 2082 struct iscsi_endpoint *ep; 2083 struct beiscsi_hba *phba; 2084 2085 cq = pbe_eq->cq; 2086 sol = queue_tail_node(cq); 2087 phba = pbe_eq->phba; 2088 2089 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] & 2090 CQE_VALID_MASK) { 2091 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe)); 2092 2093 code = (sol->dw[offsetof(struct amap_sol_cqe, code) / 2094 32] & CQE_CODE_MASK); 2095 2096 /* Get the CID */ 2097 if (is_chip_be2_be3r(phba)) { 2098 cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol); 2099 } else { 2100 if ((code == DRIVERMSG_NOTIFY) || 2101 (code == UNSOL_HDR_NOTIFY) || 2102 (code == UNSOL_DATA_NOTIFY)) 2103 cid = AMAP_GET_BITS( 2104 struct amap_i_t_dpdu_cqe_v2, 2105 cid, sol); 2106 else 2107 cid = AMAP_GET_BITS(struct amap_sol_cqe_v2, 2108 cid, sol); 2109 } 2110 2111 cri_index = BE_GET_CRI_FROM_CID(cid); 2112 ep = phba->ep_array[cri_index]; 2113 beiscsi_ep = ep->dd_data; 2114 beiscsi_conn = beiscsi_ep->conn; 2115 2116 if (num_processed >= 32) { 2117 hwi_ring_cq_db(phba, cq->id, 2118 num_processed, 0, 0); 2119 tot_nump += num_processed; 2120 num_processed = 0; 2121 } 2122 2123 switch (code) { 2124 case SOL_CMD_COMPLETE: 2125 hwi_complete_cmd(beiscsi_conn, phba, sol); 2126 break; 2127 case DRIVERMSG_NOTIFY: 2128 beiscsi_log(phba, KERN_INFO, 2129 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2130 "BM_%d : Received %s[%d] on CID : %d\n", 2131 cqe_desc[code], code, cid); 2132 2133 dmsg = (struct dmsg_cqe *)sol; 2134 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol); 2135 break; 2136 case UNSOL_HDR_NOTIFY: 2137 beiscsi_log(phba, KERN_INFO, 2138 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2139 "BM_%d : Received %s[%d] on CID : %d\n", 2140 cqe_desc[code], code, cid); 2141 2142 spin_lock_bh(&phba->async_pdu_lock); 2143 hwi_process_default_pdu_ring(beiscsi_conn, phba, 2144 (struct i_t_dpdu_cqe *)sol); 2145 spin_unlock_bh(&phba->async_pdu_lock); 2146 break; 2147 case UNSOL_DATA_NOTIFY: 2148 beiscsi_log(phba, KERN_INFO, 2149 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 2150 "BM_%d : Received %s[%d] on CID : %d\n", 2151 cqe_desc[code], code, cid); 2152 2153 spin_lock_bh(&phba->async_pdu_lock); 2154 hwi_process_default_pdu_ring(beiscsi_conn, phba, 2155 (struct i_t_dpdu_cqe *)sol); 2156 spin_unlock_bh(&phba->async_pdu_lock); 2157 break; 2158 case CXN_INVALIDATE_INDEX_NOTIFY: 2159 case CMD_INVALIDATED_NOTIFY: 2160 case CXN_INVALIDATE_NOTIFY: 2161 beiscsi_log(phba, KERN_ERR, 2162 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2163 "BM_%d : Ignoring %s[%d] on CID : %d\n", 2164 cqe_desc[code], code, cid); 2165 break; 2166 case SOL_CMD_KILLED_DATA_DIGEST_ERR: 2167 case CMD_KILLED_INVALID_STATSN_RCVD: 2168 case CMD_KILLED_INVALID_R2T_RCVD: 2169 case CMD_CXN_KILLED_LUN_INVALID: 2170 case CMD_CXN_KILLED_ICD_INVALID: 2171 case CMD_CXN_KILLED_ITT_INVALID: 2172 case CMD_CXN_KILLED_SEQ_OUTOFORDER: 2173 case CMD_CXN_KILLED_INVALID_DATASN_RCVD: 2174 beiscsi_log(phba, KERN_ERR, 2175 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 2176 "BM_%d : Cmd Notification %s[%d] on CID : %d\n", 2177 cqe_desc[code], code, cid); 2178 break; 2179 case UNSOL_DATA_DIGEST_ERROR_NOTIFY: 2180 beiscsi_log(phba, KERN_ERR, 2181 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2182 "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n", 2183 cqe_desc[code], code, cid); 2184 spin_lock_bh(&phba->async_pdu_lock); 2185 hwi_flush_default_pdu_buffer(phba, beiscsi_conn, 2186 (struct i_t_dpdu_cqe *) sol); 2187 spin_unlock_bh(&phba->async_pdu_lock); 2188 break; 2189 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL: 2190 case CXN_KILLED_BURST_LEN_MISMATCH: 2191 case CXN_KILLED_AHS_RCVD: 2192 case CXN_KILLED_HDR_DIGEST_ERR: 2193 case CXN_KILLED_UNKNOWN_HDR: 2194 case CXN_KILLED_STALE_ITT_TTT_RCVD: 2195 case CXN_KILLED_INVALID_ITT_TTT_RCVD: 2196 case CXN_KILLED_TIMED_OUT: 2197 case CXN_KILLED_FIN_RCVD: 2198 case CXN_KILLED_RST_SENT: 2199 case CXN_KILLED_RST_RCVD: 2200 case CXN_KILLED_BAD_UNSOL_PDU_RCVD: 2201 case CXN_KILLED_BAD_WRB_INDEX_ERROR: 2202 case CXN_KILLED_OVER_RUN_RESIDUAL: 2203 case CXN_KILLED_UNDER_RUN_RESIDUAL: 2204 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN: 2205 beiscsi_log(phba, KERN_ERR, 2206 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2207 "BM_%d : Event %s[%d] received on CID : %d\n", 2208 cqe_desc[code], code, cid); 2209 if (beiscsi_conn) 2210 iscsi_conn_failure(beiscsi_conn->conn, 2211 ISCSI_ERR_CONN_FAILED); 2212 break; 2213 default: 2214 beiscsi_log(phba, KERN_ERR, 2215 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2216 "BM_%d : Invalid CQE Event Received Code : %d" 2217 "CID 0x%x...\n", 2218 code, cid); 2219 break; 2220 } 2221 2222 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0); 2223 queue_tail_inc(cq); 2224 sol = queue_tail_node(cq); 2225 num_processed++; 2226 } 2227 2228 if (num_processed > 0) { 2229 tot_nump += num_processed; 2230 hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0); 2231 } 2232 return tot_nump; 2233 } 2234 2235 void beiscsi_process_all_cqs(struct work_struct *work) 2236 { 2237 unsigned long flags; 2238 struct hwi_controller *phwi_ctrlr; 2239 struct hwi_context_memory *phwi_context; 2240 struct beiscsi_hba *phba; 2241 struct be_eq_obj *pbe_eq = 2242 container_of(work, struct be_eq_obj, work_cqs); 2243 2244 phba = pbe_eq->phba; 2245 phwi_ctrlr = phba->phwi_ctrlr; 2246 phwi_context = phwi_ctrlr->phwi_ctxt; 2247 2248 if (pbe_eq->todo_mcc_cq) { 2249 spin_lock_irqsave(&phba->isr_lock, flags); 2250 pbe_eq->todo_mcc_cq = false; 2251 spin_unlock_irqrestore(&phba->isr_lock, flags); 2252 beiscsi_process_mcc_isr(phba); 2253 } 2254 2255 if (pbe_eq->todo_cq) { 2256 spin_lock_irqsave(&phba->isr_lock, flags); 2257 pbe_eq->todo_cq = false; 2258 spin_unlock_irqrestore(&phba->isr_lock, flags); 2259 beiscsi_process_cq(pbe_eq); 2260 } 2261 2262 /* rearm EQ for further interrupts */ 2263 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); 2264 } 2265 2266 static int be_iopoll(struct blk_iopoll *iop, int budget) 2267 { 2268 unsigned int ret; 2269 struct beiscsi_hba *phba; 2270 struct be_eq_obj *pbe_eq; 2271 2272 pbe_eq = container_of(iop, struct be_eq_obj, iopoll); 2273 ret = beiscsi_process_cq(pbe_eq); 2274 pbe_eq->cq_count += ret; 2275 if (ret < budget) { 2276 phba = pbe_eq->phba; 2277 blk_iopoll_complete(iop); 2278 beiscsi_log(phba, KERN_INFO, 2279 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 2280 "BM_%d : rearm pbe_eq->q.id =%d\n", 2281 pbe_eq->q.id); 2282 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); 2283 } 2284 return ret; 2285 } 2286 2287 static void 2288 hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg, 2289 unsigned int num_sg, struct beiscsi_io_task *io_task) 2290 { 2291 struct iscsi_sge *psgl; 2292 unsigned int sg_len, index; 2293 unsigned int sge_len = 0; 2294 unsigned long long addr; 2295 struct scatterlist *l_sg; 2296 unsigned int offset; 2297 2298 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb, 2299 io_task->bhs_pa.u.a32.address_lo); 2300 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb, 2301 io_task->bhs_pa.u.a32.address_hi); 2302 2303 l_sg = sg; 2304 for (index = 0; (index < num_sg) && (index < 2); index++, 2305 sg = sg_next(sg)) { 2306 if (index == 0) { 2307 sg_len = sg_dma_len(sg); 2308 addr = (u64) sg_dma_address(sg); 2309 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2310 sge0_addr_lo, pwrb, 2311 lower_32_bits(addr)); 2312 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2313 sge0_addr_hi, pwrb, 2314 upper_32_bits(addr)); 2315 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2316 sge0_len, pwrb, 2317 sg_len); 2318 sge_len = sg_len; 2319 } else { 2320 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset, 2321 pwrb, sge_len); 2322 sg_len = sg_dma_len(sg); 2323 addr = (u64) sg_dma_address(sg); 2324 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2325 sge1_addr_lo, pwrb, 2326 lower_32_bits(addr)); 2327 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2328 sge1_addr_hi, pwrb, 2329 upper_32_bits(addr)); 2330 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2331 sge1_len, pwrb, 2332 sg_len); 2333 } 2334 } 2335 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2336 memset(psgl, 0, sizeof(*psgl) * BE2_SGE); 2337 2338 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); 2339 2340 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2341 io_task->bhs_pa.u.a32.address_hi); 2342 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2343 io_task->bhs_pa.u.a32.address_lo); 2344 2345 if (num_sg == 1) { 2346 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, 2347 1); 2348 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, 2349 0); 2350 } else if (num_sg == 2) { 2351 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, 2352 0); 2353 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, 2354 1); 2355 } else { 2356 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, 2357 0); 2358 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, 2359 0); 2360 } 2361 2362 sg = l_sg; 2363 psgl++; 2364 psgl++; 2365 offset = 0; 2366 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { 2367 sg_len = sg_dma_len(sg); 2368 addr = (u64) sg_dma_address(sg); 2369 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2370 lower_32_bits(addr)); 2371 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2372 upper_32_bits(addr)); 2373 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); 2374 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); 2375 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2376 offset += sg_len; 2377 } 2378 psgl--; 2379 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2380 } 2381 2382 static void 2383 hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg, 2384 unsigned int num_sg, struct beiscsi_io_task *io_task) 2385 { 2386 struct iscsi_sge *psgl; 2387 unsigned int sg_len, index; 2388 unsigned int sge_len = 0; 2389 unsigned long long addr; 2390 struct scatterlist *l_sg; 2391 unsigned int offset; 2392 2393 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, 2394 io_task->bhs_pa.u.a32.address_lo); 2395 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, 2396 io_task->bhs_pa.u.a32.address_hi); 2397 2398 l_sg = sg; 2399 for (index = 0; (index < num_sg) && (index < 2); index++, 2400 sg = sg_next(sg)) { 2401 if (index == 0) { 2402 sg_len = sg_dma_len(sg); 2403 addr = (u64) sg_dma_address(sg); 2404 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, 2405 ((u32)(addr & 0xFFFFFFFF))); 2406 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, 2407 ((u32)(addr >> 32))); 2408 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, 2409 sg_len); 2410 sge_len = sg_len; 2411 } else { 2412 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset, 2413 pwrb, sge_len); 2414 sg_len = sg_dma_len(sg); 2415 addr = (u64) sg_dma_address(sg); 2416 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb, 2417 ((u32)(addr & 0xFFFFFFFF))); 2418 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb, 2419 ((u32)(addr >> 32))); 2420 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb, 2421 sg_len); 2422 } 2423 } 2424 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2425 memset(psgl, 0, sizeof(*psgl) * BE2_SGE); 2426 2427 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); 2428 2429 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2430 io_task->bhs_pa.u.a32.address_hi); 2431 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2432 io_task->bhs_pa.u.a32.address_lo); 2433 2434 if (num_sg == 1) { 2435 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2436 1); 2437 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2438 0); 2439 } else if (num_sg == 2) { 2440 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2441 0); 2442 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2443 1); 2444 } else { 2445 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2446 0); 2447 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2448 0); 2449 } 2450 sg = l_sg; 2451 psgl++; 2452 psgl++; 2453 offset = 0; 2454 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { 2455 sg_len = sg_dma_len(sg); 2456 addr = (u64) sg_dma_address(sg); 2457 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2458 (addr & 0xFFFFFFFF)); 2459 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2460 (addr >> 32)); 2461 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); 2462 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); 2463 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2464 offset += sg_len; 2465 } 2466 psgl--; 2467 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2468 } 2469 2470 /** 2471 * hwi_write_buffer()- Populate the WRB with task info 2472 * @pwrb: ptr to the WRB entry 2473 * @task: iscsi task which is to be executed 2474 **/ 2475 static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task) 2476 { 2477 struct iscsi_sge *psgl; 2478 struct beiscsi_io_task *io_task = task->dd_data; 2479 struct beiscsi_conn *beiscsi_conn = io_task->conn; 2480 struct beiscsi_hba *phba = beiscsi_conn->phba; 2481 uint8_t dsp_value = 0; 2482 2483 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2; 2484 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, 2485 io_task->bhs_pa.u.a32.address_lo); 2486 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, 2487 io_task->bhs_pa.u.a32.address_hi); 2488 2489 if (task->data) { 2490 2491 /* Check for the data_count */ 2492 dsp_value = (task->data_count) ? 1 : 0; 2493 2494 if (is_chip_be2_be3r(phba)) 2495 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, 2496 pwrb, dsp_value); 2497 else 2498 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, 2499 pwrb, dsp_value); 2500 2501 /* Map addr only if there is data_count */ 2502 if (dsp_value) { 2503 io_task->mtask_addr = pci_map_single(phba->pcidev, 2504 task->data, 2505 task->data_count, 2506 PCI_DMA_TODEVICE); 2507 io_task->mtask_data_count = task->data_count; 2508 } else 2509 io_task->mtask_addr = 0; 2510 2511 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, 2512 lower_32_bits(io_task->mtask_addr)); 2513 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, 2514 upper_32_bits(io_task->mtask_addr)); 2515 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, 2516 task->data_count); 2517 2518 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1); 2519 } else { 2520 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); 2521 io_task->mtask_addr = 0; 2522 } 2523 2524 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2525 2526 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len); 2527 2528 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2529 io_task->bhs_pa.u.a32.address_hi); 2530 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2531 io_task->bhs_pa.u.a32.address_lo); 2532 if (task->data) { 2533 psgl++; 2534 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0); 2535 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0); 2536 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0); 2537 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0); 2538 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0); 2539 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2540 2541 psgl++; 2542 if (task->data) { 2543 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2544 lower_32_bits(io_task->mtask_addr)); 2545 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2546 upper_32_bits(io_task->mtask_addr)); 2547 } 2548 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106); 2549 } 2550 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2551 } 2552 2553 /** 2554 * beiscsi_find_mem_req()- Find mem needed 2555 * @phba: ptr to HBA struct 2556 **/ 2557 static void beiscsi_find_mem_req(struct beiscsi_hba *phba) 2558 { 2559 uint8_t mem_descr_index, ulp_num; 2560 unsigned int num_cq_pages, num_async_pdu_buf_pages; 2561 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn; 2562 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages; 2563 2564 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \ 2565 sizeof(struct sol_cqe)); 2566 2567 phba->params.hwi_ws_sz = sizeof(struct hwi_controller); 2568 2569 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 * 2570 BE_ISCSI_PDU_HEADER_SIZE; 2571 phba->mem_req[HWI_MEM_ADDN_CONTEXT] = 2572 sizeof(struct hwi_context_memory); 2573 2574 2575 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb) 2576 * (phba->params.wrbs_per_cxn) 2577 * phba->params.cxns_per_ctrl; 2578 wrb_sz_per_cxn = sizeof(struct wrb_handle) * 2579 (phba->params.wrbs_per_cxn); 2580 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) * 2581 phba->params.cxns_per_ctrl); 2582 2583 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) * 2584 phba->params.icds_per_ctrl; 2585 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) * 2586 phba->params.num_sge_per_io * phba->params.icds_per_ctrl; 2587 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 2588 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 2589 2590 num_async_pdu_buf_sgl_pages = 2591 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( 2592 phba, ulp_num) * 2593 sizeof(struct phys_addr)); 2594 2595 num_async_pdu_buf_pages = 2596 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( 2597 phba, ulp_num) * 2598 phba->params.defpdu_hdr_sz); 2599 2600 num_async_pdu_data_pages = 2601 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( 2602 phba, ulp_num) * 2603 phba->params.defpdu_data_sz); 2604 2605 num_async_pdu_data_sgl_pages = 2606 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( 2607 phba, ulp_num) * 2608 sizeof(struct phys_addr)); 2609 2610 mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 + 2611 (ulp_num * MEM_DESCR_OFFSET)); 2612 phba->mem_req[mem_descr_index] = 2613 BEISCSI_GET_CID_COUNT(phba, ulp_num) * 2614 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE; 2615 2616 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 + 2617 (ulp_num * MEM_DESCR_OFFSET)); 2618 phba->mem_req[mem_descr_index] = 2619 num_async_pdu_buf_pages * 2620 PAGE_SIZE; 2621 2622 mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 + 2623 (ulp_num * MEM_DESCR_OFFSET)); 2624 phba->mem_req[mem_descr_index] = 2625 num_async_pdu_data_pages * 2626 PAGE_SIZE; 2627 2628 mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 + 2629 (ulp_num * MEM_DESCR_OFFSET)); 2630 phba->mem_req[mem_descr_index] = 2631 num_async_pdu_buf_sgl_pages * 2632 PAGE_SIZE; 2633 2634 mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 + 2635 (ulp_num * MEM_DESCR_OFFSET)); 2636 phba->mem_req[mem_descr_index] = 2637 num_async_pdu_data_sgl_pages * 2638 PAGE_SIZE; 2639 2640 mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 + 2641 (ulp_num * MEM_DESCR_OFFSET)); 2642 phba->mem_req[mem_descr_index] = 2643 BEISCSI_GET_CID_COUNT(phba, ulp_num) * 2644 sizeof(struct async_pdu_handle); 2645 2646 mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 + 2647 (ulp_num * MEM_DESCR_OFFSET)); 2648 phba->mem_req[mem_descr_index] = 2649 BEISCSI_GET_CID_COUNT(phba, ulp_num) * 2650 sizeof(struct async_pdu_handle); 2651 2652 mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 + 2653 (ulp_num * MEM_DESCR_OFFSET)); 2654 phba->mem_req[mem_descr_index] = 2655 sizeof(struct hwi_async_pdu_context) + 2656 (BEISCSI_GET_CID_COUNT(phba, ulp_num) * 2657 sizeof(struct hwi_async_entry)); 2658 } 2659 } 2660 } 2661 2662 static int beiscsi_alloc_mem(struct beiscsi_hba *phba) 2663 { 2664 dma_addr_t bus_add; 2665 struct hwi_controller *phwi_ctrlr; 2666 struct be_mem_descriptor *mem_descr; 2667 struct mem_array *mem_arr, *mem_arr_orig; 2668 unsigned int i, j, alloc_size, curr_alloc_size; 2669 2670 phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL); 2671 if (!phba->phwi_ctrlr) 2672 return -ENOMEM; 2673 2674 /* Allocate memory for wrb_context */ 2675 phwi_ctrlr = phba->phwi_ctrlr; 2676 phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) * 2677 phba->params.cxns_per_ctrl, 2678 GFP_KERNEL); 2679 if (!phwi_ctrlr->wrb_context) 2680 return -ENOMEM; 2681 2682 phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr), 2683 GFP_KERNEL); 2684 if (!phba->init_mem) { 2685 kfree(phwi_ctrlr->wrb_context); 2686 kfree(phba->phwi_ctrlr); 2687 return -ENOMEM; 2688 } 2689 2690 mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT, 2691 GFP_KERNEL); 2692 if (!mem_arr_orig) { 2693 kfree(phba->init_mem); 2694 kfree(phwi_ctrlr->wrb_context); 2695 kfree(phba->phwi_ctrlr); 2696 return -ENOMEM; 2697 } 2698 2699 mem_descr = phba->init_mem; 2700 for (i = 0; i < SE_MEM_MAX; i++) { 2701 if (!phba->mem_req[i]) { 2702 mem_descr->mem_array = NULL; 2703 mem_descr++; 2704 continue; 2705 } 2706 2707 j = 0; 2708 mem_arr = mem_arr_orig; 2709 alloc_size = phba->mem_req[i]; 2710 memset(mem_arr, 0, sizeof(struct mem_array) * 2711 BEISCSI_MAX_FRAGS_INIT); 2712 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size); 2713 do { 2714 mem_arr->virtual_address = pci_alloc_consistent( 2715 phba->pcidev, 2716 curr_alloc_size, 2717 &bus_add); 2718 if (!mem_arr->virtual_address) { 2719 if (curr_alloc_size <= BE_MIN_MEM_SIZE) 2720 goto free_mem; 2721 if (curr_alloc_size - 2722 rounddown_pow_of_two(curr_alloc_size)) 2723 curr_alloc_size = rounddown_pow_of_two 2724 (curr_alloc_size); 2725 else 2726 curr_alloc_size = curr_alloc_size / 2; 2727 } else { 2728 mem_arr->bus_address.u. 2729 a64.address = (__u64) bus_add; 2730 mem_arr->size = curr_alloc_size; 2731 alloc_size -= curr_alloc_size; 2732 curr_alloc_size = min(be_max_phys_size * 2733 1024, alloc_size); 2734 j++; 2735 mem_arr++; 2736 } 2737 } while (alloc_size); 2738 mem_descr->num_elements = j; 2739 mem_descr->size_in_bytes = phba->mem_req[i]; 2740 mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j, 2741 GFP_KERNEL); 2742 if (!mem_descr->mem_array) 2743 goto free_mem; 2744 2745 memcpy(mem_descr->mem_array, mem_arr_orig, 2746 sizeof(struct mem_array) * j); 2747 mem_descr++; 2748 } 2749 kfree(mem_arr_orig); 2750 return 0; 2751 free_mem: 2752 mem_descr->num_elements = j; 2753 while ((i) || (j)) { 2754 for (j = mem_descr->num_elements; j > 0; j--) { 2755 pci_free_consistent(phba->pcidev, 2756 mem_descr->mem_array[j - 1].size, 2757 mem_descr->mem_array[j - 1]. 2758 virtual_address, 2759 (unsigned long)mem_descr-> 2760 mem_array[j - 1]. 2761 bus_address.u.a64.address); 2762 } 2763 if (i) { 2764 i--; 2765 kfree(mem_descr->mem_array); 2766 mem_descr--; 2767 } 2768 } 2769 kfree(mem_arr_orig); 2770 kfree(phba->init_mem); 2771 kfree(phba->phwi_ctrlr->wrb_context); 2772 kfree(phba->phwi_ctrlr); 2773 return -ENOMEM; 2774 } 2775 2776 static int beiscsi_get_memory(struct beiscsi_hba *phba) 2777 { 2778 beiscsi_find_mem_req(phba); 2779 return beiscsi_alloc_mem(phba); 2780 } 2781 2782 static void iscsi_init_global_templates(struct beiscsi_hba *phba) 2783 { 2784 struct pdu_data_out *pdata_out; 2785 struct pdu_nop_out *pnop_out; 2786 struct be_mem_descriptor *mem_descr; 2787 2788 mem_descr = phba->init_mem; 2789 mem_descr += ISCSI_MEM_GLOBAL_HEADER; 2790 pdata_out = 2791 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address; 2792 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE); 2793 2794 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out, 2795 IIOC_SCSI_DATA); 2796 2797 pnop_out = 2798 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0]. 2799 virtual_address + BE_ISCSI_PDU_HEADER_SIZE); 2800 2801 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE); 2802 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF); 2803 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1); 2804 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0); 2805 } 2806 2807 static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba) 2808 { 2809 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb; 2810 struct hwi_context_memory *phwi_ctxt; 2811 struct wrb_handle *pwrb_handle = NULL; 2812 struct hwi_controller *phwi_ctrlr; 2813 struct hwi_wrb_context *pwrb_context; 2814 struct iscsi_wrb *pwrb = NULL; 2815 unsigned int num_cxn_wrbh = 0; 2816 unsigned int num_cxn_wrb = 0, j, idx = 0, index; 2817 2818 mem_descr_wrbh = phba->init_mem; 2819 mem_descr_wrbh += HWI_MEM_WRBH; 2820 2821 mem_descr_wrb = phba->init_mem; 2822 mem_descr_wrb += HWI_MEM_WRB; 2823 phwi_ctrlr = phba->phwi_ctrlr; 2824 2825 /* Allocate memory for WRBQ */ 2826 phwi_ctxt = phwi_ctrlr->phwi_ctxt; 2827 phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) * 2828 phba->params.cxns_per_ctrl, 2829 GFP_KERNEL); 2830 if (!phwi_ctxt->be_wrbq) { 2831 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 2832 "BM_%d : WRBQ Mem Alloc Failed\n"); 2833 return -ENOMEM; 2834 } 2835 2836 for (index = 0; index < phba->params.cxns_per_ctrl; index++) { 2837 pwrb_context = &phwi_ctrlr->wrb_context[index]; 2838 pwrb_context->pwrb_handle_base = 2839 kzalloc(sizeof(struct wrb_handle *) * 2840 phba->params.wrbs_per_cxn, GFP_KERNEL); 2841 if (!pwrb_context->pwrb_handle_base) { 2842 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 2843 "BM_%d : Mem Alloc Failed. Failing to load\n"); 2844 goto init_wrb_hndl_failed; 2845 } 2846 pwrb_context->pwrb_handle_basestd = 2847 kzalloc(sizeof(struct wrb_handle *) * 2848 phba->params.wrbs_per_cxn, GFP_KERNEL); 2849 if (!pwrb_context->pwrb_handle_basestd) { 2850 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 2851 "BM_%d : Mem Alloc Failed. Failing to load\n"); 2852 goto init_wrb_hndl_failed; 2853 } 2854 if (!num_cxn_wrbh) { 2855 pwrb_handle = 2856 mem_descr_wrbh->mem_array[idx].virtual_address; 2857 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) / 2858 ((sizeof(struct wrb_handle)) * 2859 phba->params.wrbs_per_cxn)); 2860 idx++; 2861 } 2862 pwrb_context->alloc_index = 0; 2863 pwrb_context->wrb_handles_available = 0; 2864 pwrb_context->free_index = 0; 2865 2866 if (num_cxn_wrbh) { 2867 for (j = 0; j < phba->params.wrbs_per_cxn; j++) { 2868 pwrb_context->pwrb_handle_base[j] = pwrb_handle; 2869 pwrb_context->pwrb_handle_basestd[j] = 2870 pwrb_handle; 2871 pwrb_context->wrb_handles_available++; 2872 pwrb_handle->wrb_index = j; 2873 pwrb_handle++; 2874 } 2875 num_cxn_wrbh--; 2876 } 2877 } 2878 idx = 0; 2879 for (index = 0; index < phba->params.cxns_per_ctrl; index++) { 2880 pwrb_context = &phwi_ctrlr->wrb_context[index]; 2881 if (!num_cxn_wrb) { 2882 pwrb = mem_descr_wrb->mem_array[idx].virtual_address; 2883 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) / 2884 ((sizeof(struct iscsi_wrb) * 2885 phba->params.wrbs_per_cxn)); 2886 idx++; 2887 } 2888 2889 if (num_cxn_wrb) { 2890 for (j = 0; j < phba->params.wrbs_per_cxn; j++) { 2891 pwrb_handle = pwrb_context->pwrb_handle_base[j]; 2892 pwrb_handle->pwrb = pwrb; 2893 pwrb++; 2894 } 2895 num_cxn_wrb--; 2896 } 2897 } 2898 return 0; 2899 init_wrb_hndl_failed: 2900 for (j = index; j > 0; j--) { 2901 pwrb_context = &phwi_ctrlr->wrb_context[j]; 2902 kfree(pwrb_context->pwrb_handle_base); 2903 kfree(pwrb_context->pwrb_handle_basestd); 2904 } 2905 return -ENOMEM; 2906 } 2907 2908 static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba) 2909 { 2910 uint8_t ulp_num; 2911 struct hwi_controller *phwi_ctrlr; 2912 struct hba_parameters *p = &phba->params; 2913 struct hwi_async_pdu_context *pasync_ctx; 2914 struct async_pdu_handle *pasync_header_h, *pasync_data_h; 2915 unsigned int index, idx, num_per_mem, num_async_data; 2916 struct be_mem_descriptor *mem_descr; 2917 2918 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 2919 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 2920 2921 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2922 mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 + 2923 (ulp_num * MEM_DESCR_OFFSET)); 2924 2925 phwi_ctrlr = phba->phwi_ctrlr; 2926 phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] = 2927 (struct hwi_async_pdu_context *) 2928 mem_descr->mem_array[0].virtual_address; 2929 2930 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num]; 2931 memset(pasync_ctx, 0, sizeof(*pasync_ctx)); 2932 2933 pasync_ctx->async_entry = 2934 (struct hwi_async_entry *) 2935 ((long unsigned int)pasync_ctx + 2936 sizeof(struct hwi_async_pdu_context)); 2937 2938 pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba, 2939 ulp_num); 2940 pasync_ctx->buffer_size = p->defpdu_hdr_sz; 2941 2942 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2943 mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 + 2944 (ulp_num * MEM_DESCR_OFFSET); 2945 if (mem_descr->mem_array[0].virtual_address) { 2946 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2947 "BM_%d : hwi_init_async_pdu_ctx" 2948 " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n", 2949 ulp_num, 2950 mem_descr->mem_array[0]. 2951 virtual_address); 2952 } else 2953 beiscsi_log(phba, KERN_WARNING, 2954 BEISCSI_LOG_INIT, 2955 "BM_%d : No Virtual address for ULP : %d\n", 2956 ulp_num); 2957 2958 pasync_ctx->async_header.va_base = 2959 mem_descr->mem_array[0].virtual_address; 2960 2961 pasync_ctx->async_header.pa_base.u.a64.address = 2962 mem_descr->mem_array[0]. 2963 bus_address.u.a64.address; 2964 2965 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2966 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 + 2967 (ulp_num * MEM_DESCR_OFFSET); 2968 if (mem_descr->mem_array[0].virtual_address) { 2969 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2970 "BM_%d : hwi_init_async_pdu_ctx" 2971 " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n", 2972 ulp_num, 2973 mem_descr->mem_array[0]. 2974 virtual_address); 2975 } else 2976 beiscsi_log(phba, KERN_WARNING, 2977 BEISCSI_LOG_INIT, 2978 "BM_%d : No Virtual address for ULP : %d\n", 2979 ulp_num); 2980 2981 pasync_ctx->async_header.ring_base = 2982 mem_descr->mem_array[0].virtual_address; 2983 2984 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2985 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 + 2986 (ulp_num * MEM_DESCR_OFFSET); 2987 if (mem_descr->mem_array[0].virtual_address) { 2988 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2989 "BM_%d : hwi_init_async_pdu_ctx" 2990 " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n", 2991 ulp_num, 2992 mem_descr->mem_array[0]. 2993 virtual_address); 2994 } else 2995 beiscsi_log(phba, KERN_WARNING, 2996 BEISCSI_LOG_INIT, 2997 "BM_%d : No Virtual address for ULP : %d\n", 2998 ulp_num); 2999 3000 pasync_ctx->async_header.handle_base = 3001 mem_descr->mem_array[0].virtual_address; 3002 pasync_ctx->async_header.writables = 0; 3003 INIT_LIST_HEAD(&pasync_ctx->async_header.free_list); 3004 3005 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 3006 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 + 3007 (ulp_num * MEM_DESCR_OFFSET); 3008 if (mem_descr->mem_array[0].virtual_address) { 3009 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3010 "BM_%d : hwi_init_async_pdu_ctx" 3011 " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n", 3012 ulp_num, 3013 mem_descr->mem_array[0]. 3014 virtual_address); 3015 } else 3016 beiscsi_log(phba, KERN_WARNING, 3017 BEISCSI_LOG_INIT, 3018 "BM_%d : No Virtual address for ULP : %d\n", 3019 ulp_num); 3020 3021 pasync_ctx->async_data.ring_base = 3022 mem_descr->mem_array[0].virtual_address; 3023 3024 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 3025 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 + 3026 (ulp_num * MEM_DESCR_OFFSET); 3027 if (!mem_descr->mem_array[0].virtual_address) 3028 beiscsi_log(phba, KERN_WARNING, 3029 BEISCSI_LOG_INIT, 3030 "BM_%d : No Virtual address for ULP : %d\n", 3031 ulp_num); 3032 3033 pasync_ctx->async_data.handle_base = 3034 mem_descr->mem_array[0].virtual_address; 3035 pasync_ctx->async_data.writables = 0; 3036 INIT_LIST_HEAD(&pasync_ctx->async_data.free_list); 3037 3038 pasync_header_h = 3039 (struct async_pdu_handle *) 3040 pasync_ctx->async_header.handle_base; 3041 pasync_data_h = 3042 (struct async_pdu_handle *) 3043 pasync_ctx->async_data.handle_base; 3044 3045 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 3046 mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 + 3047 (ulp_num * MEM_DESCR_OFFSET); 3048 if (mem_descr->mem_array[0].virtual_address) { 3049 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3050 "BM_%d : hwi_init_async_pdu_ctx" 3051 " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n", 3052 ulp_num, 3053 mem_descr->mem_array[0]. 3054 virtual_address); 3055 } else 3056 beiscsi_log(phba, KERN_WARNING, 3057 BEISCSI_LOG_INIT, 3058 "BM_%d : No Virtual address for ULP : %d\n", 3059 ulp_num); 3060 3061 idx = 0; 3062 pasync_ctx->async_data.va_base = 3063 mem_descr->mem_array[idx].virtual_address; 3064 pasync_ctx->async_data.pa_base.u.a64.address = 3065 mem_descr->mem_array[idx]. 3066 bus_address.u.a64.address; 3067 3068 num_async_data = ((mem_descr->mem_array[idx].size) / 3069 phba->params.defpdu_data_sz); 3070 num_per_mem = 0; 3071 3072 for (index = 0; index < BEISCSI_GET_CID_COUNT 3073 (phba, ulp_num); index++) { 3074 pasync_header_h->cri = -1; 3075 pasync_header_h->index = (char)index; 3076 INIT_LIST_HEAD(&pasync_header_h->link); 3077 pasync_header_h->pbuffer = 3078 (void *)((unsigned long) 3079 (pasync_ctx-> 3080 async_header.va_base) + 3081 (p->defpdu_hdr_sz * index)); 3082 3083 pasync_header_h->pa.u.a64.address = 3084 pasync_ctx->async_header.pa_base.u.a64. 3085 address + (p->defpdu_hdr_sz * index); 3086 3087 list_add_tail(&pasync_header_h->link, 3088 &pasync_ctx->async_header. 3089 free_list); 3090 pasync_header_h++; 3091 pasync_ctx->async_header.free_entries++; 3092 pasync_ctx->async_header.writables++; 3093 3094 INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. 3095 wait_queue.list); 3096 INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. 3097 header_busy_list); 3098 pasync_data_h->cri = -1; 3099 pasync_data_h->index = (char)index; 3100 INIT_LIST_HEAD(&pasync_data_h->link); 3101 3102 if (!num_async_data) { 3103 num_per_mem = 0; 3104 idx++; 3105 pasync_ctx->async_data.va_base = 3106 mem_descr->mem_array[idx]. 3107 virtual_address; 3108 pasync_ctx->async_data.pa_base.u. 3109 a64.address = 3110 mem_descr->mem_array[idx]. 3111 bus_address.u.a64.address; 3112 num_async_data = 3113 ((mem_descr->mem_array[idx]. 3114 size) / 3115 phba->params.defpdu_data_sz); 3116 } 3117 pasync_data_h->pbuffer = 3118 (void *)((unsigned long) 3119 (pasync_ctx->async_data.va_base) + 3120 (p->defpdu_data_sz * num_per_mem)); 3121 3122 pasync_data_h->pa.u.a64.address = 3123 pasync_ctx->async_data.pa_base.u.a64. 3124 address + (p->defpdu_data_sz * 3125 num_per_mem); 3126 num_per_mem++; 3127 num_async_data--; 3128 3129 list_add_tail(&pasync_data_h->link, 3130 &pasync_ctx->async_data. 3131 free_list); 3132 pasync_data_h++; 3133 pasync_ctx->async_data.free_entries++; 3134 pasync_ctx->async_data.writables++; 3135 3136 INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. 3137 data_busy_list); 3138 } 3139 3140 pasync_ctx->async_header.host_write_ptr = 0; 3141 pasync_ctx->async_header.ep_read_ptr = -1; 3142 pasync_ctx->async_data.host_write_ptr = 0; 3143 pasync_ctx->async_data.ep_read_ptr = -1; 3144 } 3145 } 3146 3147 return 0; 3148 } 3149 3150 static int 3151 be_sgl_create_contiguous(void *virtual_address, 3152 u64 physical_address, u32 length, 3153 struct be_dma_mem *sgl) 3154 { 3155 WARN_ON(!virtual_address); 3156 WARN_ON(!physical_address); 3157 WARN_ON(!length > 0); 3158 WARN_ON(!sgl); 3159 3160 sgl->va = virtual_address; 3161 sgl->dma = (unsigned long)physical_address; 3162 sgl->size = length; 3163 3164 return 0; 3165 } 3166 3167 static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl) 3168 { 3169 memset(sgl, 0, sizeof(*sgl)); 3170 } 3171 3172 static void 3173 hwi_build_be_sgl_arr(struct beiscsi_hba *phba, 3174 struct mem_array *pmem, struct be_dma_mem *sgl) 3175 { 3176 if (sgl->va) 3177 be_sgl_destroy_contiguous(sgl); 3178 3179 be_sgl_create_contiguous(pmem->virtual_address, 3180 pmem->bus_address.u.a64.address, 3181 pmem->size, sgl); 3182 } 3183 3184 static void 3185 hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba, 3186 struct mem_array *pmem, struct be_dma_mem *sgl) 3187 { 3188 if (sgl->va) 3189 be_sgl_destroy_contiguous(sgl); 3190 3191 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address, 3192 pmem->bus_address.u.a64.address, 3193 pmem->size, sgl); 3194 } 3195 3196 static int be_fill_queue(struct be_queue_info *q, 3197 u16 len, u16 entry_size, void *vaddress) 3198 { 3199 struct be_dma_mem *mem = &q->dma_mem; 3200 3201 memset(q, 0, sizeof(*q)); 3202 q->len = len; 3203 q->entry_size = entry_size; 3204 mem->size = len * entry_size; 3205 mem->va = vaddress; 3206 if (!mem->va) 3207 return -ENOMEM; 3208 memset(mem->va, 0, mem->size); 3209 return 0; 3210 } 3211 3212 static int beiscsi_create_eqs(struct beiscsi_hba *phba, 3213 struct hwi_context_memory *phwi_context) 3214 { 3215 unsigned int i, num_eq_pages; 3216 int ret = 0, eq_for_mcc; 3217 struct be_queue_info *eq; 3218 struct be_dma_mem *mem; 3219 void *eq_vaddress; 3220 dma_addr_t paddr; 3221 3222 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \ 3223 sizeof(struct be_eq_entry)); 3224 3225 if (phba->msix_enabled) 3226 eq_for_mcc = 1; 3227 else 3228 eq_for_mcc = 0; 3229 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { 3230 eq = &phwi_context->be_eq[i].q; 3231 mem = &eq->dma_mem; 3232 phwi_context->be_eq[i].phba = phba; 3233 eq_vaddress = pci_alloc_consistent(phba->pcidev, 3234 num_eq_pages * PAGE_SIZE, 3235 &paddr); 3236 if (!eq_vaddress) 3237 goto create_eq_error; 3238 3239 mem->va = eq_vaddress; 3240 ret = be_fill_queue(eq, phba->params.num_eq_entries, 3241 sizeof(struct be_eq_entry), eq_vaddress); 3242 if (ret) { 3243 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3244 "BM_%d : be_fill_queue Failed for EQ\n"); 3245 goto create_eq_error; 3246 } 3247 3248 mem->dma = paddr; 3249 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq, 3250 phwi_context->cur_eqd); 3251 if (ret) { 3252 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3253 "BM_%d : beiscsi_cmd_eq_create" 3254 "Failed for EQ\n"); 3255 goto create_eq_error; 3256 } 3257 3258 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3259 "BM_%d : eqid = %d\n", 3260 phwi_context->be_eq[i].q.id); 3261 } 3262 return 0; 3263 create_eq_error: 3264 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { 3265 eq = &phwi_context->be_eq[i].q; 3266 mem = &eq->dma_mem; 3267 if (mem->va) 3268 pci_free_consistent(phba->pcidev, num_eq_pages 3269 * PAGE_SIZE, 3270 mem->va, mem->dma); 3271 } 3272 return ret; 3273 } 3274 3275 static int beiscsi_create_cqs(struct beiscsi_hba *phba, 3276 struct hwi_context_memory *phwi_context) 3277 { 3278 unsigned int i, num_cq_pages; 3279 int ret = 0; 3280 struct be_queue_info *cq, *eq; 3281 struct be_dma_mem *mem; 3282 struct be_eq_obj *pbe_eq; 3283 void *cq_vaddress; 3284 dma_addr_t paddr; 3285 3286 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \ 3287 sizeof(struct sol_cqe)); 3288 3289 for (i = 0; i < phba->num_cpus; i++) { 3290 cq = &phwi_context->be_cq[i]; 3291 eq = &phwi_context->be_eq[i].q; 3292 pbe_eq = &phwi_context->be_eq[i]; 3293 pbe_eq->cq = cq; 3294 pbe_eq->phba = phba; 3295 mem = &cq->dma_mem; 3296 cq_vaddress = pci_alloc_consistent(phba->pcidev, 3297 num_cq_pages * PAGE_SIZE, 3298 &paddr); 3299 if (!cq_vaddress) 3300 goto create_cq_error; 3301 ret = be_fill_queue(cq, phba->params.num_cq_entries, 3302 sizeof(struct sol_cqe), cq_vaddress); 3303 if (ret) { 3304 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3305 "BM_%d : be_fill_queue Failed " 3306 "for ISCSI CQ\n"); 3307 goto create_cq_error; 3308 } 3309 3310 mem->dma = paddr; 3311 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false, 3312 false, 0); 3313 if (ret) { 3314 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3315 "BM_%d : beiscsi_cmd_eq_create" 3316 "Failed for ISCSI CQ\n"); 3317 goto create_cq_error; 3318 } 3319 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3320 "BM_%d : iscsi cq_id is %d for eq_id %d\n" 3321 "iSCSI CQ CREATED\n", cq->id, eq->id); 3322 } 3323 return 0; 3324 3325 create_cq_error: 3326 for (i = 0; i < phba->num_cpus; i++) { 3327 cq = &phwi_context->be_cq[i]; 3328 mem = &cq->dma_mem; 3329 if (mem->va) 3330 pci_free_consistent(phba->pcidev, num_cq_pages 3331 * PAGE_SIZE, 3332 mem->va, mem->dma); 3333 } 3334 return ret; 3335 3336 } 3337 3338 static int 3339 beiscsi_create_def_hdr(struct beiscsi_hba *phba, 3340 struct hwi_context_memory *phwi_context, 3341 struct hwi_controller *phwi_ctrlr, 3342 unsigned int def_pdu_ring_sz, uint8_t ulp_num) 3343 { 3344 unsigned int idx; 3345 int ret; 3346 struct be_queue_info *dq, *cq; 3347 struct be_dma_mem *mem; 3348 struct be_mem_descriptor *mem_descr; 3349 void *dq_vaddress; 3350 3351 idx = 0; 3352 dq = &phwi_context->be_def_hdrq[ulp_num]; 3353 cq = &phwi_context->be_cq[0]; 3354 mem = &dq->dma_mem; 3355 mem_descr = phba->init_mem; 3356 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 + 3357 (ulp_num * MEM_DESCR_OFFSET); 3358 dq_vaddress = mem_descr->mem_array[idx].virtual_address; 3359 ret = be_fill_queue(dq, mem_descr->mem_array[0].size / 3360 sizeof(struct phys_addr), 3361 sizeof(struct phys_addr), dq_vaddress); 3362 if (ret) { 3363 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3364 "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n", 3365 ulp_num); 3366 3367 return ret; 3368 } 3369 mem->dma = (unsigned long)mem_descr->mem_array[idx]. 3370 bus_address.u.a64.address; 3371 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq, 3372 def_pdu_ring_sz, 3373 phba->params.defpdu_hdr_sz, 3374 BEISCSI_DEFQ_HDR, ulp_num); 3375 if (ret) { 3376 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3377 "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n", 3378 ulp_num); 3379 3380 return ret; 3381 } 3382 3383 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3384 "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n", 3385 ulp_num, 3386 phwi_context->be_def_hdrq[ulp_num].id); 3387 hwi_post_async_buffers(phba, BEISCSI_DEFQ_HDR, ulp_num); 3388 return 0; 3389 } 3390 3391 static int 3392 beiscsi_create_def_data(struct beiscsi_hba *phba, 3393 struct hwi_context_memory *phwi_context, 3394 struct hwi_controller *phwi_ctrlr, 3395 unsigned int def_pdu_ring_sz, uint8_t ulp_num) 3396 { 3397 unsigned int idx; 3398 int ret; 3399 struct be_queue_info *dataq, *cq; 3400 struct be_dma_mem *mem; 3401 struct be_mem_descriptor *mem_descr; 3402 void *dq_vaddress; 3403 3404 idx = 0; 3405 dataq = &phwi_context->be_def_dataq[ulp_num]; 3406 cq = &phwi_context->be_cq[0]; 3407 mem = &dataq->dma_mem; 3408 mem_descr = phba->init_mem; 3409 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 + 3410 (ulp_num * MEM_DESCR_OFFSET); 3411 dq_vaddress = mem_descr->mem_array[idx].virtual_address; 3412 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size / 3413 sizeof(struct phys_addr), 3414 sizeof(struct phys_addr), dq_vaddress); 3415 if (ret) { 3416 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3417 "BM_%d : be_fill_queue Failed for DEF PDU " 3418 "DATA on ULP : %d\n", 3419 ulp_num); 3420 3421 return ret; 3422 } 3423 mem->dma = (unsigned long)mem_descr->mem_array[idx]. 3424 bus_address.u.a64.address; 3425 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq, 3426 def_pdu_ring_sz, 3427 phba->params.defpdu_data_sz, 3428 BEISCSI_DEFQ_DATA, ulp_num); 3429 if (ret) { 3430 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3431 "BM_%d be_cmd_create_default_pdu_queue" 3432 " Failed for DEF PDU DATA on ULP : %d\n", 3433 ulp_num); 3434 return ret; 3435 } 3436 3437 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3438 "BM_%d : iscsi def data id on ULP : %d is %d\n", 3439 ulp_num, 3440 phwi_context->be_def_dataq[ulp_num].id); 3441 3442 hwi_post_async_buffers(phba, BEISCSI_DEFQ_DATA, ulp_num); 3443 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3444 "BM_%d : DEFAULT PDU DATA RING CREATED" 3445 "on ULP : %d\n", ulp_num); 3446 3447 return 0; 3448 } 3449 3450 3451 static int 3452 beiscsi_post_template_hdr(struct beiscsi_hba *phba) 3453 { 3454 struct be_mem_descriptor *mem_descr; 3455 struct mem_array *pm_arr; 3456 struct be_dma_mem sgl; 3457 int status, ulp_num; 3458 3459 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3460 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3461 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 3462 mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 + 3463 (ulp_num * MEM_DESCR_OFFSET); 3464 pm_arr = mem_descr->mem_array; 3465 3466 hwi_build_be_sgl_arr(phba, pm_arr, &sgl); 3467 status = be_cmd_iscsi_post_template_hdr( 3468 &phba->ctrl, &sgl); 3469 3470 if (status != 0) { 3471 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3472 "BM_%d : Post Template HDR Failed for" 3473 "ULP_%d\n", ulp_num); 3474 return status; 3475 } 3476 3477 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3478 "BM_%d : Template HDR Pages Posted for" 3479 "ULP_%d\n", ulp_num); 3480 } 3481 } 3482 return 0; 3483 } 3484 3485 static int 3486 beiscsi_post_pages(struct beiscsi_hba *phba) 3487 { 3488 struct be_mem_descriptor *mem_descr; 3489 struct mem_array *pm_arr; 3490 unsigned int page_offset, i; 3491 struct be_dma_mem sgl; 3492 int status, ulp_num = 0; 3493 3494 mem_descr = phba->init_mem; 3495 mem_descr += HWI_MEM_SGE; 3496 pm_arr = mem_descr->mem_array; 3497 3498 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 3499 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) 3500 break; 3501 3502 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io * 3503 phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE; 3504 for (i = 0; i < mem_descr->num_elements; i++) { 3505 hwi_build_be_sgl_arr(phba, pm_arr, &sgl); 3506 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl, 3507 page_offset, 3508 (pm_arr->size / PAGE_SIZE)); 3509 page_offset += pm_arr->size / PAGE_SIZE; 3510 if (status != 0) { 3511 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3512 "BM_%d : post sgl failed.\n"); 3513 return status; 3514 } 3515 pm_arr++; 3516 } 3517 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3518 "BM_%d : POSTED PAGES\n"); 3519 return 0; 3520 } 3521 3522 static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q) 3523 { 3524 struct be_dma_mem *mem = &q->dma_mem; 3525 if (mem->va) { 3526 pci_free_consistent(phba->pcidev, mem->size, 3527 mem->va, mem->dma); 3528 mem->va = NULL; 3529 } 3530 } 3531 3532 static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q, 3533 u16 len, u16 entry_size) 3534 { 3535 struct be_dma_mem *mem = &q->dma_mem; 3536 3537 memset(q, 0, sizeof(*q)); 3538 q->len = len; 3539 q->entry_size = entry_size; 3540 mem->size = len * entry_size; 3541 mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma); 3542 if (!mem->va) 3543 return -ENOMEM; 3544 memset(mem->va, 0, mem->size); 3545 return 0; 3546 } 3547 3548 static int 3549 beiscsi_create_wrb_rings(struct beiscsi_hba *phba, 3550 struct hwi_context_memory *phwi_context, 3551 struct hwi_controller *phwi_ctrlr) 3552 { 3553 unsigned int wrb_mem_index, offset, size, num_wrb_rings; 3554 u64 pa_addr_lo; 3555 unsigned int idx, num, i, ulp_num; 3556 struct mem_array *pwrb_arr; 3557 void *wrb_vaddr; 3558 struct be_dma_mem sgl; 3559 struct be_mem_descriptor *mem_descr; 3560 struct hwi_wrb_context *pwrb_context; 3561 int status; 3562 uint8_t ulp_count = 0, ulp_base_num = 0; 3563 uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 }; 3564 3565 idx = 0; 3566 mem_descr = phba->init_mem; 3567 mem_descr += HWI_MEM_WRB; 3568 pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl, 3569 GFP_KERNEL); 3570 if (!pwrb_arr) { 3571 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3572 "BM_%d : Memory alloc failed in create wrb ring.\n"); 3573 return -ENOMEM; 3574 } 3575 wrb_vaddr = mem_descr->mem_array[idx].virtual_address; 3576 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address; 3577 num_wrb_rings = mem_descr->mem_array[idx].size / 3578 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb)); 3579 3580 for (num = 0; num < phba->params.cxns_per_ctrl; num++) { 3581 if (num_wrb_rings) { 3582 pwrb_arr[num].virtual_address = wrb_vaddr; 3583 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo; 3584 pwrb_arr[num].size = phba->params.wrbs_per_cxn * 3585 sizeof(struct iscsi_wrb); 3586 wrb_vaddr += pwrb_arr[num].size; 3587 pa_addr_lo += pwrb_arr[num].size; 3588 num_wrb_rings--; 3589 } else { 3590 idx++; 3591 wrb_vaddr = mem_descr->mem_array[idx].virtual_address; 3592 pa_addr_lo = mem_descr->mem_array[idx].\ 3593 bus_address.u.a64.address; 3594 num_wrb_rings = mem_descr->mem_array[idx].size / 3595 (phba->params.wrbs_per_cxn * 3596 sizeof(struct iscsi_wrb)); 3597 pwrb_arr[num].virtual_address = wrb_vaddr; 3598 pwrb_arr[num].bus_address.u.a64.address\ 3599 = pa_addr_lo; 3600 pwrb_arr[num].size = phba->params.wrbs_per_cxn * 3601 sizeof(struct iscsi_wrb); 3602 wrb_vaddr += pwrb_arr[num].size; 3603 pa_addr_lo += pwrb_arr[num].size; 3604 num_wrb_rings--; 3605 } 3606 } 3607 3608 /* Get the ULP Count */ 3609 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 3610 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3611 ulp_count++; 3612 ulp_base_num = ulp_num; 3613 cid_count_ulp[ulp_num] = 3614 BEISCSI_GET_CID_COUNT(phba, ulp_num); 3615 } 3616 3617 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 3618 wrb_mem_index = 0; 3619 offset = 0; 3620 size = 0; 3621 3622 if (ulp_count > 1) { 3623 ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT; 3624 3625 if (!cid_count_ulp[ulp_base_num]) 3626 ulp_base_num = (ulp_base_num + 1) % 3627 BEISCSI_ULP_COUNT; 3628 3629 cid_count_ulp[ulp_base_num]--; 3630 } 3631 3632 3633 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl); 3634 status = be_cmd_wrbq_create(&phba->ctrl, &sgl, 3635 &phwi_context->be_wrbq[i], 3636 &phwi_ctrlr->wrb_context[i], 3637 ulp_base_num); 3638 if (status != 0) { 3639 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3640 "BM_%d : wrbq create failed."); 3641 kfree(pwrb_arr); 3642 return status; 3643 } 3644 pwrb_context = &phwi_ctrlr->wrb_context[i]; 3645 BE_SET_CID_TO_CRI(i, pwrb_context->cid); 3646 } 3647 kfree(pwrb_arr); 3648 return 0; 3649 } 3650 3651 static void free_wrb_handles(struct beiscsi_hba *phba) 3652 { 3653 unsigned int index; 3654 struct hwi_controller *phwi_ctrlr; 3655 struct hwi_wrb_context *pwrb_context; 3656 3657 phwi_ctrlr = phba->phwi_ctrlr; 3658 for (index = 0; index < phba->params.cxns_per_ctrl; index++) { 3659 pwrb_context = &phwi_ctrlr->wrb_context[index]; 3660 kfree(pwrb_context->pwrb_handle_base); 3661 kfree(pwrb_context->pwrb_handle_basestd); 3662 } 3663 } 3664 3665 static void be_mcc_queues_destroy(struct beiscsi_hba *phba) 3666 { 3667 struct be_queue_info *q; 3668 struct be_ctrl_info *ctrl = &phba->ctrl; 3669 3670 q = &phba->ctrl.mcc_obj.q; 3671 if (q->created) 3672 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ); 3673 be_queue_free(phba, q); 3674 3675 q = &phba->ctrl.mcc_obj.cq; 3676 if (q->created) 3677 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); 3678 be_queue_free(phba, q); 3679 } 3680 3681 static void hwi_cleanup(struct beiscsi_hba *phba) 3682 { 3683 struct be_queue_info *q; 3684 struct be_ctrl_info *ctrl = &phba->ctrl; 3685 struct hwi_controller *phwi_ctrlr; 3686 struct hwi_context_memory *phwi_context; 3687 struct hwi_async_pdu_context *pasync_ctx; 3688 int i, eq_for_mcc, ulp_num; 3689 3690 phwi_ctrlr = phba->phwi_ctrlr; 3691 phwi_context = phwi_ctrlr->phwi_ctxt; 3692 3693 be_cmd_iscsi_remove_template_hdr(ctrl); 3694 3695 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 3696 q = &phwi_context->be_wrbq[i]; 3697 if (q->created) 3698 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ); 3699 } 3700 kfree(phwi_context->be_wrbq); 3701 free_wrb_handles(phba); 3702 3703 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3704 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3705 3706 q = &phwi_context->be_def_hdrq[ulp_num]; 3707 if (q->created) 3708 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); 3709 3710 q = &phwi_context->be_def_dataq[ulp_num]; 3711 if (q->created) 3712 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); 3713 3714 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num]; 3715 } 3716 } 3717 3718 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); 3719 3720 for (i = 0; i < (phba->num_cpus); i++) { 3721 q = &phwi_context->be_cq[i]; 3722 if (q->created) 3723 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); 3724 } 3725 3726 be_mcc_queues_destroy(phba); 3727 if (phba->msix_enabled) 3728 eq_for_mcc = 1; 3729 else 3730 eq_for_mcc = 0; 3731 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { 3732 q = &phwi_context->be_eq[i].q; 3733 if (q->created) 3734 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ); 3735 } 3736 be_cmd_fw_uninit(ctrl); 3737 } 3738 3739 static int be_mcc_queues_create(struct beiscsi_hba *phba, 3740 struct hwi_context_memory *phwi_context) 3741 { 3742 struct be_queue_info *q, *cq; 3743 struct be_ctrl_info *ctrl = &phba->ctrl; 3744 3745 /* Alloc MCC compl queue */ 3746 cq = &phba->ctrl.mcc_obj.cq; 3747 if (be_queue_alloc(phba, cq, MCC_CQ_LEN, 3748 sizeof(struct be_mcc_compl))) 3749 goto err; 3750 /* Ask BE to create MCC compl queue; */ 3751 if (phba->msix_enabled) { 3752 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq 3753 [phba->num_cpus].q, false, true, 0)) 3754 goto mcc_cq_free; 3755 } else { 3756 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q, 3757 false, true, 0)) 3758 goto mcc_cq_free; 3759 } 3760 3761 /* Alloc MCC queue */ 3762 q = &phba->ctrl.mcc_obj.q; 3763 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb))) 3764 goto mcc_cq_destroy; 3765 3766 /* Ask BE to create MCC queue */ 3767 if (beiscsi_cmd_mccq_create(phba, q, cq)) 3768 goto mcc_q_free; 3769 3770 return 0; 3771 3772 mcc_q_free: 3773 be_queue_free(phba, q); 3774 mcc_cq_destroy: 3775 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ); 3776 mcc_cq_free: 3777 be_queue_free(phba, cq); 3778 err: 3779 return -ENOMEM; 3780 } 3781 3782 /** 3783 * find_num_cpus()- Get the CPU online count 3784 * @phba: ptr to priv structure 3785 * 3786 * CPU count is used for creating EQ. 3787 **/ 3788 static void find_num_cpus(struct beiscsi_hba *phba) 3789 { 3790 int num_cpus = 0; 3791 3792 num_cpus = num_online_cpus(); 3793 3794 switch (phba->generation) { 3795 case BE_GEN2: 3796 case BE_GEN3: 3797 phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ? 3798 BEISCSI_MAX_NUM_CPUS : num_cpus; 3799 break; 3800 case BE_GEN4: 3801 /* 3802 * If eqid_count == 1 fall back to 3803 * INTX mechanism 3804 **/ 3805 if (phba->fw_config.eqid_count == 1) { 3806 enable_msix = 0; 3807 phba->num_cpus = 1; 3808 return; 3809 } 3810 3811 phba->num_cpus = 3812 (num_cpus > (phba->fw_config.eqid_count - 1)) ? 3813 (phba->fw_config.eqid_count - 1) : num_cpus; 3814 break; 3815 default: 3816 phba->num_cpus = 1; 3817 } 3818 } 3819 3820 static int hwi_init_port(struct beiscsi_hba *phba) 3821 { 3822 struct hwi_controller *phwi_ctrlr; 3823 struct hwi_context_memory *phwi_context; 3824 unsigned int def_pdu_ring_sz; 3825 struct be_ctrl_info *ctrl = &phba->ctrl; 3826 int status, ulp_num; 3827 3828 phwi_ctrlr = phba->phwi_ctrlr; 3829 phwi_context = phwi_ctrlr->phwi_ctxt; 3830 phwi_context->max_eqd = 128; 3831 phwi_context->min_eqd = 0; 3832 phwi_context->cur_eqd = 0; 3833 be_cmd_fw_initialize(&phba->ctrl); 3834 3835 status = beiscsi_create_eqs(phba, phwi_context); 3836 if (status != 0) { 3837 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3838 "BM_%d : EQ not created\n"); 3839 goto error; 3840 } 3841 3842 status = be_mcc_queues_create(phba, phwi_context); 3843 if (status != 0) 3844 goto error; 3845 3846 status = mgmt_check_supported_fw(ctrl, phba); 3847 if (status != 0) { 3848 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3849 "BM_%d : Unsupported fw version\n"); 3850 goto error; 3851 } 3852 3853 status = beiscsi_create_cqs(phba, phwi_context); 3854 if (status != 0) { 3855 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3856 "BM_%d : CQ not created\n"); 3857 goto error; 3858 } 3859 3860 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3861 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3862 3863 def_pdu_ring_sz = 3864 BEISCSI_GET_CID_COUNT(phba, ulp_num) * 3865 sizeof(struct phys_addr); 3866 3867 status = beiscsi_create_def_hdr(phba, phwi_context, 3868 phwi_ctrlr, 3869 def_pdu_ring_sz, 3870 ulp_num); 3871 if (status != 0) { 3872 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3873 "BM_%d : Default Header not created for ULP : %d\n", 3874 ulp_num); 3875 goto error; 3876 } 3877 3878 status = beiscsi_create_def_data(phba, phwi_context, 3879 phwi_ctrlr, 3880 def_pdu_ring_sz, 3881 ulp_num); 3882 if (status != 0) { 3883 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3884 "BM_%d : Default Data not created for ULP : %d\n", 3885 ulp_num); 3886 goto error; 3887 } 3888 } 3889 } 3890 3891 status = beiscsi_post_pages(phba); 3892 if (status != 0) { 3893 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3894 "BM_%d : Post SGL Pages Failed\n"); 3895 goto error; 3896 } 3897 3898 status = beiscsi_post_template_hdr(phba); 3899 if (status != 0) { 3900 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3901 "BM_%d : Template HDR Posting for CXN Failed\n"); 3902 } 3903 3904 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr); 3905 if (status != 0) { 3906 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3907 "BM_%d : WRB Rings not created\n"); 3908 goto error; 3909 } 3910 3911 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3912 uint16_t async_arr_idx = 0; 3913 3914 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3915 uint16_t cri = 0; 3916 struct hwi_async_pdu_context *pasync_ctx; 3917 3918 pasync_ctx = HWI_GET_ASYNC_PDU_CTX( 3919 phwi_ctrlr, ulp_num); 3920 for (cri = 0; cri < 3921 phba->params.cxns_per_ctrl; cri++) { 3922 if (ulp_num == BEISCSI_GET_ULP_FROM_CRI 3923 (phwi_ctrlr, cri)) 3924 pasync_ctx->cid_to_async_cri_map[ 3925 phwi_ctrlr->wrb_context[cri].cid] = 3926 async_arr_idx++; 3927 } 3928 } 3929 } 3930 3931 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3932 "BM_%d : hwi_init_port success\n"); 3933 return 0; 3934 3935 error: 3936 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3937 "BM_%d : hwi_init_port failed"); 3938 hwi_cleanup(phba); 3939 return status; 3940 } 3941 3942 static int hwi_init_controller(struct beiscsi_hba *phba) 3943 { 3944 struct hwi_controller *phwi_ctrlr; 3945 3946 phwi_ctrlr = phba->phwi_ctrlr; 3947 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) { 3948 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba-> 3949 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address; 3950 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3951 "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n", 3952 phwi_ctrlr->phwi_ctxt); 3953 } else { 3954 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3955 "BM_%d : HWI_MEM_ADDN_CONTEXT is more " 3956 "than one element.Failing to load\n"); 3957 return -ENOMEM; 3958 } 3959 3960 iscsi_init_global_templates(phba); 3961 if (beiscsi_init_wrb_handle(phba)) 3962 return -ENOMEM; 3963 3964 if (hwi_init_async_pdu_ctx(phba)) { 3965 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3966 "BM_%d : hwi_init_async_pdu_ctx failed\n"); 3967 return -ENOMEM; 3968 } 3969 3970 if (hwi_init_port(phba) != 0) { 3971 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3972 "BM_%d : hwi_init_controller failed\n"); 3973 3974 return -ENOMEM; 3975 } 3976 return 0; 3977 } 3978 3979 static void beiscsi_free_mem(struct beiscsi_hba *phba) 3980 { 3981 struct be_mem_descriptor *mem_descr; 3982 int i, j; 3983 3984 mem_descr = phba->init_mem; 3985 i = 0; 3986 j = 0; 3987 for (i = 0; i < SE_MEM_MAX; i++) { 3988 for (j = mem_descr->num_elements; j > 0; j--) { 3989 pci_free_consistent(phba->pcidev, 3990 mem_descr->mem_array[j - 1].size, 3991 mem_descr->mem_array[j - 1].virtual_address, 3992 (unsigned long)mem_descr->mem_array[j - 1]. 3993 bus_address.u.a64.address); 3994 } 3995 3996 kfree(mem_descr->mem_array); 3997 mem_descr++; 3998 } 3999 kfree(phba->init_mem); 4000 kfree(phba->phwi_ctrlr->wrb_context); 4001 kfree(phba->phwi_ctrlr); 4002 } 4003 4004 static int beiscsi_init_controller(struct beiscsi_hba *phba) 4005 { 4006 int ret = -ENOMEM; 4007 4008 ret = beiscsi_get_memory(phba); 4009 if (ret < 0) { 4010 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4011 "BM_%d : beiscsi_dev_probe -" 4012 "Failed in beiscsi_alloc_memory\n"); 4013 return ret; 4014 } 4015 4016 ret = hwi_init_controller(phba); 4017 if (ret) 4018 goto free_init; 4019 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4020 "BM_%d : Return success from beiscsi_init_controller"); 4021 4022 return 0; 4023 4024 free_init: 4025 beiscsi_free_mem(phba); 4026 return ret; 4027 } 4028 4029 static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba) 4030 { 4031 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg; 4032 struct sgl_handle *psgl_handle; 4033 struct iscsi_sge *pfrag; 4034 unsigned int arr_index, i, idx; 4035 unsigned int ulp_icd_start, ulp_num = 0; 4036 4037 phba->io_sgl_hndl_avbl = 0; 4038 phba->eh_sgl_hndl_avbl = 0; 4039 4040 mem_descr_sglh = phba->init_mem; 4041 mem_descr_sglh += HWI_MEM_SGLH; 4042 if (1 == mem_descr_sglh->num_elements) { 4043 phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) * 4044 phba->params.ios_per_ctrl, 4045 GFP_KERNEL); 4046 if (!phba->io_sgl_hndl_base) { 4047 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4048 "BM_%d : Mem Alloc Failed. Failing to load\n"); 4049 return -ENOMEM; 4050 } 4051 phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) * 4052 (phba->params.icds_per_ctrl - 4053 phba->params.ios_per_ctrl), 4054 GFP_KERNEL); 4055 if (!phba->eh_sgl_hndl_base) { 4056 kfree(phba->io_sgl_hndl_base); 4057 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4058 "BM_%d : Mem Alloc Failed. Failing to load\n"); 4059 return -ENOMEM; 4060 } 4061 } else { 4062 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4063 "BM_%d : HWI_MEM_SGLH is more than one element." 4064 "Failing to load\n"); 4065 return -ENOMEM; 4066 } 4067 4068 arr_index = 0; 4069 idx = 0; 4070 while (idx < mem_descr_sglh->num_elements) { 4071 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address; 4072 4073 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size / 4074 sizeof(struct sgl_handle)); i++) { 4075 if (arr_index < phba->params.ios_per_ctrl) { 4076 phba->io_sgl_hndl_base[arr_index] = psgl_handle; 4077 phba->io_sgl_hndl_avbl++; 4078 arr_index++; 4079 } else { 4080 phba->eh_sgl_hndl_base[arr_index - 4081 phba->params.ios_per_ctrl] = 4082 psgl_handle; 4083 arr_index++; 4084 phba->eh_sgl_hndl_avbl++; 4085 } 4086 psgl_handle++; 4087 } 4088 idx++; 4089 } 4090 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4091 "BM_%d : phba->io_sgl_hndl_avbl=%d" 4092 "phba->eh_sgl_hndl_avbl=%d\n", 4093 phba->io_sgl_hndl_avbl, 4094 phba->eh_sgl_hndl_avbl); 4095 4096 mem_descr_sg = phba->init_mem; 4097 mem_descr_sg += HWI_MEM_SGE; 4098 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4099 "\n BM_%d : mem_descr_sg->num_elements=%d\n", 4100 mem_descr_sg->num_elements); 4101 4102 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 4103 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) 4104 break; 4105 4106 ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num]; 4107 4108 arr_index = 0; 4109 idx = 0; 4110 while (idx < mem_descr_sg->num_elements) { 4111 pfrag = mem_descr_sg->mem_array[idx].virtual_address; 4112 4113 for (i = 0; 4114 i < (mem_descr_sg->mem_array[idx].size) / 4115 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io); 4116 i++) { 4117 if (arr_index < phba->params.ios_per_ctrl) 4118 psgl_handle = phba->io_sgl_hndl_base[arr_index]; 4119 else 4120 psgl_handle = phba->eh_sgl_hndl_base[arr_index - 4121 phba->params.ios_per_ctrl]; 4122 psgl_handle->pfrag = pfrag; 4123 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0); 4124 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0); 4125 pfrag += phba->params.num_sge_per_io; 4126 psgl_handle->sgl_index = ulp_icd_start + arr_index++; 4127 } 4128 idx++; 4129 } 4130 phba->io_sgl_free_index = 0; 4131 phba->io_sgl_alloc_index = 0; 4132 phba->eh_sgl_free_index = 0; 4133 phba->eh_sgl_alloc_index = 0; 4134 return 0; 4135 } 4136 4137 static int hba_setup_cid_tbls(struct beiscsi_hba *phba) 4138 { 4139 int ret; 4140 uint16_t i, ulp_num; 4141 struct ulp_cid_info *ptr_cid_info = NULL; 4142 4143 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4144 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4145 ptr_cid_info = kzalloc(sizeof(struct ulp_cid_info), 4146 GFP_KERNEL); 4147 4148 if (!ptr_cid_info) { 4149 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4150 "BM_%d : Failed to allocate memory" 4151 "for ULP_CID_INFO for ULP : %d\n", 4152 ulp_num); 4153 ret = -ENOMEM; 4154 goto free_memory; 4155 4156 } 4157 4158 /* Allocate memory for CID array */ 4159 ptr_cid_info->cid_array = kzalloc(sizeof(void *) * 4160 BEISCSI_GET_CID_COUNT(phba, 4161 ulp_num), GFP_KERNEL); 4162 if (!ptr_cid_info->cid_array) { 4163 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4164 "BM_%d : Failed to allocate memory" 4165 "for CID_ARRAY for ULP : %d\n", 4166 ulp_num); 4167 kfree(ptr_cid_info); 4168 ptr_cid_info = NULL; 4169 ret = -ENOMEM; 4170 4171 goto free_memory; 4172 } 4173 ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT( 4174 phba, ulp_num); 4175 4176 /* Save the cid_info_array ptr */ 4177 phba->cid_array_info[ulp_num] = ptr_cid_info; 4178 } 4179 } 4180 phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) * 4181 phba->params.cxns_per_ctrl, GFP_KERNEL); 4182 if (!phba->ep_array) { 4183 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4184 "BM_%d : Failed to allocate memory in " 4185 "hba_setup_cid_tbls\n"); 4186 ret = -ENOMEM; 4187 4188 goto free_memory; 4189 } 4190 4191 phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) * 4192 phba->params.cxns_per_ctrl, GFP_KERNEL); 4193 if (!phba->conn_table) { 4194 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4195 "BM_%d : Failed to allocate memory in" 4196 "hba_setup_cid_tbls\n"); 4197 4198 kfree(phba->ep_array); 4199 phba->ep_array = NULL; 4200 ret = -ENOMEM; 4201 4202 goto free_memory; 4203 } 4204 4205 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 4206 ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num; 4207 4208 ptr_cid_info = phba->cid_array_info[ulp_num]; 4209 ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] = 4210 phba->phwi_ctrlr->wrb_context[i].cid; 4211 4212 } 4213 4214 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4215 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4216 ptr_cid_info = phba->cid_array_info[ulp_num]; 4217 4218 ptr_cid_info->cid_alloc = 0; 4219 ptr_cid_info->cid_free = 0; 4220 } 4221 } 4222 return 0; 4223 4224 free_memory: 4225 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4226 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4227 ptr_cid_info = phba->cid_array_info[ulp_num]; 4228 4229 if (ptr_cid_info) { 4230 kfree(ptr_cid_info->cid_array); 4231 kfree(ptr_cid_info); 4232 phba->cid_array_info[ulp_num] = NULL; 4233 } 4234 } 4235 } 4236 4237 return ret; 4238 } 4239 4240 static void hwi_enable_intr(struct beiscsi_hba *phba) 4241 { 4242 struct be_ctrl_info *ctrl = &phba->ctrl; 4243 struct hwi_controller *phwi_ctrlr; 4244 struct hwi_context_memory *phwi_context; 4245 struct be_queue_info *eq; 4246 u8 __iomem *addr; 4247 u32 reg, i; 4248 u32 enabled; 4249 4250 phwi_ctrlr = phba->phwi_ctrlr; 4251 phwi_context = phwi_ctrlr->phwi_ctxt; 4252 4253 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg + 4254 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET); 4255 reg = ioread32(addr); 4256 4257 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4258 if (!enabled) { 4259 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4260 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4261 "BM_%d : reg =x%08x addr=%p\n", reg, addr); 4262 iowrite32(reg, addr); 4263 } 4264 4265 if (!phba->msix_enabled) { 4266 eq = &phwi_context->be_eq[0].q; 4267 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4268 "BM_%d : eq->id=%d\n", eq->id); 4269 4270 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); 4271 } else { 4272 for (i = 0; i <= phba->num_cpus; i++) { 4273 eq = &phwi_context->be_eq[i].q; 4274 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4275 "BM_%d : eq->id=%d\n", eq->id); 4276 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); 4277 } 4278 } 4279 } 4280 4281 static void hwi_disable_intr(struct beiscsi_hba *phba) 4282 { 4283 struct be_ctrl_info *ctrl = &phba->ctrl; 4284 4285 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET; 4286 u32 reg = ioread32(addr); 4287 4288 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4289 if (enabled) { 4290 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4291 iowrite32(reg, addr); 4292 } else 4293 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, 4294 "BM_%d : In hwi_disable_intr, Already Disabled\n"); 4295 } 4296 4297 /** 4298 * beiscsi_get_boot_info()- Get the boot session info 4299 * @phba: The device priv structure instance 4300 * 4301 * Get the boot target info and store in driver priv structure 4302 * 4303 * return values 4304 * Success: 0 4305 * Failure: Non-Zero Value 4306 **/ 4307 static int beiscsi_get_boot_info(struct beiscsi_hba *phba) 4308 { 4309 struct be_cmd_get_session_resp *session_resp; 4310 struct be_dma_mem nonemb_cmd; 4311 unsigned int tag; 4312 unsigned int s_handle; 4313 int ret = -ENOMEM; 4314 4315 /* Get the session handle of the boot target */ 4316 ret = be_mgmt_get_boot_shandle(phba, &s_handle); 4317 if (ret) { 4318 beiscsi_log(phba, KERN_ERR, 4319 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, 4320 "BM_%d : No boot session\n"); 4321 return ret; 4322 } 4323 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, 4324 sizeof(*session_resp), 4325 &nonemb_cmd.dma); 4326 if (nonemb_cmd.va == NULL) { 4327 beiscsi_log(phba, KERN_ERR, 4328 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, 4329 "BM_%d : Failed to allocate memory for" 4330 "beiscsi_get_session_info\n"); 4331 4332 return -ENOMEM; 4333 } 4334 4335 memset(nonemb_cmd.va, 0, sizeof(*session_resp)); 4336 tag = mgmt_get_session_info(phba, s_handle, 4337 &nonemb_cmd); 4338 if (!tag) { 4339 beiscsi_log(phba, KERN_ERR, 4340 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, 4341 "BM_%d : beiscsi_get_session_info" 4342 " Failed\n"); 4343 4344 goto boot_freemem; 4345 } 4346 4347 ret = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd); 4348 if (ret) { 4349 beiscsi_log(phba, KERN_ERR, 4350 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, 4351 "BM_%d : beiscsi_get_session_info Failed"); 4352 4353 if (ret != -EBUSY) 4354 goto boot_freemem; 4355 else 4356 return ret; 4357 } 4358 4359 session_resp = nonemb_cmd.va ; 4360 4361 memcpy(&phba->boot_sess, &session_resp->session_info, 4362 sizeof(struct mgmt_session_info)); 4363 ret = 0; 4364 4365 boot_freemem: 4366 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 4367 nonemb_cmd.va, nonemb_cmd.dma); 4368 return ret; 4369 } 4370 4371 static void beiscsi_boot_release(void *data) 4372 { 4373 struct beiscsi_hba *phba = data; 4374 4375 scsi_host_put(phba->shost); 4376 } 4377 4378 static int beiscsi_setup_boot_info(struct beiscsi_hba *phba) 4379 { 4380 struct iscsi_boot_kobj *boot_kobj; 4381 4382 /* get boot info using mgmt cmd */ 4383 if (beiscsi_get_boot_info(phba)) 4384 /* Try to see if we can carry on without this */ 4385 return 0; 4386 4387 phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no); 4388 if (!phba->boot_kset) 4389 return -ENOMEM; 4390 4391 /* get a ref because the show function will ref the phba */ 4392 if (!scsi_host_get(phba->shost)) 4393 goto free_kset; 4394 boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba, 4395 beiscsi_show_boot_tgt_info, 4396 beiscsi_tgt_get_attr_visibility, 4397 beiscsi_boot_release); 4398 if (!boot_kobj) 4399 goto put_shost; 4400 4401 if (!scsi_host_get(phba->shost)) 4402 goto free_kset; 4403 boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba, 4404 beiscsi_show_boot_ini_info, 4405 beiscsi_ini_get_attr_visibility, 4406 beiscsi_boot_release); 4407 if (!boot_kobj) 4408 goto put_shost; 4409 4410 if (!scsi_host_get(phba->shost)) 4411 goto free_kset; 4412 boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba, 4413 beiscsi_show_boot_eth_info, 4414 beiscsi_eth_get_attr_visibility, 4415 beiscsi_boot_release); 4416 if (!boot_kobj) 4417 goto put_shost; 4418 return 0; 4419 4420 put_shost: 4421 scsi_host_put(phba->shost); 4422 free_kset: 4423 iscsi_boot_destroy_kset(phba->boot_kset); 4424 return -ENOMEM; 4425 } 4426 4427 static int beiscsi_init_port(struct beiscsi_hba *phba) 4428 { 4429 int ret; 4430 4431 ret = beiscsi_init_controller(phba); 4432 if (ret < 0) { 4433 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4434 "BM_%d : beiscsi_dev_probe - Failed in" 4435 "beiscsi_init_controller\n"); 4436 return ret; 4437 } 4438 ret = beiscsi_init_sgl_handle(phba); 4439 if (ret < 0) { 4440 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4441 "BM_%d : beiscsi_dev_probe - Failed in" 4442 "beiscsi_init_sgl_handle\n"); 4443 goto do_cleanup_ctrlr; 4444 } 4445 4446 if (hba_setup_cid_tbls(phba)) { 4447 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4448 "BM_%d : Failed in hba_setup_cid_tbls\n"); 4449 kfree(phba->io_sgl_hndl_base); 4450 kfree(phba->eh_sgl_hndl_base); 4451 goto do_cleanup_ctrlr; 4452 } 4453 4454 return ret; 4455 4456 do_cleanup_ctrlr: 4457 hwi_cleanup(phba); 4458 return ret; 4459 } 4460 4461 static void hwi_purge_eq(struct beiscsi_hba *phba) 4462 { 4463 struct hwi_controller *phwi_ctrlr; 4464 struct hwi_context_memory *phwi_context; 4465 struct be_queue_info *eq; 4466 struct be_eq_entry *eqe = NULL; 4467 int i, eq_msix; 4468 unsigned int num_processed; 4469 4470 phwi_ctrlr = phba->phwi_ctrlr; 4471 phwi_context = phwi_ctrlr->phwi_ctxt; 4472 if (phba->msix_enabled) 4473 eq_msix = 1; 4474 else 4475 eq_msix = 0; 4476 4477 for (i = 0; i < (phba->num_cpus + eq_msix); i++) { 4478 eq = &phwi_context->be_eq[i].q; 4479 eqe = queue_tail_node(eq); 4480 num_processed = 0; 4481 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 4482 & EQE_VALID_MASK) { 4483 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 4484 queue_tail_inc(eq); 4485 eqe = queue_tail_node(eq); 4486 num_processed++; 4487 } 4488 4489 if (num_processed) 4490 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1); 4491 } 4492 } 4493 4494 static void beiscsi_clean_port(struct beiscsi_hba *phba) 4495 { 4496 int mgmt_status, ulp_num; 4497 struct ulp_cid_info *ptr_cid_info = NULL; 4498 4499 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4500 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4501 mgmt_status = mgmt_epfw_cleanup(phba, ulp_num); 4502 if (mgmt_status) 4503 beiscsi_log(phba, KERN_WARNING, 4504 BEISCSI_LOG_INIT, 4505 "BM_%d : mgmt_epfw_cleanup FAILED" 4506 " for ULP_%d\n", ulp_num); 4507 } 4508 } 4509 4510 hwi_purge_eq(phba); 4511 hwi_cleanup(phba); 4512 kfree(phba->io_sgl_hndl_base); 4513 kfree(phba->eh_sgl_hndl_base); 4514 kfree(phba->ep_array); 4515 kfree(phba->conn_table); 4516 4517 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4518 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4519 ptr_cid_info = phba->cid_array_info[ulp_num]; 4520 4521 if (ptr_cid_info) { 4522 kfree(ptr_cid_info->cid_array); 4523 kfree(ptr_cid_info); 4524 phba->cid_array_info[ulp_num] = NULL; 4525 } 4526 } 4527 } 4528 4529 } 4530 4531 /** 4532 * beiscsi_free_mgmt_task_handles()- Free driver CXN resources 4533 * @beiscsi_conn: ptr to the conn to be cleaned up 4534 * @task: ptr to iscsi_task resource to be freed. 4535 * 4536 * Free driver mgmt resources binded to CXN. 4537 **/ 4538 void 4539 beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, 4540 struct iscsi_task *task) 4541 { 4542 struct beiscsi_io_task *io_task; 4543 struct beiscsi_hba *phba = beiscsi_conn->phba; 4544 struct hwi_wrb_context *pwrb_context; 4545 struct hwi_controller *phwi_ctrlr; 4546 uint16_t cri_index = BE_GET_CRI_FROM_CID( 4547 beiscsi_conn->beiscsi_conn_cid); 4548 4549 phwi_ctrlr = phba->phwi_ctrlr; 4550 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 4551 4552 io_task = task->dd_data; 4553 4554 if (io_task->pwrb_handle) { 4555 memset(io_task->pwrb_handle->pwrb, 0, 4556 sizeof(struct iscsi_wrb)); 4557 free_wrb_handle(phba, pwrb_context, 4558 io_task->pwrb_handle); 4559 io_task->pwrb_handle = NULL; 4560 } 4561 4562 if (io_task->psgl_handle) { 4563 spin_lock_bh(&phba->mgmt_sgl_lock); 4564 free_mgmt_sgl_handle(phba, 4565 io_task->psgl_handle); 4566 io_task->psgl_handle = NULL; 4567 spin_unlock_bh(&phba->mgmt_sgl_lock); 4568 } 4569 4570 if (io_task->mtask_addr) 4571 pci_unmap_single(phba->pcidev, 4572 io_task->mtask_addr, 4573 io_task->mtask_data_count, 4574 PCI_DMA_TODEVICE); 4575 } 4576 4577 /** 4578 * beiscsi_cleanup_task()- Free driver resources of the task 4579 * @task: ptr to the iscsi task 4580 * 4581 **/ 4582 static void beiscsi_cleanup_task(struct iscsi_task *task) 4583 { 4584 struct beiscsi_io_task *io_task = task->dd_data; 4585 struct iscsi_conn *conn = task->conn; 4586 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4587 struct beiscsi_hba *phba = beiscsi_conn->phba; 4588 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; 4589 struct hwi_wrb_context *pwrb_context; 4590 struct hwi_controller *phwi_ctrlr; 4591 uint16_t cri_index = BE_GET_CRI_FROM_CID( 4592 beiscsi_conn->beiscsi_conn_cid); 4593 4594 phwi_ctrlr = phba->phwi_ctrlr; 4595 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 4596 4597 if (io_task->cmd_bhs) { 4598 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, 4599 io_task->bhs_pa.u.a64.address); 4600 io_task->cmd_bhs = NULL; 4601 } 4602 4603 if (task->sc) { 4604 if (io_task->pwrb_handle) { 4605 free_wrb_handle(phba, pwrb_context, 4606 io_task->pwrb_handle); 4607 io_task->pwrb_handle = NULL; 4608 } 4609 4610 if (io_task->psgl_handle) { 4611 spin_lock(&phba->io_sgl_lock); 4612 free_io_sgl_handle(phba, io_task->psgl_handle); 4613 spin_unlock(&phba->io_sgl_lock); 4614 io_task->psgl_handle = NULL; 4615 } 4616 4617 if (io_task->scsi_cmnd) { 4618 scsi_dma_unmap(io_task->scsi_cmnd); 4619 io_task->scsi_cmnd = NULL; 4620 } 4621 } else { 4622 if (!beiscsi_conn->login_in_progress) 4623 beiscsi_free_mgmt_task_handles(beiscsi_conn, task); 4624 } 4625 } 4626 4627 void 4628 beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn, 4629 struct beiscsi_offload_params *params) 4630 { 4631 struct wrb_handle *pwrb_handle; 4632 struct beiscsi_hba *phba = beiscsi_conn->phba; 4633 struct iscsi_task *task = beiscsi_conn->task; 4634 struct iscsi_session *session = task->conn->session; 4635 u32 doorbell = 0; 4636 4637 /* 4638 * We can always use 0 here because it is reserved by libiscsi for 4639 * login/startup related tasks. 4640 */ 4641 beiscsi_conn->login_in_progress = 0; 4642 spin_lock_bh(&session->back_lock); 4643 beiscsi_cleanup_task(task); 4644 spin_unlock_bh(&session->back_lock); 4645 4646 pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid); 4647 4648 /* Check for the adapter family */ 4649 if (is_chip_be2_be3r(phba)) 4650 beiscsi_offload_cxn_v0(params, pwrb_handle, 4651 phba->init_mem); 4652 else 4653 beiscsi_offload_cxn_v2(params, pwrb_handle); 4654 4655 be_dws_le_to_cpu(pwrb_handle->pwrb, 4656 sizeof(struct iscsi_target_context_update_wrb)); 4657 4658 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 4659 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK) 4660 << DB_DEF_PDU_WRB_INDEX_SHIFT; 4661 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4662 iowrite32(doorbell, phba->db_va + 4663 beiscsi_conn->doorbell_offset); 4664 } 4665 4666 static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt, 4667 int *index, int *age) 4668 { 4669 *index = (int)itt; 4670 if (age) 4671 *age = conn->session->age; 4672 } 4673 4674 /** 4675 * beiscsi_alloc_pdu - allocates pdu and related resources 4676 * @task: libiscsi task 4677 * @opcode: opcode of pdu for task 4678 * 4679 * This is called with the session lock held. It will allocate 4680 * the wrb and sgl if needed for the command. And it will prep 4681 * the pdu's itt. beiscsi_parse_pdu will later translate 4682 * the pdu itt to the libiscsi task itt. 4683 */ 4684 static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode) 4685 { 4686 struct beiscsi_io_task *io_task = task->dd_data; 4687 struct iscsi_conn *conn = task->conn; 4688 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4689 struct beiscsi_hba *phba = beiscsi_conn->phba; 4690 struct hwi_wrb_context *pwrb_context; 4691 struct hwi_controller *phwi_ctrlr; 4692 itt_t itt; 4693 uint16_t cri_index = 0; 4694 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; 4695 dma_addr_t paddr; 4696 4697 io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool, 4698 GFP_ATOMIC, &paddr); 4699 if (!io_task->cmd_bhs) 4700 return -ENOMEM; 4701 io_task->bhs_pa.u.a64.address = paddr; 4702 io_task->libiscsi_itt = (itt_t)task->itt; 4703 io_task->conn = beiscsi_conn; 4704 4705 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr; 4706 task->hdr_max = sizeof(struct be_cmd_bhs); 4707 io_task->psgl_handle = NULL; 4708 io_task->pwrb_handle = NULL; 4709 4710 if (task->sc) { 4711 spin_lock(&phba->io_sgl_lock); 4712 io_task->psgl_handle = alloc_io_sgl_handle(phba); 4713 spin_unlock(&phba->io_sgl_lock); 4714 if (!io_task->psgl_handle) { 4715 beiscsi_log(phba, KERN_ERR, 4716 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4717 "BM_%d : Alloc of IO_SGL_ICD Failed" 4718 "for the CID : %d\n", 4719 beiscsi_conn->beiscsi_conn_cid); 4720 goto free_hndls; 4721 } 4722 io_task->pwrb_handle = alloc_wrb_handle(phba, 4723 beiscsi_conn->beiscsi_conn_cid); 4724 if (!io_task->pwrb_handle) { 4725 beiscsi_log(phba, KERN_ERR, 4726 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4727 "BM_%d : Alloc of WRB_HANDLE Failed" 4728 "for the CID : %d\n", 4729 beiscsi_conn->beiscsi_conn_cid); 4730 goto free_io_hndls; 4731 } 4732 } else { 4733 io_task->scsi_cmnd = NULL; 4734 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) { 4735 beiscsi_conn->task = task; 4736 if (!beiscsi_conn->login_in_progress) { 4737 spin_lock(&phba->mgmt_sgl_lock); 4738 io_task->psgl_handle = (struct sgl_handle *) 4739 alloc_mgmt_sgl_handle(phba); 4740 spin_unlock(&phba->mgmt_sgl_lock); 4741 if (!io_task->psgl_handle) { 4742 beiscsi_log(phba, KERN_ERR, 4743 BEISCSI_LOG_IO | 4744 BEISCSI_LOG_CONFIG, 4745 "BM_%d : Alloc of MGMT_SGL_ICD Failed" 4746 "for the CID : %d\n", 4747 beiscsi_conn-> 4748 beiscsi_conn_cid); 4749 goto free_hndls; 4750 } 4751 4752 beiscsi_conn->login_in_progress = 1; 4753 beiscsi_conn->plogin_sgl_handle = 4754 io_task->psgl_handle; 4755 io_task->pwrb_handle = 4756 alloc_wrb_handle(phba, 4757 beiscsi_conn->beiscsi_conn_cid); 4758 if (!io_task->pwrb_handle) { 4759 beiscsi_log(phba, KERN_ERR, 4760 BEISCSI_LOG_IO | 4761 BEISCSI_LOG_CONFIG, 4762 "BM_%d : Alloc of WRB_HANDLE Failed" 4763 "for the CID : %d\n", 4764 beiscsi_conn-> 4765 beiscsi_conn_cid); 4766 goto free_mgmt_hndls; 4767 } 4768 beiscsi_conn->plogin_wrb_handle = 4769 io_task->pwrb_handle; 4770 4771 } else { 4772 io_task->psgl_handle = 4773 beiscsi_conn->plogin_sgl_handle; 4774 io_task->pwrb_handle = 4775 beiscsi_conn->plogin_wrb_handle; 4776 } 4777 } else { 4778 spin_lock(&phba->mgmt_sgl_lock); 4779 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba); 4780 spin_unlock(&phba->mgmt_sgl_lock); 4781 if (!io_task->psgl_handle) { 4782 beiscsi_log(phba, KERN_ERR, 4783 BEISCSI_LOG_IO | 4784 BEISCSI_LOG_CONFIG, 4785 "BM_%d : Alloc of MGMT_SGL_ICD Failed" 4786 "for the CID : %d\n", 4787 beiscsi_conn-> 4788 beiscsi_conn_cid); 4789 goto free_hndls; 4790 } 4791 io_task->pwrb_handle = 4792 alloc_wrb_handle(phba, 4793 beiscsi_conn->beiscsi_conn_cid); 4794 if (!io_task->pwrb_handle) { 4795 beiscsi_log(phba, KERN_ERR, 4796 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4797 "BM_%d : Alloc of WRB_HANDLE Failed" 4798 "for the CID : %d\n", 4799 beiscsi_conn->beiscsi_conn_cid); 4800 goto free_mgmt_hndls; 4801 } 4802 4803 } 4804 } 4805 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle-> 4806 wrb_index << 16) | (unsigned int) 4807 (io_task->psgl_handle->sgl_index)); 4808 io_task->pwrb_handle->pio_handle = task; 4809 4810 io_task->cmd_bhs->iscsi_hdr.itt = itt; 4811 return 0; 4812 4813 free_io_hndls: 4814 spin_lock(&phba->io_sgl_lock); 4815 free_io_sgl_handle(phba, io_task->psgl_handle); 4816 spin_unlock(&phba->io_sgl_lock); 4817 goto free_hndls; 4818 free_mgmt_hndls: 4819 spin_lock(&phba->mgmt_sgl_lock); 4820 free_mgmt_sgl_handle(phba, io_task->psgl_handle); 4821 io_task->psgl_handle = NULL; 4822 spin_unlock(&phba->mgmt_sgl_lock); 4823 free_hndls: 4824 phwi_ctrlr = phba->phwi_ctrlr; 4825 cri_index = BE_GET_CRI_FROM_CID( 4826 beiscsi_conn->beiscsi_conn_cid); 4827 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 4828 if (io_task->pwrb_handle) 4829 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle); 4830 io_task->pwrb_handle = NULL; 4831 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, 4832 io_task->bhs_pa.u.a64.address); 4833 io_task->cmd_bhs = NULL; 4834 return -ENOMEM; 4835 } 4836 int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg, 4837 unsigned int num_sg, unsigned int xferlen, 4838 unsigned int writedir) 4839 { 4840 4841 struct beiscsi_io_task *io_task = task->dd_data; 4842 struct iscsi_conn *conn = task->conn; 4843 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4844 struct beiscsi_hba *phba = beiscsi_conn->phba; 4845 struct iscsi_wrb *pwrb = NULL; 4846 unsigned int doorbell = 0; 4847 4848 pwrb = io_task->pwrb_handle->pwrb; 4849 4850 io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0; 4851 io_task->bhs_len = sizeof(struct be_cmd_bhs); 4852 4853 if (writedir) { 4854 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb, 4855 INI_WR_CMD); 4856 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1); 4857 } else { 4858 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb, 4859 INI_RD_CMD); 4860 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0); 4861 } 4862 4863 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2, 4864 type, pwrb); 4865 4866 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb, 4867 cpu_to_be16(*(unsigned short *) 4868 &io_task->cmd_bhs->iscsi_hdr.lun)); 4869 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen); 4870 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb, 4871 io_task->pwrb_handle->wrb_index); 4872 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb, 4873 be32_to_cpu(task->cmdsn)); 4874 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb, 4875 io_task->psgl_handle->sgl_index); 4876 4877 hwi_write_sgl_v2(pwrb, sg, num_sg, io_task); 4878 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb, 4879 io_task->pwrb_handle->nxt_wrb_index); 4880 4881 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); 4882 4883 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 4884 doorbell |= (io_task->pwrb_handle->wrb_index & 4885 DB_DEF_PDU_WRB_INDEX_MASK) << 4886 DB_DEF_PDU_WRB_INDEX_SHIFT; 4887 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4888 iowrite32(doorbell, phba->db_va + 4889 beiscsi_conn->doorbell_offset); 4890 return 0; 4891 } 4892 4893 static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg, 4894 unsigned int num_sg, unsigned int xferlen, 4895 unsigned int writedir) 4896 { 4897 4898 struct beiscsi_io_task *io_task = task->dd_data; 4899 struct iscsi_conn *conn = task->conn; 4900 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4901 struct beiscsi_hba *phba = beiscsi_conn->phba; 4902 struct iscsi_wrb *pwrb = NULL; 4903 unsigned int doorbell = 0; 4904 4905 pwrb = io_task->pwrb_handle->pwrb; 4906 io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0; 4907 io_task->bhs_len = sizeof(struct be_cmd_bhs); 4908 4909 if (writedir) { 4910 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4911 INI_WR_CMD); 4912 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1); 4913 } else { 4914 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4915 INI_RD_CMD); 4916 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); 4917 } 4918 4919 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb, 4920 type, pwrb); 4921 4922 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb, 4923 cpu_to_be16(*(unsigned short *) 4924 &io_task->cmd_bhs->iscsi_hdr.lun)); 4925 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen); 4926 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, 4927 io_task->pwrb_handle->wrb_index); 4928 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 4929 be32_to_cpu(task->cmdsn)); 4930 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, 4931 io_task->psgl_handle->sgl_index); 4932 4933 hwi_write_sgl(pwrb, sg, num_sg, io_task); 4934 4935 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, 4936 io_task->pwrb_handle->nxt_wrb_index); 4937 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); 4938 4939 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 4940 doorbell |= (io_task->pwrb_handle->wrb_index & 4941 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; 4942 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4943 4944 iowrite32(doorbell, phba->db_va + 4945 beiscsi_conn->doorbell_offset); 4946 return 0; 4947 } 4948 4949 static int beiscsi_mtask(struct iscsi_task *task) 4950 { 4951 struct beiscsi_io_task *io_task = task->dd_data; 4952 struct iscsi_conn *conn = task->conn; 4953 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4954 struct beiscsi_hba *phba = beiscsi_conn->phba; 4955 struct iscsi_wrb *pwrb = NULL; 4956 unsigned int doorbell = 0; 4957 unsigned int cid; 4958 unsigned int pwrb_typeoffset = 0; 4959 4960 cid = beiscsi_conn->beiscsi_conn_cid; 4961 pwrb = io_task->pwrb_handle->pwrb; 4962 memset(pwrb, 0, sizeof(*pwrb)); 4963 4964 if (is_chip_be2_be3r(phba)) { 4965 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 4966 be32_to_cpu(task->cmdsn)); 4967 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, 4968 io_task->pwrb_handle->wrb_index); 4969 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, 4970 io_task->psgl_handle->sgl_index); 4971 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, 4972 task->data_count); 4973 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, 4974 io_task->pwrb_handle->nxt_wrb_index); 4975 pwrb_typeoffset = BE_WRB_TYPE_OFFSET; 4976 } else { 4977 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb, 4978 be32_to_cpu(task->cmdsn)); 4979 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb, 4980 io_task->pwrb_handle->wrb_index); 4981 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb, 4982 io_task->psgl_handle->sgl_index); 4983 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, 4984 task->data_count); 4985 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb, 4986 io_task->pwrb_handle->nxt_wrb_index); 4987 pwrb_typeoffset = SKH_WRB_TYPE_OFFSET; 4988 } 4989 4990 4991 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) { 4992 case ISCSI_OP_LOGIN: 4993 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1); 4994 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); 4995 hwi_write_buffer(pwrb, task); 4996 break; 4997 case ISCSI_OP_NOOP_OUT: 4998 if (task->hdr->ttt != ISCSI_RESERVED_TAG) { 4999 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); 5000 if (is_chip_be2_be3r(phba)) 5001 AMAP_SET_BITS(struct amap_iscsi_wrb, 5002 dmsg, pwrb, 1); 5003 else 5004 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 5005 dmsg, pwrb, 1); 5006 } else { 5007 ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset); 5008 if (is_chip_be2_be3r(phba)) 5009 AMAP_SET_BITS(struct amap_iscsi_wrb, 5010 dmsg, pwrb, 0); 5011 else 5012 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 5013 dmsg, pwrb, 0); 5014 } 5015 hwi_write_buffer(pwrb, task); 5016 break; 5017 case ISCSI_OP_TEXT: 5018 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); 5019 hwi_write_buffer(pwrb, task); 5020 break; 5021 case ISCSI_OP_SCSI_TMFUNC: 5022 ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset); 5023 hwi_write_buffer(pwrb, task); 5024 break; 5025 case ISCSI_OP_LOGOUT: 5026 ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset); 5027 hwi_write_buffer(pwrb, task); 5028 break; 5029 5030 default: 5031 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 5032 "BM_%d : opcode =%d Not supported\n", 5033 task->hdr->opcode & ISCSI_OPCODE_MASK); 5034 5035 return -EINVAL; 5036 } 5037 5038 /* Set the task type */ 5039 io_task->wrb_type = (is_chip_be2_be3r(phba)) ? 5040 AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) : 5041 AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb); 5042 5043 doorbell |= cid & DB_WRB_POST_CID_MASK; 5044 doorbell |= (io_task->pwrb_handle->wrb_index & 5045 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; 5046 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 5047 iowrite32(doorbell, phba->db_va + 5048 beiscsi_conn->doorbell_offset); 5049 return 0; 5050 } 5051 5052 static int beiscsi_task_xmit(struct iscsi_task *task) 5053 { 5054 struct beiscsi_io_task *io_task = task->dd_data; 5055 struct scsi_cmnd *sc = task->sc; 5056 struct beiscsi_hba *phba = NULL; 5057 struct scatterlist *sg; 5058 int num_sg; 5059 unsigned int writedir = 0, xferlen = 0; 5060 5061 phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba; 5062 5063 if (!sc) 5064 return beiscsi_mtask(task); 5065 5066 io_task->scsi_cmnd = sc; 5067 num_sg = scsi_dma_map(sc); 5068 if (num_sg < 0) { 5069 struct iscsi_conn *conn = task->conn; 5070 struct beiscsi_hba *phba = NULL; 5071 5072 phba = ((struct beiscsi_conn *)conn->dd_data)->phba; 5073 beiscsi_log(phba, KERN_ERR, 5074 BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI, 5075 "BM_%d : scsi_dma_map Failed " 5076 "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n", 5077 be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt), 5078 io_task->libiscsi_itt, scsi_bufflen(sc)); 5079 5080 return num_sg; 5081 } 5082 xferlen = scsi_bufflen(sc); 5083 sg = scsi_sglist(sc); 5084 if (sc->sc_data_direction == DMA_TO_DEVICE) 5085 writedir = 1; 5086 else 5087 writedir = 0; 5088 5089 return phba->iotask_fn(task, sg, num_sg, xferlen, writedir); 5090 } 5091 5092 /** 5093 * beiscsi_bsg_request - handle bsg request from ISCSI transport 5094 * @job: job to handle 5095 */ 5096 static int beiscsi_bsg_request(struct bsg_job *job) 5097 { 5098 struct Scsi_Host *shost; 5099 struct beiscsi_hba *phba; 5100 struct iscsi_bsg_request *bsg_req = job->request; 5101 int rc = -EINVAL; 5102 unsigned int tag; 5103 struct be_dma_mem nonemb_cmd; 5104 struct be_cmd_resp_hdr *resp; 5105 struct iscsi_bsg_reply *bsg_reply = job->reply; 5106 unsigned short status, extd_status; 5107 5108 shost = iscsi_job_to_shost(job); 5109 phba = iscsi_host_priv(shost); 5110 5111 switch (bsg_req->msgcode) { 5112 case ISCSI_BSG_HST_VENDOR: 5113 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, 5114 job->request_payload.payload_len, 5115 &nonemb_cmd.dma); 5116 if (nonemb_cmd.va == NULL) { 5117 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 5118 "BM_%d : Failed to allocate memory for " 5119 "beiscsi_bsg_request\n"); 5120 return -ENOMEM; 5121 } 5122 tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job, 5123 &nonemb_cmd); 5124 if (!tag) { 5125 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 5126 "BM_%d : MBX Tag Allocation Failed\n"); 5127 5128 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 5129 nonemb_cmd.va, nonemb_cmd.dma); 5130 return -EAGAIN; 5131 } 5132 5133 rc = wait_event_interruptible_timeout( 5134 phba->ctrl.mcc_wait[tag], 5135 phba->ctrl.mcc_numtag[tag], 5136 msecs_to_jiffies( 5137 BEISCSI_HOST_MBX_TIMEOUT)); 5138 extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8; 5139 status = phba->ctrl.mcc_numtag[tag] & 0x000000FF; 5140 free_mcc_tag(&phba->ctrl, tag); 5141 resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va; 5142 sg_copy_from_buffer(job->reply_payload.sg_list, 5143 job->reply_payload.sg_cnt, 5144 nonemb_cmd.va, (resp->response_length 5145 + sizeof(*resp))); 5146 bsg_reply->reply_payload_rcv_len = resp->response_length; 5147 bsg_reply->result = status; 5148 bsg_job_done(job, bsg_reply->result, 5149 bsg_reply->reply_payload_rcv_len); 5150 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, 5151 nonemb_cmd.va, nonemb_cmd.dma); 5152 if (status || extd_status) { 5153 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 5154 "BM_%d : MBX Cmd Failed" 5155 " status = %d extd_status = %d\n", 5156 status, extd_status); 5157 5158 return -EIO; 5159 } else { 5160 rc = 0; 5161 } 5162 break; 5163 5164 default: 5165 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 5166 "BM_%d : Unsupported bsg command: 0x%x\n", 5167 bsg_req->msgcode); 5168 break; 5169 } 5170 5171 return rc; 5172 } 5173 5174 void beiscsi_hba_attrs_init(struct beiscsi_hba *phba) 5175 { 5176 /* Set the logging parameter */ 5177 beiscsi_log_enable_init(phba, beiscsi_log_enable); 5178 } 5179 5180 /* 5181 * beiscsi_quiesce()- Cleanup Driver resources 5182 * @phba: Instance Priv structure 5183 * @unload_state:i Clean or EEH unload state 5184 * 5185 * Free the OS and HW resources held by the driver 5186 **/ 5187 static void beiscsi_quiesce(struct beiscsi_hba *phba, 5188 uint32_t unload_state) 5189 { 5190 struct hwi_controller *phwi_ctrlr; 5191 struct hwi_context_memory *phwi_context; 5192 struct be_eq_obj *pbe_eq; 5193 unsigned int i, msix_vec; 5194 5195 phwi_ctrlr = phba->phwi_ctrlr; 5196 phwi_context = phwi_ctrlr->phwi_ctxt; 5197 hwi_disable_intr(phba); 5198 if (phba->msix_enabled) { 5199 for (i = 0; i <= phba->num_cpus; i++) { 5200 msix_vec = phba->msix_entries[i].vector; 5201 synchronize_irq(msix_vec); 5202 free_irq(msix_vec, &phwi_context->be_eq[i]); 5203 kfree(phba->msi_name[i]); 5204 } 5205 } else 5206 if (phba->pcidev->irq) { 5207 synchronize_irq(phba->pcidev->irq); 5208 free_irq(phba->pcidev->irq, phba); 5209 } 5210 pci_disable_msix(phba->pcidev); 5211 5212 for (i = 0; i < phba->num_cpus; i++) { 5213 pbe_eq = &phwi_context->be_eq[i]; 5214 blk_iopoll_disable(&pbe_eq->iopoll); 5215 } 5216 5217 if (unload_state == BEISCSI_CLEAN_UNLOAD) { 5218 destroy_workqueue(phba->wq); 5219 beiscsi_clean_port(phba); 5220 beiscsi_free_mem(phba); 5221 5222 beiscsi_unmap_pci_function(phba); 5223 pci_free_consistent(phba->pcidev, 5224 phba->ctrl.mbox_mem_alloced.size, 5225 phba->ctrl.mbox_mem_alloced.va, 5226 phba->ctrl.mbox_mem_alloced.dma); 5227 } else { 5228 hwi_purge_eq(phba); 5229 hwi_cleanup(phba); 5230 } 5231 5232 cancel_delayed_work_sync(&phba->beiscsi_hw_check_task); 5233 } 5234 5235 static void beiscsi_remove(struct pci_dev *pcidev) 5236 { 5237 5238 struct beiscsi_hba *phba = NULL; 5239 5240 phba = pci_get_drvdata(pcidev); 5241 if (!phba) { 5242 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n"); 5243 return; 5244 } 5245 5246 beiscsi_destroy_def_ifaces(phba); 5247 beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD); 5248 iscsi_boot_destroy_kset(phba->boot_kset); 5249 iscsi_host_remove(phba->shost); 5250 pci_dev_put(phba->pcidev); 5251 iscsi_host_free(phba->shost); 5252 pci_disable_pcie_error_reporting(pcidev); 5253 pci_set_drvdata(pcidev, NULL); 5254 pci_disable_device(pcidev); 5255 } 5256 5257 static void beiscsi_shutdown(struct pci_dev *pcidev) 5258 { 5259 5260 struct beiscsi_hba *phba = NULL; 5261 5262 phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev); 5263 if (!phba) { 5264 dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n"); 5265 return; 5266 } 5267 5268 phba->state = BE_ADAPTER_STATE_SHUTDOWN; 5269 iscsi_host_for_each_session(phba->shost, be2iscsi_fail_session); 5270 beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD); 5271 pci_disable_device(pcidev); 5272 } 5273 5274 static void beiscsi_msix_enable(struct beiscsi_hba *phba) 5275 { 5276 int i, status; 5277 5278 for (i = 0; i <= phba->num_cpus; i++) 5279 phba->msix_entries[i].entry = i; 5280 5281 status = pci_enable_msix(phba->pcidev, phba->msix_entries, 5282 (phba->num_cpus + 1)); 5283 if (!status) 5284 phba->msix_enabled = true; 5285 5286 return; 5287 } 5288 5289 static void be_eqd_update(struct beiscsi_hba *phba) 5290 { 5291 struct be_set_eqd set_eqd[MAX_CPUS]; 5292 struct be_aic_obj *aic; 5293 struct be_eq_obj *pbe_eq; 5294 struct hwi_controller *phwi_ctrlr; 5295 struct hwi_context_memory *phwi_context; 5296 int eqd, i, num = 0; 5297 ulong now; 5298 u32 pps, delta; 5299 unsigned int tag; 5300 5301 phwi_ctrlr = phba->phwi_ctrlr; 5302 phwi_context = phwi_ctrlr->phwi_ctxt; 5303 5304 for (i = 0; i <= phba->num_cpus; i++) { 5305 aic = &phba->aic_obj[i]; 5306 pbe_eq = &phwi_context->be_eq[i]; 5307 now = jiffies; 5308 if (!aic->jiffs || time_before(now, aic->jiffs) || 5309 pbe_eq->cq_count < aic->eq_prev) { 5310 aic->jiffs = now; 5311 aic->eq_prev = pbe_eq->cq_count; 5312 continue; 5313 } 5314 delta = jiffies_to_msecs(now - aic->jiffs); 5315 pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta); 5316 eqd = (pps / 1500) << 2; 5317 5318 if (eqd < 8) 5319 eqd = 0; 5320 eqd = min_t(u32, eqd, phwi_context->max_eqd); 5321 eqd = max_t(u32, eqd, phwi_context->min_eqd); 5322 5323 aic->jiffs = now; 5324 aic->eq_prev = pbe_eq->cq_count; 5325 5326 if (eqd != aic->prev_eqd) { 5327 set_eqd[num].delay_multiplier = (eqd * 65)/100; 5328 set_eqd[num].eq_id = pbe_eq->q.id; 5329 aic->prev_eqd = eqd; 5330 num++; 5331 } 5332 } 5333 if (num) { 5334 tag = be_cmd_modify_eq_delay(phba, set_eqd, num); 5335 if (tag) 5336 beiscsi_mccq_compl(phba, tag, NULL, NULL); 5337 } 5338 } 5339 5340 /* 5341 * beiscsi_hw_health_check()- Check adapter health 5342 * @work: work item to check HW health 5343 * 5344 * Check if adapter in an unrecoverable state or not. 5345 **/ 5346 static void 5347 beiscsi_hw_health_check(struct work_struct *work) 5348 { 5349 struct beiscsi_hba *phba = 5350 container_of(work, struct beiscsi_hba, 5351 beiscsi_hw_check_task.work); 5352 5353 be_eqd_update(phba); 5354 5355 beiscsi_ue_detect(phba); 5356 5357 schedule_delayed_work(&phba->beiscsi_hw_check_task, 5358 msecs_to_jiffies(1000)); 5359 } 5360 5361 5362 static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev, 5363 pci_channel_state_t state) 5364 { 5365 struct beiscsi_hba *phba = NULL; 5366 5367 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); 5368 phba->state |= BE_ADAPTER_PCI_ERR; 5369 5370 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5371 "BM_%d : EEH error detected\n"); 5372 5373 beiscsi_quiesce(phba, BEISCSI_EEH_UNLOAD); 5374 5375 if (state == pci_channel_io_perm_failure) { 5376 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5377 "BM_%d : EEH : State PERM Failure"); 5378 return PCI_ERS_RESULT_DISCONNECT; 5379 } 5380 5381 pci_disable_device(pdev); 5382 5383 /* The error could cause the FW to trigger a flash debug dump. 5384 * Resetting the card while flash dump is in progress 5385 * can cause it not to recover; wait for it to finish. 5386 * Wait only for first function as it is needed only once per 5387 * adapter. 5388 **/ 5389 if (pdev->devfn == 0) 5390 ssleep(30); 5391 5392 return PCI_ERS_RESULT_NEED_RESET; 5393 } 5394 5395 static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev) 5396 { 5397 struct beiscsi_hba *phba = NULL; 5398 int status = 0; 5399 5400 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); 5401 5402 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5403 "BM_%d : EEH Reset\n"); 5404 5405 status = pci_enable_device(pdev); 5406 if (status) 5407 return PCI_ERS_RESULT_DISCONNECT; 5408 5409 pci_set_master(pdev); 5410 pci_set_power_state(pdev, PCI_D0); 5411 pci_restore_state(pdev); 5412 5413 /* Wait for the CHIP Reset to complete */ 5414 status = be_chk_reset_complete(phba); 5415 if (!status) { 5416 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, 5417 "BM_%d : EEH Reset Completed\n"); 5418 } else { 5419 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, 5420 "BM_%d : EEH Reset Completion Failure\n"); 5421 return PCI_ERS_RESULT_DISCONNECT; 5422 } 5423 5424 pci_cleanup_aer_uncorrect_error_status(pdev); 5425 return PCI_ERS_RESULT_RECOVERED; 5426 } 5427 5428 static void beiscsi_eeh_resume(struct pci_dev *pdev) 5429 { 5430 int ret = 0, i; 5431 struct be_eq_obj *pbe_eq; 5432 struct beiscsi_hba *phba = NULL; 5433 struct hwi_controller *phwi_ctrlr; 5434 struct hwi_context_memory *phwi_context; 5435 5436 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); 5437 pci_save_state(pdev); 5438 5439 if (enable_msix) 5440 find_num_cpus(phba); 5441 else 5442 phba->num_cpus = 1; 5443 5444 if (enable_msix) { 5445 beiscsi_msix_enable(phba); 5446 if (!phba->msix_enabled) 5447 phba->num_cpus = 1; 5448 } 5449 5450 ret = beiscsi_cmd_reset_function(phba); 5451 if (ret) { 5452 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5453 "BM_%d : Reset Failed\n"); 5454 goto ret_err; 5455 } 5456 5457 ret = be_chk_reset_complete(phba); 5458 if (ret) { 5459 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5460 "BM_%d : Failed to get out of reset.\n"); 5461 goto ret_err; 5462 } 5463 5464 beiscsi_get_params(phba); 5465 phba->shost->max_id = phba->params.cxns_per_ctrl; 5466 phba->shost->can_queue = phba->params.ios_per_ctrl; 5467 ret = hwi_init_controller(phba); 5468 5469 for (i = 0; i < MAX_MCC_CMD; i++) { 5470 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); 5471 phba->ctrl.mcc_tag[i] = i + 1; 5472 phba->ctrl.mcc_numtag[i + 1] = 0; 5473 phba->ctrl.mcc_tag_available++; 5474 } 5475 5476 phwi_ctrlr = phba->phwi_ctrlr; 5477 phwi_context = phwi_ctrlr->phwi_ctxt; 5478 5479 for (i = 0; i < phba->num_cpus; i++) { 5480 pbe_eq = &phwi_context->be_eq[i]; 5481 blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget, 5482 be_iopoll); 5483 blk_iopoll_enable(&pbe_eq->iopoll); 5484 } 5485 5486 i = (phba->msix_enabled) ? i : 0; 5487 /* Work item for MCC handling */ 5488 pbe_eq = &phwi_context->be_eq[i]; 5489 INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs); 5490 5491 ret = beiscsi_init_irqs(phba); 5492 if (ret < 0) { 5493 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5494 "BM_%d : beiscsi_eeh_resume - " 5495 "Failed to beiscsi_init_irqs\n"); 5496 goto ret_err; 5497 } 5498 5499 hwi_enable_intr(phba); 5500 phba->state &= ~BE_ADAPTER_PCI_ERR; 5501 5502 return; 5503 ret_err: 5504 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5505 "BM_%d : AER EEH Resume Failed\n"); 5506 } 5507 5508 static int beiscsi_dev_probe(struct pci_dev *pcidev, 5509 const struct pci_device_id *id) 5510 { 5511 struct beiscsi_hba *phba = NULL; 5512 struct hwi_controller *phwi_ctrlr; 5513 struct hwi_context_memory *phwi_context; 5514 struct be_eq_obj *pbe_eq; 5515 int ret = 0, i; 5516 5517 ret = beiscsi_enable_pci(pcidev); 5518 if (ret < 0) { 5519 dev_err(&pcidev->dev, 5520 "beiscsi_dev_probe - Failed to enable pci device\n"); 5521 return ret; 5522 } 5523 5524 phba = beiscsi_hba_alloc(pcidev); 5525 if (!phba) { 5526 dev_err(&pcidev->dev, 5527 "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n"); 5528 goto disable_pci; 5529 } 5530 5531 /* Enable EEH reporting */ 5532 ret = pci_enable_pcie_error_reporting(pcidev); 5533 if (ret) 5534 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, 5535 "BM_%d : PCIe Error Reporting " 5536 "Enabling Failed\n"); 5537 5538 pci_save_state(pcidev); 5539 5540 /* Initialize Driver configuration Paramters */ 5541 beiscsi_hba_attrs_init(phba); 5542 5543 phba->fw_timeout = false; 5544 phba->mac_addr_set = false; 5545 5546 5547 switch (pcidev->device) { 5548 case BE_DEVICE_ID1: 5549 case OC_DEVICE_ID1: 5550 case OC_DEVICE_ID2: 5551 phba->generation = BE_GEN2; 5552 phba->iotask_fn = beiscsi_iotask; 5553 break; 5554 case BE_DEVICE_ID2: 5555 case OC_DEVICE_ID3: 5556 phba->generation = BE_GEN3; 5557 phba->iotask_fn = beiscsi_iotask; 5558 break; 5559 case OC_SKH_ID1: 5560 phba->generation = BE_GEN4; 5561 phba->iotask_fn = beiscsi_iotask_v2; 5562 break; 5563 default: 5564 phba->generation = 0; 5565 } 5566 5567 ret = be_ctrl_init(phba, pcidev); 5568 if (ret) { 5569 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5570 "BM_%d : beiscsi_dev_probe-" 5571 "Failed in be_ctrl_init\n"); 5572 goto hba_free; 5573 } 5574 5575 ret = beiscsi_cmd_reset_function(phba); 5576 if (ret) { 5577 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5578 "BM_%d : Reset Failed\n"); 5579 goto hba_free; 5580 } 5581 ret = be_chk_reset_complete(phba); 5582 if (ret) { 5583 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5584 "BM_%d : Failed to get out of reset.\n"); 5585 goto hba_free; 5586 } 5587 5588 spin_lock_init(&phba->io_sgl_lock); 5589 spin_lock_init(&phba->mgmt_sgl_lock); 5590 spin_lock_init(&phba->isr_lock); 5591 spin_lock_init(&phba->async_pdu_lock); 5592 ret = mgmt_get_fw_config(&phba->ctrl, phba); 5593 if (ret != 0) { 5594 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5595 "BM_%d : Error getting fw config\n"); 5596 goto free_port; 5597 } 5598 5599 if (enable_msix) 5600 find_num_cpus(phba); 5601 else 5602 phba->num_cpus = 1; 5603 5604 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 5605 "BM_%d : num_cpus = %d\n", 5606 phba->num_cpus); 5607 5608 if (enable_msix) { 5609 beiscsi_msix_enable(phba); 5610 if (!phba->msix_enabled) 5611 phba->num_cpus = 1; 5612 } 5613 5614 phba->shost->max_id = phba->params.cxns_per_ctrl; 5615 beiscsi_get_params(phba); 5616 phba->shost->can_queue = phba->params.ios_per_ctrl; 5617 ret = beiscsi_init_port(phba); 5618 if (ret < 0) { 5619 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5620 "BM_%d : beiscsi_dev_probe-" 5621 "Failed in beiscsi_init_port\n"); 5622 goto free_port; 5623 } 5624 5625 for (i = 0; i < MAX_MCC_CMD; i++) { 5626 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); 5627 phba->ctrl.mcc_tag[i] = i + 1; 5628 phba->ctrl.mcc_numtag[i + 1] = 0; 5629 phba->ctrl.mcc_tag_available++; 5630 memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0, 5631 sizeof(struct be_dma_mem)); 5632 } 5633 5634 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0; 5635 5636 snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq", 5637 phba->shost->host_no); 5638 phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name); 5639 if (!phba->wq) { 5640 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5641 "BM_%d : beiscsi_dev_probe-" 5642 "Failed to allocate work queue\n"); 5643 goto free_twq; 5644 } 5645 5646 INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task, 5647 beiscsi_hw_health_check); 5648 5649 phwi_ctrlr = phba->phwi_ctrlr; 5650 phwi_context = phwi_ctrlr->phwi_ctxt; 5651 5652 for (i = 0; i < phba->num_cpus; i++) { 5653 pbe_eq = &phwi_context->be_eq[i]; 5654 blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget, 5655 be_iopoll); 5656 blk_iopoll_enable(&pbe_eq->iopoll); 5657 } 5658 5659 i = (phba->msix_enabled) ? i : 0; 5660 /* Work item for MCC handling */ 5661 pbe_eq = &phwi_context->be_eq[i]; 5662 INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs); 5663 5664 ret = beiscsi_init_irqs(phba); 5665 if (ret < 0) { 5666 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5667 "BM_%d : beiscsi_dev_probe-" 5668 "Failed to beiscsi_init_irqs\n"); 5669 goto free_blkenbld; 5670 } 5671 hwi_enable_intr(phba); 5672 5673 if (iscsi_host_add(phba->shost, &phba->pcidev->dev)) 5674 goto free_blkenbld; 5675 5676 if (beiscsi_setup_boot_info(phba)) 5677 /* 5678 * log error but continue, because we may not be using 5679 * iscsi boot. 5680 */ 5681 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5682 "BM_%d : Could not set up " 5683 "iSCSI boot info.\n"); 5684 5685 beiscsi_create_def_ifaces(phba); 5686 schedule_delayed_work(&phba->beiscsi_hw_check_task, 5687 msecs_to_jiffies(1000)); 5688 5689 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 5690 "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n"); 5691 return 0; 5692 5693 free_blkenbld: 5694 destroy_workqueue(phba->wq); 5695 for (i = 0; i < phba->num_cpus; i++) { 5696 pbe_eq = &phwi_context->be_eq[i]; 5697 blk_iopoll_disable(&pbe_eq->iopoll); 5698 } 5699 free_twq: 5700 beiscsi_clean_port(phba); 5701 beiscsi_free_mem(phba); 5702 free_port: 5703 pci_free_consistent(phba->pcidev, 5704 phba->ctrl.mbox_mem_alloced.size, 5705 phba->ctrl.mbox_mem_alloced.va, 5706 phba->ctrl.mbox_mem_alloced.dma); 5707 beiscsi_unmap_pci_function(phba); 5708 hba_free: 5709 if (phba->msix_enabled) 5710 pci_disable_msix(phba->pcidev); 5711 iscsi_host_remove(phba->shost); 5712 pci_dev_put(phba->pcidev); 5713 iscsi_host_free(phba->shost); 5714 disable_pci: 5715 pci_disable_device(pcidev); 5716 return ret; 5717 } 5718 5719 static struct pci_error_handlers beiscsi_eeh_handlers = { 5720 .error_detected = beiscsi_eeh_err_detected, 5721 .slot_reset = beiscsi_eeh_reset, 5722 .resume = beiscsi_eeh_resume, 5723 }; 5724 5725 struct iscsi_transport beiscsi_iscsi_transport = { 5726 .owner = THIS_MODULE, 5727 .name = DRV_NAME, 5728 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO | 5729 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD, 5730 .create_session = beiscsi_session_create, 5731 .destroy_session = beiscsi_session_destroy, 5732 .create_conn = beiscsi_conn_create, 5733 .bind_conn = beiscsi_conn_bind, 5734 .destroy_conn = iscsi_conn_teardown, 5735 .attr_is_visible = be2iscsi_attr_is_visible, 5736 .set_iface_param = be2iscsi_iface_set_param, 5737 .get_iface_param = be2iscsi_iface_get_param, 5738 .set_param = beiscsi_set_param, 5739 .get_conn_param = iscsi_conn_get_param, 5740 .get_session_param = iscsi_session_get_param, 5741 .get_host_param = beiscsi_get_host_param, 5742 .start_conn = beiscsi_conn_start, 5743 .stop_conn = iscsi_conn_stop, 5744 .send_pdu = iscsi_conn_send_pdu, 5745 .xmit_task = beiscsi_task_xmit, 5746 .cleanup_task = beiscsi_cleanup_task, 5747 .alloc_pdu = beiscsi_alloc_pdu, 5748 .parse_pdu_itt = beiscsi_parse_pdu, 5749 .get_stats = beiscsi_conn_get_stats, 5750 .get_ep_param = beiscsi_ep_get_param, 5751 .ep_connect = beiscsi_ep_connect, 5752 .ep_poll = beiscsi_ep_poll, 5753 .ep_disconnect = beiscsi_ep_disconnect, 5754 .session_recovery_timedout = iscsi_session_recovery_timedout, 5755 .bsg_request = beiscsi_bsg_request, 5756 }; 5757 5758 static struct pci_driver beiscsi_pci_driver = { 5759 .name = DRV_NAME, 5760 .probe = beiscsi_dev_probe, 5761 .remove = beiscsi_remove, 5762 .shutdown = beiscsi_shutdown, 5763 .id_table = beiscsi_pci_id_table, 5764 .err_handler = &beiscsi_eeh_handlers 5765 }; 5766 5767 5768 static int __init beiscsi_module_init(void) 5769 { 5770 int ret; 5771 5772 beiscsi_scsi_transport = 5773 iscsi_register_transport(&beiscsi_iscsi_transport); 5774 if (!beiscsi_scsi_transport) { 5775 printk(KERN_ERR 5776 "beiscsi_module_init - Unable to register beiscsi transport.\n"); 5777 return -ENOMEM; 5778 } 5779 printk(KERN_INFO "In beiscsi_module_init, tt=%p\n", 5780 &beiscsi_iscsi_transport); 5781 5782 ret = pci_register_driver(&beiscsi_pci_driver); 5783 if (ret) { 5784 printk(KERN_ERR 5785 "beiscsi_module_init - Unable to register beiscsi pci driver.\n"); 5786 goto unregister_iscsi_transport; 5787 } 5788 return 0; 5789 5790 unregister_iscsi_transport: 5791 iscsi_unregister_transport(&beiscsi_iscsi_transport); 5792 return ret; 5793 } 5794 5795 static void __exit beiscsi_module_exit(void) 5796 { 5797 pci_unregister_driver(&beiscsi_pci_driver); 5798 iscsi_unregister_transport(&beiscsi_iscsi_transport); 5799 } 5800 5801 module_init(beiscsi_module_init); 5802 module_exit(beiscsi_module_exit); 5803