1 /* 2 * This file is part of the Emulex Linux Device Driver for Enterprise iSCSI 3 * Host Bus Adapters. Refer to the README file included with this package 4 * for driver version and adapter compatibility. 5 * 6 * Copyright (c) 2018 Broadcom. All Rights Reserved. 7 * The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of version 2 of the GNU General Public License as published 11 * by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful. ALL EXPRESS 14 * OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, INCLUDING ANY 15 * IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, 16 * OR NON-INFRINGEMENT, ARE DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH 17 * DISCLAIMERS ARE HELD TO BE LEGALLY INVALID. 18 * See the GNU General Public License for more details, a copy of which 19 * can be found in the file COPYING included with this package. 20 * 21 * Contact Information: 22 * linux-drivers@broadcom.com 23 * 24 */ 25 26 #include <linux/reboot.h> 27 #include <linux/delay.h> 28 #include <linux/slab.h> 29 #include <linux/interrupt.h> 30 #include <linux/blkdev.h> 31 #include <linux/pci.h> 32 #include <linux/string.h> 33 #include <linux/kernel.h> 34 #include <linux/semaphore.h> 35 #include <linux/iscsi_boot_sysfs.h> 36 #include <linux/module.h> 37 #include <linux/bsg-lib.h> 38 #include <linux/irq_poll.h> 39 40 #include <scsi/libiscsi.h> 41 #include <scsi/scsi_bsg_iscsi.h> 42 #include <scsi/scsi_netlink.h> 43 #include <scsi/scsi_transport_iscsi.h> 44 #include <scsi/scsi_transport.h> 45 #include <scsi/scsi_cmnd.h> 46 #include <scsi/scsi_device.h> 47 #include <scsi/scsi_host.h> 48 #include <scsi/scsi.h> 49 #include "be_main.h" 50 #include "be_iscsi.h" 51 #include "be_mgmt.h" 52 #include "be_cmds.h" 53 54 static unsigned int be_iopoll_budget = 10; 55 static unsigned int be_max_phys_size = 64; 56 static unsigned int enable_msix = 1; 57 58 MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR); 59 MODULE_VERSION(BUILD_STR); 60 MODULE_AUTHOR("Emulex Corporation"); 61 MODULE_LICENSE("GPL"); 62 module_param(be_iopoll_budget, int, 0); 63 module_param(enable_msix, int, 0); 64 module_param(be_max_phys_size, uint, S_IRUGO); 65 MODULE_PARM_DESC(be_max_phys_size, 66 "Maximum Size (In Kilobytes) of physically contiguous " 67 "memory that can be allocated. Range is 16 - 128"); 68 69 #define beiscsi_disp_param(_name)\ 70 static ssize_t \ 71 beiscsi_##_name##_disp(struct device *dev,\ 72 struct device_attribute *attrib, char *buf) \ 73 { \ 74 struct Scsi_Host *shost = class_to_shost(dev);\ 75 struct beiscsi_hba *phba = iscsi_host_priv(shost); \ 76 return snprintf(buf, PAGE_SIZE, "%d\n",\ 77 phba->attr_##_name);\ 78 } 79 80 #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\ 81 static int \ 82 beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\ 83 {\ 84 if (val >= _minval && val <= _maxval) {\ 85 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\ 86 "BA_%d : beiscsi_"#_name" updated "\ 87 "from 0x%x ==> 0x%x\n",\ 88 phba->attr_##_name, val); \ 89 phba->attr_##_name = val;\ 90 return 0;\ 91 } \ 92 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \ 93 "BA_%d beiscsi_"#_name" attribute "\ 94 "cannot be updated to 0x%x, "\ 95 "range allowed is ["#_minval" - "#_maxval"]\n", val);\ 96 return -EINVAL;\ 97 } 98 99 #define beiscsi_store_param(_name) \ 100 static ssize_t \ 101 beiscsi_##_name##_store(struct device *dev,\ 102 struct device_attribute *attr, const char *buf,\ 103 size_t count) \ 104 { \ 105 struct Scsi_Host *shost = class_to_shost(dev);\ 106 struct beiscsi_hba *phba = iscsi_host_priv(shost);\ 107 uint32_t param_val = 0;\ 108 if (!isdigit(buf[0]))\ 109 return -EINVAL;\ 110 if (sscanf(buf, "%i", ¶m_val) != 1)\ 111 return -EINVAL;\ 112 if (beiscsi_##_name##_change(phba, param_val) == 0) \ 113 return strlen(buf);\ 114 else \ 115 return -EINVAL;\ 116 } 117 118 #define beiscsi_init_param(_name, _minval, _maxval, _defval) \ 119 static int \ 120 beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \ 121 { \ 122 if (val >= _minval && val <= _maxval) {\ 123 phba->attr_##_name = val;\ 124 return 0;\ 125 } \ 126 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\ 127 "BA_%d beiscsi_"#_name" attribute " \ 128 "cannot be updated to 0x%x, "\ 129 "range allowed is ["#_minval" - "#_maxval"]\n", val);\ 130 phba->attr_##_name = _defval;\ 131 return -EINVAL;\ 132 } 133 134 #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \ 135 static uint beiscsi_##_name = _defval;\ 136 module_param(beiscsi_##_name, uint, S_IRUGO);\ 137 MODULE_PARM_DESC(beiscsi_##_name, _descp);\ 138 beiscsi_disp_param(_name)\ 139 beiscsi_change_param(_name, _minval, _maxval, _defval)\ 140 beiscsi_store_param(_name)\ 141 beiscsi_init_param(_name, _minval, _maxval, _defval)\ 142 static DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\ 143 beiscsi_##_name##_disp, beiscsi_##_name##_store) 144 145 /* 146 * When new log level added update MAX allowed value for log_enable 147 */ 148 BEISCSI_RW_ATTR(log_enable, 0x00, 149 0xFF, 0x00, "Enable logging Bit Mask\n" 150 "\t\t\t\tInitialization Events : 0x01\n" 151 "\t\t\t\tMailbox Events : 0x02\n" 152 "\t\t\t\tMiscellaneous Events : 0x04\n" 153 "\t\t\t\tError Handling : 0x08\n" 154 "\t\t\t\tIO Path Events : 0x10\n" 155 "\t\t\t\tConfiguration Path : 0x20\n" 156 "\t\t\t\tiSCSI Protocol : 0x40\n"); 157 158 static DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL); 159 static DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL); 160 static DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL); 161 static DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL); 162 static DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO, 163 beiscsi_active_session_disp, NULL); 164 static DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO, 165 beiscsi_free_session_disp, NULL); 166 167 static struct attribute *beiscsi_attrs[] = { 168 &dev_attr_beiscsi_log_enable.attr, 169 &dev_attr_beiscsi_drvr_ver.attr, 170 &dev_attr_beiscsi_adapter_family.attr, 171 &dev_attr_beiscsi_fw_ver.attr, 172 &dev_attr_beiscsi_active_session_count.attr, 173 &dev_attr_beiscsi_free_session_count.attr, 174 &dev_attr_beiscsi_phys_port.attr, 175 NULL, 176 }; 177 178 ATTRIBUTE_GROUPS(beiscsi); 179 180 static char const *cqe_desc[] = { 181 "RESERVED_DESC", 182 "SOL_CMD_COMPLETE", 183 "SOL_CMD_KILLED_DATA_DIGEST_ERR", 184 "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL", 185 "CXN_KILLED_BURST_LEN_MISMATCH", 186 "CXN_KILLED_AHS_RCVD", 187 "CXN_KILLED_HDR_DIGEST_ERR", 188 "CXN_KILLED_UNKNOWN_HDR", 189 "CXN_KILLED_STALE_ITT_TTT_RCVD", 190 "CXN_KILLED_INVALID_ITT_TTT_RCVD", 191 "CXN_KILLED_RST_RCVD", 192 "CXN_KILLED_TIMED_OUT", 193 "CXN_KILLED_RST_SENT", 194 "CXN_KILLED_FIN_RCVD", 195 "CXN_KILLED_BAD_UNSOL_PDU_RCVD", 196 "CXN_KILLED_BAD_WRB_INDEX_ERROR", 197 "CXN_KILLED_OVER_RUN_RESIDUAL", 198 "CXN_KILLED_UNDER_RUN_RESIDUAL", 199 "CMD_KILLED_INVALID_STATSN_RCVD", 200 "CMD_KILLED_INVALID_R2T_RCVD", 201 "CMD_CXN_KILLED_LUN_INVALID", 202 "CMD_CXN_KILLED_ICD_INVALID", 203 "CMD_CXN_KILLED_ITT_INVALID", 204 "CMD_CXN_KILLED_SEQ_OUTOFORDER", 205 "CMD_CXN_KILLED_INVALID_DATASN_RCVD", 206 "CXN_INVALIDATE_NOTIFY", 207 "CXN_INVALIDATE_INDEX_NOTIFY", 208 "CMD_INVALIDATED_NOTIFY", 209 "UNSOL_HDR_NOTIFY", 210 "UNSOL_DATA_NOTIFY", 211 "UNSOL_DATA_DIGEST_ERROR_NOTIFY", 212 "DRIVERMSG_NOTIFY", 213 "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN", 214 "SOL_CMD_KILLED_DIF_ERR", 215 "CXN_KILLED_SYN_RCVD", 216 "CXN_KILLED_IMM_DATA_RCVD" 217 }; 218 219 static int beiscsi_eh_abort(struct scsi_cmnd *sc) 220 { 221 struct iscsi_task *abrt_task = iscsi_cmd(sc)->task; 222 struct iscsi_cls_session *cls_session; 223 struct beiscsi_io_task *abrt_io_task; 224 struct beiscsi_conn *beiscsi_conn; 225 struct iscsi_session *session; 226 struct invldt_cmd_tbl inv_tbl; 227 struct beiscsi_hba *phba; 228 struct iscsi_conn *conn; 229 int rc; 230 231 cls_session = starget_to_session(scsi_target(sc->device)); 232 session = cls_session->dd_data; 233 234 completion_check: 235 /* check if we raced, task just got cleaned up under us */ 236 spin_lock_bh(&session->back_lock); 237 if (!abrt_task || !abrt_task->sc) { 238 spin_unlock_bh(&session->back_lock); 239 return SUCCESS; 240 } 241 /* get a task ref till FW processes the req for the ICD used */ 242 if (!iscsi_get_task(abrt_task)) { 243 spin_unlock(&session->back_lock); 244 /* We are just about to call iscsi_free_task so wait for it. */ 245 udelay(5); 246 goto completion_check; 247 } 248 249 abrt_io_task = abrt_task->dd_data; 250 conn = abrt_task->conn; 251 beiscsi_conn = conn->dd_data; 252 phba = beiscsi_conn->phba; 253 /* mark WRB invalid which have been not processed by FW yet */ 254 if (is_chip_be2_be3r(phba)) { 255 AMAP_SET_BITS(struct amap_iscsi_wrb, invld, 256 abrt_io_task->pwrb_handle->pwrb, 1); 257 } else { 258 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, invld, 259 abrt_io_task->pwrb_handle->pwrb, 1); 260 } 261 inv_tbl.cid = beiscsi_conn->beiscsi_conn_cid; 262 inv_tbl.icd = abrt_io_task->psgl_handle->sgl_index; 263 spin_unlock_bh(&session->back_lock); 264 265 rc = beiscsi_mgmt_invalidate_icds(phba, &inv_tbl, 1); 266 iscsi_put_task(abrt_task); 267 if (rc) { 268 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH, 269 "BM_%d : sc %p invalidation failed %d\n", 270 sc, rc); 271 return FAILED; 272 } 273 274 return iscsi_eh_abort(sc); 275 } 276 277 static int beiscsi_eh_device_reset(struct scsi_cmnd *sc) 278 { 279 struct beiscsi_invldt_cmd_tbl { 280 struct invldt_cmd_tbl tbl[BE_INVLDT_CMD_TBL_SZ]; 281 struct iscsi_task *task[BE_INVLDT_CMD_TBL_SZ]; 282 } *inv_tbl; 283 struct iscsi_cls_session *cls_session; 284 struct beiscsi_conn *beiscsi_conn; 285 struct beiscsi_io_task *io_task; 286 struct iscsi_session *session; 287 struct beiscsi_hba *phba; 288 struct iscsi_conn *conn; 289 struct iscsi_task *task; 290 unsigned int i, nents; 291 int rc, more = 0; 292 293 cls_session = starget_to_session(scsi_target(sc->device)); 294 session = cls_session->dd_data; 295 296 spin_lock_bh(&session->frwd_lock); 297 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) { 298 spin_unlock_bh(&session->frwd_lock); 299 return FAILED; 300 } 301 302 conn = session->leadconn; 303 beiscsi_conn = conn->dd_data; 304 phba = beiscsi_conn->phba; 305 306 inv_tbl = kzalloc_obj(*inv_tbl, GFP_ATOMIC); 307 if (!inv_tbl) { 308 spin_unlock_bh(&session->frwd_lock); 309 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH, 310 "BM_%d : invldt_cmd_tbl alloc failed\n"); 311 return FAILED; 312 } 313 nents = 0; 314 /* take back_lock to prevent task from getting cleaned up under us */ 315 spin_lock(&session->back_lock); 316 for (i = 0; i < conn->session->cmds_max; i++) { 317 task = conn->session->cmds[i]; 318 if (!task->sc) 319 continue; 320 321 if (sc->device->lun != task->sc->device->lun) 322 continue; 323 /** 324 * Can't fit in more cmds? Normally this won't happen b'coz 325 * BEISCSI_CMD_PER_LUN is same as BE_INVLDT_CMD_TBL_SZ. 326 */ 327 if (nents == BE_INVLDT_CMD_TBL_SZ) { 328 more = 1; 329 break; 330 } 331 332 /* get a task ref till FW processes the req for the ICD used */ 333 if (!iscsi_get_task(task)) { 334 /* 335 * The task has completed in the driver and is 336 * completing in libiscsi. Just ignore it here. When we 337 * call iscsi_eh_device_reset, it will wait for us. 338 */ 339 continue; 340 } 341 342 io_task = task->dd_data; 343 /* mark WRB invalid which have been not processed by FW yet */ 344 if (is_chip_be2_be3r(phba)) { 345 AMAP_SET_BITS(struct amap_iscsi_wrb, invld, 346 io_task->pwrb_handle->pwrb, 1); 347 } else { 348 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, invld, 349 io_task->pwrb_handle->pwrb, 1); 350 } 351 352 inv_tbl->tbl[nents].cid = beiscsi_conn->beiscsi_conn_cid; 353 inv_tbl->tbl[nents].icd = io_task->psgl_handle->sgl_index; 354 inv_tbl->task[nents] = task; 355 nents++; 356 } 357 spin_unlock(&session->back_lock); 358 spin_unlock_bh(&session->frwd_lock); 359 360 rc = SUCCESS; 361 if (!nents) 362 goto end_reset; 363 364 if (more) { 365 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH, 366 "BM_%d : number of cmds exceeds size of invalidation table\n"); 367 rc = FAILED; 368 goto end_reset; 369 } 370 371 if (beiscsi_mgmt_invalidate_icds(phba, &inv_tbl->tbl[0], nents)) { 372 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH, 373 "BM_%d : cid %u scmds invalidation failed\n", 374 beiscsi_conn->beiscsi_conn_cid); 375 rc = FAILED; 376 } 377 378 end_reset: 379 for (i = 0; i < nents; i++) 380 iscsi_put_task(inv_tbl->task[i]); 381 kfree(inv_tbl); 382 383 if (rc == SUCCESS) 384 rc = iscsi_eh_device_reset(sc); 385 return rc; 386 } 387 388 /*------------------- PCI Driver operations and data ----------------- */ 389 static const struct pci_device_id beiscsi_pci_id_table[] = { 390 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) }, 391 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) }, 392 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) }, 393 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) }, 394 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) }, 395 { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) }, 396 { 0 } 397 }; 398 MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table); 399 400 401 static const struct scsi_host_template beiscsi_sht = { 402 .module = THIS_MODULE, 403 .name = "Emulex 10Gbe open-iscsi Initiator Driver", 404 .proc_name = DRV_NAME, 405 .queuecommand = iscsi_queuecommand, 406 .change_queue_depth = scsi_change_queue_depth, 407 .target_alloc = iscsi_target_alloc, 408 .eh_timed_out = iscsi_eh_cmd_timed_out, 409 .eh_abort_handler = beiscsi_eh_abort, 410 .eh_device_reset_handler = beiscsi_eh_device_reset, 411 .eh_target_reset_handler = iscsi_eh_session_reset, 412 .shost_groups = beiscsi_groups, 413 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS, 414 .can_queue = BE2_IO_DEPTH, 415 .this_id = -1, 416 .max_sectors = BEISCSI_MAX_SECTORS, 417 .max_segment_size = 65536, 418 .cmd_per_lun = BEISCSI_CMD_PER_LUN, 419 .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID, 420 .track_queue_depth = 1, 421 .cmd_size = sizeof(struct iscsi_cmd), 422 }; 423 424 static struct scsi_transport_template *beiscsi_scsi_transport; 425 426 static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev) 427 { 428 struct beiscsi_hba *phba; 429 struct Scsi_Host *shost; 430 431 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0); 432 if (!shost) { 433 dev_err(&pcidev->dev, 434 "beiscsi_hba_alloc - iscsi_host_alloc failed\n"); 435 return NULL; 436 } 437 shost->max_id = BE2_MAX_SESSIONS - 1; 438 shost->max_channel = 0; 439 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN; 440 shost->max_lun = BEISCSI_NUM_MAX_LUN; 441 shost->transportt = beiscsi_scsi_transport; 442 phba = iscsi_host_priv(shost); 443 memset(phba, 0, sizeof(*phba)); 444 phba->shost = shost; 445 phba->pcidev = pci_dev_get(pcidev); 446 pci_set_drvdata(pcidev, phba); 447 phba->interface_handle = 0xFFFFFFFF; 448 449 return phba; 450 } 451 452 static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba) 453 { 454 if (phba->csr_va) { 455 iounmap(phba->csr_va); 456 phba->csr_va = NULL; 457 } 458 if (phba->db_va) { 459 iounmap(phba->db_va); 460 phba->db_va = NULL; 461 } 462 if (phba->pci_va) { 463 iounmap(phba->pci_va); 464 phba->pci_va = NULL; 465 } 466 } 467 468 static int beiscsi_map_pci_bars(struct beiscsi_hba *phba, 469 struct pci_dev *pcidev) 470 { 471 u8 __iomem *addr; 472 int pcicfg_reg; 473 474 addr = ioremap(pci_resource_start(pcidev, 2), 475 pci_resource_len(pcidev, 2)); 476 if (addr == NULL) 477 return -ENOMEM; 478 phba->ctrl.csr = addr; 479 phba->csr_va = addr; 480 481 addr = ioremap(pci_resource_start(pcidev, 4), 128 * 1024); 482 if (addr == NULL) 483 goto pci_map_err; 484 phba->ctrl.db = addr; 485 phba->db_va = addr; 486 487 if (phba->generation == BE_GEN2) 488 pcicfg_reg = 1; 489 else 490 pcicfg_reg = 0; 491 492 addr = ioremap(pci_resource_start(pcidev, pcicfg_reg), 493 pci_resource_len(pcidev, pcicfg_reg)); 494 495 if (addr == NULL) 496 goto pci_map_err; 497 phba->ctrl.pcicfg = addr; 498 phba->pci_va = addr; 499 return 0; 500 501 pci_map_err: 502 beiscsi_unmap_pci_function(phba); 503 return -ENOMEM; 504 } 505 506 static int beiscsi_enable_pci(struct pci_dev *pcidev) 507 { 508 int ret; 509 510 ret = pci_enable_device(pcidev); 511 if (ret) { 512 dev_err(&pcidev->dev, 513 "beiscsi_enable_pci - enable device failed\n"); 514 return ret; 515 } 516 517 ret = pci_request_regions(pcidev, DRV_NAME); 518 if (ret) { 519 dev_err(&pcidev->dev, 520 "beiscsi_enable_pci - request region failed\n"); 521 goto pci_dev_disable; 522 } 523 524 pci_set_master(pcidev); 525 ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64)); 526 if (ret) { 527 ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)); 528 if (ret) { 529 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n"); 530 goto pci_region_release; 531 } 532 } 533 return 0; 534 535 pci_region_release: 536 pci_release_regions(pcidev); 537 pci_dev_disable: 538 pci_disable_device(pcidev); 539 540 return ret; 541 } 542 543 static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev) 544 { 545 struct be_ctrl_info *ctrl = &phba->ctrl; 546 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced; 547 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem; 548 int status = 0; 549 550 ctrl->pdev = pdev; 551 status = beiscsi_map_pci_bars(phba, pdev); 552 if (status) 553 return status; 554 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16; 555 mbox_mem_alloc->va = dma_alloc_coherent(&pdev->dev, 556 mbox_mem_alloc->size, &mbox_mem_alloc->dma, GFP_KERNEL); 557 if (!mbox_mem_alloc->va) { 558 beiscsi_unmap_pci_function(phba); 559 return -ENOMEM; 560 } 561 562 mbox_mem_align->size = sizeof(struct be_mcc_mailbox); 563 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16); 564 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16); 565 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox)); 566 mutex_init(&ctrl->mbox_lock); 567 spin_lock_init(&phba->ctrl.mcc_lock); 568 569 return status; 570 } 571 572 /** 573 * beiscsi_get_params()- Set the config paramters 574 * @phba: ptr device priv structure 575 **/ 576 static void beiscsi_get_params(struct beiscsi_hba *phba) 577 { 578 uint32_t total_cid_count = 0; 579 uint32_t total_icd_count = 0; 580 uint8_t ulp_num = 0; 581 582 total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) + 583 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1); 584 585 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 586 uint32_t align_mask = 0; 587 uint32_t icd_post_per_page = 0; 588 uint32_t icd_count_unavailable = 0; 589 uint32_t icd_start = 0, icd_count = 0; 590 uint32_t icd_start_align = 0, icd_count_align = 0; 591 592 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 593 icd_start = phba->fw_config.iscsi_icd_start[ulp_num]; 594 icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; 595 596 /* Get ICD count that can be posted on each page */ 597 icd_post_per_page = (PAGE_SIZE / (BE2_SGE * 598 sizeof(struct iscsi_sge))); 599 align_mask = (icd_post_per_page - 1); 600 601 /* Check if icd_start is aligned ICD per page posting */ 602 if (icd_start % icd_post_per_page) { 603 icd_start_align = ((icd_start + 604 icd_post_per_page) & 605 ~(align_mask)); 606 phba->fw_config. 607 iscsi_icd_start[ulp_num] = 608 icd_start_align; 609 } 610 611 icd_count_align = (icd_count & ~align_mask); 612 613 /* ICD discarded in the process of alignment */ 614 if (icd_start_align) 615 icd_count_unavailable = ((icd_start_align - 616 icd_start) + 617 (icd_count - 618 icd_count_align)); 619 620 /* Updated ICD count available */ 621 phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count - 622 icd_count_unavailable); 623 624 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 625 "BM_%d : Aligned ICD values\n" 626 "\t ICD Start : %d\n" 627 "\t ICD Count : %d\n" 628 "\t ICD Discarded : %d\n", 629 phba->fw_config. 630 iscsi_icd_start[ulp_num], 631 phba->fw_config. 632 iscsi_icd_count[ulp_num], 633 icd_count_unavailable); 634 break; 635 } 636 } 637 638 total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; 639 phba->params.ios_per_ctrl = (total_icd_count - 640 (total_cid_count + 641 BE2_TMFS + BE2_NOPOUT_REQ)); 642 phba->params.cxns_per_ctrl = total_cid_count; 643 phba->params.icds_per_ctrl = total_icd_count; 644 phba->params.num_sge_per_io = BE2_SGE; 645 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ; 646 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ; 647 phba->params.num_eq_entries = 1024; 648 phba->params.num_cq_entries = 1024; 649 phba->params.wrbs_per_cxn = 256; 650 } 651 652 static void hwi_ring_eq_db(struct beiscsi_hba *phba, 653 unsigned int id, unsigned int clr_interrupt, 654 unsigned int num_processed, 655 unsigned char rearm, unsigned char event) 656 { 657 u32 val = 0; 658 659 if (rearm) 660 val |= 1 << DB_EQ_REARM_SHIFT; 661 if (clr_interrupt) 662 val |= 1 << DB_EQ_CLR_SHIFT; 663 if (event) 664 val |= 1 << DB_EQ_EVNT_SHIFT; 665 666 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT; 667 /* Setting lower order EQ_ID Bits */ 668 val |= (id & DB_EQ_RING_ID_LOW_MASK); 669 670 /* Setting Higher order EQ_ID Bits */ 671 val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) & 672 DB_EQ_RING_ID_HIGH_MASK) 673 << DB_EQ_HIGH_SET_SHIFT); 674 675 iowrite32(val, phba->db_va + DB_EQ_OFFSET); 676 } 677 678 /** 679 * be_isr_mcc - The isr routine of the driver. 680 * @irq: Not used 681 * @dev_id: Pointer to host adapter structure 682 */ 683 static irqreturn_t be_isr_mcc(int irq, void *dev_id) 684 { 685 struct beiscsi_hba *phba; 686 struct be_eq_entry *eqe; 687 struct be_queue_info *eq; 688 struct be_queue_info *mcc; 689 unsigned int mcc_events; 690 struct be_eq_obj *pbe_eq; 691 692 pbe_eq = dev_id; 693 eq = &pbe_eq->q; 694 phba = pbe_eq->phba; 695 mcc = &phba->ctrl.mcc_obj.cq; 696 eqe = queue_tail_node(eq); 697 698 mcc_events = 0; 699 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 700 & EQE_VALID_MASK) { 701 if (((eqe->dw[offsetof(struct amap_eq_entry, 702 resource_id) / 32] & 703 EQE_RESID_MASK) >> 16) == mcc->id) { 704 mcc_events++; 705 } 706 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 707 queue_tail_inc(eq); 708 eqe = queue_tail_node(eq); 709 } 710 711 if (mcc_events) { 712 queue_work(phba->wq, &pbe_eq->mcc_work); 713 hwi_ring_eq_db(phba, eq->id, 1, mcc_events, 1, 1); 714 } 715 return IRQ_HANDLED; 716 } 717 718 /** 719 * be_isr_msix - The isr routine of the driver. 720 * @irq: Not used 721 * @dev_id: Pointer to host adapter structure 722 */ 723 static irqreturn_t be_isr_msix(int irq, void *dev_id) 724 { 725 struct beiscsi_hba *phba; 726 struct be_queue_info *eq; 727 struct be_eq_obj *pbe_eq; 728 729 pbe_eq = dev_id; 730 eq = &pbe_eq->q; 731 732 phba = pbe_eq->phba; 733 /* disable interrupt till iopoll completes */ 734 hwi_ring_eq_db(phba, eq->id, 1, 0, 0, 1); 735 irq_poll_sched(&pbe_eq->iopoll); 736 737 return IRQ_HANDLED; 738 } 739 740 /** 741 * be_isr - The isr routine of the driver. 742 * @irq: Not used 743 * @dev_id: Pointer to host adapter structure 744 */ 745 static irqreturn_t be_isr(int irq, void *dev_id) 746 { 747 struct beiscsi_hba *phba; 748 struct hwi_controller *phwi_ctrlr; 749 struct hwi_context_memory *phwi_context; 750 struct be_eq_entry *eqe; 751 struct be_queue_info *eq; 752 struct be_queue_info *mcc; 753 unsigned int mcc_events, io_events; 754 struct be_ctrl_info *ctrl; 755 struct be_eq_obj *pbe_eq; 756 int isr, rearm; 757 758 phba = dev_id; 759 ctrl = &phba->ctrl; 760 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET + 761 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE)); 762 if (!isr) 763 return IRQ_NONE; 764 765 phwi_ctrlr = phba->phwi_ctrlr; 766 phwi_context = phwi_ctrlr->phwi_ctxt; 767 pbe_eq = &phwi_context->be_eq[0]; 768 769 eq = &phwi_context->be_eq[0].q; 770 mcc = &phba->ctrl.mcc_obj.cq; 771 eqe = queue_tail_node(eq); 772 773 io_events = 0; 774 mcc_events = 0; 775 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 776 & EQE_VALID_MASK) { 777 if (((eqe->dw[offsetof(struct amap_eq_entry, 778 resource_id) / 32] & EQE_RESID_MASK) >> 16) == mcc->id) 779 mcc_events++; 780 else 781 io_events++; 782 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 783 queue_tail_inc(eq); 784 eqe = queue_tail_node(eq); 785 } 786 if (!io_events && !mcc_events) 787 return IRQ_NONE; 788 789 /* no need to rearm if interrupt is only for IOs */ 790 rearm = 0; 791 if (mcc_events) { 792 queue_work(phba->wq, &pbe_eq->mcc_work); 793 /* rearm for MCCQ */ 794 rearm = 1; 795 } 796 if (io_events) 797 irq_poll_sched(&pbe_eq->iopoll); 798 hwi_ring_eq_db(phba, eq->id, 0, (io_events + mcc_events), rearm, 1); 799 return IRQ_HANDLED; 800 } 801 802 static void beiscsi_free_irqs(struct beiscsi_hba *phba) 803 { 804 struct hwi_context_memory *phwi_context; 805 int i; 806 807 if (!phba->pcidev->msix_enabled) { 808 if (phba->pcidev->irq) 809 free_irq(phba->pcidev->irq, phba); 810 return; 811 } 812 813 phwi_context = phba->phwi_ctrlr->phwi_ctxt; 814 for (i = 0; i <= phba->num_cpus; i++) { 815 free_irq(pci_irq_vector(phba->pcidev, i), 816 &phwi_context->be_eq[i]); 817 kfree(phba->msi_name[i]); 818 } 819 } 820 821 static int beiscsi_init_irqs(struct beiscsi_hba *phba) 822 { 823 struct pci_dev *pcidev = phba->pcidev; 824 struct hwi_controller *phwi_ctrlr; 825 struct hwi_context_memory *phwi_context; 826 int ret, i, j; 827 828 phwi_ctrlr = phba->phwi_ctrlr; 829 phwi_context = phwi_ctrlr->phwi_ctxt; 830 831 if (pcidev->msix_enabled) { 832 for (i = 0; i < phba->num_cpus; i++) { 833 phba->msi_name[i] = kasprintf(GFP_KERNEL, 834 "beiscsi_%02x_%02x", 835 phba->shost->host_no, i); 836 if (!phba->msi_name[i]) { 837 ret = -ENOMEM; 838 goto free_msix_irqs; 839 } 840 841 ret = request_irq(pci_irq_vector(pcidev, i), 842 be_isr_msix, 0, phba->msi_name[i], 843 &phwi_context->be_eq[i]); 844 if (ret) { 845 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 846 "BM_%d : %s-Failed to register msix for i = %d\n", 847 __func__, i); 848 kfree(phba->msi_name[i]); 849 goto free_msix_irqs; 850 } 851 } 852 phba->msi_name[i] = kasprintf(GFP_KERNEL, "beiscsi_mcc_%02x", 853 phba->shost->host_no); 854 if (!phba->msi_name[i]) { 855 ret = -ENOMEM; 856 goto free_msix_irqs; 857 } 858 ret = request_irq(pci_irq_vector(pcidev, i), be_isr_mcc, 0, 859 phba->msi_name[i], &phwi_context->be_eq[i]); 860 if (ret) { 861 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 862 "BM_%d : %s-Failed to register beiscsi_msix_mcc\n", 863 __func__); 864 kfree(phba->msi_name[i]); 865 goto free_msix_irqs; 866 } 867 868 } else { 869 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED, 870 "beiscsi", phba); 871 if (ret) { 872 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 873 "BM_%d : %s-Failed to register irq\n", 874 __func__); 875 return ret; 876 } 877 } 878 return 0; 879 free_msix_irqs: 880 for (j = i - 1; j >= 0; j--) { 881 free_irq(pci_irq_vector(pcidev, i), &phwi_context->be_eq[j]); 882 kfree(phba->msi_name[j]); 883 } 884 return ret; 885 } 886 887 void hwi_ring_cq_db(struct beiscsi_hba *phba, 888 unsigned int id, unsigned int num_processed, 889 unsigned char rearm) 890 { 891 u32 val = 0; 892 893 if (rearm) 894 val |= 1 << DB_CQ_REARM_SHIFT; 895 896 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT; 897 898 /* Setting lower order CQ_ID Bits */ 899 val |= (id & DB_CQ_RING_ID_LOW_MASK); 900 901 /* Setting Higher order CQ_ID Bits */ 902 val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) & 903 DB_CQ_RING_ID_HIGH_MASK) 904 << DB_CQ_HIGH_SET_SHIFT); 905 906 iowrite32(val, phba->db_va + DB_CQ_OFFSET); 907 } 908 909 static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba) 910 { 911 struct sgl_handle *psgl_handle; 912 unsigned long flags; 913 914 spin_lock_irqsave(&phba->io_sgl_lock, flags); 915 if (phba->io_sgl_hndl_avbl) { 916 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, 917 "BM_%d : In alloc_io_sgl_handle," 918 " io_sgl_alloc_index=%d\n", 919 phba->io_sgl_alloc_index); 920 921 psgl_handle = phba->io_sgl_hndl_base[phba-> 922 io_sgl_alloc_index]; 923 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL; 924 phba->io_sgl_hndl_avbl--; 925 if (phba->io_sgl_alloc_index == (phba->params. 926 ios_per_ctrl - 1)) 927 phba->io_sgl_alloc_index = 0; 928 else 929 phba->io_sgl_alloc_index++; 930 } else 931 psgl_handle = NULL; 932 spin_unlock_irqrestore(&phba->io_sgl_lock, flags); 933 return psgl_handle; 934 } 935 936 static void 937 free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) 938 { 939 unsigned long flags; 940 941 spin_lock_irqsave(&phba->io_sgl_lock, flags); 942 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, 943 "BM_%d : In free_,io_sgl_free_index=%d\n", 944 phba->io_sgl_free_index); 945 946 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) { 947 /* 948 * this can happen if clean_task is called on a task that 949 * failed in xmit_task or alloc_pdu. 950 */ 951 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, 952 "BM_%d : Double Free in IO SGL io_sgl_free_index=%d, value there=%p\n", 953 phba->io_sgl_free_index, 954 phba->io_sgl_hndl_base[phba->io_sgl_free_index]); 955 spin_unlock_irqrestore(&phba->io_sgl_lock, flags); 956 return; 957 } 958 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle; 959 phba->io_sgl_hndl_avbl++; 960 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1)) 961 phba->io_sgl_free_index = 0; 962 else 963 phba->io_sgl_free_index++; 964 spin_unlock_irqrestore(&phba->io_sgl_lock, flags); 965 } 966 967 static inline struct wrb_handle * 968 beiscsi_get_wrb_handle(struct hwi_wrb_context *pwrb_context, 969 unsigned int wrbs_per_cxn) 970 { 971 struct wrb_handle *pwrb_handle; 972 unsigned long flags; 973 974 spin_lock_irqsave(&pwrb_context->wrb_lock, flags); 975 if (!pwrb_context->wrb_handles_available) { 976 spin_unlock_irqrestore(&pwrb_context->wrb_lock, flags); 977 return NULL; 978 } 979 pwrb_handle = pwrb_context->pwrb_handle_base[pwrb_context->alloc_index]; 980 pwrb_context->wrb_handles_available--; 981 if (pwrb_context->alloc_index == (wrbs_per_cxn - 1)) 982 pwrb_context->alloc_index = 0; 983 else 984 pwrb_context->alloc_index++; 985 spin_unlock_irqrestore(&pwrb_context->wrb_lock, flags); 986 987 if (pwrb_handle) 988 memset(pwrb_handle->pwrb, 0, sizeof(*pwrb_handle->pwrb)); 989 990 return pwrb_handle; 991 } 992 993 /** 994 * alloc_wrb_handle - To allocate a wrb handle 995 * @phba: The hba pointer 996 * @cid: The cid to use for allocation 997 * @pcontext: ptr to ptr to wrb context 998 * 999 * This happens under session_lock until submission to chip 1000 */ 1001 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid, 1002 struct hwi_wrb_context **pcontext) 1003 { 1004 struct hwi_wrb_context *pwrb_context; 1005 struct hwi_controller *phwi_ctrlr; 1006 uint16_t cri_index = BE_GET_CRI_FROM_CID(cid); 1007 1008 phwi_ctrlr = phba->phwi_ctrlr; 1009 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 1010 /* return the context address */ 1011 *pcontext = pwrb_context; 1012 return beiscsi_get_wrb_handle(pwrb_context, phba->params.wrbs_per_cxn); 1013 } 1014 1015 static inline void 1016 beiscsi_put_wrb_handle(struct hwi_wrb_context *pwrb_context, 1017 struct wrb_handle *pwrb_handle, 1018 unsigned int wrbs_per_cxn) 1019 { 1020 unsigned long flags; 1021 1022 spin_lock_irqsave(&pwrb_context->wrb_lock, flags); 1023 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle; 1024 pwrb_context->wrb_handles_available++; 1025 if (pwrb_context->free_index == (wrbs_per_cxn - 1)) 1026 pwrb_context->free_index = 0; 1027 else 1028 pwrb_context->free_index++; 1029 pwrb_handle->pio_handle = NULL; 1030 spin_unlock_irqrestore(&pwrb_context->wrb_lock, flags); 1031 } 1032 1033 /** 1034 * free_wrb_handle - To free the wrb handle back to pool 1035 * @phba: The hba pointer 1036 * @pwrb_context: The context to free from 1037 * @pwrb_handle: The wrb_handle to free 1038 * 1039 * This happens under session_lock until submission to chip 1040 */ 1041 static void 1042 free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context, 1043 struct wrb_handle *pwrb_handle) 1044 { 1045 beiscsi_put_wrb_handle(pwrb_context, 1046 pwrb_handle, 1047 phba->params.wrbs_per_cxn); 1048 beiscsi_log(phba, KERN_INFO, 1049 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1050 "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x " 1051 "wrb_handles_available=%d\n", 1052 pwrb_handle, pwrb_context->free_index, 1053 pwrb_context->wrb_handles_available); 1054 } 1055 1056 static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba) 1057 { 1058 struct sgl_handle *psgl_handle; 1059 unsigned long flags; 1060 1061 spin_lock_irqsave(&phba->mgmt_sgl_lock, flags); 1062 if (phba->eh_sgl_hndl_avbl) { 1063 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index]; 1064 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL; 1065 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, 1066 "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n", 1067 phba->eh_sgl_alloc_index, 1068 phba->eh_sgl_alloc_index); 1069 1070 phba->eh_sgl_hndl_avbl--; 1071 if (phba->eh_sgl_alloc_index == 1072 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1073 1)) 1074 phba->eh_sgl_alloc_index = 0; 1075 else 1076 phba->eh_sgl_alloc_index++; 1077 } else 1078 psgl_handle = NULL; 1079 spin_unlock_irqrestore(&phba->mgmt_sgl_lock, flags); 1080 return psgl_handle; 1081 } 1082 1083 void 1084 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) 1085 { 1086 unsigned long flags; 1087 1088 spin_lock_irqsave(&phba->mgmt_sgl_lock, flags); 1089 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, 1090 "BM_%d : In free_mgmt_sgl_handle," 1091 "eh_sgl_free_index=%d\n", 1092 phba->eh_sgl_free_index); 1093 1094 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) { 1095 /* 1096 * this can happen if clean_task is called on a task that 1097 * failed in xmit_task or alloc_pdu. 1098 */ 1099 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG, 1100 "BM_%d : Double Free in eh SGL ," 1101 "eh_sgl_free_index=%d\n", 1102 phba->eh_sgl_free_index); 1103 spin_unlock_irqrestore(&phba->mgmt_sgl_lock, flags); 1104 return; 1105 } 1106 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle; 1107 phba->eh_sgl_hndl_avbl++; 1108 if (phba->eh_sgl_free_index == 1109 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1)) 1110 phba->eh_sgl_free_index = 0; 1111 else 1112 phba->eh_sgl_free_index++; 1113 spin_unlock_irqrestore(&phba->mgmt_sgl_lock, flags); 1114 } 1115 1116 static void 1117 be_complete_io(struct beiscsi_conn *beiscsi_conn, 1118 struct iscsi_task *task, 1119 struct common_sol_cqe *csol_cqe) 1120 { 1121 struct beiscsi_io_task *io_task = task->dd_data; 1122 struct be_status_bhs *sts_bhs = 1123 (struct be_status_bhs *)io_task->cmd_bhs; 1124 struct iscsi_conn *conn = beiscsi_conn->conn; 1125 unsigned char *sense; 1126 u32 resid = 0, exp_cmdsn, max_cmdsn; 1127 u8 rsp, status, flags; 1128 1129 exp_cmdsn = csol_cqe->exp_cmdsn; 1130 max_cmdsn = (csol_cqe->exp_cmdsn + 1131 csol_cqe->cmd_wnd - 1); 1132 rsp = csol_cqe->i_resp; 1133 status = csol_cqe->i_sts; 1134 flags = csol_cqe->i_flags; 1135 resid = csol_cqe->res_cnt; 1136 1137 if (!task->sc) { 1138 if (io_task->scsi_cmnd) { 1139 scsi_dma_unmap(io_task->scsi_cmnd); 1140 io_task->scsi_cmnd = NULL; 1141 } 1142 1143 return; 1144 } 1145 task->sc->result = (DID_OK << 16) | status; 1146 if (rsp != ISCSI_STATUS_CMD_COMPLETED) { 1147 task->sc->result = DID_ERROR << 16; 1148 goto unmap; 1149 } 1150 1151 /* bidi not initially supported */ 1152 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) { 1153 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW)) 1154 task->sc->result = DID_ERROR << 16; 1155 1156 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) { 1157 scsi_set_resid(task->sc, resid); 1158 if (!status && (scsi_bufflen(task->sc) - resid < 1159 task->sc->underflow)) 1160 task->sc->result = DID_ERROR << 16; 1161 } 1162 } 1163 1164 if (status == SAM_STAT_CHECK_CONDITION) { 1165 u16 sense_len; 1166 unsigned short *slen = (unsigned short *)sts_bhs->sense_info; 1167 1168 sense = sts_bhs->sense_info + sizeof(unsigned short); 1169 sense_len = be16_to_cpu(*slen); 1170 memcpy(task->sc->sense_buffer, sense, 1171 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE)); 1172 } 1173 1174 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) 1175 conn->rxdata_octets += resid; 1176 unmap: 1177 if (io_task->scsi_cmnd) { 1178 scsi_dma_unmap(io_task->scsi_cmnd); 1179 io_task->scsi_cmnd = NULL; 1180 } 1181 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn); 1182 } 1183 1184 static void 1185 be_complete_logout(struct beiscsi_conn *beiscsi_conn, 1186 struct iscsi_task *task, 1187 struct common_sol_cqe *csol_cqe) 1188 { 1189 struct iscsi_logout_rsp *hdr; 1190 struct beiscsi_io_task *io_task = task->dd_data; 1191 struct iscsi_conn *conn = beiscsi_conn->conn; 1192 1193 hdr = (struct iscsi_logout_rsp *)task->hdr; 1194 hdr->opcode = ISCSI_OP_LOGOUT_RSP; 1195 hdr->t2wait = 5; 1196 hdr->t2retain = 0; 1197 hdr->flags = csol_cqe->i_flags; 1198 hdr->response = csol_cqe->i_resp; 1199 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); 1200 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + 1201 csol_cqe->cmd_wnd - 1); 1202 1203 hdr->dlength[0] = 0; 1204 hdr->dlength[1] = 0; 1205 hdr->dlength[2] = 0; 1206 hdr->hlength = 0; 1207 hdr->itt = io_task->libiscsi_itt; 1208 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); 1209 } 1210 1211 static void 1212 be_complete_tmf(struct beiscsi_conn *beiscsi_conn, 1213 struct iscsi_task *task, 1214 struct common_sol_cqe *csol_cqe) 1215 { 1216 struct iscsi_tm_rsp *hdr; 1217 struct iscsi_conn *conn = beiscsi_conn->conn; 1218 struct beiscsi_io_task *io_task = task->dd_data; 1219 1220 hdr = (struct iscsi_tm_rsp *)task->hdr; 1221 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP; 1222 hdr->flags = csol_cqe->i_flags; 1223 hdr->response = csol_cqe->i_resp; 1224 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); 1225 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + 1226 csol_cqe->cmd_wnd - 1); 1227 1228 hdr->itt = io_task->libiscsi_itt; 1229 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); 1230 } 1231 1232 static void 1233 hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn, 1234 struct beiscsi_hba *phba, struct sol_cqe *psol) 1235 { 1236 struct hwi_wrb_context *pwrb_context; 1237 uint16_t wrb_index, cid, cri_index; 1238 struct hwi_controller *phwi_ctrlr; 1239 struct wrb_handle *pwrb_handle; 1240 struct iscsi_session *session; 1241 struct iscsi_task *task; 1242 1243 phwi_ctrlr = phba->phwi_ctrlr; 1244 if (is_chip_be2_be3r(phba)) { 1245 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe, 1246 wrb_idx, psol); 1247 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe, 1248 cid, psol); 1249 } else { 1250 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2, 1251 wrb_idx, psol); 1252 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2, 1253 cid, psol); 1254 } 1255 1256 cri_index = BE_GET_CRI_FROM_CID(cid); 1257 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 1258 pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index]; 1259 session = beiscsi_conn->conn->session; 1260 spin_lock_bh(&session->back_lock); 1261 task = pwrb_handle->pio_handle; 1262 if (task) 1263 __iscsi_put_task(task); 1264 spin_unlock_bh(&session->back_lock); 1265 } 1266 1267 static void 1268 be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn, 1269 struct iscsi_task *task, 1270 struct common_sol_cqe *csol_cqe) 1271 { 1272 struct iscsi_nopin *hdr; 1273 struct iscsi_conn *conn = beiscsi_conn->conn; 1274 struct beiscsi_io_task *io_task = task->dd_data; 1275 1276 hdr = (struct iscsi_nopin *)task->hdr; 1277 hdr->flags = csol_cqe->i_flags; 1278 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); 1279 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + 1280 csol_cqe->cmd_wnd - 1); 1281 1282 hdr->opcode = ISCSI_OP_NOOP_IN; 1283 hdr->itt = io_task->libiscsi_itt; 1284 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); 1285 } 1286 1287 static void adapter_get_sol_cqe(struct beiscsi_hba *phba, 1288 struct sol_cqe *psol, 1289 struct common_sol_cqe *csol_cqe) 1290 { 1291 if (is_chip_be2_be3r(phba)) { 1292 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe, 1293 i_exp_cmd_sn, psol); 1294 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe, 1295 i_res_cnt, psol); 1296 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe, 1297 i_cmd_wnd, psol); 1298 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe, 1299 wrb_index, psol); 1300 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe, 1301 cid, psol); 1302 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe, 1303 hw_sts, psol); 1304 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe, 1305 i_resp, psol); 1306 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe, 1307 i_sts, psol); 1308 csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe, 1309 i_flags, psol); 1310 } else { 1311 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1312 i_exp_cmd_sn, psol); 1313 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1314 i_res_cnt, psol); 1315 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1316 wrb_index, psol); 1317 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1318 cid, psol); 1319 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1320 hw_sts, psol); 1321 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1322 i_cmd_wnd, psol); 1323 if (AMAP_GET_BITS(struct amap_sol_cqe_v2, 1324 cmd_cmpl, psol)) 1325 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1326 i_sts, psol); 1327 else 1328 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1329 i_sts, psol); 1330 if (AMAP_GET_BITS(struct amap_sol_cqe_v2, 1331 u, psol)) 1332 csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW; 1333 1334 if (AMAP_GET_BITS(struct amap_sol_cqe_v2, 1335 o, psol)) 1336 csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW; 1337 } 1338 } 1339 1340 1341 static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn, 1342 struct beiscsi_hba *phba, struct sol_cqe *psol) 1343 { 1344 struct iscsi_conn *conn = beiscsi_conn->conn; 1345 struct iscsi_session *session = conn->session; 1346 struct common_sol_cqe csol_cqe = {0}; 1347 struct hwi_wrb_context *pwrb_context; 1348 struct hwi_controller *phwi_ctrlr; 1349 struct wrb_handle *pwrb_handle; 1350 struct iscsi_task *task; 1351 uint16_t cri_index = 0; 1352 uint8_t type; 1353 1354 phwi_ctrlr = phba->phwi_ctrlr; 1355 1356 /* Copy the elements to a common structure */ 1357 adapter_get_sol_cqe(phba, psol, &csol_cqe); 1358 1359 cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid); 1360 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 1361 1362 pwrb_handle = pwrb_context->pwrb_handle_basestd[ 1363 csol_cqe.wrb_index]; 1364 1365 spin_lock_bh(&session->back_lock); 1366 task = pwrb_handle->pio_handle; 1367 if (!task) { 1368 spin_unlock_bh(&session->back_lock); 1369 return; 1370 } 1371 type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type; 1372 1373 switch (type) { 1374 case HWH_TYPE_IO: 1375 case HWH_TYPE_IO_RD: 1376 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == 1377 ISCSI_OP_NOOP_OUT) 1378 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe); 1379 else 1380 be_complete_io(beiscsi_conn, task, &csol_cqe); 1381 break; 1382 1383 case HWH_TYPE_LOGOUT: 1384 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT) 1385 be_complete_logout(beiscsi_conn, task, &csol_cqe); 1386 else 1387 be_complete_tmf(beiscsi_conn, task, &csol_cqe); 1388 break; 1389 1390 case HWH_TYPE_LOGIN: 1391 beiscsi_log(phba, KERN_ERR, 1392 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1393 "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in" 1394 " %s- Solicited path\n", __func__); 1395 break; 1396 1397 case HWH_TYPE_NOP: 1398 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe); 1399 break; 1400 1401 default: 1402 beiscsi_log(phba, KERN_WARNING, 1403 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1404 "BM_%d : In %s, unknown type = %d " 1405 "wrb_index 0x%x CID 0x%x\n", __func__, type, 1406 csol_cqe.wrb_index, 1407 csol_cqe.cid); 1408 break; 1409 } 1410 1411 spin_unlock_bh(&session->back_lock); 1412 } 1413 1414 /* 1415 * ASYNC PDUs include 1416 * a. Unsolicited NOP-In (target initiated NOP-In) 1417 * b. ASYNC Messages 1418 * c. Reject PDU 1419 * d. Login response 1420 * These headers arrive unprocessed by the EP firmware. 1421 * iSCSI layer processes them. 1422 */ 1423 static unsigned int 1424 beiscsi_complete_pdu(struct beiscsi_conn *beiscsi_conn, 1425 struct pdu_base *phdr, void *pdata, unsigned int dlen) 1426 { 1427 struct beiscsi_hba *phba = beiscsi_conn->phba; 1428 struct iscsi_conn *conn = beiscsi_conn->conn; 1429 struct beiscsi_io_task *io_task; 1430 struct iscsi_hdr *login_hdr; 1431 struct iscsi_task *task; 1432 u8 code; 1433 1434 code = AMAP_GET_BITS(struct amap_pdu_base, opcode, phdr); 1435 switch (code) { 1436 case ISCSI_OP_NOOP_IN: 1437 pdata = NULL; 1438 dlen = 0; 1439 break; 1440 case ISCSI_OP_ASYNC_EVENT: 1441 break; 1442 case ISCSI_OP_REJECT: 1443 WARN_ON(!pdata); 1444 WARN_ON(!(dlen == 48)); 1445 beiscsi_log(phba, KERN_ERR, 1446 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1447 "BM_%d : In ISCSI_OP_REJECT\n"); 1448 break; 1449 case ISCSI_OP_LOGIN_RSP: 1450 case ISCSI_OP_TEXT_RSP: 1451 task = conn->login_task; 1452 io_task = task->dd_data; 1453 login_hdr = (struct iscsi_hdr *)phdr; 1454 login_hdr->itt = io_task->libiscsi_itt; 1455 break; 1456 default: 1457 beiscsi_log(phba, KERN_WARNING, 1458 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1459 "BM_%d : unrecognized async PDU opcode 0x%x\n", 1460 code); 1461 return 1; 1462 } 1463 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)phdr, pdata, dlen); 1464 return 0; 1465 } 1466 1467 static inline void 1468 beiscsi_hdl_put_handle(struct hd_async_context *pasync_ctx, 1469 struct hd_async_handle *pasync_handle) 1470 { 1471 pasync_handle->is_final = 0; 1472 pasync_handle->buffer_len = 0; 1473 pasync_handle->in_use = 0; 1474 list_del_init(&pasync_handle->link); 1475 } 1476 1477 static void 1478 beiscsi_hdl_purge_handles(struct beiscsi_hba *phba, 1479 struct hd_async_context *pasync_ctx, 1480 u16 cri) 1481 { 1482 struct hd_async_handle *pasync_handle, *tmp_handle; 1483 struct list_head *plist; 1484 1485 plist = &pasync_ctx->async_entry[cri].wq.list; 1486 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) 1487 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle); 1488 1489 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wq.list); 1490 pasync_ctx->async_entry[cri].wq.hdr_len = 0; 1491 pasync_ctx->async_entry[cri].wq.bytes_received = 0; 1492 pasync_ctx->async_entry[cri].wq.bytes_needed = 0; 1493 } 1494 1495 static struct hd_async_handle * 1496 beiscsi_hdl_get_handle(struct beiscsi_conn *beiscsi_conn, 1497 struct hd_async_context *pasync_ctx, 1498 struct i_t_dpdu_cqe *pdpdu_cqe, 1499 u8 *header) 1500 { 1501 struct beiscsi_hba *phba = beiscsi_conn->phba; 1502 struct hd_async_handle *pasync_handle; 1503 struct be_bus_address phys_addr; 1504 u16 cid, code, ci, cri; 1505 u8 final, error = 0; 1506 u32 dpl; 1507 1508 cid = beiscsi_conn->beiscsi_conn_cid; 1509 cri = BE_GET_ASYNC_CRI_FROM_CID(cid); 1510 /** 1511 * This function is invoked to get the right async_handle structure 1512 * from a given DEF PDU CQ entry. 1513 * 1514 * - index in CQ entry gives the vertical index 1515 * - address in CQ entry is the offset where the DMA last ended 1516 * - final - no more notifications for this PDU 1517 */ 1518 if (is_chip_be2_be3r(phba)) { 1519 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1520 dpl, pdpdu_cqe); 1521 ci = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1522 index, pdpdu_cqe); 1523 final = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1524 final, pdpdu_cqe); 1525 } else { 1526 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, 1527 dpl, pdpdu_cqe); 1528 ci = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, 1529 index, pdpdu_cqe); 1530 final = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, 1531 final, pdpdu_cqe); 1532 } 1533 1534 /** 1535 * DB addr Hi/Lo is same for BE and SKH. 1536 * Subtract the dataplacementlength to get to the base. 1537 */ 1538 phys_addr.u.a32.address_lo = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1539 db_addr_lo, pdpdu_cqe); 1540 phys_addr.u.a32.address_lo -= dpl; 1541 phys_addr.u.a32.address_hi = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1542 db_addr_hi, pdpdu_cqe); 1543 1544 code = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, code, pdpdu_cqe); 1545 switch (code) { 1546 case UNSOL_HDR_NOTIFY: 1547 pasync_handle = pasync_ctx->async_entry[ci].header; 1548 *header = 1; 1549 break; 1550 case UNSOL_DATA_DIGEST_ERROR_NOTIFY: 1551 error = 1; 1552 fallthrough; 1553 case UNSOL_DATA_NOTIFY: 1554 pasync_handle = pasync_ctx->async_entry[ci].data; 1555 break; 1556 /* called only for above codes */ 1557 default: 1558 return NULL; 1559 } 1560 1561 if (pasync_handle->pa.u.a64.address != phys_addr.u.a64.address || 1562 pasync_handle->index != ci) { 1563 /* driver bug - if ci does not match async handle index */ 1564 error = 1; 1565 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI, 1566 "BM_%d : cid %u async PDU handle mismatch - addr in %cQE %llx at %u:addr in CQE %llx ci %u\n", 1567 cid, pasync_handle->is_header ? 'H' : 'D', 1568 pasync_handle->pa.u.a64.address, 1569 pasync_handle->index, 1570 phys_addr.u.a64.address, ci); 1571 /* FW has stale address - attempt continuing by dropping */ 1572 } 1573 1574 /** 1575 * DEF PDU header and data buffers with errors should be simply 1576 * dropped as there are no consumers for it. 1577 */ 1578 if (error) { 1579 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle); 1580 return NULL; 1581 } 1582 1583 if (pasync_handle->in_use || !list_empty(&pasync_handle->link)) { 1584 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI, 1585 "BM_%d : cid %d async PDU handle in use - code %d ci %d addr %llx\n", 1586 cid, code, ci, phys_addr.u.a64.address); 1587 beiscsi_hdl_purge_handles(phba, pasync_ctx, cri); 1588 } 1589 1590 list_del_init(&pasync_handle->link); 1591 /** 1592 * Each CID is associated with unique CRI. 1593 * ASYNC_CRI_FROM_CID mapping and CRI_FROM_CID are totaly different. 1594 **/ 1595 pasync_handle->cri = cri; 1596 pasync_handle->is_final = final; 1597 pasync_handle->buffer_len = dpl; 1598 pasync_handle->in_use = 1; 1599 1600 return pasync_handle; 1601 } 1602 1603 static unsigned int 1604 beiscsi_hdl_fwd_pdu(struct beiscsi_conn *beiscsi_conn, 1605 struct hd_async_context *pasync_ctx, 1606 u16 cri) 1607 { 1608 struct iscsi_session *session = beiscsi_conn->conn->session; 1609 struct hd_async_handle *pasync_handle, *plast_handle; 1610 struct beiscsi_hba *phba = beiscsi_conn->phba; 1611 void *phdr = NULL, *pdata = NULL; 1612 u32 dlen = 0, status = 0; 1613 struct list_head *plist; 1614 1615 plist = &pasync_ctx->async_entry[cri].wq.list; 1616 plast_handle = NULL; 1617 list_for_each_entry(pasync_handle, plist, link) { 1618 plast_handle = pasync_handle; 1619 /* get the header, the first entry */ 1620 if (!phdr) { 1621 phdr = pasync_handle->pbuffer; 1622 continue; 1623 } 1624 /* use first buffer to collect all the data */ 1625 if (!pdata) { 1626 pdata = pasync_handle->pbuffer; 1627 dlen = pasync_handle->buffer_len; 1628 continue; 1629 } 1630 if (!pasync_handle->buffer_len || 1631 (dlen + pasync_handle->buffer_len) > 1632 pasync_ctx->async_data.buffer_size) 1633 break; 1634 memcpy(pdata + dlen, pasync_handle->pbuffer, 1635 pasync_handle->buffer_len); 1636 dlen += pasync_handle->buffer_len; 1637 } 1638 1639 if (!plast_handle->is_final) { 1640 /* last handle should have final PDU notification from FW */ 1641 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI, 1642 "BM_%d : cid %u %p fwd async PDU opcode %x with last handle missing - HL%u:DN%u:DR%u\n", 1643 beiscsi_conn->beiscsi_conn_cid, plast_handle, 1644 AMAP_GET_BITS(struct amap_pdu_base, opcode, phdr), 1645 pasync_ctx->async_entry[cri].wq.hdr_len, 1646 pasync_ctx->async_entry[cri].wq.bytes_needed, 1647 pasync_ctx->async_entry[cri].wq.bytes_received); 1648 } 1649 spin_lock_bh(&session->back_lock); 1650 status = beiscsi_complete_pdu(beiscsi_conn, phdr, pdata, dlen); 1651 spin_unlock_bh(&session->back_lock); 1652 beiscsi_hdl_purge_handles(phba, pasync_ctx, cri); 1653 return status; 1654 } 1655 1656 static unsigned int 1657 beiscsi_hdl_gather_pdu(struct beiscsi_conn *beiscsi_conn, 1658 struct hd_async_context *pasync_ctx, 1659 struct hd_async_handle *pasync_handle) 1660 { 1661 unsigned int bytes_needed = 0, status = 0; 1662 u16 cri = pasync_handle->cri; 1663 struct cri_wait_queue *wq; 1664 struct beiscsi_hba *phba; 1665 struct pdu_base *ppdu; 1666 char *err = ""; 1667 1668 phba = beiscsi_conn->phba; 1669 wq = &pasync_ctx->async_entry[cri].wq; 1670 if (pasync_handle->is_header) { 1671 /* check if PDU hdr is rcv'd when old hdr not completed */ 1672 if (wq->hdr_len) { 1673 err = "incomplete"; 1674 goto drop_pdu; 1675 } 1676 ppdu = pasync_handle->pbuffer; 1677 bytes_needed = AMAP_GET_BITS(struct amap_pdu_base, 1678 data_len_hi, ppdu); 1679 bytes_needed <<= 16; 1680 bytes_needed |= be16_to_cpu(AMAP_GET_BITS(struct amap_pdu_base, 1681 data_len_lo, ppdu)); 1682 wq->hdr_len = pasync_handle->buffer_len; 1683 wq->bytes_received = 0; 1684 wq->bytes_needed = bytes_needed; 1685 list_add_tail(&pasync_handle->link, &wq->list); 1686 if (!bytes_needed) 1687 status = beiscsi_hdl_fwd_pdu(beiscsi_conn, 1688 pasync_ctx, cri); 1689 } else { 1690 /* check if data received has header and is needed */ 1691 if (!wq->hdr_len || !wq->bytes_needed) { 1692 err = "header less"; 1693 goto drop_pdu; 1694 } 1695 wq->bytes_received += pasync_handle->buffer_len; 1696 /* Something got overwritten? Better catch it here. */ 1697 if (wq->bytes_received > wq->bytes_needed) { 1698 err = "overflow"; 1699 goto drop_pdu; 1700 } 1701 list_add_tail(&pasync_handle->link, &wq->list); 1702 if (wq->bytes_received == wq->bytes_needed) 1703 status = beiscsi_hdl_fwd_pdu(beiscsi_conn, 1704 pasync_ctx, cri); 1705 } 1706 return status; 1707 1708 drop_pdu: 1709 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_ISCSI, 1710 "BM_%d : cid %u async PDU %s - def-%c:HL%u:DN%u:DR%u\n", 1711 beiscsi_conn->beiscsi_conn_cid, err, 1712 pasync_handle->is_header ? 'H' : 'D', 1713 wq->hdr_len, wq->bytes_needed, 1714 pasync_handle->buffer_len); 1715 /* discard this handle */ 1716 beiscsi_hdl_put_handle(pasync_ctx, pasync_handle); 1717 /* free all the other handles in cri_wait_queue */ 1718 beiscsi_hdl_purge_handles(phba, pasync_ctx, cri); 1719 /* try continuing */ 1720 return status; 1721 } 1722 1723 static void 1724 beiscsi_hdq_post_handles(struct beiscsi_hba *phba, 1725 u8 header, u8 ulp_num, u16 nbuf) 1726 { 1727 struct hd_async_handle *pasync_handle; 1728 struct hd_async_context *pasync_ctx; 1729 struct hwi_controller *phwi_ctrlr; 1730 struct phys_addr *pasync_sge; 1731 u32 ring_id, doorbell = 0; 1732 u32 doorbell_offset; 1733 u16 prod, pi; 1734 1735 phwi_ctrlr = phba->phwi_ctrlr; 1736 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num); 1737 if (header) { 1738 pasync_sge = pasync_ctx->async_header.ring_base; 1739 pi = pasync_ctx->async_header.pi; 1740 ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id; 1741 doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num]. 1742 doorbell_offset; 1743 } else { 1744 pasync_sge = pasync_ctx->async_data.ring_base; 1745 pi = pasync_ctx->async_data.pi; 1746 ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id; 1747 doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num]. 1748 doorbell_offset; 1749 } 1750 1751 for (prod = 0; prod < nbuf; prod++) { 1752 if (header) 1753 pasync_handle = pasync_ctx->async_entry[pi].header; 1754 else 1755 pasync_handle = pasync_ctx->async_entry[pi].data; 1756 WARN_ON(pasync_handle->is_header != header); 1757 WARN_ON(pasync_handle->index != pi); 1758 /* setup the ring only once */ 1759 if (nbuf == pasync_ctx->num_entries) { 1760 /* note hi is lo */ 1761 pasync_sge[pi].hi = pasync_handle->pa.u.a32.address_lo; 1762 pasync_sge[pi].lo = pasync_handle->pa.u.a32.address_hi; 1763 } 1764 if (++pi == pasync_ctx->num_entries) 1765 pi = 0; 1766 } 1767 1768 if (header) 1769 pasync_ctx->async_header.pi = pi; 1770 else 1771 pasync_ctx->async_data.pi = pi; 1772 1773 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK; 1774 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT; 1775 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT; 1776 doorbell |= (prod & DB_DEF_PDU_CQPROC_MASK) << DB_DEF_PDU_CQPROC_SHIFT; 1777 iowrite32(doorbell, phba->db_va + doorbell_offset); 1778 } 1779 1780 static void 1781 beiscsi_hdq_process_compl(struct beiscsi_conn *beiscsi_conn, 1782 struct i_t_dpdu_cqe *pdpdu_cqe) 1783 { 1784 struct beiscsi_hba *phba = beiscsi_conn->phba; 1785 struct hd_async_handle *pasync_handle = NULL; 1786 struct hd_async_context *pasync_ctx; 1787 struct hwi_controller *phwi_ctrlr; 1788 u8 ulp_num, consumed, header = 0; 1789 u16 cid_cri; 1790 1791 phwi_ctrlr = phba->phwi_ctrlr; 1792 cid_cri = BE_GET_CRI_FROM_CID(beiscsi_conn->beiscsi_conn_cid); 1793 ulp_num = BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cid_cri); 1794 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num); 1795 pasync_handle = beiscsi_hdl_get_handle(beiscsi_conn, pasync_ctx, 1796 pdpdu_cqe, &header); 1797 if (is_chip_be2_be3r(phba)) 1798 consumed = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, 1799 num_cons, pdpdu_cqe); 1800 else 1801 consumed = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, 1802 num_cons, pdpdu_cqe); 1803 if (pasync_handle) 1804 beiscsi_hdl_gather_pdu(beiscsi_conn, pasync_ctx, pasync_handle); 1805 /* num_cons indicates number of 8 RQEs consumed */ 1806 if (consumed) 1807 beiscsi_hdq_post_handles(phba, header, ulp_num, 8 * consumed); 1808 } 1809 1810 void beiscsi_process_mcc_cq(struct beiscsi_hba *phba) 1811 { 1812 struct be_queue_info *mcc_cq; 1813 struct be_mcc_compl *mcc_compl; 1814 unsigned int num_processed = 0; 1815 1816 mcc_cq = &phba->ctrl.mcc_obj.cq; 1817 mcc_compl = queue_tail_node(mcc_cq); 1818 mcc_compl->flags = le32_to_cpu(mcc_compl->flags); 1819 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) { 1820 if (beiscsi_hba_in_error(phba)) 1821 return; 1822 1823 if (num_processed >= 32) { 1824 hwi_ring_cq_db(phba, mcc_cq->id, 1825 num_processed, 0); 1826 num_processed = 0; 1827 } 1828 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) { 1829 beiscsi_process_async_event(phba, mcc_compl); 1830 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) { 1831 beiscsi_process_mcc_compl(&phba->ctrl, mcc_compl); 1832 } 1833 1834 mcc_compl->flags = 0; 1835 queue_tail_inc(mcc_cq); 1836 mcc_compl = queue_tail_node(mcc_cq); 1837 mcc_compl->flags = le32_to_cpu(mcc_compl->flags); 1838 num_processed++; 1839 } 1840 1841 if (num_processed > 0) 1842 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1); 1843 } 1844 1845 static void beiscsi_mcc_work(struct work_struct *work) 1846 { 1847 struct be_eq_obj *pbe_eq; 1848 struct beiscsi_hba *phba; 1849 1850 pbe_eq = container_of(work, struct be_eq_obj, mcc_work); 1851 phba = pbe_eq->phba; 1852 beiscsi_process_mcc_cq(phba); 1853 /* rearm EQ for further interrupts */ 1854 if (!beiscsi_hba_in_error(phba)) 1855 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); 1856 } 1857 1858 /** 1859 * beiscsi_process_cq()- Process the Completion Queue 1860 * @pbe_eq: Event Q on which the Completion has come 1861 * @budget: Max number of events to processed 1862 * 1863 * return 1864 * Number of Completion Entries processed. 1865 **/ 1866 unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget) 1867 { 1868 struct be_queue_info *cq; 1869 struct sol_cqe *sol; 1870 unsigned int total = 0; 1871 unsigned int num_processed = 0; 1872 unsigned short code = 0, cid = 0; 1873 uint16_t cri_index = 0; 1874 struct beiscsi_conn *beiscsi_conn; 1875 struct beiscsi_endpoint *beiscsi_ep; 1876 struct iscsi_endpoint *ep; 1877 struct beiscsi_hba *phba; 1878 1879 cq = pbe_eq->cq; 1880 sol = queue_tail_node(cq); 1881 phba = pbe_eq->phba; 1882 1883 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] & 1884 CQE_VALID_MASK) { 1885 if (beiscsi_hba_in_error(phba)) 1886 return 0; 1887 1888 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe)); 1889 1890 code = (sol->dw[offsetof(struct amap_sol_cqe, code) / 32] & 1891 CQE_CODE_MASK); 1892 1893 /* Get the CID */ 1894 if (is_chip_be2_be3r(phba)) { 1895 cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol); 1896 } else { 1897 if ((code == DRIVERMSG_NOTIFY) || 1898 (code == UNSOL_HDR_NOTIFY) || 1899 (code == UNSOL_DATA_NOTIFY)) 1900 cid = AMAP_GET_BITS( 1901 struct amap_i_t_dpdu_cqe_v2, 1902 cid, sol); 1903 else 1904 cid = AMAP_GET_BITS(struct amap_sol_cqe_v2, 1905 cid, sol); 1906 } 1907 1908 cri_index = BE_GET_CRI_FROM_CID(cid); 1909 ep = phba->ep_array[cri_index]; 1910 1911 if (ep == NULL) { 1912 /* connection has already been freed 1913 * just move on to next one 1914 */ 1915 beiscsi_log(phba, KERN_WARNING, 1916 BEISCSI_LOG_INIT, 1917 "BM_%d : proc cqe of disconn ep: cid %d\n", 1918 cid); 1919 goto proc_next_cqe; 1920 } 1921 1922 beiscsi_ep = ep->dd_data; 1923 beiscsi_conn = beiscsi_ep->conn; 1924 1925 /* replenish cq */ 1926 if (num_processed == 32) { 1927 hwi_ring_cq_db(phba, cq->id, 32, 0); 1928 num_processed = 0; 1929 } 1930 total++; 1931 1932 switch (code) { 1933 case SOL_CMD_COMPLETE: 1934 hwi_complete_cmd(beiscsi_conn, phba, sol); 1935 break; 1936 case DRIVERMSG_NOTIFY: 1937 beiscsi_log(phba, KERN_INFO, 1938 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1939 "BM_%d : Received %s[%d] on CID : %d\n", 1940 cqe_desc[code], code, cid); 1941 1942 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol); 1943 break; 1944 case UNSOL_HDR_NOTIFY: 1945 beiscsi_log(phba, KERN_INFO, 1946 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1947 "BM_%d : Received %s[%d] on CID : %d\n", 1948 cqe_desc[code], code, cid); 1949 1950 spin_lock_bh(&phba->async_pdu_lock); 1951 beiscsi_hdq_process_compl(beiscsi_conn, 1952 (struct i_t_dpdu_cqe *)sol); 1953 spin_unlock_bh(&phba->async_pdu_lock); 1954 break; 1955 case UNSOL_DATA_NOTIFY: 1956 beiscsi_log(phba, KERN_INFO, 1957 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1958 "BM_%d : Received %s[%d] on CID : %d\n", 1959 cqe_desc[code], code, cid); 1960 1961 spin_lock_bh(&phba->async_pdu_lock); 1962 beiscsi_hdq_process_compl(beiscsi_conn, 1963 (struct i_t_dpdu_cqe *)sol); 1964 spin_unlock_bh(&phba->async_pdu_lock); 1965 break; 1966 case CXN_INVALIDATE_INDEX_NOTIFY: 1967 case CMD_INVALIDATED_NOTIFY: 1968 case CXN_INVALIDATE_NOTIFY: 1969 beiscsi_log(phba, KERN_ERR, 1970 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1971 "BM_%d : Ignoring %s[%d] on CID : %d\n", 1972 cqe_desc[code], code, cid); 1973 break; 1974 case CXN_KILLED_HDR_DIGEST_ERR: 1975 case SOL_CMD_KILLED_DATA_DIGEST_ERR: 1976 beiscsi_log(phba, KERN_ERR, 1977 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1978 "BM_%d : Cmd Notification %s[%d] on CID : %d\n", 1979 cqe_desc[code], code, cid); 1980 break; 1981 case CMD_KILLED_INVALID_STATSN_RCVD: 1982 case CMD_KILLED_INVALID_R2T_RCVD: 1983 case CMD_CXN_KILLED_LUN_INVALID: 1984 case CMD_CXN_KILLED_ICD_INVALID: 1985 case CMD_CXN_KILLED_ITT_INVALID: 1986 case CMD_CXN_KILLED_SEQ_OUTOFORDER: 1987 case CMD_CXN_KILLED_INVALID_DATASN_RCVD: 1988 beiscsi_log(phba, KERN_ERR, 1989 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 1990 "BM_%d : Cmd Notification %s[%d] on CID : %d\n", 1991 cqe_desc[code], code, cid); 1992 break; 1993 case UNSOL_DATA_DIGEST_ERROR_NOTIFY: 1994 beiscsi_log(phba, KERN_ERR, 1995 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 1996 "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n", 1997 cqe_desc[code], code, cid); 1998 spin_lock_bh(&phba->async_pdu_lock); 1999 /* driver consumes the entry and drops the contents */ 2000 beiscsi_hdq_process_compl(beiscsi_conn, 2001 (struct i_t_dpdu_cqe *)sol); 2002 spin_unlock_bh(&phba->async_pdu_lock); 2003 break; 2004 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL: 2005 case CXN_KILLED_BURST_LEN_MISMATCH: 2006 case CXN_KILLED_AHS_RCVD: 2007 case CXN_KILLED_UNKNOWN_HDR: 2008 case CXN_KILLED_STALE_ITT_TTT_RCVD: 2009 case CXN_KILLED_INVALID_ITT_TTT_RCVD: 2010 case CXN_KILLED_TIMED_OUT: 2011 case CXN_KILLED_FIN_RCVD: 2012 case CXN_KILLED_RST_SENT: 2013 case CXN_KILLED_RST_RCVD: 2014 case CXN_KILLED_BAD_UNSOL_PDU_RCVD: 2015 case CXN_KILLED_BAD_WRB_INDEX_ERROR: 2016 case CXN_KILLED_OVER_RUN_RESIDUAL: 2017 case CXN_KILLED_UNDER_RUN_RESIDUAL: 2018 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN: 2019 beiscsi_log(phba, KERN_ERR, 2020 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2021 "BM_%d : Event %s[%d] received on CID : %d\n", 2022 cqe_desc[code], code, cid); 2023 if (beiscsi_conn) 2024 iscsi_conn_failure(beiscsi_conn->conn, 2025 ISCSI_ERR_CONN_FAILED); 2026 break; 2027 default: 2028 beiscsi_log(phba, KERN_ERR, 2029 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 2030 "BM_%d : Invalid CQE Event Received Code : %d CID 0x%x...\n", 2031 code, cid); 2032 break; 2033 } 2034 2035 proc_next_cqe: 2036 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0); 2037 queue_tail_inc(cq); 2038 sol = queue_tail_node(cq); 2039 num_processed++; 2040 if (total == budget) 2041 break; 2042 } 2043 2044 hwi_ring_cq_db(phba, cq->id, num_processed, 1); 2045 return total; 2046 } 2047 2048 static int be_iopoll(struct irq_poll *iop, int budget) 2049 { 2050 unsigned int ret, io_events; 2051 struct beiscsi_hba *phba; 2052 struct be_eq_obj *pbe_eq; 2053 struct be_eq_entry *eqe = NULL; 2054 struct be_queue_info *eq; 2055 2056 pbe_eq = container_of(iop, struct be_eq_obj, iopoll); 2057 phba = pbe_eq->phba; 2058 if (beiscsi_hba_in_error(phba)) { 2059 irq_poll_complete(iop); 2060 return 0; 2061 } 2062 2063 io_events = 0; 2064 eq = &pbe_eq->q; 2065 eqe = queue_tail_node(eq); 2066 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] & 2067 EQE_VALID_MASK) { 2068 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 2069 queue_tail_inc(eq); 2070 eqe = queue_tail_node(eq); 2071 io_events++; 2072 } 2073 hwi_ring_eq_db(phba, eq->id, 1, io_events, 0, 1); 2074 2075 ret = beiscsi_process_cq(pbe_eq, budget); 2076 pbe_eq->cq_count += ret; 2077 if (ret < budget) { 2078 irq_poll_complete(iop); 2079 beiscsi_log(phba, KERN_INFO, 2080 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, 2081 "BM_%d : rearm pbe_eq->q.id =%d ret %d\n", 2082 pbe_eq->q.id, ret); 2083 if (!beiscsi_hba_in_error(phba)) 2084 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); 2085 } 2086 return ret; 2087 } 2088 2089 static void 2090 hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg, 2091 unsigned int num_sg, struct beiscsi_io_task *io_task) 2092 { 2093 struct iscsi_sge *psgl; 2094 unsigned int sg_len, index; 2095 unsigned int sge_len = 0; 2096 unsigned long long addr; 2097 struct scatterlist *l_sg; 2098 unsigned int offset; 2099 2100 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb, 2101 io_task->bhs_pa.u.a32.address_lo); 2102 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb, 2103 io_task->bhs_pa.u.a32.address_hi); 2104 2105 l_sg = sg; 2106 for (index = 0; (index < num_sg) && (index < 2); index++, 2107 sg = sg_next(sg)) { 2108 if (index == 0) { 2109 sg_len = sg_dma_len(sg); 2110 addr = (u64) sg_dma_address(sg); 2111 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2112 sge0_addr_lo, pwrb, 2113 lower_32_bits(addr)); 2114 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2115 sge0_addr_hi, pwrb, 2116 upper_32_bits(addr)); 2117 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2118 sge0_len, pwrb, 2119 sg_len); 2120 sge_len = sg_len; 2121 } else { 2122 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset, 2123 pwrb, sge_len); 2124 sg_len = sg_dma_len(sg); 2125 addr = (u64) sg_dma_address(sg); 2126 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2127 sge1_addr_lo, pwrb, 2128 lower_32_bits(addr)); 2129 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2130 sge1_addr_hi, pwrb, 2131 upper_32_bits(addr)); 2132 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 2133 sge1_len, pwrb, 2134 sg_len); 2135 } 2136 } 2137 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2138 memset(psgl, 0, sizeof(*psgl) * BE2_SGE); 2139 2140 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); 2141 2142 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2143 io_task->bhs_pa.u.a32.address_hi); 2144 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2145 io_task->bhs_pa.u.a32.address_lo); 2146 2147 if (num_sg == 1) { 2148 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, 2149 1); 2150 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, 2151 0); 2152 } else if (num_sg == 2) { 2153 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, 2154 0); 2155 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, 2156 1); 2157 } else { 2158 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, 2159 0); 2160 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, 2161 0); 2162 } 2163 2164 sg = l_sg; 2165 psgl++; 2166 psgl++; 2167 offset = 0; 2168 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { 2169 sg_len = sg_dma_len(sg); 2170 addr = (u64) sg_dma_address(sg); 2171 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2172 lower_32_bits(addr)); 2173 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2174 upper_32_bits(addr)); 2175 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); 2176 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); 2177 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2178 offset += sg_len; 2179 } 2180 psgl--; 2181 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2182 } 2183 2184 static void 2185 hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg, 2186 unsigned int num_sg, struct beiscsi_io_task *io_task) 2187 { 2188 struct iscsi_sge *psgl; 2189 unsigned int sg_len, index; 2190 unsigned int sge_len = 0; 2191 unsigned long long addr; 2192 struct scatterlist *l_sg; 2193 unsigned int offset; 2194 2195 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, 2196 io_task->bhs_pa.u.a32.address_lo); 2197 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, 2198 io_task->bhs_pa.u.a32.address_hi); 2199 2200 l_sg = sg; 2201 for (index = 0; (index < num_sg) && (index < 2); index++, 2202 sg = sg_next(sg)) { 2203 if (index == 0) { 2204 sg_len = sg_dma_len(sg); 2205 addr = (u64) sg_dma_address(sg); 2206 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, 2207 ((u32)(addr & 0xFFFFFFFF))); 2208 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, 2209 ((u32)(addr >> 32))); 2210 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, 2211 sg_len); 2212 sge_len = sg_len; 2213 } else { 2214 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset, 2215 pwrb, sge_len); 2216 sg_len = sg_dma_len(sg); 2217 addr = (u64) sg_dma_address(sg); 2218 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb, 2219 ((u32)(addr & 0xFFFFFFFF))); 2220 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb, 2221 ((u32)(addr >> 32))); 2222 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb, 2223 sg_len); 2224 } 2225 } 2226 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2227 memset(psgl, 0, sizeof(*psgl) * BE2_SGE); 2228 2229 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); 2230 2231 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2232 io_task->bhs_pa.u.a32.address_hi); 2233 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2234 io_task->bhs_pa.u.a32.address_lo); 2235 2236 if (num_sg == 1) { 2237 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2238 1); 2239 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2240 0); 2241 } else if (num_sg == 2) { 2242 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2243 0); 2244 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2245 1); 2246 } else { 2247 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 2248 0); 2249 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, 2250 0); 2251 } 2252 sg = l_sg; 2253 psgl++; 2254 psgl++; 2255 offset = 0; 2256 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { 2257 sg_len = sg_dma_len(sg); 2258 addr = (u64) sg_dma_address(sg); 2259 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2260 (addr & 0xFFFFFFFF)); 2261 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2262 (addr >> 32)); 2263 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); 2264 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); 2265 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2266 offset += sg_len; 2267 } 2268 psgl--; 2269 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2270 } 2271 2272 /** 2273 * hwi_write_buffer()- Populate the WRB with task info 2274 * @pwrb: ptr to the WRB entry 2275 * @task: iscsi task which is to be executed 2276 **/ 2277 static int hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task) 2278 { 2279 struct iscsi_sge *psgl; 2280 struct beiscsi_io_task *io_task = task->dd_data; 2281 struct beiscsi_conn *beiscsi_conn = io_task->conn; 2282 struct beiscsi_hba *phba = beiscsi_conn->phba; 2283 uint8_t dsp_value = 0; 2284 2285 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2; 2286 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, 2287 io_task->bhs_pa.u.a32.address_lo); 2288 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, 2289 io_task->bhs_pa.u.a32.address_hi); 2290 2291 if (task->data) { 2292 2293 /* Check for the data_count */ 2294 dsp_value = (task->data_count) ? 1 : 0; 2295 2296 if (is_chip_be2_be3r(phba)) 2297 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, 2298 pwrb, dsp_value); 2299 else 2300 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, 2301 pwrb, dsp_value); 2302 2303 /* Map addr only if there is data_count */ 2304 if (dsp_value) { 2305 io_task->mtask_addr = dma_map_single(&phba->pcidev->dev, 2306 task->data, 2307 task->data_count, 2308 DMA_TO_DEVICE); 2309 if (dma_mapping_error(&phba->pcidev->dev, 2310 io_task->mtask_addr)) 2311 return -ENOMEM; 2312 io_task->mtask_data_count = task->data_count; 2313 } else 2314 io_task->mtask_addr = 0; 2315 2316 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, 2317 lower_32_bits(io_task->mtask_addr)); 2318 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, 2319 upper_32_bits(io_task->mtask_addr)); 2320 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, 2321 task->data_count); 2322 2323 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1); 2324 } else { 2325 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); 2326 io_task->mtask_addr = 0; 2327 } 2328 2329 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; 2330 2331 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len); 2332 2333 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2334 io_task->bhs_pa.u.a32.address_hi); 2335 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2336 io_task->bhs_pa.u.a32.address_lo); 2337 if (task->data) { 2338 psgl++; 2339 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0); 2340 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0); 2341 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0); 2342 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0); 2343 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0); 2344 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); 2345 2346 psgl++; 2347 if (task->data) { 2348 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 2349 lower_32_bits(io_task->mtask_addr)); 2350 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 2351 upper_32_bits(io_task->mtask_addr)); 2352 } 2353 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106); 2354 } 2355 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); 2356 return 0; 2357 } 2358 2359 /** 2360 * beiscsi_find_mem_req()- Find mem needed 2361 * @phba: ptr to HBA struct 2362 **/ 2363 static void beiscsi_find_mem_req(struct beiscsi_hba *phba) 2364 { 2365 uint8_t mem_descr_index, ulp_num; 2366 unsigned int num_async_pdu_buf_pages; 2367 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn; 2368 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages; 2369 2370 phba->params.hwi_ws_sz = sizeof(struct hwi_controller); 2371 2372 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 * 2373 BE_ISCSI_PDU_HEADER_SIZE; 2374 phba->mem_req[HWI_MEM_ADDN_CONTEXT] = 2375 sizeof(struct hwi_context_memory); 2376 2377 2378 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb) 2379 * (phba->params.wrbs_per_cxn) 2380 * phba->params.cxns_per_ctrl; 2381 wrb_sz_per_cxn = sizeof(struct wrb_handle) * 2382 (phba->params.wrbs_per_cxn); 2383 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) * 2384 phba->params.cxns_per_ctrl); 2385 2386 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) * 2387 phba->params.icds_per_ctrl; 2388 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) * 2389 phba->params.num_sge_per_io * phba->params.icds_per_ctrl; 2390 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 2391 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 2392 2393 num_async_pdu_buf_sgl_pages = 2394 PAGES_REQUIRED(BEISCSI_ASYNC_HDQ_SIZE( 2395 phba, ulp_num) * 2396 sizeof(struct phys_addr)); 2397 2398 num_async_pdu_buf_pages = 2399 PAGES_REQUIRED(BEISCSI_ASYNC_HDQ_SIZE( 2400 phba, ulp_num) * 2401 phba->params.defpdu_hdr_sz); 2402 2403 num_async_pdu_data_pages = 2404 PAGES_REQUIRED(BEISCSI_ASYNC_HDQ_SIZE( 2405 phba, ulp_num) * 2406 phba->params.defpdu_data_sz); 2407 2408 num_async_pdu_data_sgl_pages = 2409 PAGES_REQUIRED(BEISCSI_ASYNC_HDQ_SIZE( 2410 phba, ulp_num) * 2411 sizeof(struct phys_addr)); 2412 2413 mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 + 2414 (ulp_num * MEM_DESCR_OFFSET)); 2415 phba->mem_req[mem_descr_index] = 2416 BEISCSI_GET_CID_COUNT(phba, ulp_num) * 2417 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE; 2418 2419 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 + 2420 (ulp_num * MEM_DESCR_OFFSET)); 2421 phba->mem_req[mem_descr_index] = 2422 num_async_pdu_buf_pages * 2423 PAGE_SIZE; 2424 2425 mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 + 2426 (ulp_num * MEM_DESCR_OFFSET)); 2427 phba->mem_req[mem_descr_index] = 2428 num_async_pdu_data_pages * 2429 PAGE_SIZE; 2430 2431 mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 + 2432 (ulp_num * MEM_DESCR_OFFSET)); 2433 phba->mem_req[mem_descr_index] = 2434 num_async_pdu_buf_sgl_pages * 2435 PAGE_SIZE; 2436 2437 mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 + 2438 (ulp_num * MEM_DESCR_OFFSET)); 2439 phba->mem_req[mem_descr_index] = 2440 num_async_pdu_data_sgl_pages * 2441 PAGE_SIZE; 2442 2443 mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 + 2444 (ulp_num * MEM_DESCR_OFFSET)); 2445 phba->mem_req[mem_descr_index] = 2446 BEISCSI_ASYNC_HDQ_SIZE(phba, ulp_num) * 2447 sizeof(struct hd_async_handle); 2448 2449 mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 + 2450 (ulp_num * MEM_DESCR_OFFSET)); 2451 phba->mem_req[mem_descr_index] = 2452 BEISCSI_ASYNC_HDQ_SIZE(phba, ulp_num) * 2453 sizeof(struct hd_async_handle); 2454 2455 mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 + 2456 (ulp_num * MEM_DESCR_OFFSET)); 2457 phba->mem_req[mem_descr_index] = 2458 sizeof(struct hd_async_context) + 2459 (BEISCSI_ASYNC_HDQ_SIZE(phba, ulp_num) * 2460 sizeof(struct hd_async_entry)); 2461 } 2462 } 2463 } 2464 2465 static int beiscsi_alloc_mem(struct beiscsi_hba *phba) 2466 { 2467 dma_addr_t bus_add; 2468 struct hwi_controller *phwi_ctrlr; 2469 struct be_mem_descriptor *mem_descr; 2470 struct mem_array *mem_arr, *mem_arr_orig; 2471 unsigned int i, j, alloc_size, curr_alloc_size; 2472 2473 phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL); 2474 if (!phba->phwi_ctrlr) 2475 return -ENOMEM; 2476 2477 /* Allocate memory for wrb_context */ 2478 phwi_ctrlr = phba->phwi_ctrlr; 2479 phwi_ctrlr->wrb_context = kzalloc_objs(struct hwi_wrb_context, 2480 phba->params.cxns_per_ctrl); 2481 if (!phwi_ctrlr->wrb_context) { 2482 kfree(phba->phwi_ctrlr); 2483 return -ENOMEM; 2484 } 2485 2486 phba->init_mem = kzalloc_objs(*mem_descr, SE_MEM_MAX); 2487 if (!phba->init_mem) { 2488 kfree(phwi_ctrlr->wrb_context); 2489 kfree(phba->phwi_ctrlr); 2490 return -ENOMEM; 2491 } 2492 2493 mem_arr_orig = kmalloc_objs(*mem_arr_orig, BEISCSI_MAX_FRAGS_INIT); 2494 if (!mem_arr_orig) { 2495 kfree(phba->init_mem); 2496 kfree(phwi_ctrlr->wrb_context); 2497 kfree(phba->phwi_ctrlr); 2498 return -ENOMEM; 2499 } 2500 2501 mem_descr = phba->init_mem; 2502 for (i = 0; i < SE_MEM_MAX; i++) { 2503 if (!phba->mem_req[i]) { 2504 mem_descr->mem_array = NULL; 2505 mem_descr++; 2506 continue; 2507 } 2508 2509 j = 0; 2510 mem_arr = mem_arr_orig; 2511 alloc_size = phba->mem_req[i]; 2512 memset(mem_arr, 0, sizeof(struct mem_array) * 2513 BEISCSI_MAX_FRAGS_INIT); 2514 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size); 2515 do { 2516 mem_arr->virtual_address = 2517 dma_alloc_coherent(&phba->pcidev->dev, 2518 curr_alloc_size, &bus_add, GFP_KERNEL); 2519 if (!mem_arr->virtual_address) { 2520 if (curr_alloc_size <= BE_MIN_MEM_SIZE) 2521 goto free_mem; 2522 if (curr_alloc_size - 2523 rounddown_pow_of_two(curr_alloc_size)) 2524 curr_alloc_size = rounddown_pow_of_two 2525 (curr_alloc_size); 2526 else 2527 curr_alloc_size = curr_alloc_size / 2; 2528 } else { 2529 mem_arr->bus_address.u. 2530 a64.address = (__u64) bus_add; 2531 mem_arr->size = curr_alloc_size; 2532 alloc_size -= curr_alloc_size; 2533 curr_alloc_size = min(be_max_phys_size * 2534 1024, alloc_size); 2535 j++; 2536 mem_arr++; 2537 } 2538 } while (alloc_size); 2539 mem_descr->num_elements = j; 2540 mem_descr->size_in_bytes = phba->mem_req[i]; 2541 mem_descr->mem_array = kmalloc_objs(*mem_arr, j); 2542 if (!mem_descr->mem_array) 2543 goto free_mem; 2544 2545 memcpy(mem_descr->mem_array, mem_arr_orig, 2546 sizeof(struct mem_array) * j); 2547 mem_descr++; 2548 } 2549 kfree(mem_arr_orig); 2550 return 0; 2551 free_mem: 2552 mem_descr->num_elements = j; 2553 while ((i) || (j)) { 2554 for (j = mem_descr->num_elements; j > 0; j--) { 2555 dma_free_coherent(&phba->pcidev->dev, 2556 mem_descr->mem_array[j - 1].size, 2557 mem_descr->mem_array[j - 1]. 2558 virtual_address, 2559 (unsigned long)mem_descr-> 2560 mem_array[j - 1]. 2561 bus_address.u.a64.address); 2562 } 2563 if (i) { 2564 i--; 2565 kfree(mem_descr->mem_array); 2566 mem_descr--; 2567 } 2568 } 2569 kfree(mem_arr_orig); 2570 kfree(phba->init_mem); 2571 kfree(phba->phwi_ctrlr->wrb_context); 2572 kfree(phba->phwi_ctrlr); 2573 return -ENOMEM; 2574 } 2575 2576 static int beiscsi_get_memory(struct beiscsi_hba *phba) 2577 { 2578 beiscsi_find_mem_req(phba); 2579 return beiscsi_alloc_mem(phba); 2580 } 2581 2582 static void iscsi_init_global_templates(struct beiscsi_hba *phba) 2583 { 2584 struct pdu_data_out *pdata_out; 2585 struct pdu_nop_out *pnop_out; 2586 struct be_mem_descriptor *mem_descr; 2587 2588 mem_descr = phba->init_mem; 2589 mem_descr += ISCSI_MEM_GLOBAL_HEADER; 2590 pdata_out = 2591 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address; 2592 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE); 2593 2594 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out, 2595 IIOC_SCSI_DATA); 2596 2597 pnop_out = 2598 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0]. 2599 virtual_address + BE_ISCSI_PDU_HEADER_SIZE); 2600 2601 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE); 2602 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF); 2603 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1); 2604 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0); 2605 } 2606 2607 static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba) 2608 { 2609 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb; 2610 struct hwi_context_memory *phwi_ctxt; 2611 struct wrb_handle *pwrb_handle = NULL; 2612 struct hwi_controller *phwi_ctrlr; 2613 struct hwi_wrb_context *pwrb_context; 2614 struct iscsi_wrb *pwrb = NULL; 2615 unsigned int num_cxn_wrbh = 0; 2616 unsigned int num_cxn_wrb = 0, j, idx = 0, index; 2617 2618 mem_descr_wrbh = phba->init_mem; 2619 mem_descr_wrbh += HWI_MEM_WRBH; 2620 2621 mem_descr_wrb = phba->init_mem; 2622 mem_descr_wrb += HWI_MEM_WRB; 2623 phwi_ctrlr = phba->phwi_ctrlr; 2624 2625 /* Allocate memory for WRBQ */ 2626 phwi_ctxt = phwi_ctrlr->phwi_ctxt; 2627 phwi_ctxt->be_wrbq = kzalloc_objs(struct be_queue_info, 2628 phba->params.cxns_per_ctrl); 2629 if (!phwi_ctxt->be_wrbq) { 2630 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 2631 "BM_%d : WRBQ Mem Alloc Failed\n"); 2632 return -ENOMEM; 2633 } 2634 2635 for (index = 0; index < phba->params.cxns_per_ctrl; index++) { 2636 pwrb_context = &phwi_ctrlr->wrb_context[index]; 2637 pwrb_context->pwrb_handle_base = 2638 kzalloc_objs(struct wrb_handle *, 2639 phba->params.wrbs_per_cxn); 2640 if (!pwrb_context->pwrb_handle_base) { 2641 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 2642 "BM_%d : Mem Alloc Failed. Failing to load\n"); 2643 goto init_wrb_hndl_failed; 2644 } 2645 pwrb_context->pwrb_handle_basestd = 2646 kzalloc_objs(struct wrb_handle *, 2647 phba->params.wrbs_per_cxn); 2648 if (!pwrb_context->pwrb_handle_basestd) { 2649 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 2650 "BM_%d : Mem Alloc Failed. Failing to load\n"); 2651 goto init_wrb_hndl_failed; 2652 } 2653 if (!num_cxn_wrbh) { 2654 pwrb_handle = 2655 mem_descr_wrbh->mem_array[idx].virtual_address; 2656 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) / 2657 ((sizeof(struct wrb_handle)) * 2658 phba->params.wrbs_per_cxn)); 2659 idx++; 2660 } 2661 pwrb_context->alloc_index = 0; 2662 pwrb_context->wrb_handles_available = 0; 2663 pwrb_context->free_index = 0; 2664 2665 if (num_cxn_wrbh) { 2666 for (j = 0; j < phba->params.wrbs_per_cxn; j++) { 2667 pwrb_context->pwrb_handle_base[j] = pwrb_handle; 2668 pwrb_context->pwrb_handle_basestd[j] = 2669 pwrb_handle; 2670 pwrb_context->wrb_handles_available++; 2671 pwrb_handle->wrb_index = j; 2672 pwrb_handle++; 2673 } 2674 num_cxn_wrbh--; 2675 } 2676 spin_lock_init(&pwrb_context->wrb_lock); 2677 } 2678 idx = 0; 2679 for (index = 0; index < phba->params.cxns_per_ctrl; index++) { 2680 pwrb_context = &phwi_ctrlr->wrb_context[index]; 2681 if (!num_cxn_wrb) { 2682 pwrb = mem_descr_wrb->mem_array[idx].virtual_address; 2683 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) / 2684 ((sizeof(struct iscsi_wrb) * 2685 phba->params.wrbs_per_cxn)); 2686 idx++; 2687 } 2688 2689 if (num_cxn_wrb) { 2690 for (j = 0; j < phba->params.wrbs_per_cxn; j++) { 2691 pwrb_handle = pwrb_context->pwrb_handle_base[j]; 2692 pwrb_handle->pwrb = pwrb; 2693 pwrb++; 2694 } 2695 num_cxn_wrb--; 2696 } 2697 } 2698 return 0; 2699 init_wrb_hndl_failed: 2700 for (j = index; j > 0; j--) { 2701 pwrb_context = &phwi_ctrlr->wrb_context[j]; 2702 kfree(pwrb_context->pwrb_handle_base); 2703 kfree(pwrb_context->pwrb_handle_basestd); 2704 } 2705 kfree(phwi_ctxt->be_wrbq); 2706 return -ENOMEM; 2707 } 2708 2709 static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba) 2710 { 2711 uint8_t ulp_num; 2712 struct hwi_controller *phwi_ctrlr; 2713 struct hba_parameters *p = &phba->params; 2714 struct hd_async_context *pasync_ctx; 2715 struct hd_async_handle *pasync_header_h, *pasync_data_h; 2716 unsigned int index, idx, num_per_mem, num_async_data; 2717 struct be_mem_descriptor *mem_descr; 2718 2719 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 2720 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 2721 /* get async_ctx for each ULP */ 2722 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2723 mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 + 2724 (ulp_num * MEM_DESCR_OFFSET)); 2725 2726 phwi_ctrlr = phba->phwi_ctrlr; 2727 phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] = 2728 (struct hd_async_context *) 2729 mem_descr->mem_array[0].virtual_address; 2730 2731 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num]; 2732 memset(pasync_ctx, 0, sizeof(*pasync_ctx)); 2733 2734 pasync_ctx->async_entry = 2735 (struct hd_async_entry *) 2736 ((long unsigned int)pasync_ctx + 2737 sizeof(struct hd_async_context)); 2738 2739 pasync_ctx->num_entries = BEISCSI_ASYNC_HDQ_SIZE(phba, 2740 ulp_num); 2741 /* setup header buffers */ 2742 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2743 mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 + 2744 (ulp_num * MEM_DESCR_OFFSET); 2745 if (mem_descr->mem_array[0].virtual_address) { 2746 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2747 "BM_%d : hwi_init_async_pdu_ctx" 2748 " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n", 2749 ulp_num, 2750 mem_descr->mem_array[0]. 2751 virtual_address); 2752 } else 2753 beiscsi_log(phba, KERN_WARNING, 2754 BEISCSI_LOG_INIT, 2755 "BM_%d : No Virtual address for ULP : %d\n", 2756 ulp_num); 2757 2758 pasync_ctx->async_header.pi = 0; 2759 pasync_ctx->async_header.buffer_size = p->defpdu_hdr_sz; 2760 pasync_ctx->async_header.va_base = 2761 mem_descr->mem_array[0].virtual_address; 2762 2763 pasync_ctx->async_header.pa_base.u.a64.address = 2764 mem_descr->mem_array[0]. 2765 bus_address.u.a64.address; 2766 2767 /* setup header buffer sgls */ 2768 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2769 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 + 2770 (ulp_num * MEM_DESCR_OFFSET); 2771 if (mem_descr->mem_array[0].virtual_address) { 2772 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2773 "BM_%d : hwi_init_async_pdu_ctx" 2774 " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n", 2775 ulp_num, 2776 mem_descr->mem_array[0]. 2777 virtual_address); 2778 } else 2779 beiscsi_log(phba, KERN_WARNING, 2780 BEISCSI_LOG_INIT, 2781 "BM_%d : No Virtual address for ULP : %d\n", 2782 ulp_num); 2783 2784 pasync_ctx->async_header.ring_base = 2785 mem_descr->mem_array[0].virtual_address; 2786 2787 /* setup header buffer handles */ 2788 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2789 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 + 2790 (ulp_num * MEM_DESCR_OFFSET); 2791 if (mem_descr->mem_array[0].virtual_address) { 2792 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2793 "BM_%d : hwi_init_async_pdu_ctx" 2794 " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n", 2795 ulp_num, 2796 mem_descr->mem_array[0]. 2797 virtual_address); 2798 } else 2799 beiscsi_log(phba, KERN_WARNING, 2800 BEISCSI_LOG_INIT, 2801 "BM_%d : No Virtual address for ULP : %d\n", 2802 ulp_num); 2803 2804 pasync_ctx->async_header.handle_base = 2805 mem_descr->mem_array[0].virtual_address; 2806 2807 /* setup data buffer sgls */ 2808 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2809 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 + 2810 (ulp_num * MEM_DESCR_OFFSET); 2811 if (mem_descr->mem_array[0].virtual_address) { 2812 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2813 "BM_%d : hwi_init_async_pdu_ctx" 2814 " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n", 2815 ulp_num, 2816 mem_descr->mem_array[0]. 2817 virtual_address); 2818 } else 2819 beiscsi_log(phba, KERN_WARNING, 2820 BEISCSI_LOG_INIT, 2821 "BM_%d : No Virtual address for ULP : %d\n", 2822 ulp_num); 2823 2824 pasync_ctx->async_data.ring_base = 2825 mem_descr->mem_array[0].virtual_address; 2826 2827 /* setup data buffer handles */ 2828 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2829 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 + 2830 (ulp_num * MEM_DESCR_OFFSET); 2831 if (!mem_descr->mem_array[0].virtual_address) 2832 beiscsi_log(phba, KERN_WARNING, 2833 BEISCSI_LOG_INIT, 2834 "BM_%d : No Virtual address for ULP : %d\n", 2835 ulp_num); 2836 2837 pasync_ctx->async_data.handle_base = 2838 mem_descr->mem_array[0].virtual_address; 2839 2840 pasync_header_h = 2841 (struct hd_async_handle *) 2842 pasync_ctx->async_header.handle_base; 2843 pasync_data_h = 2844 (struct hd_async_handle *) 2845 pasync_ctx->async_data.handle_base; 2846 2847 /* setup data buffers */ 2848 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 2849 mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 + 2850 (ulp_num * MEM_DESCR_OFFSET); 2851 if (mem_descr->mem_array[0].virtual_address) { 2852 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 2853 "BM_%d : hwi_init_async_pdu_ctx" 2854 " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n", 2855 ulp_num, 2856 mem_descr->mem_array[0]. 2857 virtual_address); 2858 } else 2859 beiscsi_log(phba, KERN_WARNING, 2860 BEISCSI_LOG_INIT, 2861 "BM_%d : No Virtual address for ULP : %d\n", 2862 ulp_num); 2863 2864 idx = 0; 2865 pasync_ctx->async_data.pi = 0; 2866 pasync_ctx->async_data.buffer_size = p->defpdu_data_sz; 2867 pasync_ctx->async_data.va_base = 2868 mem_descr->mem_array[idx].virtual_address; 2869 pasync_ctx->async_data.pa_base.u.a64.address = 2870 mem_descr->mem_array[idx]. 2871 bus_address.u.a64.address; 2872 2873 num_async_data = ((mem_descr->mem_array[idx].size) / 2874 phba->params.defpdu_data_sz); 2875 num_per_mem = 0; 2876 2877 for (index = 0; index < BEISCSI_ASYNC_HDQ_SIZE 2878 (phba, ulp_num); index++) { 2879 pasync_header_h->cri = -1; 2880 pasync_header_h->is_header = 1; 2881 pasync_header_h->index = index; 2882 INIT_LIST_HEAD(&pasync_header_h->link); 2883 pasync_header_h->pbuffer = 2884 (void *)((unsigned long) 2885 (pasync_ctx-> 2886 async_header.va_base) + 2887 (p->defpdu_hdr_sz * index)); 2888 2889 pasync_header_h->pa.u.a64.address = 2890 pasync_ctx->async_header.pa_base.u.a64. 2891 address + (p->defpdu_hdr_sz * index); 2892 2893 pasync_ctx->async_entry[index].header = 2894 pasync_header_h; 2895 pasync_header_h++; 2896 INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. 2897 wq.list); 2898 2899 pasync_data_h->cri = -1; 2900 pasync_data_h->is_header = 0; 2901 pasync_data_h->index = index; 2902 INIT_LIST_HEAD(&pasync_data_h->link); 2903 2904 if (!num_async_data) { 2905 num_per_mem = 0; 2906 idx++; 2907 pasync_ctx->async_data.va_base = 2908 mem_descr->mem_array[idx]. 2909 virtual_address; 2910 pasync_ctx->async_data.pa_base.u. 2911 a64.address = 2912 mem_descr->mem_array[idx]. 2913 bus_address.u.a64.address; 2914 num_async_data = 2915 ((mem_descr->mem_array[idx]. 2916 size) / 2917 phba->params.defpdu_data_sz); 2918 } 2919 pasync_data_h->pbuffer = 2920 (void *)((unsigned long) 2921 (pasync_ctx->async_data.va_base) + 2922 (p->defpdu_data_sz * num_per_mem)); 2923 2924 pasync_data_h->pa.u.a64.address = 2925 pasync_ctx->async_data.pa_base.u.a64. 2926 address + (p->defpdu_data_sz * 2927 num_per_mem); 2928 num_per_mem++; 2929 num_async_data--; 2930 2931 pasync_ctx->async_entry[index].data = 2932 pasync_data_h; 2933 pasync_data_h++; 2934 } 2935 } 2936 } 2937 2938 return 0; 2939 } 2940 2941 static int 2942 be_sgl_create_contiguous(void *virtual_address, 2943 u64 physical_address, u32 length, 2944 struct be_dma_mem *sgl) 2945 { 2946 WARN_ON(!virtual_address); 2947 WARN_ON(!physical_address); 2948 WARN_ON(!length); 2949 WARN_ON(!sgl); 2950 2951 sgl->va = virtual_address; 2952 sgl->dma = (unsigned long)physical_address; 2953 sgl->size = length; 2954 2955 return 0; 2956 } 2957 2958 static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl) 2959 { 2960 memset(sgl, 0, sizeof(*sgl)); 2961 } 2962 2963 static void 2964 hwi_build_be_sgl_arr(struct beiscsi_hba *phba, 2965 struct mem_array *pmem, struct be_dma_mem *sgl) 2966 { 2967 if (sgl->va) 2968 be_sgl_destroy_contiguous(sgl); 2969 2970 be_sgl_create_contiguous(pmem->virtual_address, 2971 pmem->bus_address.u.a64.address, 2972 pmem->size, sgl); 2973 } 2974 2975 static void 2976 hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba, 2977 struct mem_array *pmem, struct be_dma_mem *sgl) 2978 { 2979 if (sgl->va) 2980 be_sgl_destroy_contiguous(sgl); 2981 2982 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address, 2983 pmem->bus_address.u.a64.address, 2984 pmem->size, sgl); 2985 } 2986 2987 static int be_fill_queue(struct be_queue_info *q, 2988 u16 len, u16 entry_size, void *vaddress) 2989 { 2990 struct be_dma_mem *mem = &q->dma_mem; 2991 2992 memset(q, 0, sizeof(*q)); 2993 q->len = len; 2994 q->entry_size = entry_size; 2995 mem->size = len * entry_size; 2996 mem->va = vaddress; 2997 if (!mem->va) 2998 return -ENOMEM; 2999 memset(mem->va, 0, mem->size); 3000 return 0; 3001 } 3002 3003 static int beiscsi_create_eqs(struct beiscsi_hba *phba, 3004 struct hwi_context_memory *phwi_context) 3005 { 3006 int ret = -ENOMEM, eq_for_mcc; 3007 unsigned int i, num_eq_pages; 3008 struct be_queue_info *eq; 3009 struct be_dma_mem *mem; 3010 void *eq_vaddress; 3011 dma_addr_t paddr; 3012 3013 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * 3014 sizeof(struct be_eq_entry)); 3015 3016 if (phba->pcidev->msix_enabled) 3017 eq_for_mcc = 1; 3018 else 3019 eq_for_mcc = 0; 3020 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { 3021 eq = &phwi_context->be_eq[i].q; 3022 mem = &eq->dma_mem; 3023 phwi_context->be_eq[i].phba = phba; 3024 eq_vaddress = dma_alloc_coherent(&phba->pcidev->dev, 3025 num_eq_pages * PAGE_SIZE, 3026 &paddr, GFP_KERNEL); 3027 if (!eq_vaddress) { 3028 ret = -ENOMEM; 3029 goto create_eq_error; 3030 } 3031 3032 mem->va = eq_vaddress; 3033 ret = be_fill_queue(eq, phba->params.num_eq_entries, 3034 sizeof(struct be_eq_entry), eq_vaddress); 3035 if (ret) { 3036 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3037 "BM_%d : be_fill_queue Failed for EQ\n"); 3038 goto create_eq_error; 3039 } 3040 3041 mem->dma = paddr; 3042 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq, 3043 BEISCSI_EQ_DELAY_DEF); 3044 if (ret) { 3045 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3046 "BM_%d : beiscsi_cmd_eq_create Failed for EQ\n"); 3047 goto create_eq_error; 3048 } 3049 3050 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3051 "BM_%d : eqid = %d\n", 3052 phwi_context->be_eq[i].q.id); 3053 } 3054 return 0; 3055 3056 create_eq_error: 3057 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { 3058 eq = &phwi_context->be_eq[i].q; 3059 mem = &eq->dma_mem; 3060 if (mem->va) 3061 dma_free_coherent(&phba->pcidev->dev, num_eq_pages 3062 * PAGE_SIZE, 3063 mem->va, mem->dma); 3064 } 3065 return ret; 3066 } 3067 3068 static int beiscsi_create_cqs(struct beiscsi_hba *phba, 3069 struct hwi_context_memory *phwi_context) 3070 { 3071 unsigned int i, num_cq_pages; 3072 struct be_queue_info *cq, *eq; 3073 struct be_dma_mem *mem; 3074 struct be_eq_obj *pbe_eq; 3075 void *cq_vaddress; 3076 int ret = -ENOMEM; 3077 dma_addr_t paddr; 3078 3079 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * 3080 sizeof(struct sol_cqe)); 3081 3082 for (i = 0; i < phba->num_cpus; i++) { 3083 cq = &phwi_context->be_cq[i]; 3084 eq = &phwi_context->be_eq[i].q; 3085 pbe_eq = &phwi_context->be_eq[i]; 3086 pbe_eq->cq = cq; 3087 pbe_eq->phba = phba; 3088 mem = &cq->dma_mem; 3089 cq_vaddress = dma_alloc_coherent(&phba->pcidev->dev, 3090 num_cq_pages * PAGE_SIZE, 3091 &paddr, GFP_KERNEL); 3092 if (!cq_vaddress) { 3093 ret = -ENOMEM; 3094 goto create_cq_error; 3095 } 3096 3097 ret = be_fill_queue(cq, phba->params.num_cq_entries, 3098 sizeof(struct sol_cqe), cq_vaddress); 3099 if (ret) { 3100 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3101 "BM_%d : be_fill_queue Failed for ISCSI CQ\n"); 3102 goto create_cq_error; 3103 } 3104 3105 mem->dma = paddr; 3106 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false, 3107 false, 0); 3108 if (ret) { 3109 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3110 "BM_%d : beiscsi_cmd_eq_create Failed for ISCSI CQ\n"); 3111 goto create_cq_error; 3112 } 3113 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3114 "BM_%d : iscsi cq_id is %d for eq_id %d\n" 3115 "iSCSI CQ CREATED\n", cq->id, eq->id); 3116 } 3117 return 0; 3118 3119 create_cq_error: 3120 for (i = 0; i < phba->num_cpus; i++) { 3121 cq = &phwi_context->be_cq[i]; 3122 mem = &cq->dma_mem; 3123 if (mem->va) 3124 dma_free_coherent(&phba->pcidev->dev, num_cq_pages 3125 * PAGE_SIZE, 3126 mem->va, mem->dma); 3127 } 3128 return ret; 3129 } 3130 3131 static int 3132 beiscsi_create_def_hdr(struct beiscsi_hba *phba, 3133 struct hwi_context_memory *phwi_context, 3134 struct hwi_controller *phwi_ctrlr, 3135 unsigned int def_pdu_ring_sz, uint8_t ulp_num) 3136 { 3137 unsigned int idx; 3138 int ret; 3139 struct be_queue_info *dq, *cq; 3140 struct be_dma_mem *mem; 3141 struct be_mem_descriptor *mem_descr; 3142 void *dq_vaddress; 3143 3144 idx = 0; 3145 dq = &phwi_context->be_def_hdrq[ulp_num]; 3146 cq = &phwi_context->be_cq[0]; 3147 mem = &dq->dma_mem; 3148 mem_descr = phba->init_mem; 3149 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 + 3150 (ulp_num * MEM_DESCR_OFFSET); 3151 dq_vaddress = mem_descr->mem_array[idx].virtual_address; 3152 ret = be_fill_queue(dq, mem_descr->mem_array[0].size / 3153 sizeof(struct phys_addr), 3154 sizeof(struct phys_addr), dq_vaddress); 3155 if (ret) { 3156 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3157 "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n", 3158 ulp_num); 3159 3160 return ret; 3161 } 3162 mem->dma = (unsigned long)mem_descr->mem_array[idx]. 3163 bus_address.u.a64.address; 3164 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq, 3165 def_pdu_ring_sz, 3166 phba->params.defpdu_hdr_sz, 3167 BEISCSI_DEFQ_HDR, ulp_num); 3168 if (ret) { 3169 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3170 "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n", 3171 ulp_num); 3172 3173 return ret; 3174 } 3175 3176 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3177 "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n", 3178 ulp_num, 3179 phwi_context->be_def_hdrq[ulp_num].id); 3180 return 0; 3181 } 3182 3183 static int 3184 beiscsi_create_def_data(struct beiscsi_hba *phba, 3185 struct hwi_context_memory *phwi_context, 3186 struct hwi_controller *phwi_ctrlr, 3187 unsigned int def_pdu_ring_sz, uint8_t ulp_num) 3188 { 3189 unsigned int idx; 3190 int ret; 3191 struct be_queue_info *dataq, *cq; 3192 struct be_dma_mem *mem; 3193 struct be_mem_descriptor *mem_descr; 3194 void *dq_vaddress; 3195 3196 idx = 0; 3197 dataq = &phwi_context->be_def_dataq[ulp_num]; 3198 cq = &phwi_context->be_cq[0]; 3199 mem = &dataq->dma_mem; 3200 mem_descr = phba->init_mem; 3201 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 + 3202 (ulp_num * MEM_DESCR_OFFSET); 3203 dq_vaddress = mem_descr->mem_array[idx].virtual_address; 3204 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size / 3205 sizeof(struct phys_addr), 3206 sizeof(struct phys_addr), dq_vaddress); 3207 if (ret) { 3208 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3209 "BM_%d : be_fill_queue Failed for DEF PDU " 3210 "DATA on ULP : %d\n", 3211 ulp_num); 3212 3213 return ret; 3214 } 3215 mem->dma = (unsigned long)mem_descr->mem_array[idx]. 3216 bus_address.u.a64.address; 3217 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq, 3218 def_pdu_ring_sz, 3219 phba->params.defpdu_data_sz, 3220 BEISCSI_DEFQ_DATA, ulp_num); 3221 if (ret) { 3222 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3223 "BM_%d be_cmd_create_default_pdu_queue" 3224 " Failed for DEF PDU DATA on ULP : %d\n", 3225 ulp_num); 3226 return ret; 3227 } 3228 3229 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3230 "BM_%d : iscsi def data id on ULP : %d is %d\n", 3231 ulp_num, 3232 phwi_context->be_def_dataq[ulp_num].id); 3233 3234 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3235 "BM_%d : DEFAULT PDU DATA RING CREATED on ULP : %d\n", 3236 ulp_num); 3237 return 0; 3238 } 3239 3240 3241 static int 3242 beiscsi_post_template_hdr(struct beiscsi_hba *phba) 3243 { 3244 struct be_mem_descriptor *mem_descr; 3245 struct mem_array *pm_arr; 3246 struct be_dma_mem sgl; 3247 int status, ulp_num; 3248 3249 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3250 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3251 mem_descr = (struct be_mem_descriptor *)phba->init_mem; 3252 mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 + 3253 (ulp_num * MEM_DESCR_OFFSET); 3254 pm_arr = mem_descr->mem_array; 3255 3256 hwi_build_be_sgl_arr(phba, pm_arr, &sgl); 3257 status = be_cmd_iscsi_post_template_hdr( 3258 &phba->ctrl, &sgl); 3259 3260 if (status != 0) { 3261 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3262 "BM_%d : Post Template HDR Failed for " 3263 "ULP_%d\n", ulp_num); 3264 return status; 3265 } 3266 3267 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3268 "BM_%d : Template HDR Pages Posted for " 3269 "ULP_%d\n", ulp_num); 3270 } 3271 } 3272 return 0; 3273 } 3274 3275 static int 3276 beiscsi_post_pages(struct beiscsi_hba *phba) 3277 { 3278 struct be_mem_descriptor *mem_descr; 3279 struct mem_array *pm_arr; 3280 unsigned int page_offset, i; 3281 struct be_dma_mem sgl; 3282 int status, ulp_num = 0; 3283 3284 mem_descr = phba->init_mem; 3285 mem_descr += HWI_MEM_SGE; 3286 pm_arr = mem_descr->mem_array; 3287 3288 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 3289 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) 3290 break; 3291 3292 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io * 3293 phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE; 3294 for (i = 0; i < mem_descr->num_elements; i++) { 3295 hwi_build_be_sgl_arr(phba, pm_arr, &sgl); 3296 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl, 3297 page_offset, 3298 (pm_arr->size / PAGE_SIZE)); 3299 page_offset += pm_arr->size / PAGE_SIZE; 3300 if (status != 0) { 3301 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3302 "BM_%d : post sgl failed.\n"); 3303 return status; 3304 } 3305 pm_arr++; 3306 } 3307 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3308 "BM_%d : POSTED PAGES\n"); 3309 return 0; 3310 } 3311 3312 static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q) 3313 { 3314 struct be_dma_mem *mem = &q->dma_mem; 3315 if (mem->va) { 3316 dma_free_coherent(&phba->pcidev->dev, mem->size, 3317 mem->va, mem->dma); 3318 mem->va = NULL; 3319 } 3320 } 3321 3322 static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q, 3323 u16 len, u16 entry_size) 3324 { 3325 struct be_dma_mem *mem = &q->dma_mem; 3326 3327 memset(q, 0, sizeof(*q)); 3328 q->len = len; 3329 q->entry_size = entry_size; 3330 mem->size = len * entry_size; 3331 mem->va = dma_alloc_coherent(&phba->pcidev->dev, mem->size, &mem->dma, 3332 GFP_KERNEL); 3333 if (!mem->va) 3334 return -ENOMEM; 3335 return 0; 3336 } 3337 3338 static int 3339 beiscsi_create_wrb_rings(struct beiscsi_hba *phba, 3340 struct hwi_context_memory *phwi_context, 3341 struct hwi_controller *phwi_ctrlr) 3342 { 3343 unsigned int num_wrb_rings; 3344 u64 pa_addr_lo; 3345 unsigned int idx, num, i, ulp_num; 3346 struct mem_array *pwrb_arr; 3347 void *wrb_vaddr; 3348 struct be_dma_mem sgl; 3349 struct be_mem_descriptor *mem_descr; 3350 struct hwi_wrb_context *pwrb_context; 3351 int status; 3352 uint8_t ulp_count = 0, ulp_base_num = 0; 3353 uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 }; 3354 3355 idx = 0; 3356 mem_descr = phba->init_mem; 3357 mem_descr += HWI_MEM_WRB; 3358 pwrb_arr = kmalloc_objs(*pwrb_arr, phba->params.cxns_per_ctrl); 3359 if (!pwrb_arr) { 3360 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3361 "BM_%d : Memory alloc failed in create wrb ring.\n"); 3362 return -ENOMEM; 3363 } 3364 wrb_vaddr = mem_descr->mem_array[idx].virtual_address; 3365 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address; 3366 num_wrb_rings = mem_descr->mem_array[idx].size / 3367 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb)); 3368 3369 for (num = 0; num < phba->params.cxns_per_ctrl; num++) { 3370 if (num_wrb_rings) { 3371 pwrb_arr[num].virtual_address = wrb_vaddr; 3372 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo; 3373 pwrb_arr[num].size = phba->params.wrbs_per_cxn * 3374 sizeof(struct iscsi_wrb); 3375 wrb_vaddr += pwrb_arr[num].size; 3376 pa_addr_lo += pwrb_arr[num].size; 3377 num_wrb_rings--; 3378 } else { 3379 idx++; 3380 wrb_vaddr = mem_descr->mem_array[idx].virtual_address; 3381 pa_addr_lo = mem_descr->mem_array[idx]. 3382 bus_address.u.a64.address; 3383 num_wrb_rings = mem_descr->mem_array[idx].size / 3384 (phba->params.wrbs_per_cxn * 3385 sizeof(struct iscsi_wrb)); 3386 pwrb_arr[num].virtual_address = wrb_vaddr; 3387 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo; 3388 pwrb_arr[num].size = phba->params.wrbs_per_cxn * 3389 sizeof(struct iscsi_wrb); 3390 wrb_vaddr += pwrb_arr[num].size; 3391 pa_addr_lo += pwrb_arr[num].size; 3392 num_wrb_rings--; 3393 } 3394 } 3395 3396 /* Get the ULP Count */ 3397 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 3398 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3399 ulp_count++; 3400 ulp_base_num = ulp_num; 3401 cid_count_ulp[ulp_num] = 3402 BEISCSI_GET_CID_COUNT(phba, ulp_num); 3403 } 3404 3405 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 3406 if (ulp_count > 1) { 3407 ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT; 3408 3409 if (!cid_count_ulp[ulp_base_num]) 3410 ulp_base_num = (ulp_base_num + 1) % 3411 BEISCSI_ULP_COUNT; 3412 3413 cid_count_ulp[ulp_base_num]--; 3414 } 3415 3416 3417 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl); 3418 status = be_cmd_wrbq_create(&phba->ctrl, &sgl, 3419 &phwi_context->be_wrbq[i], 3420 &phwi_ctrlr->wrb_context[i], 3421 ulp_base_num); 3422 if (status != 0) { 3423 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3424 "BM_%d : wrbq create failed."); 3425 kfree(pwrb_arr); 3426 return status; 3427 } 3428 pwrb_context = &phwi_ctrlr->wrb_context[i]; 3429 BE_SET_CID_TO_CRI(i, pwrb_context->cid); 3430 } 3431 kfree(pwrb_arr); 3432 return 0; 3433 } 3434 3435 static void free_wrb_handles(struct beiscsi_hba *phba) 3436 { 3437 unsigned int index; 3438 struct hwi_controller *phwi_ctrlr; 3439 struct hwi_wrb_context *pwrb_context; 3440 3441 phwi_ctrlr = phba->phwi_ctrlr; 3442 for (index = 0; index < phba->params.cxns_per_ctrl; index++) { 3443 pwrb_context = &phwi_ctrlr->wrb_context[index]; 3444 kfree(pwrb_context->pwrb_handle_base); 3445 kfree(pwrb_context->pwrb_handle_basestd); 3446 } 3447 } 3448 3449 static void be_mcc_queues_destroy(struct beiscsi_hba *phba) 3450 { 3451 struct be_ctrl_info *ctrl = &phba->ctrl; 3452 struct be_dma_mem *ptag_mem; 3453 struct be_queue_info *q; 3454 int i, tag; 3455 3456 q = &phba->ctrl.mcc_obj.q; 3457 for (i = 0; i < MAX_MCC_CMD; i++) { 3458 tag = i + 1; 3459 if (!test_bit(MCC_TAG_STATE_RUNNING, 3460 &ctrl->ptag_state[tag].tag_state)) 3461 continue; 3462 3463 if (test_bit(MCC_TAG_STATE_TIMEOUT, 3464 &ctrl->ptag_state[tag].tag_state)) { 3465 ptag_mem = &ctrl->ptag_state[tag].tag_mem_state; 3466 if (ptag_mem->size) { 3467 dma_free_coherent(&ctrl->pdev->dev, 3468 ptag_mem->size, 3469 ptag_mem->va, 3470 ptag_mem->dma); 3471 ptag_mem->size = 0; 3472 } 3473 continue; 3474 } 3475 /** 3476 * If MCC is still active and waiting then wake up the process. 3477 * We are here only because port is going offline. The process 3478 * sees that (BEISCSI_HBA_ONLINE is cleared) and EIO error is 3479 * returned for the operation and allocated memory cleaned up. 3480 */ 3481 if (waitqueue_active(&ctrl->mcc_wait[tag])) { 3482 ctrl->mcc_tag_status[tag] = MCC_STATUS_FAILED; 3483 ctrl->mcc_tag_status[tag] |= CQE_VALID_MASK; 3484 wake_up_interruptible(&ctrl->mcc_wait[tag]); 3485 /* 3486 * Control tag info gets reinitialized in enable 3487 * so wait for the process to clear running state. 3488 */ 3489 while (test_bit(MCC_TAG_STATE_RUNNING, 3490 &ctrl->ptag_state[tag].tag_state)) 3491 schedule_timeout_uninterruptible(HZ); 3492 } 3493 /** 3494 * For MCC with tag_states MCC_TAG_STATE_ASYNC and 3495 * MCC_TAG_STATE_IGNORE nothing needs to done. 3496 */ 3497 } 3498 if (q->created) { 3499 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ); 3500 be_queue_free(phba, q); 3501 } 3502 3503 q = &phba->ctrl.mcc_obj.cq; 3504 if (q->created) { 3505 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); 3506 be_queue_free(phba, q); 3507 } 3508 } 3509 3510 static int be_mcc_queues_create(struct beiscsi_hba *phba, 3511 struct hwi_context_memory *phwi_context) 3512 { 3513 struct be_queue_info *q, *cq; 3514 struct be_ctrl_info *ctrl = &phba->ctrl; 3515 3516 /* Alloc MCC compl queue */ 3517 cq = &phba->ctrl.mcc_obj.cq; 3518 if (be_queue_alloc(phba, cq, MCC_CQ_LEN, 3519 sizeof(struct be_mcc_compl))) 3520 goto err; 3521 /* Ask BE to create MCC compl queue; */ 3522 if (phba->pcidev->msix_enabled) { 3523 if (beiscsi_cmd_cq_create(ctrl, cq, 3524 &phwi_context->be_eq[phba->num_cpus].q, 3525 false, true, 0)) 3526 goto mcc_cq_free; 3527 } else { 3528 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q, 3529 false, true, 0)) 3530 goto mcc_cq_free; 3531 } 3532 3533 /* Alloc MCC queue */ 3534 q = &phba->ctrl.mcc_obj.q; 3535 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb))) 3536 goto mcc_cq_destroy; 3537 3538 /* Ask BE to create MCC queue */ 3539 if (beiscsi_cmd_mccq_create(phba, q, cq)) 3540 goto mcc_q_free; 3541 3542 return 0; 3543 3544 mcc_q_free: 3545 be_queue_free(phba, q); 3546 mcc_cq_destroy: 3547 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ); 3548 mcc_cq_free: 3549 be_queue_free(phba, cq); 3550 err: 3551 return -ENOMEM; 3552 } 3553 3554 static void be2iscsi_enable_msix(struct beiscsi_hba *phba) 3555 { 3556 int nvec = 1; 3557 3558 switch (phba->generation) { 3559 case BE_GEN2: 3560 case BE_GEN3: 3561 nvec = BEISCSI_MAX_NUM_CPUS + 1; 3562 break; 3563 case BE_GEN4: 3564 nvec = phba->fw_config.eqid_count; 3565 break; 3566 default: 3567 nvec = 2; 3568 break; 3569 } 3570 3571 /* if eqid_count == 1 fall back to INTX */ 3572 if (enable_msix && nvec > 1) { 3573 struct irq_affinity desc = { .post_vectors = 1 }; 3574 3575 if (pci_alloc_irq_vectors_affinity(phba->pcidev, 2, nvec, 3576 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc) < 0) { 3577 phba->num_cpus = nvec - 1; 3578 return; 3579 } 3580 } 3581 3582 phba->num_cpus = 1; 3583 } 3584 3585 static void hwi_purge_eq(struct beiscsi_hba *phba) 3586 { 3587 struct hwi_controller *phwi_ctrlr; 3588 struct hwi_context_memory *phwi_context; 3589 struct be_queue_info *eq; 3590 struct be_eq_entry *eqe = NULL; 3591 int i, eq_msix; 3592 unsigned int num_processed; 3593 3594 if (beiscsi_hba_in_error(phba)) 3595 return; 3596 3597 phwi_ctrlr = phba->phwi_ctrlr; 3598 phwi_context = phwi_ctrlr->phwi_ctxt; 3599 if (phba->pcidev->msix_enabled) 3600 eq_msix = 1; 3601 else 3602 eq_msix = 0; 3603 3604 for (i = 0; i < (phba->num_cpus + eq_msix); i++) { 3605 eq = &phwi_context->be_eq[i].q; 3606 eqe = queue_tail_node(eq); 3607 num_processed = 0; 3608 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] 3609 & EQE_VALID_MASK) { 3610 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); 3611 queue_tail_inc(eq); 3612 eqe = queue_tail_node(eq); 3613 num_processed++; 3614 } 3615 3616 if (num_processed) 3617 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1); 3618 } 3619 } 3620 3621 static void hwi_cleanup_port(struct beiscsi_hba *phba) 3622 { 3623 struct be_queue_info *q; 3624 struct be_ctrl_info *ctrl = &phba->ctrl; 3625 struct hwi_controller *phwi_ctrlr; 3626 struct hwi_context_memory *phwi_context; 3627 int i, eq_for_mcc, ulp_num; 3628 3629 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 3630 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) 3631 beiscsi_cmd_iscsi_cleanup(phba, ulp_num); 3632 3633 /** 3634 * Purge all EQ entries that may have been left out. This is to 3635 * workaround a problem we've seen occasionally where driver gets an 3636 * interrupt with EQ entry bit set after stopping the controller. 3637 */ 3638 hwi_purge_eq(phba); 3639 3640 phwi_ctrlr = phba->phwi_ctrlr; 3641 phwi_context = phwi_ctrlr->phwi_ctxt; 3642 3643 be_cmd_iscsi_remove_template_hdr(ctrl); 3644 3645 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 3646 q = &phwi_context->be_wrbq[i]; 3647 if (q->created) 3648 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ); 3649 } 3650 kfree(phwi_context->be_wrbq); 3651 free_wrb_handles(phba); 3652 3653 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3654 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3655 3656 q = &phwi_context->be_def_hdrq[ulp_num]; 3657 if (q->created) 3658 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); 3659 3660 q = &phwi_context->be_def_dataq[ulp_num]; 3661 if (q->created) 3662 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); 3663 } 3664 } 3665 3666 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); 3667 3668 for (i = 0; i < (phba->num_cpus); i++) { 3669 q = &phwi_context->be_cq[i]; 3670 if (q->created) { 3671 be_queue_free(phba, q); 3672 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); 3673 } 3674 } 3675 3676 be_mcc_queues_destroy(phba); 3677 if (phba->pcidev->msix_enabled) 3678 eq_for_mcc = 1; 3679 else 3680 eq_for_mcc = 0; 3681 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { 3682 q = &phwi_context->be_eq[i].q; 3683 if (q->created) { 3684 be_queue_free(phba, q); 3685 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ); 3686 } 3687 } 3688 /* this ensures complete FW cleanup */ 3689 beiscsi_cmd_function_reset(phba); 3690 /* last communication, indicate driver is unloading */ 3691 beiscsi_cmd_special_wrb(&phba->ctrl, 0); 3692 } 3693 3694 static int hwi_init_port(struct beiscsi_hba *phba) 3695 { 3696 struct hwi_controller *phwi_ctrlr; 3697 struct hwi_context_memory *phwi_context; 3698 unsigned int def_pdu_ring_sz; 3699 struct be_ctrl_info *ctrl = &phba->ctrl; 3700 int status, ulp_num; 3701 u16 nbufs; 3702 3703 phwi_ctrlr = phba->phwi_ctrlr; 3704 phwi_context = phwi_ctrlr->phwi_ctxt; 3705 /* set port optic state to unknown */ 3706 phba->optic_state = 0xff; 3707 3708 status = beiscsi_create_eqs(phba, phwi_context); 3709 if (status != 0) { 3710 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3711 "BM_%d : EQ not created\n"); 3712 goto error; 3713 } 3714 3715 status = be_mcc_queues_create(phba, phwi_context); 3716 if (status != 0) 3717 goto error; 3718 3719 status = beiscsi_check_supported_fw(ctrl, phba); 3720 if (status != 0) { 3721 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3722 "BM_%d : Unsupported fw version\n"); 3723 goto error; 3724 } 3725 3726 status = beiscsi_create_cqs(phba, phwi_context); 3727 if (status != 0) { 3728 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3729 "BM_%d : CQ not created\n"); 3730 goto error; 3731 } 3732 3733 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3734 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3735 nbufs = phwi_context->pasync_ctx[ulp_num]->num_entries; 3736 def_pdu_ring_sz = nbufs * sizeof(struct phys_addr); 3737 3738 status = beiscsi_create_def_hdr(phba, phwi_context, 3739 phwi_ctrlr, 3740 def_pdu_ring_sz, 3741 ulp_num); 3742 if (status != 0) { 3743 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3744 "BM_%d : Default Header not created for ULP : %d\n", 3745 ulp_num); 3746 goto error; 3747 } 3748 3749 status = beiscsi_create_def_data(phba, phwi_context, 3750 phwi_ctrlr, 3751 def_pdu_ring_sz, 3752 ulp_num); 3753 if (status != 0) { 3754 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3755 "BM_%d : Default Data not created for ULP : %d\n", 3756 ulp_num); 3757 goto error; 3758 } 3759 /** 3760 * Now that the default PDU rings have been created, 3761 * let EP know about it. 3762 */ 3763 beiscsi_hdq_post_handles(phba, BEISCSI_DEFQ_HDR, 3764 ulp_num, nbufs); 3765 beiscsi_hdq_post_handles(phba, BEISCSI_DEFQ_DATA, 3766 ulp_num, nbufs); 3767 } 3768 } 3769 3770 status = beiscsi_post_pages(phba); 3771 if (status != 0) { 3772 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3773 "BM_%d : Post SGL Pages Failed\n"); 3774 goto error; 3775 } 3776 3777 status = beiscsi_post_template_hdr(phba); 3778 if (status != 0) { 3779 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3780 "BM_%d : Template HDR Posting for CXN Failed\n"); 3781 } 3782 3783 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr); 3784 if (status != 0) { 3785 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3786 "BM_%d : WRB Rings not created\n"); 3787 goto error; 3788 } 3789 3790 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3791 uint16_t async_arr_idx = 0; 3792 3793 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { 3794 uint16_t cri = 0; 3795 struct hd_async_context *pasync_ctx; 3796 3797 pasync_ctx = HWI_GET_ASYNC_PDU_CTX( 3798 phwi_ctrlr, ulp_num); 3799 for (cri = 0; cri < 3800 phba->params.cxns_per_ctrl; cri++) { 3801 if (ulp_num == BEISCSI_GET_ULP_FROM_CRI 3802 (phwi_ctrlr, cri)) 3803 pasync_ctx->cid_to_async_cri_map[ 3804 phwi_ctrlr->wrb_context[cri].cid] = 3805 async_arr_idx++; 3806 } 3807 } 3808 } 3809 3810 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3811 "BM_%d : hwi_init_port success\n"); 3812 return 0; 3813 3814 error: 3815 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3816 "BM_%d : hwi_init_port failed"); 3817 hwi_cleanup_port(phba); 3818 return status; 3819 } 3820 3821 static int hwi_init_controller(struct beiscsi_hba *phba) 3822 { 3823 struct hwi_controller *phwi_ctrlr; 3824 3825 phwi_ctrlr = phba->phwi_ctrlr; 3826 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) { 3827 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba-> 3828 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address; 3829 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3830 "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n", 3831 phwi_ctrlr->phwi_ctxt); 3832 } else { 3833 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3834 "BM_%d : HWI_MEM_ADDN_CONTEXT is more " 3835 "than one element.Failing to load\n"); 3836 return -ENOMEM; 3837 } 3838 3839 iscsi_init_global_templates(phba); 3840 if (beiscsi_init_wrb_handle(phba)) 3841 return -ENOMEM; 3842 3843 if (hwi_init_async_pdu_ctx(phba)) { 3844 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3845 "BM_%d : hwi_init_async_pdu_ctx failed\n"); 3846 return -ENOMEM; 3847 } 3848 3849 if (hwi_init_port(phba) != 0) { 3850 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3851 "BM_%d : hwi_init_controller failed\n"); 3852 3853 return -ENOMEM; 3854 } 3855 return 0; 3856 } 3857 3858 static void beiscsi_free_mem(struct beiscsi_hba *phba) 3859 { 3860 struct be_mem_descriptor *mem_descr; 3861 int i, j; 3862 3863 mem_descr = phba->init_mem; 3864 for (i = 0; i < SE_MEM_MAX; i++) { 3865 for (j = mem_descr->num_elements; j > 0; j--) { 3866 dma_free_coherent(&phba->pcidev->dev, 3867 mem_descr->mem_array[j - 1].size, 3868 mem_descr->mem_array[j - 1].virtual_address, 3869 (unsigned long)mem_descr->mem_array[j - 1]. 3870 bus_address.u.a64.address); 3871 } 3872 3873 kfree(mem_descr->mem_array); 3874 mem_descr++; 3875 } 3876 kfree(phba->init_mem); 3877 kfree(phba->phwi_ctrlr->wrb_context); 3878 kfree(phba->phwi_ctrlr); 3879 } 3880 3881 static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba) 3882 { 3883 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg; 3884 struct sgl_handle *psgl_handle; 3885 struct iscsi_sge *pfrag; 3886 unsigned int arr_index, i, idx; 3887 unsigned int ulp_icd_start, ulp_num = 0; 3888 3889 phba->io_sgl_hndl_avbl = 0; 3890 phba->eh_sgl_hndl_avbl = 0; 3891 3892 mem_descr_sglh = phba->init_mem; 3893 mem_descr_sglh += HWI_MEM_SGLH; 3894 if (1 == mem_descr_sglh->num_elements) { 3895 phba->io_sgl_hndl_base = kzalloc_objs(struct sgl_handle *, 3896 phba->params.ios_per_ctrl); 3897 if (!phba->io_sgl_hndl_base) { 3898 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3899 "BM_%d : Mem Alloc Failed. Failing to load\n"); 3900 return -ENOMEM; 3901 } 3902 phba->eh_sgl_hndl_base = 3903 kzalloc_objs(struct sgl_handle *, 3904 phba->params.icds_per_ctrl - phba->params.ios_per_ctrl); 3905 if (!phba->eh_sgl_hndl_base) { 3906 kfree(phba->io_sgl_hndl_base); 3907 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3908 "BM_%d : Mem Alloc Failed. Failing to load\n"); 3909 return -ENOMEM; 3910 } 3911 } else { 3912 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 3913 "BM_%d : HWI_MEM_SGLH is more than one element." 3914 "Failing to load\n"); 3915 return -ENOMEM; 3916 } 3917 3918 arr_index = 0; 3919 idx = 0; 3920 while (idx < mem_descr_sglh->num_elements) { 3921 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address; 3922 3923 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size / 3924 sizeof(struct sgl_handle)); i++) { 3925 if (arr_index < phba->params.ios_per_ctrl) { 3926 phba->io_sgl_hndl_base[arr_index] = psgl_handle; 3927 phba->io_sgl_hndl_avbl++; 3928 arr_index++; 3929 } else { 3930 phba->eh_sgl_hndl_base[arr_index - 3931 phba->params.ios_per_ctrl] = 3932 psgl_handle; 3933 arr_index++; 3934 phba->eh_sgl_hndl_avbl++; 3935 } 3936 psgl_handle++; 3937 } 3938 idx++; 3939 } 3940 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3941 "BM_%d : phba->io_sgl_hndl_avbl=%d " 3942 "phba->eh_sgl_hndl_avbl=%d\n", 3943 phba->io_sgl_hndl_avbl, 3944 phba->eh_sgl_hndl_avbl); 3945 3946 mem_descr_sg = phba->init_mem; 3947 mem_descr_sg += HWI_MEM_SGE; 3948 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 3949 "\n BM_%d : mem_descr_sg->num_elements=%d\n", 3950 mem_descr_sg->num_elements); 3951 3952 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) 3953 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) 3954 break; 3955 3956 ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num]; 3957 3958 arr_index = 0; 3959 idx = 0; 3960 while (idx < mem_descr_sg->num_elements) { 3961 pfrag = mem_descr_sg->mem_array[idx].virtual_address; 3962 3963 for (i = 0; 3964 i < (mem_descr_sg->mem_array[idx].size) / 3965 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io); 3966 i++) { 3967 if (arr_index < phba->params.ios_per_ctrl) 3968 psgl_handle = phba->io_sgl_hndl_base[arr_index]; 3969 else 3970 psgl_handle = phba->eh_sgl_hndl_base[arr_index - 3971 phba->params.ios_per_ctrl]; 3972 psgl_handle->pfrag = pfrag; 3973 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0); 3974 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0); 3975 pfrag += phba->params.num_sge_per_io; 3976 psgl_handle->sgl_index = ulp_icd_start + arr_index++; 3977 } 3978 idx++; 3979 } 3980 phba->io_sgl_free_index = 0; 3981 phba->io_sgl_alloc_index = 0; 3982 phba->eh_sgl_free_index = 0; 3983 phba->eh_sgl_alloc_index = 0; 3984 return 0; 3985 } 3986 3987 static int hba_setup_cid_tbls(struct beiscsi_hba *phba) 3988 { 3989 int ret; 3990 uint16_t i, ulp_num; 3991 struct ulp_cid_info *ptr_cid_info = NULL; 3992 3993 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 3994 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 3995 ptr_cid_info = kzalloc_obj(struct ulp_cid_info); 3996 3997 if (!ptr_cid_info) { 3998 ret = -ENOMEM; 3999 goto free_memory; 4000 } 4001 4002 /* Allocate memory for CID array */ 4003 ptr_cid_info->cid_array = 4004 kcalloc(BEISCSI_GET_CID_COUNT(phba, ulp_num), 4005 sizeof(*ptr_cid_info->cid_array), 4006 GFP_KERNEL); 4007 if (!ptr_cid_info->cid_array) { 4008 kfree(ptr_cid_info); 4009 ptr_cid_info = NULL; 4010 ret = -ENOMEM; 4011 4012 goto free_memory; 4013 } 4014 ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT( 4015 phba, ulp_num); 4016 4017 /* Save the cid_info_array ptr */ 4018 phba->cid_array_info[ulp_num] = ptr_cid_info; 4019 } 4020 } 4021 phba->ep_array = kzalloc_objs(struct iscsi_endpoint *, 4022 phba->params.cxns_per_ctrl); 4023 if (!phba->ep_array) { 4024 ret = -ENOMEM; 4025 4026 goto free_memory; 4027 } 4028 4029 phba->conn_table = kzalloc_objs(struct beiscsi_conn *, 4030 phba->params.cxns_per_ctrl); 4031 if (!phba->conn_table) { 4032 kfree(phba->ep_array); 4033 phba->ep_array = NULL; 4034 ret = -ENOMEM; 4035 4036 goto free_memory; 4037 } 4038 4039 for (i = 0; i < phba->params.cxns_per_ctrl; i++) { 4040 ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num; 4041 4042 ptr_cid_info = phba->cid_array_info[ulp_num]; 4043 ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] = 4044 phba->phwi_ctrlr->wrb_context[i].cid; 4045 4046 } 4047 4048 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4049 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4050 ptr_cid_info = phba->cid_array_info[ulp_num]; 4051 4052 ptr_cid_info->cid_alloc = 0; 4053 ptr_cid_info->cid_free = 0; 4054 } 4055 } 4056 return 0; 4057 4058 free_memory: 4059 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4060 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4061 ptr_cid_info = phba->cid_array_info[ulp_num]; 4062 4063 if (ptr_cid_info) { 4064 kfree(ptr_cid_info->cid_array); 4065 kfree(ptr_cid_info); 4066 phba->cid_array_info[ulp_num] = NULL; 4067 } 4068 } 4069 } 4070 4071 return ret; 4072 } 4073 4074 static void hwi_enable_intr(struct beiscsi_hba *phba) 4075 { 4076 struct be_ctrl_info *ctrl = &phba->ctrl; 4077 struct hwi_controller *phwi_ctrlr; 4078 struct hwi_context_memory *phwi_context; 4079 struct be_queue_info *eq; 4080 u8 __iomem *addr; 4081 u32 reg, i; 4082 u32 enabled; 4083 4084 phwi_ctrlr = phba->phwi_ctrlr; 4085 phwi_context = phwi_ctrlr->phwi_ctxt; 4086 4087 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg + 4088 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET); 4089 reg = ioread32(addr); 4090 4091 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4092 if (!enabled) { 4093 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4094 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4095 "BM_%d : reg =x%08x addr=%p\n", reg, addr); 4096 iowrite32(reg, addr); 4097 } 4098 4099 if (!phba->pcidev->msix_enabled) { 4100 eq = &phwi_context->be_eq[0].q; 4101 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4102 "BM_%d : eq->id=%d\n", eq->id); 4103 4104 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); 4105 } else { 4106 for (i = 0; i <= phba->num_cpus; i++) { 4107 eq = &phwi_context->be_eq[i].q; 4108 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 4109 "BM_%d : eq->id=%d\n", eq->id); 4110 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); 4111 } 4112 } 4113 } 4114 4115 static void hwi_disable_intr(struct beiscsi_hba *phba) 4116 { 4117 struct be_ctrl_info *ctrl = &phba->ctrl; 4118 4119 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET; 4120 u32 reg = ioread32(addr); 4121 4122 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4123 if (enabled) { 4124 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; 4125 iowrite32(reg, addr); 4126 } else 4127 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, 4128 "BM_%d : In hwi_disable_intr, Already Disabled\n"); 4129 } 4130 4131 static int beiscsi_init_port(struct beiscsi_hba *phba) 4132 { 4133 int ret; 4134 4135 ret = hwi_init_controller(phba); 4136 if (ret < 0) { 4137 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4138 "BM_%d : init controller failed\n"); 4139 return ret; 4140 } 4141 ret = beiscsi_init_sgl_handle(phba); 4142 if (ret < 0) { 4143 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4144 "BM_%d : init sgl handles failed\n"); 4145 goto cleanup_port; 4146 } 4147 4148 ret = hba_setup_cid_tbls(phba); 4149 if (ret < 0) { 4150 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 4151 "BM_%d : setup CID table failed\n"); 4152 kfree(phba->io_sgl_hndl_base); 4153 kfree(phba->eh_sgl_hndl_base); 4154 goto cleanup_port; 4155 } 4156 return ret; 4157 4158 cleanup_port: 4159 hwi_cleanup_port(phba); 4160 return ret; 4161 } 4162 4163 static void beiscsi_cleanup_port(struct beiscsi_hba *phba) 4164 { 4165 struct ulp_cid_info *ptr_cid_info = NULL; 4166 int ulp_num; 4167 4168 kfree(phba->io_sgl_hndl_base); 4169 kfree(phba->eh_sgl_hndl_base); 4170 kfree(phba->ep_array); 4171 kfree(phba->conn_table); 4172 4173 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { 4174 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { 4175 ptr_cid_info = phba->cid_array_info[ulp_num]; 4176 4177 if (ptr_cid_info) { 4178 kfree(ptr_cid_info->cid_array); 4179 kfree(ptr_cid_info); 4180 phba->cid_array_info[ulp_num] = NULL; 4181 } 4182 } 4183 } 4184 } 4185 4186 /** 4187 * beiscsi_free_mgmt_task_handles()- Free driver CXN resources 4188 * @beiscsi_conn: ptr to the conn to be cleaned up 4189 * @task: ptr to iscsi_task resource to be freed. 4190 * 4191 * Free driver mgmt resources binded to CXN. 4192 **/ 4193 void 4194 beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, 4195 struct iscsi_task *task) 4196 { 4197 struct beiscsi_io_task *io_task; 4198 struct beiscsi_hba *phba = beiscsi_conn->phba; 4199 struct hwi_wrb_context *pwrb_context; 4200 struct hwi_controller *phwi_ctrlr; 4201 uint16_t cri_index = BE_GET_CRI_FROM_CID( 4202 beiscsi_conn->beiscsi_conn_cid); 4203 4204 phwi_ctrlr = phba->phwi_ctrlr; 4205 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 4206 4207 io_task = task->dd_data; 4208 4209 if (io_task->pwrb_handle) { 4210 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle); 4211 io_task->pwrb_handle = NULL; 4212 } 4213 4214 if (io_task->psgl_handle) { 4215 free_mgmt_sgl_handle(phba, io_task->psgl_handle); 4216 io_task->psgl_handle = NULL; 4217 } 4218 4219 if (io_task->mtask_addr) { 4220 dma_unmap_single(&phba->pcidev->dev, 4221 io_task->mtask_addr, 4222 io_task->mtask_data_count, 4223 DMA_TO_DEVICE); 4224 io_task->mtask_addr = 0; 4225 } 4226 } 4227 4228 /** 4229 * beiscsi_cleanup_task()- Free driver resources of the task 4230 * @task: ptr to the iscsi task 4231 * 4232 **/ 4233 static void beiscsi_cleanup_task(struct iscsi_task *task) 4234 { 4235 struct beiscsi_io_task *io_task = task->dd_data; 4236 struct iscsi_conn *conn = task->conn; 4237 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4238 struct beiscsi_hba *phba = beiscsi_conn->phba; 4239 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; 4240 struct hwi_wrb_context *pwrb_context; 4241 struct hwi_controller *phwi_ctrlr; 4242 uint16_t cri_index = BE_GET_CRI_FROM_CID( 4243 beiscsi_conn->beiscsi_conn_cid); 4244 4245 phwi_ctrlr = phba->phwi_ctrlr; 4246 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 4247 4248 if (io_task->cmd_bhs) { 4249 dma_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, 4250 io_task->bhs_pa.u.a64.address); 4251 io_task->cmd_bhs = NULL; 4252 task->hdr = NULL; 4253 } 4254 4255 if (task->sc) { 4256 if (io_task->pwrb_handle) { 4257 free_wrb_handle(phba, pwrb_context, 4258 io_task->pwrb_handle); 4259 io_task->pwrb_handle = NULL; 4260 } 4261 4262 if (io_task->psgl_handle) { 4263 free_io_sgl_handle(phba, io_task->psgl_handle); 4264 io_task->psgl_handle = NULL; 4265 } 4266 4267 if (io_task->scsi_cmnd) { 4268 if (io_task->num_sg) 4269 scsi_dma_unmap(io_task->scsi_cmnd); 4270 io_task->scsi_cmnd = NULL; 4271 } 4272 } else { 4273 if (!beiscsi_conn->login_in_progress) 4274 beiscsi_free_mgmt_task_handles(beiscsi_conn, task); 4275 } 4276 } 4277 4278 void 4279 beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn, 4280 struct beiscsi_offload_params *params) 4281 { 4282 struct wrb_handle *pwrb_handle; 4283 struct hwi_wrb_context *pwrb_context = NULL; 4284 struct beiscsi_hba *phba = beiscsi_conn->phba; 4285 struct iscsi_task *task = beiscsi_conn->task; 4286 struct iscsi_session *session = task->conn->session; 4287 u32 doorbell = 0; 4288 4289 /* 4290 * We can always use 0 here because it is reserved by libiscsi for 4291 * login/startup related tasks. 4292 */ 4293 beiscsi_conn->login_in_progress = 0; 4294 spin_lock_bh(&session->back_lock); 4295 beiscsi_cleanup_task(task); 4296 spin_unlock_bh(&session->back_lock); 4297 4298 pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid, 4299 &pwrb_context); 4300 4301 /* Check for the adapter family */ 4302 if (is_chip_be2_be3r(phba)) 4303 beiscsi_offload_cxn_v0(params, pwrb_handle, 4304 phba->init_mem, 4305 pwrb_context); 4306 else 4307 beiscsi_offload_cxn_v2(params, pwrb_handle, 4308 pwrb_context); 4309 4310 be_dws_le_to_cpu(pwrb_handle->pwrb, 4311 sizeof(struct iscsi_target_context_update_wrb)); 4312 4313 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 4314 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK) 4315 << DB_DEF_PDU_WRB_INDEX_SHIFT; 4316 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4317 iowrite32(doorbell, phba->db_va + 4318 beiscsi_conn->doorbell_offset); 4319 4320 /* 4321 * There is no completion for CONTEXT_UPDATE. The completion of next 4322 * WRB posted guarantees FW's processing and DMA'ing of it. 4323 * Use beiscsi_put_wrb_handle to put it back in the pool which makes 4324 * sure zero'ing or reuse of the WRB only after wrbs_per_cxn. 4325 */ 4326 beiscsi_put_wrb_handle(pwrb_context, pwrb_handle, 4327 phba->params.wrbs_per_cxn); 4328 beiscsi_log(phba, KERN_INFO, 4329 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4330 "BM_%d : put CONTEXT_UPDATE pwrb_handle=%p free_index=0x%x wrb_handles_available=%d\n", 4331 pwrb_handle, pwrb_context->free_index, 4332 pwrb_context->wrb_handles_available); 4333 } 4334 4335 static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt, 4336 int *index, int *age) 4337 { 4338 *index = (int)itt; 4339 if (age) 4340 *age = conn->session->age; 4341 } 4342 4343 /** 4344 * beiscsi_alloc_pdu - allocates pdu and related resources 4345 * @task: libiscsi task 4346 * @opcode: opcode of pdu for task 4347 * 4348 * This is called with the session lock held. It will allocate 4349 * the wrb and sgl if needed for the command. And it will prep 4350 * the pdu's itt. beiscsi_parse_pdu will later translate 4351 * the pdu itt to the libiscsi task itt. 4352 */ 4353 static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode) 4354 { 4355 struct beiscsi_io_task *io_task = task->dd_data; 4356 struct iscsi_conn *conn = task->conn; 4357 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4358 struct beiscsi_hba *phba = beiscsi_conn->phba; 4359 struct hwi_wrb_context *pwrb_context; 4360 struct hwi_controller *phwi_ctrlr; 4361 itt_t itt; 4362 uint16_t cri_index = 0; 4363 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; 4364 dma_addr_t paddr; 4365 4366 io_task->cmd_bhs = dma_pool_alloc(beiscsi_sess->bhs_pool, 4367 GFP_ATOMIC, &paddr); 4368 if (!io_task->cmd_bhs) 4369 return -ENOMEM; 4370 io_task->bhs_pa.u.a64.address = paddr; 4371 io_task->libiscsi_itt = (itt_t)task->itt; 4372 io_task->conn = beiscsi_conn; 4373 4374 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr; 4375 task->hdr_max = sizeof(struct be_cmd_bhs); 4376 io_task->psgl_handle = NULL; 4377 io_task->pwrb_handle = NULL; 4378 4379 if (task->sc) { 4380 io_task->psgl_handle = alloc_io_sgl_handle(phba); 4381 if (!io_task->psgl_handle) { 4382 beiscsi_log(phba, KERN_ERR, 4383 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4384 "BM_%d : Alloc of IO_SGL_ICD Failed " 4385 "for the CID : %d\n", 4386 beiscsi_conn->beiscsi_conn_cid); 4387 goto free_hndls; 4388 } 4389 io_task->pwrb_handle = alloc_wrb_handle(phba, 4390 beiscsi_conn->beiscsi_conn_cid, 4391 &io_task->pwrb_context); 4392 if (!io_task->pwrb_handle) { 4393 beiscsi_log(phba, KERN_ERR, 4394 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4395 "BM_%d : Alloc of WRB_HANDLE Failed " 4396 "for the CID : %d\n", 4397 beiscsi_conn->beiscsi_conn_cid); 4398 goto free_io_hndls; 4399 } 4400 } else { 4401 io_task->scsi_cmnd = NULL; 4402 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) { 4403 beiscsi_conn->task = task; 4404 if (!beiscsi_conn->login_in_progress) { 4405 io_task->psgl_handle = (struct sgl_handle *) 4406 alloc_mgmt_sgl_handle(phba); 4407 if (!io_task->psgl_handle) { 4408 beiscsi_log(phba, KERN_ERR, 4409 BEISCSI_LOG_IO | 4410 BEISCSI_LOG_CONFIG, 4411 "BM_%d : Alloc of MGMT_SGL_ICD Failed " 4412 "for the CID : %d\n", 4413 beiscsi_conn->beiscsi_conn_cid); 4414 goto free_hndls; 4415 } 4416 4417 beiscsi_conn->login_in_progress = 1; 4418 beiscsi_conn->plogin_sgl_handle = 4419 io_task->psgl_handle; 4420 io_task->pwrb_handle = 4421 alloc_wrb_handle(phba, 4422 beiscsi_conn->beiscsi_conn_cid, 4423 &io_task->pwrb_context); 4424 if (!io_task->pwrb_handle) { 4425 beiscsi_log(phba, KERN_ERR, 4426 BEISCSI_LOG_IO | 4427 BEISCSI_LOG_CONFIG, 4428 "BM_%d : Alloc of WRB_HANDLE Failed " 4429 "for the CID : %d\n", 4430 beiscsi_conn->beiscsi_conn_cid); 4431 goto free_mgmt_hndls; 4432 } 4433 beiscsi_conn->plogin_wrb_handle = 4434 io_task->pwrb_handle; 4435 4436 } else { 4437 io_task->psgl_handle = 4438 beiscsi_conn->plogin_sgl_handle; 4439 io_task->pwrb_handle = 4440 beiscsi_conn->plogin_wrb_handle; 4441 } 4442 } else { 4443 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba); 4444 if (!io_task->psgl_handle) { 4445 beiscsi_log(phba, KERN_ERR, 4446 BEISCSI_LOG_IO | 4447 BEISCSI_LOG_CONFIG, 4448 "BM_%d : Alloc of MGMT_SGL_ICD Failed " 4449 "for the CID : %d\n", 4450 beiscsi_conn->beiscsi_conn_cid); 4451 goto free_hndls; 4452 } 4453 io_task->pwrb_handle = 4454 alloc_wrb_handle(phba, 4455 beiscsi_conn->beiscsi_conn_cid, 4456 &io_task->pwrb_context); 4457 if (!io_task->pwrb_handle) { 4458 beiscsi_log(phba, KERN_ERR, 4459 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, 4460 "BM_%d : Alloc of WRB_HANDLE Failed " 4461 "for the CID : %d\n", 4462 beiscsi_conn->beiscsi_conn_cid); 4463 goto free_mgmt_hndls; 4464 } 4465 4466 } 4467 } 4468 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle-> 4469 wrb_index << 16) | (unsigned int) 4470 (io_task->psgl_handle->sgl_index)); 4471 io_task->pwrb_handle->pio_handle = task; 4472 4473 io_task->cmd_bhs->iscsi_hdr.itt = itt; 4474 return 0; 4475 4476 free_io_hndls: 4477 free_io_sgl_handle(phba, io_task->psgl_handle); 4478 goto free_hndls; 4479 free_mgmt_hndls: 4480 free_mgmt_sgl_handle(phba, io_task->psgl_handle); 4481 io_task->psgl_handle = NULL; 4482 free_hndls: 4483 phwi_ctrlr = phba->phwi_ctrlr; 4484 cri_index = BE_GET_CRI_FROM_CID( 4485 beiscsi_conn->beiscsi_conn_cid); 4486 pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; 4487 if (io_task->pwrb_handle) 4488 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle); 4489 io_task->pwrb_handle = NULL; 4490 dma_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, 4491 io_task->bhs_pa.u.a64.address); 4492 io_task->cmd_bhs = NULL; 4493 return -ENOMEM; 4494 } 4495 static int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg, 4496 unsigned int num_sg, unsigned int xferlen, 4497 unsigned int writedir) 4498 { 4499 4500 struct beiscsi_io_task *io_task = task->dd_data; 4501 struct iscsi_conn *conn = task->conn; 4502 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4503 struct beiscsi_hba *phba = beiscsi_conn->phba; 4504 struct iscsi_wrb *pwrb = NULL; 4505 unsigned int doorbell = 0; 4506 4507 pwrb = io_task->pwrb_handle->pwrb; 4508 4509 io_task->bhs_len = sizeof(struct be_cmd_bhs); 4510 4511 if (writedir) { 4512 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb, 4513 INI_WR_CMD); 4514 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1); 4515 } else { 4516 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb, 4517 INI_RD_CMD); 4518 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0); 4519 } 4520 4521 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2, 4522 type, pwrb); 4523 4524 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb, 4525 cpu_to_be16(*(unsigned short *) 4526 &io_task->cmd_bhs->iscsi_hdr.lun)); 4527 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen); 4528 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb, 4529 io_task->pwrb_handle->wrb_index); 4530 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb, 4531 be32_to_cpu(task->cmdsn)); 4532 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb, 4533 io_task->psgl_handle->sgl_index); 4534 4535 hwi_write_sgl_v2(pwrb, sg, num_sg, io_task); 4536 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb, 4537 io_task->pwrb_handle->wrb_index); 4538 if (io_task->pwrb_context->plast_wrb) 4539 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, 4540 io_task->pwrb_context->plast_wrb, 4541 io_task->pwrb_handle->wrb_index); 4542 io_task->pwrb_context->plast_wrb = pwrb; 4543 4544 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); 4545 4546 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 4547 doorbell |= (io_task->pwrb_handle->wrb_index & 4548 DB_DEF_PDU_WRB_INDEX_MASK) << 4549 DB_DEF_PDU_WRB_INDEX_SHIFT; 4550 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4551 iowrite32(doorbell, phba->db_va + 4552 beiscsi_conn->doorbell_offset); 4553 return 0; 4554 } 4555 4556 static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg, 4557 unsigned int num_sg, unsigned int xferlen, 4558 unsigned int writedir) 4559 { 4560 4561 struct beiscsi_io_task *io_task = task->dd_data; 4562 struct iscsi_conn *conn = task->conn; 4563 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4564 struct beiscsi_hba *phba = beiscsi_conn->phba; 4565 struct iscsi_wrb *pwrb = NULL; 4566 unsigned int doorbell = 0; 4567 4568 pwrb = io_task->pwrb_handle->pwrb; 4569 io_task->bhs_len = sizeof(struct be_cmd_bhs); 4570 4571 if (writedir) { 4572 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4573 INI_WR_CMD); 4574 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1); 4575 } else { 4576 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, 4577 INI_RD_CMD); 4578 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); 4579 } 4580 4581 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb, 4582 type, pwrb); 4583 4584 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb, 4585 cpu_to_be16(*(unsigned short *) 4586 &io_task->cmd_bhs->iscsi_hdr.lun)); 4587 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen); 4588 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, 4589 io_task->pwrb_handle->wrb_index); 4590 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 4591 be32_to_cpu(task->cmdsn)); 4592 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, 4593 io_task->psgl_handle->sgl_index); 4594 4595 hwi_write_sgl(pwrb, sg, num_sg, io_task); 4596 4597 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, 4598 io_task->pwrb_handle->wrb_index); 4599 if (io_task->pwrb_context->plast_wrb) 4600 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, 4601 io_task->pwrb_context->plast_wrb, 4602 io_task->pwrb_handle->wrb_index); 4603 io_task->pwrb_context->plast_wrb = pwrb; 4604 4605 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); 4606 4607 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; 4608 doorbell |= (io_task->pwrb_handle->wrb_index & 4609 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; 4610 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4611 4612 iowrite32(doorbell, phba->db_va + 4613 beiscsi_conn->doorbell_offset); 4614 return 0; 4615 } 4616 4617 static int beiscsi_mtask(struct iscsi_task *task) 4618 { 4619 struct beiscsi_io_task *io_task = task->dd_data; 4620 struct iscsi_conn *conn = task->conn; 4621 struct beiscsi_conn *beiscsi_conn = conn->dd_data; 4622 struct beiscsi_hba *phba = beiscsi_conn->phba; 4623 struct iscsi_wrb *pwrb = NULL; 4624 unsigned int doorbell = 0; 4625 unsigned int cid; 4626 unsigned int pwrb_typeoffset = 0; 4627 int ret = 0; 4628 4629 cid = beiscsi_conn->beiscsi_conn_cid; 4630 pwrb = io_task->pwrb_handle->pwrb; 4631 4632 if (is_chip_be2_be3r(phba)) { 4633 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 4634 be32_to_cpu(task->cmdsn)); 4635 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, 4636 io_task->pwrb_handle->wrb_index); 4637 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, 4638 io_task->psgl_handle->sgl_index); 4639 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, 4640 task->data_count); 4641 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, 4642 io_task->pwrb_handle->wrb_index); 4643 if (io_task->pwrb_context->plast_wrb) 4644 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, 4645 io_task->pwrb_context->plast_wrb, 4646 io_task->pwrb_handle->wrb_index); 4647 io_task->pwrb_context->plast_wrb = pwrb; 4648 4649 pwrb_typeoffset = BE_WRB_TYPE_OFFSET; 4650 } else { 4651 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb, 4652 be32_to_cpu(task->cmdsn)); 4653 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb, 4654 io_task->pwrb_handle->wrb_index); 4655 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb, 4656 io_task->psgl_handle->sgl_index); 4657 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, 4658 task->data_count); 4659 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb, 4660 io_task->pwrb_handle->wrb_index); 4661 if (io_task->pwrb_context->plast_wrb) 4662 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, 4663 io_task->pwrb_context->plast_wrb, 4664 io_task->pwrb_handle->wrb_index); 4665 io_task->pwrb_context->plast_wrb = pwrb; 4666 4667 pwrb_typeoffset = SKH_WRB_TYPE_OFFSET; 4668 } 4669 4670 4671 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) { 4672 case ISCSI_OP_LOGIN: 4673 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1); 4674 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); 4675 ret = hwi_write_buffer(pwrb, task); 4676 break; 4677 case ISCSI_OP_NOOP_OUT: 4678 if (task->hdr->ttt != ISCSI_RESERVED_TAG) { 4679 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); 4680 if (is_chip_be2_be3r(phba)) 4681 AMAP_SET_BITS(struct amap_iscsi_wrb, 4682 dmsg, pwrb, 1); 4683 else 4684 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 4685 dmsg, pwrb, 1); 4686 } else { 4687 ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset); 4688 if (is_chip_be2_be3r(phba)) 4689 AMAP_SET_BITS(struct amap_iscsi_wrb, 4690 dmsg, pwrb, 0); 4691 else 4692 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, 4693 dmsg, pwrb, 0); 4694 } 4695 ret = hwi_write_buffer(pwrb, task); 4696 break; 4697 case ISCSI_OP_TEXT: 4698 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); 4699 ret = hwi_write_buffer(pwrb, task); 4700 break; 4701 case ISCSI_OP_SCSI_TMFUNC: 4702 ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset); 4703 ret = hwi_write_buffer(pwrb, task); 4704 break; 4705 case ISCSI_OP_LOGOUT: 4706 ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset); 4707 ret = hwi_write_buffer(pwrb, task); 4708 break; 4709 4710 default: 4711 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 4712 "BM_%d : opcode =%d Not supported\n", 4713 task->hdr->opcode & ISCSI_OPCODE_MASK); 4714 4715 return -EINVAL; 4716 } 4717 4718 if (ret) 4719 return ret; 4720 4721 /* Set the task type */ 4722 io_task->wrb_type = (is_chip_be2_be3r(phba)) ? 4723 AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) : 4724 AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb); 4725 4726 doorbell |= cid & DB_WRB_POST_CID_MASK; 4727 doorbell |= (io_task->pwrb_handle->wrb_index & 4728 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; 4729 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; 4730 iowrite32(doorbell, phba->db_va + 4731 beiscsi_conn->doorbell_offset); 4732 return 0; 4733 } 4734 4735 static int beiscsi_task_xmit(struct iscsi_task *task) 4736 { 4737 struct beiscsi_io_task *io_task = task->dd_data; 4738 struct scsi_cmnd *sc = task->sc; 4739 struct beiscsi_hba *phba; 4740 struct scatterlist *sg; 4741 int num_sg; 4742 unsigned int writedir = 0, xferlen = 0; 4743 4744 phba = io_task->conn->phba; 4745 /** 4746 * HBA in error includes BEISCSI_HBA_FW_TIMEOUT. IO path might be 4747 * operational if FW still gets heartbeat from EP FW. Is management 4748 * path really needed to continue further? 4749 */ 4750 if (!beiscsi_hba_is_online(phba)) 4751 return -EIO; 4752 4753 if (!io_task->conn->login_in_progress) 4754 task->hdr->exp_statsn = 0; 4755 4756 if (!sc) 4757 return beiscsi_mtask(task); 4758 4759 io_task->scsi_cmnd = sc; 4760 io_task->num_sg = 0; 4761 num_sg = scsi_dma_map(sc); 4762 if (num_sg < 0) { 4763 beiscsi_log(phba, KERN_ERR, 4764 BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI, 4765 "BM_%d : scsi_dma_map Failed " 4766 "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n", 4767 be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt), 4768 io_task->libiscsi_itt, scsi_bufflen(sc)); 4769 4770 return num_sg; 4771 } 4772 /** 4773 * For scsi cmd task, check num_sg before unmapping in cleanup_task. 4774 * For management task, cleanup_task checks mtask_addr before unmapping. 4775 */ 4776 io_task->num_sg = num_sg; 4777 xferlen = scsi_bufflen(sc); 4778 sg = scsi_sglist(sc); 4779 if (sc->sc_data_direction == DMA_TO_DEVICE) 4780 writedir = 1; 4781 else 4782 writedir = 0; 4783 4784 return phba->iotask_fn(task, sg, num_sg, xferlen, writedir); 4785 } 4786 4787 /** 4788 * beiscsi_bsg_request - handle bsg request from ISCSI transport 4789 * @job: job to handle 4790 */ 4791 static int beiscsi_bsg_request(struct bsg_job *job) 4792 { 4793 struct Scsi_Host *shost; 4794 struct beiscsi_hba *phba; 4795 struct iscsi_bsg_request *bsg_req = job->request; 4796 int rc = -EINVAL; 4797 unsigned int tag; 4798 struct be_dma_mem nonemb_cmd; 4799 struct be_cmd_resp_hdr *resp; 4800 struct iscsi_bsg_reply *bsg_reply = job->reply; 4801 unsigned short status, extd_status; 4802 4803 shost = iscsi_job_to_shost(job); 4804 phba = iscsi_host_priv(shost); 4805 4806 if (!beiscsi_hba_is_online(phba)) { 4807 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, 4808 "BM_%d : HBA in error 0x%lx\n", phba->state); 4809 return -ENXIO; 4810 } 4811 4812 switch (bsg_req->msgcode) { 4813 case ISCSI_BSG_HST_VENDOR: 4814 nonemb_cmd.va = dma_alloc_coherent(&phba->ctrl.pdev->dev, 4815 job->request_payload.payload_len, 4816 &nonemb_cmd.dma, GFP_KERNEL); 4817 if (nonemb_cmd.va == NULL) { 4818 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 4819 "BM_%d : Failed to allocate memory for " 4820 "beiscsi_bsg_request\n"); 4821 return -ENOMEM; 4822 } 4823 tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job, 4824 &nonemb_cmd); 4825 if (!tag) { 4826 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 4827 "BM_%d : MBX Tag Allocation Failed\n"); 4828 4829 dma_free_coherent(&phba->ctrl.pdev->dev, nonemb_cmd.size, 4830 nonemb_cmd.va, nonemb_cmd.dma); 4831 return -EAGAIN; 4832 } 4833 4834 rc = wait_event_interruptible_timeout( 4835 phba->ctrl.mcc_wait[tag], 4836 phba->ctrl.mcc_tag_status[tag], 4837 msecs_to_jiffies( 4838 BEISCSI_HOST_MBX_TIMEOUT)); 4839 4840 if (!test_bit(BEISCSI_HBA_ONLINE, &phba->state)) { 4841 clear_bit(MCC_TAG_STATE_RUNNING, 4842 &phba->ctrl.ptag_state[tag].tag_state); 4843 dma_free_coherent(&phba->ctrl.pdev->dev, nonemb_cmd.size, 4844 nonemb_cmd.va, nonemb_cmd.dma); 4845 return -EIO; 4846 } 4847 extd_status = (phba->ctrl.mcc_tag_status[tag] & 4848 CQE_STATUS_ADDL_MASK) >> CQE_STATUS_ADDL_SHIFT; 4849 status = phba->ctrl.mcc_tag_status[tag] & CQE_STATUS_MASK; 4850 free_mcc_wrb(&phba->ctrl, tag); 4851 resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va; 4852 sg_copy_from_buffer(job->reply_payload.sg_list, 4853 job->reply_payload.sg_cnt, 4854 nonemb_cmd.va, (resp->response_length 4855 + sizeof(*resp))); 4856 bsg_reply->reply_payload_rcv_len = resp->response_length; 4857 bsg_reply->result = status; 4858 bsg_job_done(job, bsg_reply->result, 4859 bsg_reply->reply_payload_rcv_len); 4860 dma_free_coherent(&phba->ctrl.pdev->dev, nonemb_cmd.size, 4861 nonemb_cmd.va, nonemb_cmd.dma); 4862 if (status || extd_status) { 4863 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 4864 "BM_%d : MBX Cmd Failed" 4865 " status = %d extd_status = %d\n", 4866 status, extd_status); 4867 4868 return -EIO; 4869 } else { 4870 rc = 0; 4871 } 4872 break; 4873 4874 default: 4875 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, 4876 "BM_%d : Unsupported bsg command: 0x%x\n", 4877 bsg_req->msgcode); 4878 break; 4879 } 4880 4881 return rc; 4882 } 4883 4884 static void beiscsi_hba_attrs_init(struct beiscsi_hba *phba) 4885 { 4886 /* Set the logging parameter */ 4887 beiscsi_log_enable_init(phba, beiscsi_log_enable); 4888 } 4889 4890 void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle) 4891 { 4892 if (phba->boot_struct.boot_kset) 4893 return; 4894 4895 /* skip if boot work is already in progress */ 4896 if (test_and_set_bit(BEISCSI_HBA_BOOT_WORK, &phba->state)) 4897 return; 4898 4899 phba->boot_struct.retry = 3; 4900 phba->boot_struct.tag = 0; 4901 phba->boot_struct.s_handle = s_handle; 4902 phba->boot_struct.action = BEISCSI_BOOT_GET_SHANDLE; 4903 schedule_work(&phba->boot_work); 4904 } 4905 4906 #define BEISCSI_SYSFS_ISCSI_BOOT_FLAGS 3 4907 /* 4908 * beiscsi_show_boot_tgt_info() 4909 * Boot flag info for iscsi-utilities 4910 * Bit 0 Block valid flag 4911 * Bit 1 Firmware booting selected 4912 */ 4913 static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf) 4914 { 4915 struct beiscsi_hba *phba = data; 4916 struct mgmt_session_info *boot_sess = &phba->boot_struct.boot_sess; 4917 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0]; 4918 char *str = buf; 4919 int rc = -EPERM; 4920 4921 switch (type) { 4922 case ISCSI_BOOT_TGT_NAME: 4923 rc = sprintf(buf, "%.*s\n", 4924 (int)strlen(boot_sess->target_name), 4925 (char *)&boot_sess->target_name); 4926 break; 4927 case ISCSI_BOOT_TGT_IP_ADDR: 4928 if (boot_conn->dest_ipaddr.ip_type == BEISCSI_IP_TYPE_V4) 4929 rc = sprintf(buf, "%pI4\n", 4930 (char *)&boot_conn->dest_ipaddr.addr); 4931 else 4932 rc = sprintf(str, "%pI6\n", 4933 (char *)&boot_conn->dest_ipaddr.addr); 4934 break; 4935 case ISCSI_BOOT_TGT_PORT: 4936 rc = sprintf(str, "%d\n", boot_conn->dest_port); 4937 break; 4938 4939 case ISCSI_BOOT_TGT_CHAP_NAME: 4940 rc = sprintf(str, "%.*s\n", 4941 boot_conn->negotiated_login_options.auth_data.chap. 4942 target_chap_name_length, 4943 (char *)&boot_conn->negotiated_login_options. 4944 auth_data.chap.target_chap_name); 4945 break; 4946 case ISCSI_BOOT_TGT_CHAP_SECRET: 4947 rc = sprintf(str, "%.*s\n", 4948 boot_conn->negotiated_login_options.auth_data.chap. 4949 target_secret_length, 4950 (char *)&boot_conn->negotiated_login_options. 4951 auth_data.chap.target_secret); 4952 break; 4953 case ISCSI_BOOT_TGT_REV_CHAP_NAME: 4954 rc = sprintf(str, "%.*s\n", 4955 boot_conn->negotiated_login_options.auth_data.chap. 4956 intr_chap_name_length, 4957 (char *)&boot_conn->negotiated_login_options. 4958 auth_data.chap.intr_chap_name); 4959 break; 4960 case ISCSI_BOOT_TGT_REV_CHAP_SECRET: 4961 rc = sprintf(str, "%.*s\n", 4962 boot_conn->negotiated_login_options.auth_data.chap. 4963 intr_secret_length, 4964 (char *)&boot_conn->negotiated_login_options. 4965 auth_data.chap.intr_secret); 4966 break; 4967 case ISCSI_BOOT_TGT_FLAGS: 4968 rc = sprintf(str, "%d\n", BEISCSI_SYSFS_ISCSI_BOOT_FLAGS); 4969 break; 4970 case ISCSI_BOOT_TGT_NIC_ASSOC: 4971 rc = sprintf(str, "0\n"); 4972 break; 4973 } 4974 return rc; 4975 } 4976 4977 static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf) 4978 { 4979 struct beiscsi_hba *phba = data; 4980 char *str = buf; 4981 int rc = -EPERM; 4982 4983 switch (type) { 4984 case ISCSI_BOOT_INI_INITIATOR_NAME: 4985 rc = sprintf(str, "%s\n", 4986 phba->boot_struct.boot_sess.initiator_iscsiname); 4987 break; 4988 } 4989 return rc; 4990 } 4991 4992 static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf) 4993 { 4994 struct beiscsi_hba *phba = data; 4995 char *str = buf; 4996 int rc = -EPERM; 4997 4998 switch (type) { 4999 case ISCSI_BOOT_ETH_FLAGS: 5000 rc = sprintf(str, "%d\n", BEISCSI_SYSFS_ISCSI_BOOT_FLAGS); 5001 break; 5002 case ISCSI_BOOT_ETH_INDEX: 5003 rc = sprintf(str, "0\n"); 5004 break; 5005 case ISCSI_BOOT_ETH_MAC: 5006 rc = beiscsi_get_macaddr(str, phba); 5007 break; 5008 } 5009 return rc; 5010 } 5011 5012 static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type) 5013 { 5014 umode_t rc = 0; 5015 5016 switch (type) { 5017 case ISCSI_BOOT_TGT_NAME: 5018 case ISCSI_BOOT_TGT_IP_ADDR: 5019 case ISCSI_BOOT_TGT_PORT: 5020 case ISCSI_BOOT_TGT_CHAP_NAME: 5021 case ISCSI_BOOT_TGT_CHAP_SECRET: 5022 case ISCSI_BOOT_TGT_REV_CHAP_NAME: 5023 case ISCSI_BOOT_TGT_REV_CHAP_SECRET: 5024 case ISCSI_BOOT_TGT_NIC_ASSOC: 5025 case ISCSI_BOOT_TGT_FLAGS: 5026 rc = S_IRUGO; 5027 break; 5028 } 5029 return rc; 5030 } 5031 5032 static umode_t beiscsi_ini_get_attr_visibility(void *data, int type) 5033 { 5034 umode_t rc = 0; 5035 5036 switch (type) { 5037 case ISCSI_BOOT_INI_INITIATOR_NAME: 5038 rc = S_IRUGO; 5039 break; 5040 } 5041 return rc; 5042 } 5043 5044 static umode_t beiscsi_eth_get_attr_visibility(void *data, int type) 5045 { 5046 umode_t rc = 0; 5047 5048 switch (type) { 5049 case ISCSI_BOOT_ETH_FLAGS: 5050 case ISCSI_BOOT_ETH_MAC: 5051 case ISCSI_BOOT_ETH_INDEX: 5052 rc = S_IRUGO; 5053 break; 5054 } 5055 return rc; 5056 } 5057 5058 static void beiscsi_boot_kobj_release(void *data) 5059 { 5060 struct beiscsi_hba *phba = data; 5061 5062 scsi_host_put(phba->shost); 5063 } 5064 5065 static int beiscsi_boot_create_kset(struct beiscsi_hba *phba) 5066 { 5067 struct boot_struct *bs = &phba->boot_struct; 5068 struct iscsi_boot_kobj *boot_kobj; 5069 5070 if (bs->boot_kset) { 5071 __beiscsi_log(phba, KERN_ERR, 5072 "BM_%d: boot_kset already created\n"); 5073 return 0; 5074 } 5075 5076 bs->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no); 5077 if (!bs->boot_kset) { 5078 __beiscsi_log(phba, KERN_ERR, 5079 "BM_%d: boot_kset alloc failed\n"); 5080 return -ENOMEM; 5081 } 5082 5083 /* get shost ref because the show function will refer phba */ 5084 if (!scsi_host_get(phba->shost)) 5085 goto free_kset; 5086 5087 boot_kobj = iscsi_boot_create_target(bs->boot_kset, 0, phba, 5088 beiscsi_show_boot_tgt_info, 5089 beiscsi_tgt_get_attr_visibility, 5090 beiscsi_boot_kobj_release); 5091 if (!boot_kobj) 5092 goto put_shost; 5093 5094 if (!scsi_host_get(phba->shost)) 5095 goto free_kset; 5096 5097 boot_kobj = iscsi_boot_create_initiator(bs->boot_kset, 0, phba, 5098 beiscsi_show_boot_ini_info, 5099 beiscsi_ini_get_attr_visibility, 5100 beiscsi_boot_kobj_release); 5101 if (!boot_kobj) 5102 goto put_shost; 5103 5104 if (!scsi_host_get(phba->shost)) 5105 goto free_kset; 5106 5107 boot_kobj = iscsi_boot_create_ethernet(bs->boot_kset, 0, phba, 5108 beiscsi_show_boot_eth_info, 5109 beiscsi_eth_get_attr_visibility, 5110 beiscsi_boot_kobj_release); 5111 if (!boot_kobj) 5112 goto put_shost; 5113 5114 return 0; 5115 5116 put_shost: 5117 scsi_host_put(phba->shost); 5118 free_kset: 5119 iscsi_boot_destroy_kset(bs->boot_kset); 5120 bs->boot_kset = NULL; 5121 return -ENOMEM; 5122 } 5123 5124 static void beiscsi_boot_work(struct work_struct *work) 5125 { 5126 struct beiscsi_hba *phba = 5127 container_of(work, struct beiscsi_hba, boot_work); 5128 struct boot_struct *bs = &phba->boot_struct; 5129 unsigned int tag = 0; 5130 5131 if (!beiscsi_hba_is_online(phba)) 5132 return; 5133 5134 beiscsi_log(phba, KERN_INFO, 5135 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 5136 "BM_%d : %s action %d\n", 5137 __func__, phba->boot_struct.action); 5138 5139 switch (phba->boot_struct.action) { 5140 case BEISCSI_BOOT_REOPEN_SESS: 5141 tag = beiscsi_boot_reopen_sess(phba); 5142 break; 5143 case BEISCSI_BOOT_GET_SHANDLE: 5144 tag = __beiscsi_boot_get_shandle(phba, 1); 5145 break; 5146 case BEISCSI_BOOT_GET_SINFO: 5147 tag = beiscsi_boot_get_sinfo(phba); 5148 break; 5149 case BEISCSI_BOOT_LOGOUT_SESS: 5150 tag = beiscsi_boot_logout_sess(phba); 5151 break; 5152 case BEISCSI_BOOT_CREATE_KSET: 5153 beiscsi_boot_create_kset(phba); 5154 /** 5155 * updated boot_kset is made visible to all before 5156 * ending the boot work. 5157 */ 5158 mb(); 5159 clear_bit(BEISCSI_HBA_BOOT_WORK, &phba->state); 5160 return; 5161 } 5162 if (!tag) { 5163 if (bs->retry--) 5164 schedule_work(&phba->boot_work); 5165 else 5166 clear_bit(BEISCSI_HBA_BOOT_WORK, &phba->state); 5167 } 5168 } 5169 5170 static void beiscsi_eqd_update_work(struct work_struct *work) 5171 { 5172 struct hwi_context_memory *phwi_context; 5173 struct be_set_eqd set_eqd[MAX_CPUS]; 5174 struct hwi_controller *phwi_ctrlr; 5175 struct be_eq_obj *pbe_eq; 5176 struct beiscsi_hba *phba; 5177 unsigned int pps, delta; 5178 struct be_aic_obj *aic; 5179 int eqd, i, num = 0; 5180 unsigned long now; 5181 5182 phba = container_of(work, struct beiscsi_hba, eqd_update.work); 5183 if (!beiscsi_hba_is_online(phba)) 5184 return; 5185 5186 phwi_ctrlr = phba->phwi_ctrlr; 5187 phwi_context = phwi_ctrlr->phwi_ctxt; 5188 5189 for (i = 0; i <= phba->num_cpus; i++) { 5190 aic = &phba->aic_obj[i]; 5191 pbe_eq = &phwi_context->be_eq[i]; 5192 now = jiffies; 5193 if (!aic->jiffies || time_before(now, aic->jiffies) || 5194 pbe_eq->cq_count < aic->eq_prev) { 5195 aic->jiffies = now; 5196 aic->eq_prev = pbe_eq->cq_count; 5197 continue; 5198 } 5199 delta = jiffies_to_msecs(now - aic->jiffies); 5200 pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta); 5201 eqd = (pps / 1500) << 2; 5202 5203 if (eqd < 8) 5204 eqd = 0; 5205 eqd = min_t(u32, eqd, BEISCSI_EQ_DELAY_MAX); 5206 eqd = max_t(u32, eqd, BEISCSI_EQ_DELAY_MIN); 5207 5208 aic->jiffies = now; 5209 aic->eq_prev = pbe_eq->cq_count; 5210 5211 if (eqd != aic->prev_eqd) { 5212 set_eqd[num].delay_multiplier = (eqd * 65)/100; 5213 set_eqd[num].eq_id = pbe_eq->q.id; 5214 aic->prev_eqd = eqd; 5215 num++; 5216 } 5217 } 5218 if (num) 5219 /* completion of this is ignored */ 5220 beiscsi_modify_eq_delay(phba, set_eqd, num); 5221 5222 schedule_delayed_work(&phba->eqd_update, 5223 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL)); 5224 } 5225 5226 static void beiscsi_hw_tpe_check(struct timer_list *t) 5227 { 5228 struct beiscsi_hba *phba = timer_container_of(phba, t, hw_check); 5229 u32 wait; 5230 5231 /* if not TPE, do nothing */ 5232 if (!beiscsi_detect_tpe(phba)) 5233 return; 5234 5235 /* wait default 4000ms before recovering */ 5236 wait = 4000; 5237 if (phba->ue2rp > BEISCSI_UE_DETECT_INTERVAL) 5238 wait = phba->ue2rp - BEISCSI_UE_DETECT_INTERVAL; 5239 queue_delayed_work(phba->wq, &phba->recover_port, 5240 msecs_to_jiffies(wait)); 5241 } 5242 5243 static void beiscsi_hw_health_check(struct timer_list *t) 5244 { 5245 struct beiscsi_hba *phba = timer_container_of(phba, t, hw_check); 5246 5247 beiscsi_detect_ue(phba); 5248 if (beiscsi_detect_ue(phba)) { 5249 __beiscsi_log(phba, KERN_ERR, 5250 "BM_%d : port in error: %lx\n", phba->state); 5251 /* sessions are no longer valid, so first fail the sessions */ 5252 queue_work(phba->wq, &phba->sess_work); 5253 5254 /* detect UER supported */ 5255 if (!test_bit(BEISCSI_HBA_UER_SUPP, &phba->state)) 5256 return; 5257 /* modify this timer to check TPE */ 5258 phba->hw_check.function = beiscsi_hw_tpe_check; 5259 } 5260 5261 mod_timer(&phba->hw_check, 5262 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL)); 5263 } 5264 5265 /* 5266 * beiscsi_enable_port()- Enables the disabled port. 5267 * Only port resources freed in disable function are reallocated. 5268 * This is called in HBA error handling path. 5269 * 5270 * @phba: Instance of driver private structure 5271 * 5272 **/ 5273 static int beiscsi_enable_port(struct beiscsi_hba *phba) 5274 { 5275 struct hwi_context_memory *phwi_context; 5276 struct hwi_controller *phwi_ctrlr; 5277 struct be_eq_obj *pbe_eq; 5278 int ret, i; 5279 5280 if (test_bit(BEISCSI_HBA_ONLINE, &phba->state)) { 5281 __beiscsi_log(phba, KERN_ERR, 5282 "BM_%d : %s : port is online %lx\n", 5283 __func__, phba->state); 5284 return 0; 5285 } 5286 5287 ret = beiscsi_init_sliport(phba); 5288 if (ret) 5289 return ret; 5290 5291 be2iscsi_enable_msix(phba); 5292 5293 beiscsi_get_params(phba); 5294 beiscsi_set_host_data(phba); 5295 /* Re-enable UER. If different TPE occurs then it is recoverable. */ 5296 beiscsi_set_uer_feature(phba); 5297 5298 phba->shost->max_id = phba->params.cxns_per_ctrl - 1; 5299 phba->shost->can_queue = phba->params.ios_per_ctrl; 5300 ret = beiscsi_init_port(phba); 5301 if (ret < 0) { 5302 __beiscsi_log(phba, KERN_ERR, 5303 "BM_%d : init port failed\n"); 5304 goto disable_msix; 5305 } 5306 5307 for (i = 0; i < MAX_MCC_CMD; i++) { 5308 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); 5309 phba->ctrl.mcc_tag[i] = i + 1; 5310 phba->ctrl.mcc_tag_status[i + 1] = 0; 5311 phba->ctrl.mcc_tag_available++; 5312 } 5313 5314 phwi_ctrlr = phba->phwi_ctrlr; 5315 phwi_context = phwi_ctrlr->phwi_ctxt; 5316 for (i = 0; i < phba->num_cpus; i++) { 5317 pbe_eq = &phwi_context->be_eq[i]; 5318 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, be_iopoll); 5319 } 5320 5321 i = (phba->pcidev->msix_enabled) ? i : 0; 5322 /* Work item for MCC handling */ 5323 pbe_eq = &phwi_context->be_eq[i]; 5324 INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work); 5325 5326 ret = beiscsi_init_irqs(phba); 5327 if (ret < 0) { 5328 __beiscsi_log(phba, KERN_ERR, 5329 "BM_%d : setup IRQs failed %d\n", ret); 5330 goto cleanup_port; 5331 } 5332 hwi_enable_intr(phba); 5333 /* port operational: clear all error bits */ 5334 set_bit(BEISCSI_HBA_ONLINE, &phba->state); 5335 __beiscsi_log(phba, KERN_INFO, 5336 "BM_%d : port online: 0x%lx\n", phba->state); 5337 5338 /* start hw_check timer and eqd_update work */ 5339 schedule_delayed_work(&phba->eqd_update, 5340 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL)); 5341 5342 /** 5343 * Timer function gets modified for TPE detection. 5344 * Always reinit to do health check first. 5345 */ 5346 phba->hw_check.function = beiscsi_hw_health_check; 5347 mod_timer(&phba->hw_check, 5348 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL)); 5349 return 0; 5350 5351 cleanup_port: 5352 for (i = 0; i < phba->num_cpus; i++) { 5353 pbe_eq = &phwi_context->be_eq[i]; 5354 irq_poll_disable(&pbe_eq->iopoll); 5355 } 5356 hwi_cleanup_port(phba); 5357 5358 disable_msix: 5359 pci_free_irq_vectors(phba->pcidev); 5360 return ret; 5361 } 5362 5363 /* 5364 * beiscsi_disable_port()- Disable port and cleanup driver resources. 5365 * This is called in HBA error handling and driver removal. 5366 * @phba: Instance Priv structure 5367 * @unload: indicate driver is unloading 5368 * 5369 * Free the OS and HW resources held by the driver 5370 **/ 5371 static void beiscsi_disable_port(struct beiscsi_hba *phba, int unload) 5372 { 5373 struct hwi_context_memory *phwi_context; 5374 struct hwi_controller *phwi_ctrlr; 5375 struct be_eq_obj *pbe_eq; 5376 unsigned int i; 5377 5378 if (!test_and_clear_bit(BEISCSI_HBA_ONLINE, &phba->state)) 5379 return; 5380 5381 phwi_ctrlr = phba->phwi_ctrlr; 5382 phwi_context = phwi_ctrlr->phwi_ctxt; 5383 hwi_disable_intr(phba); 5384 beiscsi_free_irqs(phba); 5385 pci_free_irq_vectors(phba->pcidev); 5386 5387 for (i = 0; i < phba->num_cpus; i++) { 5388 pbe_eq = &phwi_context->be_eq[i]; 5389 irq_poll_disable(&pbe_eq->iopoll); 5390 } 5391 cancel_delayed_work_sync(&phba->eqd_update); 5392 cancel_work_sync(&phba->boot_work); 5393 /* WQ might be running cancel queued mcc_work if we are not exiting */ 5394 if (!unload && beiscsi_hba_in_error(phba)) { 5395 pbe_eq = &phwi_context->be_eq[i]; 5396 cancel_work_sync(&pbe_eq->mcc_work); 5397 } 5398 hwi_cleanup_port(phba); 5399 beiscsi_cleanup_port(phba); 5400 } 5401 5402 static void beiscsi_sess_work(struct work_struct *work) 5403 { 5404 struct beiscsi_hba *phba; 5405 5406 phba = container_of(work, struct beiscsi_hba, sess_work); 5407 /* 5408 * This work gets scheduled only in case of HBA error. 5409 * Old sessions are gone so need to be re-established. 5410 * iscsi_session_failure needs process context hence this work. 5411 */ 5412 iscsi_host_for_each_session(phba->shost, beiscsi_session_fail); 5413 } 5414 5415 static void beiscsi_recover_port(struct work_struct *work) 5416 { 5417 struct beiscsi_hba *phba; 5418 5419 phba = container_of(work, struct beiscsi_hba, recover_port.work); 5420 beiscsi_disable_port(phba, 0); 5421 beiscsi_enable_port(phba); 5422 } 5423 5424 static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev, 5425 pci_channel_state_t state) 5426 { 5427 struct beiscsi_hba *phba = NULL; 5428 5429 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); 5430 set_bit(BEISCSI_HBA_PCI_ERR, &phba->state); 5431 5432 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5433 "BM_%d : EEH error detected\n"); 5434 5435 /* first stop UE detection when PCI error detected */ 5436 timer_delete_sync(&phba->hw_check); 5437 cancel_delayed_work_sync(&phba->recover_port); 5438 5439 /* sessions are no longer valid, so first fail the sessions */ 5440 iscsi_host_for_each_session(phba->shost, beiscsi_session_fail); 5441 beiscsi_disable_port(phba, 0); 5442 5443 if (state == pci_channel_io_perm_failure) { 5444 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5445 "BM_%d : EEH : State PERM Failure"); 5446 return PCI_ERS_RESULT_DISCONNECT; 5447 } 5448 5449 pci_disable_device(pdev); 5450 5451 /* The error could cause the FW to trigger a flash debug dump. 5452 * Resetting the card while flash dump is in progress 5453 * can cause it not to recover; wait for it to finish. 5454 * Wait only for first function as it is needed only once per 5455 * adapter. 5456 **/ 5457 if (pdev->devfn == 0) 5458 ssleep(30); 5459 5460 return PCI_ERS_RESULT_NEED_RESET; 5461 } 5462 5463 static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev) 5464 { 5465 struct beiscsi_hba *phba = NULL; 5466 int status = 0; 5467 5468 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); 5469 5470 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5471 "BM_%d : EEH Reset\n"); 5472 5473 status = pci_enable_device(pdev); 5474 if (status) 5475 return PCI_ERS_RESULT_DISCONNECT; 5476 5477 pci_set_master(pdev); 5478 pci_set_power_state(pdev, PCI_D0); 5479 pci_restore_state(pdev); 5480 5481 status = beiscsi_check_fw_rdy(phba); 5482 if (status) { 5483 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, 5484 "BM_%d : EEH Reset Completed\n"); 5485 } else { 5486 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, 5487 "BM_%d : EEH Reset Completion Failure\n"); 5488 return PCI_ERS_RESULT_DISCONNECT; 5489 } 5490 5491 return PCI_ERS_RESULT_RECOVERED; 5492 } 5493 5494 static void beiscsi_eeh_resume(struct pci_dev *pdev) 5495 { 5496 struct beiscsi_hba *phba; 5497 int ret; 5498 5499 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); 5500 pci_save_state(pdev); 5501 5502 ret = beiscsi_enable_port(phba); 5503 if (ret) 5504 __beiscsi_log(phba, KERN_ERR, 5505 "BM_%d : AER EEH resume failed\n"); 5506 } 5507 5508 static int beiscsi_dev_probe(struct pci_dev *pcidev, 5509 const struct pci_device_id *id) 5510 { 5511 struct hwi_context_memory *phwi_context; 5512 struct hwi_controller *phwi_ctrlr; 5513 struct beiscsi_hba *phba = NULL; 5514 struct be_eq_obj *pbe_eq; 5515 unsigned int s_handle; 5516 int ret, i; 5517 5518 ret = beiscsi_enable_pci(pcidev); 5519 if (ret < 0) { 5520 dev_err(&pcidev->dev, 5521 "beiscsi_dev_probe - Failed to enable pci device\n"); 5522 return ret; 5523 } 5524 5525 phba = beiscsi_hba_alloc(pcidev); 5526 if (!phba) { 5527 dev_err(&pcidev->dev, 5528 "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n"); 5529 ret = -ENOMEM; 5530 goto disable_pci; 5531 } 5532 5533 pci_save_state(pcidev); 5534 5535 /* Initialize Driver configuration Paramters */ 5536 beiscsi_hba_attrs_init(phba); 5537 5538 phba->mac_addr_set = false; 5539 5540 switch (pcidev->device) { 5541 case BE_DEVICE_ID1: 5542 case OC_DEVICE_ID1: 5543 case OC_DEVICE_ID2: 5544 phba->generation = BE_GEN2; 5545 phba->iotask_fn = beiscsi_iotask; 5546 dev_warn(&pcidev->dev, 5547 "Obsolete/Unsupported BE2 Adapter Family\n"); 5548 break; 5549 case BE_DEVICE_ID2: 5550 case OC_DEVICE_ID3: 5551 phba->generation = BE_GEN3; 5552 phba->iotask_fn = beiscsi_iotask; 5553 break; 5554 case OC_SKH_ID1: 5555 phba->generation = BE_GEN4; 5556 phba->iotask_fn = beiscsi_iotask_v2; 5557 break; 5558 default: 5559 phba->generation = 0; 5560 } 5561 5562 ret = be_ctrl_init(phba, pcidev); 5563 if (ret) { 5564 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5565 "BM_%d : be_ctrl_init failed\n"); 5566 goto free_hba; 5567 } 5568 5569 ret = beiscsi_init_sliport(phba); 5570 if (ret) 5571 goto free_hba; 5572 5573 spin_lock_init(&phba->io_sgl_lock); 5574 spin_lock_init(&phba->mgmt_sgl_lock); 5575 spin_lock_init(&phba->async_pdu_lock); 5576 ret = beiscsi_get_fw_config(&phba->ctrl, phba); 5577 if (ret != 0) { 5578 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5579 "BM_%d : Error getting fw config\n"); 5580 goto free_port; 5581 } 5582 beiscsi_get_port_name(&phba->ctrl, phba); 5583 beiscsi_get_params(phba); 5584 beiscsi_set_host_data(phba); 5585 beiscsi_set_uer_feature(phba); 5586 5587 be2iscsi_enable_msix(phba); 5588 5589 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 5590 "BM_%d : num_cpus = %d\n", 5591 phba->num_cpus); 5592 5593 phba->shost->max_id = phba->params.cxns_per_ctrl; 5594 phba->shost->can_queue = phba->params.ios_per_ctrl; 5595 ret = beiscsi_get_memory(phba); 5596 if (ret < 0) { 5597 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5598 "BM_%d : alloc host mem failed\n"); 5599 goto free_port; 5600 } 5601 5602 ret = beiscsi_init_port(phba); 5603 if (ret < 0) { 5604 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5605 "BM_%d : init port failed\n"); 5606 beiscsi_free_mem(phba); 5607 goto free_port; 5608 } 5609 5610 for (i = 0; i < MAX_MCC_CMD; i++) { 5611 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); 5612 phba->ctrl.mcc_tag[i] = i + 1; 5613 phba->ctrl.mcc_tag_status[i + 1] = 0; 5614 phba->ctrl.mcc_tag_available++; 5615 memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0, 5616 sizeof(struct be_dma_mem)); 5617 } 5618 5619 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0; 5620 5621 phba->wq = alloc_workqueue("beiscsi_%02x_wq", 5622 WQ_MEM_RECLAIM | WQ_PERCPU, 1, 5623 phba->shost->host_no); 5624 if (!phba->wq) { 5625 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5626 "BM_%d : beiscsi_dev_probe-" 5627 "Failed to allocate work queue\n"); 5628 ret = -ENOMEM; 5629 goto free_twq; 5630 } 5631 5632 INIT_DELAYED_WORK(&phba->eqd_update, beiscsi_eqd_update_work); 5633 5634 phwi_ctrlr = phba->phwi_ctrlr; 5635 phwi_context = phwi_ctrlr->phwi_ctxt; 5636 5637 for (i = 0; i < phba->num_cpus; i++) { 5638 pbe_eq = &phwi_context->be_eq[i]; 5639 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, be_iopoll); 5640 } 5641 5642 i = (phba->pcidev->msix_enabled) ? i : 0; 5643 /* Work item for MCC handling */ 5644 pbe_eq = &phwi_context->be_eq[i]; 5645 INIT_WORK(&pbe_eq->mcc_work, beiscsi_mcc_work); 5646 5647 ret = beiscsi_init_irqs(phba); 5648 if (ret < 0) { 5649 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 5650 "BM_%d : beiscsi_dev_probe-" 5651 "Failed to beiscsi_init_irqs\n"); 5652 goto disable_iopoll; 5653 } 5654 hwi_enable_intr(phba); 5655 5656 ret = iscsi_host_add(phba->shost, &phba->pcidev->dev); 5657 if (ret) 5658 goto free_irqs; 5659 5660 /* set online bit after port is operational */ 5661 set_bit(BEISCSI_HBA_ONLINE, &phba->state); 5662 __beiscsi_log(phba, KERN_INFO, 5663 "BM_%d : port online: 0x%lx\n", phba->state); 5664 5665 INIT_WORK(&phba->boot_work, beiscsi_boot_work); 5666 ret = beiscsi_boot_get_shandle(phba, &s_handle); 5667 if (ret > 0) { 5668 beiscsi_start_boot_work(phba, s_handle); 5669 /** 5670 * Set this bit after starting the work to let 5671 * probe handle it first. 5672 * ASYNC event can too schedule this work. 5673 */ 5674 set_bit(BEISCSI_HBA_BOOT_FOUND, &phba->state); 5675 } 5676 5677 beiscsi_iface_create_default(phba); 5678 schedule_delayed_work(&phba->eqd_update, 5679 msecs_to_jiffies(BEISCSI_EQD_UPDATE_INTERVAL)); 5680 5681 INIT_WORK(&phba->sess_work, beiscsi_sess_work); 5682 INIT_DELAYED_WORK(&phba->recover_port, beiscsi_recover_port); 5683 /** 5684 * Start UE detection here. UE before this will cause stall in probe 5685 * and eventually fail the probe. 5686 */ 5687 timer_setup(&phba->hw_check, beiscsi_hw_health_check, 0); 5688 mod_timer(&phba->hw_check, 5689 jiffies + msecs_to_jiffies(BEISCSI_UE_DETECT_INTERVAL)); 5690 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 5691 "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n"); 5692 return 0; 5693 5694 free_irqs: 5695 hwi_disable_intr(phba); 5696 beiscsi_free_irqs(phba); 5697 disable_iopoll: 5698 for (i = 0; i < phba->num_cpus; i++) { 5699 pbe_eq = &phwi_context->be_eq[i]; 5700 irq_poll_disable(&pbe_eq->iopoll); 5701 } 5702 destroy_workqueue(phba->wq); 5703 free_twq: 5704 hwi_cleanup_port(phba); 5705 beiscsi_cleanup_port(phba); 5706 beiscsi_free_mem(phba); 5707 free_port: 5708 dma_free_coherent(&phba->pcidev->dev, 5709 phba->ctrl.mbox_mem_alloced.size, 5710 phba->ctrl.mbox_mem_alloced.va, 5711 phba->ctrl.mbox_mem_alloced.dma); 5712 beiscsi_unmap_pci_function(phba); 5713 free_hba: 5714 pci_disable_msix(phba->pcidev); 5715 pci_dev_put(phba->pcidev); 5716 iscsi_host_free(phba->shost); 5717 pci_set_drvdata(pcidev, NULL); 5718 disable_pci: 5719 pci_release_regions(pcidev); 5720 pci_disable_device(pcidev); 5721 return ret; 5722 } 5723 5724 static void beiscsi_remove(struct pci_dev *pcidev) 5725 { 5726 struct beiscsi_hba *phba = NULL; 5727 5728 phba = pci_get_drvdata(pcidev); 5729 if (!phba) { 5730 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n"); 5731 return; 5732 } 5733 5734 /* first stop UE detection before unloading */ 5735 timer_delete_sync(&phba->hw_check); 5736 cancel_delayed_work_sync(&phba->recover_port); 5737 cancel_work_sync(&phba->sess_work); 5738 5739 beiscsi_iface_destroy_default(phba); 5740 iscsi_host_remove(phba->shost, false); 5741 beiscsi_disable_port(phba, 1); 5742 5743 /* after cancelling boot_work */ 5744 iscsi_boot_destroy_kset(phba->boot_struct.boot_kset); 5745 5746 /* free all resources */ 5747 destroy_workqueue(phba->wq); 5748 beiscsi_free_mem(phba); 5749 5750 /* ctrl uninit */ 5751 beiscsi_unmap_pci_function(phba); 5752 dma_free_coherent(&phba->pcidev->dev, 5753 phba->ctrl.mbox_mem_alloced.size, 5754 phba->ctrl.mbox_mem_alloced.va, 5755 phba->ctrl.mbox_mem_alloced.dma); 5756 5757 pci_dev_put(phba->pcidev); 5758 iscsi_host_free(phba->shost); 5759 pci_set_drvdata(pcidev, NULL); 5760 pci_release_regions(pcidev); 5761 pci_disable_device(pcidev); 5762 } 5763 5764 5765 static const struct pci_error_handlers beiscsi_eeh_handlers = { 5766 .error_detected = beiscsi_eeh_err_detected, 5767 .slot_reset = beiscsi_eeh_reset, 5768 .resume = beiscsi_eeh_resume, 5769 }; 5770 5771 struct iscsi_transport beiscsi_iscsi_transport = { 5772 .owner = THIS_MODULE, 5773 .name = DRV_NAME, 5774 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO | 5775 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD, 5776 .create_session = beiscsi_session_create, 5777 .destroy_session = beiscsi_session_destroy, 5778 .create_conn = beiscsi_conn_create, 5779 .bind_conn = beiscsi_conn_bind, 5780 .unbind_conn = iscsi_conn_unbind, 5781 .destroy_conn = iscsi_conn_teardown, 5782 .attr_is_visible = beiscsi_attr_is_visible, 5783 .set_iface_param = beiscsi_iface_set_param, 5784 .get_iface_param = beiscsi_iface_get_param, 5785 .set_param = beiscsi_set_param, 5786 .get_conn_param = iscsi_conn_get_param, 5787 .get_session_param = iscsi_session_get_param, 5788 .get_host_param = beiscsi_get_host_param, 5789 .start_conn = beiscsi_conn_start, 5790 .stop_conn = iscsi_conn_stop, 5791 .send_pdu = iscsi_conn_send_pdu, 5792 .xmit_task = beiscsi_task_xmit, 5793 .cleanup_task = beiscsi_cleanup_task, 5794 .alloc_pdu = beiscsi_alloc_pdu, 5795 .parse_pdu_itt = beiscsi_parse_pdu, 5796 .get_stats = beiscsi_conn_get_stats, 5797 .get_ep_param = beiscsi_ep_get_param, 5798 .ep_connect = beiscsi_ep_connect, 5799 .ep_poll = beiscsi_ep_poll, 5800 .ep_disconnect = beiscsi_ep_disconnect, 5801 .session_recovery_timedout = iscsi_session_recovery_timedout, 5802 .bsg_request = beiscsi_bsg_request, 5803 }; 5804 5805 static struct pci_driver beiscsi_pci_driver = { 5806 .name = DRV_NAME, 5807 .probe = beiscsi_dev_probe, 5808 .remove = beiscsi_remove, 5809 .id_table = beiscsi_pci_id_table, 5810 .err_handler = &beiscsi_eeh_handlers 5811 }; 5812 5813 static int __init beiscsi_module_init(void) 5814 { 5815 int ret; 5816 5817 beiscsi_scsi_transport = 5818 iscsi_register_transport(&beiscsi_iscsi_transport); 5819 if (!beiscsi_scsi_transport) { 5820 printk(KERN_ERR 5821 "beiscsi_module_init - Unable to register beiscsi transport.\n"); 5822 return -ENOMEM; 5823 } 5824 printk(KERN_INFO "In beiscsi_module_init, tt=%p\n", 5825 &beiscsi_iscsi_transport); 5826 5827 ret = pci_register_driver(&beiscsi_pci_driver); 5828 if (ret) { 5829 printk(KERN_ERR 5830 "beiscsi_module_init - Unable to register beiscsi pci driver.\n"); 5831 goto unregister_iscsi_transport; 5832 } 5833 return 0; 5834 5835 unregister_iscsi_transport: 5836 iscsi_unregister_transport(&beiscsi_iscsi_transport); 5837 return ret; 5838 } 5839 5840 static void __exit beiscsi_module_exit(void) 5841 { 5842 pci_unregister_driver(&beiscsi_pci_driver); 5843 iscsi_unregister_transport(&beiscsi_iscsi_transport); 5844 } 5845 5846 module_init(beiscsi_module_init); 5847 module_exit(beiscsi_module_exit); 5848