xref: /linux/drivers/scsi/aic7xxx/aic79xx.h (revision 14b42963f64b98ab61fa9723c03d71aa5ef4f862)
1 /*
2  * Core definitions and data structures shareable across OS platforms.
3  *
4  * Copyright (c) 1994-2002 Justin T. Gibbs.
5  * Copyright (c) 2000-2002 Adaptec Inc.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions, and the following disclaimer,
13  *    without modification.
14  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15  *    substantially similar to the "NO WARRANTY" disclaimer below
16  *    ("Disclaimer") and any redistribution must be conditioned upon
17  *    including a substantially similar Disclaimer requirement for further
18  *    binary redistribution.
19  * 3. Neither the names of the above-listed copyright holders nor the names
20  *    of any contributors may be used to endorse or promote products derived
21  *    from this software without specific prior written permission.
22  *
23  * Alternatively, this software may be distributed under the terms of the
24  * GNU General Public License ("GPL") version 2 as published by the Free
25  * Software Foundation.
26  *
27  * NO WARRANTY
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGES.
39  *
40  * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#109 $
41  *
42  * $FreeBSD$
43  */
44 
45 #ifndef _AIC79XX_H_
46 #define _AIC79XX_H_
47 
48 /* Register Definitions */
49 #include "aic79xx_reg.h"
50 
51 /************************* Forward Declarations *******************************/
52 struct ahd_platform_data;
53 struct scb_platform_data;
54 
55 /****************************** Useful Macros *********************************/
56 #ifndef MAX
57 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
58 #endif
59 
60 #ifndef MIN
61 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
62 #endif
63 
64 #ifndef TRUE
65 #define TRUE 1
66 #endif
67 #ifndef FALSE
68 #define FALSE 0
69 #endif
70 
71 #define ALL_CHANNELS '\0'
72 #define ALL_TARGETS_MASK 0xFFFF
73 #define INITIATOR_WILDCARD	(~0)
74 #define	SCB_LIST_NULL		0xFF00
75 #define	SCB_LIST_NULL_LE	(ahd_htole16(SCB_LIST_NULL))
76 #define QOUTFIFO_ENTRY_VALID 0x80
77 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
78 
79 #define SCSIID_TARGET(ahd, scsiid)	\
80 	(((scsiid) & TID) >> TID_SHIFT)
81 #define SCSIID_OUR_ID(scsiid)		\
82 	((scsiid) & OID)
83 #define SCSIID_CHANNEL(ahd, scsiid) ('A')
84 #define	SCB_IS_SCSIBUS_B(ahd, scb) (0)
85 #define	SCB_GET_OUR_ID(scb) \
86 	SCSIID_OUR_ID((scb)->hscb->scsiid)
87 #define	SCB_GET_TARGET(ahd, scb) \
88 	SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
89 #define	SCB_GET_CHANNEL(ahd, scb) \
90 	SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
91 #define	SCB_GET_LUN(scb) \
92 	((scb)->hscb->lun)
93 #define SCB_GET_TARGET_OFFSET(ahd, scb)	\
94 	SCB_GET_TARGET(ahd, scb)
95 #define SCB_GET_TARGET_MASK(ahd, scb) \
96 	(0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
97 #ifdef AHD_DEBUG
98 #define SCB_IS_SILENT(scb)					\
99 	((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0		\
100       && (((scb)->flags & SCB_SILENT) != 0))
101 #else
102 #define SCB_IS_SILENT(scb)					\
103 	(((scb)->flags & SCB_SILENT) != 0)
104 #endif
105 /*
106  * TCLs have the following format: TTTTLLLLLLLL
107  */
108 #define TCL_TARGET_OFFSET(tcl) \
109 	((((tcl) >> 4) & TID) >> 4)
110 #define TCL_LUN(tcl) \
111 	(tcl & (AHD_NUM_LUNS - 1))
112 #define BUILD_TCL(scsiid, lun) \
113 	((lun) | (((scsiid) & TID) << 4))
114 #define BUILD_TCL_RAW(target, channel, lun) \
115 	((lun) | ((target) << 8))
116 
117 #define SCB_GET_TAG(scb) \
118 	ahd_le16toh(scb->hscb->tag)
119 
120 #ifndef	AHD_TARGET_MODE
121 #undef	AHD_TMODE_ENABLE
122 #define	AHD_TMODE_ENABLE 0
123 #endif
124 
125 #define AHD_BUILD_COL_IDX(target, lun)				\
126 	(((lun) << 4) | target)
127 
128 #define AHD_GET_SCB_COL_IDX(ahd, scb)				\
129 	((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
130 
131 #define AHD_SET_SCB_COL_IDX(scb, col_idx)				\
132 do {									\
133 	(scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID;		\
134 	(scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1);	\
135 } while (0)
136 
137 #define AHD_COPY_SCB_COL_IDX(dst, src)				\
138 do {								\
139 	dst->hscb->scsiid = src->hscb->scsiid;			\
140 	dst->hscb->lun = src->hscb->lun;			\
141 } while (0)
142 
143 #define	AHD_NEVER_COL_IDX 0xFFFF
144 
145 /**************************** Driver Constants ********************************/
146 /*
147  * The maximum number of supported targets.
148  */
149 #define AHD_NUM_TARGETS 16
150 
151 /*
152  * The maximum number of supported luns.
153  * The identify message only supports 64 luns in non-packetized transfers.
154  * You can have 2^64 luns when information unit transfers are enabled,
155  * but until we see a need to support that many, we support 256.
156  */
157 #define AHD_NUM_LUNS_NONPKT 64
158 #define AHD_NUM_LUNS 256
159 
160 /*
161  * The maximum transfer per S/G segment.
162  */
163 #define AHD_MAXTRANSFER_SIZE	 0x00ffffff	/* limited by 24bit counter */
164 
165 /*
166  * The maximum amount of SCB storage in hardware on a controller.
167  * This value represents an upper bound.  Due to software design,
168  * we may not be able to use this number.
169  */
170 #define AHD_SCB_MAX	512
171 
172 /*
173  * The maximum number of concurrent transactions supported per driver instance.
174  * Sequencer Control Blocks (SCBs) store per-transaction information.
175  */
176 #define AHD_MAX_QUEUE	AHD_SCB_MAX
177 
178 /*
179  * Define the size of our QIN and QOUT FIFOs.  They must be a power of 2
180  * in size and accommodate as many transactions as can be queued concurrently.
181  */
182 #define	AHD_QIN_SIZE	AHD_MAX_QUEUE
183 #define	AHD_QOUT_SIZE	AHD_MAX_QUEUE
184 
185 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
186 /*
187  * The maximum amount of SCB storage we allocate in host memory.
188  */
189 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
190 
191 /*
192  * Ring Buffer of incoming target commands.
193  * We allocate 256 to simplify the logic in the sequencer
194  * by using the natural wrap point of an 8bit counter.
195  */
196 #define AHD_TMODE_CMDS	256
197 
198 /* Reset line assertion time in us */
199 #define AHD_BUSRESET_DELAY	25
200 
201 /******************* Chip Characteristics/Operating Settings  *****************/
202 /*
203  * Chip Type
204  * The chip order is from least sophisticated to most sophisticated.
205  */
206 typedef enum {
207 	AHD_NONE	= 0x0000,
208 	AHD_CHIPID_MASK	= 0x00FF,
209 	AHD_AIC7901	= 0x0001,
210 	AHD_AIC7902	= 0x0002,
211 	AHD_AIC7901A	= 0x0003,
212 	AHD_PCI		= 0x0100,	/* Bus type PCI */
213 	AHD_PCIX	= 0x0200,	/* Bus type PCIX */
214 	AHD_BUS_MASK	= 0x0F00
215 } ahd_chip;
216 
217 /*
218  * Features available in each chip type.
219  */
220 typedef enum {
221 	AHD_FENONE		= 0x00000,
222 	AHD_WIDE  		= 0x00001,/* Wide Channel */
223 	AHD_AIC79XXB_SLOWCRC    = 0x00002,/* SLOWCRC bit should be set */
224 	AHD_MULTI_FUNC		= 0x00100,/* Multi-Function/Channel Device */
225 	AHD_TARGETMODE		= 0x01000,/* Has tested target mode support */
226 	AHD_MULTIROLE		= 0x02000,/* Space for two roles at a time */
227 	AHD_RTI			= 0x04000,/* Retained Training Support */
228 	AHD_NEW_IOCELL_OPTS	= 0x08000,/* More Signal knobs in the IOCELL */
229 	AHD_NEW_DFCNTRL_OPTS	= 0x10000,/* SCSIENWRDIS bit */
230 	AHD_FAST_CDB_DELIVERY	= 0x20000,/* CDB acks released to Output Sync */
231 	AHD_REMOVABLE		= 0x00000,/* Hot-Swap supported - None so far*/
232 	AHD_AIC7901_FE		= AHD_FENONE,
233 	AHD_AIC7901A_FE		= AHD_FENONE,
234 	AHD_AIC7902_FE		= AHD_MULTI_FUNC
235 } ahd_feature;
236 
237 /*
238  * Bugs in the silicon that we work around in software.
239  */
240 typedef enum {
241 	AHD_BUGNONE		= 0x0000,
242 	/*
243 	 * Rev A hardware fails to update LAST/CURR/NEXTSCB
244 	 * correctly in certain packetized selection cases.
245 	 */
246 	AHD_SENT_SCB_UPDATE_BUG	= 0x0001,
247 	/* The wrong SCB is accessed to check the abort pending bit. */
248 	AHD_ABORT_LQI_BUG	= 0x0002,
249 	/* Packetized bitbucket crosses packet boundaries. */
250 	AHD_PKT_BITBUCKET_BUG	= 0x0004,
251 	/* The selection timer runs twice as long as its setting. */
252 	AHD_LONG_SETIMO_BUG	= 0x0008,
253 	/* The Non-LQ CRC error status is delayed until phase change. */
254 	AHD_NLQICRC_DELAYED_BUG	= 0x0010,
255 	/* The chip must be reset for all outgoing bus resets.  */
256 	AHD_SCSIRST_BUG		= 0x0020,
257 	/* Some PCIX fields must be saved and restored across chip reset. */
258 	AHD_PCIX_CHIPRST_BUG	= 0x0040,
259 	/* MMAPIO is not functional in PCI-X mode.  */
260 	AHD_PCIX_MMAPIO_BUG	= 0x0080,
261 	/* Reads to SCBRAM fail to reset the discard timer. */
262 	AHD_PCIX_SCBRAM_RD_BUG  = 0x0100,
263 	/* Bug workarounds that can be disabled on non-PCIX busses. */
264 	AHD_PCIX_BUG_MASK	= AHD_PCIX_CHIPRST_BUG
265 				| AHD_PCIX_MMAPIO_BUG
266 				| AHD_PCIX_SCBRAM_RD_BUG,
267 	/*
268 	 * LQOSTOP0 status set even for forced selections with ATN
269 	 * to perform non-packetized message delivery.
270 	 */
271 	AHD_LQO_ATNO_BUG	= 0x0200,
272 	/* FIFO auto-flush does not always trigger.  */
273 	AHD_AUTOFLUSH_BUG	= 0x0400,
274 	/* The CLRLQO registers are not self-clearing. */
275 	AHD_CLRLQO_AUTOCLR_BUG	= 0x0800,
276 	/* The PACKETIZED status bit refers to the previous connection. */
277 	AHD_PKTIZED_STATUS_BUG  = 0x1000,
278 	/* "Short Luns" are not placed into outgoing LQ packets correctly. */
279 	AHD_PKT_LUN_BUG		= 0x2000,
280 	/*
281 	 * Only the FIFO allocated to the non-packetized connection may
282 	 * be in use during a non-packetzied connection.
283 	 */
284 	AHD_NONPACKFIFO_BUG	= 0x4000,
285 	/*
286 	 * Writing to a DFF SCBPTR register may fail if concurent with
287 	 * a hardware write to the other DFF SCBPTR register.  This is
288 	 * not currently a concern in our sequencer since all chips with
289 	 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
290 	 * occur in non-packetized connections.
291 	 */
292 	AHD_MDFF_WSCBPTR_BUG	= 0x8000,
293 	/* SGHADDR updates are slow. */
294 	AHD_REG_SLOW_SETTLE_BUG	= 0x10000,
295 	/*
296 	 * Changing the MODE_PTR coincident with an interrupt that
297 	 * switches to a different mode will cause the interrupt to
298 	 * be in the mode written outside of interrupt context.
299 	 */
300 	AHD_SET_MODE_BUG	= 0x20000,
301 	/* Non-packetized busfree revision does not work. */
302 	AHD_BUSFREEREV_BUG	= 0x40000,
303 	/*
304 	 * Paced transfers are indicated with a non-standard PPR
305 	 * option bit in the neg table, 160MHz is indicated by
306 	 * sync factor 0x7, and the offset if off by a factor of 2.
307 	 */
308 	AHD_PACED_NEGTABLE_BUG	= 0x80000,
309 	/* LQOOVERRUN false positives. */
310 	AHD_LQOOVERRUN_BUG	= 0x100000,
311 	/*
312 	 * Controller write to INTSTAT will lose to a host
313 	 * write to CLRINT.
314 	 */
315 	AHD_INTCOLLISION_BUG	= 0x200000,
316 	/*
317 	 * The GEM318 violates the SCSI spec by not waiting
318 	 * the mandated bus settle delay between phase changes
319 	 * in some situations.  Some aic79xx chip revs. are more
320 	 * strict in this regard and will treat REQ assertions
321 	 * that fall within the bus settle delay window as
322 	 * glitches.  This flag tells the firmware to tolerate
323 	 * early REQ assertions.
324 	 */
325 	AHD_EARLY_REQ_BUG	= 0x400000,
326 	/*
327 	 * The LED does not stay on long enough in packetized modes.
328 	 */
329 	AHD_FAINT_LED_BUG	= 0x800000
330 } ahd_bug;
331 
332 /*
333  * Configuration specific settings.
334  * The driver determines these settings by probing the
335  * chip/controller's configuration.
336  */
337 typedef enum {
338 	AHD_FNONE	      = 0x00000,
339 	AHD_BOOT_CHANNEL      = 0x00001,/* We were set as the boot channel. */
340 	AHD_USEDEFAULTS	      = 0x00004,/*
341 					 * For cards without an seeprom
342 					 * or a BIOS to initialize the chip's
343 					 * SRAM, we use the default target
344 					 * settings.
345 					 */
346 	AHD_SEQUENCER_DEBUG   = 0x00008,
347 	AHD_RESET_BUS_A	      = 0x00010,
348 	AHD_EXTENDED_TRANS_A  = 0x00020,
349 	AHD_TERM_ENB_A	      = 0x00040,
350 	AHD_SPCHK_ENB_A	      = 0x00080,
351 	AHD_STPWLEVEL_A	      = 0x00100,
352 	AHD_INITIATORROLE     = 0x00200,/*
353 					 * Allow initiator operations on
354 					 * this controller.
355 					 */
356 	AHD_TARGETROLE	      = 0x00400,/*
357 					 * Allow target operations on this
358 					 * controller.
359 					 */
360 	AHD_RESOURCE_SHORTAGE = 0x00800,
361 	AHD_TQINFIFO_BLOCKED  = 0x01000,/* Blocked waiting for ATIOs */
362 	AHD_INT50_SPEEDFLEX   = 0x02000,/*
363 					 * Internal 50pin connector
364 					 * sits behind an aic3860
365 					 */
366 	AHD_BIOS_ENABLED      = 0x04000,
367 	AHD_ALL_INTERRUPTS    = 0x08000,
368 	AHD_39BIT_ADDRESSING  = 0x10000,/* Use 39 bit addressing scheme. */
369 	AHD_64BIT_ADDRESSING  = 0x20000,/* Use 64 bit addressing scheme. */
370 	AHD_CURRENT_SENSING   = 0x40000,
371 	AHD_SCB_CONFIG_USED   = 0x80000,/* No SEEPROM but SCB had info. */
372 	AHD_HP_BOARD	      = 0x100000,
373 	AHD_BUS_RESET_ACTIVE  = 0x200000,
374 	AHD_UPDATE_PEND_CMDS  = 0x400000,
375 	AHD_RUNNING_QOUTFIFO  = 0x800000,
376 	AHD_HAD_FIRST_SEL     = 0x1000000
377 } ahd_flag;
378 
379 /************************* Hardware  SCB Definition ***************************/
380 
381 /*
382  * The driver keeps up to MAX_SCB scb structures per card in memory.  The SCB
383  * consists of a "hardware SCB" mirroring the fields available on the card
384  * and additional information the kernel stores for each transaction.
385  *
386  * To minimize space utilization, a portion of the hardware scb stores
387  * different data during different portions of a SCSI transaction.
388  * As initialized by the host driver for the initiator role, this area
389  * contains the SCSI cdb (or a pointer to the  cdb) to be executed.  After
390  * the cdb has been presented to the target, this area serves to store
391  * residual transfer information and the SCSI status byte.
392  * For the target role, the contents of this area do not change, but
393  * still serve a different purpose than for the initiator role.  See
394  * struct target_data for details.
395  */
396 
397 /*
398  * Status information embedded in the shared poriton of
399  * an SCB after passing the cdb to the target.  The kernel
400  * driver will only read this data for transactions that
401  * complete abnormally.
402  */
403 struct initiator_status {
404 	uint32_t residual_datacnt;	/* Residual in the current S/G seg */
405 	uint32_t residual_sgptr;	/* The next S/G for this transfer */
406 	uint8_t	 scsi_status;		/* Standard SCSI status byte */
407 };
408 
409 struct target_status {
410 	uint32_t residual_datacnt;	/* Residual in the current S/G seg */
411 	uint32_t residual_sgptr;	/* The next S/G for this transfer */
412 	uint8_t  scsi_status;		/* SCSI status to give to initiator */
413 	uint8_t  target_phases;		/* Bitmap of phases to execute */
414 	uint8_t  data_phase;		/* Data-In or Data-Out */
415 	uint8_t  initiator_tag;		/* Initiator's transaction tag */
416 };
417 
418 /*
419  * Initiator mode SCB shared data area.
420  * If the embedded CDB is 12 bytes or less, we embed
421  * the sense buffer address in the SCB.  This allows
422  * us to retrieve sense information without interrupting
423  * the host in packetized mode.
424  */
425 typedef uint32_t sense_addr_t;
426 #define MAX_CDB_LEN 16
427 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
428 union initiator_data {
429 	struct {
430 		uint64_t cdbptr;
431 		uint8_t  cdblen;
432 	} cdb_from_host;
433 	uint8_t	 cdb[MAX_CDB_LEN];
434 	struct {
435 		uint8_t	 cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
436 		sense_addr_t sense_addr;
437 	} cdb_plus_saddr;
438 };
439 
440 /*
441  * Target mode version of the shared data SCB segment.
442  */
443 struct target_data {
444 	uint32_t spare[2];
445 	uint8_t  scsi_status;		/* SCSI status to give to initiator */
446 	uint8_t  target_phases;		/* Bitmap of phases to execute */
447 	uint8_t  data_phase;		/* Data-In or Data-Out */
448 	uint8_t  initiator_tag;		/* Initiator's transaction tag */
449 };
450 
451 struct hardware_scb {
452 /*0*/	union {
453 		union	initiator_data idata;
454 		struct	target_data tdata;
455 		struct	initiator_status istatus;
456 		struct	target_status tstatus;
457 	} shared_data;
458 /*
459  * A word about residuals.
460  * The scb is presented to the sequencer with the dataptr and datacnt
461  * fields initialized to the contents of the first S/G element to
462  * transfer.  The sgptr field is initialized to the bus address for
463  * the S/G element that follows the first in the in core S/G array
464  * or'ed with the SG_FULL_RESID flag.  Sgptr may point to an invalid
465  * S/G entry for this transfer (single S/G element transfer with the
466  * first elements address and length preloaded in the dataptr/datacnt
467  * fields).  If no transfer is to occur, sgptr is set to SG_LIST_NULL.
468  * The SG_FULL_RESID flag ensures that the residual will be correctly
469  * noted even if no data transfers occur.  Once the data phase is entered,
470  * the residual sgptr and datacnt are loaded from the sgptr and the
471  * datacnt fields.  After each S/G element's dataptr and length are
472  * loaded into the hardware, the residual sgptr is advanced.  After
473  * each S/G element is expired, its datacnt field is checked to see
474  * if the LAST_SEG flag is set.  If so, SG_LIST_NULL is set in the
475  * residual sg ptr and the transfer is considered complete.  If the
476  * sequencer determines that there is a residual in the tranfer, or
477  * there is non-zero status, it will set the SG_STATUS_VALID flag in
478  * sgptr and dma the scb back into host memory.  To sumarize:
479  *
480  * Sequencer:
481  *	o A residual has occurred if SG_FULL_RESID is set in sgptr,
482  *	  or residual_sgptr does not have SG_LIST_NULL set.
483  *
484  *	o We are transfering the last segment if residual_datacnt has
485  *	  the SG_LAST_SEG flag set.
486  *
487  * Host:
488  *	o A residual can only have occurred if a completed scb has the
489  *	  SG_STATUS_VALID flag set.  Inspection of the SCSI status field,
490  *	  the residual_datacnt, and the residual_sgptr field will tell
491  *	  for sure.
492  *
493  *	o residual_sgptr and sgptr refer to the "next" sg entry
494  *	  and so may point beyond the last valid sg entry for the
495  *	  transfer.
496  */
497 #define SG_PTR_MASK	0xFFFFFFF8
498 /*16*/	uint16_t tag;		/* Reused by Sequencer. */
499 /*18*/	uint8_t  control;	/* See SCB_CONTROL in aic79xx.reg for details */
500 /*19*/	uint8_t	 scsiid;	/*
501 				 * Selection out Id
502 				 * Our Id (bits 0-3) Their ID (bits 4-7)
503 				 */
504 /*20*/	uint8_t  lun;
505 /*21*/	uint8_t  task_attribute;
506 /*22*/	uint8_t  cdb_len;
507 /*23*/	uint8_t  task_management;
508 /*24*/	uint64_t dataptr;
509 /*32*/	uint32_t datacnt;	/* Byte 3 is spare. */
510 /*36*/	uint32_t sgptr;
511 /*40*/	uint32_t hscb_busaddr;
512 /*44*/	uint32_t next_hscb_busaddr;
513 /********** Long lun field only downloaded for full 8 byte lun support ********/
514 /*48*/  uint8_t	 pkt_long_lun[8];
515 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
516 /*56*/  uint8_t	 spare[8];
517 };
518 
519 /************************ Kernel SCB Definitions ******************************/
520 /*
521  * Some fields of the SCB are OS dependent.  Here we collect the
522  * definitions for elements that all OS platforms need to include
523  * in there SCB definition.
524  */
525 
526 /*
527  * Definition of a scatter/gather element as transfered to the controller.
528  * The aic7xxx chips only support a 24bit length.  We use the top byte of
529  * the length to store additional address bits and a flag to indicate
530  * that a given segment terminates the transfer.  This gives us an
531  * addressable range of 512GB on machines with 64bit PCI or with chips
532  * that can support dual address cycles on 32bit PCI busses.
533  */
534 struct ahd_dma_seg {
535 	uint32_t	addr;
536 	uint32_t	len;
537 #define	AHD_DMA_LAST_SEG	0x80000000
538 #define	AHD_SG_HIGH_ADDR_MASK	0x7F000000
539 #define	AHD_SG_LEN_MASK		0x00FFFFFF
540 };
541 
542 struct ahd_dma64_seg {
543 	uint64_t	addr;
544 	uint32_t	len;
545 	uint32_t	pad;
546 };
547 
548 struct map_node {
549 	bus_dmamap_t		 dmamap;
550 	dma_addr_t		 physaddr;
551 	uint8_t			*vaddr;
552 	SLIST_ENTRY(map_node)	 links;
553 };
554 
555 /*
556  * The current state of this SCB.
557  */
558 typedef enum {
559 	SCB_FLAG_NONE		= 0x00000,
560 	SCB_TRANSMISSION_ERROR	= 0x00001,/*
561 					   * We detected a parity or CRC
562 					   * error that has effected the
563 					   * payload of the command.  This
564 					   * flag is checked when normal
565 					   * status is returned to catch
566 					   * the case of a target not
567 					   * responding to our attempt
568 					   * to report the error.
569 					   */
570 	SCB_OTHERTCL_TIMEOUT	= 0x00002,/*
571 					   * Another device was active
572 					   * during the first timeout for
573 					   * this SCB so we gave ourselves
574 					   * an additional timeout period
575 					   * in case it was hogging the
576 					   * bus.
577 				           */
578 	SCB_DEVICE_RESET	= 0x00004,
579 	SCB_SENSE		= 0x00008,
580 	SCB_CDB32_PTR		= 0x00010,
581 	SCB_RECOVERY_SCB	= 0x00020,
582 	SCB_AUTO_NEGOTIATE	= 0x00040,/* Negotiate to achieve goal. */
583 	SCB_NEGOTIATE		= 0x00080,/* Negotiation forced for command. */
584 	SCB_ABORT		= 0x00100,
585 	SCB_ACTIVE		= 0x00200,
586 	SCB_TARGET_IMMEDIATE	= 0x00400,
587 	SCB_PACKETIZED		= 0x00800,
588 	SCB_EXPECT_PPR_BUSFREE	= 0x01000,
589 	SCB_PKT_SENSE		= 0x02000,
590 	SCB_EXTERNAL_RESET	= 0x04000,/* Device was reset externally */
591 	SCB_ON_COL_LIST		= 0x08000,
592 	SCB_SILENT		= 0x10000 /*
593 					   * Be quiet about transmission type
594 					   * errors.  They are expected and we
595 					   * don't want to upset the user.  This
596 					   * flag is typically used during DV.
597 					   */
598 } scb_flag;
599 
600 struct scb {
601 	struct	hardware_scb	 *hscb;
602 	union {
603 		SLIST_ENTRY(scb)  sle;
604 		LIST_ENTRY(scb)	  le;
605 		TAILQ_ENTRY(scb)  tqe;
606 	} links;
607 	union {
608 		SLIST_ENTRY(scb)  sle;
609 		LIST_ENTRY(scb)	  le;
610 		TAILQ_ENTRY(scb)  tqe;
611 	} links2;
612 #define pending_links links2.le
613 #define collision_links links2.le
614 	struct scb		 *col_scb;
615 	ahd_io_ctx_t		  io_ctx;
616 	struct ahd_softc	 *ahd_softc;
617 	scb_flag		  flags;
618 #ifndef __linux__
619 	bus_dmamap_t		  dmamap;
620 #endif
621 	struct scb_platform_data *platform_data;
622 	struct map_node	 	 *hscb_map;
623 	struct map_node	 	 *sg_map;
624 	struct map_node	 	 *sense_map;
625 	void			 *sg_list;
626 	uint8_t			 *sense_data;
627 	dma_addr_t		  sg_list_busaddr;
628 	dma_addr_t		  sense_busaddr;
629 	u_int			  sg_count;/* How full ahd_dma_seg is */
630 #define	AHD_MAX_LQ_CRC_ERRORS 5
631 	u_int			  crc_retry_count;
632 };
633 
634 TAILQ_HEAD(scb_tailq, scb);
635 LIST_HEAD(scb_list, scb);
636 
637 struct scb_data {
638 	/*
639 	 * TAILQ of lists of free SCBs grouped by device
640 	 * collision domains.
641 	 */
642 	struct scb_tailq free_scbs;
643 
644 	/*
645 	 * Per-device lists of SCBs whose tag ID would collide
646 	 * with an already active tag on the device.
647 	 */
648 	struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
649 
650 	/*
651 	 * SCBs that will not collide with any active device.
652 	 */
653 	struct scb_list any_dev_free_scb_list;
654 
655 	/*
656 	 * Mapping from tag to SCB.
657 	 */
658 	struct	scb *scbindex[AHD_SCB_MAX];
659 
660 	/*
661 	 * "Bus" addresses of our data structures.
662 	 */
663 	bus_dma_tag_t	 hscb_dmat;	/* dmat for our hardware SCB array */
664 	bus_dma_tag_t	 sg_dmat;	/* dmat for our sg segments */
665 	bus_dma_tag_t	 sense_dmat;	/* dmat for our sense buffers */
666 	SLIST_HEAD(, map_node) hscb_maps;
667 	SLIST_HEAD(, map_node) sg_maps;
668 	SLIST_HEAD(, map_node) sense_maps;
669 	int		 scbs_left;	/* unallocated scbs in head map_node */
670 	int		 sgs_left;	/* unallocated sgs in head map_node */
671 	int		 sense_left;	/* unallocated sense in head map_node */
672 	uint16_t	 numscbs;
673 	uint16_t	 maxhscbs;	/* Number of SCBs on the card */
674 	uint8_t		 init_level;	/*
675 					 * How far we've initialized
676 					 * this structure.
677 					 */
678 };
679 
680 /************************ Target Mode Definitions *****************************/
681 
682 /*
683  * Connection desciptor for select-in requests in target mode.
684  */
685 struct target_cmd {
686 	uint8_t scsiid;		/* Our ID and the initiator's ID */
687 	uint8_t identify;	/* Identify message */
688 	uint8_t bytes[22];	/*
689 				 * Bytes contains any additional message
690 				 * bytes terminated by 0xFF.  The remainder
691 				 * is the cdb to execute.
692 				 */
693 	uint8_t cmd_valid;	/*
694 				 * When a command is complete, the firmware
695 				 * will set cmd_valid to all bits set.
696 				 * After the host has seen the command,
697 				 * the bits are cleared.  This allows us
698 				 * to just peek at host memory to determine
699 				 * if more work is complete. cmd_valid is on
700 				 * an 8 byte boundary to simplify setting
701 				 * it on aic7880 hardware which only has
702 				 * limited direct access to the DMA FIFO.
703 				 */
704 	uint8_t pad[7];
705 };
706 
707 /*
708  * Number of events we can buffer up if we run out
709  * of immediate notify ccbs.
710  */
711 #define AHD_TMODE_EVENT_BUFFER_SIZE 8
712 struct ahd_tmode_event {
713 	uint8_t initiator_id;
714 	uint8_t event_type;	/* MSG type or EVENT_TYPE_BUS_RESET */
715 #define	EVENT_TYPE_BUS_RESET 0xFF
716 	uint8_t event_arg;
717 };
718 
719 /*
720  * Per enabled lun target mode state.
721  * As this state is directly influenced by the host OS'es target mode
722  * environment, we let the OS module define it.  Forward declare the
723  * structure here so we can store arrays of them, etc. in OS neutral
724  * data structures.
725  */
726 #ifdef AHD_TARGET_MODE
727 struct ahd_tmode_lstate {
728 	struct cam_path *path;
729 	struct ccb_hdr_slist accept_tios;
730 	struct ccb_hdr_slist immed_notifies;
731 	struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
732 	uint8_t event_r_idx;
733 	uint8_t event_w_idx;
734 };
735 #else
736 struct ahd_tmode_lstate;
737 #endif
738 
739 /******************** Transfer Negotiation Datastructures *********************/
740 #define AHD_TRANS_CUR		0x01	/* Modify current neogtiation status */
741 #define AHD_TRANS_ACTIVE	0x03	/* Assume this target is on the bus */
742 #define AHD_TRANS_GOAL		0x04	/* Modify negotiation goal */
743 #define AHD_TRANS_USER		0x08	/* Modify user negotiation settings */
744 #define AHD_PERIOD_10MHz	0x19
745 
746 #define AHD_WIDTH_UNKNOWN	0xFF
747 #define AHD_PERIOD_UNKNOWN	0xFF
748 #define AHD_OFFSET_UNKNOWN	0xFF
749 #define AHD_PPR_OPTS_UNKNOWN	0xFF
750 
751 /*
752  * Transfer Negotiation Information.
753  */
754 struct ahd_transinfo {
755 	uint8_t protocol_version;	/* SCSI Revision level */
756 	uint8_t transport_version;	/* SPI Revision level */
757 	uint8_t width;			/* Bus width */
758 	uint8_t period;			/* Sync rate factor */
759 	uint8_t offset;			/* Sync offset */
760 	uint8_t ppr_options;		/* Parallel Protocol Request options */
761 };
762 
763 /*
764  * Per-initiator current, goal and user transfer negotiation information. */
765 struct ahd_initiator_tinfo {
766 	struct ahd_transinfo curr;
767 	struct ahd_transinfo goal;
768 	struct ahd_transinfo user;
769 };
770 
771 /*
772  * Per enabled target ID state.
773  * Pointers to lun target state as well as sync/wide negotiation information
774  * for each initiator<->target mapping.  For the initiator role we pretend
775  * that we are the target and the targets are the initiators since the
776  * negotiation is the same regardless of role.
777  */
778 struct ahd_tmode_tstate {
779 	struct ahd_tmode_lstate*	enabled_luns[AHD_NUM_LUNS];
780 	struct ahd_initiator_tinfo	transinfo[AHD_NUM_TARGETS];
781 
782 	/*
783 	 * Per initiator state bitmasks.
784 	 */
785 	uint16_t	 auto_negotiate;/* Auto Negotiation Required */
786 	uint16_t	 discenable;	/* Disconnection allowed  */
787 	uint16_t	 tagenable;	/* Tagged Queuing allowed */
788 };
789 
790 /*
791  * Points of interest along the negotiated transfer scale.
792  */
793 #define AHD_SYNCRATE_160	0x8
794 #define AHD_SYNCRATE_PACED	0x8
795 #define AHD_SYNCRATE_DT		0x9
796 #define AHD_SYNCRATE_ULTRA2	0xa
797 #define AHD_SYNCRATE_ULTRA	0xc
798 #define AHD_SYNCRATE_FAST	0x19
799 #define AHD_SYNCRATE_MIN_DT	AHD_SYNCRATE_FAST
800 #define AHD_SYNCRATE_SYNC	0x32
801 #define AHD_SYNCRATE_MIN	0x60
802 #define	AHD_SYNCRATE_ASYNC	0xFF
803 #define AHD_SYNCRATE_MAX	AHD_SYNCRATE_160
804 
805 /* Safe and valid period for async negotiations. */
806 #define	AHD_ASYNC_XFER_PERIOD	0x44
807 
808 /*
809  * In RevA, the synctable uses a 120MHz rate for the period
810  * factor 8 and 160MHz for the period factor 7.  The 120MHz
811  * rate never made it into the official SCSI spec, so we must
812  * compensate when setting the negotiation table for Rev A
813  * parts.
814  */
815 #define AHD_SYNCRATE_REVA_120	0x8
816 #define AHD_SYNCRATE_REVA_160	0x7
817 
818 /***************************** Lookup Tables **********************************/
819 /*
820  * Phase -> name and message out response
821  * to parity errors in each phase table.
822  */
823 struct ahd_phase_table_entry {
824         uint8_t phase;
825         uint8_t mesg_out; /* Message response to parity errors */
826 	char *phasemsg;
827 };
828 
829 /************************** Serial EEPROM Format ******************************/
830 
831 struct seeprom_config {
832 /*
833  * Per SCSI ID Configuration Flags
834  */
835 	uint16_t device_flags[16];	/* words 0-15 */
836 #define		CFXFER		0x003F	/* synchronous transfer rate */
837 #define			CFXFER_ASYNC	0x3F
838 #define		CFQAS		0x0040	/* Negotiate QAS */
839 #define		CFPACKETIZED	0x0080	/* Negotiate Packetized Transfers */
840 #define		CFSTART		0x0100	/* send start unit SCSI command */
841 #define		CFINCBIOS	0x0200	/* include in BIOS scan */
842 #define		CFDISC		0x0400	/* enable disconnection */
843 #define		CFMULTILUNDEV	0x0800	/* Probe multiple luns in BIOS scan */
844 #define		CFWIDEB		0x1000	/* wide bus device */
845 #define		CFHOSTMANAGED	0x8000	/* Managed by a RAID controller */
846 
847 /*
848  * BIOS Control Bits
849  */
850 	uint16_t bios_control;		/* word 16 */
851 #define		CFSUPREM	0x0001	/* support all removeable drives */
852 #define		CFSUPREMB	0x0002	/* support removeable boot drives */
853 #define		CFBIOSSTATE	0x000C	/* BIOS Action State */
854 #define		    CFBS_DISABLED	0x00
855 #define		    CFBS_ENABLED	0x04
856 #define		    CFBS_DISABLED_SCAN	0x08
857 #define		CFENABLEDV	0x0010	/* Perform Domain Validation */
858 #define		CFCTRL_A	0x0020	/* BIOS displays Ctrl-A message */
859 #define		CFSPARITY	0x0040	/* SCSI parity */
860 #define		CFEXTEND	0x0080	/* extended translation enabled */
861 #define		CFBOOTCD	0x0100  /* Support Bootable CD-ROM */
862 #define		CFMSG_LEVEL	0x0600	/* BIOS Message Level */
863 #define			CFMSG_VERBOSE	0x0000
864 #define			CFMSG_SILENT	0x0200
865 #define			CFMSG_DIAG	0x0400
866 #define		CFRESETB	0x0800	/* reset SCSI bus at boot */
867 /*		UNUSED		0xf000	*/
868 
869 /*
870  * Host Adapter Control Bits
871  */
872 	uint16_t adapter_control;	/* word 17 */
873 #define		CFAUTOTERM	0x0001	/* Perform Auto termination */
874 #define		CFSTERM		0x0002	/* SCSI low byte termination */
875 #define		CFWSTERM	0x0004	/* SCSI high byte termination */
876 #define		CFSEAUTOTERM	0x0008	/* Ultra2 Perform secondary Auto Term*/
877 #define		CFSELOWTERM	0x0010	/* Ultra2 secondary low term */
878 #define		CFSEHIGHTERM	0x0020	/* Ultra2 secondary high term */
879 #define		CFSTPWLEVEL	0x0040	/* Termination level control */
880 #define		CFBIOSAUTOTERM	0x0080	/* Perform Auto termination */
881 #define		CFTERM_MENU	0x0100	/* BIOS displays termination menu */
882 #define		CFCLUSTERENB	0x8000	/* Cluster Enable */
883 
884 /*
885  * Bus Release Time, Host Adapter ID
886  */
887 	uint16_t brtime_id;		/* word 18 */
888 #define		CFSCSIID	0x000f	/* host adapter SCSI ID */
889 /*		UNUSED		0x00f0	*/
890 #define		CFBRTIME	0xff00	/* bus release time/PCI Latency Time */
891 
892 /*
893  * Maximum targets
894  */
895 	uint16_t max_targets;		/* word 19 */
896 #define		CFMAXTARG	0x00ff	/* maximum targets */
897 #define		CFBOOTLUN	0x0f00	/* Lun to boot from */
898 #define		CFBOOTID	0xf000	/* Target to boot from */
899 	uint16_t res_1[10];		/* words 20-29 */
900 	uint16_t signature;		/* BIOS Signature */
901 #define		CFSIGNATURE	0x400
902 	uint16_t checksum;		/* word 31 */
903 };
904 
905 /*
906  * Vital Product Data used during POST and by the BIOS.
907  */
908 struct vpd_config {
909 	uint8_t  bios_flags;
910 #define		VPDMASTERBIOS	0x0001
911 #define		VPDBOOTHOST	0x0002
912 	uint8_t  reserved_1[21];
913 	uint8_t  resource_type;
914 	uint8_t  resource_len[2];
915 	uint8_t  resource_data[8];
916 	uint8_t  vpd_tag;
917 	uint16_t vpd_len;
918 	uint8_t  vpd_keyword[2];
919 	uint8_t  length;
920 	uint8_t  revision;
921 	uint8_t  device_flags;
922 	uint8_t  termnation_menus[2];
923 	uint8_t  fifo_threshold;
924 	uint8_t  end_tag;
925 	uint8_t  vpd_checksum;
926 	uint16_t default_target_flags;
927 	uint16_t default_bios_flags;
928 	uint16_t default_ctrl_flags;
929 	uint8_t  default_irq;
930 	uint8_t  pci_lattime;
931 	uint8_t  max_target;
932 	uint8_t  boot_lun;
933 	uint16_t signature;
934 	uint8_t  reserved_2;
935 	uint8_t  checksum;
936 	uint8_t	 reserved_3[4];
937 };
938 
939 /****************************** Flexport Logic ********************************/
940 #define FLXADDR_TERMCTL			0x0
941 #define		FLX_TERMCTL_ENSECHIGH	0x8
942 #define		FLX_TERMCTL_ENSECLOW	0x4
943 #define		FLX_TERMCTL_ENPRIHIGH	0x2
944 #define		FLX_TERMCTL_ENPRILOW	0x1
945 #define FLXADDR_ROMSTAT_CURSENSECTL	0x1
946 #define		FLX_ROMSTAT_SEECFG	0xF0
947 #define		FLX_ROMSTAT_EECFG	0x0F
948 #define		FLX_ROMSTAT_SEE_93C66	0x00
949 #define		FLX_ROMSTAT_SEE_NONE	0xF0
950 #define		FLX_ROMSTAT_EE_512x8	0x0
951 #define		FLX_ROMSTAT_EE_1MBx8	0x1
952 #define		FLX_ROMSTAT_EE_2MBx8	0x2
953 #define		FLX_ROMSTAT_EE_4MBx8	0x3
954 #define		FLX_ROMSTAT_EE_16MBx8	0x4
955 #define 		CURSENSE_ENB	0x1
956 #define	FLXADDR_FLEXSTAT		0x2
957 #define		FLX_FSTAT_BUSY		0x1
958 #define FLXADDR_CURRENT_STAT		0x4
959 #define		FLX_CSTAT_SEC_HIGH	0xC0
960 #define		FLX_CSTAT_SEC_LOW	0x30
961 #define		FLX_CSTAT_PRI_HIGH	0x0C
962 #define		FLX_CSTAT_PRI_LOW	0x03
963 #define		FLX_CSTAT_MASK		0x03
964 #define		FLX_CSTAT_SHIFT		2
965 #define		FLX_CSTAT_OKAY		0x0
966 #define		FLX_CSTAT_OVER		0x1
967 #define		FLX_CSTAT_UNDER		0x2
968 #define		FLX_CSTAT_INVALID	0x3
969 
970 int		ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
971 				 u_int start_addr, u_int count, int bstream);
972 
973 int		ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
974 				  u_int start_addr, u_int count);
975 int		ahd_wait_seeprom(struct ahd_softc *ahd);
976 int		ahd_verify_vpd_cksum(struct vpd_config *vpd);
977 int		ahd_verify_cksum(struct seeprom_config *sc);
978 int		ahd_acquire_seeprom(struct ahd_softc *ahd);
979 void		ahd_release_seeprom(struct ahd_softc *ahd);
980 
981 /****************************  Message Buffer *********************************/
982 typedef enum {
983 	MSG_FLAG_NONE			= 0x00,
984 	MSG_FLAG_EXPECT_PPR_BUSFREE	= 0x01,
985 	MSG_FLAG_IU_REQ_CHANGED		= 0x02,
986 	MSG_FLAG_EXPECT_IDE_BUSFREE	= 0x04,
987 	MSG_FLAG_EXPECT_QASREJ_BUSFREE	= 0x08,
988 	MSG_FLAG_PACKETIZED		= 0x10
989 } ahd_msg_flags;
990 
991 typedef enum {
992 	MSG_TYPE_NONE			= 0x00,
993 	MSG_TYPE_INITIATOR_MSGOUT	= 0x01,
994 	MSG_TYPE_INITIATOR_MSGIN	= 0x02,
995 	MSG_TYPE_TARGET_MSGOUT		= 0x03,
996 	MSG_TYPE_TARGET_MSGIN		= 0x04
997 } ahd_msg_type;
998 
999 typedef enum {
1000 	MSGLOOP_IN_PROG,
1001 	MSGLOOP_MSGCOMPLETE,
1002 	MSGLOOP_TERMINATED
1003 } msg_loop_stat;
1004 
1005 /*********************** Software Configuration Structure *********************/
1006 struct ahd_suspend_channel_state {
1007 	uint8_t	scsiseq;
1008 	uint8_t	sxfrctl0;
1009 	uint8_t	sxfrctl1;
1010 	uint8_t	simode0;
1011 	uint8_t	simode1;
1012 	uint8_t	seltimer;
1013 	uint8_t	seqctl;
1014 };
1015 
1016 struct ahd_suspend_state {
1017 	struct	ahd_suspend_channel_state channel[2];
1018 	uint8_t	optionmode;
1019 	uint8_t	dscommand0;
1020 	uint8_t	dspcistatus;
1021 	/* hsmailbox */
1022 	uint8_t	crccontrol1;
1023 	uint8_t	scbbaddr;
1024 	/* Host and sequencer SCB counts */
1025 	uint8_t	dff_thrsh;
1026 	uint8_t	*scratch_ram;
1027 	uint8_t	*btt;
1028 };
1029 
1030 typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
1031 
1032 typedef enum {
1033 	AHD_MODE_DFF0,
1034 	AHD_MODE_DFF1,
1035 	AHD_MODE_CCHAN,
1036 	AHD_MODE_SCSI,
1037 	AHD_MODE_CFG,
1038 	AHD_MODE_UNKNOWN
1039 } ahd_mode;
1040 
1041 #define AHD_MK_MSK(x) (0x01 << (x))
1042 #define AHD_MODE_DFF0_MSK	AHD_MK_MSK(AHD_MODE_DFF0)
1043 #define AHD_MODE_DFF1_MSK	AHD_MK_MSK(AHD_MODE_DFF1)
1044 #define AHD_MODE_CCHAN_MSK	AHD_MK_MSK(AHD_MODE_CCHAN)
1045 #define AHD_MODE_SCSI_MSK	AHD_MK_MSK(AHD_MODE_SCSI)
1046 #define AHD_MODE_CFG_MSK	AHD_MK_MSK(AHD_MODE_CFG)
1047 #define AHD_MODE_UNKNOWN_MSK	AHD_MK_MSK(AHD_MODE_UNKNOWN)
1048 #define AHD_MODE_ANY_MSK (~0)
1049 
1050 typedef uint8_t ahd_mode_state;
1051 
1052 typedef void ahd_callback_t (void *);
1053 
1054 struct ahd_completion
1055 {
1056 	uint16_t	tag;
1057 	uint8_t		sg_status;
1058 	uint8_t		valid_tag;
1059 };
1060 
1061 struct ahd_softc {
1062 	bus_space_tag_t           tags[2];
1063 	bus_space_handle_t        bshs[2];
1064 #ifndef __linux__
1065 	bus_dma_tag_t		  buffer_dmat;   /* dmat for buffer I/O */
1066 #endif
1067 	struct scb_data		  scb_data;
1068 
1069 	struct hardware_scb	 *next_queued_hscb;
1070 	struct map_node		 *next_queued_hscb_map;
1071 
1072 	/*
1073 	 * SCBs that have been sent to the controller
1074 	 */
1075 	LIST_HEAD(, scb)	  pending_scbs;
1076 
1077 	/*
1078 	 * Current register window mode information.
1079 	 */
1080 	ahd_mode		  dst_mode;
1081 	ahd_mode		  src_mode;
1082 
1083 	/*
1084 	 * Saved register window mode information
1085 	 * used for restore on next unpause.
1086 	 */
1087 	ahd_mode		  saved_dst_mode;
1088 	ahd_mode		  saved_src_mode;
1089 
1090 	/*
1091 	 * Platform specific data.
1092 	 */
1093 	struct ahd_platform_data *platform_data;
1094 
1095 	/*
1096 	 * Platform specific device information.
1097 	 */
1098 	ahd_dev_softc_t		  dev_softc;
1099 
1100 	/*
1101 	 * Bus specific device information.
1102 	 */
1103 	ahd_bus_intr_t		  bus_intr;
1104 
1105 	/*
1106 	 * Target mode related state kept on a per enabled lun basis.
1107 	 * Targets that are not enabled will have null entries.
1108 	 * As an initiator, we keep one target entry for our initiator
1109 	 * ID to store our sync/wide transfer settings.
1110 	 */
1111 	struct ahd_tmode_tstate  *enabled_targets[AHD_NUM_TARGETS];
1112 
1113 	/*
1114 	 * The black hole device responsible for handling requests for
1115 	 * disabled luns on enabled targets.
1116 	 */
1117 	struct ahd_tmode_lstate  *black_hole;
1118 
1119 	/*
1120 	 * Device instance currently on the bus awaiting a continue TIO
1121 	 * for a command that was not given the disconnect priveledge.
1122 	 */
1123 	struct ahd_tmode_lstate  *pending_device;
1124 
1125 	/*
1126 	 * Timer handles for timer driven callbacks.
1127 	 */
1128 	ahd_timer_t		  reset_timer;
1129 	ahd_timer_t		  stat_timer;
1130 
1131 	/*
1132 	 * Statistics.
1133 	 */
1134 #define	AHD_STAT_UPDATE_US	250000 /* 250ms */
1135 #define	AHD_STAT_BUCKETS	4
1136 	u_int			  cmdcmplt_bucket;
1137 	uint32_t		  cmdcmplt_counts[AHD_STAT_BUCKETS];
1138 	uint32_t		  cmdcmplt_total;
1139 
1140 	/*
1141 	 * Card characteristics
1142 	 */
1143 	ahd_chip		  chip;
1144 	ahd_feature		  features;
1145 	ahd_bug			  bugs;
1146 	ahd_flag		  flags;
1147 	struct seeprom_config	 *seep_config;
1148 
1149 	/* Command Queues */
1150 	struct ahd_completion	  *qoutfifo;
1151 	uint16_t		  qoutfifonext;
1152 	uint16_t		  qoutfifonext_valid_tag;
1153 	uint16_t		  qinfifonext;
1154 	uint16_t		  qinfifo[AHD_SCB_MAX];
1155 
1156 	/*
1157 	 * Our qfreeze count.  The sequencer compares
1158 	 * this value with its own counter to determine
1159 	 * whether to allow selections to occur.
1160 	 */
1161 	uint16_t		  qfreeze_cnt;
1162 
1163 	/* Values to store in the SEQCTL register for pause and unpause */
1164 	uint8_t			  unpause;
1165 	uint8_t			  pause;
1166 
1167 	/* Critical Section Data */
1168 	struct cs		 *critical_sections;
1169 	u_int			  num_critical_sections;
1170 
1171 	/* Buffer for handling packetized bitbucket. */
1172 	uint8_t			 *overrun_buf;
1173 
1174 	/* Links for chaining softcs */
1175 	TAILQ_ENTRY(ahd_softc)	  links;
1176 
1177 	/* Channel Names ('A', 'B', etc.) */
1178 	char			  channel;
1179 
1180 	/* Initiator Bus ID */
1181 	uint8_t			  our_id;
1182 
1183 	/*
1184 	 * Target incoming command FIFO.
1185 	 */
1186 	struct target_cmd	 *targetcmds;
1187 	uint8_t			  tqinfifonext;
1188 
1189 	/*
1190 	 * Cached verson of the hs_mailbox so we can avoid
1191 	 * pausing the sequencer during mailbox updates.
1192 	 */
1193 	uint8_t			  hs_mailbox;
1194 
1195 	/*
1196 	 * Incoming and outgoing message handling.
1197 	 */
1198 	uint8_t			  send_msg_perror;
1199 	ahd_msg_flags		  msg_flags;
1200 	ahd_msg_type		  msg_type;
1201 	uint8_t			  msgout_buf[12];/* Message we are sending */
1202 	uint8_t			  msgin_buf[12];/* Message we are receiving */
1203 	u_int			  msgout_len;	/* Length of message to send */
1204 	u_int			  msgout_index;	/* Current index in msgout */
1205 	u_int			  msgin_index;	/* Current index in msgin */
1206 
1207 	/*
1208 	 * Mapping information for data structures shared
1209 	 * between the sequencer and kernel.
1210 	 */
1211 	bus_dma_tag_t		  parent_dmat;
1212 	bus_dma_tag_t		  shared_data_dmat;
1213 	struct map_node		  shared_data_map;
1214 
1215 	/* Information saved through suspend/resume cycles */
1216 	struct ahd_suspend_state  suspend_state;
1217 
1218 	/* Number of enabled target mode device on this card */
1219 	u_int			  enabled_luns;
1220 
1221 	/* Initialization level of this data structure */
1222 	u_int			  init_level;
1223 
1224 	/* PCI cacheline size. */
1225 	u_int			  pci_cachesize;
1226 
1227 	/* IO Cell Parameters */
1228 	uint8_t			  iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1229 
1230 	u_int			  stack_size;
1231 	uint16_t		 *saved_stack;
1232 
1233 	/* Per-Unit descriptive information */
1234 	const char		 *description;
1235 	const char		 *bus_description;
1236 	char			 *name;
1237 	int			  unit;
1238 
1239 	/* Selection Timer settings */
1240 	int			  seltime;
1241 
1242 	/*
1243 	 * Interrupt coalescing settings.
1244 	 */
1245 #define	AHD_INT_COALESCING_TIMER_DEFAULT		250 /*us*/
1246 #define	AHD_INT_COALESCING_MAXCMDS_DEFAULT		10
1247 #define	AHD_INT_COALESCING_MAXCMDS_MAX			127
1248 #define	AHD_INT_COALESCING_MINCMDS_DEFAULT		5
1249 #define	AHD_INT_COALESCING_MINCMDS_MAX			127
1250 #define	AHD_INT_COALESCING_THRESHOLD_DEFAULT		2000
1251 #define	AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT	1000
1252 	u_int			  int_coalescing_timer;
1253 	u_int			  int_coalescing_maxcmds;
1254 	u_int			  int_coalescing_mincmds;
1255 	u_int			  int_coalescing_threshold;
1256 	u_int			  int_coalescing_stop_threshold;
1257 
1258 	uint16_t	 	  user_discenable;/* Disconnection allowed  */
1259 	uint16_t		  user_tagenable;/* Tagged Queuing allowed */
1260 };
1261 
1262 /*************************** IO Cell Configuration ****************************/
1263 #define	AHD_PRECOMP_SLEW_INDEX						\
1264     (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1265 
1266 #define	AHD_AMPLITUDE_INDEX						\
1267     (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1268 
1269 #define AHD_SET_SLEWRATE(ahd, new_slew)					\
1270 do {									\
1271     (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK;	\
1272     (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |=			\
1273 	(((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK);	\
1274 } while (0)
1275 
1276 #define AHD_SET_PRECOMP(ahd, new_pcomp)					\
1277 do {									\
1278     (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;	\
1279     (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |=			\
1280 	(((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK);	\
1281 } while (0)
1282 
1283 #define AHD_SET_AMPLITUDE(ahd, new_amp)					\
1284 do {									\
1285     (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK;	\
1286     (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |=				\
1287 	(((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK);	\
1288 } while (0)
1289 
1290 /************************ Active Device Information ***************************/
1291 typedef enum {
1292 	ROLE_UNKNOWN,
1293 	ROLE_INITIATOR,
1294 	ROLE_TARGET
1295 } role_t;
1296 
1297 struct ahd_devinfo {
1298 	int	 our_scsiid;
1299 	int	 target_offset;
1300 	uint16_t target_mask;
1301 	u_int	 target;
1302 	u_int	 lun;
1303 	char	 channel;
1304 	role_t	 role;		/*
1305 				 * Only guaranteed to be correct if not
1306 				 * in the busfree state.
1307 				 */
1308 };
1309 
1310 /****************************** PCI Structures ********************************/
1311 #define AHD_PCI_IOADDR0	PCIR_BAR(0)	/* I/O BAR*/
1312 #define AHD_PCI_MEMADDR	PCIR_BAR(1)	/* Memory BAR */
1313 #define AHD_PCI_IOADDR1	PCIR_BAR(3)	/* Second I/O BAR */
1314 
1315 typedef int (ahd_device_setup_t)(struct ahd_softc *);
1316 
1317 struct ahd_pci_identity {
1318 	uint64_t		 full_id;
1319 	uint64_t		 id_mask;
1320 	char			*name;
1321 	ahd_device_setup_t	*setup;
1322 };
1323 extern struct ahd_pci_identity ahd_pci_ident_table [];
1324 extern const u_int ahd_num_pci_devs;
1325 
1326 /***************************** VL/EISA Declarations ***************************/
1327 struct aic7770_identity {
1328 	uint32_t		 full_id;
1329 	uint32_t		 id_mask;
1330 	char			*name;
1331 	ahd_device_setup_t	*setup;
1332 };
1333 extern struct aic7770_identity aic7770_ident_table [];
1334 extern const int ahd_num_aic7770_devs;
1335 
1336 #define AHD_EISA_SLOT_OFFSET	0xc00
1337 #define AHD_EISA_IOSIZE		0x100
1338 
1339 /*************************** Function Declarations ****************************/
1340 /******************************************************************************/
1341 void			ahd_reset_cmds_pending(struct ahd_softc *ahd);
1342 u_int			ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl);
1343 void			ahd_busy_tcl(struct ahd_softc *ahd,
1344 				     u_int tcl, u_int busyid);
1345 static __inline void	ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl);
1346 static __inline void
1347 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
1348 {
1349 	ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
1350 }
1351 
1352 /***************************** PCI Front End *********************************/
1353 struct	ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t);
1354 int			  ahd_pci_config(struct ahd_softc *,
1355 					 struct ahd_pci_identity *);
1356 int	ahd_pci_test_register_access(struct ahd_softc *);
1357 
1358 /************************** SCB and SCB queue management **********************/
1359 int		ahd_probe_scbs(struct ahd_softc *);
1360 void		ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
1361 					 struct scb *scb);
1362 int		ahd_match_scb(struct ahd_softc *ahd, struct scb *scb,
1363 			      int target, char channel, int lun,
1364 			      u_int tag, role_t role);
1365 
1366 /****************************** Initialization ********************************/
1367 struct ahd_softc	*ahd_alloc(void *platform_arg, char *name);
1368 int			 ahd_softc_init(struct ahd_softc *);
1369 void			 ahd_controller_info(struct ahd_softc *ahd, char *buf);
1370 int			 ahd_init(struct ahd_softc *ahd);
1371 int			 ahd_default_config(struct ahd_softc *ahd);
1372 int			 ahd_parse_vpddata(struct ahd_softc *ahd,
1373 					   struct vpd_config *vpd);
1374 int			 ahd_parse_cfgdata(struct ahd_softc *ahd,
1375 					   struct seeprom_config *sc);
1376 void			 ahd_intr_enable(struct ahd_softc *ahd, int enable);
1377 void			 ahd_update_coalescing_values(struct ahd_softc *ahd,
1378 						      u_int timer,
1379 						      u_int maxcmds,
1380 						      u_int mincmds);
1381 void			 ahd_enable_coalescing(struct ahd_softc *ahd,
1382 					       int enable);
1383 void			 ahd_pause_and_flushwork(struct ahd_softc *ahd);
1384 int			 ahd_suspend(struct ahd_softc *ahd);
1385 int			 ahd_resume(struct ahd_softc *ahd);
1386 void			 ahd_set_unit(struct ahd_softc *, int);
1387 void			 ahd_set_name(struct ahd_softc *, char *);
1388 struct scb		*ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
1389 void			 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
1390 void			 ahd_alloc_scbs(struct ahd_softc *ahd);
1391 void			 ahd_free(struct ahd_softc *ahd);
1392 int			 ahd_reset(struct ahd_softc *ahd, int reinit);
1393 void			 ahd_shutdown(void *arg);
1394 int			 ahd_write_flexport(struct ahd_softc *ahd,
1395 					    u_int addr, u_int value);
1396 int			 ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1397 					   uint8_t *value);
1398 int			 ahd_wait_flexport(struct ahd_softc *ahd);
1399 
1400 /*************************** Interrupt Services *******************************/
1401 void			ahd_pci_intr(struct ahd_softc *ahd);
1402 void			ahd_clear_intstat(struct ahd_softc *ahd);
1403 void			ahd_flush_qoutfifo(struct ahd_softc *ahd);
1404 void			ahd_run_qoutfifo(struct ahd_softc *ahd);
1405 #ifdef AHD_TARGET_MODE
1406 void			ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
1407 #endif
1408 void			ahd_handle_hwerrint(struct ahd_softc *ahd);
1409 void			ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
1410 void			ahd_handle_scsiint(struct ahd_softc *ahd,
1411 					   u_int intstat);
1412 void			ahd_clear_critical_section(struct ahd_softc *ahd);
1413 
1414 /***************************** Error Recovery *********************************/
1415 typedef enum {
1416 	SEARCH_COMPLETE,
1417 	SEARCH_COUNT,
1418 	SEARCH_REMOVE,
1419 	SEARCH_PRINT
1420 } ahd_search_action;
1421 int			ahd_search_qinfifo(struct ahd_softc *ahd, int target,
1422 					   char channel, int lun, u_int tag,
1423 					   role_t role, uint32_t status,
1424 					   ahd_search_action action);
1425 int			ahd_search_disc_list(struct ahd_softc *ahd, int target,
1426 					     char channel, int lun, u_int tag,
1427 					     int stop_on_first, int remove,
1428 					     int save_state);
1429 void			ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb);
1430 int			ahd_reset_channel(struct ahd_softc *ahd, char channel,
1431 					  int initiate_reset);
1432 int			ahd_abort_scbs(struct ahd_softc *ahd, int target,
1433 				       char channel, int lun, u_int tag,
1434 				       role_t role, uint32_t status);
1435 void			ahd_restart(struct ahd_softc *ahd);
1436 void			ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo);
1437 void			ahd_handle_scb_status(struct ahd_softc *ahd,
1438 					      struct scb *scb);
1439 void			ahd_handle_scsi_status(struct ahd_softc *ahd,
1440 					       struct scb *scb);
1441 void			ahd_calc_residual(struct ahd_softc *ahd,
1442 					  struct scb *scb);
1443 /*************************** Utility Functions ********************************/
1444 struct ahd_phase_table_entry*
1445 			ahd_lookup_phase_entry(int phase);
1446 void			ahd_compile_devinfo(struct ahd_devinfo *devinfo,
1447 					    u_int our_id, u_int target,
1448 					    u_int lun, char channel,
1449 					    role_t role);
1450 /************************** Transfer Negotiation ******************************/
1451 void			ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
1452 					  u_int *ppr_options, u_int maxsync);
1453 void			ahd_validate_offset(struct ahd_softc *ahd,
1454 					    struct ahd_initiator_tinfo *tinfo,
1455 					    u_int period, u_int *offset,
1456 					    int wide, role_t role);
1457 void			ahd_validate_width(struct ahd_softc *ahd,
1458 					   struct ahd_initiator_tinfo *tinfo,
1459 					   u_int *bus_width,
1460 					   role_t role);
1461 /*
1462  * Negotiation types.  These are used to qualify if we should renegotiate
1463  * even if our goal and current transport parameters are identical.
1464  */
1465 typedef enum {
1466 	AHD_NEG_TO_GOAL,	/* Renegotiate only if goal and curr differ. */
1467 	AHD_NEG_IF_NON_ASYNC,	/* Renegotiate so long as goal is non-async. */
1468 	AHD_NEG_ALWAYS		/* Renegotiat even if goal is async. */
1469 } ahd_neg_type;
1470 int			ahd_update_neg_request(struct ahd_softc*,
1471 					       struct ahd_devinfo*,
1472 					       struct ahd_tmode_tstate*,
1473 					       struct ahd_initiator_tinfo*,
1474 					       ahd_neg_type);
1475 void			ahd_set_width(struct ahd_softc *ahd,
1476 				      struct ahd_devinfo *devinfo,
1477 				      u_int width, u_int type, int paused);
1478 void			ahd_set_syncrate(struct ahd_softc *ahd,
1479 					 struct ahd_devinfo *devinfo,
1480 					 u_int period, u_int offset,
1481 					 u_int ppr_options,
1482 					 u_int type, int paused);
1483 typedef enum {
1484 	AHD_QUEUE_NONE,
1485 	AHD_QUEUE_BASIC,
1486 	AHD_QUEUE_TAGGED
1487 } ahd_queue_alg;
1488 
1489 void			ahd_set_tags(struct ahd_softc *ahd,
1490 				     struct scsi_cmnd *cmd,
1491 				     struct ahd_devinfo *devinfo,
1492 				     ahd_queue_alg alg);
1493 
1494 /**************************** Target Mode *************************************/
1495 #ifdef AHD_TARGET_MODE
1496 void		ahd_send_lstate_events(struct ahd_softc *,
1497 				       struct ahd_tmode_lstate *);
1498 void		ahd_handle_en_lun(struct ahd_softc *ahd,
1499 				  struct cam_sim *sim, union ccb *ccb);
1500 cam_status	ahd_find_tmode_devs(struct ahd_softc *ahd,
1501 				    struct cam_sim *sim, union ccb *ccb,
1502 				    struct ahd_tmode_tstate **tstate,
1503 				    struct ahd_tmode_lstate **lstate,
1504 				    int notfound_failure);
1505 #ifndef AHD_TMODE_ENABLE
1506 #define AHD_TMODE_ENABLE 0
1507 #endif
1508 #endif
1509 /******************************* Debug ***************************************/
1510 #ifdef AHD_DEBUG
1511 extern uint32_t ahd_debug;
1512 #define AHD_SHOW_MISC		0x00001
1513 #define AHD_SHOW_SENSE		0x00002
1514 #define AHD_SHOW_RECOVERY	0x00004
1515 #define AHD_DUMP_SEEPROM	0x00008
1516 #define AHD_SHOW_TERMCTL	0x00010
1517 #define AHD_SHOW_MEMORY		0x00020
1518 #define AHD_SHOW_MESSAGES	0x00040
1519 #define AHD_SHOW_MODEPTR	0x00080
1520 #define AHD_SHOW_SELTO		0x00100
1521 #define AHD_SHOW_FIFOS		0x00200
1522 #define AHD_SHOW_QFULL		0x00400
1523 #define	AHD_SHOW_DV		0x00800
1524 #define AHD_SHOW_MASKED_ERRORS	0x01000
1525 #define AHD_SHOW_QUEUE		0x02000
1526 #define AHD_SHOW_TQIN		0x04000
1527 #define AHD_SHOW_SG		0x08000
1528 #define AHD_SHOW_INT_COALESCING	0x10000
1529 #define AHD_DEBUG_SEQUENCER	0x20000
1530 #endif
1531 void			ahd_print_scb(struct scb *scb);
1532 void			ahd_print_devinfo(struct ahd_softc *ahd,
1533 					  struct ahd_devinfo *devinfo);
1534 void			ahd_dump_sglist(struct scb *scb);
1535 void			ahd_dump_card_state(struct ahd_softc *ahd);
1536 int			ahd_print_register(ahd_reg_parse_entry_t *table,
1537 					   u_int num_entries,
1538 					   const char *name,
1539 					   u_int address,
1540 					   u_int value,
1541 					   u_int *cur_column,
1542 					   u_int wrap_point);
1543 void			ahd_dump_scbs(struct ahd_softc *ahd);
1544 #endif /* _AIC79XX_H_ */
1545