1 /* -*- mode: c; c-basic-offset: 8 -*- */ 2 3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios 4 * 5 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com 6 */ 7 8 #ifndef _53C700_H 9 #define _53C700_H 10 11 #include <linux/interrupt.h> 12 #include <asm/io.h> 13 14 #include <scsi/scsi_device.h> 15 16 17 /* Turn on for general debugging---too verbose for normal use */ 18 #undef NCR_700_DEBUG 19 /* Debug the tag queues, checking hash queue allocation and deallocation 20 * and search for duplicate tags */ 21 #undef NCR_700_TAG_DEBUG 22 23 #ifdef NCR_700_DEBUG 24 #define DEBUG(x) printk x 25 #define DDEBUG(prefix, sdev, fmt, a...) \ 26 sdev_printk(prefix, sdev, fmt, ##a) 27 #define CDEBUG(prefix, scmd, fmt, a...) \ 28 scmd_printk(prefix, scmd, fmt, ##a) 29 #else 30 #define DEBUG(x) do {} while (0) 31 #define DDEBUG(prefix, scmd, fmt, a...) do {} while (0) 32 #define CDEBUG(prefix, scmd, fmt, a...) do {} while (0) 33 #endif 34 35 /* The number of available command slots */ 36 #define NCR_700_COMMAND_SLOTS_PER_HOST 64 37 /* The maximum number of Scatter Gathers we allow */ 38 #define NCR_700_SG_SEGMENTS 32 39 /* The maximum number of luns (make this of the form 2^n) */ 40 #define NCR_700_MAX_LUNS 32 41 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1) 42 /* Maximum number of tags the driver ever allows per device */ 43 #define NCR_700_MAX_TAGS 16 44 /* Tag depth the driver starts out with (can be altered in sysfs) */ 45 #define NCR_700_DEFAULT_TAGS 4 46 /* This is the default number of commands per LUN in the untagged case. 47 * two is a good value because it means we can have one command active and 48 * one command fully prepared and waiting 49 */ 50 #define NCR_700_CMD_PER_LUN 2 51 /* magic byte identifying an internally generated REQUEST_SENSE command */ 52 #define NCR_700_INTERNAL_SENSE_MAGIC 0x42 53 54 struct NCR_700_Host_Parameters; 55 56 /* These are the externally used routines */ 57 struct Scsi_Host *NCR_700_detect(struct scsi_host_template *, 58 struct NCR_700_Host_Parameters *, struct device *); 59 int NCR_700_release(struct Scsi_Host *host); 60 irqreturn_t NCR_700_intr(int, void *, struct pt_regs *); 61 62 63 enum NCR_700_Host_State { 64 NCR_700_HOST_BUSY, 65 NCR_700_HOST_FREE, 66 }; 67 68 struct NCR_700_SG_List { 69 /* The following is a script fragment to move the buffer onto the 70 * bus and then link the next fragment or return */ 71 #define SCRIPT_MOVE_DATA_IN 0x09000000 72 #define SCRIPT_MOVE_DATA_OUT 0x08000000 73 __u32 ins; 74 __u32 pAddr; 75 #define SCRIPT_NOP 0x80000000 76 #define SCRIPT_RETURN 0x90080000 77 }; 78 79 /* We use device->hostdata to store negotiated parameters. This is 80 * supposed to be a pointer to a device private area, but we cannot 81 * really use it as such since it will never be freed, so just use the 82 * 32 bits to cram the information. The SYNC negotiation sequence looks 83 * like: 84 * 85 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the 86 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION 87 * If we get an SDTR reply, work out the SXFER parameters, squirrel 88 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set 89 * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel 90 * 91 * 92 * 0:7 SXFER_REG negotiated value for this device 93 * 8:15 Current queue depth 94 * 16 negotiated SYNC flag 95 * 17 begin SYNC negotiation flag 96 * 18 device supports tag queueing */ 97 #define NCR_700_DEV_NEGOTIATED_SYNC (1<<16) 98 #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17) 99 #define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19) 100 101 static inline void 102 NCR_700_set_depth(struct scsi_device *SDp, __u8 depth) 103 { 104 long l = (long)SDp->hostdata; 105 106 l &= 0xffff00ff; 107 l |= 0xff00 & (depth << 8); 108 SDp->hostdata = (void *)l; 109 } 110 static inline __u8 111 NCR_700_get_depth(struct scsi_device *SDp) 112 { 113 return ((((unsigned long)SDp->hostdata) & 0xff00)>>8); 114 } 115 static inline int 116 NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag) 117 { 118 return (spi_flags(SDp->sdev_target) & flag) == flag; 119 } 120 static inline int 121 NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag) 122 { 123 return (spi_flags(SDp->sdev_target) & flag) == 0; 124 } 125 static inline void 126 NCR_700_set_flag(struct scsi_device *SDp, __u32 flag) 127 { 128 spi_flags(SDp->sdev_target) |= flag; 129 } 130 static inline void 131 NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag) 132 { 133 spi_flags(SDp->sdev_target) &= ~flag; 134 } 135 136 enum NCR_700_tag_neg_state { 137 NCR_700_START_TAG_NEGOTIATION = 0, 138 NCR_700_DURING_TAG_NEGOTIATION = 1, 139 NCR_700_FINISHED_TAG_NEGOTIATION = 2, 140 }; 141 142 static inline enum NCR_700_tag_neg_state 143 NCR_700_get_tag_neg_state(struct scsi_device *SDp) 144 { 145 return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3); 146 } 147 148 static inline void 149 NCR_700_set_tag_neg_state(struct scsi_device *SDp, 150 enum NCR_700_tag_neg_state state) 151 { 152 /* clear the slot */ 153 spi_flags(SDp->sdev_target) &= ~(0x3 << 20); 154 spi_flags(SDp->sdev_target) |= ((__u32)state) << 20; 155 } 156 157 struct NCR_700_command_slot { 158 struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1]; 159 struct NCR_700_SG_List *pSG; 160 #define NCR_700_SLOT_MASK 0xFC 161 #define NCR_700_SLOT_MAGIC 0xb8 162 #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */ 163 #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */ 164 #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */ 165 __u8 state; 166 #define NCR_700_FLAG_AUTOSENSE 0x01 167 __u8 flags; 168 int tag; 169 __u32 resume_offset; 170 struct scsi_cmnd *cmnd; 171 /* The pci_mapped address of the actual command in cmnd */ 172 dma_addr_t pCmd; 173 __u32 temp; 174 /* if this command is a pci_single mapping, holds the dma address 175 * for later unmapping in the done routine */ 176 dma_addr_t dma_handle; 177 /* historical remnant, now used to link free commands */ 178 struct NCR_700_command_slot *ITL_forw; 179 }; 180 181 struct NCR_700_Host_Parameters { 182 /* These must be filled in by the calling driver */ 183 int clock; /* board clock speed in MHz */ 184 void __iomem *base; /* the base for the port (copied to host) */ 185 struct device *dev; 186 __u32 dmode_extra; /* adjustable bus settings */ 187 __u32 differential:1; /* if we are differential */ 188 #ifdef CONFIG_53C700_LE_ON_BE 189 /* This option is for HP only. Set it if your chip is wired for 190 * little endian on this platform (which is big endian) */ 191 __u32 force_le_on_be:1; 192 #endif 193 __u32 chip710:1; /* set if really a 710 not 700 */ 194 __u32 burst_disable:1; /* set to 1 to disable 710 bursting */ 195 196 /* NOTHING BELOW HERE NEEDS ALTERING */ 197 __u32 fast:1; /* if we can alter the SCSI bus clock 198 speed (so can negiotiate sync) */ 199 int sync_clock; /* The speed of the SYNC core */ 200 201 __u32 *script; /* pointer to script location */ 202 __u32 pScript; /* physical mem addr of script */ 203 204 enum NCR_700_Host_State state; /* protected by state lock */ 205 struct scsi_cmnd *cmd; 206 /* Note: pScript contains the single consistent block of 207 * memory. All the msgin, msgout and status are allocated in 208 * this memory too (at separate cache lines). TOTAL_MEM_SIZE 209 * represents the total size of this area */ 210 #define MSG_ARRAY_SIZE 8 211 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT))) 212 __u8 *msgout; 213 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 214 __u8 *msgin; 215 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 216 __u8 *status; 217 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 218 struct NCR_700_command_slot *slots; 219 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST)) 220 int saved_slot_position; 221 int command_slot_count; /* protected by state lock */ 222 __u8 tag_negotiated; 223 __u8 rev; 224 __u8 reselection_id; 225 __u8 min_period; 226 227 /* Free list, singly linked by ITL_forw elements */ 228 struct NCR_700_command_slot *free_list; 229 /* Completion for waited for ops, like reset, abort or 230 * device reset. 231 * 232 * NOTE: relies on single threading in the error handler to 233 * have only one outstanding at once */ 234 struct completion *eh_complete; 235 }; 236 237 /* 238 * 53C700 Register Interface - the offset from the Selected base 239 * I/O address */ 240 #ifdef CONFIG_53C700_LE_ON_BE 241 #define bE (hostdata->force_le_on_be ? 0 : 3) 242 #define bSWAP (hostdata->force_le_on_be) 243 #define bEBus (!hostdata->force_le_on_be) 244 #elif defined(__BIG_ENDIAN) 245 #define bE 3 246 #define bSWAP 0 247 #elif defined(__LITTLE_ENDIAN) 248 #define bE 0 249 #define bSWAP 0 250 #else 251 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?" 252 #endif 253 #ifndef bEBus 254 #ifdef CONFIG_53C700_BE_BUS 255 #define bEBus 1 256 #else 257 #define bEBus 0 258 #endif 259 #endif 260 #define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x)) 261 #define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x)) 262 263 /* NOTE: These registers are in the LE register space only, the required byte 264 * swapping is done by the NCR_700_{read|write}[b] functions */ 265 #define SCNTL0_REG 0x00 266 #define FULL_ARBITRATION 0xc0 267 #define PARITY 0x08 268 #define ENABLE_PARITY 0x04 269 #define AUTO_ATN 0x02 270 #define SCNTL1_REG 0x01 271 #define SLOW_BUS 0x80 272 #define ENABLE_SELECT 0x20 273 #define ASSERT_RST 0x08 274 #define ASSERT_EVEN_PARITY 0x04 275 #define SDID_REG 0x02 276 #define SIEN_REG 0x03 277 #define PHASE_MM_INT 0x80 278 #define FUNC_COMP_INT 0x40 279 #define SEL_TIMEOUT_INT 0x20 280 #define SELECT_INT 0x10 281 #define GROSS_ERR_INT 0x08 282 #define UX_DISC_INT 0x04 283 #define RST_INT 0x02 284 #define PAR_ERR_INT 0x01 285 #define SCID_REG 0x04 286 #define SXFER_REG 0x05 287 #define ASYNC_OPERATION 0x00 288 #define SODL_REG 0x06 289 #define SOCL_REG 0x07 290 #define SFBR_REG 0x08 291 #define SIDL_REG 0x09 292 #define SBDL_REG 0x0A 293 #define SBCL_REG 0x0B 294 /* read bits */ 295 #define SBCL_IO 0x01 296 /*write bits */ 297 #define SYNC_DIV_AS_ASYNC 0x00 298 #define SYNC_DIV_1_0 0x01 299 #define SYNC_DIV_1_5 0x02 300 #define SYNC_DIV_2_0 0x03 301 #define DSTAT_REG 0x0C 302 #define ILGL_INST_DETECTED 0x01 303 #define WATCH_DOG_INTERRUPT 0x02 304 #define SCRIPT_INT_RECEIVED 0x04 305 #define ABORTED 0x10 306 #define SSTAT0_REG 0x0D 307 #define PARITY_ERROR 0x01 308 #define SCSI_RESET_DETECTED 0x02 309 #define UNEXPECTED_DISCONNECT 0x04 310 #define SCSI_GROSS_ERROR 0x08 311 #define SELECTED 0x10 312 #define SELECTION_TIMEOUT 0x20 313 #define FUNCTION_COMPLETE 0x40 314 #define PHASE_MISMATCH 0x80 315 #define SSTAT1_REG 0x0E 316 #define SIDL_REG_FULL 0x80 317 #define SODR_REG_FULL 0x40 318 #define SODL_REG_FULL 0x20 319 #define SSTAT2_REG 0x0F 320 #define CTEST0_REG 0x14 321 #define BTB_TIMER_DISABLE 0x40 322 #define CTEST1_REG 0x15 323 #define CTEST2_REG 0x16 324 #define CTEST3_REG 0x17 325 #define CTEST4_REG 0x18 326 #define DISABLE_FIFO 0x00 327 #define SLBE 0x10 328 #define SFWR 0x08 329 #define BYTE_LANE0 0x04 330 #define BYTE_LANE1 0x05 331 #define BYTE_LANE2 0x06 332 #define BYTE_LANE3 0x07 333 #define SCSI_ZMODE 0x20 334 #define ZMODE 0x40 335 #define CTEST5_REG 0x19 336 #define MASTER_CONTROL 0x10 337 #define DMA_DIRECTION 0x08 338 #define CTEST7_REG 0x1B 339 #define BURST_DISABLE 0x80 /* 710 only */ 340 #define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */ 341 #define DFP 0x08 342 #define EVP 0x04 343 #define DIFF 0x01 344 #define CTEST6_REG 0x1A 345 #define TEMP_REG 0x1C 346 #define DFIFO_REG 0x20 347 #define FLUSH_DMA_FIFO 0x80 348 #define CLR_FIFO 0x40 349 #define ISTAT_REG 0x21 350 #define ABORT_OPERATION 0x80 351 #define SOFTWARE_RESET_710 0x40 352 #define DMA_INT_PENDING 0x01 353 #define SCSI_INT_PENDING 0x02 354 #define CONNECTED 0x08 355 #define CTEST8_REG 0x22 356 #define LAST_DIS_ENBL 0x01 357 #define SHORTEN_FILTERING 0x04 358 #define ENABLE_ACTIVE_NEGATION 0x10 359 #define GENERATE_RECEIVE_PARITY 0x20 360 #define CLR_FIFO_710 0x04 361 #define FLUSH_DMA_FIFO_710 0x08 362 #define CTEST9_REG 0x23 363 #define DBC_REG 0x24 364 #define DCMD_REG 0x27 365 #define DNAD_REG 0x28 366 #define DIEN_REG 0x39 367 #define BUS_FAULT 0x20 368 #define ABORT_INT 0x10 369 #define INT_INST_INT 0x04 370 #define WD_INT 0x02 371 #define ILGL_INST_INT 0x01 372 #define DCNTL_REG 0x3B 373 #define SOFTWARE_RESET 0x01 374 #define COMPAT_700_MODE 0x01 375 #define SCRPTS_16BITS 0x20 376 #define ASYNC_DIV_2_0 0x00 377 #define ASYNC_DIV_1_5 0x40 378 #define ASYNC_DIV_1_0 0x80 379 #define ASYNC_DIV_3_0 0xc0 380 #define DMODE_710_REG 0x38 381 #define DMODE_700_REG 0x34 382 #define BURST_LENGTH_1 0x00 383 #define BURST_LENGTH_2 0x40 384 #define BURST_LENGTH_4 0x80 385 #define BURST_LENGTH_8 0xC0 386 #define DMODE_FC1 0x10 387 #define DMODE_FC2 0x20 388 #define BW16 32 389 #define MODE_286 16 390 #define IO_XFER 8 391 #define FIXED_ADDR 4 392 393 #define DSP_REG 0x2C 394 #define DSPS_REG 0x30 395 396 /* Parameters to begin SDTR negotiations. Empirically, I find that 397 * the 53c700-66 cannot handle an offset >8, so don't change this */ 398 #define NCR_700_MAX_OFFSET 8 399 /* Was hoping the max offset would be greater for the 710, but 400 * empirically it seems to be 8 also */ 401 #define NCR_710_MAX_OFFSET 8 402 #define NCR_700_MIN_XFERP 1 403 #define NCR_710_MIN_XFERP 0 404 #define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */ 405 406 #define script_patch_32(script, symbol, value) \ 407 { \ 408 int i; \ 409 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 410 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + value; \ 411 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 412 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 413 DEBUG((" script, patching %s at %d to 0x%lx\n", \ 414 #symbol, A_##symbol##_used[i], (value))); \ 415 } \ 416 } 417 418 #define script_patch_32_abs(script, symbol, value) \ 419 { \ 420 int i; \ 421 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 422 (script)[A_##symbol##_used[i]] = bS_to_host(value); \ 423 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 424 DEBUG((" script, patching %s at %d to 0x%lx\n", \ 425 #symbol, A_##symbol##_used[i], (value))); \ 426 } \ 427 } 428 429 /* Used for patching the SCSI ID in the SELECT instruction */ 430 #define script_patch_ID(script, symbol, value) \ 431 { \ 432 int i; \ 433 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 434 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \ 435 val &= 0xff00ffff; \ 436 val |= ((value) & 0xff) << 16; \ 437 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 438 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 439 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \ 440 #symbol, A_##symbol##_used[i], val)); \ 441 } \ 442 } 443 444 #define script_patch_16(script, symbol, value) \ 445 { \ 446 int i; \ 447 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 448 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \ 449 val &= 0xffff0000; \ 450 val |= ((value) & 0xffff); \ 451 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 452 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 453 DEBUG((" script, patching short field %s at %d to 0x%x\n", \ 454 #symbol, A_##symbol##_used[i], val)); \ 455 } \ 456 } 457 458 459 static inline __u8 460 NCR_700_readb(struct Scsi_Host *host, __u32 reg) 461 { 462 const struct NCR_700_Host_Parameters *hostdata 463 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 464 465 return ioread8(hostdata->base + (reg^bE)); 466 } 467 468 static inline __u32 469 NCR_700_readl(struct Scsi_Host *host, __u32 reg) 470 { 471 const struct NCR_700_Host_Parameters *hostdata 472 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 473 __u32 value = bEBus ? ioread32be(hostdata->base + reg) : 474 ioread32(hostdata->base + reg); 475 #if 1 476 /* sanity check the register */ 477 if((reg & 0x3) != 0) 478 BUG(); 479 #endif 480 481 return value; 482 } 483 484 static inline void 485 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg) 486 { 487 const struct NCR_700_Host_Parameters *hostdata 488 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 489 490 iowrite8(value, hostdata->base + (reg^bE)); 491 } 492 493 static inline void 494 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg) 495 { 496 const struct NCR_700_Host_Parameters *hostdata 497 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 498 499 #if 1 500 /* sanity check the register */ 501 if((reg & 0x3) != 0) 502 BUG(); 503 #endif 504 505 bEBus ? iowrite32be(value, hostdata->base + reg): 506 iowrite32(value, hostdata->base + reg); 507 } 508 509 #endif 510