1 /* -*- mode: c; c-basic-offset: 8 -*- */ 2 3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios 4 * 5 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com 6 */ 7 8 #ifndef _53C700_H 9 #define _53C700_H 10 11 #include <linux/interrupt.h> 12 #include <asm/io.h> 13 14 #include <scsi/scsi_device.h> 15 16 17 /* Turn on for general debugging---too verbose for normal use */ 18 #undef NCR_700_DEBUG 19 /* Debug the tag queues, checking hash queue allocation and deallocation 20 * and search for duplicate tags */ 21 #undef NCR_700_TAG_DEBUG 22 23 #ifdef NCR_700_DEBUG 24 #define DEBUG(x) printk x 25 #define DDEBUG(prefix, sdev, fmt, a...) \ 26 sdev_printk(prefix, sdev, fmt, ##a) 27 #define CDEBUG(prefix, scmd, fmt, a...) \ 28 scmd_printk(prefix, scmd, fmt, ##a) 29 #else 30 #define DEBUG(x) do {} while (0) 31 #define DDEBUG(prefix, scmd, fmt, a...) do {} while (0) 32 #define CDEBUG(prefix, scmd, fmt, a...) do {} while (0) 33 #endif 34 35 /* The number of available command slots */ 36 #define NCR_700_COMMAND_SLOTS_PER_HOST 64 37 /* The maximum number of Scatter Gathers we allow */ 38 #define NCR_700_SG_SEGMENTS 32 39 /* The maximum number of luns (make this of the form 2^n) */ 40 #define NCR_700_MAX_LUNS 32 41 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1) 42 /* Maximum number of tags the driver ever allows per device */ 43 #define NCR_700_MAX_TAGS 16 44 /* Tag depth the driver starts out with (can be altered in sysfs) */ 45 #define NCR_700_DEFAULT_TAGS 4 46 /* This is the default number of commands per LUN in the untagged case. 47 * two is a good value because it means we can have one command active and 48 * one command fully prepared and waiting 49 */ 50 #define NCR_700_CMD_PER_LUN 2 51 /* magic byte identifying an internally generated REQUEST_SENSE command */ 52 #define NCR_700_INTERNAL_SENSE_MAGIC 0x42 53 54 struct NCR_700_Host_Parameters; 55 56 /* These are the externally used routines */ 57 struct Scsi_Host *NCR_700_detect(struct scsi_host_template *, 58 struct NCR_700_Host_Parameters *, struct device *); 59 int NCR_700_release(struct Scsi_Host *host); 60 irqreturn_t NCR_700_intr(int, void *, struct pt_regs *); 61 62 63 enum NCR_700_Host_State { 64 NCR_700_HOST_BUSY, 65 NCR_700_HOST_FREE, 66 }; 67 68 struct NCR_700_SG_List { 69 /* The following is a script fragment to move the buffer onto the 70 * bus and then link the next fragment or return */ 71 #define SCRIPT_MOVE_DATA_IN 0x09000000 72 #define SCRIPT_MOVE_DATA_OUT 0x08000000 73 __u32 ins; 74 __u32 pAddr; 75 #define SCRIPT_NOP 0x80000000 76 #define SCRIPT_RETURN 0x90080000 77 }; 78 79 /* We use device->hostdata to store negotiated parameters. This is 80 * supposed to be a pointer to a device private area, but we cannot 81 * really use it as such since it will never be freed, so just use the 82 * 32 bits to cram the information. The SYNC negotiation sequence looks 83 * like: 84 * 85 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the 86 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION 87 * If we get an SDTR reply, work out the SXFER parameters, squirrel 88 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set 89 * DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel 90 * 91 * 92 * 0:7 SXFER_REG negotiated value for this device 93 * 8:15 Current queue depth 94 * 16 negotiated SYNC flag 95 * 17 begin SYNC negotiation flag 96 * 18 device supports tag queueing */ 97 #define NCR_700_DEV_NEGOTIATED_SYNC (1<<16) 98 #define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17) 99 #define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19) 100 101 static inline void 102 NCR_700_set_depth(struct scsi_device *SDp, __u8 depth) 103 { 104 long l = (long)SDp->hostdata; 105 106 l &= 0xffff00ff; 107 l |= 0xff00 & (depth << 8); 108 SDp->hostdata = (void *)l; 109 } 110 static inline __u8 111 NCR_700_get_depth(struct scsi_device *SDp) 112 { 113 return ((((unsigned long)SDp->hostdata) & 0xff00)>>8); 114 } 115 static inline int 116 NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag) 117 { 118 return (spi_flags(SDp->sdev_target) & flag) == flag; 119 } 120 static inline int 121 NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag) 122 { 123 return (spi_flags(SDp->sdev_target) & flag) == 0; 124 } 125 static inline void 126 NCR_700_set_flag(struct scsi_device *SDp, __u32 flag) 127 { 128 spi_flags(SDp->sdev_target) |= flag; 129 } 130 static inline void 131 NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag) 132 { 133 spi_flags(SDp->sdev_target) &= ~flag; 134 } 135 136 enum NCR_700_tag_neg_state { 137 NCR_700_START_TAG_NEGOTIATION = 0, 138 NCR_700_DURING_TAG_NEGOTIATION = 1, 139 NCR_700_FINISHED_TAG_NEGOTIATION = 2, 140 }; 141 142 static inline enum NCR_700_tag_neg_state 143 NCR_700_get_tag_neg_state(struct scsi_device *SDp) 144 { 145 return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3); 146 } 147 148 static inline void 149 NCR_700_set_tag_neg_state(struct scsi_device *SDp, 150 enum NCR_700_tag_neg_state state) 151 { 152 /* clear the slot */ 153 spi_flags(SDp->sdev_target) &= ~(0x3 << 20); 154 spi_flags(SDp->sdev_target) |= ((__u32)state) << 20; 155 } 156 157 struct NCR_700_command_slot { 158 struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1]; 159 struct NCR_700_SG_List *pSG; 160 #define NCR_700_SLOT_MASK 0xFC 161 #define NCR_700_SLOT_MAGIC 0xb8 162 #define NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */ 163 #define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */ 164 #define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */ 165 __u8 state; 166 int tag; 167 __u32 resume_offset; 168 struct scsi_cmnd *cmnd; 169 /* The pci_mapped address of the actual command in cmnd */ 170 dma_addr_t pCmd; 171 __u32 temp; 172 /* if this command is a pci_single mapping, holds the dma address 173 * for later unmapping in the done routine */ 174 dma_addr_t dma_handle; 175 /* historical remnant, now used to link free commands */ 176 struct NCR_700_command_slot *ITL_forw; 177 }; 178 179 struct NCR_700_Host_Parameters { 180 /* These must be filled in by the calling driver */ 181 int clock; /* board clock speed in MHz */ 182 void __iomem *base; /* the base for the port (copied to host) */ 183 struct device *dev; 184 __u32 dmode_extra; /* adjustable bus settings */ 185 __u32 differential:1; /* if we are differential */ 186 #ifdef CONFIG_53C700_LE_ON_BE 187 /* This option is for HP only. Set it if your chip is wired for 188 * little endian on this platform (which is big endian) */ 189 __u32 force_le_on_be:1; 190 #endif 191 __u32 chip710:1; /* set if really a 710 not 700 */ 192 __u32 burst_disable:1; /* set to 1 to disable 710 bursting */ 193 194 /* NOTHING BELOW HERE NEEDS ALTERING */ 195 __u32 fast:1; /* if we can alter the SCSI bus clock 196 speed (so can negiotiate sync) */ 197 int sync_clock; /* The speed of the SYNC core */ 198 199 __u32 *script; /* pointer to script location */ 200 __u32 pScript; /* physical mem addr of script */ 201 202 enum NCR_700_Host_State state; /* protected by state lock */ 203 struct scsi_cmnd *cmd; 204 /* Note: pScript contains the single consistent block of 205 * memory. All the msgin, msgout and status are allocated in 206 * this memory too (at separate cache lines). TOTAL_MEM_SIZE 207 * represents the total size of this area */ 208 #define MSG_ARRAY_SIZE 8 209 #define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT))) 210 __u8 *msgout; 211 #define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 212 __u8 *msgin; 213 #define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 214 __u8 *status; 215 #define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE)) 216 struct NCR_700_command_slot *slots; 217 #define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST)) 218 int saved_slot_position; 219 int command_slot_count; /* protected by state lock */ 220 __u8 tag_negotiated; 221 __u8 rev; 222 __u8 reselection_id; 223 __u8 min_period; 224 225 /* Free list, singly linked by ITL_forw elements */ 226 struct NCR_700_command_slot *free_list; 227 /* Completion for waited for ops, like reset, abort or 228 * device reset. 229 * 230 * NOTE: relies on single threading in the error handler to 231 * have only one outstanding at once */ 232 struct completion *eh_complete; 233 }; 234 235 /* 236 * 53C700 Register Interface - the offset from the Selected base 237 * I/O address */ 238 #ifdef CONFIG_53C700_LE_ON_BE 239 #define bE (hostdata->force_le_on_be ? 0 : 3) 240 #define bSWAP (hostdata->force_le_on_be) 241 /* This is terrible, but there's no raw version of ioread32. That means 242 * that on a be board we swap twice (once in ioread32 and once again to 243 * get the value correct) */ 244 #define bS_to_io(x) ((hostdata->force_le_on_be) ? (x) : cpu_to_le32(x)) 245 #elif defined(__BIG_ENDIAN) 246 #define bE 3 247 #define bSWAP 0 248 #define bS_to_io(x) (x) 249 #elif defined(__LITTLE_ENDIAN) 250 #define bE 0 251 #define bSWAP 0 252 #define bS_to_io(x) (x) 253 #else 254 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?" 255 #endif 256 #define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x)) 257 #define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x)) 258 259 /* NOTE: These registers are in the LE register space only, the required byte 260 * swapping is done by the NCR_700_{read|write}[b] functions */ 261 #define SCNTL0_REG 0x00 262 #define FULL_ARBITRATION 0xc0 263 #define PARITY 0x08 264 #define ENABLE_PARITY 0x04 265 #define AUTO_ATN 0x02 266 #define SCNTL1_REG 0x01 267 #define SLOW_BUS 0x80 268 #define ENABLE_SELECT 0x20 269 #define ASSERT_RST 0x08 270 #define ASSERT_EVEN_PARITY 0x04 271 #define SDID_REG 0x02 272 #define SIEN_REG 0x03 273 #define PHASE_MM_INT 0x80 274 #define FUNC_COMP_INT 0x40 275 #define SEL_TIMEOUT_INT 0x20 276 #define SELECT_INT 0x10 277 #define GROSS_ERR_INT 0x08 278 #define UX_DISC_INT 0x04 279 #define RST_INT 0x02 280 #define PAR_ERR_INT 0x01 281 #define SCID_REG 0x04 282 #define SXFER_REG 0x05 283 #define ASYNC_OPERATION 0x00 284 #define SODL_REG 0x06 285 #define SOCL_REG 0x07 286 #define SFBR_REG 0x08 287 #define SIDL_REG 0x09 288 #define SBDL_REG 0x0A 289 #define SBCL_REG 0x0B 290 /* read bits */ 291 #define SBCL_IO 0x01 292 /*write bits */ 293 #define SYNC_DIV_AS_ASYNC 0x00 294 #define SYNC_DIV_1_0 0x01 295 #define SYNC_DIV_1_5 0x02 296 #define SYNC_DIV_2_0 0x03 297 #define DSTAT_REG 0x0C 298 #define ILGL_INST_DETECTED 0x01 299 #define WATCH_DOG_INTERRUPT 0x02 300 #define SCRIPT_INT_RECEIVED 0x04 301 #define ABORTED 0x10 302 #define SSTAT0_REG 0x0D 303 #define PARITY_ERROR 0x01 304 #define SCSI_RESET_DETECTED 0x02 305 #define UNEXPECTED_DISCONNECT 0x04 306 #define SCSI_GROSS_ERROR 0x08 307 #define SELECTED 0x10 308 #define SELECTION_TIMEOUT 0x20 309 #define FUNCTION_COMPLETE 0x40 310 #define PHASE_MISMATCH 0x80 311 #define SSTAT1_REG 0x0E 312 #define SIDL_REG_FULL 0x80 313 #define SODR_REG_FULL 0x40 314 #define SODL_REG_FULL 0x20 315 #define SSTAT2_REG 0x0F 316 #define CTEST0_REG 0x14 317 #define BTB_TIMER_DISABLE 0x40 318 #define CTEST1_REG 0x15 319 #define CTEST2_REG 0x16 320 #define CTEST3_REG 0x17 321 #define CTEST4_REG 0x18 322 #define DISABLE_FIFO 0x00 323 #define SLBE 0x10 324 #define SFWR 0x08 325 #define BYTE_LANE0 0x04 326 #define BYTE_LANE1 0x05 327 #define BYTE_LANE2 0x06 328 #define BYTE_LANE3 0x07 329 #define SCSI_ZMODE 0x20 330 #define ZMODE 0x40 331 #define CTEST5_REG 0x19 332 #define MASTER_CONTROL 0x10 333 #define DMA_DIRECTION 0x08 334 #define CTEST7_REG 0x1B 335 #define BURST_DISABLE 0x80 /* 710 only */ 336 #define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */ 337 #define DFP 0x08 338 #define EVP 0x04 339 #define DIFF 0x01 340 #define CTEST6_REG 0x1A 341 #define TEMP_REG 0x1C 342 #define DFIFO_REG 0x20 343 #define FLUSH_DMA_FIFO 0x80 344 #define CLR_FIFO 0x40 345 #define ISTAT_REG 0x21 346 #define ABORT_OPERATION 0x80 347 #define SOFTWARE_RESET_710 0x40 348 #define DMA_INT_PENDING 0x01 349 #define SCSI_INT_PENDING 0x02 350 #define CONNECTED 0x08 351 #define CTEST8_REG 0x22 352 #define LAST_DIS_ENBL 0x01 353 #define SHORTEN_FILTERING 0x04 354 #define ENABLE_ACTIVE_NEGATION 0x10 355 #define GENERATE_RECEIVE_PARITY 0x20 356 #define CLR_FIFO_710 0x04 357 #define FLUSH_DMA_FIFO_710 0x08 358 #define CTEST9_REG 0x23 359 #define DBC_REG 0x24 360 #define DCMD_REG 0x27 361 #define DNAD_REG 0x28 362 #define DIEN_REG 0x39 363 #define BUS_FAULT 0x20 364 #define ABORT_INT 0x10 365 #define INT_INST_INT 0x04 366 #define WD_INT 0x02 367 #define ILGL_INST_INT 0x01 368 #define DCNTL_REG 0x3B 369 #define SOFTWARE_RESET 0x01 370 #define COMPAT_700_MODE 0x01 371 #define SCRPTS_16BITS 0x20 372 #define ASYNC_DIV_2_0 0x00 373 #define ASYNC_DIV_1_5 0x40 374 #define ASYNC_DIV_1_0 0x80 375 #define ASYNC_DIV_3_0 0xc0 376 #define DMODE_710_REG 0x38 377 #define DMODE_700_REG 0x34 378 #define BURST_LENGTH_1 0x00 379 #define BURST_LENGTH_2 0x40 380 #define BURST_LENGTH_4 0x80 381 #define BURST_LENGTH_8 0xC0 382 #define DMODE_FC1 0x10 383 #define DMODE_FC2 0x20 384 #define BW16 32 385 #define MODE_286 16 386 #define IO_XFER 8 387 #define FIXED_ADDR 4 388 389 #define DSP_REG 0x2C 390 #define DSPS_REG 0x30 391 392 /* Parameters to begin SDTR negotiations. Empirically, I find that 393 * the 53c700-66 cannot handle an offset >8, so don't change this */ 394 #define NCR_700_MAX_OFFSET 8 395 /* Was hoping the max offset would be greater for the 710, but 396 * empirically it seems to be 8 also */ 397 #define NCR_710_MAX_OFFSET 8 398 #define NCR_700_MIN_XFERP 1 399 #define NCR_710_MIN_XFERP 0 400 #define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */ 401 402 #define script_patch_32(script, symbol, value) \ 403 { \ 404 int i; \ 405 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 406 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + value; \ 407 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 408 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 409 DEBUG((" script, patching %s at %d to 0x%lx\n", \ 410 #symbol, A_##symbol##_used[i], (value))); \ 411 } \ 412 } 413 414 #define script_patch_32_abs(script, symbol, value) \ 415 { \ 416 int i; \ 417 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 418 (script)[A_##symbol##_used[i]] = bS_to_host(value); \ 419 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 420 DEBUG((" script, patching %s at %d to 0x%lx\n", \ 421 #symbol, A_##symbol##_used[i], (value))); \ 422 } \ 423 } 424 425 /* Used for patching the SCSI ID in the SELECT instruction */ 426 #define script_patch_ID(script, symbol, value) \ 427 { \ 428 int i; \ 429 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 430 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \ 431 val &= 0xff00ffff; \ 432 val |= ((value) & 0xff) << 16; \ 433 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 434 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 435 DEBUG((" script, patching ID field %s at %d to 0x%x\n", \ 436 #symbol, A_##symbol##_used[i], val)); \ 437 } \ 438 } 439 440 #define script_patch_16(script, symbol, value) \ 441 { \ 442 int i; \ 443 for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \ 444 __u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \ 445 val &= 0xffff0000; \ 446 val |= ((value) & 0xffff); \ 447 (script)[A_##symbol##_used[i]] = bS_to_host(val); \ 448 dma_cache_sync(&(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \ 449 DEBUG((" script, patching short field %s at %d to 0x%x\n", \ 450 #symbol, A_##symbol##_used[i], val)); \ 451 } \ 452 } 453 454 455 static inline __u8 456 NCR_700_readb(struct Scsi_Host *host, __u32 reg) 457 { 458 const struct NCR_700_Host_Parameters *hostdata 459 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 460 461 return ioread8(hostdata->base + (reg^bE)); 462 } 463 464 static inline __u32 465 NCR_700_readl(struct Scsi_Host *host, __u32 reg) 466 { 467 const struct NCR_700_Host_Parameters *hostdata 468 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 469 __u32 value = ioread32(hostdata->base + reg); 470 #if 1 471 /* sanity check the register */ 472 if((reg & 0x3) != 0) 473 BUG(); 474 #endif 475 476 return bS_to_io(value); 477 } 478 479 static inline void 480 NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg) 481 { 482 const struct NCR_700_Host_Parameters *hostdata 483 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 484 485 iowrite8(value, hostdata->base + (reg^bE)); 486 } 487 488 static inline void 489 NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg) 490 { 491 const struct NCR_700_Host_Parameters *hostdata 492 = (struct NCR_700_Host_Parameters *)host->hostdata[0]; 493 494 #if 1 495 /* sanity check the register */ 496 if((reg & 0x3) != 0) 497 BUG(); 498 #endif 499 500 iowrite32(bS_to_io(value), hostdata->base + reg); 501 } 502 503 #endif 504