1 // SPDX-License-Identifier: GPL-2.0-only 2 /* uctrl.c: TS102 Microcontroller interface on Tadpole Sparcbook 3 3 * 4 * Copyright 1999 Derrick J Brashear (shadow@dementia.org) 5 * Copyright 2008 David S. Miller (davem@davemloft.net) 6 */ 7 8 #include <linux/module.h> 9 #include <linux/errno.h> 10 #include <linux/delay.h> 11 #include <linux/interrupt.h> 12 #include <linux/slab.h> 13 #include <linux/mutex.h> 14 #include <linux/ioport.h> 15 #include <linux/miscdevice.h> 16 #include <linux/mm.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 20 #include <asm/openprom.h> 21 #include <asm/oplib.h> 22 #include <asm/irq.h> 23 #include <asm/io.h> 24 25 #define DEBUG 1 26 #ifdef DEBUG 27 #define dprintk(x) printk x 28 #else 29 #define dprintk(x) 30 #endif 31 32 struct uctrl_regs { 33 u32 uctrl_intr; 34 u32 uctrl_data; 35 u32 uctrl_stat; 36 u32 uctrl_xxx[5]; 37 }; 38 39 struct ts102_regs { 40 u32 card_a_intr; 41 u32 card_a_stat; 42 u32 card_a_ctrl; 43 u32 card_a_xxx; 44 u32 card_b_intr; 45 u32 card_b_stat; 46 u32 card_b_ctrl; 47 u32 card_b_xxx; 48 u32 uctrl_intr; 49 u32 uctrl_data; 50 u32 uctrl_stat; 51 u32 uctrl_xxx; 52 u32 ts102_xxx[4]; 53 }; 54 55 /* Bits for uctrl_intr register */ 56 #define UCTRL_INTR_TXE_REQ 0x01 /* transmit FIFO empty int req */ 57 #define UCTRL_INTR_TXNF_REQ 0x02 /* transmit FIFO not full int req */ 58 #define UCTRL_INTR_RXNE_REQ 0x04 /* receive FIFO not empty int req */ 59 #define UCTRL_INTR_RXO_REQ 0x08 /* receive FIFO overflow int req */ 60 #define UCTRL_INTR_TXE_MSK 0x10 /* transmit FIFO empty mask */ 61 #define UCTRL_INTR_TXNF_MSK 0x20 /* transmit FIFO not full mask */ 62 #define UCTRL_INTR_RXNE_MSK 0x40 /* receive FIFO not empty mask */ 63 #define UCTRL_INTR_RXO_MSK 0x80 /* receive FIFO overflow mask */ 64 65 /* Bits for uctrl_stat register */ 66 #define UCTRL_STAT_TXE_STA 0x01 /* transmit FIFO empty status */ 67 #define UCTRL_STAT_TXNF_STA 0x02 /* transmit FIFO not full status */ 68 #define UCTRL_STAT_RXNE_STA 0x04 /* receive FIFO not empty status */ 69 #define UCTRL_STAT_RXO_STA 0x08 /* receive FIFO overflow status */ 70 71 static DEFINE_MUTEX(uctrl_mutex); 72 static const char *uctrl_extstatus[16] = { 73 "main power available", 74 "internal battery attached", 75 "external battery attached", 76 "external VGA attached", 77 "external keyboard attached", 78 "external mouse attached", 79 "lid down", 80 "internal battery currently charging", 81 "external battery currently charging", 82 "internal battery currently discharging", 83 "external battery currently discharging", 84 }; 85 86 /* Everything required for one transaction with the uctrl */ 87 struct uctrl_txn { 88 u8 opcode; 89 u8 inbits; 90 u8 outbits; 91 u8 *inbuf; 92 u8 *outbuf; 93 }; 94 95 struct uctrl_status { 96 u8 current_temp; /* 0x07 */ 97 u8 reset_status; /* 0x0b */ 98 u16 event_status; /* 0x0c */ 99 u16 error_status; /* 0x10 */ 100 u16 external_status; /* 0x11, 0x1b */ 101 u8 internal_charge; /* 0x18 */ 102 u8 external_charge; /* 0x19 */ 103 u16 control_lcd; /* 0x20 */ 104 u8 control_bitport; /* 0x21 */ 105 u8 speaker_volume; /* 0x23 */ 106 u8 control_tft_brightness; /* 0x24 */ 107 u8 control_kbd_repeat_delay; /* 0x28 */ 108 u8 control_kbd_repeat_period; /* 0x29 */ 109 u8 control_screen_contrast; /* 0x2F */ 110 }; 111 112 enum uctrl_opcode { 113 READ_SERIAL_NUMBER=0x1, 114 READ_ETHERNET_ADDRESS=0x2, 115 READ_HARDWARE_VERSION=0x3, 116 READ_MICROCONTROLLER_VERSION=0x4, 117 READ_MAX_TEMPERATURE=0x5, 118 READ_MIN_TEMPERATURE=0x6, 119 READ_CURRENT_TEMPERATURE=0x7, 120 READ_SYSTEM_VARIANT=0x8, 121 READ_POWERON_CYCLES=0x9, 122 READ_POWERON_SECONDS=0xA, 123 READ_RESET_STATUS=0xB, 124 READ_EVENT_STATUS=0xC, 125 READ_REAL_TIME_CLOCK=0xD, 126 READ_EXTERNAL_VGA_PORT=0xE, 127 READ_MICROCONTROLLER_ROM_CHECKSUM=0xF, 128 READ_ERROR_STATUS=0x10, 129 READ_EXTERNAL_STATUS=0x11, 130 READ_USER_CONFIGURATION_AREA=0x12, 131 READ_MICROCONTROLLER_VOLTAGE=0x13, 132 READ_INTERNAL_BATTERY_VOLTAGE=0x14, 133 READ_DCIN_VOLTAGE=0x15, 134 READ_HORIZONTAL_POINTER_VOLTAGE=0x16, 135 READ_VERTICAL_POINTER_VOLTAGE=0x17, 136 READ_INTERNAL_BATTERY_CHARGE_LEVEL=0x18, 137 READ_EXTERNAL_BATTERY_CHARGE_LEVEL=0x19, 138 READ_REAL_TIME_CLOCK_ALARM=0x1A, 139 READ_EVENT_STATUS_NO_RESET=0x1B, 140 READ_INTERNAL_KEYBOARD_LAYOUT=0x1C, 141 READ_EXTERNAL_KEYBOARD_LAYOUT=0x1D, 142 READ_EEPROM_STATUS=0x1E, 143 CONTROL_LCD=0x20, 144 CONTROL_BITPORT=0x21, 145 SPEAKER_VOLUME=0x23, 146 CONTROL_TFT_BRIGHTNESS=0x24, 147 CONTROL_WATCHDOG=0x25, 148 CONTROL_FACTORY_EEPROM_AREA=0x26, 149 CONTROL_KBD_TIME_UNTIL_REPEAT=0x28, 150 CONTROL_KBD_TIME_BETWEEN_REPEATS=0x29, 151 CONTROL_TIMEZONE=0x2A, 152 CONTROL_MARK_SPACE_RATIO=0x2B, 153 CONTROL_DIAGNOSTIC_MODE=0x2E, 154 CONTROL_SCREEN_CONTRAST=0x2F, 155 RING_BELL=0x30, 156 SET_DIAGNOSTIC_STATUS=0x32, 157 CLEAR_KEY_COMBINATION_TABLE=0x33, 158 PERFORM_SOFTWARE_RESET=0x34, 159 SET_REAL_TIME_CLOCK=0x35, 160 RECALIBRATE_POINTING_STICK=0x36, 161 SET_BELL_FREQUENCY=0x37, 162 SET_INTERNAL_BATTERY_CHARGE_RATE=0x39, 163 SET_EXTERNAL_BATTERY_CHARGE_RATE=0x3A, 164 SET_REAL_TIME_CLOCK_ALARM=0x3B, 165 READ_EEPROM=0x40, 166 WRITE_EEPROM=0x41, 167 WRITE_TO_STATUS_DISPLAY=0x42, 168 DEFINE_SPECIAL_CHARACTER=0x43, 169 DEFINE_KEY_COMBINATION_ENTRY=0x50, 170 DEFINE_STRING_TABLE_ENTRY=0x51, 171 DEFINE_STATUS_SCREEN_DISPLAY=0x52, 172 PERFORM_EMU_COMMANDS=0x64, 173 READ_EMU_REGISTER=0x65, 174 WRITE_EMU_REGISTER=0x66, 175 READ_EMU_RAM=0x67, 176 WRITE_EMU_RAM=0x68, 177 READ_BQ_REGISTER=0x69, 178 WRITE_BQ_REGISTER=0x6A, 179 SET_USER_PASSWORD=0x70, 180 VERIFY_USER_PASSWORD=0x71, 181 GET_SYSTEM_PASSWORD_KEY=0x72, 182 VERIFY_SYSTEM_PASSWORD=0x73, 183 POWER_OFF=0x82, 184 POWER_RESTART=0x83, 185 }; 186 187 static struct uctrl_driver { 188 struct uctrl_regs __iomem *regs; 189 int irq; 190 int pending; 191 struct uctrl_status status; 192 } *global_driver; 193 194 static void uctrl_get_event_status(struct uctrl_driver *); 195 static void uctrl_get_external_status(struct uctrl_driver *); 196 197 static long 198 uctrl_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 199 { 200 switch (cmd) { 201 default: 202 return -EINVAL; 203 } 204 return 0; 205 } 206 207 static int 208 uctrl_open(struct inode *inode, struct file *file) 209 { 210 mutex_lock(&uctrl_mutex); 211 uctrl_get_event_status(global_driver); 212 uctrl_get_external_status(global_driver); 213 mutex_unlock(&uctrl_mutex); 214 return 0; 215 } 216 217 static irqreturn_t uctrl_interrupt(int irq, void *dev_id) 218 { 219 return IRQ_HANDLED; 220 } 221 222 static const struct file_operations uctrl_fops = { 223 .owner = THIS_MODULE, 224 .unlocked_ioctl = uctrl_ioctl, 225 .open = uctrl_open, 226 }; 227 228 static struct miscdevice uctrl_dev = { 229 UCTRL_MINOR, 230 "uctrl", 231 &uctrl_fops 232 }; 233 234 /* Wait for space to write, then write to it */ 235 #define WRITEUCTLDATA(value) \ 236 { \ 237 unsigned int i; \ 238 for (i = 0; i < 10000; i++) { \ 239 if (UCTRL_STAT_TXNF_STA & sbus_readl(&driver->regs->uctrl_stat)) \ 240 break; \ 241 } \ 242 dprintk(("write data 0x%02x\n", value)); \ 243 sbus_writel(value, &driver->regs->uctrl_data); \ 244 } 245 246 /* Wait for something to read, read it, then clear the bit */ 247 #define READUCTLDATA(value) \ 248 { \ 249 unsigned int i; \ 250 value = 0; \ 251 for (i = 0; i < 10000; i++) { \ 252 if ((UCTRL_STAT_RXNE_STA & sbus_readl(&driver->regs->uctrl_stat)) == 0) \ 253 break; \ 254 udelay(1); \ 255 } \ 256 value = sbus_readl(&driver->regs->uctrl_data); \ 257 dprintk(("read data 0x%02x\n", value)); \ 258 sbus_writel(UCTRL_STAT_RXNE_STA, &driver->regs->uctrl_stat); \ 259 } 260 261 static void uctrl_do_txn(struct uctrl_driver *driver, struct uctrl_txn *txn) 262 { 263 int stat, incnt, outcnt, bytecnt, intr; 264 u32 byte; 265 266 stat = sbus_readl(&driver->regs->uctrl_stat); 267 intr = sbus_readl(&driver->regs->uctrl_intr); 268 sbus_writel(stat, &driver->regs->uctrl_stat); 269 270 dprintk(("interrupt stat 0x%x int 0x%x\n", stat, intr)); 271 272 incnt = txn->inbits; 273 outcnt = txn->outbits; 274 byte = (txn->opcode << 8); 275 WRITEUCTLDATA(byte); 276 277 bytecnt = 0; 278 while (incnt > 0) { 279 byte = (txn->inbuf[bytecnt] << 8); 280 WRITEUCTLDATA(byte); 281 incnt--; 282 bytecnt++; 283 } 284 285 /* Get the ack */ 286 READUCTLDATA(byte); 287 dprintk(("ack was %x\n", (byte >> 8))); 288 289 bytecnt = 0; 290 while (outcnt > 0) { 291 READUCTLDATA(byte); 292 txn->outbuf[bytecnt] = (byte >> 8); 293 dprintk(("set byte to %02x\n", byte)); 294 outcnt--; 295 bytecnt++; 296 } 297 } 298 299 static void uctrl_get_event_status(struct uctrl_driver *driver) 300 { 301 struct uctrl_txn txn; 302 u8 outbits[2]; 303 304 txn.opcode = READ_EVENT_STATUS; 305 txn.inbits = 0; 306 txn.outbits = 2; 307 txn.inbuf = NULL; 308 txn.outbuf = outbits; 309 310 uctrl_do_txn(driver, &txn); 311 312 dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff))); 313 driver->status.event_status = 314 ((outbits[0] & 0xff) << 8) | (outbits[1] & 0xff); 315 dprintk(("ev is %x\n", driver->status.event_status)); 316 } 317 318 static void uctrl_get_external_status(struct uctrl_driver *driver) 319 { 320 struct uctrl_txn txn; 321 u8 outbits[2]; 322 int i, v; 323 324 txn.opcode = READ_EXTERNAL_STATUS; 325 txn.inbits = 0; 326 txn.outbits = 2; 327 txn.inbuf = NULL; 328 txn.outbuf = outbits; 329 330 uctrl_do_txn(driver, &txn); 331 332 dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff))); 333 driver->status.external_status = 334 ((outbits[0] * 256) + (outbits[1])); 335 dprintk(("ex is %x\n", driver->status.external_status)); 336 v = driver->status.external_status; 337 for (i = 0; v != 0; i++, v >>= 1) { 338 if (v & 1) { 339 dprintk(("%s%s", " ", uctrl_extstatus[i])); 340 } 341 } 342 dprintk(("\n")); 343 344 } 345 346 static int uctrl_probe(struct platform_device *op) 347 { 348 struct uctrl_driver *p; 349 int err = -ENOMEM; 350 351 p = kzalloc(sizeof(*p), GFP_KERNEL); 352 if (!p) { 353 printk(KERN_ERR "uctrl: Unable to allocate device struct.\n"); 354 goto out; 355 } 356 357 p->regs = of_ioremap(&op->resource[0], 0, 358 resource_size(&op->resource[0]), 359 "uctrl"); 360 if (!p->regs) { 361 printk(KERN_ERR "uctrl: Unable to map registers.\n"); 362 goto out_free; 363 } 364 365 p->irq = op->archdata.irqs[0]; 366 err = request_irq(p->irq, uctrl_interrupt, 0, "uctrl", p); 367 if (err) { 368 printk(KERN_ERR "uctrl: Unable to register irq.\n"); 369 goto out_iounmap; 370 } 371 372 err = misc_register(&uctrl_dev); 373 if (err) { 374 printk(KERN_ERR "uctrl: Unable to register misc device.\n"); 375 goto out_free_irq; 376 } 377 378 sbus_writel(UCTRL_INTR_RXNE_REQ|UCTRL_INTR_RXNE_MSK, &p->regs->uctrl_intr); 379 printk(KERN_INFO "%pOF: uctrl regs[0x%p] (irq %d)\n", 380 op->dev.of_node, p->regs, p->irq); 381 uctrl_get_event_status(p); 382 uctrl_get_external_status(p); 383 384 dev_set_drvdata(&op->dev, p); 385 global_driver = p; 386 387 out: 388 return err; 389 390 out_free_irq: 391 free_irq(p->irq, p); 392 393 out_iounmap: 394 of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0])); 395 396 out_free: 397 kfree(p); 398 goto out; 399 } 400 401 static void uctrl_remove(struct platform_device *op) 402 { 403 struct uctrl_driver *p = dev_get_drvdata(&op->dev); 404 405 if (p) { 406 misc_deregister(&uctrl_dev); 407 free_irq(p->irq, p); 408 of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0])); 409 kfree(p); 410 } 411 } 412 413 static const struct of_device_id uctrl_match[] = { 414 { 415 .name = "uctrl", 416 }, 417 {}, 418 }; 419 MODULE_DEVICE_TABLE(of, uctrl_match); 420 421 static struct platform_driver uctrl_driver = { 422 .driver = { 423 .name = "uctrl", 424 .of_match_table = uctrl_match, 425 }, 426 .probe = uctrl_probe, 427 .remove_new = uctrl_remove, 428 }; 429 430 431 module_platform_driver(uctrl_driver); 432 433 MODULE_DESCRIPTION("Tadpole TS102 Microcontroller driver"); 434 MODULE_LICENSE("GPL"); 435