1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright IBM Corp. 2000, 2009 4 * Author(s): Utz Bacher <utz.bacher@de.ibm.com> 5 * Jan Glauber <jang@linux.vnet.ibm.com> 6 */ 7 #ifndef _CIO_QDIO_H 8 #define _CIO_QDIO_H 9 10 #include <asm/page.h> 11 #include <asm/schid.h> 12 #include <asm/debug.h> 13 #include "chsc.h" 14 15 #define QDIO_BUSY_BIT_PATIENCE (100 << 12) /* 100 microseconds */ 16 #define QDIO_BUSY_BIT_RETRY_DELAY 10 /* 10 milliseconds */ 17 #define QDIO_BUSY_BIT_RETRIES 1000 /* = 10s retry time */ 18 19 enum qdio_irq_states { 20 QDIO_IRQ_STATE_INACTIVE, 21 QDIO_IRQ_STATE_ESTABLISHED, 22 QDIO_IRQ_STATE_ACTIVE, 23 QDIO_IRQ_STATE_STOPPED, 24 QDIO_IRQ_STATE_CLEANUP, 25 QDIO_IRQ_STATE_ERR, 26 NR_QDIO_IRQ_STATES, 27 }; 28 29 /* used as intparm in do_IO */ 30 #define QDIO_DOING_ESTABLISH 1 31 #define QDIO_DOING_ACTIVATE 2 32 #define QDIO_DOING_CLEANUP 3 33 34 #define SLSB_STATE_NOT_INIT 0x0 35 #define SLSB_STATE_EMPTY 0x1 36 #define SLSB_STATE_PRIMED 0x2 37 #define SLSB_STATE_PENDING 0x3 38 #define SLSB_STATE_HALTED 0xe 39 #define SLSB_STATE_ERROR 0xf 40 #define SLSB_TYPE_INPUT 0x0 41 #define SLSB_TYPE_OUTPUT 0x20 42 #define SLSB_OWNER_PROG 0x80 43 #define SLSB_OWNER_CU 0x40 44 45 #define SLSB_P_INPUT_NOT_INIT \ 46 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT) /* 0x80 */ 47 #define SLSB_P_INPUT_ACK \ 48 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x81 */ 49 #define SLSB_CU_INPUT_EMPTY \ 50 (SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x41 */ 51 #define SLSB_P_INPUT_PRIMED \ 52 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED) /* 0x82 */ 53 #define SLSB_P_INPUT_HALTED \ 54 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED) /* 0x8e */ 55 #define SLSB_P_INPUT_ERROR \ 56 (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR) /* 0x8f */ 57 #define SLSB_P_OUTPUT_NOT_INIT \ 58 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */ 59 #define SLSB_P_OUTPUT_EMPTY \ 60 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY) /* 0xa1 */ 61 #define SLSB_P_OUTPUT_PENDING \ 62 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_PENDING) /* 0xa3 */ 63 #define SLSB_CU_OUTPUT_PRIMED \ 64 (SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED) /* 0x62 */ 65 #define SLSB_P_OUTPUT_HALTED \ 66 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED) /* 0xae */ 67 #define SLSB_P_OUTPUT_ERROR \ 68 (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR) /* 0xaf */ 69 70 #define SLSB_ERROR_DURING_LOOKUP 0xff 71 72 /* additional CIWs returned by extended Sense-ID */ 73 #define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */ 74 #define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */ 75 76 /* flags for st qdio sch data */ 77 #define CHSC_FLAG_QDIO_CAPABILITY 0x80 78 #define CHSC_FLAG_VALIDITY 0x40 79 80 /* SIGA flags */ 81 #define QDIO_SIGA_WRITE 0x00 82 #define QDIO_SIGA_READ 0x01 83 #define QDIO_SIGA_SYNC 0x02 84 #define QDIO_SIGA_WRITEM 0x03 85 #define QDIO_SIGA_WRITEQ 0x04 86 #define QDIO_SIGA_QEBSM_FLAG 0x80 87 88 static inline int do_sqbs(u64 token, unsigned char state, int queue, 89 int *start, int *count) 90 { 91 register unsigned long _ccq asm ("0") = *count; 92 register unsigned long _token asm ("1") = token; 93 unsigned long _queuestart = ((unsigned long)queue << 32) | *start; 94 95 asm volatile( 96 " .insn rsy,0xeb000000008A,%1,0,0(%2)" 97 : "+d" (_ccq), "+d" (_queuestart) 98 : "d" ((unsigned long)state), "d" (_token) 99 : "memory", "cc"); 100 *count = _ccq & 0xff; 101 *start = _queuestart & 0xff; 102 103 return (_ccq >> 32) & 0xff; 104 } 105 106 static inline int do_eqbs(u64 token, unsigned char *state, int queue, 107 int *start, int *count, int ack) 108 { 109 register unsigned long _ccq asm ("0") = *count; 110 register unsigned long _token asm ("1") = token; 111 unsigned long _queuestart = ((unsigned long)queue << 32) | *start; 112 unsigned long _state = (unsigned long)ack << 63; 113 114 asm volatile( 115 " .insn rrf,0xB99c0000,%1,%2,0,0" 116 : "+d" (_ccq), "+d" (_queuestart), "+d" (_state) 117 : "d" (_token) 118 : "memory", "cc"); 119 *count = _ccq & 0xff; 120 *start = _queuestart & 0xff; 121 *state = _state & 0xff; 122 123 return (_ccq >> 32) & 0xff; 124 } 125 126 struct qdio_irq; 127 128 struct siga_flag { 129 u8 input:1; 130 u8 output:1; 131 u8 sync:1; 132 u8 sync_after_ai:1; 133 u8 sync_out_after_pci:1; 134 u8:3; 135 } __attribute__ ((packed)); 136 137 struct qdio_dev_perf_stat { 138 unsigned int adapter_int; 139 unsigned int qdio_int; 140 unsigned int pci_request_int; 141 142 unsigned int tasklet_outbound; 143 144 unsigned int siga_read; 145 unsigned int siga_write; 146 unsigned int siga_sync; 147 148 unsigned int inbound_call; 149 unsigned int stop_polling; 150 unsigned int inbound_queue_full; 151 unsigned int outbound_call; 152 unsigned int outbound_handler; 153 unsigned int outbound_queue_full; 154 unsigned int fast_requeue; 155 unsigned int target_full; 156 unsigned int eqbs; 157 unsigned int eqbs_partial; 158 unsigned int sqbs; 159 unsigned int sqbs_partial; 160 unsigned int int_discarded; 161 } ____cacheline_aligned; 162 163 struct qdio_queue_perf_stat { 164 /* Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128. */ 165 unsigned int nr_sbals[8]; 166 unsigned int nr_sbal_error; 167 unsigned int nr_sbal_nop; 168 unsigned int nr_sbal_total; 169 }; 170 171 enum qdio_irq_poll_states { 172 QDIO_IRQ_DISABLED, 173 }; 174 175 struct qdio_input_q { 176 /* Batch of SBALs that we processed while polling the queue: */ 177 unsigned int batch_start; 178 unsigned int batch_count; 179 }; 180 181 struct qdio_output_q { 182 /* PCIs are enabled for the queue */ 183 int pci_out_enabled; 184 /* timer to check for more outbound work */ 185 struct timer_list timer; 186 /* tasklet to check for completions */ 187 struct tasklet_struct tasklet; 188 }; 189 190 /* 191 * Note on cache alignment: grouped slsb and write mostly data at the beginning 192 * sbal[] is read-only and starts on a new cacheline followed by read mostly. 193 */ 194 struct qdio_q { 195 struct slsb slsb; 196 197 union { 198 struct qdio_input_q in; 199 struct qdio_output_q out; 200 } u; 201 202 /* 203 * inbound: next buffer the program should check for 204 * outbound: next buffer to check if adapter processed it 205 */ 206 int first_to_check; 207 208 /* number of buffers in use by the adapter */ 209 atomic_t nr_buf_used; 210 211 /* last scan of the queue */ 212 u64 timestamp; 213 214 struct qdio_queue_perf_stat q_stats; 215 216 struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned; 217 218 /* queue number */ 219 int nr; 220 221 /* bitmask of queue number */ 222 int mask; 223 224 /* input or output queue */ 225 int is_input_q; 226 227 /* upper-layer program handler */ 228 qdio_handler_t (*handler); 229 230 struct qdio_irq *irq_ptr; 231 struct sl *sl; 232 /* 233 * A page is allocated under this pointer and used for slib and sl. 234 * slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2. 235 */ 236 struct slib *slib; 237 } __attribute__ ((aligned(256))); 238 239 struct qdio_irq { 240 struct qib qib; 241 u32 *dsci; /* address of device state change indicator */ 242 struct ccw_device *cdev; 243 struct list_head entry; /* list of thinint devices */ 244 struct dentry *debugfs_dev; 245 u64 last_data_irq_time; 246 247 unsigned long int_parm; 248 struct subchannel_id schid; 249 unsigned long sch_token; /* QEBSM facility */ 250 251 enum qdio_irq_states state; 252 253 struct siga_flag siga_flag; /* siga sync information from qdioac */ 254 255 int nr_input_qs; 256 int nr_output_qs; 257 258 struct ccw1 ccw; 259 struct ciw equeue; 260 struct ciw aqueue; 261 262 struct qdio_ssqd_desc ssqd_desc; 263 void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *); 264 265 unsigned int scan_threshold; /* used SBALs before tasklet schedule */ 266 int perf_stat_enabled; 267 268 struct qdr *qdr; 269 unsigned long chsc_page; 270 271 struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ]; 272 struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ]; 273 unsigned int max_input_qs; 274 unsigned int max_output_qs; 275 276 void (*irq_poll)(struct ccw_device *cdev, unsigned long data); 277 unsigned long poll_state; 278 279 debug_info_t *debug_area; 280 struct mutex setup_mutex; 281 struct qdio_dev_perf_stat perf_stat; 282 }; 283 284 /* helper functions */ 285 #define queue_type(q) q->irq_ptr->qib.qfmt 286 #define SCH_NO(q) (q->irq_ptr->schid.sch_no) 287 288 #define is_thinint_irq(irq) \ 289 (irq->qib.qfmt == QDIO_IQDIO_QFMT || \ 290 css_general_characteristics.aif_osa) 291 292 #define qperf(__qdev, __attr) ((__qdev)->perf_stat.(__attr)) 293 294 #define QDIO_PERF_STAT_INC(__irq, __attr) \ 295 ({ \ 296 struct qdio_irq *qdev = __irq; \ 297 if (qdev->perf_stat_enabled) \ 298 (qdev->perf_stat.__attr)++; \ 299 }) 300 301 #define qperf_inc(__q, __attr) QDIO_PERF_STAT_INC((__q)->irq_ptr, __attr) 302 303 static inline void account_sbals_error(struct qdio_q *q, int count) 304 { 305 q->q_stats.nr_sbal_error += count; 306 q->q_stats.nr_sbal_total += count; 307 } 308 309 /* the highest iqdio queue is used for multicast */ 310 static inline int multicast_outbound(struct qdio_q *q) 311 { 312 return (q->irq_ptr->nr_output_qs > 1) && 313 (q->nr == q->irq_ptr->nr_output_qs - 1); 314 } 315 316 static inline void qdio_deliver_irq(struct qdio_irq *irq) 317 { 318 if (!test_and_set_bit(QDIO_IRQ_DISABLED, &irq->poll_state)) 319 irq->irq_poll(irq->cdev, irq->int_parm); 320 else 321 QDIO_PERF_STAT_INC(irq, int_discarded); 322 } 323 324 #define pci_out_supported(irq) ((irq)->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED) 325 #define is_qebsm(q) (q->irq_ptr->sch_token != 0) 326 327 #define need_siga_in(q) (q->irq_ptr->siga_flag.input) 328 #define need_siga_out(q) (q->irq_ptr->siga_flag.output) 329 #define need_siga_sync(q) (unlikely(q->irq_ptr->siga_flag.sync)) 330 #define need_siga_sync_after_ai(q) \ 331 (unlikely(q->irq_ptr->siga_flag.sync_after_ai)) 332 #define need_siga_sync_out_after_pci(q) \ 333 (unlikely(q->irq_ptr->siga_flag.sync_out_after_pci)) 334 335 #define for_each_input_queue(irq_ptr, q, i) \ 336 for (i = 0; i < irq_ptr->nr_input_qs && \ 337 ({ q = irq_ptr->input_qs[i]; 1; }); i++) 338 #define for_each_output_queue(irq_ptr, q, i) \ 339 for (i = 0; i < irq_ptr->nr_output_qs && \ 340 ({ q = irq_ptr->output_qs[i]; 1; }); i++) 341 342 #define add_buf(bufnr, inc) QDIO_BUFNR((bufnr) + (inc)) 343 #define next_buf(bufnr) add_buf(bufnr, 1) 344 #define sub_buf(bufnr, dec) QDIO_BUFNR((bufnr) - (dec)) 345 #define prev_buf(bufnr) sub_buf(bufnr, 1) 346 347 #define queue_irqs_enabled(q) \ 348 (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0) 349 #define queue_irqs_disabled(q) \ 350 (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0) 351 352 extern u64 last_ai_time; 353 354 /* prototypes for thin interrupt */ 355 int qdio_establish_thinint(struct qdio_irq *irq_ptr); 356 void qdio_shutdown_thinint(struct qdio_irq *irq_ptr); 357 int qdio_thinint_init(void); 358 void qdio_thinint_exit(void); 359 int test_nonshared_ind(struct qdio_irq *); 360 361 /* prototypes for setup */ 362 void qdio_outbound_tasklet(struct tasklet_struct *t); 363 void qdio_outbound_timer(struct timer_list *t); 364 void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm, 365 struct irb *irb); 366 int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs, 367 int nr_output_qs); 368 void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr); 369 int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr, 370 struct subchannel_id *schid, 371 struct qdio_ssqd_desc *data); 372 int qdio_setup_irq(struct qdio_irq *irq_ptr, struct qdio_initialize *init_data); 373 void qdio_shutdown_irq(struct qdio_irq *irq); 374 void qdio_print_subchannel_info(struct qdio_irq *irq_ptr); 375 void qdio_free_queues(struct qdio_irq *irq_ptr); 376 int qdio_setup_init(void); 377 void qdio_setup_exit(void); 378 379 int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr, 380 unsigned char *state); 381 #endif /* _CIO_QDIO_H */ 382