1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Texas Instruments K3 RTC driver 4 * 5 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/sys_soc.h> 14 #include <linux/property.h> 15 #include <linux/regmap.h> 16 #include <linux/rtc.h> 17 18 /* Registers */ 19 #define REG_K3RTC_S_CNT_LSW 0x08 20 #define REG_K3RTC_S_CNT_MSW 0x0c 21 #define REG_K3RTC_COMP 0x10 22 #define REG_K3RTC_ON_OFF_S_CNT_LSW 0x20 23 #define REG_K3RTC_ON_OFF_S_CNT_MSW 0x24 24 #define REG_K3RTC_SCRATCH0 0x30 25 #define REG_K3RTC_SCRATCH7 0x4c 26 #define REG_K3RTC_GENERAL_CTL 0x50 27 #define REG_K3RTC_IRQSTATUS_RAW_SYS 0x54 28 #define REG_K3RTC_IRQSTATUS_SYS 0x58 29 #define REG_K3RTC_IRQENABLE_SET_SYS 0x5c 30 #define REG_K3RTC_IRQENABLE_CLR_SYS 0x60 31 #define REG_K3RTC_SYNCPEND 0x68 32 #define REG_K3RTC_KICK0 0x70 33 #define REG_K3RTC_KICK1 0x74 34 35 /* Freeze when lsw is read and unfreeze when msw is read */ 36 #define K3RTC_CNT_FMODE_S_CNT_VALUE (0x2 << 24) 37 38 /* Magic values for lock/unlock */ 39 #define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13 40 #define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0 41 42 /* Multiplier for ppb conversions */ 43 #define K3RTC_PPB_MULT (1000000000LL) 44 /* Min and max values supported with 'offset' interface (swapped sign) */ 45 #define K3RTC_MIN_OFFSET (-277761) 46 #define K3RTC_MAX_OFFSET (277778) 47 48 static const struct regmap_config ti_k3_rtc_regmap_config = { 49 .name = "peripheral-registers", 50 .reg_bits = 32, 51 .val_bits = 32, 52 .reg_stride = 4, 53 .max_register = REG_K3RTC_KICK1, 54 }; 55 56 enum ti_k3_rtc_fields { 57 K3RTC_KICK0, 58 K3RTC_KICK1, 59 K3RTC_S_CNT_LSW, 60 K3RTC_S_CNT_MSW, 61 K3RTC_O32K_OSC_DEP_EN, 62 K3RTC_UNLOCK, 63 K3RTC_CNT_FMODE, 64 K3RTC_PEND, 65 K3RTC_RELOAD_FROM_BBD, 66 K3RTC_COMP, 67 68 K3RTC_ALM_S_CNT_LSW, 69 K3RTC_ALM_S_CNT_MSW, 70 K3RTC_IRQ_STATUS_RAW, 71 K3RTC_IRQ_STATUS, 72 K3RTC_IRQ_ENABLE_SET, 73 K3RTC_IRQ_ENABLE_CLR, 74 75 K3RTC_IRQ_STATUS_ALT, 76 K3RTC_IRQ_ENABLE_CLR_ALT, 77 78 K3_RTC_MAX_FIELDS 79 }; 80 81 static const struct reg_field ti_rtc_reg_fields[] = { 82 [K3RTC_KICK0] = REG_FIELD(REG_K3RTC_KICK0, 0, 31), 83 [K3RTC_KICK1] = REG_FIELD(REG_K3RTC_KICK1, 0, 31), 84 [K3RTC_S_CNT_LSW] = REG_FIELD(REG_K3RTC_S_CNT_LSW, 0, 31), 85 [K3RTC_S_CNT_MSW] = REG_FIELD(REG_K3RTC_S_CNT_MSW, 0, 15), 86 [K3RTC_O32K_OSC_DEP_EN] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 21, 21), 87 [K3RTC_UNLOCK] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 23, 23), 88 [K3RTC_CNT_FMODE] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 24, 25), 89 [K3RTC_PEND] = REG_FIELD(REG_K3RTC_SYNCPEND, 0, 1), 90 [K3RTC_RELOAD_FROM_BBD] = REG_FIELD(REG_K3RTC_SYNCPEND, 31, 31), 91 [K3RTC_COMP] = REG_FIELD(REG_K3RTC_COMP, 0, 31), 92 93 /* We use on to off as alarm trigger */ 94 [K3RTC_ALM_S_CNT_LSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_LSW, 0, 31), 95 [K3RTC_ALM_S_CNT_MSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_MSW, 0, 15), 96 [K3RTC_IRQ_STATUS_RAW] = REG_FIELD(REG_K3RTC_IRQSTATUS_RAW_SYS, 0, 0), 97 [K3RTC_IRQ_STATUS] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 0, 0), 98 [K3RTC_IRQ_ENABLE_SET] = REG_FIELD(REG_K3RTC_IRQENABLE_SET_SYS, 0, 0), 99 [K3RTC_IRQ_ENABLE_CLR] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 0, 0), 100 /* Off to on is alternate */ 101 [K3RTC_IRQ_STATUS_ALT] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 1, 1), 102 [K3RTC_IRQ_ENABLE_CLR_ALT] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 1, 1), 103 }; 104 105 /** 106 * struct ti_k3_rtc - Private data for ti-k3-rtc 107 * @irq: IRQ 108 * @sync_timeout_us: data sync timeout period in uSec 109 * @rate_32k: 32k clock rate in Hz 110 * @rtc_dev: rtc device 111 * @regmap: rtc mmio regmap 112 * @r_fields: rtc register fields 113 */ 114 struct ti_k3_rtc { 115 unsigned int irq; 116 u32 sync_timeout_us; 117 unsigned long rate_32k; 118 struct rtc_device *rtc_dev; 119 struct regmap *regmap; 120 struct regmap_field *r_fields[K3_RTC_MAX_FIELDS]; 121 }; 122 123 static int k3rtc_field_read(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f) 124 { 125 int ret; 126 int val; 127 128 ret = regmap_field_read(priv->r_fields[f], &val); 129 /* 130 * We shouldn't be seeing regmap fail on us for mmio reads 131 * This is possible if clock context fails, but that isn't the case for us 132 */ 133 if (WARN_ON_ONCE(ret)) 134 return ret; 135 return val; 136 } 137 138 static void k3rtc_field_write(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f, u32 val) 139 { 140 regmap_field_write(priv->r_fields[f], val); 141 } 142 143 /** 144 * k3rtc_fence - Ensure a register sync took place between the two domains 145 * @priv: pointer to priv data 146 * 147 * Return: 0 if the sync took place, else returns -ETIMEDOUT 148 */ 149 static int k3rtc_fence(struct ti_k3_rtc *priv) 150 { 151 int ret; 152 153 ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_PEND], ret, 154 !ret, 2, priv->sync_timeout_us); 155 156 return ret; 157 } 158 159 static inline int k3rtc_check_unlocked(struct ti_k3_rtc *priv) 160 { 161 int ret; 162 163 ret = k3rtc_field_read(priv, K3RTC_UNLOCK); 164 if (ret < 0) 165 return ret; 166 167 return (ret) ? 0 : 1; 168 } 169 170 static int k3rtc_unlock_rtc(struct ti_k3_rtc *priv) 171 { 172 int ret; 173 174 ret = k3rtc_check_unlocked(priv); 175 if (!ret) 176 return ret; 177 178 k3rtc_field_write(priv, K3RTC_KICK0, K3RTC_KICK0_UNLOCK_VALUE); 179 k3rtc_field_write(priv, K3RTC_KICK1, K3RTC_KICK1_UNLOCK_VALUE); 180 181 /* Skip fence since we are going to check the unlock bit as fence */ 182 ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_UNLOCK], ret, 183 ret, 2, priv->sync_timeout_us); 184 185 return ret; 186 } 187 188 /* 189 * This is the list of SoCs affected by TI's i2327 errata causing the RTC 190 * state-machine to break if not unlocked fast enough during boot. These 191 * SoCs must have the bootloader unlock this device very early in the 192 * boot-flow before we (Linux) can use this device. 193 */ 194 static const struct soc_device_attribute has_erratum_i2327[] = { 195 { .family = "AM62X", .revision = "SR1.0" }, 196 { /* sentinel */ } 197 }; 198 199 static int k3rtc_configure(struct device *dev) 200 { 201 int ret; 202 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 203 204 /* 205 * HWBUG: The compare state machine is broken if the RTC module 206 * is NOT unlocked in under one second of boot - which is pretty long 207 * time from the perspective of Linux driver (module load, u-boot 208 * shell all can take much longer than this. 209 * 210 * In such occurrence, it is assumed that the RTC module is unusable 211 */ 212 if (soc_device_match(has_erratum_i2327)) { 213 ret = k3rtc_check_unlocked(priv); 214 /* If there is an error OR if we are locked, return error */ 215 if (ret) { 216 dev_err(dev, 217 HW_ERR "Erratum i2327 unlock QUIRK! Cannot operate!!\n"); 218 return -EFAULT; 219 } 220 } else { 221 /* May need to explicitly unlock first time */ 222 ret = k3rtc_unlock_rtc(priv); 223 if (ret) { 224 dev_err(dev, "Failed to unlock(%d)!\n", ret); 225 return ret; 226 } 227 } 228 229 /* Enable Shadow register sync on 32k clock boundary */ 230 k3rtc_field_write(priv, K3RTC_O32K_OSC_DEP_EN, 0x1); 231 232 /* 233 * Wait at least clock sync time before proceeding further programming. 234 * This ensures that the 32k based sync is active. 235 */ 236 usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 5); 237 238 /* We need to ensure fence here to make sure sync here */ 239 ret = k3rtc_fence(priv); 240 if (ret) { 241 dev_err(dev, 242 "Failed fence osc_dep enable(%d) - is 32k clk working?!\n", ret); 243 return ret; 244 } 245 246 /* 247 * FMODE setting: Reading lower seconds will freeze value on higher 248 * seconds. This also implies that we must *ALWAYS* read lower seconds 249 * prior to reading higher seconds 250 */ 251 k3rtc_field_write(priv, K3RTC_CNT_FMODE, K3RTC_CNT_FMODE_S_CNT_VALUE); 252 253 /* Clear any spurious IRQ sources if any */ 254 k3rtc_field_write(priv, K3RTC_IRQ_STATUS_ALT, 0x1); 255 k3rtc_field_write(priv, K3RTC_IRQ_STATUS, 0x1); 256 /* Disable all IRQs */ 257 k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR_ALT, 0x1); 258 k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR, 0x1); 259 260 /* And.. Let us Sync the writes in */ 261 return k3rtc_fence(priv); 262 } 263 264 static int ti_k3_rtc_read_time(struct device *dev, struct rtc_time *tm) 265 { 266 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 267 u32 seconds_lo, seconds_hi; 268 269 seconds_lo = k3rtc_field_read(priv, K3RTC_S_CNT_LSW); 270 seconds_hi = k3rtc_field_read(priv, K3RTC_S_CNT_MSW); 271 272 rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, tm); 273 274 return 0; 275 } 276 277 static int ti_k3_rtc_set_time(struct device *dev, struct rtc_time *tm) 278 { 279 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 280 time64_t seconds; 281 282 seconds = rtc_tm_to_time64(tm); 283 284 /* 285 * Read operation on LSW will freeze the RTC, so to update 286 * the time, we cannot use field operations. Just write since the 287 * reserved bits are ignored. 288 */ 289 regmap_write(priv->regmap, REG_K3RTC_S_CNT_LSW, seconds); 290 regmap_write(priv->regmap, REG_K3RTC_S_CNT_MSW, seconds >> 32); 291 292 return k3rtc_fence(priv); 293 } 294 295 static int ti_k3_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 296 { 297 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 298 u32 reg; 299 u32 offset = enabled ? K3RTC_IRQ_ENABLE_SET : K3RTC_IRQ_ENABLE_CLR; 300 301 reg = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET); 302 if ((enabled && reg) || (!enabled && !reg)) 303 return 0; 304 305 k3rtc_field_write(priv, offset, 0x1); 306 307 /* 308 * Ensure the write sync is through - NOTE: it should be OK to have 309 * ISR to fire as we are checking sync (which should be done in a 32k 310 * cycle or so). 311 */ 312 return k3rtc_fence(priv); 313 } 314 315 static int ti_k3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 316 { 317 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 318 u32 seconds_lo, seconds_hi; 319 320 seconds_lo = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_LSW); 321 seconds_hi = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_MSW); 322 323 rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, &alarm->time); 324 325 alarm->enabled = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET); 326 327 return 0; 328 } 329 330 static int ti_k3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 331 { 332 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 333 time64_t seconds; 334 int ret; 335 336 seconds = rtc_tm_to_time64(&alarm->time); 337 338 k3rtc_field_write(priv, K3RTC_ALM_S_CNT_LSW, seconds); 339 k3rtc_field_write(priv, K3RTC_ALM_S_CNT_MSW, (seconds >> 32)); 340 341 /* Make sure the alarm time is synced in */ 342 ret = k3rtc_fence(priv); 343 if (ret) { 344 dev_err(dev, "Failed to fence(%d)! Potential config issue?\n", ret); 345 return ret; 346 } 347 348 /* Alarm IRQ enable will do a sync */ 349 return ti_k3_rtc_alarm_irq_enable(dev, alarm->enabled); 350 } 351 352 static int ti_k3_rtc_read_offset(struct device *dev, long *offset) 353 { 354 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 355 u32 ticks_per_hr = priv->rate_32k * 3600; 356 int comp; 357 s64 tmp; 358 359 comp = k3rtc_field_read(priv, K3RTC_COMP); 360 361 /* Convert from RTC calibration register format to ppb format */ 362 tmp = comp * (s64)K3RTC_PPB_MULT; 363 if (tmp < 0) 364 tmp -= ticks_per_hr / 2LL; 365 else 366 tmp += ticks_per_hr / 2LL; 367 tmp = div_s64(tmp, ticks_per_hr); 368 369 /* Offset value operates in negative way, so swap sign */ 370 *offset = (long)-tmp; 371 372 return 0; 373 } 374 375 static int ti_k3_rtc_set_offset(struct device *dev, long offset) 376 { 377 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 378 u32 ticks_per_hr = priv->rate_32k * 3600; 379 int comp; 380 s64 tmp; 381 382 /* Make sure offset value is within supported range */ 383 if (offset < K3RTC_MIN_OFFSET || offset > K3RTC_MAX_OFFSET) 384 return -ERANGE; 385 386 /* Convert from ppb format to RTC calibration register format */ 387 tmp = offset * (s64)ticks_per_hr; 388 if (tmp < 0) 389 tmp -= K3RTC_PPB_MULT / 2LL; 390 else 391 tmp += K3RTC_PPB_MULT / 2LL; 392 tmp = div_s64(tmp, K3RTC_PPB_MULT); 393 394 /* Offset value operates in negative way, so swap sign */ 395 comp = (int)-tmp; 396 397 k3rtc_field_write(priv, K3RTC_COMP, comp); 398 399 return k3rtc_fence(priv); 400 } 401 402 static irqreturn_t ti_k3_rtc_interrupt(s32 irq, void *dev_id) 403 { 404 struct device *dev = dev_id; 405 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 406 u32 reg; 407 int ret; 408 409 /* 410 * IRQ assertion can be very fast, however, the IRQ Status clear 411 * de-assert depends on 32k clock edge in the 32k domain 412 * If we clear the status prior to the first 32k clock edge, 413 * the status bit is cleared, but the IRQ stays re-asserted. 414 * 415 * To prevent this condition, we need to wait for clock sync time. 416 * We can either do that by polling the 32k observability signal for 417 * a toggle OR we could just sleep and let the processor do other 418 * stuff. 419 */ 420 usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 2); 421 422 /* Lets make sure that this is a valid interrupt */ 423 reg = k3rtc_field_read(priv, K3RTC_IRQ_STATUS); 424 425 if (!reg) { 426 u32 raw = k3rtc_field_read(priv, K3RTC_IRQ_STATUS_RAW); 427 428 dev_err(dev, 429 HW_ERR 430 "Erratum i2327/IRQ trig: status: 0x%08x / 0x%08x\n", reg, raw); 431 return IRQ_NONE; 432 } 433 434 /* 435 * Write 1 to clear status reg 436 * We cannot use a field operation here due to a potential race between 437 * 32k domain and vbus domain. 438 */ 439 regmap_write(priv->regmap, REG_K3RTC_IRQSTATUS_SYS, 0x1); 440 441 /* Sync the write in */ 442 ret = k3rtc_fence(priv); 443 if (ret) { 444 dev_err(dev, "Failed to fence irq status clr(%d)!\n", ret); 445 return IRQ_NONE; 446 } 447 448 /* 449 * Force the 32k status to be reloaded back in to ensure status is 450 * reflected back correctly. 451 */ 452 k3rtc_field_write(priv, K3RTC_RELOAD_FROM_BBD, 0x1); 453 454 /* Ensure the write sync is through */ 455 ret = k3rtc_fence(priv); 456 if (ret) { 457 dev_err(dev, "Failed to fence reload from bbd(%d)!\n", ret); 458 return IRQ_NONE; 459 } 460 461 /* Now we ensure that the status bit is cleared */ 462 ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_IRQ_STATUS], 463 ret, !ret, 2, priv->sync_timeout_us); 464 if (ret) { 465 dev_err(dev, "Time out waiting for status clear\n"); 466 return IRQ_NONE; 467 } 468 469 /* Notify RTC core on event */ 470 rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF); 471 472 return IRQ_HANDLED; 473 } 474 475 static const struct rtc_class_ops ti_k3_rtc_ops = { 476 .read_time = ti_k3_rtc_read_time, 477 .set_time = ti_k3_rtc_set_time, 478 .read_alarm = ti_k3_rtc_read_alarm, 479 .set_alarm = ti_k3_rtc_set_alarm, 480 .read_offset = ti_k3_rtc_read_offset, 481 .set_offset = ti_k3_rtc_set_offset, 482 .alarm_irq_enable = ti_k3_rtc_alarm_irq_enable, 483 }; 484 485 static int ti_k3_rtc_scratch_read(void *priv_data, unsigned int offset, 486 void *val, size_t bytes) 487 { 488 struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data; 489 490 return regmap_bulk_read(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4); 491 } 492 493 static int ti_k3_rtc_scratch_write(void *priv_data, unsigned int offset, 494 void *val, size_t bytes) 495 { 496 struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data; 497 int ret; 498 499 ret = regmap_bulk_write(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4); 500 if (ret) 501 return ret; 502 503 return k3rtc_fence(priv); 504 } 505 506 static struct nvmem_config ti_k3_rtc_nvmem_config = { 507 .name = "ti_k3_rtc_scratch", 508 .word_size = 4, 509 .stride = 4, 510 .size = REG_K3RTC_SCRATCH7 - REG_K3RTC_SCRATCH0 + 4, 511 .reg_read = ti_k3_rtc_scratch_read, 512 .reg_write = ti_k3_rtc_scratch_write, 513 }; 514 515 static int k3rtc_get_32kclk(struct device *dev, struct ti_k3_rtc *priv) 516 { 517 struct clk *clk; 518 519 clk = devm_clk_get_enabled(dev, "osc32k"); 520 if (IS_ERR(clk)) 521 return PTR_ERR(clk); 522 523 priv->rate_32k = clk_get_rate(clk); 524 525 /* Make sure we are exact 32k clock. Else, try to compensate delay */ 526 if (priv->rate_32k != 32768) 527 dev_warn(dev, "Clock rate %ld is not 32768! Could misbehave!\n", 528 priv->rate_32k); 529 530 /* 531 * Sync timeout should be two 32k clk sync cycles = ~61uS. We double 532 * it to comprehend intermediate bus segment and cpu frequency 533 * deltas 534 */ 535 priv->sync_timeout_us = (u32)(DIV_ROUND_UP_ULL(1000000, priv->rate_32k) * 4); 536 537 return 0; 538 } 539 540 static int k3rtc_get_vbusclk(struct device *dev, struct ti_k3_rtc *priv) 541 { 542 struct clk *clk; 543 544 /* Note: VBUS isn't a context clock, it is needed for hardware operation */ 545 clk = devm_clk_get_enabled(dev, "vbus"); 546 if (IS_ERR(clk)) 547 return PTR_ERR(clk); 548 549 return 0; 550 } 551 552 static int ti_k3_rtc_probe(struct platform_device *pdev) 553 { 554 struct device *dev = &pdev->dev; 555 struct ti_k3_rtc *priv; 556 void __iomem *rtc_base; 557 int ret; 558 559 priv = devm_kzalloc(dev, sizeof(struct ti_k3_rtc), GFP_KERNEL); 560 if (!priv) 561 return -ENOMEM; 562 563 rtc_base = devm_platform_ioremap_resource(pdev, 0); 564 if (IS_ERR(rtc_base)) 565 return PTR_ERR(rtc_base); 566 567 priv->regmap = devm_regmap_init_mmio(dev, rtc_base, &ti_k3_rtc_regmap_config); 568 if (IS_ERR(priv->regmap)) 569 return PTR_ERR(priv->regmap); 570 571 ret = devm_regmap_field_bulk_alloc(dev, priv->regmap, priv->r_fields, 572 ti_rtc_reg_fields, K3_RTC_MAX_FIELDS); 573 if (ret) 574 return ret; 575 576 ret = k3rtc_get_32kclk(dev, priv); 577 if (ret) 578 return ret; 579 ret = k3rtc_get_vbusclk(dev, priv); 580 if (ret) 581 return ret; 582 583 ret = platform_get_irq(pdev, 0); 584 if (ret < 0) 585 return ret; 586 priv->irq = (unsigned int)ret; 587 588 priv->rtc_dev = devm_rtc_allocate_device(dev); 589 if (IS_ERR(priv->rtc_dev)) 590 return PTR_ERR(priv->rtc_dev); 591 592 priv->rtc_dev->ops = &ti_k3_rtc_ops; 593 priv->rtc_dev->range_max = (1ULL << 48) - 1; /* 48Bit seconds */ 594 ti_k3_rtc_nvmem_config.priv = priv; 595 596 ret = devm_request_threaded_irq(dev, priv->irq, NULL, 597 ti_k3_rtc_interrupt, 598 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 599 dev_name(dev), dev); 600 if (ret) { 601 dev_err(dev, "Could not request IRQ: %d\n", ret); 602 return ret; 603 } 604 605 platform_set_drvdata(pdev, priv); 606 607 ret = k3rtc_configure(dev); 608 if (ret) 609 return ret; 610 611 if (device_property_present(dev, "wakeup-source")) 612 device_init_wakeup(dev, true); 613 else 614 device_set_wakeup_capable(dev, true); 615 616 ret = devm_rtc_register_device(priv->rtc_dev); 617 if (ret) 618 return ret; 619 620 return devm_rtc_nvmem_register(priv->rtc_dev, &ti_k3_rtc_nvmem_config); 621 } 622 623 static const struct of_device_id ti_k3_rtc_of_match_table[] = { 624 {.compatible = "ti,am62-rtc" }, 625 {} 626 }; 627 MODULE_DEVICE_TABLE(of, ti_k3_rtc_of_match_table); 628 629 static int __maybe_unused ti_k3_rtc_suspend(struct device *dev) 630 { 631 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 632 633 if (device_may_wakeup(dev)) 634 return enable_irq_wake(priv->irq); 635 636 return 0; 637 } 638 639 static int __maybe_unused ti_k3_rtc_resume(struct device *dev) 640 { 641 struct ti_k3_rtc *priv = dev_get_drvdata(dev); 642 int ret = 0; 643 644 if (k3rtc_check_unlocked(priv)) { 645 /* RTC locked implies low power mode exit where RTC loses context */ 646 ret = k3rtc_configure(dev); 647 if (ret) 648 return ret; 649 } 650 651 if (device_may_wakeup(dev)) 652 disable_irq_wake(priv->irq); 653 return ret; 654 } 655 656 static SIMPLE_DEV_PM_OPS(ti_k3_rtc_pm_ops, ti_k3_rtc_suspend, ti_k3_rtc_resume); 657 658 static struct platform_driver ti_k3_rtc_driver = { 659 .probe = ti_k3_rtc_probe, 660 .driver = { 661 .name = "rtc-ti-k3", 662 .of_match_table = ti_k3_rtc_of_match_table, 663 .pm = &ti_k3_rtc_pm_ops, 664 }, 665 }; 666 module_platform_driver(ti_k3_rtc_driver); 667 668 MODULE_LICENSE("GPL"); 669 MODULE_DESCRIPTION("TI K3 RTC driver"); 670 MODULE_AUTHOR("Nishanth Menon"); 671