1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * An RTC driver for the NVIDIA Tegra 200 series internal RTC. 4 * 5 * Copyright (c) 2010-2019, NVIDIA Corporation. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/irq.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm.h> 17 #include <linux/rtc.h> 18 #include <linux/slab.h> 19 20 /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */ 21 #define TEGRA_RTC_REG_BUSY 0x004 22 #define TEGRA_RTC_REG_SECONDS 0x008 23 /* When msec is read, the seconds are buffered into shadow seconds. */ 24 #define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c 25 #define TEGRA_RTC_REG_MILLI_SECONDS 0x010 26 #define TEGRA_RTC_REG_SECONDS_ALARM0 0x014 27 #define TEGRA_RTC_REG_SECONDS_ALARM1 0x018 28 #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c 29 #define TEGRA_RTC_REG_INTR_MASK 0x028 30 /* write 1 bits to clear status bits */ 31 #define TEGRA_RTC_REG_INTR_STATUS 0x02c 32 33 /* bits in INTR_MASK */ 34 #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4) 35 #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3) 36 #define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2) 37 #define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1) 38 #define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0) 39 40 /* bits in INTR_STATUS */ 41 #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4) 42 #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3) 43 #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2) 44 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1) 45 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0) 46 47 struct tegra_rtc_info { 48 struct platform_device *pdev; 49 struct rtc_device *rtc; 50 void __iomem *base; /* NULL if not initialized */ 51 struct clk *clk; 52 int irq; /* alarm and periodic IRQ */ 53 spinlock_t lock; 54 }; 55 56 /* 57 * RTC hardware is busy when it is updating its values over AHB once every 58 * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to 59 * write. CPU is always free to read. 60 */ 61 static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info) 62 { 63 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1; 64 } 65 66 /* 67 * Wait for hardware to be ready for writing. This function tries to maximize 68 * the amount of time before the next update. It does this by waiting for the 69 * RTC to become busy with its periodic update, then returning once the RTC 70 * first becomes not busy. 71 * 72 * This periodic update (where the seconds and milliseconds are copied to the 73 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this 74 * function allows us to make some assumptions without introducing a race, 75 * because 250 us is plenty of time to read/write a value. 76 */ 77 static int tegra_rtc_wait_while_busy(struct device *dev) 78 { 79 struct tegra_rtc_info *info = dev_get_drvdata(dev); 80 int retries = 500; /* ~490 us is the worst case, ~250 us is best */ 81 82 /* 83 * First wait for the RTC to become busy. This is when it posts its 84 * updated seconds+msec registers to AHB side. 85 */ 86 while (tegra_rtc_check_busy(info)) { 87 if (!retries--) 88 goto retry_failed; 89 90 udelay(1); 91 } 92 93 /* now we have about 250 us to manipulate registers */ 94 return 0; 95 96 retry_failed: 97 dev_err(dev, "write failed: retry count exceeded\n"); 98 return -ETIMEDOUT; 99 } 100 101 static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm) 102 { 103 struct tegra_rtc_info *info = dev_get_drvdata(dev); 104 unsigned long flags; 105 u32 sec; 106 107 /* 108 * RTC hardware copies seconds to shadow seconds when a read of 109 * milliseconds occurs. use a lock to keep other threads out. 110 */ 111 spin_lock_irqsave(&info->lock, flags); 112 113 readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS); 114 sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS); 115 116 spin_unlock_irqrestore(&info->lock, flags); 117 118 rtc_time64_to_tm(sec, tm); 119 120 dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm); 121 122 return 0; 123 } 124 125 static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm) 126 { 127 struct tegra_rtc_info *info = dev_get_drvdata(dev); 128 u32 sec; 129 int ret; 130 131 /* convert tm to seconds */ 132 sec = rtc_tm_to_time64(tm); 133 134 dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm); 135 136 /* seconds only written if wait succeeded */ 137 ret = tegra_rtc_wait_while_busy(dev); 138 if (!ret) 139 writel(sec, info->base + TEGRA_RTC_REG_SECONDS); 140 141 dev_vdbg(dev, "time read back as %d\n", 142 readl(info->base + TEGRA_RTC_REG_SECONDS)); 143 144 return ret; 145 } 146 147 static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) 148 { 149 struct tegra_rtc_info *info = dev_get_drvdata(dev); 150 u32 sec, value; 151 152 sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0); 153 154 if (sec == 0) { 155 /* alarm is disabled */ 156 alarm->enabled = 0; 157 } else { 158 /* alarm is enabled */ 159 alarm->enabled = 1; 160 rtc_time64_to_tm(sec, &alarm->time); 161 } 162 163 value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS); 164 alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0; 165 166 return 0; 167 } 168 169 static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 170 { 171 struct tegra_rtc_info *info = dev_get_drvdata(dev); 172 unsigned long flags; 173 u32 status; 174 175 tegra_rtc_wait_while_busy(dev); 176 spin_lock_irqsave(&info->lock, flags); 177 178 /* read the original value, and OR in the flag */ 179 status = readl(info->base + TEGRA_RTC_REG_INTR_MASK); 180 if (enabled) 181 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */ 182 else 183 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */ 184 185 writel(status, info->base + TEGRA_RTC_REG_INTR_MASK); 186 187 spin_unlock_irqrestore(&info->lock, flags); 188 189 return 0; 190 } 191 192 static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) 193 { 194 struct tegra_rtc_info *info = dev_get_drvdata(dev); 195 u32 sec; 196 197 if (alarm->enabled) 198 sec = rtc_tm_to_time64(&alarm->time); 199 else 200 sec = 0; 201 202 tegra_rtc_wait_while_busy(dev); 203 writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0); 204 dev_vdbg(dev, "alarm read back as %d\n", 205 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0)); 206 207 /* if successfully written and alarm is enabled ... */ 208 if (sec) { 209 tegra_rtc_alarm_irq_enable(dev, 1); 210 dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time); 211 } else { 212 /* disable alarm if 0 or write error */ 213 dev_vdbg(dev, "alarm disabled\n"); 214 tegra_rtc_alarm_irq_enable(dev, 0); 215 } 216 217 return 0; 218 } 219 220 static int tegra_rtc_proc(struct device *dev, struct seq_file *seq) 221 { 222 if (!dev || !dev->driver) 223 return 0; 224 225 seq_printf(seq, "name\t\t: %s\n", dev_name(dev)); 226 227 return 0; 228 } 229 230 static irqreturn_t tegra_rtc_irq_handler(int irq, void *data) 231 { 232 struct device *dev = data; 233 struct tegra_rtc_info *info = dev_get_drvdata(dev); 234 unsigned long events = 0; 235 u32 status; 236 237 status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS); 238 if (status) { 239 /* clear the interrupt masks and status on any IRQ */ 240 tegra_rtc_wait_while_busy(dev); 241 242 spin_lock(&info->lock); 243 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK); 244 writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS); 245 spin_unlock(&info->lock); 246 } 247 248 /* check if alarm */ 249 if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) 250 events |= RTC_IRQF | RTC_AF; 251 252 /* check if periodic */ 253 if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM) 254 events |= RTC_IRQF | RTC_PF; 255 256 rtc_update_irq(info->rtc, 1, events); 257 258 return IRQ_HANDLED; 259 } 260 261 static const struct rtc_class_ops tegra_rtc_ops = { 262 .read_time = tegra_rtc_read_time, 263 .set_time = tegra_rtc_set_time, 264 .read_alarm = tegra_rtc_read_alarm, 265 .set_alarm = tegra_rtc_set_alarm, 266 .proc = tegra_rtc_proc, 267 .alarm_irq_enable = tegra_rtc_alarm_irq_enable, 268 }; 269 270 static const struct of_device_id tegra_rtc_dt_match[] = { 271 { .compatible = "nvidia,tegra20-rtc", }, 272 {} 273 }; 274 MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match); 275 276 static const struct acpi_device_id tegra_rtc_acpi_match[] = { 277 { "NVDA0280" }, 278 { } 279 }; 280 MODULE_DEVICE_TABLE(acpi, tegra_rtc_acpi_match); 281 282 static int tegra_rtc_probe(struct platform_device *pdev) 283 { 284 struct tegra_rtc_info *info; 285 int ret; 286 287 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 288 if (!info) 289 return -ENOMEM; 290 291 info->base = devm_platform_ioremap_resource(pdev, 0); 292 if (IS_ERR(info->base)) 293 return PTR_ERR(info->base); 294 295 ret = platform_get_irq(pdev, 0); 296 if (ret <= 0) 297 return ret; 298 299 info->irq = ret; 300 301 info->rtc = devm_rtc_allocate_device(&pdev->dev); 302 if (IS_ERR(info->rtc)) 303 return PTR_ERR(info->rtc); 304 305 info->rtc->ops = &tegra_rtc_ops; 306 info->rtc->range_max = U32_MAX; 307 308 if (dev_of_node(&pdev->dev)) { 309 info->clk = devm_clk_get_enabled(&pdev->dev, NULL); 310 if (IS_ERR(info->clk)) 311 return PTR_ERR(info->clk); 312 } 313 314 /* set context info */ 315 info->pdev = pdev; 316 spin_lock_init(&info->lock); 317 318 platform_set_drvdata(pdev, info); 319 320 /* clear out the hardware */ 321 writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0); 322 writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS); 323 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK); 324 325 device_init_wakeup(&pdev->dev, true); 326 327 ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler, 328 IRQF_TRIGGER_HIGH, dev_name(&pdev->dev), 329 &pdev->dev); 330 if (ret) 331 return dev_err_probe(&pdev->dev, ret, "failed to request interrupt\n"); 332 333 ret = devm_rtc_register_device(info->rtc); 334 if (ret) 335 return ret; 336 337 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n"); 338 339 return 0; 340 } 341 342 static int tegra_rtc_suspend(struct device *dev) 343 { 344 struct tegra_rtc_info *info = dev_get_drvdata(dev); 345 346 tegra_rtc_wait_while_busy(dev); 347 348 /* only use ALARM0 as a wake source */ 349 writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS); 350 writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0, 351 info->base + TEGRA_RTC_REG_INTR_MASK); 352 353 dev_vdbg(dev, "alarm sec = %d\n", 354 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0)); 355 356 dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n", 357 device_may_wakeup(dev), info->irq); 358 359 /* leave the alarms on as a wake source */ 360 if (device_may_wakeup(dev)) 361 enable_irq_wake(info->irq); 362 363 return 0; 364 } 365 366 static int tegra_rtc_resume(struct device *dev) 367 { 368 struct tegra_rtc_info *info = dev_get_drvdata(dev); 369 370 dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n", 371 device_may_wakeup(dev)); 372 373 /* alarms were left on as a wake source, turn them off */ 374 if (device_may_wakeup(dev)) 375 disable_irq_wake(info->irq); 376 377 return 0; 378 } 379 380 static DEFINE_SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume); 381 382 static void tegra_rtc_shutdown(struct platform_device *pdev) 383 { 384 dev_vdbg(&pdev->dev, "disabling interrupts\n"); 385 tegra_rtc_alarm_irq_enable(&pdev->dev, 0); 386 } 387 388 static struct platform_driver tegra_rtc_driver = { 389 .probe = tegra_rtc_probe, 390 .shutdown = tegra_rtc_shutdown, 391 .driver = { 392 .name = "tegra_rtc", 393 .of_match_table = tegra_rtc_dt_match, 394 .acpi_match_table = tegra_rtc_acpi_match, 395 .pm = pm_sleep_ptr(&tegra_rtc_pm_ops), 396 }, 397 }; 398 module_platform_driver(tegra_rtc_driver); 399 400 MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>"); 401 MODULE_DESCRIPTION("driver for Tegra internal RTC"); 402 MODULE_LICENSE("GPL"); 403