1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * An RTC driver for Allwinner A31/A23 4 * 5 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org> 6 * 7 * based on rtc-sunxi.c 8 * 9 * An RTC driver for Allwinner A10/A20 10 * 11 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/clk/sunxi-ng.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/fs.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/rtc.h> 30 #include <linux/slab.h> 31 #include <linux/types.h> 32 33 /* Control register */ 34 #define SUN6I_LOSC_CTRL 0x0000 35 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) 36 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) 37 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) 38 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) 39 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) 40 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) 41 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) 42 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) 43 44 #define SUN6I_LOSC_CLK_PRESCAL 0x0008 45 46 /* RTC */ 47 #define SUN6I_RTC_YMD 0x0010 48 #define SUN6I_RTC_HMS 0x0014 49 50 /* Alarm 0 (counter) */ 51 #define SUN6I_ALRM_COUNTER 0x0020 52 /* This holds the remaining alarm seconds on older SoCs (current value) */ 53 #define SUN6I_ALRM_COUNTER_HMS 0x0024 54 #define SUN6I_ALRM_EN 0x0028 55 #define SUN6I_ALRM_EN_CNT_EN BIT(0) 56 #define SUN6I_ALRM_IRQ_EN 0x002c 57 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) 58 #define SUN6I_ALRM_IRQ_STA 0x0030 59 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) 60 61 /* Alarm 1 (wall clock) */ 62 #define SUN6I_ALRM1_EN 0x0044 63 #define SUN6I_ALRM1_IRQ_EN 0x0048 64 #define SUN6I_ALRM1_IRQ_STA 0x004c 65 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) 66 67 /* Alarm config */ 68 #define SUN6I_ALARM_CONFIG 0x0050 69 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) 70 71 #define SUN6I_LOSC_OUT_GATING 0x0060 72 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 73 74 /* General-purpose data */ 75 #define SUN6I_GP_DATA 0x0100 76 #define SUN6I_GP_DATA_SIZE 0x20 77 78 /* 79 * Get date values 80 */ 81 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) 82 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) 83 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) 84 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) 85 86 /* 87 * Get time values 88 */ 89 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) 90 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) 91 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) 92 93 /* 94 * Set date values 95 */ 96 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) 97 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) 98 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) 99 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) 100 101 /* 102 * Set time values 103 */ 104 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) 105 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) 106 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) 107 108 /* 109 * The year parameter passed to the driver is usually an offset relative to 110 * the year 1900. This macro is used to convert this offset to another one 111 * relative to the minimum year allowed by the hardware. 112 * 113 * The year range is 1970 - 2033. This range is selected to match Allwinner's 114 * driver, even though it is somewhat limited. 115 */ 116 #define SUN6I_YEAR_MIN 1970 117 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) 118 119 #define SECS_PER_DAY (24 * 3600ULL) 120 121 /* 122 * There are other differences between models, including: 123 * 124 * - number of GPIO pins that can be configured to hold a certain level 125 * - crypto-key related registers (H5, H6) 126 * - boot process related (super standby, secondary processor entry address) 127 * registers (R40, H6) 128 * - SYS power domain controls (R40) 129 * - DCXO controls (H6) 130 * - RC oscillator calibration (H6) 131 * 132 * These functions are not covered by this driver. 133 */ 134 struct sun6i_rtc_clk_data { 135 unsigned long rc_osc_rate; 136 unsigned int fixed_prescaler : 16; 137 unsigned int has_prescaler : 1; 138 unsigned int has_out_clk : 1; 139 unsigned int has_losc_en : 1; 140 unsigned int has_auto_swt : 1; 141 }; 142 143 #define RTC_LINEAR_DAY BIT(0) 144 145 struct sun6i_rtc_dev { 146 struct rtc_device *rtc; 147 const struct sun6i_rtc_clk_data *data; 148 void __iomem *base; 149 int irq; 150 time64_t alarm; 151 unsigned long flags; 152 153 struct clk_hw hw; 154 struct clk_hw *int_osc; 155 struct clk *losc; 156 struct clk *ext_losc; 157 158 spinlock_t lock; 159 }; 160 161 static struct sun6i_rtc_dev *sun6i_rtc; 162 163 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, 164 unsigned long parent_rate) 165 { 166 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 167 u32 val = 0; 168 169 val = readl(rtc->base + SUN6I_LOSC_CTRL); 170 if (val & SUN6I_LOSC_CTRL_EXT_OSC) 171 return parent_rate; 172 173 if (rtc->data->fixed_prescaler) 174 parent_rate /= rtc->data->fixed_prescaler; 175 176 if (rtc->data->has_prescaler) { 177 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); 178 val &= GENMASK(4, 0); 179 } 180 181 return parent_rate / (val + 1); 182 } 183 184 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) 185 { 186 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 187 188 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; 189 } 190 191 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) 192 { 193 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 194 unsigned long flags; 195 u32 val; 196 197 if (index > 1) 198 return -EINVAL; 199 200 spin_lock_irqsave(&rtc->lock, flags); 201 val = readl(rtc->base + SUN6I_LOSC_CTRL); 202 val &= ~SUN6I_LOSC_CTRL_EXT_OSC; 203 val |= SUN6I_LOSC_CTRL_KEY; 204 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; 205 if (rtc->data->has_losc_en) { 206 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; 207 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; 208 } 209 writel(val, rtc->base + SUN6I_LOSC_CTRL); 210 spin_unlock_irqrestore(&rtc->lock, flags); 211 212 return 0; 213 } 214 215 static const struct clk_ops sun6i_rtc_osc_ops = { 216 .recalc_rate = sun6i_rtc_osc_recalc_rate, 217 .determine_rate = clk_hw_determine_rate_no_reparent, 218 219 .get_parent = sun6i_rtc_osc_get_parent, 220 .set_parent = sun6i_rtc_osc_set_parent, 221 }; 222 223 static void __init sun6i_rtc_clk_init(struct device_node *node, 224 const struct sun6i_rtc_clk_data *data) 225 { 226 struct clk_hw_onecell_data *clk_data; 227 struct sun6i_rtc_dev *rtc; 228 struct clk_init_data init = { 229 .ops = &sun6i_rtc_osc_ops, 230 .name = "losc", 231 }; 232 const char *iosc_name = "rtc-int-osc"; 233 const char *clkout_name = "osc32k-out"; 234 const char *parents[2]; 235 u32 reg; 236 237 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL); 238 if (!rtc) 239 return; 240 241 rtc->data = data; 242 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL); 243 if (!clk_data) { 244 kfree(rtc); 245 return; 246 } 247 248 spin_lock_init(&rtc->lock); 249 250 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); 251 if (IS_ERR(rtc->base)) { 252 pr_crit("Can't map RTC registers"); 253 goto err; 254 } 255 256 reg = SUN6I_LOSC_CTRL_KEY; 257 if (rtc->data->has_auto_swt) { 258 /* Bypass auto-switch to int osc, on ext losc failure */ 259 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; 260 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 261 } 262 263 /* Switch to the external, more precise, oscillator, if present */ 264 if (of_property_present(node, "clocks")) { 265 reg |= SUN6I_LOSC_CTRL_EXT_OSC; 266 if (rtc->data->has_losc_en) 267 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; 268 } 269 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 270 271 /* Yes, I know, this is ugly. */ 272 sun6i_rtc = rtc; 273 274 of_property_read_string_index(node, "clock-output-names", 2, 275 &iosc_name); 276 277 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, 278 iosc_name, 279 NULL, 0, 280 rtc->data->rc_osc_rate, 281 300000000); 282 if (IS_ERR(rtc->int_osc)) { 283 pr_crit("Couldn't register the internal oscillator\n"); 284 goto err; 285 } 286 287 parents[0] = clk_hw_get_name(rtc->int_osc); 288 /* If there is no external oscillator, this will be NULL and ... */ 289 parents[1] = of_clk_get_parent_name(node, 0); 290 291 rtc->hw.init = &init; 292 293 init.parent_names = parents; 294 /* ... number of clock parents will be 1. */ 295 init.num_parents = of_clk_get_parent_count(node) + 1; 296 of_property_read_string_index(node, "clock-output-names", 0, 297 &init.name); 298 299 rtc->losc = clk_register(NULL, &rtc->hw); 300 if (IS_ERR(rtc->losc)) { 301 pr_crit("Couldn't register the LOSC clock\n"); 302 goto err_register; 303 } 304 305 of_property_read_string_index(node, "clock-output-names", 1, 306 &clkout_name); 307 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name, 308 0, rtc->base + SUN6I_LOSC_OUT_GATING, 309 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, 310 &rtc->lock); 311 if (IS_ERR(rtc->ext_losc)) { 312 pr_crit("Couldn't register the LOSC external gate\n"); 313 goto err_register; 314 } 315 316 clk_data->num = 3; 317 clk_data->hws[0] = &rtc->hw; 318 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); 319 clk_data->hws[2] = rtc->int_osc; 320 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 321 return; 322 323 err_register: 324 clk_hw_unregister_fixed_rate(rtc->int_osc); 325 err: 326 kfree(clk_data); 327 } 328 329 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { 330 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 331 .has_prescaler = 1, 332 }; 333 334 static void __init sun6i_a31_rtc_clk_init(struct device_node *node) 335 { 336 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); 337 } 338 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", 339 sun6i_a31_rtc_clk_init); 340 341 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { 342 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 343 .has_prescaler = 1, 344 .has_out_clk = 1, 345 }; 346 347 static void __init sun8i_a23_rtc_clk_init(struct device_node *node) 348 { 349 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); 350 } 351 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", 352 sun8i_a23_rtc_clk_init); 353 354 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { 355 .rc_osc_rate = 16000000, 356 .fixed_prescaler = 32, 357 .has_prescaler = 1, 358 .has_out_clk = 1, 359 }; 360 361 static void __init sun8i_h3_rtc_clk_init(struct device_node *node) 362 { 363 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); 364 } 365 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", 366 sun8i_h3_rtc_clk_init); 367 /* As far as we are concerned, clocks for H5 are the same as H3 */ 368 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", 369 sun8i_h3_rtc_clk_init); 370 371 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { 372 .rc_osc_rate = 16000000, 373 .fixed_prescaler = 32, 374 .has_prescaler = 1, 375 .has_out_clk = 1, 376 .has_losc_en = 1, 377 .has_auto_swt = 1, 378 }; 379 380 static void __init sun50i_h6_rtc_clk_init(struct device_node *node) 381 { 382 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); 383 } 384 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", 385 sun50i_h6_rtc_clk_init); 386 387 /* 388 * The R40 user manual is self-conflicting on whether the prescaler is 389 * fixed or configurable. The clock diagram shows it as fixed, but there 390 * is also a configurable divider in the RTC block. 391 */ 392 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = { 393 .rc_osc_rate = 16000000, 394 .fixed_prescaler = 512, 395 }; 396 static void __init sun8i_r40_rtc_clk_init(struct device_node *node) 397 { 398 sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data); 399 } 400 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc", 401 sun8i_r40_rtc_clk_init); 402 403 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { 404 .rc_osc_rate = 32000, 405 .has_out_clk = 1, 406 }; 407 408 static void __init sun8i_v3_rtc_clk_init(struct device_node *node) 409 { 410 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); 411 } 412 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", 413 sun8i_v3_rtc_clk_init); 414 415 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) 416 { 417 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; 418 irqreturn_t ret = IRQ_NONE; 419 u32 val; 420 421 spin_lock(&chip->lock); 422 val = readl(chip->base + SUN6I_ALRM_IRQ_STA); 423 424 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { 425 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; 426 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); 427 428 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); 429 430 ret = IRQ_HANDLED; 431 } 432 spin_unlock(&chip->lock); 433 434 return ret; 435 } 436 437 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) 438 { 439 u32 alrm_val = 0; 440 u32 alrm_irq_val = 0; 441 u32 alrm_wake_val = 0; 442 unsigned long flags; 443 444 if (to) { 445 alrm_val = SUN6I_ALRM_EN_CNT_EN; 446 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; 447 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; 448 } else { 449 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 450 chip->base + SUN6I_ALRM_IRQ_STA); 451 } 452 453 spin_lock_irqsave(&chip->lock, flags); 454 writel(alrm_val, chip->base + SUN6I_ALRM_EN); 455 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); 456 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); 457 spin_unlock_irqrestore(&chip->lock, flags); 458 } 459 460 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 461 { 462 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 463 u32 date, time; 464 465 /* 466 * read again in case it changes 467 */ 468 do { 469 date = readl(chip->base + SUN6I_RTC_YMD); 470 time = readl(chip->base + SUN6I_RTC_HMS); 471 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || 472 (time != readl(chip->base + SUN6I_RTC_HMS))); 473 474 if (chip->flags & RTC_LINEAR_DAY) { 475 /* 476 * Newer chips store a linear day number, the manual 477 * does not mandate any epoch base. The BSP driver uses 478 * the UNIX epoch, let's just copy that, as it's the 479 * easiest anyway. 480 */ 481 rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm); 482 } else { 483 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); 484 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1; 485 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); 486 487 /* 488 * switch from (data_year->min)-relative offset to 489 * a (1900)-relative one 490 */ 491 rtc_tm->tm_year += SUN6I_YEAR_OFF; 492 } 493 494 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); 495 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); 496 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); 497 498 return 0; 499 } 500 501 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 502 { 503 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 504 unsigned long flags; 505 u32 alrm_st; 506 u32 alrm_en; 507 508 spin_lock_irqsave(&chip->lock, flags); 509 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); 510 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); 511 spin_unlock_irqrestore(&chip->lock, flags); 512 513 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); 514 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); 515 rtc_time64_to_tm(chip->alarm, &wkalrm->time); 516 517 return 0; 518 } 519 520 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 521 { 522 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 523 struct rtc_time *alrm_tm = &wkalrm->time; 524 struct rtc_time tm_now; 525 time64_t time_set; 526 u32 counter_val, counter_val_hms; 527 int ret; 528 529 time_set = rtc_tm_to_time64(alrm_tm); 530 531 if (chip->flags & RTC_LINEAR_DAY) { 532 /* 533 * The alarm registers hold the actual alarm time, encoded 534 * in the same way (linear day + HMS) as the current time. 535 */ 536 counter_val_hms = SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec) | 537 SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min) | 538 SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour); 539 /* The division will cut off the H:M:S part of alrm_tm. */ 540 counter_val = div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY); 541 } else { 542 /* The alarm register holds the number of seconds left. */ 543 time64_t time_now; 544 545 ret = sun6i_rtc_gettime(dev, &tm_now); 546 if (ret < 0) { 547 dev_err(dev, "Error in getting time\n"); 548 return -EINVAL; 549 } 550 551 time_now = rtc_tm_to_time64(&tm_now); 552 if (time_set <= time_now) { 553 dev_err(dev, "Date to set in the past\n"); 554 return -EINVAL; 555 } 556 if ((time_set - time_now) > U32_MAX) { 557 dev_err(dev, "Date too far in the future\n"); 558 return -EINVAL; 559 } 560 561 counter_val = time_set - time_now; 562 } 563 564 sun6i_rtc_setaie(0, chip); 565 writel(0, chip->base + SUN6I_ALRM_COUNTER); 566 if (chip->flags & RTC_LINEAR_DAY) 567 writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS); 568 usleep_range(100, 300); 569 570 writel(counter_val, chip->base + SUN6I_ALRM_COUNTER); 571 if (chip->flags & RTC_LINEAR_DAY) 572 writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS); 573 chip->alarm = time_set; 574 575 sun6i_rtc_setaie(wkalrm->enabled, chip); 576 577 return 0; 578 } 579 580 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, 581 unsigned int mask, unsigned int ms_timeout) 582 { 583 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); 584 u32 reg; 585 586 do { 587 reg = readl(chip->base + offset); 588 reg &= mask; 589 590 if (!reg) 591 return 0; 592 593 } while (time_before(jiffies, timeout)); 594 595 return -ETIMEDOUT; 596 } 597 598 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) 599 { 600 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 601 u32 date = 0; 602 u32 time = 0; 603 604 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | 605 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | 606 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); 607 608 if (chip->flags & RTC_LINEAR_DAY) { 609 /* The division will cut off the H:M:S part of rtc_tm. */ 610 date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY); 611 } else { 612 rtc_tm->tm_year -= SUN6I_YEAR_OFF; 613 rtc_tm->tm_mon += 1; 614 615 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | 616 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | 617 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); 618 619 if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) 620 date |= SUN6I_LEAP_SET_VALUE(1); 621 } 622 623 /* Check whether registers are writable */ 624 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 625 SUN6I_LOSC_CTRL_ACC_MASK, 50)) { 626 dev_err(dev, "rtc is still busy.\n"); 627 return -EBUSY; 628 } 629 630 writel(time, chip->base + SUN6I_RTC_HMS); 631 632 /* 633 * After writing the RTC HH-MM-SS register, the 634 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not 635 * be cleared until the real writing operation is finished 636 */ 637 638 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 639 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { 640 dev_err(dev, "Failed to set rtc time.\n"); 641 return -ETIMEDOUT; 642 } 643 644 writel(date, chip->base + SUN6I_RTC_YMD); 645 646 /* 647 * After writing the RTC YY-MM-DD register, the 648 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not 649 * be cleared until the real writing operation is finished 650 */ 651 652 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 653 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { 654 dev_err(dev, "Failed to set rtc time.\n"); 655 return -ETIMEDOUT; 656 } 657 658 return 0; 659 } 660 661 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 662 { 663 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 664 665 if (!enabled) 666 sun6i_rtc_setaie(enabled, chip); 667 668 return 0; 669 } 670 671 static const struct rtc_class_ops sun6i_rtc_ops = { 672 .read_time = sun6i_rtc_gettime, 673 .set_time = sun6i_rtc_settime, 674 .read_alarm = sun6i_rtc_getalarm, 675 .set_alarm = sun6i_rtc_setalarm, 676 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable 677 }; 678 679 static int sun6i_rtc_nvmem_read(void *priv, unsigned int offset, void *_val, size_t bytes) 680 { 681 struct sun6i_rtc_dev *chip = priv; 682 u32 *val = _val; 683 int i; 684 685 for (i = 0; i < bytes / 4; ++i) 686 val[i] = readl(chip->base + SUN6I_GP_DATA + offset + 4 * i); 687 688 return 0; 689 } 690 691 static int sun6i_rtc_nvmem_write(void *priv, unsigned int offset, void *_val, size_t bytes) 692 { 693 struct sun6i_rtc_dev *chip = priv; 694 u32 *val = _val; 695 int i; 696 697 for (i = 0; i < bytes / 4; ++i) 698 writel(val[i], chip->base + SUN6I_GP_DATA + offset + 4 * i); 699 700 return 0; 701 } 702 703 static struct nvmem_config sun6i_rtc_nvmem_cfg = { 704 .type = NVMEM_TYPE_BATTERY_BACKED, 705 .reg_read = sun6i_rtc_nvmem_read, 706 .reg_write = sun6i_rtc_nvmem_write, 707 .size = SUN6I_GP_DATA_SIZE, 708 .word_size = 4, 709 .stride = 4, 710 }; 711 712 #ifdef CONFIG_PM_SLEEP 713 /* Enable IRQ wake on suspend, to wake up from RTC. */ 714 static int sun6i_rtc_suspend(struct device *dev) 715 { 716 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 717 718 if (device_may_wakeup(dev)) 719 enable_irq_wake(chip->irq); 720 721 return 0; 722 } 723 724 /* Disable IRQ wake on resume. */ 725 static int sun6i_rtc_resume(struct device *dev) 726 { 727 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 728 729 if (device_may_wakeup(dev)) 730 disable_irq_wake(chip->irq); 731 732 return 0; 733 } 734 #endif 735 736 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, 737 sun6i_rtc_suspend, sun6i_rtc_resume); 738 739 static void sun6i_rtc_bus_clk_cleanup(void *data) 740 { 741 struct clk *bus_clk = data; 742 743 clk_disable_unprepare(bus_clk); 744 } 745 746 static int sun6i_rtc_probe(struct platform_device *pdev) 747 { 748 struct sun6i_rtc_dev *chip = sun6i_rtc; 749 struct device *dev = &pdev->dev; 750 struct clk *bus_clk; 751 int ret; 752 753 bus_clk = devm_clk_get_optional(dev, "bus"); 754 if (IS_ERR(bus_clk)) 755 return PTR_ERR(bus_clk); 756 757 if (bus_clk) { 758 ret = clk_prepare_enable(bus_clk); 759 if (ret) 760 return ret; 761 762 ret = devm_add_action_or_reset(dev, sun6i_rtc_bus_clk_cleanup, 763 bus_clk); 764 if (ret) 765 return ret; 766 } 767 768 if (!chip) { 769 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 770 if (!chip) 771 return -ENOMEM; 772 773 spin_lock_init(&chip->lock); 774 775 chip->base = devm_platform_ioremap_resource(pdev, 0); 776 if (IS_ERR(chip->base)) 777 return PTR_ERR(chip->base); 778 779 if (IS_REACHABLE(CONFIG_SUN6I_RTC_CCU)) { 780 ret = sun6i_rtc_ccu_probe(dev, chip->base); 781 if (ret) 782 return ret; 783 } 784 } 785 786 platform_set_drvdata(pdev, chip); 787 788 chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev); 789 790 chip->irq = platform_get_irq(pdev, 0); 791 if (chip->irq < 0) 792 return chip->irq; 793 794 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, 795 0, dev_name(&pdev->dev), chip); 796 if (ret) { 797 dev_err(&pdev->dev, "Could not request IRQ\n"); 798 return ret; 799 } 800 801 /* clear the alarm counter value */ 802 writel(0, chip->base + SUN6I_ALRM_COUNTER); 803 804 /* disable counter alarm */ 805 writel(0, chip->base + SUN6I_ALRM_EN); 806 807 /* disable counter alarm interrupt */ 808 writel(0, chip->base + SUN6I_ALRM_IRQ_EN); 809 810 /* disable week alarm */ 811 writel(0, chip->base + SUN6I_ALRM1_EN); 812 813 /* disable week alarm interrupt */ 814 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); 815 816 /* clear counter alarm pending interrupts */ 817 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 818 chip->base + SUN6I_ALRM_IRQ_STA); 819 820 /* clear week alarm pending interrupts */ 821 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, 822 chip->base + SUN6I_ALRM1_IRQ_STA); 823 824 /* disable alarm wakeup */ 825 writel(0, chip->base + SUN6I_ALARM_CONFIG); 826 827 clk_prepare_enable(chip->losc); 828 829 device_init_wakeup(&pdev->dev, 1); 830 831 chip->rtc = devm_rtc_allocate_device(&pdev->dev); 832 if (IS_ERR(chip->rtc)) 833 return PTR_ERR(chip->rtc); 834 835 chip->rtc->ops = &sun6i_rtc_ops; 836 if (chip->flags & RTC_LINEAR_DAY) 837 chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1; 838 else 839 chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ 840 841 ret = devm_rtc_register_device(chip->rtc); 842 if (ret) 843 return ret; 844 845 sun6i_rtc_nvmem_cfg.priv = chip; 846 ret = devm_rtc_nvmem_register(chip->rtc, &sun6i_rtc_nvmem_cfg); 847 if (ret) 848 return ret; 849 850 dev_info(&pdev->dev, "RTC enabled\n"); 851 852 return 0; 853 } 854 855 /* 856 * As far as RTC functionality goes, all models are the same. The 857 * datasheets claim that different models have different number of 858 * registers available for non-volatile storage, but experiments show 859 * that all SoCs have 16 registers available for this purpose. 860 */ 861 static const struct of_device_id sun6i_rtc_dt_ids[] = { 862 { .compatible = "allwinner,sun6i-a31-rtc" }, 863 { .compatible = "allwinner,sun8i-a23-rtc" }, 864 { .compatible = "allwinner,sun8i-h3-rtc" }, 865 { .compatible = "allwinner,sun8i-r40-rtc" }, 866 { .compatible = "allwinner,sun8i-v3-rtc" }, 867 { .compatible = "allwinner,sun50i-h5-rtc" }, 868 { .compatible = "allwinner,sun50i-h6-rtc" }, 869 { .compatible = "allwinner,sun50i-h616-rtc", 870 .data = (void *)RTC_LINEAR_DAY }, 871 { .compatible = "allwinner,sun50i-r329-rtc", 872 .data = (void *)RTC_LINEAR_DAY }, 873 { /* sentinel */ }, 874 }; 875 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); 876 877 static struct platform_driver sun6i_rtc_driver = { 878 .probe = sun6i_rtc_probe, 879 .driver = { 880 .name = "sun6i-rtc", 881 .of_match_table = sun6i_rtc_dt_ids, 882 .pm = &sun6i_rtc_pm_ops, 883 }, 884 }; 885 builtin_platform_driver(sun6i_rtc_driver); 886