1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * An RTC driver for Allwinner A31/A23 4 * 5 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org> 6 * 7 * based on rtc-sunxi.c 8 * 9 * An RTC driver for Allwinner A10/A20 10 * 11 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/clk/sunxi-ng.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/fs.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/platform_device.h> 28 #include <linux/rtc.h> 29 #include <linux/slab.h> 30 #include <linux/types.h> 31 32 /* Control register */ 33 #define SUN6I_LOSC_CTRL 0x0000 34 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16) 35 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15) 36 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9) 37 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8) 38 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7) 39 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4) 40 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0) 41 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7) 42 43 #define SUN6I_LOSC_CLK_PRESCAL 0x0008 44 45 /* RTC */ 46 #define SUN6I_RTC_YMD 0x0010 47 #define SUN6I_RTC_HMS 0x0014 48 49 /* Alarm 0 (counter) */ 50 #define SUN6I_ALRM_COUNTER 0x0020 51 /* This holds the remaining alarm seconds on older SoCs (current value) */ 52 #define SUN6I_ALRM_COUNTER_HMS 0x0024 53 #define SUN6I_ALRM_EN 0x0028 54 #define SUN6I_ALRM_EN_CNT_EN BIT(0) 55 #define SUN6I_ALRM_IRQ_EN 0x002c 56 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) 57 #define SUN6I_ALRM_IRQ_STA 0x0030 58 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) 59 60 /* Alarm 1 (wall clock) */ 61 #define SUN6I_ALRM1_EN 0x0044 62 #define SUN6I_ALRM1_IRQ_EN 0x0048 63 #define SUN6I_ALRM1_IRQ_STA 0x004c 64 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0) 65 66 /* Alarm config */ 67 #define SUN6I_ALARM_CONFIG 0x0050 68 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0) 69 70 #define SUN6I_LOSC_OUT_GATING 0x0060 71 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0 72 73 /* General-purpose data */ 74 #define SUN6I_GP_DATA 0x0100 75 #define SUN6I_GP_DATA_SIZE 0x20 76 77 /* 78 * Get date values 79 */ 80 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f) 81 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) 82 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16) 83 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22) 84 85 /* 86 * Get time values 87 */ 88 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f) 89 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) 90 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) 91 92 /* 93 * Set date values 94 */ 95 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f) 96 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00) 97 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000) 98 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000) 99 100 /* 101 * Set time values 102 */ 103 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f) 104 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00) 105 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000) 106 107 /* 108 * The year parameter passed to the driver is usually an offset relative to 109 * the year 1900. This macro is used to convert this offset to another one 110 * relative to the minimum year allowed by the hardware. 111 * 112 * The year range is 1970 - 2033. This range is selected to match Allwinner's 113 * driver, even though it is somewhat limited. 114 */ 115 #define SUN6I_YEAR_MIN 1970 116 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900) 117 118 #define SECS_PER_DAY (24 * 3600ULL) 119 120 /* 121 * There are other differences between models, including: 122 * 123 * - number of GPIO pins that can be configured to hold a certain level 124 * - crypto-key related registers (H5, H6) 125 * - boot process related (super standby, secondary processor entry address) 126 * registers (R40, H6) 127 * - SYS power domain controls (R40) 128 * - DCXO controls (H6) 129 * - RC oscillator calibration (H6) 130 * 131 * These functions are not covered by this driver. 132 */ 133 struct sun6i_rtc_clk_data { 134 unsigned long rc_osc_rate; 135 unsigned int fixed_prescaler : 16; 136 unsigned int has_prescaler : 1; 137 unsigned int has_out_clk : 1; 138 unsigned int has_losc_en : 1; 139 unsigned int has_auto_swt : 1; 140 }; 141 142 #define RTC_LINEAR_DAY BIT(0) 143 144 struct sun6i_rtc_dev { 145 struct rtc_device *rtc; 146 const struct sun6i_rtc_clk_data *data; 147 void __iomem *base; 148 int irq; 149 time64_t alarm; 150 unsigned long flags; 151 152 struct clk_hw hw; 153 struct clk_hw *int_osc; 154 struct clk *losc; 155 struct clk *ext_losc; 156 157 spinlock_t lock; 158 }; 159 160 static struct sun6i_rtc_dev *sun6i_rtc; 161 162 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, 163 unsigned long parent_rate) 164 { 165 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 166 u32 val = 0; 167 168 val = readl(rtc->base + SUN6I_LOSC_CTRL); 169 if (val & SUN6I_LOSC_CTRL_EXT_OSC) 170 return parent_rate; 171 172 if (rtc->data->fixed_prescaler) 173 parent_rate /= rtc->data->fixed_prescaler; 174 175 if (rtc->data->has_prescaler) { 176 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL); 177 val &= GENMASK(4, 0); 178 } 179 180 return parent_rate / (val + 1); 181 } 182 183 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) 184 { 185 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 186 187 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC; 188 } 189 190 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) 191 { 192 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw); 193 unsigned long flags; 194 u32 val; 195 196 if (index > 1) 197 return -EINVAL; 198 199 spin_lock_irqsave(&rtc->lock, flags); 200 val = readl(rtc->base + SUN6I_LOSC_CTRL); 201 val &= ~SUN6I_LOSC_CTRL_EXT_OSC; 202 val |= SUN6I_LOSC_CTRL_KEY; 203 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0; 204 if (rtc->data->has_losc_en) { 205 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN; 206 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0; 207 } 208 writel(val, rtc->base + SUN6I_LOSC_CTRL); 209 spin_unlock_irqrestore(&rtc->lock, flags); 210 211 return 0; 212 } 213 214 static const struct clk_ops sun6i_rtc_osc_ops = { 215 .recalc_rate = sun6i_rtc_osc_recalc_rate, 216 .determine_rate = clk_hw_determine_rate_no_reparent, 217 218 .get_parent = sun6i_rtc_osc_get_parent, 219 .set_parent = sun6i_rtc_osc_set_parent, 220 }; 221 222 static void __init sun6i_rtc_clk_init(struct device_node *node, 223 const struct sun6i_rtc_clk_data *data) 224 { 225 struct clk_hw_onecell_data *clk_data; 226 struct sun6i_rtc_dev *rtc; 227 struct clk_init_data init = { 228 .ops = &sun6i_rtc_osc_ops, 229 .name = "losc", 230 }; 231 const char *iosc_name = "rtc-int-osc"; 232 const char *clkout_name = "osc32k-out"; 233 const char *parents[2]; 234 struct resource res; 235 u32 reg; 236 237 rtc = kzalloc_obj(*rtc); 238 if (!rtc) 239 return; 240 241 rtc->data = data; 242 clk_data = kzalloc_flex(*clk_data, hws, 3); 243 if (!clk_data) { 244 kfree(rtc); 245 return; 246 } 247 248 spin_lock_init(&rtc->lock); 249 250 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node)); 251 if (IS_ERR(rtc->base)) { 252 pr_crit("Can't map RTC registers"); 253 goto err; 254 } 255 256 reg = SUN6I_LOSC_CTRL_KEY; 257 if (rtc->data->has_auto_swt) { 258 /* Bypass auto-switch to int osc, on ext losc failure */ 259 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS; 260 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 261 } 262 263 /* Switch to the external, more precise, oscillator, if present */ 264 if (of_property_present(node, "clocks")) { 265 reg |= SUN6I_LOSC_CTRL_EXT_OSC; 266 if (rtc->data->has_losc_en) 267 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN; 268 } 269 writel(reg, rtc->base + SUN6I_LOSC_CTRL); 270 271 of_property_read_string_index(node, "clock-output-names", 2, 272 &iosc_name); 273 274 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL, 275 iosc_name, 276 NULL, 0, 277 rtc->data->rc_osc_rate, 278 300000000); 279 if (IS_ERR(rtc->int_osc)) { 280 pr_crit("Couldn't register the internal oscillator\n"); 281 goto err_unmap; 282 } 283 284 parents[0] = clk_hw_get_name(rtc->int_osc); 285 /* If there is no external oscillator, this will be NULL and ... */ 286 parents[1] = of_clk_get_parent_name(node, 0); 287 288 rtc->hw.init = &init; 289 290 init.parent_names = parents; 291 /* ... number of clock parents will be 1. */ 292 init.num_parents = of_clk_get_parent_count(node) + 1; 293 of_property_read_string_index(node, "clock-output-names", 0, 294 &init.name); 295 296 rtc->losc = clk_register(NULL, &rtc->hw); 297 if (IS_ERR(rtc->losc)) { 298 pr_crit("Couldn't register the LOSC clock\n"); 299 goto err_register; 300 } 301 302 of_property_read_string_index(node, "clock-output-names", 1, 303 &clkout_name); 304 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name, 305 0, rtc->base + SUN6I_LOSC_OUT_GATING, 306 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0, 307 &rtc->lock); 308 if (IS_ERR(rtc->ext_losc)) { 309 pr_crit("Couldn't register the LOSC external gate\n"); 310 goto err_losc; 311 } 312 313 clk_data->num = 3; 314 clk_data->hws[0] = &rtc->hw; 315 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc); 316 clk_data->hws[2] = rtc->int_osc; 317 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 318 319 /* Yes, I know, this is ugly. */ 320 sun6i_rtc = rtc; 321 return; 322 323 err_losc: 324 clk_unregister(rtc->losc); 325 err_register: 326 clk_hw_unregister_fixed_rate(rtc->int_osc); 327 err_unmap: 328 iounmap(rtc->base); 329 of_address_to_resource(node, 0, &res); 330 release_mem_region(res.start, resource_size(&res)); 331 err: 332 kfree(clk_data); 333 kfree(rtc); 334 } 335 336 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = { 337 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 338 .has_prescaler = 1, 339 }; 340 341 static void __init sun6i_a31_rtc_clk_init(struct device_node *node) 342 { 343 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data); 344 } 345 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", 346 sun6i_a31_rtc_clk_init); 347 348 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = { 349 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */ 350 .has_prescaler = 1, 351 .has_out_clk = 1, 352 }; 353 354 static void __init sun8i_a23_rtc_clk_init(struct device_node *node) 355 { 356 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data); 357 } 358 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", 359 sun8i_a23_rtc_clk_init); 360 361 /* The B288 RTC clocks are the same as the A23's */ 362 CLK_OF_DECLARE_DRIVER(sun8i_b288_rtc_clk, "allwinner,sun8i-b288-rtc", 363 sun8i_a23_rtc_clk_init); 364 365 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = { 366 .rc_osc_rate = 16000000, 367 .fixed_prescaler = 32, 368 .has_prescaler = 1, 369 .has_out_clk = 1, 370 }; 371 372 static void __init sun8i_h3_rtc_clk_init(struct device_node *node) 373 { 374 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data); 375 } 376 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", 377 sun8i_h3_rtc_clk_init); 378 /* As far as we are concerned, clocks for H5 are the same as H3 */ 379 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", 380 sun8i_h3_rtc_clk_init); 381 382 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = { 383 .rc_osc_rate = 16000000, 384 .fixed_prescaler = 32, 385 .has_prescaler = 1, 386 .has_out_clk = 1, 387 .has_losc_en = 1, 388 .has_auto_swt = 1, 389 }; 390 391 static void __init sun50i_h6_rtc_clk_init(struct device_node *node) 392 { 393 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data); 394 } 395 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", 396 sun50i_h6_rtc_clk_init); 397 398 /* 399 * The R40 user manual is self-conflicting on whether the prescaler is 400 * fixed or configurable. The clock diagram shows it as fixed, but there 401 * is also a configurable divider in the RTC block. 402 */ 403 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = { 404 .rc_osc_rate = 16000000, 405 .fixed_prescaler = 512, 406 }; 407 static void __init sun8i_r40_rtc_clk_init(struct device_node *node) 408 { 409 sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data); 410 } 411 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc", 412 sun8i_r40_rtc_clk_init); 413 414 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = { 415 .rc_osc_rate = 32000, 416 .has_out_clk = 1, 417 .has_auto_swt = 1, 418 }; 419 420 static void __init sun8i_v3_rtc_clk_init(struct device_node *node) 421 { 422 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data); 423 } 424 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", 425 sun8i_v3_rtc_clk_init); 426 427 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) 428 { 429 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id; 430 irqreturn_t ret = IRQ_NONE; 431 u32 val; 432 433 spin_lock(&chip->lock); 434 val = readl(chip->base + SUN6I_ALRM_IRQ_STA); 435 436 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) { 437 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND; 438 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); 439 440 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); 441 442 ret = IRQ_HANDLED; 443 } 444 spin_unlock(&chip->lock); 445 446 return ret; 447 } 448 449 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) 450 { 451 u32 alrm_val = 0; 452 u32 alrm_irq_val = 0; 453 u32 alrm_wake_val = 0; 454 unsigned long flags; 455 456 if (to) { 457 alrm_val = SUN6I_ALRM_EN_CNT_EN; 458 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN; 459 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP; 460 } else { 461 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 462 chip->base + SUN6I_ALRM_IRQ_STA); 463 } 464 465 spin_lock_irqsave(&chip->lock, flags); 466 writel(alrm_val, chip->base + SUN6I_ALRM_EN); 467 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); 468 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); 469 spin_unlock_irqrestore(&chip->lock, flags); 470 } 471 472 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 473 { 474 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 475 u32 date, time; 476 477 /* 478 * read again in case it changes 479 */ 480 do { 481 date = readl(chip->base + SUN6I_RTC_YMD); 482 time = readl(chip->base + SUN6I_RTC_HMS); 483 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) || 484 (time != readl(chip->base + SUN6I_RTC_HMS))); 485 486 if (chip->flags & RTC_LINEAR_DAY) { 487 /* 488 * Newer chips store a linear day number, the manual 489 * does not mandate any epoch base. The BSP driver uses 490 * the UNIX epoch, let's just copy that, as it's the 491 * easiest anyway. 492 */ 493 rtc_time64_to_tm((date & 0xffff) * SECS_PER_DAY, rtc_tm); 494 } else { 495 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date); 496 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1; 497 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date); 498 499 /* 500 * switch from (data_year->min)-relative offset to 501 * a (1900)-relative one 502 */ 503 rtc_tm->tm_year += SUN6I_YEAR_OFF; 504 } 505 506 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time); 507 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time); 508 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time); 509 510 return 0; 511 } 512 513 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 514 { 515 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 516 unsigned long flags; 517 u32 alrm_st; 518 u32 alrm_en; 519 520 spin_lock_irqsave(&chip->lock, flags); 521 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN); 522 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA); 523 spin_unlock_irqrestore(&chip->lock, flags); 524 525 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN); 526 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN); 527 rtc_time64_to_tm(chip->alarm, &wkalrm->time); 528 529 return 0; 530 } 531 532 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) 533 { 534 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 535 struct rtc_time *alrm_tm = &wkalrm->time; 536 struct rtc_time tm_now; 537 time64_t time_set; 538 u32 counter_val, counter_val_hms; 539 int ret; 540 541 time_set = rtc_tm_to_time64(alrm_tm); 542 543 if (chip->flags & RTC_LINEAR_DAY) { 544 /* 545 * The alarm registers hold the actual alarm time, encoded 546 * in the same way (linear day + HMS) as the current time. 547 */ 548 counter_val_hms = SUN6I_TIME_SET_SEC_VALUE(alrm_tm->tm_sec) | 549 SUN6I_TIME_SET_MIN_VALUE(alrm_tm->tm_min) | 550 SUN6I_TIME_SET_HOUR_VALUE(alrm_tm->tm_hour); 551 /* The division will cut off the H:M:S part of alrm_tm. */ 552 counter_val = div_u64(rtc_tm_to_time64(alrm_tm), SECS_PER_DAY); 553 } else { 554 /* The alarm register holds the number of seconds left. */ 555 time64_t time_now; 556 557 ret = sun6i_rtc_gettime(dev, &tm_now); 558 if (ret < 0) { 559 dev_err(dev, "Error in getting time\n"); 560 return -EINVAL; 561 } 562 563 time_now = rtc_tm_to_time64(&tm_now); 564 if (time_set <= time_now) { 565 dev_err(dev, "Date to set in the past\n"); 566 return -EINVAL; 567 } 568 if ((time_set - time_now) > U32_MAX) { 569 dev_err(dev, "Date too far in the future\n"); 570 return -EINVAL; 571 } 572 573 counter_val = time_set - time_now; 574 } 575 576 sun6i_rtc_setaie(0, chip); 577 writel(0, chip->base + SUN6I_ALRM_COUNTER); 578 if (chip->flags & RTC_LINEAR_DAY) 579 writel(0, chip->base + SUN6I_ALRM_COUNTER_HMS); 580 usleep_range(100, 300); 581 582 writel(counter_val, chip->base + SUN6I_ALRM_COUNTER); 583 if (chip->flags & RTC_LINEAR_DAY) 584 writel(counter_val_hms, chip->base + SUN6I_ALRM_COUNTER_HMS); 585 chip->alarm = time_set; 586 587 sun6i_rtc_setaie(wkalrm->enabled, chip); 588 589 return 0; 590 } 591 592 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, 593 unsigned int mask, unsigned int ms_timeout) 594 { 595 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); 596 u32 reg; 597 598 do { 599 reg = readl(chip->base + offset); 600 reg &= mask; 601 602 if (!reg) 603 return 0; 604 605 } while (time_before(jiffies, timeout)); 606 607 return -ETIMEDOUT; 608 } 609 610 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) 611 { 612 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 613 u32 date = 0; 614 u32 time = 0; 615 616 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | 617 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | 618 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); 619 620 if (chip->flags & RTC_LINEAR_DAY) { 621 /* The division will cut off the H:M:S part of rtc_tm. */ 622 date = div_u64(rtc_tm_to_time64(rtc_tm), SECS_PER_DAY); 623 } else { 624 rtc_tm->tm_year -= SUN6I_YEAR_OFF; 625 rtc_tm->tm_mon += 1; 626 627 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | 628 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | 629 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year); 630 631 if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN)) 632 date |= SUN6I_LEAP_SET_VALUE(1); 633 } 634 635 /* Check whether registers are writable */ 636 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 637 SUN6I_LOSC_CTRL_ACC_MASK, 50)) { 638 dev_err(dev, "rtc is still busy.\n"); 639 return -EBUSY; 640 } 641 642 writel(time, chip->base + SUN6I_RTC_HMS); 643 644 /* 645 * After writing the RTC HH-MM-SS register, the 646 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not 647 * be cleared until the real writing operation is finished 648 */ 649 650 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 651 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) { 652 dev_err(dev, "Failed to set rtc time.\n"); 653 return -ETIMEDOUT; 654 } 655 656 writel(date, chip->base + SUN6I_RTC_YMD); 657 658 /* 659 * After writing the RTC YY-MM-DD register, the 660 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not 661 * be cleared until the real writing operation is finished 662 */ 663 664 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL, 665 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) { 666 dev_err(dev, "Failed to set rtc time.\n"); 667 return -ETIMEDOUT; 668 } 669 670 return 0; 671 } 672 673 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 674 { 675 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 676 677 if (!enabled) 678 sun6i_rtc_setaie(enabled, chip); 679 680 return 0; 681 } 682 683 static const struct rtc_class_ops sun6i_rtc_ops = { 684 .read_time = sun6i_rtc_gettime, 685 .set_time = sun6i_rtc_settime, 686 .read_alarm = sun6i_rtc_getalarm, 687 .set_alarm = sun6i_rtc_setalarm, 688 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable 689 }; 690 691 static int sun6i_rtc_nvmem_read(void *priv, unsigned int offset, void *_val, size_t bytes) 692 { 693 struct sun6i_rtc_dev *chip = priv; 694 u32 *val = _val; 695 int i; 696 697 for (i = 0; i < bytes / 4; ++i) 698 val[i] = readl(chip->base + SUN6I_GP_DATA + offset + 4 * i); 699 700 return 0; 701 } 702 703 static int sun6i_rtc_nvmem_write(void *priv, unsigned int offset, void *_val, size_t bytes) 704 { 705 struct sun6i_rtc_dev *chip = priv; 706 u32 *val = _val; 707 int i; 708 709 for (i = 0; i < bytes / 4; ++i) 710 writel(val[i], chip->base + SUN6I_GP_DATA + offset + 4 * i); 711 712 return 0; 713 } 714 715 static struct nvmem_config sun6i_rtc_nvmem_cfg = { 716 .type = NVMEM_TYPE_BATTERY_BACKED, 717 .reg_read = sun6i_rtc_nvmem_read, 718 .reg_write = sun6i_rtc_nvmem_write, 719 .size = SUN6I_GP_DATA_SIZE, 720 .word_size = 4, 721 .stride = 4, 722 }; 723 724 #ifdef CONFIG_PM_SLEEP 725 /* Enable IRQ wake on suspend, to wake up from RTC. */ 726 static int sun6i_rtc_suspend(struct device *dev) 727 { 728 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 729 730 if (device_may_wakeup(dev)) 731 enable_irq_wake(chip->irq); 732 733 return 0; 734 } 735 736 /* Disable IRQ wake on resume. */ 737 static int sun6i_rtc_resume(struct device *dev) 738 { 739 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev); 740 741 if (device_may_wakeup(dev)) 742 disable_irq_wake(chip->irq); 743 744 return 0; 745 } 746 #endif 747 748 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, 749 sun6i_rtc_suspend, sun6i_rtc_resume); 750 751 static void sun6i_rtc_bus_clk_cleanup(void *data) 752 { 753 struct clk *bus_clk = data; 754 755 clk_disable_unprepare(bus_clk); 756 } 757 758 static int sun6i_rtc_probe(struct platform_device *pdev) 759 { 760 struct sun6i_rtc_dev *chip = sun6i_rtc; 761 struct device *dev = &pdev->dev; 762 struct clk *bus_clk; 763 int ret; 764 765 bus_clk = devm_clk_get_optional(dev, "bus"); 766 if (IS_ERR(bus_clk)) 767 return PTR_ERR(bus_clk); 768 769 if (bus_clk) { 770 ret = clk_prepare_enable(bus_clk); 771 if (ret) 772 return ret; 773 774 ret = devm_add_action_or_reset(dev, sun6i_rtc_bus_clk_cleanup, 775 bus_clk); 776 if (ret) 777 return ret; 778 } 779 780 if (!chip) { 781 chip = devm_kzalloc_obj(&pdev->dev, *chip); 782 if (!chip) 783 return -ENOMEM; 784 785 spin_lock_init(&chip->lock); 786 787 chip->base = devm_platform_ioremap_resource(pdev, 0); 788 if (IS_ERR(chip->base)) 789 return PTR_ERR(chip->base); 790 791 if (IS_REACHABLE(CONFIG_SUN6I_RTC_CCU)) { 792 ret = sun6i_rtc_ccu_probe(dev, chip->base); 793 if (ret) 794 return ret; 795 } 796 } 797 798 platform_set_drvdata(pdev, chip); 799 800 chip->flags = (unsigned long)of_device_get_match_data(&pdev->dev); 801 802 chip->irq = platform_get_irq(pdev, 0); 803 if (chip->irq < 0) 804 return chip->irq; 805 806 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq, 807 0, dev_name(&pdev->dev), chip); 808 if (ret) { 809 dev_err(&pdev->dev, "Could not request IRQ\n"); 810 return ret; 811 } 812 813 /* clear the alarm counter value */ 814 writel(0, chip->base + SUN6I_ALRM_COUNTER); 815 816 /* disable counter alarm */ 817 writel(0, chip->base + SUN6I_ALRM_EN); 818 819 /* disable counter alarm interrupt */ 820 writel(0, chip->base + SUN6I_ALRM_IRQ_EN); 821 822 /* disable week alarm */ 823 writel(0, chip->base + SUN6I_ALRM1_EN); 824 825 /* disable week alarm interrupt */ 826 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); 827 828 /* clear counter alarm pending interrupts */ 829 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, 830 chip->base + SUN6I_ALRM_IRQ_STA); 831 832 /* clear week alarm pending interrupts */ 833 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, 834 chip->base + SUN6I_ALRM1_IRQ_STA); 835 836 /* disable alarm wakeup */ 837 writel(0, chip->base + SUN6I_ALARM_CONFIG); 838 839 clk_prepare_enable(chip->losc); 840 841 device_init_wakeup(&pdev->dev, true); 842 843 chip->rtc = devm_rtc_allocate_device(&pdev->dev); 844 if (IS_ERR(chip->rtc)) 845 return PTR_ERR(chip->rtc); 846 847 chip->rtc->ops = &sun6i_rtc_ops; 848 if (chip->flags & RTC_LINEAR_DAY) 849 chip->rtc->range_max = (65536 * SECS_PER_DAY) - 1; 850 else 851 chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */ 852 853 ret = devm_rtc_register_device(chip->rtc); 854 if (ret) 855 return ret; 856 857 sun6i_rtc_nvmem_cfg.priv = chip; 858 ret = devm_rtc_nvmem_register(chip->rtc, &sun6i_rtc_nvmem_cfg); 859 if (ret) 860 return ret; 861 862 return 0; 863 } 864 865 /* 866 * As far as RTC functionality goes, all models are the same. The 867 * datasheets claim that different models have different number of 868 * registers available for non-volatile storage, but experiments show 869 * that all SoCs have 16 registers available for this purpose. 870 */ 871 static const struct of_device_id sun6i_rtc_dt_ids[] = { 872 { .compatible = "allwinner,sun6i-a31-rtc" }, 873 { .compatible = "allwinner,sun8i-a23-rtc" }, 874 { .compatible = "allwinner,sun8i-b288-rtc" }, 875 { .compatible = "allwinner,sun8i-h3-rtc" }, 876 { .compatible = "allwinner,sun8i-r40-rtc" }, 877 { .compatible = "allwinner,sun8i-v3-rtc" }, 878 { .compatible = "allwinner,sun50i-h5-rtc" }, 879 { .compatible = "allwinner,sun50i-h6-rtc" }, 880 { .compatible = "allwinner,sun50i-h616-rtc", 881 .data = (void *)RTC_LINEAR_DAY }, 882 { .compatible = "allwinner,sun50i-r329-rtc", 883 .data = (void *)RTC_LINEAR_DAY }, 884 { /* sentinel */ }, 885 }; 886 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); 887 888 static struct platform_driver sun6i_rtc_driver = { 889 .probe = sun6i_rtc_probe, 890 .driver = { 891 .name = "sun6i-rtc", 892 .of_match_table = sun6i_rtc_dt_ids, 893 .pm = &sun6i_rtc_pm_ops, 894 }, 895 }; 896 builtin_platform_driver(sun6i_rtc_driver); 897