1 /* 2 * Freescale STMP37XX/STMP378X Real Time Clock driver 3 * 4 * Copyright (c) 2007 Sigmatel, Inc. 5 * Peter Hartley, <peter.hartley@sigmatel.com> 6 * 7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. 8 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 9 * Copyright 2011 Wolfram Sang, Pengutronix e.K. 10 */ 11 12 /* 13 * The code contained herein is licensed under the GNU General Public 14 * License. You may obtain a copy of the GNU General Public License 15 * Version 2 or later at the following locations: 16 * 17 * http://www.opensource.org/licenses/gpl-license.html 18 * http://www.gnu.org/copyleft/gpl.html 19 */ 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/io.h> 23 #include <linux/init.h> 24 #include <linux/platform_device.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/rtc.h> 28 #include <linux/slab.h> 29 #include <linux/of_device.h> 30 #include <linux/of.h> 31 #include <linux/stmp_device.h> 32 #include <linux/stmp3xxx_rtc_wdt.h> 33 34 #define STMP3XXX_RTC_CTRL 0x0 35 #define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001 36 #define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 37 #define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004 38 #define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010 39 40 #define STMP3XXX_RTC_STAT 0x10 41 #define STMP3XXX_RTC_STAT_STALE_SHIFT 16 42 #define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000 43 #define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000 44 #define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000 45 46 #define STMP3XXX_RTC_SECONDS 0x30 47 48 #define STMP3XXX_RTC_ALARM 0x40 49 50 #define STMP3XXX_RTC_WATCHDOG 0x50 51 52 #define STMP3XXX_RTC_PERSISTENT0 0x60 53 #define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) 54 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) 55 #define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2) 56 #define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4) 57 #define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) 58 #define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) 59 #define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7) 60 61 #define STMP3XXX_RTC_PERSISTENT1 0x70 62 /* missing bitmask in headers */ 63 #define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000 64 65 struct stmp3xxx_rtc_data { 66 struct rtc_device *rtc; 67 void __iomem *io; 68 int irq_alarm; 69 }; 70 71 #if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG) 72 /** 73 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC 74 * @dev: the parent device of the watchdog (= the RTC) 75 * @timeout: the desired value for the timeout register of the watchdog. 76 * 0 disables the watchdog 77 * 78 * The watchdog needs one register and two bits which are in the RTC domain. 79 * To handle the resource conflict, the RTC driver will create another 80 * platform_device for the watchdog driver as a child of the RTC device. 81 * The watchdog driver is passed the below accessor function via platform_data 82 * to configure the watchdog. Locking is not needed because accessing SET/CLR 83 * registers is atomic. 84 */ 85 86 static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout) 87 { 88 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 89 90 if (timeout) { 91 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG); 92 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, 93 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET); 94 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, 95 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET); 96 } else { 97 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, 98 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); 99 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, 100 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR); 101 } 102 } 103 104 static struct stmp3xxx_wdt_pdata wdt_pdata = { 105 .wdt_set_timeout = stmp3xxx_wdt_set_timeout, 106 }; 107 108 static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev) 109 { 110 int rc = -1; 111 struct platform_device *wdt_pdev = 112 platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id); 113 114 if (wdt_pdev) { 115 wdt_pdev->dev.parent = &rtc_pdev->dev; 116 wdt_pdev->dev.platform_data = &wdt_pdata; 117 rc = platform_device_add(wdt_pdev); 118 } 119 120 if (rc) 121 dev_err(&rtc_pdev->dev, 122 "failed to register stmp3xxx_rtc_wdt\n"); 123 } 124 #else 125 static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev) 126 { 127 } 128 #endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */ 129 130 static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data) 131 { 132 int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */ 133 /* 134 * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010 135 * states: 136 * | The order in which registers are updated is 137 * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds. 138 * | (This list is in bitfield order, from LSB to MSB, as they would 139 * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT 140 * | register. For example, the Seconds register corresponds to 141 * | STALE_REGS or NEW_REGS containing 0x80.) 142 */ 143 do { 144 if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) & 145 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT))) 146 return 0; 147 udelay(1); 148 } while (--timeout > 0); 149 return (readl(rtc_data->io + STMP3XXX_RTC_STAT) & 150 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0; 151 } 152 153 /* Time read/write */ 154 static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) 155 { 156 int ret; 157 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 158 159 ret = stmp3xxx_wait_time(rtc_data); 160 if (ret) 161 return ret; 162 163 rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm); 164 return 0; 165 } 166 167 static int stmp3xxx_rtc_set_mmss(struct device *dev, unsigned long t) 168 { 169 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 170 171 writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS); 172 return stmp3xxx_wait_time(rtc_data); 173 } 174 175 /* interrupt(s) handler */ 176 static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id) 177 { 178 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id); 179 u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL); 180 181 if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) { 182 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ, 183 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); 184 rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF); 185 return IRQ_HANDLED; 186 } 187 188 return IRQ_NONE; 189 } 190 191 static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled) 192 { 193 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 194 195 if (enabled) { 196 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | 197 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN, 198 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + 199 STMP_OFFSET_REG_SET); 200 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, 201 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET); 202 } else { 203 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | 204 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN, 205 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + 206 STMP_OFFSET_REG_CLR); 207 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, 208 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); 209 } 210 return 0; 211 } 212 213 static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm) 214 { 215 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 216 217 rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time); 218 return 0; 219 } 220 221 static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm) 222 { 223 unsigned long t; 224 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 225 226 rtc_tm_to_time(&alm->time, &t); 227 writel(t, rtc_data->io + STMP3XXX_RTC_ALARM); 228 229 stmp3xxx_alarm_irq_enable(dev, alm->enabled); 230 231 return 0; 232 } 233 234 static const struct rtc_class_ops stmp3xxx_rtc_ops = { 235 .alarm_irq_enable = 236 stmp3xxx_alarm_irq_enable, 237 .read_time = stmp3xxx_rtc_gettime, 238 .set_mmss = stmp3xxx_rtc_set_mmss, 239 .read_alarm = stmp3xxx_rtc_read_alarm, 240 .set_alarm = stmp3xxx_rtc_set_alarm, 241 }; 242 243 static int stmp3xxx_rtc_remove(struct platform_device *pdev) 244 { 245 struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev); 246 247 if (!rtc_data) 248 return 0; 249 250 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, 251 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); 252 253 return 0; 254 } 255 256 static int stmp3xxx_rtc_probe(struct platform_device *pdev) 257 { 258 struct stmp3xxx_rtc_data *rtc_data; 259 struct resource *r; 260 u32 rtc_stat; 261 u32 pers0_set, pers0_clr; 262 u32 crystalfreq = 0; 263 int err; 264 265 rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL); 266 if (!rtc_data) 267 return -ENOMEM; 268 269 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 270 if (!r) { 271 dev_err(&pdev->dev, "failed to get resource\n"); 272 return -ENXIO; 273 } 274 275 rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 276 if (!rtc_data->io) { 277 dev_err(&pdev->dev, "ioremap failed\n"); 278 return -EIO; 279 } 280 281 rtc_data->irq_alarm = platform_get_irq(pdev, 0); 282 283 rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT); 284 if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) { 285 dev_err(&pdev->dev, "no device onboard\n"); 286 return -ENODEV; 287 } 288 289 platform_set_drvdata(pdev, rtc_data); 290 291 /* 292 * Resetting the rtc stops the watchdog timer that is potentially 293 * running. So (assuming it is running on purpose) don't reset if the 294 * watchdog is enabled. 295 */ 296 if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) & 297 STMP3XXX_RTC_CTRL_WATCHDOGEN) { 298 dev_info(&pdev->dev, 299 "Watchdog is running, skip resetting rtc\n"); 300 } else { 301 err = stmp_reset_block(rtc_data->io); 302 if (err) { 303 dev_err(&pdev->dev, "stmp_reset_block failed: %d\n", 304 err); 305 return err; 306 } 307 } 308 309 /* 310 * Obviously the rtc needs a clock input to be able to run. 311 * This clock can be provided by an external 32k crystal. If that one is 312 * missing XTAL must not be disabled in suspend which consumes a 313 * lot of power. Normally the presence and exact frequency (supported 314 * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality 315 * proves these fuses are not blown correctly on all machines, so the 316 * frequency can be overridden in the device tree. 317 */ 318 if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT) 319 crystalfreq = 32000; 320 else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT) 321 crystalfreq = 32768; 322 323 of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq", 324 &crystalfreq); 325 326 switch (crystalfreq) { 327 case 32000: 328 /* keep 32kHz crystal running in low-power mode */ 329 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ | 330 STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP | 331 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE; 332 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP; 333 break; 334 case 32768: 335 /* keep 32.768kHz crystal running in low-power mode */ 336 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP | 337 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE; 338 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP | 339 STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ; 340 break; 341 default: 342 dev_warn(&pdev->dev, 343 "invalid crystal-freq specified in device-tree. Assuming no crystal\n"); 344 /* fall-through */ 345 case 0: 346 /* keep XTAL on in low-power mode */ 347 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP; 348 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP | 349 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE; 350 } 351 352 writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + 353 STMP_OFFSET_REG_SET); 354 355 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | 356 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN | 357 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr, 358 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR); 359 360 writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN | 361 STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, 362 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR); 363 364 rtc_data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, 365 &stmp3xxx_rtc_ops, THIS_MODULE); 366 if (IS_ERR(rtc_data->rtc)) 367 return PTR_ERR(rtc_data->rtc); 368 369 err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm, 370 stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev); 371 if (err) { 372 dev_err(&pdev->dev, "Cannot claim IRQ%d\n", 373 rtc_data->irq_alarm); 374 return err; 375 } 376 377 stmp3xxx_wdt_register(pdev); 378 return 0; 379 } 380 381 #ifdef CONFIG_PM_SLEEP 382 static int stmp3xxx_rtc_suspend(struct device *dev) 383 { 384 return 0; 385 } 386 387 static int stmp3xxx_rtc_resume(struct device *dev) 388 { 389 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 390 391 stmp_reset_block(rtc_data->io); 392 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | 393 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN | 394 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE, 395 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR); 396 return 0; 397 } 398 #endif 399 400 static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend, 401 stmp3xxx_rtc_resume); 402 403 static const struct of_device_id rtc_dt_ids[] = { 404 { .compatible = "fsl,stmp3xxx-rtc", }, 405 { /* sentinel */ } 406 }; 407 MODULE_DEVICE_TABLE(of, rtc_dt_ids); 408 409 static struct platform_driver stmp3xxx_rtcdrv = { 410 .probe = stmp3xxx_rtc_probe, 411 .remove = stmp3xxx_rtc_remove, 412 .driver = { 413 .name = "stmp3xxx-rtc", 414 .pm = &stmp3xxx_rtc_pm_ops, 415 .of_match_table = rtc_dt_ids, 416 }, 417 }; 418 419 module_platform_driver(stmp3xxx_rtcdrv); 420 421 MODULE_DESCRIPTION("STMP3xxx RTC Driver"); 422 MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and " 423 "Wolfram Sang <w.sang@pengutronix.de>"); 424 MODULE_LICENSE("GPL"); 425