1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2017 4 * Author: Amelie Delaunay <amelie.delaunay@st.com> 5 */ 6 7 #include <linux/bcd.h> 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/errno.h> 12 #include <linux/iopoll.h> 13 #include <linux/ioport.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 #include <linux/pinctrl/pinmux.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_wakeirq.h> 22 #include <linux/regmap.h> 23 #include <linux/rtc.h> 24 25 #define DRIVER_NAME "stm32_rtc" 26 27 /* STM32_RTC_TR bit fields */ 28 #define STM32_RTC_TR_SEC_SHIFT 0 29 #define STM32_RTC_TR_SEC GENMASK(6, 0) 30 #define STM32_RTC_TR_MIN_SHIFT 8 31 #define STM32_RTC_TR_MIN GENMASK(14, 8) 32 #define STM32_RTC_TR_HOUR_SHIFT 16 33 #define STM32_RTC_TR_HOUR GENMASK(21, 16) 34 35 /* STM32_RTC_DR bit fields */ 36 #define STM32_RTC_DR_DATE_SHIFT 0 37 #define STM32_RTC_DR_DATE GENMASK(5, 0) 38 #define STM32_RTC_DR_MONTH_SHIFT 8 39 #define STM32_RTC_DR_MONTH GENMASK(12, 8) 40 #define STM32_RTC_DR_WDAY_SHIFT 13 41 #define STM32_RTC_DR_WDAY GENMASK(15, 13) 42 #define STM32_RTC_DR_YEAR_SHIFT 16 43 #define STM32_RTC_DR_YEAR GENMASK(23, 16) 44 45 /* STM32_RTC_CR bit fields */ 46 #define STM32_RTC_CR_FMT BIT(6) 47 #define STM32_RTC_CR_ALRAE BIT(8) 48 #define STM32_RTC_CR_ALRAIE BIT(12) 49 #define STM32_RTC_CR_OSEL GENMASK(22, 21) 50 #define STM32_RTC_CR_OSEL_ALARM_A FIELD_PREP(STM32_RTC_CR_OSEL, 0x01) 51 #define STM32_RTC_CR_COE BIT(23) 52 #define STM32_RTC_CR_TAMPOE BIT(26) 53 #define STM32_RTC_CR_TAMPALRM_TYPE BIT(30) 54 #define STM32_RTC_CR_OUT2EN BIT(31) 55 56 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ 57 #define STM32_RTC_ISR_ALRAWF BIT(0) 58 #define STM32_RTC_ISR_INITS BIT(4) 59 #define STM32_RTC_ISR_RSF BIT(5) 60 #define STM32_RTC_ISR_INITF BIT(6) 61 #define STM32_RTC_ISR_INIT BIT(7) 62 #define STM32_RTC_ISR_ALRAF BIT(8) 63 64 /* STM32_RTC_PRER bit fields */ 65 #define STM32_RTC_PRER_PRED_S_SHIFT 0 66 #define STM32_RTC_PRER_PRED_S GENMASK(14, 0) 67 #define STM32_RTC_PRER_PRED_A_SHIFT 16 68 #define STM32_RTC_PRER_PRED_A GENMASK(22, 16) 69 70 /* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */ 71 #define STM32_RTC_ALRMXR_SEC_SHIFT 0 72 #define STM32_RTC_ALRMXR_SEC GENMASK(6, 0) 73 #define STM32_RTC_ALRMXR_SEC_MASK BIT(7) 74 #define STM32_RTC_ALRMXR_MIN_SHIFT 8 75 #define STM32_RTC_ALRMXR_MIN GENMASK(14, 8) 76 #define STM32_RTC_ALRMXR_MIN_MASK BIT(15) 77 #define STM32_RTC_ALRMXR_HOUR_SHIFT 16 78 #define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16) 79 #define STM32_RTC_ALRMXR_PM BIT(22) 80 #define STM32_RTC_ALRMXR_HOUR_MASK BIT(23) 81 #define STM32_RTC_ALRMXR_DATE_SHIFT 24 82 #define STM32_RTC_ALRMXR_DATE GENMASK(29, 24) 83 #define STM32_RTC_ALRMXR_WDSEL BIT(30) 84 #define STM32_RTC_ALRMXR_WDAY_SHIFT 24 85 #define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24) 86 #define STM32_RTC_ALRMXR_DATE_MASK BIT(31) 87 88 /* STM32_RTC_SR/_SCR bit fields */ 89 #define STM32_RTC_SR_ALRA BIT(0) 90 91 /* STM32_RTC_CFGR bit fields */ 92 #define STM32_RTC_CFGR_OUT2_RMP BIT(0) 93 #define STM32_RTC_CFGR_LSCOEN GENMASK(2, 1) 94 #define STM32_RTC_CFGR_LSCOEN_OUT1 1 95 #define STM32_RTC_CFGR_LSCOEN_OUT2_RMP 2 96 97 /* STM32_RTC_VERR bit fields */ 98 #define STM32_RTC_VERR_MINREV_SHIFT 0 99 #define STM32_RTC_VERR_MINREV GENMASK(3, 0) 100 #define STM32_RTC_VERR_MAJREV_SHIFT 4 101 #define STM32_RTC_VERR_MAJREV GENMASK(7, 4) 102 103 /* STM32_RTC_SECCFGR bit fields */ 104 #define STM32_RTC_SECCFGR 0x20 105 #define STM32_RTC_SECCFGR_ALRA_SEC BIT(0) 106 #define STM32_RTC_SECCFGR_INIT_SEC BIT(14) 107 #define STM32_RTC_SECCFGR_SEC BIT(15) 108 109 /* STM32_RTC_RXCIDCFGR bit fields */ 110 #define STM32_RTC_RXCIDCFGR(x) (0x80 + 0x4 * (x)) 111 #define STM32_RTC_RXCIDCFGR_CFEN BIT(0) 112 #define STM32_RTC_RXCIDCFGR_CID GENMASK(6, 4) 113 #define STM32_RTC_RXCIDCFGR_CID1 1 114 115 /* STM32_RTC_WPR key constants */ 116 #define RTC_WPR_1ST_KEY 0xCA 117 #define RTC_WPR_2ND_KEY 0x53 118 #define RTC_WPR_WRONG_KEY 0xFF 119 120 /* Max STM32 RTC register offset is 0x3FC */ 121 #define UNDEF_REG 0xFFFF 122 123 /* STM32 RTC driver time helpers */ 124 #define SEC_PER_DAY (24 * 60 * 60) 125 126 /* STM32 RTC pinctrl helpers */ 127 #define STM32_RTC_PINMUX(_name, _action, ...) { \ 128 .name = (_name), \ 129 .action = (_action), \ 130 .groups = ((const char *[]){ __VA_ARGS__ }), \ 131 .num_groups = ARRAY_SIZE(((const char *[]){ __VA_ARGS__ })), \ 132 } 133 134 struct stm32_rtc; 135 136 struct stm32_rtc_registers { 137 u16 tr; 138 u16 dr; 139 u16 cr; 140 u16 isr; 141 u16 prer; 142 u16 alrmar; 143 u16 wpr; 144 u16 sr; 145 u16 scr; 146 u16 cfgr; 147 u16 verr; 148 }; 149 150 struct stm32_rtc_events { 151 u32 alra; 152 }; 153 154 struct stm32_rtc_data { 155 const struct stm32_rtc_registers regs; 156 const struct stm32_rtc_events events; 157 void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags); 158 bool has_pclk; 159 bool need_dbp; 160 bool need_accuracy; 161 bool rif_protected; 162 bool has_lsco; 163 bool has_alarm_out; 164 }; 165 166 struct stm32_rtc { 167 struct rtc_device *rtc_dev; 168 void __iomem *base; 169 struct regmap *dbp; 170 unsigned int dbp_reg; 171 unsigned int dbp_mask; 172 struct clk *pclk; 173 struct clk *rtc_ck; 174 const struct stm32_rtc_data *data; 175 int irq_alarm; 176 struct clk *clk_lsco; 177 }; 178 179 struct stm32_rtc_rif_resource { 180 unsigned int num; 181 u32 bit; 182 }; 183 184 static const struct stm32_rtc_rif_resource STM32_RTC_RES_ALRA = {0, STM32_RTC_SECCFGR_ALRA_SEC}; 185 static const struct stm32_rtc_rif_resource STM32_RTC_RES_INIT = {5, STM32_RTC_SECCFGR_INIT_SEC}; 186 187 static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc) 188 { 189 const struct stm32_rtc_registers *regs = &rtc->data->regs; 190 191 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr); 192 writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr); 193 } 194 195 static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc) 196 { 197 const struct stm32_rtc_registers *regs = &rtc->data->regs; 198 199 writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); 200 } 201 202 enum stm32_rtc_pin_name { 203 NONE, 204 OUT1, 205 OUT2, 206 OUT2_RMP 207 }; 208 209 static const struct pinctrl_pin_desc stm32_rtc_pinctrl_pins[] = { 210 PINCTRL_PIN(OUT1, "out1"), 211 PINCTRL_PIN(OUT2, "out2"), 212 PINCTRL_PIN(OUT2_RMP, "out2_rmp"), 213 }; 214 215 static int stm32_rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 216 { 217 return ARRAY_SIZE(stm32_rtc_pinctrl_pins); 218 } 219 220 static const char *stm32_rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 221 unsigned int selector) 222 { 223 return stm32_rtc_pinctrl_pins[selector].name; 224 } 225 226 static int stm32_rtc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 227 unsigned int selector, 228 const unsigned int **pins, 229 unsigned int *num_pins) 230 { 231 *pins = &stm32_rtc_pinctrl_pins[selector].number; 232 *num_pins = 1; 233 return 0; 234 } 235 236 static const struct pinctrl_ops stm32_rtc_pinctrl_ops = { 237 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 238 .dt_free_map = pinconf_generic_dt_free_map, 239 .get_groups_count = stm32_rtc_pinctrl_get_groups_count, 240 .get_group_name = stm32_rtc_pinctrl_get_group_name, 241 .get_group_pins = stm32_rtc_pinctrl_get_group_pins, 242 }; 243 244 struct stm32_rtc_pinmux_func { 245 const char *name; 246 const char * const *groups; 247 const unsigned int num_groups; 248 int (*action)(struct pinctrl_dev *pctl_dev, unsigned int pin); 249 }; 250 251 static int stm32_rtc_pinmux_action_alarm(struct pinctrl_dev *pctldev, unsigned int pin) 252 { 253 struct stm32_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); 254 struct stm32_rtc_registers regs = rtc->data->regs; 255 unsigned int cr = readl_relaxed(rtc->base + regs.cr); 256 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); 257 258 if (!rtc->data->has_alarm_out) 259 return -EPERM; 260 261 cr &= ~STM32_RTC_CR_OSEL; 262 cr |= STM32_RTC_CR_OSEL_ALARM_A; 263 cr &= ~STM32_RTC_CR_TAMPOE; 264 cr &= ~STM32_RTC_CR_COE; 265 cr &= ~STM32_RTC_CR_TAMPALRM_TYPE; 266 267 switch (pin) { 268 case OUT1: 269 cr &= ~STM32_RTC_CR_OUT2EN; 270 cfgr &= ~STM32_RTC_CFGR_OUT2_RMP; 271 break; 272 case OUT2: 273 cr |= STM32_RTC_CR_OUT2EN; 274 cfgr &= ~STM32_RTC_CFGR_OUT2_RMP; 275 break; 276 case OUT2_RMP: 277 cr |= STM32_RTC_CR_OUT2EN; 278 cfgr |= STM32_RTC_CFGR_OUT2_RMP; 279 break; 280 default: 281 return -EINVAL; 282 } 283 284 stm32_rtc_wpr_unlock(rtc); 285 writel_relaxed(cr, rtc->base + regs.cr); 286 writel_relaxed(cfgr, rtc->base + regs.cfgr); 287 stm32_rtc_wpr_lock(rtc); 288 289 return 0; 290 } 291 292 static int stm32_rtc_pinmux_lsco_available(struct pinctrl_dev *pctldev, unsigned int pin) 293 { 294 struct stm32_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); 295 struct stm32_rtc_registers regs = rtc->data->regs; 296 unsigned int cr = readl_relaxed(rtc->base + regs.cr); 297 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); 298 unsigned int calib = STM32_RTC_CR_COE; 299 unsigned int tampalrm = STM32_RTC_CR_TAMPOE | STM32_RTC_CR_OSEL; 300 301 switch (pin) { 302 case OUT1: 303 if ((!(cr & STM32_RTC_CR_OUT2EN) && 304 ((cr & calib) || cr & tampalrm)) || 305 ((cr & calib) && (cr & tampalrm))) 306 return -EBUSY; 307 break; 308 case OUT2_RMP: 309 if ((cr & STM32_RTC_CR_OUT2EN) && 310 (cfgr & STM32_RTC_CFGR_OUT2_RMP) && 311 ((cr & calib) || (cr & tampalrm))) 312 return -EBUSY; 313 break; 314 default: 315 return -EINVAL; 316 } 317 318 if (clk_get_rate(rtc->rtc_ck) != 32768) 319 return -ERANGE; 320 321 return 0; 322 } 323 324 static int stm32_rtc_pinmux_action_lsco(struct pinctrl_dev *pctldev, unsigned int pin) 325 { 326 struct stm32_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); 327 struct stm32_rtc_registers regs = rtc->data->regs; 328 struct device *dev = rtc->rtc_dev->dev.parent; 329 u8 lscoen; 330 int ret; 331 332 if (!rtc->data->has_lsco) 333 return -EPERM; 334 335 ret = stm32_rtc_pinmux_lsco_available(pctldev, pin); 336 if (ret) 337 return ret; 338 339 lscoen = (pin == OUT1) ? STM32_RTC_CFGR_LSCOEN_OUT1 : STM32_RTC_CFGR_LSCOEN_OUT2_RMP; 340 341 rtc->clk_lsco = clk_register_gate(dev, "rtc_lsco", __clk_get_name(rtc->rtc_ck), 342 CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 343 rtc->base + regs.cfgr, lscoen, 0, NULL); 344 if (IS_ERR(rtc->clk_lsco)) 345 return PTR_ERR(rtc->clk_lsco); 346 347 of_clk_add_provider(dev->of_node, of_clk_src_simple_get, rtc->clk_lsco); 348 349 return 0; 350 } 351 352 static const struct stm32_rtc_pinmux_func stm32_rtc_pinmux_functions[] = { 353 STM32_RTC_PINMUX("lsco", &stm32_rtc_pinmux_action_lsco, "out1", "out2_rmp"), 354 STM32_RTC_PINMUX("alarm-a", &stm32_rtc_pinmux_action_alarm, "out1", "out2", "out2_rmp"), 355 }; 356 357 static int stm32_rtc_pinmux_get_functions_count(struct pinctrl_dev *pctldev) 358 { 359 return ARRAY_SIZE(stm32_rtc_pinmux_functions); 360 } 361 362 static const char *stm32_rtc_pinmux_get_fname(struct pinctrl_dev *pctldev, unsigned int selector) 363 { 364 return stm32_rtc_pinmux_functions[selector].name; 365 } 366 367 static int stm32_rtc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector, 368 const char * const **groups, unsigned int * const num_groups) 369 { 370 *groups = stm32_rtc_pinmux_functions[selector].groups; 371 *num_groups = stm32_rtc_pinmux_functions[selector].num_groups; 372 return 0; 373 } 374 375 static int stm32_rtc_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, 376 unsigned int group) 377 { 378 struct stm32_rtc_pinmux_func selected_func = stm32_rtc_pinmux_functions[selector]; 379 struct pinctrl_pin_desc pin = stm32_rtc_pinctrl_pins[group]; 380 381 /* Call action */ 382 if (selected_func.action) 383 return selected_func.action(pctldev, pin.number); 384 385 return -EINVAL; 386 } 387 388 static const struct pinmux_ops stm32_rtc_pinmux_ops = { 389 .get_functions_count = stm32_rtc_pinmux_get_functions_count, 390 .get_function_name = stm32_rtc_pinmux_get_fname, 391 .get_function_groups = stm32_rtc_pinmux_get_groups, 392 .set_mux = stm32_rtc_pinmux_set_mux, 393 .strict = true, 394 }; 395 396 static const struct pinctrl_desc stm32_rtc_pdesc = { 397 .name = DRIVER_NAME, 398 .pins = stm32_rtc_pinctrl_pins, 399 .npins = ARRAY_SIZE(stm32_rtc_pinctrl_pins), 400 .owner = THIS_MODULE, 401 .pctlops = &stm32_rtc_pinctrl_ops, 402 .pmxops = &stm32_rtc_pinmux_ops, 403 }; 404 405 static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc) 406 { 407 const struct stm32_rtc_registers *regs = &rtc->data->regs; 408 unsigned int isr = readl_relaxed(rtc->base + regs->isr); 409 410 if (!(isr & STM32_RTC_ISR_INITF)) { 411 isr |= STM32_RTC_ISR_INIT; 412 writel_relaxed(isr, rtc->base + regs->isr); 413 414 /* 415 * It takes around 2 rtc_ck clock cycles to enter in 416 * initialization phase mode (and have INITF flag set). As 417 * slowest rtc_ck frequency may be 32kHz and highest should be 418 * 1MHz, we poll every 10 us with a timeout of 100ms. 419 */ 420 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, isr, 421 (isr & STM32_RTC_ISR_INITF), 422 10, 100000); 423 } 424 425 return 0; 426 } 427 428 static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc) 429 { 430 const struct stm32_rtc_registers *regs = &rtc->data->regs; 431 unsigned int isr = readl_relaxed(rtc->base + regs->isr); 432 433 isr &= ~STM32_RTC_ISR_INIT; 434 writel_relaxed(isr, rtc->base + regs->isr); 435 } 436 437 static int stm32_rtc_wait_sync(struct stm32_rtc *rtc) 438 { 439 const struct stm32_rtc_registers *regs = &rtc->data->regs; 440 unsigned int isr = readl_relaxed(rtc->base + regs->isr); 441 442 isr &= ~STM32_RTC_ISR_RSF; 443 writel_relaxed(isr, rtc->base + regs->isr); 444 445 /* 446 * Wait for RSF to be set to ensure the calendar registers are 447 * synchronised, it takes around 2 rtc_ck clock cycles 448 */ 449 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, 450 isr, 451 (isr & STM32_RTC_ISR_RSF), 452 10, 100000); 453 } 454 455 static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc, 456 unsigned int flags) 457 { 458 rtc->data->clear_events(rtc, flags); 459 } 460 461 static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id) 462 { 463 struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id; 464 const struct stm32_rtc_registers *regs = &rtc->data->regs; 465 const struct stm32_rtc_events *evts = &rtc->data->events; 466 unsigned int status, cr; 467 468 guard(rtc_ops)(rtc->rtc_dev); 469 470 status = readl_relaxed(rtc->base + regs->sr); 471 cr = readl_relaxed(rtc->base + regs->cr); 472 473 if ((status & evts->alra) && 474 (cr & STM32_RTC_CR_ALRAIE)) { 475 /* Alarm A flag - Alarm interrupt */ 476 dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n"); 477 478 /* Pass event to the kernel */ 479 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF); 480 481 /* Clear event flags, otherwise new events won't be received */ 482 stm32_rtc_clear_event_flags(rtc, evts->alra); 483 } 484 485 return IRQ_HANDLED; 486 } 487 488 /* Convert rtc_time structure from bin to bcd format */ 489 static void tm2bcd(struct rtc_time *tm) 490 { 491 tm->tm_sec = bin2bcd(tm->tm_sec); 492 tm->tm_min = bin2bcd(tm->tm_min); 493 tm->tm_hour = bin2bcd(tm->tm_hour); 494 495 tm->tm_mday = bin2bcd(tm->tm_mday); 496 tm->tm_mon = bin2bcd(tm->tm_mon + 1); 497 tm->tm_year = bin2bcd(tm->tm_year - 100); 498 /* 499 * Number of days since Sunday 500 * - on kernel side, 0=Sunday...6=Saturday 501 * - on rtc side, 0=invalid,1=Monday...7=Sunday 502 */ 503 tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday; 504 } 505 506 /* Convert rtc_time structure from bcd to bin format */ 507 static void bcd2tm(struct rtc_time *tm) 508 { 509 tm->tm_sec = bcd2bin(tm->tm_sec); 510 tm->tm_min = bcd2bin(tm->tm_min); 511 tm->tm_hour = bcd2bin(tm->tm_hour); 512 513 tm->tm_mday = bcd2bin(tm->tm_mday); 514 tm->tm_mon = bcd2bin(tm->tm_mon) - 1; 515 tm->tm_year = bcd2bin(tm->tm_year) + 100; 516 /* 517 * Number of days since Sunday 518 * - on kernel side, 0=Sunday...6=Saturday 519 * - on rtc side, 0=invalid,1=Monday...7=Sunday 520 */ 521 tm->tm_wday %= 7; 522 } 523 524 static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm) 525 { 526 struct stm32_rtc *rtc = dev_get_drvdata(dev); 527 const struct stm32_rtc_registers *regs = &rtc->data->regs; 528 unsigned int tr, dr; 529 530 /* Time and Date in BCD format */ 531 tr = readl_relaxed(rtc->base + regs->tr); 532 dr = readl_relaxed(rtc->base + regs->dr); 533 534 tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT; 535 tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT; 536 tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT; 537 538 tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT; 539 tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT; 540 tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT; 541 tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT; 542 543 /* We don't report tm_yday and tm_isdst */ 544 545 bcd2tm(tm); 546 547 return 0; 548 } 549 550 static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm) 551 { 552 struct stm32_rtc *rtc = dev_get_drvdata(dev); 553 const struct stm32_rtc_registers *regs = &rtc->data->regs; 554 unsigned int tr, dr; 555 int ret = 0; 556 557 tm2bcd(tm); 558 559 /* Time in BCD format */ 560 tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) | 561 ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) | 562 ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR); 563 564 /* Date in BCD format */ 565 dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) | 566 ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) | 567 ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) | 568 ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY); 569 570 stm32_rtc_wpr_unlock(rtc); 571 572 ret = stm32_rtc_enter_init_mode(rtc); 573 if (ret) { 574 dev_err(dev, "Can't enter in init mode. Set time aborted.\n"); 575 goto end; 576 } 577 578 writel_relaxed(tr, rtc->base + regs->tr); 579 writel_relaxed(dr, rtc->base + regs->dr); 580 581 stm32_rtc_exit_init_mode(rtc); 582 583 ret = stm32_rtc_wait_sync(rtc); 584 end: 585 stm32_rtc_wpr_lock(rtc); 586 587 return ret; 588 } 589 590 static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 591 { 592 struct stm32_rtc *rtc = dev_get_drvdata(dev); 593 const struct stm32_rtc_registers *regs = &rtc->data->regs; 594 const struct stm32_rtc_events *evts = &rtc->data->events; 595 struct rtc_time *tm = &alrm->time; 596 unsigned int alrmar, cr, status; 597 598 alrmar = readl_relaxed(rtc->base + regs->alrmar); 599 cr = readl_relaxed(rtc->base + regs->cr); 600 status = readl_relaxed(rtc->base + regs->sr); 601 602 if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) { 603 /* 604 * Date/day doesn't matter in Alarm comparison so alarm 605 * triggers every day 606 */ 607 tm->tm_mday = -1; 608 tm->tm_wday = -1; 609 } else { 610 if (alrmar & STM32_RTC_ALRMXR_WDSEL) { 611 /* Alarm is set to a day of week */ 612 tm->tm_mday = -1; 613 tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >> 614 STM32_RTC_ALRMXR_WDAY_SHIFT; 615 tm->tm_wday %= 7; 616 } else { 617 /* Alarm is set to a day of month */ 618 tm->tm_wday = -1; 619 tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >> 620 STM32_RTC_ALRMXR_DATE_SHIFT; 621 } 622 } 623 624 if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) { 625 /* Hours don't matter in Alarm comparison */ 626 tm->tm_hour = -1; 627 } else { 628 tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >> 629 STM32_RTC_ALRMXR_HOUR_SHIFT; 630 if (alrmar & STM32_RTC_ALRMXR_PM) 631 tm->tm_hour += 12; 632 } 633 634 if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) { 635 /* Minutes don't matter in Alarm comparison */ 636 tm->tm_min = -1; 637 } else { 638 tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >> 639 STM32_RTC_ALRMXR_MIN_SHIFT; 640 } 641 642 if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) { 643 /* Seconds don't matter in Alarm comparison */ 644 tm->tm_sec = -1; 645 } else { 646 tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >> 647 STM32_RTC_ALRMXR_SEC_SHIFT; 648 } 649 650 bcd2tm(tm); 651 652 alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0; 653 alrm->pending = (status & evts->alra) ? 1 : 0; 654 655 return 0; 656 } 657 658 static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 659 { 660 struct stm32_rtc *rtc = dev_get_drvdata(dev); 661 const struct stm32_rtc_registers *regs = &rtc->data->regs; 662 const struct stm32_rtc_events *evts = &rtc->data->events; 663 unsigned int cr; 664 665 cr = readl_relaxed(rtc->base + regs->cr); 666 667 stm32_rtc_wpr_unlock(rtc); 668 669 /* We expose Alarm A to the kernel */ 670 if (enabled) 671 cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); 672 else 673 cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); 674 writel_relaxed(cr, rtc->base + regs->cr); 675 676 /* Clear event flags, otherwise new events won't be received */ 677 stm32_rtc_clear_event_flags(rtc, evts->alra); 678 679 stm32_rtc_wpr_lock(rtc); 680 681 return 0; 682 } 683 684 static int stm32_rtc_valid_alrm(struct device *dev, struct rtc_time *tm) 685 { 686 static struct rtc_time now; 687 time64_t max_alarm_time64; 688 int max_day_forward; 689 int next_month; 690 int next_year; 691 692 /* 693 * Assuming current date is M-D-Y H:M:S. 694 * RTC alarm can't be set on a specific month and year. 695 * So the valid alarm range is: 696 * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S 697 */ 698 stm32_rtc_read_time(dev, &now); 699 700 /* 701 * Find the next month and the year of the next month. 702 * Note: tm_mon and next_month are from 0 to 11 703 */ 704 next_month = now.tm_mon + 1; 705 if (next_month == 12) { 706 next_month = 0; 707 next_year = now.tm_year + 1; 708 } else { 709 next_year = now.tm_year; 710 } 711 712 /* Find the maximum limit of alarm in days. */ 713 max_day_forward = rtc_month_days(now.tm_mon, now.tm_year) 714 - now.tm_mday 715 + min(rtc_month_days(next_month, next_year), now.tm_mday); 716 717 /* Convert to timestamp and compare the alarm time and its upper limit */ 718 max_alarm_time64 = rtc_tm_to_time64(&now) + max_day_forward * SEC_PER_DAY; 719 return rtc_tm_to_time64(tm) <= max_alarm_time64 ? 0 : -EINVAL; 720 } 721 722 static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 723 { 724 struct stm32_rtc *rtc = dev_get_drvdata(dev); 725 const struct stm32_rtc_registers *regs = &rtc->data->regs; 726 struct rtc_time *tm = &alrm->time; 727 unsigned int cr, isr, alrmar; 728 int ret = 0; 729 730 /* 731 * RTC alarm can't be set on a specific date, unless this date is 732 * up to the same day of month next month. 733 */ 734 if (stm32_rtc_valid_alrm(dev, tm) < 0) { 735 dev_err(dev, "Alarm can be set only on upcoming month.\n"); 736 return -EINVAL; 737 } 738 739 tm2bcd(tm); 740 741 alrmar = 0; 742 /* tm_year and tm_mon are not used because not supported by RTC */ 743 alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) & 744 STM32_RTC_ALRMXR_DATE; 745 /* 24-hour format */ 746 alrmar &= ~STM32_RTC_ALRMXR_PM; 747 alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) & 748 STM32_RTC_ALRMXR_HOUR; 749 alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) & 750 STM32_RTC_ALRMXR_MIN; 751 alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) & 752 STM32_RTC_ALRMXR_SEC; 753 754 stm32_rtc_wpr_unlock(rtc); 755 756 /* Disable Alarm */ 757 cr = readl_relaxed(rtc->base + regs->cr); 758 cr &= ~STM32_RTC_CR_ALRAE; 759 writel_relaxed(cr, rtc->base + regs->cr); 760 761 /* 762 * Poll Alarm write flag to be sure that Alarm update is allowed: it 763 * takes around 2 rtc_ck clock cycles 764 */ 765 ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, 766 isr, 767 (isr & STM32_RTC_ISR_ALRAWF), 768 10, 100000); 769 770 if (ret) { 771 dev_err(dev, "Alarm update not allowed\n"); 772 goto end; 773 } 774 775 /* Write to Alarm register */ 776 writel_relaxed(alrmar, rtc->base + regs->alrmar); 777 778 stm32_rtc_alarm_irq_enable(dev, alrm->enabled); 779 end: 780 stm32_rtc_wpr_lock(rtc); 781 782 return ret; 783 } 784 785 static const struct rtc_class_ops stm32_rtc_ops = { 786 .read_time = stm32_rtc_read_time, 787 .set_time = stm32_rtc_set_time, 788 .read_alarm = stm32_rtc_read_alarm, 789 .set_alarm = stm32_rtc_set_alarm, 790 .alarm_irq_enable = stm32_rtc_alarm_irq_enable, 791 }; 792 793 static void stm32_rtc_clear_events(struct stm32_rtc *rtc, 794 unsigned int flags) 795 { 796 const struct stm32_rtc_registers *regs = &rtc->data->regs; 797 798 /* Flags are cleared by writing 0 in RTC_ISR */ 799 writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags, 800 rtc->base + regs->isr); 801 } 802 803 static const struct stm32_rtc_data stm32_rtc_data = { 804 .has_pclk = false, 805 .need_dbp = true, 806 .need_accuracy = false, 807 .rif_protected = false, 808 .has_lsco = false, 809 .has_alarm_out = false, 810 .regs = { 811 .tr = 0x00, 812 .dr = 0x04, 813 .cr = 0x08, 814 .isr = 0x0C, 815 .prer = 0x10, 816 .alrmar = 0x1C, 817 .wpr = 0x24, 818 .sr = 0x0C, /* set to ISR offset to ease alarm management */ 819 .scr = UNDEF_REG, 820 .cfgr = UNDEF_REG, 821 .verr = UNDEF_REG, 822 }, 823 .events = { 824 .alra = STM32_RTC_ISR_ALRAF, 825 }, 826 .clear_events = stm32_rtc_clear_events, 827 }; 828 829 static const struct stm32_rtc_data stm32h7_rtc_data = { 830 .has_pclk = true, 831 .need_dbp = true, 832 .need_accuracy = false, 833 .rif_protected = false, 834 .has_lsco = false, 835 .has_alarm_out = false, 836 .regs = { 837 .tr = 0x00, 838 .dr = 0x04, 839 .cr = 0x08, 840 .isr = 0x0C, 841 .prer = 0x10, 842 .alrmar = 0x1C, 843 .wpr = 0x24, 844 .sr = 0x0C, /* set to ISR offset to ease alarm management */ 845 .scr = UNDEF_REG, 846 .cfgr = UNDEF_REG, 847 .verr = UNDEF_REG, 848 }, 849 .events = { 850 .alra = STM32_RTC_ISR_ALRAF, 851 }, 852 .clear_events = stm32_rtc_clear_events, 853 }; 854 855 static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc, 856 unsigned int flags) 857 { 858 struct stm32_rtc_registers regs = rtc->data->regs; 859 860 /* Flags are cleared by writing 1 in RTC_SCR */ 861 writel_relaxed(flags, rtc->base + regs.scr); 862 } 863 864 static const struct stm32_rtc_data stm32mp1_data = { 865 .has_pclk = true, 866 .need_dbp = false, 867 .need_accuracy = true, 868 .rif_protected = false, 869 .has_lsco = true, 870 .has_alarm_out = true, 871 .regs = { 872 .tr = 0x00, 873 .dr = 0x04, 874 .cr = 0x18, 875 .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */ 876 .prer = 0x10, 877 .alrmar = 0x40, 878 .wpr = 0x24, 879 .sr = 0x50, 880 .scr = 0x5C, 881 .cfgr = 0x60, 882 .verr = 0x3F4, 883 }, 884 .events = { 885 .alra = STM32_RTC_SR_ALRA, 886 }, 887 .clear_events = stm32mp1_rtc_clear_events, 888 }; 889 890 static const struct stm32_rtc_data stm32mp25_data = { 891 .has_pclk = true, 892 .need_dbp = false, 893 .need_accuracy = true, 894 .rif_protected = true, 895 .has_lsco = true, 896 .has_alarm_out = true, 897 .regs = { 898 .tr = 0x00, 899 .dr = 0x04, 900 .cr = 0x18, 901 .isr = 0x0C, /* named RTC_ICSR on stm32mp25 */ 902 .prer = 0x10, 903 .alrmar = 0x40, 904 .wpr = 0x24, 905 .sr = 0x50, 906 .scr = 0x5C, 907 .cfgr = 0x60, 908 .verr = 0x3F4, 909 }, 910 .events = { 911 .alra = STM32_RTC_SR_ALRA, 912 }, 913 .clear_events = stm32mp1_rtc_clear_events, 914 }; 915 916 static const struct of_device_id stm32_rtc_of_match[] = { 917 { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data }, 918 { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data }, 919 { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data }, 920 { .compatible = "st,stm32mp25-rtc", .data = &stm32mp25_data }, 921 {} 922 }; 923 MODULE_DEVICE_TABLE(of, stm32_rtc_of_match); 924 925 static void stm32_rtc_clean_outs(struct stm32_rtc *rtc) 926 { 927 struct stm32_rtc_registers regs = rtc->data->regs; 928 unsigned int cr = readl_relaxed(rtc->base + regs.cr); 929 930 cr &= ~STM32_RTC_CR_OSEL; 931 cr &= ~STM32_RTC_CR_TAMPOE; 932 cr &= ~STM32_RTC_CR_COE; 933 cr &= ~STM32_RTC_CR_TAMPALRM_TYPE; 934 cr &= ~STM32_RTC_CR_OUT2EN; 935 936 stm32_rtc_wpr_unlock(rtc); 937 writel_relaxed(cr, rtc->base + regs.cr); 938 stm32_rtc_wpr_lock(rtc); 939 940 if (regs.cfgr != UNDEF_REG) { 941 unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); 942 943 cfgr &= ~STM32_RTC_CFGR_LSCOEN; 944 cfgr &= ~STM32_RTC_CFGR_OUT2_RMP; 945 writel_relaxed(cfgr, rtc->base + regs.cfgr); 946 } 947 } 948 949 static int stm32_rtc_check_rif(struct stm32_rtc *stm32_rtc, 950 struct stm32_rtc_rif_resource res) 951 { 952 u32 rxcidcfgr = readl_relaxed(stm32_rtc->base + STM32_RTC_RXCIDCFGR(res.num)); 953 u32 seccfgr; 954 955 /* Check if RTC available for our CID */ 956 if ((rxcidcfgr & STM32_RTC_RXCIDCFGR_CFEN) && 957 (FIELD_GET(STM32_RTC_RXCIDCFGR_CID, rxcidcfgr) != STM32_RTC_RXCIDCFGR_CID1)) 958 return -EACCES; 959 960 /* Check if RTC available for non secure world */ 961 seccfgr = readl_relaxed(stm32_rtc->base + STM32_RTC_SECCFGR); 962 if ((seccfgr & STM32_RTC_SECCFGR_SEC) | (seccfgr & res.bit)) 963 return -EACCES; 964 965 return 0; 966 } 967 968 static int stm32_rtc_init(struct platform_device *pdev, 969 struct stm32_rtc *rtc) 970 { 971 const struct stm32_rtc_registers *regs = &rtc->data->regs; 972 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr; 973 unsigned int rate; 974 int ret; 975 976 rate = clk_get_rate(rtc->rtc_ck); 977 978 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */ 979 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT; 980 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT; 981 982 if (rate > (pred_a_max + 1) * (pred_s_max + 1)) { 983 dev_err(&pdev->dev, "rtc_ck rate is too high: %dHz\n", rate); 984 return -EINVAL; 985 } 986 987 if (rtc->data->need_accuracy) { 988 for (pred_a = 0; pred_a <= pred_a_max; pred_a++) { 989 pred_s = (rate / (pred_a + 1)) - 1; 990 991 if (pred_s <= pred_s_max && ((pred_s + 1) * (pred_a + 1)) == rate) 992 break; 993 } 994 } else { 995 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) { 996 pred_s = (rate / (pred_a + 1)) - 1; 997 998 if (((pred_s + 1) * (pred_a + 1)) == rate) 999 break; 1000 } 1001 } 1002 1003 /* 1004 * Can't find a 1Hz, so give priority to RTC power consumption 1005 * by choosing the higher possible value for prediv_a 1006 */ 1007 if (pred_s > pred_s_max || pred_a > pred_a_max) { 1008 pred_a = pred_a_max; 1009 pred_s = (rate / (pred_a + 1)) - 1; 1010 1011 dev_warn(&pdev->dev, "rtc_ck is %s\n", 1012 (rate < ((pred_a + 1) * (pred_s + 1))) ? 1013 "fast" : "slow"); 1014 } 1015 1016 cr = readl_relaxed(rtc->base + regs->cr); 1017 1018 prer = readl_relaxed(rtc->base + regs->prer); 1019 prer &= STM32_RTC_PRER_PRED_S | STM32_RTC_PRER_PRED_A; 1020 1021 pred_s = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & 1022 STM32_RTC_PRER_PRED_S; 1023 pred_a = (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & 1024 STM32_RTC_PRER_PRED_A; 1025 1026 /* quit if there is nothing to initialize */ 1027 if ((cr & STM32_RTC_CR_FMT) == 0 && prer == (pred_s | pred_a)) 1028 return 0; 1029 1030 stm32_rtc_wpr_unlock(rtc); 1031 1032 ret = stm32_rtc_enter_init_mode(rtc); 1033 if (ret) { 1034 dev_err(&pdev->dev, 1035 "Can't enter in init mode. Prescaler config failed.\n"); 1036 goto end; 1037 } 1038 1039 writel_relaxed(pred_s, rtc->base + regs->prer); 1040 writel_relaxed(pred_a | pred_s, rtc->base + regs->prer); 1041 1042 /* Force 24h time format */ 1043 cr &= ~STM32_RTC_CR_FMT; 1044 writel_relaxed(cr, rtc->base + regs->cr); 1045 1046 stm32_rtc_exit_init_mode(rtc); 1047 1048 ret = stm32_rtc_wait_sync(rtc); 1049 end: 1050 stm32_rtc_wpr_lock(rtc); 1051 1052 return ret; 1053 } 1054 1055 static int stm32_rtc_probe(struct platform_device *pdev) 1056 { 1057 struct stm32_rtc *rtc; 1058 const struct stm32_rtc_registers *regs; 1059 struct pinctrl_dev *pctl; 1060 int ret; 1061 1062 rtc = devm_kzalloc_obj(&pdev->dev, *rtc); 1063 if (!rtc) 1064 return -ENOMEM; 1065 1066 rtc->base = devm_platform_ioremap_resource(pdev, 0); 1067 if (IS_ERR(rtc->base)) 1068 return PTR_ERR(rtc->base); 1069 1070 rtc->data = (struct stm32_rtc_data *) 1071 of_device_get_match_data(&pdev->dev); 1072 regs = &rtc->data->regs; 1073 1074 if (rtc->data->need_dbp) { 1075 unsigned int args[2]; 1076 1077 rtc->dbp = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, 1078 "st,syscfg", 1079 2, args); 1080 if (IS_ERR(rtc->dbp)) { 1081 dev_err(&pdev->dev, "no st,syscfg\n"); 1082 return PTR_ERR(rtc->dbp); 1083 } 1084 1085 rtc->dbp_reg = args[0]; 1086 rtc->dbp_mask = args[1]; 1087 } 1088 1089 if (!rtc->data->has_pclk) { 1090 rtc->pclk = NULL; 1091 rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL); 1092 } else { 1093 rtc->pclk = devm_clk_get(&pdev->dev, "pclk"); 1094 if (IS_ERR(rtc->pclk)) 1095 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->pclk), "no pclk clock"); 1096 1097 rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck"); 1098 } 1099 if (IS_ERR(rtc->rtc_ck)) 1100 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->rtc_ck), "no rtc_ck clock"); 1101 1102 if (rtc->data->has_pclk) { 1103 ret = clk_prepare_enable(rtc->pclk); 1104 if (ret) 1105 return ret; 1106 } 1107 1108 ret = clk_prepare_enable(rtc->rtc_ck); 1109 if (ret) 1110 goto err_no_rtc_ck; 1111 1112 if (rtc->data->need_dbp) 1113 regmap_update_bits(rtc->dbp, rtc->dbp_reg, 1114 rtc->dbp_mask, rtc->dbp_mask); 1115 1116 if (rtc->data->rif_protected) { 1117 ret = stm32_rtc_check_rif(rtc, STM32_RTC_RES_INIT); 1118 if (!ret) 1119 ret = stm32_rtc_check_rif(rtc, STM32_RTC_RES_ALRA); 1120 if (ret) { 1121 dev_err(&pdev->dev, "Failed to probe RTC due to RIF configuration\n"); 1122 goto err; 1123 } 1124 } 1125 1126 /* 1127 * After a system reset, RTC_ISR.INITS flag can be read to check if 1128 * the calendar has been initialized or not. INITS flag is reset by a 1129 * power-on reset (no vbat, no power-supply). It is not reset if 1130 * rtc_ck parent clock has changed (so RTC prescalers need to be 1131 * changed). That's why we cannot rely on this flag to know if RTC 1132 * init has to be done. 1133 */ 1134 ret = stm32_rtc_init(pdev, rtc); 1135 if (ret) 1136 goto err; 1137 1138 rtc->irq_alarm = platform_get_irq(pdev, 0); 1139 if (rtc->irq_alarm <= 0) { 1140 ret = rtc->irq_alarm; 1141 goto err; 1142 } 1143 1144 ret = devm_device_init_wakeup(&pdev->dev); 1145 if (ret) 1146 goto err; 1147 1148 ret = devm_pm_set_wake_irq(&pdev->dev, rtc->irq_alarm); 1149 if (ret) 1150 goto err; 1151 1152 platform_set_drvdata(pdev, rtc); 1153 1154 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name, 1155 &stm32_rtc_ops, THIS_MODULE); 1156 if (IS_ERR(rtc->rtc_dev)) { 1157 ret = PTR_ERR(rtc->rtc_dev); 1158 dev_err(&pdev->dev, "rtc device registration failed, err=%d\n", 1159 ret); 1160 goto err; 1161 } 1162 1163 /* Handle RTC alarm interrupts */ 1164 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL, 1165 stm32_rtc_alarm_irq, IRQF_ONESHOT, 1166 pdev->name, rtc); 1167 if (ret) { 1168 dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n", 1169 rtc->irq_alarm); 1170 goto err; 1171 } 1172 1173 stm32_rtc_clean_outs(rtc); 1174 1175 ret = devm_pinctrl_register_and_init(&pdev->dev, &stm32_rtc_pdesc, rtc, &pctl); 1176 if (ret) 1177 return dev_err_probe(&pdev->dev, ret, "pinctrl register failed"); 1178 1179 ret = pinctrl_enable(pctl); 1180 if (ret) 1181 return dev_err_probe(&pdev->dev, ret, "pinctrl enable failed"); 1182 1183 /* 1184 * If INITS flag is reset (calendar year field set to 0x00), calendar 1185 * must be initialized 1186 */ 1187 if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS)) 1188 dev_warn(&pdev->dev, "Date/Time must be initialized\n"); 1189 1190 if (regs->verr != UNDEF_REG) { 1191 u32 ver = readl_relaxed(rtc->base + regs->verr); 1192 1193 dev_info(&pdev->dev, "registered rev:%d.%d\n", 1194 (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF, 1195 (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF); 1196 } 1197 1198 return 0; 1199 1200 err: 1201 clk_disable_unprepare(rtc->rtc_ck); 1202 err_no_rtc_ck: 1203 if (rtc->data->has_pclk) 1204 clk_disable_unprepare(rtc->pclk); 1205 1206 if (rtc->data->need_dbp) 1207 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0); 1208 1209 return ret; 1210 } 1211 1212 static void stm32_rtc_remove(struct platform_device *pdev) 1213 { 1214 struct stm32_rtc *rtc = platform_get_drvdata(pdev); 1215 const struct stm32_rtc_registers *regs = &rtc->data->regs; 1216 unsigned int cr; 1217 1218 if (!IS_ERR_OR_NULL(rtc->clk_lsco)) 1219 clk_unregister_gate(rtc->clk_lsco); 1220 1221 /* Disable interrupts */ 1222 stm32_rtc_wpr_unlock(rtc); 1223 cr = readl_relaxed(rtc->base + regs->cr); 1224 cr &= ~STM32_RTC_CR_ALRAIE; 1225 writel_relaxed(cr, rtc->base + regs->cr); 1226 stm32_rtc_wpr_lock(rtc); 1227 1228 clk_disable_unprepare(rtc->rtc_ck); 1229 if (rtc->data->has_pclk) 1230 clk_disable_unprepare(rtc->pclk); 1231 1232 /* Enable backup domain write protection if needed */ 1233 if (rtc->data->need_dbp) 1234 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0); 1235 } 1236 1237 static int stm32_rtc_suspend(struct device *dev) 1238 { 1239 struct stm32_rtc *rtc = dev_get_drvdata(dev); 1240 1241 if (rtc->data->has_pclk) 1242 clk_disable_unprepare(rtc->pclk); 1243 1244 return 0; 1245 } 1246 1247 static int stm32_rtc_resume(struct device *dev) 1248 { 1249 struct stm32_rtc *rtc = dev_get_drvdata(dev); 1250 int ret = 0; 1251 1252 if (rtc->data->has_pclk) { 1253 ret = clk_prepare_enable(rtc->pclk); 1254 if (ret) 1255 return ret; 1256 } 1257 1258 ret = stm32_rtc_wait_sync(rtc); 1259 if (ret < 0) { 1260 if (rtc->data->has_pclk) 1261 clk_disable_unprepare(rtc->pclk); 1262 return ret; 1263 } 1264 1265 return ret; 1266 } 1267 1268 static const struct dev_pm_ops stm32_rtc_pm_ops = { 1269 NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_rtc_suspend, stm32_rtc_resume) 1270 }; 1271 1272 static struct platform_driver stm32_rtc_driver = { 1273 .probe = stm32_rtc_probe, 1274 .remove = stm32_rtc_remove, 1275 .driver = { 1276 .name = DRIVER_NAME, 1277 .pm = &stm32_rtc_pm_ops, 1278 .of_match_table = stm32_rtc_of_match, 1279 }, 1280 }; 1281 1282 module_platform_driver(stm32_rtc_driver); 1283 1284 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 1285 MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver"); 1286 MODULE_LICENSE("GPL v2"); 1287