1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2017 4 * Author: Amelie Delaunay <amelie.delaunay@st.com> 5 */ 6 7 #include <linux/bcd.h> 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/errno.h> 11 #include <linux/iopoll.h> 12 #include <linux/ioport.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/regmap.h> 19 #include <linux/rtc.h> 20 21 #define DRIVER_NAME "stm32_rtc" 22 23 /* STM32_RTC_TR bit fields */ 24 #define STM32_RTC_TR_SEC_SHIFT 0 25 #define STM32_RTC_TR_SEC GENMASK(6, 0) 26 #define STM32_RTC_TR_MIN_SHIFT 8 27 #define STM32_RTC_TR_MIN GENMASK(14, 8) 28 #define STM32_RTC_TR_HOUR_SHIFT 16 29 #define STM32_RTC_TR_HOUR GENMASK(21, 16) 30 31 /* STM32_RTC_DR bit fields */ 32 #define STM32_RTC_DR_DATE_SHIFT 0 33 #define STM32_RTC_DR_DATE GENMASK(5, 0) 34 #define STM32_RTC_DR_MONTH_SHIFT 8 35 #define STM32_RTC_DR_MONTH GENMASK(12, 8) 36 #define STM32_RTC_DR_WDAY_SHIFT 13 37 #define STM32_RTC_DR_WDAY GENMASK(15, 13) 38 #define STM32_RTC_DR_YEAR_SHIFT 16 39 #define STM32_RTC_DR_YEAR GENMASK(23, 16) 40 41 /* STM32_RTC_CR bit fields */ 42 #define STM32_RTC_CR_FMT BIT(6) 43 #define STM32_RTC_CR_ALRAE BIT(8) 44 #define STM32_RTC_CR_ALRAIE BIT(12) 45 46 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ 47 #define STM32_RTC_ISR_ALRAWF BIT(0) 48 #define STM32_RTC_ISR_INITS BIT(4) 49 #define STM32_RTC_ISR_RSF BIT(5) 50 #define STM32_RTC_ISR_INITF BIT(6) 51 #define STM32_RTC_ISR_INIT BIT(7) 52 #define STM32_RTC_ISR_ALRAF BIT(8) 53 54 /* STM32_RTC_PRER bit fields */ 55 #define STM32_RTC_PRER_PRED_S_SHIFT 0 56 #define STM32_RTC_PRER_PRED_S GENMASK(14, 0) 57 #define STM32_RTC_PRER_PRED_A_SHIFT 16 58 #define STM32_RTC_PRER_PRED_A GENMASK(22, 16) 59 60 /* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */ 61 #define STM32_RTC_ALRMXR_SEC_SHIFT 0 62 #define STM32_RTC_ALRMXR_SEC GENMASK(6, 0) 63 #define STM32_RTC_ALRMXR_SEC_MASK BIT(7) 64 #define STM32_RTC_ALRMXR_MIN_SHIFT 8 65 #define STM32_RTC_ALRMXR_MIN GENMASK(14, 8) 66 #define STM32_RTC_ALRMXR_MIN_MASK BIT(15) 67 #define STM32_RTC_ALRMXR_HOUR_SHIFT 16 68 #define STM32_RTC_ALRMXR_HOUR GENMASK(21, 16) 69 #define STM32_RTC_ALRMXR_PM BIT(22) 70 #define STM32_RTC_ALRMXR_HOUR_MASK BIT(23) 71 #define STM32_RTC_ALRMXR_DATE_SHIFT 24 72 #define STM32_RTC_ALRMXR_DATE GENMASK(29, 24) 73 #define STM32_RTC_ALRMXR_WDSEL BIT(30) 74 #define STM32_RTC_ALRMXR_WDAY_SHIFT 24 75 #define STM32_RTC_ALRMXR_WDAY GENMASK(27, 24) 76 #define STM32_RTC_ALRMXR_DATE_MASK BIT(31) 77 78 /* STM32_RTC_SR/_SCR bit fields */ 79 #define STM32_RTC_SR_ALRA BIT(0) 80 81 /* STM32_RTC_VERR bit fields */ 82 #define STM32_RTC_VERR_MINREV_SHIFT 0 83 #define STM32_RTC_VERR_MINREV GENMASK(3, 0) 84 #define STM32_RTC_VERR_MAJREV_SHIFT 4 85 #define STM32_RTC_VERR_MAJREV GENMASK(7, 4) 86 87 /* STM32_RTC_SECCFGR bit fields */ 88 #define STM32_RTC_SECCFGR 0x20 89 #define STM32_RTC_SECCFGR_ALRA_SEC BIT(0) 90 #define STM32_RTC_SECCFGR_INIT_SEC BIT(14) 91 #define STM32_RTC_SECCFGR_SEC BIT(15) 92 93 /* STM32_RTC_RXCIDCFGR bit fields */ 94 #define STM32_RTC_RXCIDCFGR(x) (0x80 + 0x4 * (x)) 95 #define STM32_RTC_RXCIDCFGR_CFEN BIT(0) 96 #define STM32_RTC_RXCIDCFGR_CID GENMASK(6, 4) 97 #define STM32_RTC_RXCIDCFGR_CID1 1 98 99 /* STM32_RTC_WPR key constants */ 100 #define RTC_WPR_1ST_KEY 0xCA 101 #define RTC_WPR_2ND_KEY 0x53 102 #define RTC_WPR_WRONG_KEY 0xFF 103 104 /* Max STM32 RTC register offset is 0x3FC */ 105 #define UNDEF_REG 0xFFFF 106 107 /* STM32 RTC driver time helpers */ 108 #define SEC_PER_DAY (24 * 60 * 60) 109 110 struct stm32_rtc; 111 112 struct stm32_rtc_registers { 113 u16 tr; 114 u16 dr; 115 u16 cr; 116 u16 isr; 117 u16 prer; 118 u16 alrmar; 119 u16 wpr; 120 u16 sr; 121 u16 scr; 122 u16 verr; 123 }; 124 125 struct stm32_rtc_events { 126 u32 alra; 127 }; 128 129 struct stm32_rtc_data { 130 const struct stm32_rtc_registers regs; 131 const struct stm32_rtc_events events; 132 void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags); 133 bool has_pclk; 134 bool need_dbp; 135 bool need_accuracy; 136 bool rif_protected; 137 }; 138 139 struct stm32_rtc { 140 struct rtc_device *rtc_dev; 141 void __iomem *base; 142 struct regmap *dbp; 143 unsigned int dbp_reg; 144 unsigned int dbp_mask; 145 struct clk *pclk; 146 struct clk *rtc_ck; 147 const struct stm32_rtc_data *data; 148 int irq_alarm; 149 }; 150 151 struct stm32_rtc_rif_resource { 152 unsigned int num; 153 u32 bit; 154 }; 155 156 static const struct stm32_rtc_rif_resource STM32_RTC_RES_ALRA = {0, STM32_RTC_SECCFGR_ALRA_SEC}; 157 static const struct stm32_rtc_rif_resource STM32_RTC_RES_INIT = {5, STM32_RTC_SECCFGR_INIT_SEC}; 158 159 static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc) 160 { 161 const struct stm32_rtc_registers *regs = &rtc->data->regs; 162 163 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr); 164 writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr); 165 } 166 167 static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc) 168 { 169 const struct stm32_rtc_registers *regs = &rtc->data->regs; 170 171 writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); 172 } 173 174 static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc) 175 { 176 const struct stm32_rtc_registers *regs = &rtc->data->regs; 177 unsigned int isr = readl_relaxed(rtc->base + regs->isr); 178 179 if (!(isr & STM32_RTC_ISR_INITF)) { 180 isr |= STM32_RTC_ISR_INIT; 181 writel_relaxed(isr, rtc->base + regs->isr); 182 183 /* 184 * It takes around 2 rtc_ck clock cycles to enter in 185 * initialization phase mode (and have INITF flag set). As 186 * slowest rtc_ck frequency may be 32kHz and highest should be 187 * 1MHz, we poll every 10 us with a timeout of 100ms. 188 */ 189 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, isr, 190 (isr & STM32_RTC_ISR_INITF), 191 10, 100000); 192 } 193 194 return 0; 195 } 196 197 static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc) 198 { 199 const struct stm32_rtc_registers *regs = &rtc->data->regs; 200 unsigned int isr = readl_relaxed(rtc->base + regs->isr); 201 202 isr &= ~STM32_RTC_ISR_INIT; 203 writel_relaxed(isr, rtc->base + regs->isr); 204 } 205 206 static int stm32_rtc_wait_sync(struct stm32_rtc *rtc) 207 { 208 const struct stm32_rtc_registers *regs = &rtc->data->regs; 209 unsigned int isr = readl_relaxed(rtc->base + regs->isr); 210 211 isr &= ~STM32_RTC_ISR_RSF; 212 writel_relaxed(isr, rtc->base + regs->isr); 213 214 /* 215 * Wait for RSF to be set to ensure the calendar registers are 216 * synchronised, it takes around 2 rtc_ck clock cycles 217 */ 218 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, 219 isr, 220 (isr & STM32_RTC_ISR_RSF), 221 10, 100000); 222 } 223 224 static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc, 225 unsigned int flags) 226 { 227 rtc->data->clear_events(rtc, flags); 228 } 229 230 static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id) 231 { 232 struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id; 233 const struct stm32_rtc_registers *regs = &rtc->data->regs; 234 const struct stm32_rtc_events *evts = &rtc->data->events; 235 unsigned int status, cr; 236 237 rtc_lock(rtc->rtc_dev); 238 239 status = readl_relaxed(rtc->base + regs->sr); 240 cr = readl_relaxed(rtc->base + regs->cr); 241 242 if ((status & evts->alra) && 243 (cr & STM32_RTC_CR_ALRAIE)) { 244 /* Alarm A flag - Alarm interrupt */ 245 dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n"); 246 247 /* Pass event to the kernel */ 248 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF); 249 250 /* Clear event flags, otherwise new events won't be received */ 251 stm32_rtc_clear_event_flags(rtc, evts->alra); 252 } 253 254 rtc_unlock(rtc->rtc_dev); 255 256 return IRQ_HANDLED; 257 } 258 259 /* Convert rtc_time structure from bin to bcd format */ 260 static void tm2bcd(struct rtc_time *tm) 261 { 262 tm->tm_sec = bin2bcd(tm->tm_sec); 263 tm->tm_min = bin2bcd(tm->tm_min); 264 tm->tm_hour = bin2bcd(tm->tm_hour); 265 266 tm->tm_mday = bin2bcd(tm->tm_mday); 267 tm->tm_mon = bin2bcd(tm->tm_mon + 1); 268 tm->tm_year = bin2bcd(tm->tm_year - 100); 269 /* 270 * Number of days since Sunday 271 * - on kernel side, 0=Sunday...6=Saturday 272 * - on rtc side, 0=invalid,1=Monday...7=Sunday 273 */ 274 tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday; 275 } 276 277 /* Convert rtc_time structure from bcd to bin format */ 278 static void bcd2tm(struct rtc_time *tm) 279 { 280 tm->tm_sec = bcd2bin(tm->tm_sec); 281 tm->tm_min = bcd2bin(tm->tm_min); 282 tm->tm_hour = bcd2bin(tm->tm_hour); 283 284 tm->tm_mday = bcd2bin(tm->tm_mday); 285 tm->tm_mon = bcd2bin(tm->tm_mon) - 1; 286 tm->tm_year = bcd2bin(tm->tm_year) + 100; 287 /* 288 * Number of days since Sunday 289 * - on kernel side, 0=Sunday...6=Saturday 290 * - on rtc side, 0=invalid,1=Monday...7=Sunday 291 */ 292 tm->tm_wday %= 7; 293 } 294 295 static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm) 296 { 297 struct stm32_rtc *rtc = dev_get_drvdata(dev); 298 const struct stm32_rtc_registers *regs = &rtc->data->regs; 299 unsigned int tr, dr; 300 301 /* Time and Date in BCD format */ 302 tr = readl_relaxed(rtc->base + regs->tr); 303 dr = readl_relaxed(rtc->base + regs->dr); 304 305 tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT; 306 tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT; 307 tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT; 308 309 tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT; 310 tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT; 311 tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT; 312 tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT; 313 314 /* We don't report tm_yday and tm_isdst */ 315 316 bcd2tm(tm); 317 318 return 0; 319 } 320 321 static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm) 322 { 323 struct stm32_rtc *rtc = dev_get_drvdata(dev); 324 const struct stm32_rtc_registers *regs = &rtc->data->regs; 325 unsigned int tr, dr; 326 int ret = 0; 327 328 tm2bcd(tm); 329 330 /* Time in BCD format */ 331 tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) | 332 ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) | 333 ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR); 334 335 /* Date in BCD format */ 336 dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) | 337 ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) | 338 ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) | 339 ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY); 340 341 stm32_rtc_wpr_unlock(rtc); 342 343 ret = stm32_rtc_enter_init_mode(rtc); 344 if (ret) { 345 dev_err(dev, "Can't enter in init mode. Set time aborted.\n"); 346 goto end; 347 } 348 349 writel_relaxed(tr, rtc->base + regs->tr); 350 writel_relaxed(dr, rtc->base + regs->dr); 351 352 stm32_rtc_exit_init_mode(rtc); 353 354 ret = stm32_rtc_wait_sync(rtc); 355 end: 356 stm32_rtc_wpr_lock(rtc); 357 358 return ret; 359 } 360 361 static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 362 { 363 struct stm32_rtc *rtc = dev_get_drvdata(dev); 364 const struct stm32_rtc_registers *regs = &rtc->data->regs; 365 const struct stm32_rtc_events *evts = &rtc->data->events; 366 struct rtc_time *tm = &alrm->time; 367 unsigned int alrmar, cr, status; 368 369 alrmar = readl_relaxed(rtc->base + regs->alrmar); 370 cr = readl_relaxed(rtc->base + regs->cr); 371 status = readl_relaxed(rtc->base + regs->sr); 372 373 if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) { 374 /* 375 * Date/day doesn't matter in Alarm comparison so alarm 376 * triggers every day 377 */ 378 tm->tm_mday = -1; 379 tm->tm_wday = -1; 380 } else { 381 if (alrmar & STM32_RTC_ALRMXR_WDSEL) { 382 /* Alarm is set to a day of week */ 383 tm->tm_mday = -1; 384 tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >> 385 STM32_RTC_ALRMXR_WDAY_SHIFT; 386 tm->tm_wday %= 7; 387 } else { 388 /* Alarm is set to a day of month */ 389 tm->tm_wday = -1; 390 tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >> 391 STM32_RTC_ALRMXR_DATE_SHIFT; 392 } 393 } 394 395 if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) { 396 /* Hours don't matter in Alarm comparison */ 397 tm->tm_hour = -1; 398 } else { 399 tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >> 400 STM32_RTC_ALRMXR_HOUR_SHIFT; 401 if (alrmar & STM32_RTC_ALRMXR_PM) 402 tm->tm_hour += 12; 403 } 404 405 if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) { 406 /* Minutes don't matter in Alarm comparison */ 407 tm->tm_min = -1; 408 } else { 409 tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >> 410 STM32_RTC_ALRMXR_MIN_SHIFT; 411 } 412 413 if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) { 414 /* Seconds don't matter in Alarm comparison */ 415 tm->tm_sec = -1; 416 } else { 417 tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >> 418 STM32_RTC_ALRMXR_SEC_SHIFT; 419 } 420 421 bcd2tm(tm); 422 423 alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0; 424 alrm->pending = (status & evts->alra) ? 1 : 0; 425 426 return 0; 427 } 428 429 static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) 430 { 431 struct stm32_rtc *rtc = dev_get_drvdata(dev); 432 const struct stm32_rtc_registers *regs = &rtc->data->regs; 433 const struct stm32_rtc_events *evts = &rtc->data->events; 434 unsigned int cr; 435 436 cr = readl_relaxed(rtc->base + regs->cr); 437 438 stm32_rtc_wpr_unlock(rtc); 439 440 /* We expose Alarm A to the kernel */ 441 if (enabled) 442 cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); 443 else 444 cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); 445 writel_relaxed(cr, rtc->base + regs->cr); 446 447 /* Clear event flags, otherwise new events won't be received */ 448 stm32_rtc_clear_event_flags(rtc, evts->alra); 449 450 stm32_rtc_wpr_lock(rtc); 451 452 return 0; 453 } 454 455 static int stm32_rtc_valid_alrm(struct device *dev, struct rtc_time *tm) 456 { 457 static struct rtc_time now; 458 time64_t max_alarm_time64; 459 int max_day_forward; 460 int next_month; 461 int next_year; 462 463 /* 464 * Assuming current date is M-D-Y H:M:S. 465 * RTC alarm can't be set on a specific month and year. 466 * So the valid alarm range is: 467 * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S 468 */ 469 stm32_rtc_read_time(dev, &now); 470 471 /* 472 * Find the next month and the year of the next month. 473 * Note: tm_mon and next_month are from 0 to 11 474 */ 475 next_month = now.tm_mon + 1; 476 if (next_month == 12) { 477 next_month = 0; 478 next_year = now.tm_year + 1; 479 } else { 480 next_year = now.tm_year; 481 } 482 483 /* Find the maximum limit of alarm in days. */ 484 max_day_forward = rtc_month_days(now.tm_mon, now.tm_year) 485 - now.tm_mday 486 + min(rtc_month_days(next_month, next_year), now.tm_mday); 487 488 /* Convert to timestamp and compare the alarm time and its upper limit */ 489 max_alarm_time64 = rtc_tm_to_time64(&now) + max_day_forward * SEC_PER_DAY; 490 return rtc_tm_to_time64(tm) <= max_alarm_time64 ? 0 : -EINVAL; 491 } 492 493 static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 494 { 495 struct stm32_rtc *rtc = dev_get_drvdata(dev); 496 const struct stm32_rtc_registers *regs = &rtc->data->regs; 497 struct rtc_time *tm = &alrm->time; 498 unsigned int cr, isr, alrmar; 499 int ret = 0; 500 501 /* 502 * RTC alarm can't be set on a specific date, unless this date is 503 * up to the same day of month next month. 504 */ 505 if (stm32_rtc_valid_alrm(dev, tm) < 0) { 506 dev_err(dev, "Alarm can be set only on upcoming month.\n"); 507 return -EINVAL; 508 } 509 510 tm2bcd(tm); 511 512 alrmar = 0; 513 /* tm_year and tm_mon are not used because not supported by RTC */ 514 alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) & 515 STM32_RTC_ALRMXR_DATE; 516 /* 24-hour format */ 517 alrmar &= ~STM32_RTC_ALRMXR_PM; 518 alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) & 519 STM32_RTC_ALRMXR_HOUR; 520 alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) & 521 STM32_RTC_ALRMXR_MIN; 522 alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) & 523 STM32_RTC_ALRMXR_SEC; 524 525 stm32_rtc_wpr_unlock(rtc); 526 527 /* Disable Alarm */ 528 cr = readl_relaxed(rtc->base + regs->cr); 529 cr &= ~STM32_RTC_CR_ALRAE; 530 writel_relaxed(cr, rtc->base + regs->cr); 531 532 /* 533 * Poll Alarm write flag to be sure that Alarm update is allowed: it 534 * takes around 2 rtc_ck clock cycles 535 */ 536 ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, 537 isr, 538 (isr & STM32_RTC_ISR_ALRAWF), 539 10, 100000); 540 541 if (ret) { 542 dev_err(dev, "Alarm update not allowed\n"); 543 goto end; 544 } 545 546 /* Write to Alarm register */ 547 writel_relaxed(alrmar, rtc->base + regs->alrmar); 548 549 stm32_rtc_alarm_irq_enable(dev, alrm->enabled); 550 end: 551 stm32_rtc_wpr_lock(rtc); 552 553 return ret; 554 } 555 556 static const struct rtc_class_ops stm32_rtc_ops = { 557 .read_time = stm32_rtc_read_time, 558 .set_time = stm32_rtc_set_time, 559 .read_alarm = stm32_rtc_read_alarm, 560 .set_alarm = stm32_rtc_set_alarm, 561 .alarm_irq_enable = stm32_rtc_alarm_irq_enable, 562 }; 563 564 static void stm32_rtc_clear_events(struct stm32_rtc *rtc, 565 unsigned int flags) 566 { 567 const struct stm32_rtc_registers *regs = &rtc->data->regs; 568 569 /* Flags are cleared by writing 0 in RTC_ISR */ 570 writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags, 571 rtc->base + regs->isr); 572 } 573 574 static const struct stm32_rtc_data stm32_rtc_data = { 575 .has_pclk = false, 576 .need_dbp = true, 577 .need_accuracy = false, 578 .rif_protected = false, 579 .regs = { 580 .tr = 0x00, 581 .dr = 0x04, 582 .cr = 0x08, 583 .isr = 0x0C, 584 .prer = 0x10, 585 .alrmar = 0x1C, 586 .wpr = 0x24, 587 .sr = 0x0C, /* set to ISR offset to ease alarm management */ 588 .scr = UNDEF_REG, 589 .verr = UNDEF_REG, 590 }, 591 .events = { 592 .alra = STM32_RTC_ISR_ALRAF, 593 }, 594 .clear_events = stm32_rtc_clear_events, 595 }; 596 597 static const struct stm32_rtc_data stm32h7_rtc_data = { 598 .has_pclk = true, 599 .need_dbp = true, 600 .need_accuracy = false, 601 .rif_protected = false, 602 .regs = { 603 .tr = 0x00, 604 .dr = 0x04, 605 .cr = 0x08, 606 .isr = 0x0C, 607 .prer = 0x10, 608 .alrmar = 0x1C, 609 .wpr = 0x24, 610 .sr = 0x0C, /* set to ISR offset to ease alarm management */ 611 .scr = UNDEF_REG, 612 .verr = UNDEF_REG, 613 }, 614 .events = { 615 .alra = STM32_RTC_ISR_ALRAF, 616 }, 617 .clear_events = stm32_rtc_clear_events, 618 }; 619 620 static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc, 621 unsigned int flags) 622 { 623 struct stm32_rtc_registers regs = rtc->data->regs; 624 625 /* Flags are cleared by writing 1 in RTC_SCR */ 626 writel_relaxed(flags, rtc->base + regs.scr); 627 } 628 629 static const struct stm32_rtc_data stm32mp1_data = { 630 .has_pclk = true, 631 .need_dbp = false, 632 .need_accuracy = true, 633 .rif_protected = false, 634 .regs = { 635 .tr = 0x00, 636 .dr = 0x04, 637 .cr = 0x18, 638 .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */ 639 .prer = 0x10, 640 .alrmar = 0x40, 641 .wpr = 0x24, 642 .sr = 0x50, 643 .scr = 0x5C, 644 .verr = 0x3F4, 645 }, 646 .events = { 647 .alra = STM32_RTC_SR_ALRA, 648 }, 649 .clear_events = stm32mp1_rtc_clear_events, 650 }; 651 652 static const struct stm32_rtc_data stm32mp25_data = { 653 .has_pclk = true, 654 .need_dbp = false, 655 .need_accuracy = true, 656 .rif_protected = true, 657 .regs = { 658 .tr = 0x00, 659 .dr = 0x04, 660 .cr = 0x18, 661 .isr = 0x0C, /* named RTC_ICSR on stm32mp25 */ 662 .prer = 0x10, 663 .alrmar = 0x40, 664 .wpr = 0x24, 665 .sr = 0x50, 666 .scr = 0x5C, 667 .verr = 0x3F4, 668 }, 669 .events = { 670 .alra = STM32_RTC_SR_ALRA, 671 }, 672 .clear_events = stm32mp1_rtc_clear_events, 673 }; 674 675 static const struct of_device_id stm32_rtc_of_match[] = { 676 { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data }, 677 { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data }, 678 { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data }, 679 { .compatible = "st,stm32mp25-rtc", .data = &stm32mp25_data }, 680 {} 681 }; 682 MODULE_DEVICE_TABLE(of, stm32_rtc_of_match); 683 684 static int stm32_rtc_check_rif(struct stm32_rtc *stm32_rtc, 685 struct stm32_rtc_rif_resource res) 686 { 687 u32 rxcidcfgr = readl_relaxed(stm32_rtc->base + STM32_RTC_RXCIDCFGR(res.num)); 688 u32 seccfgr; 689 690 /* Check if RTC available for our CID */ 691 if ((rxcidcfgr & STM32_RTC_RXCIDCFGR_CFEN) && 692 (FIELD_GET(STM32_RTC_RXCIDCFGR_CID, rxcidcfgr) != STM32_RTC_RXCIDCFGR_CID1)) 693 return -EACCES; 694 695 /* Check if RTC available for non secure world */ 696 seccfgr = readl_relaxed(stm32_rtc->base + STM32_RTC_SECCFGR); 697 if ((seccfgr & STM32_RTC_SECCFGR_SEC) | (seccfgr & res.bit)) 698 return -EACCES; 699 700 return 0; 701 } 702 703 static int stm32_rtc_init(struct platform_device *pdev, 704 struct stm32_rtc *rtc) 705 { 706 const struct stm32_rtc_registers *regs = &rtc->data->regs; 707 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr; 708 unsigned int rate; 709 int ret; 710 711 rate = clk_get_rate(rtc->rtc_ck); 712 713 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */ 714 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT; 715 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT; 716 717 if (rate > (pred_a_max + 1) * (pred_s_max + 1)) { 718 dev_err(&pdev->dev, "rtc_ck rate is too high: %dHz\n", rate); 719 return -EINVAL; 720 } 721 722 if (rtc->data->need_accuracy) { 723 for (pred_a = 0; pred_a <= pred_a_max; pred_a++) { 724 pred_s = (rate / (pred_a + 1)) - 1; 725 726 if (pred_s <= pred_s_max && ((pred_s + 1) * (pred_a + 1)) == rate) 727 break; 728 } 729 } else { 730 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) { 731 pred_s = (rate / (pred_a + 1)) - 1; 732 733 if (((pred_s + 1) * (pred_a + 1)) == rate) 734 break; 735 } 736 } 737 738 /* 739 * Can't find a 1Hz, so give priority to RTC power consumption 740 * by choosing the higher possible value for prediv_a 741 */ 742 if (pred_s > pred_s_max || pred_a > pred_a_max) { 743 pred_a = pred_a_max; 744 pred_s = (rate / (pred_a + 1)) - 1; 745 746 dev_warn(&pdev->dev, "rtc_ck is %s\n", 747 (rate < ((pred_a + 1) * (pred_s + 1))) ? 748 "fast" : "slow"); 749 } 750 751 cr = readl_relaxed(rtc->base + regs->cr); 752 753 prer = readl_relaxed(rtc->base + regs->prer); 754 prer &= STM32_RTC_PRER_PRED_S | STM32_RTC_PRER_PRED_A; 755 756 pred_s = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & 757 STM32_RTC_PRER_PRED_S; 758 pred_a = (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & 759 STM32_RTC_PRER_PRED_A; 760 761 /* quit if there is nothing to initialize */ 762 if ((cr & STM32_RTC_CR_FMT) == 0 && prer == (pred_s | pred_a)) 763 return 0; 764 765 stm32_rtc_wpr_unlock(rtc); 766 767 ret = stm32_rtc_enter_init_mode(rtc); 768 if (ret) { 769 dev_err(&pdev->dev, 770 "Can't enter in init mode. Prescaler config failed.\n"); 771 goto end; 772 } 773 774 writel_relaxed(pred_s, rtc->base + regs->prer); 775 writel_relaxed(pred_a | pred_s, rtc->base + regs->prer); 776 777 /* Force 24h time format */ 778 cr &= ~STM32_RTC_CR_FMT; 779 writel_relaxed(cr, rtc->base + regs->cr); 780 781 stm32_rtc_exit_init_mode(rtc); 782 783 ret = stm32_rtc_wait_sync(rtc); 784 end: 785 stm32_rtc_wpr_lock(rtc); 786 787 return ret; 788 } 789 790 static int stm32_rtc_probe(struct platform_device *pdev) 791 { 792 struct stm32_rtc *rtc; 793 const struct stm32_rtc_registers *regs; 794 int ret; 795 796 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); 797 if (!rtc) 798 return -ENOMEM; 799 800 rtc->base = devm_platform_ioremap_resource(pdev, 0); 801 if (IS_ERR(rtc->base)) 802 return PTR_ERR(rtc->base); 803 804 rtc->data = (struct stm32_rtc_data *) 805 of_device_get_match_data(&pdev->dev); 806 regs = &rtc->data->regs; 807 808 if (rtc->data->need_dbp) { 809 rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 810 "st,syscfg"); 811 if (IS_ERR(rtc->dbp)) { 812 dev_err(&pdev->dev, "no st,syscfg\n"); 813 return PTR_ERR(rtc->dbp); 814 } 815 816 ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg", 817 1, &rtc->dbp_reg); 818 if (ret) { 819 dev_err(&pdev->dev, "can't read DBP register offset\n"); 820 return ret; 821 } 822 823 ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg", 824 2, &rtc->dbp_mask); 825 if (ret) { 826 dev_err(&pdev->dev, "can't read DBP register mask\n"); 827 return ret; 828 } 829 } 830 831 if (!rtc->data->has_pclk) { 832 rtc->pclk = NULL; 833 rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL); 834 } else { 835 rtc->pclk = devm_clk_get(&pdev->dev, "pclk"); 836 if (IS_ERR(rtc->pclk)) 837 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->pclk), "no pclk clock"); 838 839 rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck"); 840 } 841 if (IS_ERR(rtc->rtc_ck)) 842 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->rtc_ck), "no rtc_ck clock"); 843 844 if (rtc->data->has_pclk) { 845 ret = clk_prepare_enable(rtc->pclk); 846 if (ret) 847 return ret; 848 } 849 850 ret = clk_prepare_enable(rtc->rtc_ck); 851 if (ret) 852 goto err_no_rtc_ck; 853 854 if (rtc->data->need_dbp) 855 regmap_update_bits(rtc->dbp, rtc->dbp_reg, 856 rtc->dbp_mask, rtc->dbp_mask); 857 858 if (rtc->data->rif_protected) { 859 ret = stm32_rtc_check_rif(rtc, STM32_RTC_RES_INIT); 860 if (!ret) 861 ret = stm32_rtc_check_rif(rtc, STM32_RTC_RES_ALRA); 862 if (ret) { 863 dev_err(&pdev->dev, "Failed to probe RTC due to RIF configuration\n"); 864 goto err; 865 } 866 } 867 868 /* 869 * After a system reset, RTC_ISR.INITS flag can be read to check if 870 * the calendar has been initialized or not. INITS flag is reset by a 871 * power-on reset (no vbat, no power-supply). It is not reset if 872 * rtc_ck parent clock has changed (so RTC prescalers need to be 873 * changed). That's why we cannot rely on this flag to know if RTC 874 * init has to be done. 875 */ 876 ret = stm32_rtc_init(pdev, rtc); 877 if (ret) 878 goto err; 879 880 rtc->irq_alarm = platform_get_irq(pdev, 0); 881 if (rtc->irq_alarm <= 0) { 882 ret = rtc->irq_alarm; 883 goto err; 884 } 885 886 ret = device_init_wakeup(&pdev->dev, true); 887 if (ret) 888 goto err; 889 890 ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq_alarm); 891 if (ret) 892 goto err; 893 894 platform_set_drvdata(pdev, rtc); 895 896 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name, 897 &stm32_rtc_ops, THIS_MODULE); 898 if (IS_ERR(rtc->rtc_dev)) { 899 ret = PTR_ERR(rtc->rtc_dev); 900 dev_err(&pdev->dev, "rtc device registration failed, err=%d\n", 901 ret); 902 goto err; 903 } 904 905 /* Handle RTC alarm interrupts */ 906 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL, 907 stm32_rtc_alarm_irq, IRQF_ONESHOT, 908 pdev->name, rtc); 909 if (ret) { 910 dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n", 911 rtc->irq_alarm); 912 goto err; 913 } 914 915 /* 916 * If INITS flag is reset (calendar year field set to 0x00), calendar 917 * must be initialized 918 */ 919 if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS)) 920 dev_warn(&pdev->dev, "Date/Time must be initialized\n"); 921 922 if (regs->verr != UNDEF_REG) { 923 u32 ver = readl_relaxed(rtc->base + regs->verr); 924 925 dev_info(&pdev->dev, "registered rev:%d.%d\n", 926 (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF, 927 (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF); 928 } 929 930 return 0; 931 932 err: 933 clk_disable_unprepare(rtc->rtc_ck); 934 err_no_rtc_ck: 935 if (rtc->data->has_pclk) 936 clk_disable_unprepare(rtc->pclk); 937 938 if (rtc->data->need_dbp) 939 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0); 940 941 dev_pm_clear_wake_irq(&pdev->dev); 942 device_init_wakeup(&pdev->dev, false); 943 944 return ret; 945 } 946 947 static void stm32_rtc_remove(struct platform_device *pdev) 948 { 949 struct stm32_rtc *rtc = platform_get_drvdata(pdev); 950 const struct stm32_rtc_registers *regs = &rtc->data->regs; 951 unsigned int cr; 952 953 /* Disable interrupts */ 954 stm32_rtc_wpr_unlock(rtc); 955 cr = readl_relaxed(rtc->base + regs->cr); 956 cr &= ~STM32_RTC_CR_ALRAIE; 957 writel_relaxed(cr, rtc->base + regs->cr); 958 stm32_rtc_wpr_lock(rtc); 959 960 clk_disable_unprepare(rtc->rtc_ck); 961 if (rtc->data->has_pclk) 962 clk_disable_unprepare(rtc->pclk); 963 964 /* Enable backup domain write protection if needed */ 965 if (rtc->data->need_dbp) 966 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0); 967 968 dev_pm_clear_wake_irq(&pdev->dev); 969 device_init_wakeup(&pdev->dev, false); 970 } 971 972 static int stm32_rtc_suspend(struct device *dev) 973 { 974 struct stm32_rtc *rtc = dev_get_drvdata(dev); 975 976 if (rtc->data->has_pclk) 977 clk_disable_unprepare(rtc->pclk); 978 979 return 0; 980 } 981 982 static int stm32_rtc_resume(struct device *dev) 983 { 984 struct stm32_rtc *rtc = dev_get_drvdata(dev); 985 int ret = 0; 986 987 if (rtc->data->has_pclk) { 988 ret = clk_prepare_enable(rtc->pclk); 989 if (ret) 990 return ret; 991 } 992 993 ret = stm32_rtc_wait_sync(rtc); 994 if (ret < 0) { 995 if (rtc->data->has_pclk) 996 clk_disable_unprepare(rtc->pclk); 997 return ret; 998 } 999 1000 return ret; 1001 } 1002 1003 static const struct dev_pm_ops stm32_rtc_pm_ops = { 1004 NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_rtc_suspend, stm32_rtc_resume) 1005 }; 1006 1007 static struct platform_driver stm32_rtc_driver = { 1008 .probe = stm32_rtc_probe, 1009 .remove_new = stm32_rtc_remove, 1010 .driver = { 1011 .name = DRIVER_NAME, 1012 .pm = &stm32_rtc_pm_ops, 1013 .of_match_table = stm32_rtc_of_match, 1014 }, 1015 }; 1016 1017 module_platform_driver(stm32_rtc_driver); 1018 1019 MODULE_ALIAS("platform:" DRIVER_NAME); 1020 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 1021 MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver"); 1022 MODULE_LICENSE("GPL v2"); 1023