1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2b9d7c5d3SArnd Bergmann /* 3b9d7c5d3SArnd Bergmann * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 4b9d7c5d3SArnd Bergmann * http://www.simtec.co.uk/products/SWLINUX/ 5b9d7c5d3SArnd Bergmann * 6b9d7c5d3SArnd Bergmann * S3C2410 Internal RTC register definition 7b9d7c5d3SArnd Bergmann */ 8b9d7c5d3SArnd Bergmann 9b9d7c5d3SArnd Bergmann #ifndef __ASM_ARCH_REGS_RTC_H 10b9d7c5d3SArnd Bergmann #define __ASM_ARCH_REGS_RTC_H __FILE__ 11b9d7c5d3SArnd Bergmann 12b9d7c5d3SArnd Bergmann #define S3C2410_RTCREG(x) (x) 13b9d7c5d3SArnd Bergmann #define S3C2410_INTP S3C2410_RTCREG(0x30) 14b9d7c5d3SArnd Bergmann #define S3C2410_INTP_ALM (1 << 1) 15b9d7c5d3SArnd Bergmann #define S3C2410_INTP_TIC (1 << 0) 16b9d7c5d3SArnd Bergmann 17b9d7c5d3SArnd Bergmann #define S3C2410_RTCCON S3C2410_RTCREG(0x40) 18b9d7c5d3SArnd Bergmann #define S3C2410_RTCCON_RTCEN (1 << 0) 19b9d7c5d3SArnd Bergmann #define S3C2410_RTCCON_CNTSEL (1 << 2) 20b9d7c5d3SArnd Bergmann #define S3C2410_RTCCON_CLKRST (1 << 3) 21b9d7c5d3SArnd Bergmann #define S3C2443_RTCCON_TICSEL (1 << 4) 22b9d7c5d3SArnd Bergmann #define S3C64XX_RTCCON_TICEN (1 << 8) 23b9d7c5d3SArnd Bergmann 24b9d7c5d3SArnd Bergmann #define S3C2410_TICNT S3C2410_RTCREG(0x44) 25b9d7c5d3SArnd Bergmann #define S3C2410_TICNT_ENABLE (1 << 7) 26b9d7c5d3SArnd Bergmann 27b9d7c5d3SArnd Bergmann /* S3C2443: tick count is 15 bit wide 28b9d7c5d3SArnd Bergmann * TICNT[6:0] contains upper 7 bits 29b9d7c5d3SArnd Bergmann * TICNT1[7:0] contains lower 8 bits 30b9d7c5d3SArnd Bergmann */ 31b9d7c5d3SArnd Bergmann #define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8) 32b9d7c5d3SArnd Bergmann #define S3C2443_TICNT1 S3C2410_RTCREG(0x4C) 33b9d7c5d3SArnd Bergmann #define S3C2443_TICNT1_PART(x) (x & 0xff) 34b9d7c5d3SArnd Bergmann 35b9d7c5d3SArnd Bergmann /* S3C2416: tick count is 32 bit wide 36b9d7c5d3SArnd Bergmann * TICNT[6:0] contains bits [14:8] 37b9d7c5d3SArnd Bergmann * TICNT1[7:0] contains lower 8 bits 38b9d7c5d3SArnd Bergmann * TICNT2[16:0] contains upper 17 bits 39b9d7c5d3SArnd Bergmann */ 40b9d7c5d3SArnd Bergmann #define S3C2416_TICNT2 S3C2410_RTCREG(0x48) 41b9d7c5d3SArnd Bergmann #define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15) 42b9d7c5d3SArnd Bergmann 43b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM S3C2410_RTCREG(0x50) 44b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_ALMEN (1 << 6) 45b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_YEAREN (1 << 5) 46b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_MONEN (1 << 4) 47b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_DAYEN (1 << 3) 48b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_HOUREN (1 << 2) 49b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_MINEN (1 << 1) 50b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_SECEN (1 << 0) 51b9d7c5d3SArnd Bergmann 52b9d7c5d3SArnd Bergmann #define S3C2410_ALMSEC S3C2410_RTCREG(0x54) 53b9d7c5d3SArnd Bergmann #define S3C2410_ALMMIN S3C2410_RTCREG(0x58) 54b9d7c5d3SArnd Bergmann #define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) 55b9d7c5d3SArnd Bergmann 56b9d7c5d3SArnd Bergmann #define S3C2410_ALMDATE S3C2410_RTCREG(0x60) 57b9d7c5d3SArnd Bergmann #define S3C2410_ALMMON S3C2410_RTCREG(0x64) 58b9d7c5d3SArnd Bergmann #define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) 59b9d7c5d3SArnd Bergmann 60b9d7c5d3SArnd Bergmann #define S3C2410_RTCSEC S3C2410_RTCREG(0x70) 61b9d7c5d3SArnd Bergmann #define S3C2410_RTCMIN S3C2410_RTCREG(0x74) 62b9d7c5d3SArnd Bergmann #define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) 63b9d7c5d3SArnd Bergmann #define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) 64b9d7c5d3SArnd Bergmann #define S3C2410_RTCMON S3C2410_RTCREG(0x84) 65b9d7c5d3SArnd Bergmann #define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) 66b9d7c5d3SArnd Bergmann 67b9d7c5d3SArnd Bergmann #endif /* __ASM_ARCH_REGS_RTC_H */ 68