1*b9d7c5d3SArnd Bergmann /* 2*b9d7c5d3SArnd Bergmann * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 3*b9d7c5d3SArnd Bergmann * http://www.simtec.co.uk/products/SWLINUX/ 4*b9d7c5d3SArnd Bergmann * 5*b9d7c5d3SArnd Bergmann * This program is free software; you can redistribute it and/or modify 6*b9d7c5d3SArnd Bergmann * it under the terms of the GNU General Public License version 2 as 7*b9d7c5d3SArnd Bergmann * published by the Free Software Foundation. 8*b9d7c5d3SArnd Bergmann * 9*b9d7c5d3SArnd Bergmann * S3C2410 Internal RTC register definition 10*b9d7c5d3SArnd Bergmann */ 11*b9d7c5d3SArnd Bergmann 12*b9d7c5d3SArnd Bergmann #ifndef __ASM_ARCH_REGS_RTC_H 13*b9d7c5d3SArnd Bergmann #define __ASM_ARCH_REGS_RTC_H __FILE__ 14*b9d7c5d3SArnd Bergmann 15*b9d7c5d3SArnd Bergmann #define S3C2410_RTCREG(x) (x) 16*b9d7c5d3SArnd Bergmann #define S3C2410_INTP S3C2410_RTCREG(0x30) 17*b9d7c5d3SArnd Bergmann #define S3C2410_INTP_ALM (1 << 1) 18*b9d7c5d3SArnd Bergmann #define S3C2410_INTP_TIC (1 << 0) 19*b9d7c5d3SArnd Bergmann 20*b9d7c5d3SArnd Bergmann #define S3C2410_RTCCON S3C2410_RTCREG(0x40) 21*b9d7c5d3SArnd Bergmann #define S3C2410_RTCCON_RTCEN (1 << 0) 22*b9d7c5d3SArnd Bergmann #define S3C2410_RTCCON_CNTSEL (1 << 2) 23*b9d7c5d3SArnd Bergmann #define S3C2410_RTCCON_CLKRST (1 << 3) 24*b9d7c5d3SArnd Bergmann #define S3C2443_RTCCON_TICSEL (1 << 4) 25*b9d7c5d3SArnd Bergmann #define S3C64XX_RTCCON_TICEN (1 << 8) 26*b9d7c5d3SArnd Bergmann 27*b9d7c5d3SArnd Bergmann #define S3C2410_TICNT S3C2410_RTCREG(0x44) 28*b9d7c5d3SArnd Bergmann #define S3C2410_TICNT_ENABLE (1 << 7) 29*b9d7c5d3SArnd Bergmann 30*b9d7c5d3SArnd Bergmann /* S3C2443: tick count is 15 bit wide 31*b9d7c5d3SArnd Bergmann * TICNT[6:0] contains upper 7 bits 32*b9d7c5d3SArnd Bergmann * TICNT1[7:0] contains lower 8 bits 33*b9d7c5d3SArnd Bergmann */ 34*b9d7c5d3SArnd Bergmann #define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8) 35*b9d7c5d3SArnd Bergmann #define S3C2443_TICNT1 S3C2410_RTCREG(0x4C) 36*b9d7c5d3SArnd Bergmann #define S3C2443_TICNT1_PART(x) (x & 0xff) 37*b9d7c5d3SArnd Bergmann 38*b9d7c5d3SArnd Bergmann /* S3C2416: tick count is 32 bit wide 39*b9d7c5d3SArnd Bergmann * TICNT[6:0] contains bits [14:8] 40*b9d7c5d3SArnd Bergmann * TICNT1[7:0] contains lower 8 bits 41*b9d7c5d3SArnd Bergmann * TICNT2[16:0] contains upper 17 bits 42*b9d7c5d3SArnd Bergmann */ 43*b9d7c5d3SArnd Bergmann #define S3C2416_TICNT2 S3C2410_RTCREG(0x48) 44*b9d7c5d3SArnd Bergmann #define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15) 45*b9d7c5d3SArnd Bergmann 46*b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM S3C2410_RTCREG(0x50) 47*b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_ALMEN (1 << 6) 48*b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_YEAREN (1 << 5) 49*b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_MONEN (1 << 4) 50*b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_DAYEN (1 << 3) 51*b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_HOUREN (1 << 2) 52*b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_MINEN (1 << 1) 53*b9d7c5d3SArnd Bergmann #define S3C2410_RTCALM_SECEN (1 << 0) 54*b9d7c5d3SArnd Bergmann 55*b9d7c5d3SArnd Bergmann #define S3C2410_ALMSEC S3C2410_RTCREG(0x54) 56*b9d7c5d3SArnd Bergmann #define S3C2410_ALMMIN S3C2410_RTCREG(0x58) 57*b9d7c5d3SArnd Bergmann #define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c) 58*b9d7c5d3SArnd Bergmann 59*b9d7c5d3SArnd Bergmann #define S3C2410_ALMDATE S3C2410_RTCREG(0x60) 60*b9d7c5d3SArnd Bergmann #define S3C2410_ALMMON S3C2410_RTCREG(0x64) 61*b9d7c5d3SArnd Bergmann #define S3C2410_ALMYEAR S3C2410_RTCREG(0x68) 62*b9d7c5d3SArnd Bergmann 63*b9d7c5d3SArnd Bergmann #define S3C2410_RTCSEC S3C2410_RTCREG(0x70) 64*b9d7c5d3SArnd Bergmann #define S3C2410_RTCMIN S3C2410_RTCREG(0x74) 65*b9d7c5d3SArnd Bergmann #define S3C2410_RTCHOUR S3C2410_RTCREG(0x78) 66*b9d7c5d3SArnd Bergmann #define S3C2410_RTCDATE S3C2410_RTCREG(0x7c) 67*b9d7c5d3SArnd Bergmann #define S3C2410_RTCMON S3C2410_RTCREG(0x84) 68*b9d7c5d3SArnd Bergmann #define S3C2410_RTCYEAR S3C2410_RTCREG(0x88) 69*b9d7c5d3SArnd Bergmann 70*b9d7c5d3SArnd Bergmann #endif /* __ASM_ARCH_REGS_RTC_H */ 71