1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Renesas RZ/N1 Real Time Clock interface for Linux 4 * 5 * Copyright: 6 * - 2014 Renesas Electronics Europe Limited 7 * - 2022 Schneider Electric 8 * 9 * Authors: 10 * - Michel Pollet <buserror@gmail.com> 11 * - Miquel Raynal <miquel.raynal@bootlin.com> 12 */ 13 14 #include <linux/bcd.h> 15 #include <linux/bitfield.h> 16 #include <linux/bits.h> 17 #include <linux/clk.h> 18 #include <linux/init.h> 19 #include <linux/iopoll.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/rtc.h> 25 #include <linux/spinlock.h> 26 27 #define RZN1_RTC_CTL0 0x00 28 #define RZN1_RTC_CTL0_SLSB_SCMP BIT(4) 29 #define RZN1_RTC_CTL0_AMPM BIT(5) 30 #define RZN1_RTC_CTL0_CEST BIT(6) 31 #define RZN1_RTC_CTL0_CE BIT(7) 32 33 #define RZN1_RTC_CTL1 0x04 34 #define RZN1_RTC_CTL1_1SE BIT(3) 35 #define RZN1_RTC_CTL1_ALME BIT(4) 36 37 #define RZN1_RTC_CTL2 0x08 38 #define RZN1_RTC_CTL2_WAIT BIT(0) 39 #define RZN1_RTC_CTL2_WST BIT(1) 40 #define RZN1_RTC_CTL2_WUST BIT(5) 41 #define RZN1_RTC_CTL2_STOPPED (RZN1_RTC_CTL2_WAIT | RZN1_RTC_CTL2_WST) 42 43 #define RZN1_RTC_TIME 0x30 44 #define RZN1_RTC_TIME_SEC GENMASK(7, 0) 45 #define RZN1_RTC_TIME_MIN GENMASK(15, 8) 46 #define RZN1_RTC_TIME_HOUR GENMASK(23, 16) 47 48 #define RZN1_RTC_CAL 0x34 49 #define RZN1_RTC_CAL_WDAY GENMASK(7, 0) 50 #define RZN1_RTC_CAL_DAY GENMASK(15, 8) 51 #define RZN1_RTC_CAL_MON GENMASK(23, 16) 52 #define RZN1_RTC_CAL_YEAR GENMASK(31, 24) 53 54 #define RZN1_RTC_SUBU 0x38 55 #define RZN1_RTC_SUBU_RTCA0FX GENMASK(5, 0) 56 #define RZN1_RTC_SUBU_DEV BIT(7) 57 #define RZN1_RTC_SUBU_DECR BIT(6) 58 59 #define RZN1_RTC_SCMP 0x3c 60 61 #define RZN1_RTC_ALM 0x40 62 #define RZN1_RTC_ALH 0x44 63 #define RZN1_RTC_ALW 0x48 64 65 #define RZN1_RTC_SECC 0x4c 66 #define RZN1_RTC_TIMEC 0x68 67 #define RZN1_RTC_CALC 0x6c 68 69 struct rzn1_rtc_data { 70 bool has_subu; 71 }; 72 73 struct rzn1_rtc { 74 struct rtc_device *rtcdev; 75 void __iomem *base; 76 /* 77 * Protects access to RZN1_RTC_CTL1 reg. rtc_lock with threaded_irqs 78 * would introduce race conditions when switching interrupts because 79 * of potential sleeps 80 */ 81 spinlock_t ctl1_access_lock; 82 struct rtc_time tm_alarm; 83 unsigned long sync_time; 84 }; 85 86 static void rzn1_rtc_get_time_snapshot(struct rzn1_rtc *rtc, struct rtc_time *tm) 87 { 88 u32 val; 89 90 val = readl(rtc->base + RZN1_RTC_TIMEC); 91 tm->tm_sec = bcd2bin(FIELD_GET(RZN1_RTC_TIME_SEC, val)); 92 tm->tm_min = bcd2bin(FIELD_GET(RZN1_RTC_TIME_MIN, val)); 93 tm->tm_hour = bcd2bin(FIELD_GET(RZN1_RTC_TIME_HOUR, val)); 94 95 val = readl(rtc->base + RZN1_RTC_CALC); 96 tm->tm_wday = FIELD_GET(RZN1_RTC_CAL_WDAY, val); 97 tm->tm_mday = bcd2bin(FIELD_GET(RZN1_RTC_CAL_DAY, val)); 98 tm->tm_mon = bcd2bin(FIELD_GET(RZN1_RTC_CAL_MON, val)) - 1; 99 tm->tm_year = bcd2bin(FIELD_GET(RZN1_RTC_CAL_YEAR, val)) + 100; 100 } 101 102 static int rzn1_rtc_read_time(struct device *dev, struct rtc_time *tm) 103 { 104 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 105 u32 val, secs; 106 107 /* 108 * The RTC was not started or is stopped and thus does not carry the 109 * proper time/date. 110 */ 111 val = readl(rtc->base + RZN1_RTC_CTL2); 112 if (val & RZN1_RTC_CTL2_STOPPED) 113 return -EINVAL; 114 115 rzn1_rtc_get_time_snapshot(rtc, tm); 116 secs = readl(rtc->base + RZN1_RTC_SECC); 117 if (tm->tm_sec != bcd2bin(secs)) 118 rzn1_rtc_get_time_snapshot(rtc, tm); 119 120 return 0; 121 } 122 123 static int rzn1_rtc_set_time(struct device *dev, struct rtc_time *tm) 124 { 125 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 126 u32 val; 127 int ret; 128 129 val = readl(rtc->base + RZN1_RTC_CTL2); 130 if (!(val & RZN1_RTC_CTL2_STOPPED)) { 131 /* Hold the counter if it was counting up */ 132 writel(RZN1_RTC_CTL2_WAIT, rtc->base + RZN1_RTC_CTL2); 133 134 /* Wait 2-4 RTC_PCLK clock cycles for the counter to stop */ 135 usleep_range(rtc->sync_time, rtc->sync_time * 2); 136 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val, 137 val & RZN1_RTC_CTL2_WST, 0, 100); 138 if (ret) 139 return ret; 140 } 141 142 val = FIELD_PREP(RZN1_RTC_TIME_SEC, bin2bcd(tm->tm_sec)) | 143 FIELD_PREP(RZN1_RTC_TIME_MIN, bin2bcd(tm->tm_min)) | 144 FIELD_PREP(RZN1_RTC_TIME_HOUR, bin2bcd(tm->tm_hour)); 145 writel(val, rtc->base + RZN1_RTC_TIME); 146 147 val = FIELD_PREP(RZN1_RTC_CAL_WDAY, tm->tm_wday) | 148 FIELD_PREP(RZN1_RTC_CAL_DAY, bin2bcd(tm->tm_mday)) | 149 FIELD_PREP(RZN1_RTC_CAL_MON, bin2bcd(tm->tm_mon + 1)) | 150 FIELD_PREP(RZN1_RTC_CAL_YEAR, bin2bcd(tm->tm_year - 100)); 151 writel(val, rtc->base + RZN1_RTC_CAL); 152 153 writel(0, rtc->base + RZN1_RTC_CTL2); 154 155 return 0; 156 } 157 158 static irqreturn_t rzn1_rtc_alarm_irq(int irq, void *dev_id) 159 { 160 struct rzn1_rtc *rtc = dev_id; 161 u32 ctl1, set_irq_bits = 0; 162 163 if (rtc->tm_alarm.tm_sec == 0) 164 rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF); 165 else 166 /* Switch to 1s interrupts */ 167 set_irq_bits = RZN1_RTC_CTL1_1SE; 168 169 guard(spinlock)(&rtc->ctl1_access_lock); 170 171 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); 172 ctl1 &= ~RZN1_RTC_CTL1_ALME; 173 ctl1 |= set_irq_bits; 174 writel(ctl1, rtc->base + RZN1_RTC_CTL1); 175 176 return IRQ_HANDLED; 177 } 178 179 static irqreturn_t rzn1_rtc_1s_irq(int irq, void *dev_id) 180 { 181 struct rzn1_rtc *rtc = dev_id; 182 u32 ctl1; 183 184 if (readl(rtc->base + RZN1_RTC_SECC) == bin2bcd(rtc->tm_alarm.tm_sec)) { 185 guard(spinlock)(&rtc->ctl1_access_lock); 186 187 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); 188 ctl1 &= ~RZN1_RTC_CTL1_1SE; 189 writel(ctl1, rtc->base + RZN1_RTC_CTL1); 190 191 rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF); 192 } 193 194 return IRQ_HANDLED; 195 } 196 197 static int rzn1_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) 198 { 199 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 200 struct rtc_time *tm = &rtc->tm_alarm, tm_now; 201 u32 ctl1; 202 int ret; 203 204 guard(spinlock_irqsave)(&rtc->ctl1_access_lock); 205 206 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); 207 208 if (enable) { 209 /* 210 * Use alarm interrupt if alarm time is at least a minute away 211 * or less than a minute but in the next minute. Otherwise use 212 * 1 second interrupt to wait for the proper second 213 */ 214 do { 215 ctl1 &= ~(RZN1_RTC_CTL1_ALME | RZN1_RTC_CTL1_1SE); 216 217 ret = rzn1_rtc_read_time(dev, &tm_now); 218 if (ret) 219 return ret; 220 221 if (rtc_tm_sub(tm, &tm_now) > 59 || tm->tm_min != tm_now.tm_min) 222 ctl1 |= RZN1_RTC_CTL1_ALME; 223 else 224 ctl1 |= RZN1_RTC_CTL1_1SE; 225 226 writel(ctl1, rtc->base + RZN1_RTC_CTL1); 227 } while (readl(rtc->base + RZN1_RTC_SECC) != bin2bcd(tm_now.tm_sec)); 228 } else { 229 ctl1 &= ~(RZN1_RTC_CTL1_ALME | RZN1_RTC_CTL1_1SE); 230 writel(ctl1, rtc->base + RZN1_RTC_CTL1); 231 } 232 233 return 0; 234 } 235 236 static int rzn1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) 237 { 238 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 239 struct rtc_time *tm = &alrm->time; 240 unsigned int min, hour, wday, delta_days; 241 time64_t alarm; 242 u32 ctl1; 243 int ret; 244 245 ret = rzn1_rtc_read_time(dev, tm); 246 if (ret) 247 return ret; 248 249 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); 250 alrm->enabled = !!(ctl1 & (RZN1_RTC_CTL1_ALME | RZN1_RTC_CTL1_1SE)); 251 252 min = readl(rtc->base + RZN1_RTC_ALM); 253 hour = readl(rtc->base + RZN1_RTC_ALH); 254 255 tm->tm_sec = 0; 256 tm->tm_min = bcd2bin(min); 257 tm->tm_hour = bcd2bin(hour); 258 259 /* 260 * If wday is zero, no bit is set in RZN1_RTC_ALW. This is the 261 * register's power-on reset value. 262 */ 263 wday = readl(rtc->base + RZN1_RTC_ALW); 264 if (!wday) 265 return 0; 266 267 delta_days = ((fls(wday) - 1) - tm->tm_wday + 7) % 7; 268 tm->tm_wday = fls(wday) - 1; 269 270 if (delta_days) { 271 alarm = rtc_tm_to_time64(tm) + (delta_days * 86400); 272 rtc_time64_to_tm(alarm, tm); 273 } 274 275 return 0; 276 } 277 278 static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) 279 { 280 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 281 struct rtc_time *tm = &alrm->time, tm_now; 282 time64_t alarm, farest; 283 int ret; 284 285 ret = rzn1_rtc_read_time(dev, &tm_now); 286 if (ret) 287 return ret; 288 289 /* We cannot set alarms more than one week ahead */ 290 farest = rtc_tm_to_time64(&tm_now) + rtc->rtcdev->alarm_offset_max; 291 alarm = rtc_tm_to_time64(tm); 292 if (alarm > farest) 293 return -ERANGE; 294 295 /* Disable alarm interrupts before reprogramming the alarm. */ 296 ret = rzn1_rtc_alarm_irq_enable(dev, 0); 297 if (ret) 298 return ret; 299 300 writel(bin2bcd(tm->tm_min), rtc->base + RZN1_RTC_ALM); 301 writel(bin2bcd(tm->tm_hour), rtc->base + RZN1_RTC_ALH); 302 writel(BIT(tm->tm_wday), rtc->base + RZN1_RTC_ALW); 303 304 rtc->tm_alarm = alrm->time; 305 306 rzn1_rtc_alarm_irq_enable(dev, alrm->enabled); 307 308 return 0; 309 } 310 311 static int rzn1_rtc_read_offset(struct device *dev, long *offset) 312 { 313 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 314 unsigned int ppb_per_step; 315 bool subtract; 316 u32 val; 317 318 val = readl(rtc->base + RZN1_RTC_SUBU); 319 ppb_per_step = val & RZN1_RTC_SUBU_DEV ? 1017 : 3051; 320 subtract = val & RZN1_RTC_SUBU_DECR; 321 val = FIELD_GET(RZN1_RTC_SUBU_RTCA0FX, val); 322 323 if (!val) 324 *offset = 0; 325 else if (subtract) 326 *offset = -(((~val) & RZN1_RTC_SUBU_RTCA0FX) + 1) * ppb_per_step; 327 else 328 *offset = (val - 1) * ppb_per_step; 329 330 return 0; 331 } 332 333 static int rzn1_rtc_set_offset(struct device *dev, long offset) 334 { 335 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 336 int stepsh, stepsl, steps; 337 u32 subu = 0, ctl2; 338 int ret; 339 340 /* 341 * Check which resolution mode (every 20 or 60s) can be used. 342 * Between 2 and 124 clock pulses can be added or substracted. 343 * 344 * In 20s mode, the minimum resolution is 2 / (32768 * 20) which is 345 * close to 3051 ppb. In 60s mode, the resolution is closer to 1017. 346 */ 347 stepsh = DIV_ROUND_CLOSEST(offset, 1017); 348 stepsl = DIV_ROUND_CLOSEST(offset, 3051); 349 350 if (stepsh >= -0x3E && stepsh <= 0x3E) { 351 /* 1017 ppb per step */ 352 steps = stepsh; 353 subu |= RZN1_RTC_SUBU_DEV; 354 } else if (stepsl >= -0x3E && stepsl <= 0x3E) { 355 /* 3051 ppb per step */ 356 steps = stepsl; 357 } else { 358 return -ERANGE; 359 } 360 361 if (!steps) 362 return 0; 363 364 if (steps > 0) { 365 subu |= steps + 1; 366 } else { 367 subu |= RZN1_RTC_SUBU_DECR; 368 subu |= (~(-steps - 1)) & RZN1_RTC_SUBU_RTCA0FX; 369 } 370 371 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2, 372 !(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000); 373 if (ret) 374 return ret; 375 376 writel(subu, rtc->base + RZN1_RTC_SUBU); 377 378 return 0; 379 } 380 381 static const struct rtc_class_ops rzn1_rtc_ops_subu = { 382 .read_time = rzn1_rtc_read_time, 383 .set_time = rzn1_rtc_set_time, 384 .read_alarm = rzn1_rtc_read_alarm, 385 .set_alarm = rzn1_rtc_set_alarm, 386 .alarm_irq_enable = rzn1_rtc_alarm_irq_enable, 387 .read_offset = rzn1_rtc_read_offset, 388 .set_offset = rzn1_rtc_set_offset, 389 }; 390 391 static const struct rtc_class_ops rzn1_rtc_ops_scmp = { 392 .read_time = rzn1_rtc_read_time, 393 .set_time = rzn1_rtc_set_time, 394 .read_alarm = rzn1_rtc_read_alarm, 395 .set_alarm = rzn1_rtc_set_alarm, 396 .alarm_irq_enable = rzn1_rtc_alarm_irq_enable, 397 }; 398 399 static void rzn1_rtc_disable_hardware(void *data) 400 { 401 struct device *dev = data; 402 struct rzn1_rtc *rtc = dev_get_drvdata(dev); 403 404 /* Disable all interrupts */ 405 writel(0, rtc->base + RZN1_RTC_CTL1); 406 407 pm_runtime_put_sync(dev); 408 } 409 410 static int rzn1_rtc_probe(struct platform_device *pdev) 411 { 412 const struct rzn1_rtc_data *data; 413 struct device *dev = &pdev->dev; 414 unsigned long rate = 32768; 415 struct rzn1_rtc *rtc; 416 u32 val, scmp_val = 0; 417 struct clk *xtal; 418 int irq, ret; 419 420 data = of_device_get_match_data(dev); 421 if (!data) 422 return -ENODEV; 423 424 rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL); 425 if (!rtc) 426 return -ENOMEM; 427 428 platform_set_drvdata(pdev, rtc); 429 430 rtc->base = devm_platform_ioremap_resource(pdev, 0); 431 if (IS_ERR(rtc->base)) 432 return dev_err_probe(dev, PTR_ERR(rtc->base), "Missing reg\n"); 433 434 irq = platform_get_irq_byname(pdev, "alarm"); 435 if (irq < 0) 436 return irq; 437 438 rtc->rtcdev = devm_rtc_allocate_device(dev); 439 if (IS_ERR(rtc->rtcdev)) 440 return PTR_ERR(rtc->rtcdev); 441 442 rtc->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000; 443 rtc->rtcdev->range_max = RTC_TIMESTAMP_END_2099; 444 rtc->rtcdev->alarm_offset_max = 7 * 86400; 445 446 ret = devm_pm_runtime_enable(dev); 447 if (ret < 0) 448 return ret; 449 ret = pm_runtime_resume_and_get(dev); 450 if (ret < 0) 451 return ret; 452 453 ret = devm_add_action_or_reset(dev, rzn1_rtc_disable_hardware, dev); 454 if (ret) 455 return ret; 456 457 /* Only switch to scmp if we have an xtal clock with a valid rate and != 32768 */ 458 xtal = devm_clk_get_optional(dev, "xtal"); 459 if (IS_ERR(xtal)) { 460 return PTR_ERR(xtal); 461 } else if (xtal) { 462 rate = clk_get_rate(xtal); 463 464 if (rate < 32000 || rate > BIT(22)) 465 return -EOPNOTSUPP; 466 467 if (rate != 32768 || !data->has_subu) 468 scmp_val = RZN1_RTC_CTL0_SLSB_SCMP; 469 } else if (!data->has_subu) { 470 /* xtal is NULL here */ 471 return dev_err_probe(dev, -EOPNOTSUPP, 472 "No valid XTAL provided and SUBU mode not supported\n"); 473 } 474 475 /* Calculate the duration of two RTC_PCLK clock cycles */ 476 rtc->sync_time = DIV_ROUND_UP(2 * USEC_PER_SEC, rate); 477 478 /* Disable controller during SUBU/SCMP setup */ 479 val = readl(rtc->base + RZN1_RTC_CTL0) & ~RZN1_RTC_CTL0_CE; 480 writel(val, rtc->base + RZN1_RTC_CTL0); 481 /* Wait 2-4 RTC_PCLK clock cycles for the disabled controller to stop */ 482 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL0, val, 483 !(val & RZN1_RTC_CTL0_CEST), rtc->sync_time, 484 rtc->sync_time * 2); 485 if (ret) 486 return ret; 487 488 /* Set desired modes leaving the controller disabled */ 489 writel(RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0); 490 491 if (scmp_val) { 492 writel(rate - 1, rtc->base + RZN1_RTC_SCMP); 493 rtc->rtcdev->ops = &rzn1_rtc_ops_scmp; 494 } else { 495 rtc->rtcdev->ops = &rzn1_rtc_ops_subu; 496 } 497 498 /* Enable controller finally */ 499 writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | scmp_val, rtc->base + RZN1_RTC_CTL0); 500 501 /* Disable all interrupts */ 502 writel(0, rtc->base + RZN1_RTC_CTL1); 503 504 spin_lock_init(&rtc->ctl1_access_lock); 505 506 ret = devm_request_irq(dev, irq, rzn1_rtc_alarm_irq, 0, "RZN1 RTC Alarm", rtc); 507 if (ret) 508 return dev_err_probe(dev, ret, "RTC alarm interrupt not available\n"); 509 510 irq = platform_get_irq_byname_optional(pdev, "pps"); 511 if (irq == -EPROBE_DEFER) 512 return irq; 513 if (irq >= 0) 514 ret = devm_request_irq(dev, irq, rzn1_rtc_1s_irq, 0, "RZN1 RTC 1s", rtc); 515 516 if (irq < 0 || ret) { 517 set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->rtcdev->features); 518 clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->rtcdev->features); 519 dev_warn(dev, "RTC pps interrupt not available. Alarm has only minute accuracy\n"); 520 } 521 522 return devm_rtc_register_device(rtc->rtcdev); 523 } 524 525 static const struct rzn1_rtc_data rzn1_rtc_rzt2h_data = { 526 .has_subu = false, 527 }; 528 529 static const struct rzn1_rtc_data rzn1_rtc_rzn1_data = { 530 .has_subu = true, 531 }; 532 533 static const struct of_device_id rzn1_rtc_of_match[] = { 534 { .compatible = "renesas,r9a09g077-rtc", .data = &rzn1_rtc_rzt2h_data }, 535 { .compatible = "renesas,rzn1-rtc", .data = &rzn1_rtc_rzn1_data }, 536 { /* sentinel */ } 537 }; 538 MODULE_DEVICE_TABLE(of, rzn1_rtc_of_match); 539 540 static struct platform_driver rzn1_rtc_driver = { 541 .probe = rzn1_rtc_probe, 542 .driver = { 543 .name = "rzn1-rtc", 544 .of_match_table = rzn1_rtc_of_match, 545 }, 546 }; 547 module_platform_driver(rzn1_rtc_driver); 548 549 MODULE_AUTHOR("Michel Pollet <buserror@gmail.com>"); 550 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>"); 551 MODULE_DESCRIPTION("RZ/N1 RTC driver"); 552 MODULE_LICENSE("GPL"); 553