1 /* 2 * A SPI driver for the Ricoh RS5C348 RTC 3 * 4 * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * The board specific init code should provide characteristics of this 11 * device: 12 * Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS 13 */ 14 15 #include <linux/bcd.h> 16 #include <linux/delay.h> 17 #include <linux/device.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/kernel.h> 21 #include <linux/string.h> 22 #include <linux/slab.h> 23 #include <linux/rtc.h> 24 #include <linux/workqueue.h> 25 #include <linux/spi/spi.h> 26 #include <linux/module.h> 27 28 #define RS5C348_REG_SECS 0 29 #define RS5C348_REG_MINS 1 30 #define RS5C348_REG_HOURS 2 31 #define RS5C348_REG_WDAY 3 32 #define RS5C348_REG_DAY 4 33 #define RS5C348_REG_MONTH 5 34 #define RS5C348_REG_YEAR 6 35 #define RS5C348_REG_CTL1 14 36 #define RS5C348_REG_CTL2 15 37 38 #define RS5C348_SECS_MASK 0x7f 39 #define RS5C348_MINS_MASK 0x7f 40 #define RS5C348_HOURS_MASK 0x3f 41 #define RS5C348_WDAY_MASK 0x03 42 #define RS5C348_DAY_MASK 0x3f 43 #define RS5C348_MONTH_MASK 0x1f 44 45 #define RS5C348_BIT_PM 0x20 /* REG_HOURS */ 46 #define RS5C348_BIT_Y2K 0x80 /* REG_MONTH */ 47 #define RS5C348_BIT_24H 0x20 /* REG_CTL1 */ 48 #define RS5C348_BIT_XSTP 0x10 /* REG_CTL2 */ 49 #define RS5C348_BIT_VDET 0x40 /* REG_CTL2 */ 50 51 #define RS5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */ 52 #define RS5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */ 53 #define RS5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */ 54 #define RS5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */ 55 56 struct rs5c348_plat_data { 57 struct rtc_device *rtc; 58 int rtc_24h; 59 }; 60 61 static int 62 rs5c348_rtc_set_time(struct device *dev, struct rtc_time *tm) 63 { 64 struct spi_device *spi = to_spi_device(dev); 65 struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev); 66 u8 txbuf[5+7], *txp; 67 int ret; 68 69 ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2)); 70 if (ret < 0) 71 return ret; 72 if (ret & RS5C348_BIT_XSTP) { 73 txbuf[0] = RS5C348_CMD_W(RS5C348_REG_CTL2); 74 txbuf[1] = 0; 75 ret = spi_write_then_read(spi, txbuf, 2, NULL, 0); 76 if (ret < 0) 77 return ret; 78 } 79 80 /* Transfer 5 bytes before writing SEC. This gives 31us for carry. */ 81 txp = txbuf; 82 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ 83 txbuf[1] = 0; /* dummy */ 84 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ 85 txbuf[3] = 0; /* dummy */ 86 txbuf[4] = RS5C348_CMD_MW(RS5C348_REG_SECS); /* cmd, sec, ... */ 87 txp = &txbuf[5]; 88 txp[RS5C348_REG_SECS] = bin2bcd(tm->tm_sec); 89 txp[RS5C348_REG_MINS] = bin2bcd(tm->tm_min); 90 if (pdata->rtc_24h) { 91 txp[RS5C348_REG_HOURS] = bin2bcd(tm->tm_hour); 92 } else { 93 /* hour 0 is AM12, noon is PM12 */ 94 txp[RS5C348_REG_HOURS] = bin2bcd((tm->tm_hour + 11) % 12 + 1) | 95 (tm->tm_hour >= 12 ? RS5C348_BIT_PM : 0); 96 } 97 txp[RS5C348_REG_WDAY] = bin2bcd(tm->tm_wday); 98 txp[RS5C348_REG_DAY] = bin2bcd(tm->tm_mday); 99 txp[RS5C348_REG_MONTH] = bin2bcd(tm->tm_mon + 1) | 100 (tm->tm_year >= 100 ? RS5C348_BIT_Y2K : 0); 101 txp[RS5C348_REG_YEAR] = bin2bcd(tm->tm_year % 100); 102 /* write in one transfer to avoid data inconsistency */ 103 ret = spi_write_then_read(spi, txbuf, sizeof(txbuf), NULL, 0); 104 udelay(62); /* Tcsr 62us */ 105 return ret; 106 } 107 108 static int 109 rs5c348_rtc_read_time(struct device *dev, struct rtc_time *tm) 110 { 111 struct spi_device *spi = to_spi_device(dev); 112 struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev); 113 u8 txbuf[5], rxbuf[7]; 114 int ret; 115 116 ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2)); 117 if (ret < 0) 118 return ret; 119 if (ret & RS5C348_BIT_VDET) 120 dev_warn(&spi->dev, "voltage-low detected.\n"); 121 if (ret & RS5C348_BIT_XSTP) { 122 dev_warn(&spi->dev, "oscillator-stop detected.\n"); 123 return -EINVAL; 124 } 125 126 /* Transfer 5 byte befores reading SEC. This gives 31us for carry. */ 127 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ 128 txbuf[1] = 0; /* dummy */ 129 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ 130 txbuf[3] = 0; /* dummy */ 131 txbuf[4] = RS5C348_CMD_MR(RS5C348_REG_SECS); /* cmd, sec, ... */ 132 133 /* read in one transfer to avoid data inconsistency */ 134 ret = spi_write_then_read(spi, txbuf, sizeof(txbuf), 135 rxbuf, sizeof(rxbuf)); 136 udelay(62); /* Tcsr 62us */ 137 if (ret < 0) 138 return ret; 139 140 tm->tm_sec = bcd2bin(rxbuf[RS5C348_REG_SECS] & RS5C348_SECS_MASK); 141 tm->tm_min = bcd2bin(rxbuf[RS5C348_REG_MINS] & RS5C348_MINS_MASK); 142 tm->tm_hour = bcd2bin(rxbuf[RS5C348_REG_HOURS] & RS5C348_HOURS_MASK); 143 if (!pdata->rtc_24h) { 144 if (rxbuf[RS5C348_REG_HOURS] & RS5C348_BIT_PM) { 145 tm->tm_hour -= 20; 146 tm->tm_hour %= 12; 147 tm->tm_hour += 12; 148 } else 149 tm->tm_hour %= 12; 150 } 151 tm->tm_wday = bcd2bin(rxbuf[RS5C348_REG_WDAY] & RS5C348_WDAY_MASK); 152 tm->tm_mday = bcd2bin(rxbuf[RS5C348_REG_DAY] & RS5C348_DAY_MASK); 153 tm->tm_mon = 154 bcd2bin(rxbuf[RS5C348_REG_MONTH] & RS5C348_MONTH_MASK) - 1; 155 /* year is 1900 + tm->tm_year */ 156 tm->tm_year = bcd2bin(rxbuf[RS5C348_REG_YEAR]) + 157 ((rxbuf[RS5C348_REG_MONTH] & RS5C348_BIT_Y2K) ? 100 : 0); 158 159 return 0; 160 } 161 162 static const struct rtc_class_ops rs5c348_rtc_ops = { 163 .read_time = rs5c348_rtc_read_time, 164 .set_time = rs5c348_rtc_set_time, 165 }; 166 167 static int rs5c348_probe(struct spi_device *spi) 168 { 169 int ret; 170 struct rtc_device *rtc; 171 struct rs5c348_plat_data *pdata; 172 173 pdata = devm_kzalloc(&spi->dev, sizeof(struct rs5c348_plat_data), 174 GFP_KERNEL); 175 if (!pdata) 176 return -ENOMEM; 177 spi->dev.platform_data = pdata; 178 179 /* Check D7 of SECOND register */ 180 ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_SECS)); 181 if (ret < 0 || (ret & 0x80)) { 182 dev_err(&spi->dev, "not found.\n"); 183 return ret; 184 } 185 186 dev_info(&spi->dev, "spiclk %u KHz.\n", 187 (spi->max_speed_hz + 500) / 1000); 188 189 ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL1)); 190 if (ret < 0) 191 return ret; 192 if (ret & RS5C348_BIT_24H) 193 pdata->rtc_24h = 1; 194 195 rtc = devm_rtc_allocate_device(&spi->dev); 196 if (IS_ERR(rtc)) 197 return PTR_ERR(rtc); 198 199 pdata->rtc = rtc; 200 201 rtc->ops = &rs5c348_rtc_ops; 202 203 return rtc_register_device(rtc); 204 } 205 206 static struct spi_driver rs5c348_driver = { 207 .driver = { 208 .name = "rtc-rs5c348", 209 }, 210 .probe = rs5c348_probe, 211 }; 212 213 module_spi_driver(rs5c348_driver); 214 215 MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>"); 216 MODULE_DESCRIPTION("Ricoh RS5C348 RTC driver"); 217 MODULE_LICENSE("GPL"); 218 MODULE_ALIAS("spi:rtc-rs5c348"); 219